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realtimeroboticsgroup.org / RealtimeRoboticsGroup / test / 870de4f40f13334ccfec9ec26fb4384e652cd32c^2..870de4f40f13334ccfec9ec26fb4384e652cd32c / .
commit870de4f40f13334ccfec9ec26fb4384e652cd32c[log] [tgz]
authorBrian Silverman <brians>Tue Dec 17 17:11:44 2013 -0800
committerBrian Silverman <brians>Tue Dec 17 17:11:44 2013 -0800
tree07d7cb2484506feb3e244493a4a6110e0f06b5c5
parent25a06d98eda3b1d85f9e915f39822dc634f016f7 [diff]
parent248053ad8ba31da1f4c64e51e7aa4b0896323d95 [diff]
merging in the infrastructure to build a custom flasher

diff --git a/bbb_cape/schematic/.gitignore b/bbb_cape/schematic/.gitignore
new file mode 100644
index 0000000..89e5079
--- /dev/null
+++ b/bbb_cape/schematic/.gitignore

@@ -0,0 +1,7 @@
+\#*.sch#
+*.sch~
+*.sym~
+*.pcb-
+*.net
+*.fp-
+*.pcb.bak*

diff --git a/bbb_cape/schematic/adc_buffer.sch b/bbb_cape/schematic/adc_buffer.sch
new file mode 100644
index 0000000..349015e
--- /dev/null
+++ b/bbb_cape/schematic/adc_buffer.sch

@@ -0,0 +1,306 @@
+v 20110115 2
+C 41600 49800 1 0 0 quad_opamp-1.sym
+{
+T 42200 50400 5 10 0 0 0 0 1
+device=QUAD_OPAMP
+T 41800 50700 5 10 1 1 0 0 1
+refdes=U2
+T 44000 52100 5 10 0 0 0 0 1
+footprint=SO14
+T 41800 52300 5 10 0 0 0 0 1
+symversion=0.1
+T 41600 49800 5 10 0 0 0 0 1
+slot=1
+T 41600 49800 5 10 0 0 0 0 1
+pn=MCP604-E/SL
+}
+C 41600 47600 1 0 0 quad_opamp-1.sym
+{
+T 42200 48200 5 10 0 0 0 0 1
+device=QUAD_OPAMP
+T 41800 48500 5 10 1 1 0 0 1
+refdes=U2
+T 44000 49900 5 10 0 0 0 0 1
+footprint=SO14
+T 41800 50100 5 10 0 0 0 0 1
+symversion=0.1
+T 41600 47600 5 10 0 0 0 0 1
+slot=2
+T 41600 47600 5 10 0 0 0 0 1
+pn=MCP604-E/SL
+}
+C 41600 45400 1 0 0 quad_opamp-1.sym
+{
+T 42200 46000 5 10 0 0 0 0 1
+device=QUAD_OPAMP
+T 41800 46300 5 10 1 1 0 0 1
+refdes=U2
+T 44000 47700 5 10 0 0 0 0 1
+footprint=SO14
+T 41800 47900 5 10 0 0 0 0 1
+symversion=0.1
+T 41600 45400 5 10 0 0 0 0 1
+slot=3
+T 41600 45400 5 10 0 0 0 0 1
+pn=MCP604-E/SL
+}
+C 41600 43200 1 0 0 quad_opamp-1.sym
+{
+T 42200 43800 5 10 0 0 0 0 1
+device=QUAD_OPAMP
+T 41800 44100 5 10 1 1 0 0 1
+refdes=U2
+T 44000 45500 5 10 0 0 0 0 1
+footprint=SO14
+T 41800 45700 5 10 0 0 0 0 1
+symversion=0.1
+T 41600 43200 5 10 0 0 0 0 1
+slot=4
+T 41600 43200 5 10 0 0 0 0 1
+pn=MCP604-E/SL
+}
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+N 41500 50400 41500 51000 4
+N 41500 51000 42800 51000 4
+N 42800 51000 42800 50200 4
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+N 41500 48200 41500 48800 4
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+N 41500 46000 41500 46600 4
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+N 42800 46600 42800 45800 4
+N 41500 43800 41600 43800 4
+N 41500 43800 41500 44400 4
+N 41500 44400 42800 44400 4
+N 42800 44400 42800 43600 4
+C 40600 49900 1 0 0 in-1.sym
+{
+T 40600 50200 5 10 0 0 0 0 1
+device=INPUT
+T 40600 50200 5 10 1 1 0 0 1
+refdes=IN1
+}
+C 40600 43300 1 0 0 in-1.sym
+{
+T 40600 43600 5 10 0 0 0 0 1
+device=INPUT
+T 40600 43600 5 10 1 1 0 0 1
+refdes=IN4
+}
+C 40600 45500 1 0 0 in-1.sym
+{
+T 40600 45800 5 10 0 0 0 0 1
+device=INPUT
+T 40600 45800 5 10 1 1 0 0 1
+refdes=IN3
+}
+C 40600 47700 1 0 0 in-1.sym
+{
+T 40600 48000 5 10 0 0 0 0 1
+device=INPUT
+T 40600 48000 5 10 1 1 0 0 1
+refdes=IN2
+}
+C 42000 51800 1 270 0 in-1.sym
+{
+T 42300 51800 5 10 0 0 270 0 1
+device=INPUT
+T 42200 51700 5 10 1 1 270 0 1
+refdes=VCC
+}
+C 42200 41600 1 90 0 in-1.sym
+{
+T 41900 41600 5 10 0 0 90 0 1
+device=INPUT
+T 42000 41700 5 10 1 1 90 0 1
+refdes=GND
+}
+C 44200 50100 1 0 0 out-1.sym
+{
+T 44200 50400 5 10 0 0 0 0 1
+device=OUTPUT
+T 44200 50300 5 10 1 1 0 0 1
+refdes=OUT1
+}
+C 44200 47900 1 0 0 out-1.sym
+{
+T 44200 48200 5 10 0 0 0 0 1
+device=OUTPUT
+T 44200 48100 5 10 1 1 0 0 1
+refdes=OUT2
+}
+C 44200 45700 1 0 0 out-1.sym
+{
+T 44200 46000 5 10 0 0 0 0 1
+device=OUTPUT
+T 44200 45900 5 10 1 1 0 0 1
+refdes=OUT3
+}
+C 44200 43500 1 0 0 out-1.sym
+{
+T 44200 43800 5 10 0 0 0 0 1
+device=OUTPUT
+T 44200 43700 5 10 1 1 0 0 1
+refdes=OUT4
+}
+N 41600 50000 41200 50000 4
+N 41600 47800 41200 47800 4
+N 41600 45600 41200 45600 4
+N 41600 43400 41200 43400 4
+N 42100 42200 42100 43200 4
+N 42100 51200 42100 50600 4
+C 47400 49700 1 90 0 capacitor-1.sym
+{
+T 46700 49900 5 10 0 0 90 0 1
+device=CAPACITOR
+T 47000 50000 5 10 1 1 90 0 1
+refdes=C5
+T 46500 49900 5 10 0 0 90 0 1
+symversion=0.1
+T 47400 50300 5 10 1 1 270 0 1
+value=0.1 uF
+T 47400 49700 5 10 0 0 270 0 1
+footprint=0603
+T 47400 49700 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+N 42100 51100 47200 51100 4
+N 47200 51100 47200 50600 4
+N 47200 49700 47200 42400 4
+N 47200 42400 42100 42400 4
+C 44300 49200 1 90 0 capacitor-1.sym
+{
+T 43600 49400 5 10 0 0 90 0 1
+device=CAPACITOR
+T 43900 49500 5 10 1 1 90 0 1
+refdes=C1
+T 43400 49400 5 10 0 0 90 0 1
+symversion=0.1
+T 44300 49800 5 10 1 1 270 0 1
+value=0.1 uF
+T 44300 49200 5 10 0 0 270 0 1
+footprint=0603
+T 44300 49200 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+C 43100 50100 1 0 0 resistor-1.sym
+{
+T 43400 50500 5 10 0 0 0 0 1
+device=RESISTOR
+T 43300 50400 5 10 1 1 0 0 1
+refdes=R1
+T 43100 50100 5 10 0 0 0 0 1
+footprint=0603
+T 43100 49900 5 10 1 1 0 0 1
+value=5 kohms
+T 43100 50100 5 10 0 1 0 0 1
+pn=CRCW06034K99FKEAHP
+}
+N 42600 50200 43100 50200 4
+N 44000 50200 44200 50200 4
+N 44100 50200 44100 50100 4
+N 42100 49800 42100 49000 4
+N 42100 49000 47200 49000 4
+N 44100 49000 44100 49200 4
+C 43100 47900 1 0 0 resistor-1.sym
+{
+T 43400 48300 5 10 0 0 0 0 1
+device=RESISTOR
+T 43300 48200 5 10 1 1 0 0 1
+refdes=R2
+T 43100 47900 5 10 0 0 0 0 1
+footprint=0603
+T 43100 47700 5 10 1 1 0 0 1
+value=5 kohms
+T 43100 47900 5 10 0 1 0 0 1
+pn=CRCW06034K99FKEAHP
+}
+N 44100 48000 44100 47900 4
+N 44100 46800 44100 47000 4
+C 44300 47000 1 90 0 capacitor-1.sym
+{
+T 43900 47300 5 10 1 1 90 0 1
+refdes=C2
+T 43600 47200 5 10 0 0 90 0 1
+device=CAPACITOR
+T 43400 47200 5 10 0 0 90 0 1
+symversion=0.1
+T 44300 47600 5 10 1 1 270 0 1
+value=0.1 uF
+T 44300 47000 5 10 0 0 270 0 1
+footprint=0603
+T 44300 47000 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+N 42600 48000 43100 48000 4
+N 44000 48000 44200 48000 4
+N 42100 46800 47200 46800 4
+N 42100 46800 42100 47600 4
+C 43100 45700 1 0 0 resistor-1.sym
+{
+T 43400 46100 5 10 0 0 0 0 1
+device=RESISTOR
+T 43300 46000 5 10 1 1 0 0 1
+refdes=R3
+T 43100 45700 5 10 0 0 0 0 1
+footprint=0603
+T 43100 45500 5 10 1 1 0 0 1
+value=5 kohms
+T 43100 45700 5 10 0 1 0 0 1
+pn=CRCW06034K99FKEAHP
+}
+N 44100 45800 44100 45700 4
+N 44100 44600 44100 44800 4
+C 44300 44800 1 90 0 capacitor-1.sym
+{
+T 43900 45100 5 10 1 1 90 0 1
+refdes=C3
+T 43600 45000 5 10 0 0 90 0 1
+device=CAPACITOR
+T 43400 45000 5 10 0 0 90 0 1
+symversion=0.1
+T 44300 45400 5 10 1 1 270 0 1
+value=0.1 uF
+T 44300 44800 5 10 0 0 270 0 1
+footprint=0603
+T 44300 44800 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+N 42600 45800 43100 45800 4
+N 44000 45800 44200 45800 4
+N 42100 44600 47200 44600 4
+N 42100 44600 42100 45400 4
+C 43100 43500 1 0 0 resistor-1.sym
+{
+T 43400 43900 5 10 0 0 0 0 1
+device=RESISTOR
+T 43300 43800 5 10 1 1 0 0 1
+refdes=R4
+T 43100 43500 5 10 0 0 0 0 1
+footprint=0603
+T 43100 43300 5 10 1 1 0 0 1
+value=5 kohms
+T 43100 43500 5 10 0 1 0 0 1
+pn=CRCW06034K99FKEAHP
+}
+N 44100 43600 44100 43500 4
+N 44100 42400 44100 42600 4
+C 44300 42600 1 90 0 capacitor-1.sym
+{
+T 43900 42900 5 10 1 1 90 0 1
+refdes=C4
+T 43600 42800 5 10 0 0 90 0 1
+device=CAPACITOR
+T 43400 42800 5 10 0 0 90 0 1
+symversion=0.1
+T 44300 43200 5 10 1 1 270 0 1
+value=0.1 uF
+T 44300 42600 5 10 0 0 270 0 1
+footprint=0603
+T 44300 42600 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+N 42600 43600 43100 43600 4
+N 44000 43600 44200 43600 4

diff --git a/bbb_cape/schematic/cape-main.sch b/bbb_cape/schematic/cape-main.sch
new file mode 100644
index 0000000..8bf601e
--- /dev/null
+++ b/bbb_cape/schematic/cape-main.sch

@@ -0,0 +1,1544 @@
+v 20110115 2
+C 41800 40100 1 0 0 STM32F2-1.sym
+{
+T 54900 51800 5 10 0 1 0 0 1
+device=STM32F2
+T 52200 53000 5 10 0 1 0 0 1
+footprint=LQFP64_10
+T 43500 52200 5 10 1 1 0 0 1
+refdes=U6
+T 41800 40100 5 10 0 1 0 0 1
+pn=STM32F205RGT6
+}
+C 50500 53100 1 180 0 digital-input-x4-1.sym
+{
+T 49200 51600 5 10 0 1 180 0 1
+device=digital-input-x4
+T 50100 51500 5 10 1 1 180 0 1
+source=encoder inputs x2.sch
+T 48500 51200 5 10 1 1 180 0 1
+refdes=X2
+}
+C 50500 45000 1 180 0 digital-input-x4-1.sym
+{
+T 49200 43500 5 10 0 1 180 0 1
+device=digital-input-x4
+T 50100 43400 5 10 1 1 180 0 1
+source=encoder inputs x2.sch
+T 48500 43100 5 10 1 1 180 0 1
+refdes=X4
+}
+N 45300 52600 47900 52600 4
+N 45300 52200 47900 52200 4
+N 47900 52200 47900 52300 4
+N 45300 51800 46800 51800 4
+N 46800 51800 46800 52000 4
+N 46800 52000 47900 52000 4
+N 45300 51400 47000 51400 4
+N 47000 51400 47000 51700 4
+N 47000 51700 47900 51700 4
+C 50500 47600 1 180 0 digital-input-x4-1.sym
+{
+T 49200 46100 5 10 0 1 180 0 1
+device=digital-input-x4
+T 50100 46000 5 10 1 1 180 0 1
+source=encoder inputs x2.sch
+T 48500 45700 5 10 1 1 180 0 1
+refdes=X3
+}
+N 45300 43400 47000 43400 4
+N 47000 43400 47000 43600 4
+N 47000 43600 47900 43600 4
+N 47900 43900 46800 43900 4
+N 46800 43900 46800 43800 4
+N 46800 43800 45300 43800 4
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+N 47900 46200 47000 46200 4
+N 47000 46200 47000 45000 4
+N 47000 45000 45300 45000 4
+C 37000 51200 1 0 0 digital-input-x4-1.sym
+{
+T 38300 52700 5 10 0 1 0 0 1
+device=digital-input-x4
+T 37400 52800 5 10 1 1 0 0 1
+source=encoder inputs x2.sch
+T 39000 53100 5 10 1 1 0 0 1
+refdes=X1
+}
+N 39600 52600 41800 52600 4
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+N 40500 52200 40500 52300 4
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+N 40700 52000 39600 52000 4
+N 39600 51700 40500 51700 4
+N 40500 51700 40500 49800 4
+N 40500 49800 41800 49800 4
+C 16100 54800 1 0 0 regulator-1.sym
+{
+T 15000 55500 5 10 0 1 0 0 1
+device=regulator
+T 16900 56100 5 10 1 1 0 0 1
+refdes=X14
+T 16100 55900 5 10 1 1 0 0 1
+source=simple switcher 5V.sch
+}
+C 33400 54500 1 0 0 regulator-1.sym
+{
+T 32300 55200 5 10 0 1 0 0 1
+device=regulator
+T 34200 55800 5 10 1 1 0 0 1
+refdes=X16
+T 33400 55600 5 10 1 1 0 0 1
+source=simple switcher 5V.sch
+}
+C 18300 35800 1 0 0 beaglebone-1.sym
+{
+T 26700 54800 5 10 1 1 0 6 1
+refdes=U8
+T 22500 45650 5 10 0 0 0 0 1
+device=BEAGLEBOND BLACK CAPE
+T 22500 45850 5 10 0 0 0 0 1
+footprint=beaglebone
+T 22000 54100 5 10 0 1 0 0 1
+pn=PRPC023DAAN-RC x2; SSQ-105-03-G-S
+}
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+N 33900 52600 37000 52600 4
+N 34900 48100 34900 54700 4
+N 34900 52300 37000 52300 4
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+C 36500 52100 1 270 0 gnd-1.sym
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+N 50500 52000 52000 52000 4
+N 52000 41600 52000 54000 4
+{
+T 51500 41600 5 10 1 1 0 0 1
+netname=SVCC
+}
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+N 52200 41300 52200 54200 4
+{
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+netname=SGND
+}
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+N 52000 43400 58800 43400 4
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+N 50500 44700 50500 44500 4
+N 50700 44200 50500 44200 4
+N 49200 45000 51800 45000 4
+N 51800 42800 51800 53800 4
+{
+T 51300 42800 5 10 1 1 0 0 1
+netname=DIFFA
+}
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+N 34400 51200 38300 51200 4
+N 49200 47600 49200 47700 4
+N 49200 47700 51800 47700 4
+N 49200 53100 49200 53800 4
+C 34500 51400 1 90 0 resistor-1.sym
+{
+T 34100 51700 5 10 0 0 90 0 1
+device=RESISTOR
+T 34200 51600 5 10 1 1 90 0 1
+refdes=R10
+T 34500 51400 5 10 0 0 90 0 1
+footprint=0603
+T 34700 51400 5 10 1 1 90 0 1
+value=500 ohms
+T 34500 51400 5 10 0 1 0 0 1
+pn=ERJ-3EKF4990V
+}
+C 35500 51400 1 90 0 resistor-1.sym
+{
+T 35100 51700 5 10 0 0 90 0 1
+device=RESISTOR
+T 35200 51600 5 10 1 1 90 0 1
+refdes=R12
+T 35500 51400 5 10 0 0 90 0 1
+footprint=0603
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+value=500 ohms
+T 35500 51400 5 10 0 1 0 0 1
+pn=ERJ-3EKF4990V
+}
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+N 35400 51400 35400 51200 4
+C 50500 50800 1 180 0 digital-input-x4-1.sym
+{
+T 49200 49300 5 10 0 1 180 0 1
+device=digital-input-x4
+T 50100 49200 5 10 1 1 180 0 1
+source=digital inputs x4.sch
+T 48500 48900 5 10 1 1 180 0 1
+refdes=X5
+}
+N 45300 49800 47000 49800 4
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+C 50500 42700 1 180 0 digital-input-x4-1.sym
+{
+T 49200 41200 5 10 0 1 180 0 1
+device=digital-input-x4
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+source=digital inputs x4.sch
+T 48500 40800 5 10 1 1 180 0 1
+refdes=X7
+}
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+N 47200 39100 47200 41300 4
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+C 37000 47000 1 0 0 digital-input-x4-1.sym
+{
+T 38300 48500 5 10 0 1 0 0 1
+device=digital-input-x4
+T 37400 48600 5 10 1 1 0 0 1
+source=digital inputs x4.sch
+T 39000 48900 5 10 1 1 0 0 1
+refdes=X6
+}
+N 41800 51000 40900 51000 4
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+N 27300 53900 27300 54600 4
+N 27300 54300 27000 54300 4
+N 27300 53900 27000 53900 4
+N 13100 50700 18400 50700 4
+C 37700 45900 1 0 0 capacitor-1.sym
+{
+T 37900 46600 5 10 0 0 0 0 1
+device=CAPACITOR
+T 37900 46400 5 10 1 1 0 0 1
+refdes=C4
+T 37900 46800 5 10 0 0 0 0 1
+symversion=0.1
+T 37700 45900 5 10 0 0 0 0 1
+footprint=0603
+T 37900 45700 5 10 1 1 0 0 1
+value=18 pF
+T 37700 45900 5 10 0 1 0 0 1
+pn=VJ0603A180JXACW1BC
+}
+C 37700 44700 1 0 0 capacitor-1.sym
+{
+T 37900 45400 5 10 0 0 0 0 1
+device=CAPACITOR
+T 37900 45200 5 10 1 1 0 0 1
+refdes=C5
+T 37900 45600 5 10 0 0 0 0 1
+symversion=0.1
+T 37700 44700 5 10 0 0 0 0 1
+footprint=0603
+T 37900 44500 5 10 1 1 0 0 1
+value=18 pF
+T 37700 44700 5 10 0 1 0 0 1
+pn=VJ0603A180JXACW1BC
+}
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+N 59300 41700 57200 41700 4
+N 57200 39000 57200 41700 4
+N 57200 39000 54700 39000 4
+N 59300 40200 57500 40200 4
+N 57500 40200 57500 38700 4
+N 57500 38700 54700 38700 4
+N 59300 38700 57800 38700 4
+N 57800 38700 57800 38400 4
+N 57800 38400 54700 38400 4
+N 54700 37200 59300 37200 4
+N 59300 35700 57600 35700 4
+N 57600 35700 57600 36900 4
+N 57600 36900 54700 36900 4
+N 59300 34200 57300 34200 4
+N 57300 34200 57300 36600 4
+N 57300 36600 54700 36600 4
+N 59300 32700 57000 32700 4
+N 57000 32700 57000 36300 4
+N 57000 36300 54700 36300 4
+C 18000 54800 1 0 0 5V-plus-1.sym
+N 18200 54800 18200 54600 4
+N 18200 54600 17600 54600 4
+C 35800 57500 1 0 0 5V-plus-1.sym
+C 49100 57500 1 0 0 5V-plus-1.sym
+C 51800 38000 1 0 0 5V-plus-1.sym
+N 52000 35700 52000 38000 4
+C 51400 34700 1 0 0 gnd-1.sym
+N 51500 35500 51500 35000 4
+C 58300 41900 1 90 0 capacitor-1.sym
+{
+T 57600 42100 5 10 0 0 90 0 1
+device=CAPACITOR
+T 57900 42200 5 10 1 1 90 0 1
+refdes=C18
+T 57400 42100 5 10 0 0 90 0 1
+symversion=0.1
+T 58300 42500 5 10 1 1 270 0 1
+value=0.1 uF
+T 58300 41900 5 10 0 0 270 0 1
+footprint=0603
+T 58300 41900 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+C 58300 40400 1 90 0 capacitor-1.sym
+{
+T 57600 40600 5 10 0 0 90 0 1
+device=CAPACITOR
+T 57900 40700 5 10 1 1 90 0 1
+refdes=C19
+T 57400 40600 5 10 0 0 90 0 1
+symversion=0.1
+T 58300 41000 5 10 1 1 270 0 1
+value=0.1 uF
+T 58300 40400 5 10 0 0 270 0 1
+footprint=0603
+T 58300 40400 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+C 58300 38900 1 90 0 capacitor-1.sym
+{
+T 57600 39100 5 10 0 0 90 0 1
+device=CAPACITOR
+T 57900 39200 5 10 1 1 90 0 1
+refdes=C20
+T 57400 39100 5 10 0 0 90 0 1
+symversion=0.1
+T 58300 39500 5 10 1 1 270 0 1
+value=0.1 uF
+T 58300 38900 5 10 0 0 270 0 1
+footprint=0603
+T 58300 38900 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+C 58300 37400 1 90 0 capacitor-1.sym
+{
+T 57600 37600 5 10 0 0 90 0 1
+device=CAPACITOR
+T 57900 37700 5 10 1 1 90 0 1
+refdes=C21
+T 57400 37600 5 10 0 0 90 0 1
+symversion=0.1
+T 58300 38000 5 10 1 1 270 0 1
+value=0.1 uF
+T 58300 37400 5 10 0 0 270 0 1
+footprint=0603
+T 58300 37400 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+C 58300 35900 1 90 0 capacitor-1.sym
+{
+T 57600 36100 5 10 0 0 90 0 1
+device=CAPACITOR
+T 57900 36200 5 10 1 1 90 0 1
+refdes=C22
+T 57400 36100 5 10 0 0 90 0 1
+symversion=0.1
+T 58300 36500 5 10 1 1 270 0 1
+value=0.1 uF
+T 58300 35900 5 10 0 0 270 0 1
+footprint=0603
+T 58300 35900 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+C 58300 34400 1 90 0 capacitor-1.sym
+{
+T 57600 34600 5 10 0 0 90 0 1
+device=CAPACITOR
+T 57900 34700 5 10 1 1 90 0 1
+refdes=C23
+T 57400 34600 5 10 0 0 90 0 1
+symversion=0.1
+T 58300 35000 5 10 1 1 270 0 1
+value=0.1 uF
+T 58300 34400 5 10 0 0 270 0 1
+footprint=0603
+T 58300 34400 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+C 58300 32900 1 90 0 capacitor-1.sym
+{
+T 57600 33100 5 10 0 0 90 0 1
+device=CAPACITOR
+T 57900 33200 5 10 1 1 90 0 1
+refdes=C24
+T 57400 33100 5 10 0 0 90 0 1
+symversion=0.1
+T 58300 33500 5 10 1 1 270 0 1
+value=0.1 uF
+T 58300 32900 5 10 0 0 270 0 1
+footprint=0603
+T 58300 32900 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+N 58100 42800 58100 43000 4
+N 58100 41900 58100 41800 4
+N 58100 41800 59000 41800 4
+N 58100 41300 58100 41500 4
+N 59000 40300 58100 40300 4
+N 58100 40300 58100 40400 4
+N 58100 39800 58100 40000 4
+N 58100 38900 58100 38800 4
+N 58100 38800 59000 38800 4
+N 58100 38300 58100 38500 4
+N 59000 37300 58100 37300 4
+N 58100 37300 58100 37400 4
+N 58100 36800 58100 37000 4
+N 59000 35800 58100 35800 4
+N 58100 35800 58100 35900 4
+N 58100 35300 58100 35500 4
+N 58100 34400 58100 34300 4
+N 58100 34300 59000 34300 4
+N 58100 33800 58100 34000 4
+N 58100 32900 58100 32800 4
+N 58100 32800 59000 32800 4
+C 58300 31400 1 90 0 capacitor-1.sym
+{
+T 57600 31600 5 10 0 0 90 0 1
+device=CAPACITOR
+T 57900 31700 5 10 1 1 90 0 1
+refdes=C25
+T 57400 31600 5 10 0 0 90 0 1
+symversion=0.1
+T 58300 32000 5 10 1 1 270 0 1
+value=0.1 uF
+T 58300 31400 5 10 0 0 270 0 1
+footprint=0603
+T 58300 31400 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+N 58100 32300 58100 32500 4
+N 58100 31400 58100 31300 4
+N 58100 31300 59000 31300 4
+C 40100 40500 1 90 0 capacitor-1.sym
+{
+T 39400 40700 5 10 0 0 90 0 1
+device=CAPACITOR
+T 39700 40800 5 10 1 1 90 0 1
+refdes=C26
+T 39200 40700 5 10 0 0 90 0 1
+symversion=0.1
+T 40100 41100 5 10 1 1 270 0 1
+value=0.1 uF
+T 40100 40500 5 10 0 0 270 0 1
+footprint=0603
+T 40100 40500 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+C 39300 40500 1 90 0 capacitor-1.sym
+{
+T 38600 40700 5 10 0 0 90 0 1
+device=CAPACITOR
+T 38900 40800 5 10 1 1 90 0 1
+refdes=C27
+T 38400 40700 5 10 0 0 90 0 1
+symversion=0.1
+T 39300 41100 5 10 1 1 270 0 1
+value=0.1 uF
+T 39300 40500 5 10 0 0 270 0 1
+footprint=0603
+T 39300 40500 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+C 38400 40500 1 90 0 capacitor-1.sym
+{
+T 37700 40700 5 10 0 0 90 0 1
+device=CAPACITOR
+T 38000 40800 5 10 1 1 90 0 1
+refdes=C28
+T 37500 40700 5 10 0 0 90 0 1
+symversion=0.1
+T 38400 41100 5 10 1 1 270 0 1
+value=0.1 uF
+T 38400 40500 5 10 0 0 270 0 1
+footprint=0603
+T 38400 40500 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+C 37600 40500 1 90 0 capacitor-1.sym
+{
+T 36900 40700 5 10 0 0 90 0 1
+device=CAPACITOR
+T 37200 40800 5 10 1 1 90 0 1
+refdes=C29
+T 36700 40700 5 10 0 0 90 0 1
+symversion=0.1
+T 37600 41100 5 10 1 1 270 0 1
+value=0.1 uF
+T 37600 40500 5 10 0 0 270 0 1
+footprint=0603
+T 37600 40500 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+C 36800 40500 1 90 0 capacitor-1.sym
+{
+T 36100 40700 5 10 0 0 90 0 1
+device=CAPACITOR
+T 36400 40800 5 10 1 1 90 0 1
+refdes=C30
+T 35900 40700 5 10 0 0 90 0 1
+symversion=0.1
+T 36800 41100 5 10 1 1 270 0 1
+value=0.1 uF
+T 36800 40500 5 10 0 0 270 0 1
+footprint=0603
+T 36800 40500 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+C 38100 40000 1 0 0 gnd-1.sym
+C 38000 41600 1 0 0 3.3V-plus-1.sym
+N 36600 40500 36600 40400 4
+N 35800 40400 39900 40400 4
+N 39900 40400 39900 40500 4
+N 39100 40500 39100 40400 4
+N 38200 40500 38200 40400 4
+N 38200 40400 38200 40300 4
+N 37400 40500 37400 40400 4
+N 36600 41400 36600 41500 4
+N 35800 41500 39900 41500 4
+N 39900 41500 39900 41400 4
+N 39100 41400 39100 41500 4
+N 38200 41500 38200 41600 4
+N 38200 41500 38200 41400 4
+N 37400 41400 37400 41500 4
+C 39000 55100 1 90 0 capacitor-1.sym
+{
+T 38300 55300 5 10 0 0 90 0 1
+device=CAPACITOR
+T 38600 55400 5 10 1 1 90 0 1
+refdes=C32
+T 38100 55300 5 10 0 0 90 0 1
+symversion=0.1
+T 39000 55700 5 10 1 1 270 0 1
+value=0.1 uF
+T 39000 55100 5 10 0 0 270 0 1
+footprint=0603
+T 39000 55100 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+N 38000 56100 38800 56100 4
+N 38800 56100 38800 56000 4
+N 38800 55100 38800 55000 4
+N 38800 55000 38000 55000 4
+C 36000 40500 1 90 0 capacitor-1.sym
+{
+T 35300 40700 5 10 0 0 90 0 1
+device=CAPACITOR
+T 35600 40800 5 10 1 1 90 0 1
+refdes=C31
+T 35100 40700 5 10 0 0 90 0 1
+symversion=0.1
+T 36000 41100 5 10 1 1 270 0 1
+value=0.1 uF
+T 36000 40500 5 10 0 0 270 0 1
+footprint=0603
+T 36000 40500 5 10 0 1 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+N 35800 41500 35800 41400 4
+N 35800 40500 35800 40400 4
+C 55100 46000 1 0 0 led-3.sym
+{
+T 56050 46650 5 10 0 0 0 0 1
+device=LED
+T 55550 46550 5 10 1 1 0 0 1
+refdes=D2
+T 55100 46000 5 10 0 0 0 0 1
+footprint=0805
+T 55300 45900 5 10 1 1 0 0 1
+value=yellow
+T 55100 46000 5 10 0 1 0 0 1
+pn=LY R971-HL-1
+}
+C 55100 45100 1 0 0 led-3.sym
+{
+T 56050 45750 5 10 0 0 0 0 1
+device=LED
+T 55550 45650 5 10 1 1 0 0 1
+refdes=D5
+T 55100 45100 5 10 0 0 0 0 1
+footprint=0805
+T 55300 45000 5 10 1 1 0 0 1
+value=green
+T 55100 45100 5 10 0 1 0 0 1
+pn=LG R971-KN-1
+}
+C 55100 44300 1 0 0 led-3.sym
+{
+T 56050 44950 5 10 0 0 0 0 1
+device=LED
+T 55550 44850 5 10 1 1 0 0 1
+refdes=D6
+T 55100 44300 5 10 0 0 0 0 1
+footprint=0805
+T 55300 44200 5 10 1 1 0 0 1
+value=red
+T 55100 44300 5 10 0 1 0 0 1
+pn=LH R974-LP-1
+}
+C 57100 46300 1 180 0 resistor-1.sym
+{
+T 56800 45900 5 10 0 0 180 0 1
+device=RESISTOR
+T 56900 46000 5 10 1 1 180 0 1
+refdes=R13
+T 57100 46300 5 10 0 0 180 0 1
+footprint=0603
+T 57100 46500 5 10 1 1 180 0 1
+value=130 ohms
+T 57100 46300 5 10 0 1 0 0 1
+pn=ERJ-3GEYJ131V
+}
+C 57100 45400 1 180 0 resistor-1.sym
+{
+T 56800 45000 5 10 0 0 180 0 1
+device=RESISTOR
+T 56900 45100 5 10 1 1 180 0 1
+refdes=R14
+T 57100 45400 5 10 0 0 180 0 1
+footprint=0603
+T 57100 45600 5 10 1 1 180 0 1
+value=130 ohms
+T 57100 45400 5 10 0 1 0 0 1
+pn=ERJ-3GEYJ131V
+}
+C 57100 44600 1 180 0 resistor-1.sym
+{
+T 56800 44200 5 10 0 0 180 0 1
+device=RESISTOR
+T 56900 44300 5 10 1 1 180 0 1
+refdes=R15
+T 57100 44600 5 10 0 0 180 0 1
+footprint=0603
+T 57100 44800 5 10 1 1 180 0 1
+value=130 ohms
+T 57100 44600 5 10 0 1 0 0 1
+pn=ERJ-3GEYJ131V
+}
+N 56000 46200 56200 46200 4
+N 56200 45300 56000 45300 4
+N 56200 44500 56000 44500 4
+C 57200 46500 1 0 0 3.3V-plus-1.sym
+N 57400 43800 57400 46500 4
+N 57400 46200 57100 46200 4
+N 57400 45300 57100 45300 4
+N 57400 44500 57100 44500 4
+N 45300 45800 47900 45800 4
+N 47900 45800 47900 45400 4
+N 47900 45400 53900 45400 4
+N 47900 46500 46400 46500 4
+N 46400 46500 46400 50600 4
+N 46400 50600 45300 50600 4
+N 47900 44500 46600 44500 4
+N 46600 44500 46600 50200 4
+N 46600 50200 45300 50200 4
+N 45300 45400 45800 45400 4
+N 45800 45400 45800 50400 4
+N 45800 50400 46800 50400 4
+N 46800 50400 46800 50300 4
+N 46800 50300 47900 50300 4
+N 50500 43900 52000 43900 4
+N 55100 46200 53900 46200 4
+N 53900 46200 53900 45400 4
+N 45300 44600 46400 44600 4
+N 46400 44600 46400 44800 4
+N 46400 44800 47200 44800 4
+N 47200 44800 47200 45200 4
+N 47200 45200 54100 45200 4
+N 54100 45200 54100 45300 4
+N 54100 45300 55100 45300 4
+N 55100 44500 54100 44500 4
+N 54100 44500 54100 40500 4
+N 54100 40500 47400 40500 4
+N 47400 40500 47400 41100 4
+N 47400 41100 46800 41100 4
+N 46800 41100 46800 41200 4
+N 46800 41200 45800 41200 4
+N 45800 41200 45800 41800 4
+N 45800 41800 45300 41800 4
+C 53600 47500 1 270 0 gnd-1.sym
+N 54300 47700 53200 47700 4
+N 53200 47700 53200 47900 4
+N 53200 47900 47800 47900 4
+N 47800 47400 47800 47900 4
+N 47800 47400 45300 47400 4
+N 54300 48000 53400 48000 4
+N 53400 48000 53400 48100 4
+N 53400 48100 47600 48100 4
+N 45300 47000 46800 47000 4
+N 46800 47000 46800 47600 4
+N 46800 47600 47600 47600 4
+N 47600 47600 47600 48100 4
+C 54000 48300 1 90 0 generic-power.sym
+{
+T 53750 48500 5 10 1 1 90 3 1
+net=NRST:1
+}
+C 37100 43700 1 180 0 generic-power.sym
+{
+T 36900 43450 5 10 1 1 180 3 1
+net=NRST:1
+}
+N 36900 43700 36900 44100 4
+C 56000 48500 1 180 0 connector4-1.sym
+{
+T 54200 47600 5 10 0 0 180 0 1
+device=CONNECTOR_4
+T 56000 47100 5 10 1 1 180 0 1
+refdes=CONN1
+T 56000 48500 5 10 0 0 0 0 1
+footprint=22-23-2041
+T 56000 48500 5 10 0 1 0 0 1
+pn=22-23-2041
+}
+N 53900 47400 54300 47400 4
+N 54000 48500 54000 48300 4
+N 54000 48300 54300 48300 4
+N 41800 49400 28900 49400 4
+N 28900 49400 28900 57000 4
+N 28900 57000 13100 57000 4
+N 13100 57000 13100 50700 4
+N 58100 32500 58800 32500 4
+N 58100 43000 58800 43000 4
+N 58100 41500 58800 41500 4
+N 58100 40000 58800 40000 4
+N 58100 38500 58800 38500 4
+N 58100 37000 58800 37000 4
+N 58100 35500 58800 35500 4
+N 58100 34000 58800 34000 4
+C 14300 48100 1 90 0 led-3.sym
+{
+T 13650 49050 5 10 0 0 90 0 1
+device=LED
+T 13750 48550 5 10 1 1 90 0 1
+refdes=D7
+T 14300 48100 5 10 0 0 90 0 1
+footprint=0805
+T 14400 48300 5 10 1 1 90 0 1
+value=green
+T 14300 48100 5 10 0 1 0 0 1
+pn=LG R971-KN-1
+}
+C 14000 50000 1 270 0 resistor-1.sym
+{
+T 14400 49700 5 10 0 0 270 0 1
+device=RESISTOR
+T 14300 49800 5 10 1 1 270 0 1
+refdes=R17
+T 14000 50000 5 10 0 0 270 0 1
+footprint=0603
+T 13800 50000 5 10 1 1 270 0 1
+value=1 kohms
+T 14000 50000 5 10 0 1 0 0 1
+pn=SG73S1JTTD102J
+}
+C 14000 47700 1 0 0 gnd-1.sym
+C 13900 50100 1 0 0 12V-plus-1.sym
+N 14100 50100 14100 50000 4
+N 14100 49000 14100 49100 4
+N 14100 48000 14100 48100 4
+C 14500 40900 1 0 0 4-40_bolt-1.sym
+{
+T 14200 42100 5 10 0 1 0 0 1
+device=4-40_bolt
+T 14500 42100 5 10 0 1 0 0 1
+footprint=4-40_bolt
+T 15000 41600 5 10 1 1 0 0 1
+refdes=B2
+}
+C 55100 43600 1 0 0 led-3.sym
+{
+T 56050 44250 5 10 0 0 0 0 1
+device=LED
+T 55550 44050 5 10 1 1 0 0 1
+refdes=D1
+T 55100 43600 5 10 0 0 0 0 1
+footprint=0805
+T 55300 43500 5 10 1 1 0 0 1
+value=green
+T 55100 43600 5 10 0 1 0 0 1
+pn=LG R971-KN-1
+}
+C 57100 43900 1 180 0 resistor-1.sym
+{
+T 56800 43500 5 10 0 0 180 0 1
+device=RESISTOR
+T 56900 43600 5 10 1 1 180 0 1
+refdes=R1
+T 57100 43900 5 10 0 0 180 0 1
+footprint=0603
+T 57100 44100 5 10 1 1 180 0 1
+value=130 ohms
+T 57100 43900 5 10 0 1 0 0 1
+pn=ERJ-3GEYJ131V
+}
+N 56200 43800 56000 43800 4
+N 57400 43800 57100 43800 4
+N 41800 51400 41100 51400 4
+N 41100 51400 41100 53400 4
+N 41100 53400 52800 53400 4
+N 52800 53400 52800 43800 4
+N 52800 43800 55100 43800 4

diff --git a/bbb_cape/schematic/cape.gsch2pcb b/bbb_cape/schematic/cape.gsch2pcb
new file mode 100644
index 0000000..e8ff08e
--- /dev/null
+++ b/bbb_cape/schematic/cape.gsch2pcb

@@ -0,0 +1,2 @@
+schematics cape-main.sch
+output-name cape

diff --git a/bbb_cape/schematic/cape.pcb b/bbb_cape/schematic/cape.pcb
new file mode 100644
index 0000000..c70b378
--- /dev/null
+++ b/bbb_cape/schematic/cape.pcb

@@ -0,0 +1,7179 @@
+# release: pcb 20110918
+
+# To read pcb files, the pcb version (or the git source date) must be >= the file version
+FileVersion[20070407]
+
+PCB["971 BBB Cape" 500000 400000]
+
+Grid[500.0 441 0 1]
+Cursor[259941 98500 0.000000]
+PolyArea[3100.006200]
+Thermal[0.500000]
+DRC[800 1000 800 10 1000 500]
+Flags("showdrc,rubberband,autodrc,clearnew,snappin")
+Groups("1,c:3:2:4,s:5")
+Styles["Signal,800,2000,1000,800:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
+
+Symbol[' ' 1800]
+(
+)
+Symbol['!' 1200]
+(
+	SymbolLine[0 4500 0 5000 800]
+	SymbolLine[0 1000 0 3500 800]
+)
+Symbol['"' 1200]
+(
+	SymbolLine[0 1000 0 2000 800]
+	SymbolLine[1000 1000 1000 2000 800]
+)
+Symbol['#' 1200]
+(
+	SymbolLine[0 3500 2000 3500 800]
+	SymbolLine[0 2500 2000 2500 800]
+	SymbolLine[1500 2000 1500 4000 800]
+	SymbolLine[500 2000 500 4000 800]
+)
+Symbol['$' 1200]
+(
+	SymbolLine[1500 1500 2000 2000 800]
+	SymbolLine[500 1500 1500 1500 800]
+	SymbolLine[0 2000 500 1500 800]
+	SymbolLine[0 2000 0 2500 800]
+	SymbolLine[0 2500 500 3000 800]
+	SymbolLine[500 3000 1500 3000 800]
+	SymbolLine[1500 3000 2000 3500 800]
+	SymbolLine[2000 3500 2000 4000 800]
+	SymbolLine[1500 4500 2000 4000 800]
+	SymbolLine[500 4500 1500 4500 800]
+	SymbolLine[0 4000 500 4500 800]
+	SymbolLine[1000 1000 1000 5000 800]
+)
+Symbol['%' 1200]
+(
+	SymbolLine[0 1500 0 2000 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[500 1000 1000 1000 800]
+	SymbolLine[1000 1000 1500 1500 800]
+	SymbolLine[1500 1500 1500 2000 800]
+	SymbolLine[1000 2500 1500 2000 800]
+	SymbolLine[500 2500 1000 2500 800]
+	SymbolLine[0 2000 500 2500 800]
+	SymbolLine[0 5000 4000 1000 800]
+	SymbolLine[3500 5000 4000 4500 800]
+	SymbolLine[4000 4000 4000 4500 800]
+	SymbolLine[3500 3500 4000 4000 800]
+	SymbolLine[3000 3500 3500 3500 800]
+	SymbolLine[2500 4000 3000 3500 800]
+	SymbolLine[2500 4000 2500 4500 800]
+	SymbolLine[2500 4500 3000 5000 800]
+	SymbolLine[3000 5000 3500 5000 800]
+)
+Symbol['&' 1200]
+(
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[0 1500 0 2500 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[0 3500 1500 2000 800]
+	SymbolLine[500 5000 1000 5000 800]
+	SymbolLine[1000 5000 2000 4000 800]
+	SymbolLine[0 2500 2500 5000 800]
+	SymbolLine[500 1000 1000 1000 800]
+	SymbolLine[1000 1000 1500 1500 800]
+	SymbolLine[1500 1500 1500 2000 800]
+	SymbolLine[0 3500 0 4500 800]
+)
+Symbol[''' 1200]
+(
+	SymbolLine[0 2000 1000 1000 800]
+)
+Symbol['(' 1200]
+(
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[0 1500 0 4500 800]
+)
+Symbol[')' 1200]
+(
+	SymbolLine[0 1000 500 1500 800]
+	SymbolLine[500 1500 500 4500 800]
+	SymbolLine[0 5000 500 4500 800]
+)
+Symbol['*' 1200]
+(
+	SymbolLine[0 2000 2000 4000 800]
+	SymbolLine[0 4000 2000 2000 800]
+	SymbolLine[0 3000 2000 3000 800]
+	SymbolLine[1000 2000 1000 4000 800]
+)
+Symbol['+' 1200]
+(
+	SymbolLine[0 3000 2000 3000 800]
+	SymbolLine[1000 2000 1000 4000 800]
+)
+Symbol[',' 1200]
+(
+	SymbolLine[0 6000 1000 5000 800]
+)
+Symbol['-' 1200]
+(
+	SymbolLine[0 3000 2000 3000 800]
+)
+Symbol['.' 1200]
+(
+	SymbolLine[0 5000 500 5000 800]
+)
+Symbol['/' 1200]
+(
+	SymbolLine[0 4500 3000 1500 800]
+)
+Symbol['0' 1200]
+(
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[0 1500 0 4500 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[500 1000 1500 1000 800]
+	SymbolLine[1500 1000 2000 1500 800]
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+Via[398441 109000 2000 1600 0 1000 "" ""]
+Via[386023 242187 2000 1600 0 1000 "" ""]
+Via[398441 227000 2000 1600 0 1000 "" ""]
+Via[440941 277000 6000 2000 0 3500 "" ""]
+Via[354441 315000 2000 1600 0 1000 "" ""]
+Via[354441 310500 2000 1600 0 1000 "" ""]
+Via[354441 304500 2000 1600 0 1000 "" ""]
+Via[354441 298500 2000 1600 0 1000 "" ""]
+Via[354441 292500 2000 1600 0 1000 "" ""]
+Via[354441 286500 2000 1600 0 1000 "" ""]
+Via[354441 280500 2000 1600 0 1000 "" ""]
+Via[387441 280500 2000 1600 0 1000 "" ""]
+Via[387441 286500 2000 1600 0 1000 "" ""]
+Via[387441 292500 2000 1600 0 1000 "" ""]
+Via[387441 298500 2000 1600 0 1000 "" ""]
+Via[387441 310500 2000 1600 0 1000 "" ""]
+Via[387441 315000 2000 1600 0 1000 "" ""]
+Via[387441 304500 2000 1600 0 1000 "" ""]
+Via[390941 324000 2000 1600 0 1000 "" ""]
+Via[390941 328500 2000 1600 0 1000 "" ""]
+Via[391441 334000 2000 1600 0 1000 "" ""]
+Via[394941 341500 2000 1600 0 1000 "" ""]
+Via[393941 348500 2000 1600 0 1000 "" ""]
+Via[392441 355000 2000 1600 0 1000 "" ""]
+Via[434449 343500 2000 1600 0 1000 "" ""]
+Via[440449 343500 2000 1600 0 1000 "" ""]
+Via[163941 272500 2000 1600 0 1000 "" ""]
+Via[193390 272500 2000 1600 0 1000 "" ""]
+Via[112222 272660 2000 1600 0 1000 "" ""]
+Via[245441 272500 2000 1600 0 1000 "" ""]
+Via[114441 278500 2000 1600 0 1000 "" ""]
+Via[115441 267500 2000 1600 0 1000 "" ""]
+Via[152441 278500 2000 1600 0 1000 "" ""]
+Via[151941 268000 2000 1600 0 1000 "" ""]
+Via[127941 252000 2000 1600 0 1000 "" ""]
+Via[141441 252000 2000 1600 0 1000 "" ""]
+Via[198441 277500 2000 1600 0 1000 "" ""]
+Via[195441 267000 2000 1600 0 1000 "" ""]
+Via[208941 252000 2000 1600 0 1000 "" ""]
+Via[223941 252000 2000 1600 0 1000 "" ""]
+Via[234441 277500 2000 1600 0 1000 "" ""]
+Via[235941 267000 2000 1600 0 1000 "" ""]
+Via[128941 125500 2000 1600 0 1000 "" ""]
+Via[128941 131500 2000 1600 0 1000 "" ""]
+Via[128941 137500 2000 1600 0 1000 "" ""]
+Via[128941 145000 2000 1600 0 1000 "" ""]
+Via[128941 151500 2000 1600 0 1000 "" ""]
+Via[128941 157500 2000 1600 0 1000 "" ""]
+Via[162441 157500 2000 1600 0 1000 "" ""]
+Via[162441 151500 2000 1600 0 1000 "" ""]
+Via[161941 145000 2000 1600 0 1000 "" ""]
+Via[162441 137500 2000 1600 0 1000 "" ""]
+Via[162941 131500 2000 1600 0 1000 "" ""]
+Via[162941 125500 2000 1600 0 1000 "" ""]
+Via[165941 169000 2000 1600 0 1000 "" ""]
+Via[165941 173500 2000 1600 0 1000 "" ""]
+Via[165941 179500 2000 1600 0 1000 "" ""]
+Via[169441 186000 2000 1600 0 1000 "" ""]
+Via[169441 191500 2000 1600 0 1000 "" ""]
+Via[169441 198500 2000 1600 0 1000 "" ""]
+Via[141307 99117 2000 1600 0 1000 "" ""]
+Via[158441 76171 2000 1600 0 1000 "" ""]
+Via[158441 71171 2000 1600 0 1000 "" ""]
+Via[158441 73500 2000 1600 0 1000 "" ""]
+Via[197441 85500 2000 1600 0 1000 "" ""]
+Via[195441 88500 2000 1600 0 1000 "" ""]
+Via[197441 91500 2000 1600 0 1000 "" ""]
+Via[124831 97615 2000 1600 0 1000 "" ""]
+Via[135441 61500 2000 1600 0 1000 "" ""]
+Via[135441 65000 2000 1600 0 1000 "" ""]
+Via[139941 62000 2000 1600 0 1000 "" ""]
+Via[153941 62000 2000 1600 0 1000 "" ""]
+Via[111941 66000 2000 1600 0 1000 "" ""]
+Via[117941 66000 2000 1600 0 1000 "" ""]
+Via[126441 66000 2000 1600 0 1000 "" ""]
+Via[126441 59500 2000 1600 0 1000 "" ""]
+Via[111941 59000 2000 1600 0 1000 "" ""]
+Via[111941 42500 2000 1600 0 1000 "" ""]
+Via[142441 42500 2000 1600 0 1000 "" ""]
+Via[142441 50500 2000 1600 0 1000 "" ""]
+Via[154941 54500 2000 1600 0 1000 "" ""]
+Via[149441 50500 2000 1600 0 1000 "" ""]
+Via[121941 42500 2000 1600 0 1000 "" ""]
+Via[130941 42500 2000 1600 0 1000 "" ""]
+Via[309441 258432 2000 1600 0 1000 "" ""]
+Via[309441 263550 2000 1600 0 1000 "" ""]
+Via[310941 284060 2000 1600 0 1000 "" ""]
+Via[305696 292500 2000 1600 0 1000 "" ""]
+Via[263441 80000 2000 1600 0 1000 "" ""]
+Via[304584 192517 2000 1600 0 1000 "" ""]
+Via[304706 189417 2000 1600 0 1000 "" ""]
+Via[305280 195617 2000 1600 0 1000 "" ""]
+Via[246941 162000 2000 1600 0 1000 "" ""]
+Via[242441 170500 2000 1600 0 1000 "" ""]
+Via[246441 170500 2000 1600 0 1000 "" ""]
+Via[250941 170500 2000 1600 0 1000 "" ""]
+Via[221884 146000 2000 1600 0 1000 "" ""]
+Via[224441 148000 2000 1600 0 1000 "" ""]
+Via[356441 167000 2000 1600 0 1000 "" ""]
+Via[338441 175808 2000 1600 0 1000 "" ""]
+Via[338441 169876 2000 1600 0 1000 "" ""]
+Via[225441 151000 2000 1600 0 1000 "" ""]
+Via[219441 127500 2000 1600 0 1000 "" ""]
+Via[220729 134420 2000 1600 0 1000 "" ""]
+Via[217441 121000 2000 1600 0 1000 "" ""]
+Via[260568 83003 2000 1600 0 1000 "" ""]
+Via[240391 121436 2000 1600 0 1000 "" ""]
+Via[230441 107000 2000 1600 0 1000 "" ""]
+Via[264034 117069 2500 1600 0 1000 "" ""]
+Via[279441 115000 2000 1600 0 1000 "" ""]
+Via[246731 96969 2000 1600 0 1000 "" ""]
+Via[270441 64000 2000 1600 0 1000 "" ""]
+Via[270441 57500 2000 1600 0 1000 "" ""]
+Via[270441 50500 2000 1600 0 1000 "" ""]
+Via[392188 161000 2000 1600 0 1000 "" ""]
+Via[388207 152720 2000 1600 0 1000 "" ""]
+Via[191363 55551 2000 1600 0 1000 "" ""]
+Via[178887 57182 2000 1600 0 1000 "" ""]
+Via[168732 49167 2000 1600 0 1000 "" ""]
+Via[296727 143773 2500 1600 0 1000 "" ""]
+Via[339837 58173 2000 1600 0 1000 "" ""]
+Via[353390 60479 2000 1600 0 1000 "" ""]
+Via[337441 237000 2000 1600 0 1000 "" ""]
+Via[377347 237822 2000 1600 0 1000 "" ""]
+Via[230441 153000 2000 1600 0 1000 "" ""]
+Via[358941 191500 2000 1600 0 1000 "" ""]
+Via[220441 140500 2000 1600 0 1000 "" ""]
+Via[218441 138500 2000 1600 0 1000 "" ""]
+Via[198441 137500 2000 1600 0 1000 "" ""]
+Via[198441 130500 2000 1600 0 1000 "" ""]
+Via[205441 123000 2000 1600 0 1000 "" ""]
+Via[185441 172000 2000 1600 0 1000 "" ""]
+Via[177441 172000 2000 1600 0 1000 "" ""]
+Via[177441 182500 2000 1600 0 1000 "" ""]
+Via[185441 182500 2000 1600 0 1000 "" ""]
+Via[193941 187500 2000 1600 0 1000 "" ""]
+Via[202441 187500 2000 1600 0 1000 "" ""]
+Via[210441 187500 2000 1600 0 1000 "" ""]
+Via[220441 185000 2000 1600 0 1000 "" ""]
+Via[224941 179500 2000 1600 0 1000 "" ""]
+Via[225441 173500 2000 1600 0 1000 "" ""]
+Via[224941 164500 2000 1600 0 1000 "" ""]
+Via[224441 156000 2000 1600 0 1000 "" ""]
+Via[212941 162000 2000 1600 0 1000 "" ""]
+Via[203941 162500 2000 1600 0 1000 "" ""]
+Via[193941 163000 2000 1600 0 1000 "" ""]
+Via[236441 164500 2000 1600 0 1000 "" ""]
+Via[181941 141500 2000 1600 0 1000 "" ""]
+Via[104441 195500 2000 1600 0 1000 "" ""]
+Via[100941 195500 2000 1600 0 1000 "" ""]
+Via[260941 208500 2000 1600 0 1000 "" ""]
+Via[269441 201500 2000 1600 0 1000 "" ""]
+Via[269941 168500 2000 1600 0 1000 "" ""]
+Via[251941 189500 2000 1600 0 1000 "" ""]
+Via[243941 198000 2000 1600 0 1000 "" ""]
+Via[245863 208476 2000 1600 0 1000 "" ""]
+Via[261502 92633 2000 1600 0 1000 "" ""]
+Via[268941 86000 2500 1600 0 1000 "" ""]
+Via[249101 71207 2000 1600 0 1000 "" ""]
+Via[229818 45012 2000 1600 0 1000 "" ""]
+Via[270441 43000 2000 1600 0 1000 "" ""]
+
+Element["lock" "22-23-2031" "X6/X1/CONN12" "" 463500 16000 21000 -12200 3 100 ""]
+(
+	Pin[-10000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[0 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[10000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	ElementLine [-15000 -12200 -15000 12800 1000]
+	ElementLine [15000 -12200 15000 12800 1000]
+	ElementLine [-15000 -12200 15000 -12200 1000]
+	ElementLine [-15000 -5700 15000 -5700 1000]
+	ElementLine [-5000 -5700 -5000 12800 1000]
+	ElementLine [5000 -5700 5000 12800 1000]
+	ElementLine [-15000 12800 15000 12800 1000]
+	ElementLine [-15000 12800 -5000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2031" "X6/X3/CONN12" "" 463500 76000 21000 -12200 3 100 ""]
+(
+	Pin[-10000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[0 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[10000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	ElementLine [-15000 -12200 -15000 12800 1000]
+	ElementLine [15000 -12200 15000 12800 1000]
+	ElementLine [15000 -12200 -15000 -12200 1000]
+	ElementLine [-15000 -5700 15000 -5700 1000]
+	ElementLine [-5000 12800 -5000 -5700 1000]
+	ElementLine [5000 12800 5000 -5700 1000]
+	ElementLine [-15000 12800 15000 12800 1000]
+	ElementLine [-15000 12800 -5000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2031" "X6/X4/CONN12" "" 463500 106000 21000 -12200 3 100 ""]
+(
+	Pin[-10000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[0 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[10000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	ElementLine [-15000 -12200 -15000 12800 1000]
+	ElementLine [15000 -12200 15000 12800 1000]
+	ElementLine [15000 -12200 -15000 -12200 1000]
+	ElementLine [-15000 -5700 15000 -5700 1000]
+	ElementLine [-5000 12800 -5000 -5700 1000]
+	ElementLine [5000 12800 5000 -5700 1000]
+	ElementLine [-15000 12800 15000 12800 1000]
+	ElementLine [-15000 12800 -5000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2031" "X7/X1/CONN12" "" 463500 136000 21000 -12200 3 100 ""]
+(
+	Pin[-10000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[0 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[10000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	ElementLine [-15000 -12200 -15000 12800 1000]
+	ElementLine [15000 -12200 15000 12800 1000]
+	ElementLine [15000 -12200 -15000 -12200 1000]
+	ElementLine [-15000 -5700 15000 -5700 1000]
+	ElementLine [-5000 12800 -5000 -5700 1000]
+	ElementLine [5000 12800 5000 -5700 1000]
+	ElementLine [-15000 12800 15000 12800 1000]
+	ElementLine [-15000 12800 -5000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2031" "X7/X2/CONN12" "" 463500 166000 21000 -12200 3 100 ""]
+(
+	Pin[-10000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[0 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[10000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	ElementLine [-15000 -12200 -15000 12800 1000]
+	ElementLine [15000 -12200 15000 12800 1000]
+	ElementLine [-15000 -12200 15000 -12200 1000]
+	ElementLine [-15000 -5700 15000 -5700 1000]
+	ElementLine [-5000 -5700 -5000 12800 1000]
+	ElementLine [5000 -5700 5000 12800 1000]
+	ElementLine [-15000 12800 15000 12800 1000]
+	ElementLine [-15000 12800 -5000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2031" "X7/X3/CONN12" "" 463500 196000 21000 -12200 3 100 "selected"]
+(
+	Pin[-10000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[0 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[10000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	ElementLine [-15000 -12200 -15000 12800 1000]
+	ElementLine [15000 -12200 15000 12800 1000]
+	ElementLine [15000 -12200 -15000 -12200 1000]
+	ElementLine [-15000 -5700 15000 -5700 1000]
+	ElementLine [-5000 12800 -5000 -5700 1000]
+	ElementLine [5000 12800 5000 -5700 1000]
+	ElementLine [-15000 12800 15000 12800 1000]
+	ElementLine [-15000 12800 -5000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2031" "X7/X4/CONN12" "" 463500 226000 21000 -12200 3 100 "selected"]
+(
+	Pin[-10000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[0 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[10000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	ElementLine [-15000 -12200 -15000 12800 1000]
+	ElementLine [15000 -12200 15000 12800 1000]
+	ElementLine [15000 -12200 -15000 -12200 1000]
+	ElementLine [-15000 -5700 15000 -5700 1000]
+	ElementLine [-5000 12800 -5000 -5700 1000]
+	ElementLine [5000 12800 5000 -5700 1000]
+	ElementLine [-15000 12800 15000 12800 1000]
+	ElementLine [-15000 12800 -5000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2031" "X5/X1/CONN12" "" 463500 256000 21000 -12200 3 100 ""]
+(
+	Pin[-10000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[0 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[10000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	ElementLine [-15000 -12200 -15000 12800 1000]
+	ElementLine [15000 -12200 15000 12800 1000]
+	ElementLine [15000 -12200 -15000 -12200 1000]
+	ElementLine [-15000 -5700 15000 -5700 1000]
+	ElementLine [-5000 12800 -5000 -5700 1000]
+	ElementLine [5000 12800 5000 -5700 1000]
+	ElementLine [-15000 12800 15000 12800 1000]
+	ElementLine [-15000 12800 -5000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2031" "X5/X2/CONN12" "" 463500 286000 21000 -12200 3 100 ""]
+(
+	Pin[-10000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[0 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[10000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	ElementLine [-15000 -12200 -15000 12800 1000]
+	ElementLine [15000 -12200 15000 12800 1000]
+	ElementLine [15000 -12200 -15000 -12200 1000]
+	ElementLine [-15000 -5700 15000 -5700 1000]
+	ElementLine [-5000 12800 -5000 -5700 1000]
+	ElementLine [5000 12800 5000 -5700 1000]
+	ElementLine [-15000 12800 15000 12800 1000]
+	ElementLine [-15000 12800 -5000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2031" "X5/X3/CONN12" "" 463500 316000 21000 -12200 3 100 ""]
+(
+	Pin[-10000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[0 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[10000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	ElementLine [-15000 -12200 -15000 12800 1000]
+	ElementLine [15000 -12200 15000 12800 1000]
+	ElementLine [15000 -12200 -15000 -12200 1000]
+	ElementLine [-15000 -5700 15000 -5700 1000]
+	ElementLine [-5000 12800 -5000 -5700 1000]
+	ElementLine [5000 12800 5000 -5700 1000]
+	ElementLine [-15000 12800 15000 12800 1000]
+	ElementLine [-15000 12800 -5000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2031" "X5/X4/CONN12" "" 463500 346000 21000 -12200 3 100 ""]
+(
+	Pin[-10000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[0 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[10000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	ElementLine [-15000 -12200 -15000 12800 1000]
+	ElementLine [15000 -12200 15000 12800 1000]
+	ElementLine [15000 -12200 -15000 -12200 1000]
+	ElementLine [-15000 -5700 15000 -5700 1000]
+	ElementLine [-5000 12800 -5000 -5700 1000]
+	ElementLine [5000 12800 5000 -5700 1000]
+	ElementLine [-15000 12800 15000 12800 1000]
+	ElementLine [-15000 12800 -5000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2041" "X1/X2/CONN4" "" 422000 16000 16000 -12200 3 100 ""]
+(
+	Pin[-15000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[-5000 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[5000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	Pin[15000 0 6500 3000 7100 4000 "4" "4" "lock,edge2"]
+	ElementLine [-20000 -12200 -20000 12800 1000]
+	ElementLine [20000 -12200 20000 12800 1000]
+	ElementLine [20000 -12200 -20000 -12200 1000]
+	ElementLine [-20000 -5700 20000 -5700 1000]
+	ElementLine [-10000 12800 -10000 -5700 1000]
+	ElementLine [0 12800 0 -5700 1000]
+	ElementLine [10000 12800 10000 -5700 1000]
+	ElementLine [-20000 12800 20000 12800 1000]
+	ElementLine [-20000 12800 -10000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2041" "X4/X4/CONN4" "" 422000 226000 16000 -12200 3 100 "selected"]
+(
+	Pin[-15000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[-5000 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[5000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	Pin[15000 0 6500 3000 7100 4000 "4" "4" "lock,edge2"]
+	ElementLine [-20000 -12200 -20000 12800 1000]
+	ElementLine [20000 -12200 20000 12800 1000]
+	ElementLine [20000 -12200 -20000 -12200 1000]
+	ElementLine [-20000 -5700 20000 -5700 1000]
+	ElementLine [-10000 12800 -10000 -5700 1000]
+	ElementLine [0 12800 0 -5700 1000]
+	ElementLine [10000 12800 10000 -5700 1000]
+	ElementLine [-20000 12800 20000 12800 1000]
+	ElementLine [-20000 12800 -10000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2041" "X4/X2/CONN4" "" 422000 196000 16000 -12200 3 100 ""]
+(
+	Pin[-15000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[-5000 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[5000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	Pin[15000 0 6500 3000 7100 4000 "4" "4" "lock,edge2"]
+	ElementLine [-20000 -12200 -20000 12800 1000]
+	ElementLine [20000 -12200 20000 12800 1000]
+	ElementLine [20000 -12200 -20000 -12200 1000]
+	ElementLine [-20000 -5700 20000 -5700 1000]
+	ElementLine [-10000 12800 -10000 -5700 1000]
+	ElementLine [0 12800 0 -5700 1000]
+	ElementLine [10000 12800 10000 -5700 1000]
+	ElementLine [-20000 12800 20000 12800 1000]
+	ElementLine [-20000 12800 -10000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2041" "X3/X4/CONN4" "" 422000 166000 16000 -12200 3 100 ""]
+(
+	Pin[-15000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[-5000 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[5000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	Pin[15000 0 6500 3000 7100 4000 "4" "4" "lock,edge2"]
+	ElementLine [-20000 -12200 -20000 12800 1000]
+	ElementLine [20000 -12200 20000 12800 1000]
+	ElementLine [20000 -12200 -20000 -12200 1000]
+	ElementLine [-20000 -5700 20000 -5700 1000]
+	ElementLine [-10000 12800 -10000 -5700 1000]
+	ElementLine [0 12800 0 -5700 1000]
+	ElementLine [10000 12800 10000 -5700 1000]
+	ElementLine [-20000 12800 20000 12800 1000]
+	ElementLine [-20000 12800 -10000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2041" "X3/X2/CONN4" "" 422000 136000 16000 -12200 3 100 ""]
+(
+	Pin[-15000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[-5000 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[5000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	Pin[15000 0 6500 3000 7100 4000 "4" "4" "lock,edge2"]
+	ElementLine [-20000 -12200 -20000 12800 1000]
+	ElementLine [20000 -12200 20000 12800 1000]
+	ElementLine [-20000 -12200 20000 -12200 1000]
+	ElementLine [-20000 -5700 20000 -5700 1000]
+	ElementLine [-10000 -5700 -10000 12800 1000]
+	ElementLine [0 -5700 0 12800 1000]
+	ElementLine [10000 -5700 10000 12800 1000]
+	ElementLine [-20000 12800 20000 12800 1000]
+	ElementLine [-20000 12800 -10000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2041" "X2/X4/CONN4" "" 422000 106000 16000 -12200 3 100 ""]
+(
+	Pin[-15000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[-5000 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[5000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	Pin[15000 0 6500 3000 7100 4000 "4" "4" "lock,edge2"]
+	ElementLine [-20000 -12200 -20000 12800 1000]
+	ElementLine [20000 -12200 20000 12800 1000]
+	ElementLine [20000 -12200 -20000 -12200 1000]
+	ElementLine [-20000 -5700 20000 -5700 1000]
+	ElementLine [-10000 12800 -10000 -5700 1000]
+	ElementLine [0 12800 0 -5700 1000]
+	ElementLine [10000 12800 10000 -5700 1000]
+	ElementLine [-20000 12800 20000 12800 1000]
+	ElementLine [-20000 12800 -10000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2041" "X2/X2/CONN4" "" 422000 76000 16000 -12200 3 100 ""]
+(
+	Pin[-15000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[-5000 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[5000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	Pin[15000 0 6500 3000 7100 4000 "4" "4" "lock,edge2"]
+	ElementLine [-20000 -12200 -20000 12800 1000]
+	ElementLine [20000 -12200 20000 12800 1000]
+	ElementLine [-20000 -12200 20000 -12200 1000]
+	ElementLine [-20000 -5700 20000 -5700 1000]
+	ElementLine [-10000 -5700 -10000 12800 1000]
+	ElementLine [0 -5700 0 12800 1000]
+	ElementLine [10000 -5700 10000 12800 1000]
+	ElementLine [-20000 12800 20000 12800 1000]
+	ElementLine [-20000 12800 -10000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2031" "X6/X2/CONN12" "" 463500 46000 21000 -12200 3 100 ""]
+(
+	Pin[-10000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[0 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[10000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	ElementLine [-15000 -12200 -15000 12800 1000]
+	ElementLine [15000 -12200 15000 12800 1000]
+	ElementLine [15000 -12200 -15000 -12200 1000]
+	ElementLine [-15000 -5700 15000 -5700 1000]
+	ElementLine [-5000 12800 -5000 -5700 1000]
+	ElementLine [5000 12800 5000 -5700 1000]
+	ElementLine [-15000 12800 15000 12800 1000]
+	ElementLine [-15000 12800 -5000 12800 1000]
+
+	)
+
+Element["lock" "22-23-2041" "X1/X4/CONN4" "" 422000 46000 16000 -12200 3 100 ""]
+(
+	Pin[-15000 0 6500 3000 7100 4000 "1" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[-5000 0 6500 3000 7100 4000 "2" "2" "lock,edge2,thermal(1X)"]
+	Pin[5000 0 6500 3000 7100 4000 "3" "3" "lock,edge2"]
+	Pin[15000 0 6500 3000 7100 4000 "4" "4" "lock,edge2"]
+	ElementLine [-20000 -12200 -20000 12800 1000]
+	ElementLine [20000 -12200 20000 12800 1000]
+	ElementLine [20000 -12200 -20000 -12200 1000]
+	ElementLine [-20000 -5700 20000 -5700 1000]
+	ElementLine [-10000 12800 -10000 -5700 1000]
+	ElementLine [0 12800 0 -5700 1000]
+	ElementLine [10000 12800 10000 -5700 1000]
+	ElementLine [-20000 12800 20000 12800 1000]
+	ElementLine [-20000 12800 -10000 12800 1000]
+
+	)
+
+Element["" "0603" "X4/C1" "" 395441 209000 -3150 3150 1 100 ""]
+(
+	Pad[-492 2559 492 2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["onsolder" "TSSOP16" "X4/U4" "" 385441 218000 6000 2000 3 100 "auto"]
+(
+	Pad[8956 9311 8956 13917 1299 1000 2299 "1B" "1" "onsolder,square,edge2"]
+	Pad[6397 9311 6397 13917 1299 1000 2299 "1A" "2" "onsolder,square,edge2"]
+	Pad[3838 9311 3838 13917 1299 1000 2299 "1Y" "3" "onsolder,square,edge2"]
+	Pad[1279 9311 1279 13917 1299 1000 2299 "ENABLE" "4" "onsolder,square,edge2"]
+	Pad[-1279 9311 -1279 13917 1299 1000 2299 "2Y" "5" "onsolder,square,edge2"]
+	Pad[-3838 9311 -3838 13917 1299 1000 2299 "2A" "6" "onsolder,square,edge2"]
+	Pad[-6397 9311 -6397 13917 1299 1000 2299 "2B" "7" "onsolder,square,edge2"]
+	Pad[-8956 9311 -8956 13917 1299 1000 2299 "GND" "8" "onsolder,square,edge2"]
+	Pad[-8956 -13917 -8956 -9311 1299 1000 2299 "3B" "9" "onsolder,square"]
+	Pad[-6397 -13917 -6397 -9311 1299 1000 2299 "3A" "10" "onsolder,square"]
+	Pad[-3838 -13917 -3838 -9311 1299 1000 2299 "3Y" "11" "onsolder,square"]
+	Pad[-1279 -13917 -1279 -9311 1299 1000 2299 "_ENABLE_" "12" "onsolder,square"]
+	Pad[1279 -13917 1279 -9311 1299 1000 2299 "4Y" "13" "onsolder,square"]
+	Pad[3838 -13917 3838 -9311 1299 1000 2299 "4A" "14" "onsolder,square"]
+	Pad[6397 -13917 6397 -9311 1299 1000 2299 "4B" "15" "onsolder,square"]
+	Pad[8956 -13917 8956 -9311 1299 1000 2299 "VCC" "16" "onsolder,square"]
+	ElementLine [-10606 15566 10606 15566 1000]
+	ElementLine [-10606 -15566 -10606 15566 1000]
+	ElementLine [-10606 -15566 10606 -15566 1000]
+	ElementLine [10606 2500 10606 15566 1000]
+	ElementLine [10606 -15566 10606 -2500 1000]
+	ElementArc [10606 0 2500 2500 270 180 1000]
+
+	)
+
+Element["onsolder" "0603" "X6/C1" "" 398441 78000 -3150 -3150 1 100 "auto"]
+(
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-492 2559 492 2559 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["" "0603" "X5/C1" "" 429441 330000 3150 3150 2 100 ""]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["onsolder" "TSSOP16" "X5/U4" "" 433603 307614 -6000 -2000 1 100 "auto"]
+(
+	Pad[-8956 -13917 -8956 -9311 1299 1000 2299 "1B" "1" "onsolder,square"]
+	Pad[-6397 -13917 -6397 -9311 1299 1000 2299 "1A" "2" "onsolder,square"]
+	Pad[-3838 -13917 -3838 -9311 1299 1000 2299 "1Y" "3" "onsolder,square"]
+	Pad[-1279 -13917 -1279 -9311 1299 1000 2299 "ENABLE" "4" "onsolder,square"]
+	Pad[1279 -13917 1279 -9311 1299 1000 2299 "2Y" "5" "onsolder,square"]
+	Pad[3838 -13917 3838 -9311 1299 1000 2299 "2A" "6" "onsolder,square"]
+	Pad[6397 -13917 6397 -9311 1299 1000 2299 "2B" "7" "onsolder,square"]
+	Pad[8956 -13917 8956 -9311 1299 1000 2299 "GND" "8" "onsolder,square"]
+	Pad[8956 9311 8956 13917 1299 1000 2299 "3B" "9" "onsolder,square,edge2"]
+	Pad[6397 9311 6397 13917 1299 1000 2299 "3A" "10" "onsolder,square,edge2"]
+	Pad[3838 9311 3838 13917 1799 1000 2799 "3Y" "11" "onsolder,square,edge2"]
+	Pad[1279 9311 1279 13917 1299 1000 2299 "_ENABLE_" "12" "onsolder,square,edge2"]
+	Pad[-1279 9311 -1279 13917 1299 1000 2299 "4Y" "13" "onsolder,square,edge2"]
+	Pad[-3838 9311 -3838 13917 1299 1000 2299 "4A" "14" "onsolder,square,edge2"]
+	Pad[-6397 9311 -6397 13917 1299 1000 2299 "4B" "15" "onsolder,square,edge2"]
+	Pad[-8956 9311 -8956 13917 1299 1000 2299 "VCC" "16" "onsolder,square,edge2"]
+	ElementLine [-10606 -15566 10606 -15566 1000]
+	ElementLine [10606 -15566 10606 15566 1000]
+	ElementLine [-10606 15566 10606 15566 1000]
+	ElementLine [-10606 -15566 -10606 -2500 1000]
+	ElementLine [-10606 2500 -10606 15566 1000]
+	ElementArc [-10606 0 2500 2500 90 180 1000]
+
+	)
+
+Element["" "0603" "X3/C1" "" 393135 150385 -3150 3150 1 100 ""]
+(
+	Pad[-492 2559 492 2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "X1/C1" "" 393441 31500 -3150 3150 1 100 ""]
+(
+	Pad[-492 2559 492 2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "X2/C1" "" 393441 91441 -3150 3150 1 100 ""]
+(
+	Pad[-492 2559 492 2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["onsolder" "0603" "X1/X2/R9" "" 424441 8000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X5/X1/C2" "" 458441 247000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X5/X4/C2" "" 458500 337000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X5/X2/C2" "" 458441 277000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X7/X3/C2" "" 458441 187000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X7/X2/C2" "" 458441 157000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X6/X1/C2" "" 458441 7000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X6/X2/C2" "" 458500 37000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X6/X3/C2" "" 458441 67000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X6/X1/R6" "" 470941 23500 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X6/X3/R6" "" 470941 83500 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X6/X4/R6" "" 470941 113500 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X7/X1/R6" "" 470941 144000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X7/X2/R6" "" 470941 173500 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X7/X3/R6" "" 470941 203500 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X7/X4/R6" "" 470941 234000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X1/X4/R9" "" 424441 38000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X1/X4/R10" "" 434441 38000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X1/X4/R6" "" 424382 53500 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X1/X4/C2" "" 411941 37000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X1/X4/R8" "" 436941 55941 -3150 -3150 1 100 "auto"]
+(
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-492 2559 492 2559 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X2/X2/R6" "" 424382 83500 -10291 74850 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X2/X2/R8" "" 436941 86059 9079 45850 1 100 "auto"]
+(
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-492 2559 492 2559 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X2/X2/C2" "" 411941 67000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X2/X2/R9" "" 424441 68000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X2/X2/R10" "" 434441 68000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X2/X4/R9" "" 424441 98000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X2/X4/R10" "" 434441 98000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X2/X4/R6" "" 424382 113500 -64291 40850 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X2/X4/R8" "" 437000 116000 21850 98850 1 100 "auto"]
+(
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-492 2559 492 2559 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X2/X4/C2" "" 411941 97000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X3/X2/R9" "" 424441 128000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X3/X2/R10" "" 434441 128000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X3/X2/R6" "" 424382 143500 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X3/X2/R8" "" 437000 146000 -3150 -3150 1 100 "auto"]
+(
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-492 2559 492 2559 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X3/X2/C2" "" 412000 127000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X3/X4/R9" "" 424441 158000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X3/X4/R10" "" 434441 158000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X3/X4/R6" "" 424500 173500 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X3/X4/R8" "" 437000 176000 -3150 -3150 1 100 "auto"]
+(
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-492 2559 492 2559 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X3/X4/C2" "" 412000 157000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X4/X2/R9" "" 424441 188000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X4/X2/R10" "" 434441 188000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X4/X2/R6" "" 424382 204000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X4/X2/C2" "" 411941 187000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X4/X4/R10" "" 434441 218000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "onsolder,square"]
+
+	)
+
+Element["onsolder" "0603" "X4/X4/R9" "" 424441 218000 3150 -3150 2 100 "auto"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "onsolder,square"]
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+(
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+	Pad[9000 -3300 9000 3300 5600 3000 6200 "GND" "2" "onsolder,square"]
+	Pad[18100 -3300 18100 3300 5600 3000 6200 "VOUT" "3" "onsolder,square"]
+	Pad[4500 24400 13500 24400 12200 3000 12800 "PAD" "4" "onsolder,square"]
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+	ElementLine [-5314 -1968 -5314 1968 800]
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+(
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+	Pad[-10000 26772 -10000 33071 3504 2000 4104 "RON" "2" "square,edge2"]
+	Pad[-5000 26772 -5000 33071 3504 2000 4104 "EN" "3" "square,edge2"]
+	Pad[0 26772 0 33071 3504 2000 4104 "GND" "4" "square,edge2"]
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+(
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+(
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+	)
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+(
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+	)
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+	)
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+	)
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+	)
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+(
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+	)
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+(
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+	)
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+	)
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+	)
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+	)
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+(
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+	Pin[-5000 0 6500 3000 7100 4000 "2" "2" "edge2"]
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+	Pin[15000 0 6500 3000 7100 4000 "4" "4" "edge2"]
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+	)
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+(
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+	)
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+	Pad[-6397 -13917 -6397 -9311 1299 1000 2299 "2B" "7" "square"]
+	Pad[-8956 -13917 -8956 -9311 1299 1000 2299 "GND" "8" "square"]
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+	Pad[-6397 9311 -6397 13917 1299 1000 2299 "3A" "10" "square,edge2"]
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+	Pad[-1279 9311 -1279 13917 1299 1000 2299 "_ENABLE_" "12" "square,edge2"]
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+	)
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+	Pad[-5000 26772 -5000 33071 3504 2000 4104 "EN" "3" "square,edge2"]
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+	)
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+	)
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+	)
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+	)
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+	)
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+	)
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+	)
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+(
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+	)
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+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "X8/R2" "" 192916 287660 3150 3150 2 100 ""]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "X9/R1" "" 111416 258660 3150 3150 2 100 ""]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "X9/R3" "" 157941 287500 -3150 -3150 0 100 ""]
+(
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "1" "1" "square"]
+	Pad[2559 -492 2559 492 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "X9/C1" "" 108941 266500 -3150 3150 1 100 ""]
+(
+	Pad[-492 2559 492 2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "X9/C4" "" 160441 266500 -3150 3150 1 100 ""]
+(
+	Pad[-492 2559 492 2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "SO14" "X9/U2" "" 134166 272660 -2000 -6000 0 100 ""]
+(
+	Pad[-13500 -15000 -7000 -15000 2000 1000 3000 "OUT" "1" "square"]
+	Pad[-13500 -10000 -7000 -10000 2000 1000 3000 "IN-" "2" "square"]
+	Pad[-13500 -5000 -7000 -5000 2000 1000 3000 "IN+" "3" "square"]
+	Pad[-13500 0 -7000 0 2000 1000 3000 "V-" "4" "square"]
+	Pad[-13500 5000 -7000 5000 2000 1000 3000 "IN+" "5" "square"]
+	Pad[-13500 10000 -7000 10000 2000 1000 3000 "IN-" "6" "square"]
+	Pad[-13500 15000 -7000 15000 2000 1000 3000 "OUT" "7" "square"]
+	Pad[7000 15000 13500 15000 2000 1000 3000 "OUT" "8" "square,edge2"]
+	Pad[7000 10000 13500 10000 2000 1000 3000 "IN-" "9" "square,edge2"]
+	Pad[7000 5000 13500 5000 2000 1000 3000 "IN+" "10" "square,edge2"]
+	Pad[7000 0 13500 0 2000 1000 3000 "V+" "11" "square,edge2"]
+	Pad[7000 -5000 13500 -5000 2000 1000 3000 "IN+" "12" "square,edge2"]
+	Pad[7000 -10000 13500 -10000 2000 1000 3000 "IN-" "13" "square,edge2"]
+	Pad[7000 -15000 13500 -15000 2000 1000 3000 "OUT" "14" "square,edge2"]
+	ElementLine [-15500 -17000 -15500 17000 1000]
+	ElementLine [-15500 17000 15500 17000 1000]
+	ElementLine [15500 17000 15500 -17000 1000]
+	ElementLine [-15500 -17000 -2500 -17000 1000]
+	ElementLine [15500 -17000 2500 -17000 1000]
+	ElementArc [0 -17000 2500 2500 0 180 1000]
+
+	)
+
+Element["" "0603" "X9/R2" "" 111441 287500 3150 3150 2 100 "selected"]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "X9/C2" "" 108941 278500 3150 -3150 3 100 ""]
+(
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 2559 492 2559 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "X9/C3" "" 160441 278500 3150 -3150 3 100 ""]
+(
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 2559 492 2559 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "X9/R4" "" 157941 258500 -3150 -3150 0 100 ""]
+(
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "1" "1" "square"]
+	Pad[2559 -492 2559 492 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "C16" "" 306188 286619 -3150 3150 1 100 ""]
+(
+	Pad[-492 2559 492 2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "C17" "" 304964 260991 -3150 3150 1 100 ""]
+(
+	Pad[-492 2559 492 2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "SO16" "U1" "" 284938 271678 -2000 -6000 0 100 ""]
+(
+	Pad[-13500 -17500 -7000 -17500 2000 1000 3000 "CH0" "1" "square"]
+	Pad[-13500 -12500 -7000 -12500 2000 1000 3000 "CH1" "2" "square"]
+	Pad[-13500 -7500 -7000 -7500 2000 1000 3000 "CH2" "3" "square"]
+	Pad[-13500 -2500 -7000 -2500 2000 1000 3000 "CH3" "4" "square"]
+	Pad[-13500 2500 -7000 2500 2000 1000 3000 "CH4" "5" "square"]
+	Pad[-13500 7500 -7000 7500 2000 1000 3000 "CH5" "6" "square"]
+	Pad[-13500 12500 -7000 12500 2000 1000 3000 "CH6" "7" "square"]
+	Pad[-13500 17500 -7000 17500 2000 1000 3000 "CH7" "8" "square"]
+	Pad[7000 17500 13500 17500 2000 1000 3000 "DGND" "9" "square,edge2"]
+	Pad[7000 12500 13500 12500 2000 1000 3000 "_CS_" "10" "square,edge2"]
+	Pad[7000 7500 13500 7500 2000 1000 3000 "MOSI" "11" "square,edge2"]
+	Pad[7000 2500 13500 2500 2000 1000 3000 "MISO" "12" "square,edge2"]
+	Pad[7000 -2500 13500 -2500 2000 1000 3000 "CLK" "13" "square,edge2"]
+	Pad[7000 -7500 13500 -7500 2000 1000 3000 "AGND" "14" "square,edge2"]
+	Pad[7000 -12500 13500 -12500 2000 1000 3000 "AVDD" "15" "square,edge2"]
+	Pad[7000 -17500 13500 -17500 2000 1000 3000 "DVDD" "16" "square,edge2"]
+	ElementLine [-15500 -19500 -15500 19500 1000]
+	ElementLine [-15500 19500 15500 19500 1000]
+	ElementLine [15500 19500 15500 -19500 1000]
+	ElementLine [-15500 -19500 -2500 -19500 1000]
+	ElementLine [15500 -19500 2500 -19500 1000]
+	ElementArc [0 -19500 2500 2500 0 180 1000]
+
+	)
+
+Element["" "0603" "C8" "" 141441 79000 3150 -3150 3 100 ""]
+(
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 2559 492 2559 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["onsolder" "SOT223" "U3" "" 136799 75571 -25300 -32900 1 100 "auto"]
+(
+	Pad[0 -3300 0 3300 5600 3000 6200 "VIN" "1" "onsolder,square,edge2"]
+	Pad[-9000 -3300 -9000 3300 5600 3000 6200 "GND" "2" "onsolder,square,edge2"]
+	Pad[-18100 -3300 -18100 3300 5600 3000 6200 "VOUT" "3" "onsolder,square,edge2"]
+	Pad[-13500 -24400 -4500 -24400 12200 3000 12800 "PAD" "4" "onsolder,square,edge2"]
+	ElementLine [5200 -32900 5200 8500 1000]
+	ElementLine [-23300 8500 5200 8500 1000]
+	ElementLine [-23300 -32900 -23300 8500 1000]
+	ElementLine [-23300 -32900 5200 -32900 1000]
+
+	)
+
+Element["" "0805" "D2" "" 248855 50500 -3150 -3150 0 100 ""]
+(
+	Pad[-3543 -393 -3543 393 5118 2000 5718 "CATHODE" "1" "square"]
+	Pad[3543 -393 3543 393 5118 2000 5718 "ANODE" "2" "square"]
+	ElementLine [-393 -2755 393 -2755 800]
+	ElementLine [-393 2755 393 2755 800]
+
+	)
+
+Element["" "0805" "D6" "" 248898 64500 -3150 -3150 0 100 ""]
+(
+	Pad[-3543 -393 -3543 393 5118 2000 5718 "CATHODE" "1" "square"]
+	Pad[3543 -393 3543 393 5118 2000 5718 "ANODE" "2" "square"]
+	ElementLine [-393 -2755 393 -2755 800]
+	ElementLine [-393 2755 393 2755 800]
+
+	)
+
+Element["" "0603" "R15" "" 263441 64500 3150 3150 2 100 ""]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "R14" "" 263398 57500 3150 3150 2 100 ""]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "R13" "" 263398 50500 3150 3150 2 100 ""]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0805" "D5" "" 248855 57500 -3150 -3150 0 100 ""]
+(
+	Pad[-3543 -393 -3543 393 5118 2000 5718 "CATHODE" "1" "square"]
+	Pad[3543 -393 3543 393 5118 2000 5718 "ANODE" "2" "square"]
+	ElementLine [-393 -2755 393 -2755 800]
+	ElementLine [-393 2755 393 2755 800]
+
+	)
+
+Element["onsolder" "TSSOP16" "X3/U4" "" 385791 159229 6000 2000 3 100 "auto"]
+(
+	Pad[8956 9311 8956 13917 1299 1000 2299 "1B" "1" "onsolder,square,edge2"]
+	Pad[6397 9311 6397 13917 1299 1000 2299 "1A" "2" "onsolder,square,edge2"]
+	Pad[3838 9311 3838 13917 1299 1000 2299 "1Y" "3" "onsolder,square,edge2"]
+	Pad[1279 9311 1279 13917 1299 1000 2299 "ENABLE" "4" "onsolder,square,edge2"]
+	Pad[-1279 9311 -1279 13917 1299 1000 2299 "2Y" "5" "onsolder,square,edge2"]
+	Pad[-3838 9311 -3838 13917 1299 1000 2299 "2A" "6" "onsolder,square,edge2"]
+	Pad[-6397 9311 -6397 13917 1299 1000 2299 "2B" "7" "onsolder,square,edge2"]
+	Pad[-8956 9311 -8956 13917 1299 1000 2299 "GND" "8" "onsolder,square,edge2"]
+	Pad[-8956 -13917 -8956 -9311 1299 1000 2299 "3B" "9" "onsolder,square"]
+	Pad[-6397 -13917 -6397 -9311 1299 1000 2299 "3A" "10" "onsolder,square"]
+	Pad[-3838 -13917 -3838 -9311 1299 1000 2299 "3Y" "11" "onsolder,square"]
+	Pad[-1279 -13917 -1279 -9311 1299 1000 2299 "_ENABLE_" "12" "onsolder,square"]
+	Pad[1279 -13917 1279 -9311 1299 1000 2299 "4Y" "13" "onsolder,square"]
+	Pad[3838 -13917 3838 -9311 1299 1000 2299 "4A" "14" "onsolder,square"]
+	Pad[6397 -13917 6397 -9311 1299 1000 2299 "4B" "15" "onsolder,square"]
+	Pad[8956 -13917 8956 -9311 1299 1000 2299 "VCC" "16" "onsolder,square"]
+	ElementLine [-10606 15566 10606 15566 1000]
+	ElementLine [-10606 -15566 -10606 15566 1000]
+	ElementLine [-10606 -15566 10606 -15566 1000]
+	ElementLine [10606 2500 10606 15566 1000]
+	ElementLine [10606 -15566 10606 -2500 1000]
+	ElementArc [10606 0 2500 2500 270 180 1000]
+
+	)
+
+Element["onsolder" "TSSOP16" "X2/U4" "" 385441 100000 6000 2000 3 100 "auto"]
+(
+	Pad[8956 9311 8956 13917 1299 1000 2299 "1B" "1" "onsolder,square,edge2"]
+	Pad[6397 9311 6397 13917 1299 1000 2299 "1A" "2" "onsolder,square,edge2"]
+	Pad[3838 9311 3838 13917 1299 1000 2299 "1Y" "3" "onsolder,square,edge2"]
+	Pad[1279 9311 1279 13917 1299 1000 2299 "ENABLE" "4" "onsolder,square,edge2"]
+	Pad[-1279 9311 -1279 13917 1299 1000 2299 "2Y" "5" "onsolder,square,edge2"]
+	Pad[-3838 9311 -3838 13917 1299 1000 2299 "2A" "6" "onsolder,square,edge2"]
+	Pad[-6397 9311 -6397 13917 1299 1000 2299 "2B" "7" "onsolder,square,edge2"]
+	Pad[-8956 9311 -8956 13917 1299 1000 2299 "GND" "8" "onsolder,square,edge2"]
+	Pad[-8956 -13917 -8956 -9311 1299 1000 2299 "3B" "9" "onsolder,square"]
+	Pad[-6397 -13917 -6397 -9311 1299 1000 2299 "3A" "10" "onsolder,square"]
+	Pad[-3838 -13917 -3838 -9311 1299 1000 2299 "3Y" "11" "onsolder,square"]
+	Pad[-1279 -13917 -1279 -9311 1299 1000 2299 "_ENABLE_" "12" "onsolder,square"]
+	Pad[1279 -13917 1279 -9311 1299 1000 2299 "4Y" "13" "onsolder,square"]
+	Pad[3838 -13917 3838 -9311 1299 1000 2299 "4A" "14" "onsolder,square"]
+	Pad[6397 -13917 6397 -9311 1299 1000 2299 "4B" "15" "onsolder,square"]
+	Pad[8956 -13917 8956 -9311 1299 1000 2299 "VCC" "16" "onsolder,square"]
+	ElementLine [-10606 15566 10606 15566 1000]
+	ElementLine [-10606 -15566 -10606 15566 1000]
+	ElementLine [-10606 -15566 10606 -15566 1000]
+	ElementLine [10606 2500 10606 15566 1000]
+	ElementLine [10606 -15566 10606 -2500 1000]
+	ElementArc [10606 0 2500 2500 270 180 1000]
+
+	)
+
+Element["onsolder" "TSSOP16" "X1/U4" "" 384941 39500 6000 2000 3 100 "auto"]
+(
+	Pad[8956 9311 8956 13917 1299 1000 2299 "1B" "1" "onsolder,square,edge2"]
+	Pad[6397 9311 6397 13917 1299 1000 2299 "1A" "2" "onsolder,square,edge2"]
+	Pad[3838 9311 3838 13917 1299 1000 2299 "1Y" "3" "onsolder,square,edge2"]
+	Pad[1279 9311 1279 13917 1299 1000 2299 "ENABLE" "4" "onsolder,square,edge2"]
+	Pad[-1279 9311 -1279 13917 1299 1000 2299 "2Y" "5" "onsolder,square,edge2"]
+	Pad[-3838 9311 -3838 13917 1299 1000 2299 "2A" "6" "onsolder,square,edge2"]
+	Pad[-6397 9311 -6397 13917 1299 1000 2299 "2B" "7" "onsolder,square,edge2"]
+	Pad[-8956 9311 -8956 13917 1299 1000 2299 "GND" "8" "onsolder,square,edge2"]
+	Pad[-8956 -13917 -8956 -9311 1299 1000 2299 "3B" "9" "onsolder,square"]
+	Pad[-6397 -13917 -6397 -9311 1299 1000 2299 "3A" "10" "onsolder,square"]
+	Pad[-3838 -13917 -3838 -9311 1299 1000 2299 "3Y" "11" "onsolder,square"]
+	Pad[-1279 -13917 -1279 -9311 1299 1000 2299 "_ENABLE_" "12" "onsolder,square"]
+	Pad[1279 -13917 1279 -9311 1299 1000 2299 "4Y" "13" "onsolder,square"]
+	Pad[3838 -13917 3838 -9311 1299 1000 2299 "4A" "14" "onsolder,square"]
+	Pad[6397 -13917 6397 -9311 1299 1000 2299 "4B" "15" "onsolder,square"]
+	Pad[8956 -13917 8956 -9311 1299 1000 2299 "VCC" "16" "onsolder,square"]
+	ElementLine [-10606 15566 10606 15566 1000]
+	ElementLine [-10606 -15566 -10606 15566 1000]
+	ElementLine [-10606 -15566 10606 -15566 1000]
+	ElementLine [10606 2500 10606 15566 1000]
+	ElementLine [10606 -15566 10606 -2500 1000]
+	ElementArc [10606 0 2500 2500 270 180 1000]
+
+	)
+
+Element["hidename" "LQFP64_10" "U6" "" 277240 119171 5000 4905 3 100 ""]
+(
+	Pad[14763 -24134 14763 -20736 1102 3000 1402 "VBAT" "1" "square"]
+	Pad[12795 -24134 12795 -20736 1102 3000 1402 "PC13" "2" "square"]
+	Pad[10826 -24134 10826 -20736 1102 3000 1402 "PC14" "3" "square"]
+	Pad[8858 -24134 8858 -20736 1102 3000 1402 "PC15" "4" "square"]
+	Pad[6889 -24134 6889 -20736 1102 3000 1402 "OSC in" "5" "square"]
+	Pad[4921 -24134 4921 -20736 1102 3000 1402 "OSC out" "6" "square"]
+	Pad[2952 -24134 2952 -20736 1102 3000 1402 "_RST_" "7" "square"]
+	Pad[984 -24134 984 -20736 1102 3000 1402 "PC0" "8" "square"]
+	Pad[-985 -24134 -985 -20736 1102 3000 1402 "PC1" "9" "square"]
+	Pad[-2953 -24134 -2953 -20736 1102 3000 1402 "PC2" "10" "square"]
+	Pad[-4922 -24134 -4922 -20736 1102 3000 1402 "PC3" "11" "square"]
+	Pad[-6890 -24134 -6890 -20736 1102 3000 1402 "VSS analog" "12" "square"]
+	Pad[-8859 -24134 -8859 -20736 1102 3000 1402 "VDD analog" "13" "square"]
+	Pad[-10827 -24134 -10827 -20736 1102 3000 1402 "PA0" "14" "square"]
+	Pad[-12796 -24134 -12796 -20736 1102 3000 1402 "PA1" "15" "square"]
+	Pad[-14764 -24134 -14764 -20736 1102 3000 1402 "PA2" "16" "square"]
+	Pad[-24134 -14763 -20736 -14763 1102 3000 1402 "PA3" "17" "square,octagon"]
+	Pad[-24134 -12795 -20736 -12795 1102 3000 1402 "VSS 4" "18" "square,octagon"]
+	Pad[-24134 -10826 -20736 -10826 1102 3000 1402 "VDD 4" "19" "square,octagon"]
+	Pad[-24134 -8858 -20736 -8858 1102 3000 1402 "PA4" "20" "square,octagon"]
+	Pad[-24134 -6889 -20736 -6889 1102 3000 1402 "PA5" "21" "square,octagon"]
+	Pad[-24134 -4921 -20736 -4921 1102 3000 1402 "PA6" "22" "square,octagon"]
+	Pad[-24134 -2952 -20736 -2952 1102 3000 1402 "PA7" "23" "square,octagon"]
+	Pad[-24134 -984 -20736 -984 1102 3000 1402 "PC4" "24" "square,octagon"]
+	Pad[-24134 985 -20736 985 1102 3000 1402 "PC5" "25" "square,octagon"]
+	Pad[-24134 2953 -20736 2953 1102 3000 1402 "PB0" "26" "square,octagon"]
+	Pad[-24134 4922 -20736 4922 1102 3000 1402 "PB1" "27" "square,octagon"]
+	Pad[-24134 6890 -20736 6890 1102 3000 1402 "PB2" "28" "square,octagon"]
+	Pad[-24134 8859 -20736 8859 1102 3000 1402 "PB10" "29" "square,octagon"]
+	Pad[-24134 10827 -20736 10827 1102 3000 1402 "PB11" "30" "square,octagon"]
+	Pad[-24134 12796 -20736 12796 1102 3000 1402 "VCAP 1" "31" "square,octagon"]
+	Pad[-24134 14764 -20736 14764 1102 3000 1402 "VDD 1" "32" "square,octagon"]
+	Pad[-14763 20736 -14763 24134 1102 3000 1402 "PB12" "33" "square,edge2"]
+	Pad[-12795 20736 -12795 24134 1102 3000 1402 "PB13" "34" "square,edge2"]
+	Pad[-10826 20736 -10826 24134 1102 3000 1402 "PB14" "35" "square,edge2"]
+	Pad[-8858 20736 -8858 24134 1102 3000 1402 "PB15" "36" "square,edge2"]
+	Pad[-6889 20736 -6889 24134 1102 3000 1402 "PC6" "37" "square,edge2"]
+	Pad[-4921 20736 -4921 24134 1102 3000 1402 "PC7" "38" "square,edge2"]
+	Pad[-2952 20736 -2952 24134 1102 3000 1402 "PC8" "39" "square,edge2"]
+	Pad[-984 20736 -984 24134 1102 3000 1402 "PC9" "40" "square,edge2"]
+	Pad[985 20736 985 24134 1102 3000 1402 "PA8" "41" "square,edge2"]
+	Pad[2953 20736 2953 24134 1102 3000 1402 "PA9" "42" "square,edge2"]
+	Pad[4922 20736 4922 24134 1102 3000 1402 "PA10" "43" "square,edge2"]
+	Pad[6890 20736 6890 24134 1102 3000 1402 "PA11" "44" "square,edge2"]
+	Pad[8859 20736 8859 24134 1102 3000 1402 "PA12" "45" "square,edge2"]
+	Pad[10827 20736 10827 24134 1102 3000 1402 "PA13" "46" "square,edge2"]
+	Pad[12796 20736 12796 24134 1102 3000 1402 "VCAP 2" "47" "square,edge2"]
+	Pad[14764 20736 14764 24134 1102 3000 1402 "VDD 2" "48" "square,edge2"]
+	Pad[20736 14763 24134 14763 1102 3000 1402 "PA14" "49" "square,octagon,edge2"]
+	Pad[20736 12795 24134 12795 1102 3000 1402 "PA15" "50" "square,octagon,edge2"]
+	Pad[20736 10826 24134 10826 1102 3000 1402 "PC10" "51" "square,octagon,edge2"]
+	Pad[20736 8858 24134 8858 1102 3000 1402 "PC11" "52" "square,octagon,edge2"]
+	Pad[20736 6889 24134 6889 1102 3000 1402 "PC12" "53" "square,octagon,edge2"]
+	Pad[20736 4921 24134 4921 1102 3000 1402 "PD2" "54" "square,octagon,edge2"]
+	Pad[20736 2952 24134 2952 1102 3000 1402 "PB3" "55" "square,octagon,edge2"]
+	Pad[20736 984 24134 984 1102 3000 1402 "PB4" "56" "square,octagon,edge2"]
+	Pad[20736 -985 24134 -985 1102 3000 1402 "PB5" "57" "square,octagon,edge2"]
+	Pad[20736 -2953 24134 -2953 1102 3000 1402 "PB6" "58" "square,octagon,edge2"]
+	Pad[20736 -4922 24134 -4922 1102 3000 1402 "PB7" "59" "square,octagon,edge2"]
+	Pad[20736 -6890 24134 -6890 1102 3000 1402 "BOOT0" "60" "square,octagon,edge2"]
+	Pad[20736 -8859 24134 -8859 1102 3000 1402 "PB8" "61" "square,octagon,edge2"]
+	Pad[20736 -10827 24134 -10827 1102 3000 1402 "PB9" "62" "square,octagon,edge2"]
+	Pad[20736 -12796 24134 -12796 1102 3000 1402 "VSS 3" "63" "square,octagon,edge2"]
+	Pad[20736 -14764 24134 -14764 1102 3000 1402 "VDD 3" "64" "square,octagon,edge2"]
+	ElementLine [19285 -16385 19285 19285 800]
+	ElementLine [-19285 19285 19285 19285 800]
+	ElementLine [-19285 -19285 -19285 19285 800]
+	ElementLine [-19285 -19285 16385 -19285 800]
+	ElementLine [16385 -19285 19285 -16385 800]
+	ElementArc [16385 -16385 1000 1000 270 360 800]
+
+	)
+
+Element["lock" "beaglebone" "U8" "" 163299 127671 -112500 -118000 0 100 ""]
+(
+	Pin[-77500 92500 18300 1800 18900 12850 "bogus_442" "442" "lock,edge2"]
+	Pin[-77500 -97500 18300 1800 18900 12850 "bogus_542" "542" "lock,edge2"]
+	Pin[182500 80000 21000 1800 23000 19000 "bogus_642" "642" "lock,edge2"]
+	Pin[182500 -85000 18300 1800 18900 12850 "bogus_742" "742" "lock,edge2"]
+	Pin[-57500 87500 6600 2000 8600 4600 "(2) GND" "48" "lock,edge2,thermal(2X)"]
+	Pin[-57500 97500 6600 2000 8600 4600 "(1) GND" "47" "square,lock,edge2,thermal(2X)"]
+	Pin[-47500 87500 6600 2000 8600 4600 "(4) DC_3.3V" "50" "lock,edge2"]
+	Pin[-47500 97500 6600 2000 8600 4600 "(3) DC_3.3V" "49" "lock,edge2"]
+	Pin[-37500 87500 6600 2000 8600 4600 "(6) VDD_5V" "52" "lock,edge2,thermal(1X)"]
+	Pin[-37500 97500 6600 2000 8600 4600 "(5) VDD_5V" "51" "lock,edge2,thermal(1X)"]
+	Pin[-27500 87500 6600 2000 8600 4600 "(8) SYS_5V" "54" "lock,edge2"]
+	Pin[-27500 97500 6600 2000 8600 4600 "(7) SYS_5V" "53" "lock,edge2"]
+	Pin[-17500 87500 6600 2000 8600 4600 "(10) SYS_RESETn (A10)" "56" "lock,edge2"]
+	Pin[-17500 97500 6600 2000 8600 4600 "(9) PWR_BUT" "55" "lock,edge2"]
+	Pin[-7500 87500 6600 2000 8600 4600 "(12) GPIO1_28 (U18)" "58" "lock,edge2"]
+	Pin[-7500 97500 6600 2000 8600 4600 "(11) UART4_RXD (T17)" "57" "lock,edge2"]
+	Pin[2500 87500 6600 2000 8600 4600 "(14) EHRPWM1A (U14)" "60" "lock,edge2"]
+	Pin[2500 97500 6600 2000 8600 4600 "(13) UART4_TXD (U17)" "59" "lock,edge2"]
+	Pin[12500 87500 6600 2000 8600 4600 "(16) EHRPWM1B (T14)" "62" "lock,edge2"]
+	Pin[12500 97500 6600 2000 8600 4600 "(15) GPIO1_16 (R13)" "61" "lock,edge2"]
+	Pin[22500 87500 6600 2000 8600 4600 "(18) I2C1_SDA (B16)" "64" "lock,edge2"]
+	Pin[22500 97500 6600 2000 8600 4600 "(17) I2C1_SCL (A16)" "63" "lock,edge2"]
+	Pin[32500 87500 6600 2000 8600 4600 "(20) I2C2_SDA (D18)" "66" "lock,edge2"]
+	Pin[32500 97500 6600 2000 8600 4600 "(19) I2C2_SCL (D17)" "65" "lock,edge2"]
+	Pin[42500 87500 6600 2000 8600 4600 "(22) UART2_RXD (A17)" "68" "lock,edge2"]
+	Pin[42500 97500 6600 2000 8600 4600 "(21) UART2_TXD (B17)" "67" "lock,edge2"]
+	Pin[52500 87500 6600 2000 8600 4600 "(24) UART1_TXD (D15)" "70" "lock,edge2"]
+	Pin[52500 97500 6600 2000 8600 4600 "(23) GPIO1_17 (V14)" "69" "lock,edge2"]
+	Pin[62500 87500 6600 2000 8600 4600 "(26) UART1_RXD (D16)" "72" "lock,edge2"]
+	Pin[62500 97500 6600 2000 8600 4600 "(25) GPIO3_21 (A14)" "71" "lock,edge2"]
+	Pin[72500 87500 6600 2000 8600 4600 "(28) SPI1_CS0 (C12)" "74" "lock,edge2"]
+	Pin[72500 97500 6600 2000 8600 4600 "(27) GPIO3_19 (C13)" "73" "lock,edge2"]
+	Pin[82500 87500 6600 2000 8600 4600 "(30) SPI1_D1 (D12)" "76" "lock,edge2"]
+	Pin[82500 97500 6600 2000 8600 4600 "(29) SPI1_D0 (B13)" "75" "lock,edge2"]
+	Pin[92500 87500 6600 2000 8600 4600 "(32) VADC" "78" "lock,edge2"]
+	Pin[92500 97500 6600 2000 8600 4600 "(31) SPI1_SCLK (A13)" "77" "lock,edge2"]
+	Pin[102500 87500 6600 2000 8600 4600 "(34) AGND" "80" "lock,edge2"]
+	Pin[102500 97500 6600 2000 8600 4600 "(33) AIN4 (C8)" "79" "lock,edge2"]
+	Pin[112500 87500 6600 2000 8600 4600 "(36) AIN5 (B8)" "82" "lock,edge2"]
+	Pin[112500 97500 6600 2000 8600 4600 "(35) AIN6 (A8)" "81" "lock,edge2"]
+	Pin[122500 87500 6600 2000 8600 4600 "(38) AIN3 (A7)" "84" "lock,edge2"]
+	Pin[122500 97500 6600 2000 8600 4600 "(37) AIN2 (B7)" "83" "lock,edge2"]
+	Pin[132500 87500 6600 2000 8600 4600 "(40) AIN1 (C7)" "86" "lock,edge2"]
+	Pin[132500 97500 6600 2000 8600 4600 "(39) AIN0 (B6)" "85" "lock,edge2"]
+	Pin[142500 87500 6600 2000 8600 4600 "(42) GPIO0_7 (C18)" "88" "lock,edge2"]
+	Pin[142500 97500 6600 2000 8600 4600 "(41) CLKOUT2 (D14)" "87" "lock,edge2"]
+	Pin[152500 87500 6600 2000 8600 4600 "(44) GND" "90" "lock,edge2"]
+	Pin[152500 97500 6600 2000 8600 4600 "(43) GND" "89" "lock,edge2"]
+	Pin[162500 87500 6600 2000 8600 4600 "(46) GND" "92" "lock,edge2"]
+	Pin[162500 97500 6600 2000 8600 4600 "(45) GND" "91" "lock,edge2"]
+	Pin[-57500 -102500 6600 2000 8600 4600 "GND" "2" "lock,edge2,thermal(2X)"]
+	Pin[-57500 -92500 6600 2000 8600 4600 "GND" "1" "square,lock,edge2,thermal(2X)"]
+	Pin[-47500 -102500 6600 2000 8600 4600 "(T9) GPIO1_7" "4" "lock,edge2"]
+	Pin[-47500 -92500 6600 2000 8600 4600 "(R9) GPIO1_6" "3" "lock,edge2"]
+	Pin[-37500 -102500 6600 2000 8600 4600 "(T8) GPIO1_3" "6" "lock,edge2"]
+	Pin[-37500 -92500 6600 2000 8600 4600 "(R8) GPIO1_2" "5" "lock,edge2"]
+	Pin[-27500 -102500 6600 2000 8600 4600 "(T7) TIMER7" "8" "lock,edge2"]
+	Pin[-27500 -92500 6600 2000 8600 4600 "(R7) TIMER4" "7" "lock,edge2"]
+	Pin[-17500 -102500 6600 2000 8600 4600 "(U6) TIMER6" "10" "lock,edge2"]
+	Pin[-17500 -92500 6600 2000 8600 4600 "(T6) TIMER5" "9" "lock,edge2"]
+	Pin[-7500 -102500 6600 2000 8600 4600 "(T12) GPIO1_12" "12" "lock,edge2"]
+	Pin[-7500 -92500 6600 2000 8600 4600 "(R12) GPIO1_13" "11" "lock,edge2"]
+	Pin[2500 -102500 6600 2000 8600 4600 "(T11) GPIO0_26" "14" "lock,edge2"]
+	Pin[2500 -92500 6600 2000 8600 4600 "(T10) EHRPWM2B" "13" "lock,edge2"]
+	Pin[12500 -102500 6600 2000 8600 4600 "(V13) GPIO1_14" "16" "lock,edge2"]
+	Pin[12500 -92500 6600 2000 8600 4600 "(U13) GPIO1_15" "15" "lock,edge2"]
+	Pin[22500 -102500 6600 2000 8600 4600 "(V12) GPIO2_1" "18" "lock,edge2"]
+	Pin[22500 -92500 6600 2000 8600 4600 "(U12) GPIO0_27" "17" "lock,edge2"]
+	Pin[32500 -102500 6600 2000 8600 4600 "(V9) GPIO1_31" "20" "lock,edge2"]
+	Pin[32500 -92500 6600 2000 8600 4600 "(U10) EHRPWM2A" "19" "lock,edge2"]
+	Pin[42500 -102500 6600 2000 8600 4600 "(V8) GPIO1_5" "22" "lock,edge2"]
+	Pin[42500 -92500 6600 2000 8600 4600 "(U9) GPIO1_30" "21" "lock,edge2"]
+	Pin[52500 -102500 6600 2000 8600 4600 "(V7) GPIO1_1" "24" "lock,edge2"]
+	Pin[52500 -92500 6600 2000 8600 4600 "(U8) GPIO1_4" "23" "lock,edge2"]
+	Pin[62500 -102500 6600 2000 8600 4600 "(V6) GPIO1_29" "26" "lock,edge2"]
+	Pin[62500 -92500 6600 2000 8600 4600 "(U7) GPIO1_0" "25" "lock,edge2"]
+	Pin[72500 -102500 6600 2000 8600 4600 "(V5) GPIO2_24" "28" "lock,edge2"]
+	Pin[72500 -92500 6600 2000 8600 4600 "(U5) GPIO2_22" "27" "lock,edge2"]
+	Pin[82500 -102500 6600 2000 8600 4600 "(R6) GPIO2_25" "30" "lock,edge2"]
+	Pin[82500 -92500 6600 2000 8600 4600 "(R5) GPIO2_23" "29" "lock,edge2"]
+	Pin[92500 -102500 6600 2000 8600 4600 "(T5) UART5_RTSN" "32" "lock,edge2"]
+	Pin[92500 -92500 6600 2000 8600 4600 "(V4) UART5_CTSN" "31" "lock,edge2"]
+	Pin[102500 -102500 6600 2000 8600 4600 "(U4) UART3_RTSN" "34" "lock,edge2"]
+	Pin[102500 -92500 6600 2000 8600 4600 "(V3) UART4_RTSN" "33" "lock,edge2"]
+	Pin[112500 -102500 6600 2000 8600 4600 "(U3) UART3_CTSN" "36" "lock,edge2"]
+	Pin[112500 -92500 6600 2000 8600 4600 "(V2) UART4_CTSN" "35" "lock,edge2"]
+	Pin[122500 -102500 6600 2000 8600 4600 "(U2) UART5_RXD" "38" "lock,edge2"]
+	Pin[122500 -92500 6600 2000 8600 4600 "(U1) UART5_TXD" "37" "lock,edge2"]
+	Pin[132500 -102500 6600 2000 8600 4600 "(T4) GPIO2_13" "40" "lock,edge2"]
+	Pin[132500 -92500 6600 2000 8600 4600 "(T3) GPIO2_12" "39" "lock,edge2"]
+	Pin[142500 -102500 6600 2000 8600 4600 "(T2) GPIO2_11" "42" "lock,edge2"]
+	Pin[142500 -92500 6600 2000 8600 4600 "(T1) GPIO2_10" "41" "lock,edge2"]
+	Pin[152500 -102500 6600 2000 8600 4600 "(R4) GPIO2_9" "44" "lock,edge2"]
+	Pin[152500 -92500 6600 2000 8600 4600 "(R3) GPIO2_8" "43" "lock,edge2"]
+	Pin[162500 -102500 6600 2000 8600 4600 "(R2) GPIO2_7" "46" "lock,edge2"]
+	Pin[162500 -92500 6600 2000 8600 4600 "(R1) GPIO2_6" "45" "lock,edge2"]
+	Pin[32500 75000 6600 2000 8600 4600 "" "UART1" "square,edge2"]
+	Pin[42500 75000 6600 2000 8600 4600 "" "UART2" "edge2"]
+	Pin[52500 75000 6600 2000 8600 4600 "" "UART3" "edge2"]
+	Pin[62500 75000 6600 2000 8600 4600 "" "UART4" "edge2"]
+	Pin[72500 75000 6600 2000 8600 4600 "" "UART5" "edge2"]
+	Pin[152500 -65000 22000 1800 24000 20000 "bogus_842" "842" "edge2"]
+
+	)
+
+Element["" "22-23-2031" "CONN12" "" 85441 170000 12200 21000 2 100 ""]
+(
+	Pin[0 -10000 6500 3000 7100 4000 "1" "1" "square,thermal(0,2X)"]
+	Pin[0 0 6500 3000 7100 4000 "2" "2" ""]
+	Pin[0 10000 6500 3000 7100 4000 "3" "3" ""]
+	ElementLine [-12800 -15000 12200 -15000 1000]
+	ElementLine [-12800 15000 12200 15000 1000]
+	ElementLine [12200 -15000 12200 15000 1000]
+	ElementLine [5700 -15000 5700 15000 1000]
+	ElementLine [-12800 -5000 5700 -5000 1000]
+	ElementLine [-12800 5000 5700 5000 1000]
+	ElementLine [-12800 -15000 -12800 15000 1000]
+	ElementLine [-12800 -15000 -12800 -5000 1000]
+
+	)
+
+Element["" "0603" "X8/R4" "" 238500 258500 -3150 -3150 0 100 ""]
+(
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "1" "1" "square"]
+	Pad[2559 -492 2559 492 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0805" "D7" "" 95941 192000 -3150 3150 1 100 ""]
+(
+	Pad[-393 3543 393 3543 5118 2000 5718 "CATHODE" "1" "square"]
+	Pad[-393 -3543 393 -3543 5118 2000 5718 "ANODE" "2" "square"]
+	ElementLine [-2755 -393 -2755 393 800]
+	ElementLine [2755 -393 2755 393 800]
+
+	)
+
+Element["" "0805" "X16/D1" "" 397441 314000 3150 -3150 3 100 ""]
+(
+	Pad[-393 -3543 393 -3543 5118 2000 5718 "CATHODE" "1" "square"]
+	Pad[-393 3543 393 3543 5118 2000 5718 "ANODE" "2" "square"]
+	ElementLine [2755 -393 2755 393 800]
+	ElementLine [-2755 -393 -2755 393 800]
+
+	)
+
+Element["" "0603" "X16/R13" "" 397441 326559 -3150 3150 1 100 ""]
+(
+	Pad[-492 2559 492 2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0805" "X14/D1" "" 170441 155000 3150 -3150 3 100 ""]
+(
+	Pad[-393 -3543 393 -3543 5118 2000 5718 "CATHODE" "1" "square"]
+	Pad[-393 3543 393 3543 5118 2000 5718 "ANODE" "2" "square"]
+	ElementLine [2755 -393 2755 393 800]
+	ElementLine [-2755 -393 -2755 393 800]
+
+	)
+
+Element["" "0603" "X14/R13" "" 171441 165559 -3150 3150 1 100 ""]
+(
+	Pad[-492 2559 492 2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0603" "R17" "" 102941 186000 3150 -3150 3 100 ""]
+(
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 2559 492 2559 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "4-40_bolt" "B2" "" 353000 250000 0 0 0 100 ""]
+(
+	Pin[0 0 18300 1800 18900 12850 "the_hole" "1" ""]
+
+	)
+
+Element["" "0603" "R1" "" 263441 43500 3150 3150 2 100 ""]
+(
+	Pad[2559 -492 2559 492 2952 2000 3552 "1" "1" "square"]
+	Pad[-2559 -492 -2559 492 2952 2000 3552 "2" "2" "square"]
+
+	)
+
+Element["" "0805" "D1" "" 248898 43500 -3150 -3150 0 100 ""]
+(
+	Pad[-3543 -393 -3543 393 5118 2000 5718 "CATHODE" "1" "square"]
+	Pad[3543 -393 3543 393 5118 2000 5718 "ANODE" "2" "square"]
+	ElementLine [-393 -2755 393 -2755 800]
+	ElementLine [-393 2755 393 2755 800]
+
+	)
+Layer(1 "top")
+(
+	Line[448750 69700 376485 69700 1000 2000 "clearline,auto,lock"]
+	Line[371215 41738 371157 41738 1000 2000 "clearline"]
+	Line[387623 41738 371287 41738 1000 2000 "clearline"]
+	Line[389279 43395 387623 41738 1000 2000 "clearline"]
+	Line[389279 43995 389279 43395 1000 2000 "clearline"]
+	Line[379941 45000 370441 45000 1000 2000 "clearline"]
+	Line[384162 49221 379941 45000 1000 2000 "clearline"]
+	Line[384162 55083 384162 49221 1000 2000 "clearline"]
+	Line[387425 213631 385730 215327 1000 2000 "clearline"]
+	Line[387441 213631 387425 213631 1000 2000 "clearline"]
+	Line[387441 213631 387441 213631 1000 2000 "clearline"]
+	Line[387441 210038 387441 213631 1000 2000 "clearline"]
+	Line[387479 210000 387441 210038 1000 2000 "clearline"]
+	Line[386720 209241 387479 210000 1000 2000 "clearline"]
+	Line[386720 196311 386720 209241 1000 2000 "clearline"]
+	Line[384162 167218 377944 161000 1000 2000 "clearline"]
+	Line[384162 173083 384162 167218 1000 2000 "clearline"]
+	Line[381044 74000 387441 74000 1000 2000 "clearline"]
+	Line[379044 76000 381044 74000 1000 2000 "clearline"]
+	Line[389279 80614 389279 75838 1000 2000 "clearline"]
+	Line[387441 74000 389279 75838 1000 2000 "clearline"]
+	Line[391838 46603 393441 45000 1000 2000 "clearline"]
+	Line[391838 62000 391838 46603 1000 2000 "clearline"]
+	Line[381441 98000 376441 93000 1000 2000 "clearline"]
+	Line[379441 88000 370441 88000 1000 2000 "clearline"]
+	Line[381603 85838 379441 88000 1000 2000 "clearline"]
+	Line[381603 78311 381603 85838 1000 2000 "clearline"]
+	Line[389279 167175 391441 165013 1000 2000 "clearline"]
+	Line[389279 173083 389279 167175 1000 2000 "clearline"]
+	Line[445441 230891 448750 234200 1000 2000 "clearline"]
+	Line[445441 219000 445441 230891 1000 2000 "clearline"]
+	Line[443441 217000 445441 219000 1000 2000 "clearline"]
+	Line[394810 217000 443441 217000 1000 2000 "clearline"]
+	Line[391810 214000 394810 217000 1000 2000 "clearline"]
+	Line[399882 211559 395441 211559 1000 2000 "clearline"]
+	Line[400441 211000 399882 211559 1000 2000 "clearline"]
+	Line[400000 206441 395441 206441 1000 2000 "clearline"]
+	Line[400441 206000 400000 206441 1000 2000 "clearline"]
+	Line[391810 204425 391810 214000 1000 2000 "clearline"]
+	Line[391838 204397 391810 204425 1000 2000 "clearline"]
+	Line[389279 215838 389441 216000 1000 2000 "clearline"]
+	Line[389279 212838 389279 215838 1000 2000 "clearline"]
+	Line[389279 196311 389279 212904 1000 2000 "clearline"]
+	Line[378441 205000 376441 205000 1000 2000 "clearline"]
+	Line[381603 201838 378441 205000 1000 2000 "clearline"]
+	Line[381603 196311 381603 201838 1000 2000 "clearline"]
+	Line[458250 203200 412250 203200 1000 2000 "clearline,auto"]
+	Line[412250 195700 412250 203200 1000 2000 "clearline,auto"]
+	Line[412250 188700 412250 202700 1000 2000 "clearline,auto"]
+	Line[412250 188700 389117 188700 1000 2000 "clearline,auto"]
+	Line[401750 188700 376485 188700 1000 2000 "clearline,auto"]
+	Line[376485 188700 376485 196311 1000 2000 "clearline,auto"]
+	Line[391973 202691 391838 202691 1000 2000 "clearline,auto"]
+	Line[394441 200000 400441 206000 1000 2000 "clearline"]
+	Line[458441 146000 456641 146000 1000 2000 "clearline,auto"]
+	Line[456641 146000 456641 147800 1000 2000 "clearline,auto"]
+	Line[456641 147800 448750 147800 1000 2000 "clearline,auto"]
+	Line[448750 147800 448750 170750 1000 2000 "clearline,auto"]
+	Line[448750 170750 394397 170750 1000 2000 "clearline,auto"]
+	Line[394397 170750 394397 173083 1000 2000 "clearline,auto"]
+	Line[458441 175000 456641 175000 1000 2000 "clearline,auto"]
+	Line[456641 175000 456641 182000 1000 2000 "clearline,auto"]
+	Line[456641 182000 379044 182000 1000 2000 "clearline,auto"]
+	Line[379044 177689 379044 182000 1000 2000 "clearline,auto"]
+	Line[458441 203200 458441 205000 1000 2000 "clearline,auto"]
+	Line[458441 203200 458250 203200 1000 2000 "clearline,auto"]
+	Line[458250 203200 458250 203200 1000 2000 "clearline,auto"]
+	Line[376485 192000 376485 196311 1000 2000 "clearline,auto"]
+	Line[458441 234200 458441 236000 1000 2000 "clearline,auto"]
+	Line[458441 234200 458250 234200 1000 2000 "clearline,auto"]
+	Line[458250 234200 458250 234200 1000 2000 "clearline,auto"]
+	Line[458250 234200 448750 234200 1000 2000 "clearline,auto"]
+	Line[391838 200917 391838 204465 1000 2000 "clearline,auto"]
+	Line[386720 165350 387070 165000 1000 2000 "clearline"]
+	Line[386720 175386 386720 165350 1000 2000 "clearline"]
+	Line[376485 166044 375441 165000 1000 2000 "clearline"]
+	Line[376485 175386 376485 166044 1000 2000 "clearline"]
+	Line[379044 194000 389279 194000 1000 2000 "clearline"]
+	Line[379044 198614 379044 194000 1000 2000 "clearline"]
+	Line[389279 198614 389279 194000 1000 2000 "clearline"]
+	Line[381603 180000 391838 180000 1000 2000 "clearline"]
+	Line[381603 175386 381603 180000 1000 2000 "clearline"]
+	Line[391838 175386 391838 180000 1000 2000 "clearline"]
+	Line[384162 198614 384162 212000 1000 2000 "clearline"]
+	Line[448750 69700 448750 77225 1000 2000 "clearline,auto"]
+	Line[376485 69700 376485 74781 1000 2000 "clearline,auto"]
+	Line[458441 25000 456641 25000 1000 2000 "clearline,auto"]
+	Line[456641 25000 456641 26800 1000 2000 "clearline,auto"]
+	Line[456641 26800 448750 26800 1000 2000 "clearline,auto"]
+	Line[448750 26800 448750 50750 1000 2000 "clearline,auto"]
+	Line[448750 50750 394397 50750 1000 2000 "clearline,auto"]
+	Line[394397 50750 394397 55083 1000 2000 "clearline,auto"]
+	Line[458441 55000 456641 55000 1000 2000 "clearline,auto"]
+	Line[456641 55000 456641 64000 1000 2000 "clearline,auto"]
+	Line[456641 64000 379044 64000 1000 2000 "clearline,auto"]
+	Line[379044 59689 379044 64000 1000 2000 "clearline,auto"]
+	Line[458441 83200 458441 85000 1000 2000 "clearline,auto"]
+	Line[458441 83200 458250 83200 1000 2000 "clearline,auto"]
+	Line[458250 83200 458250 83200 1000 2000 "clearline,auto"]
+	Line[458250 83200 448750 83200 1000 2000 "clearline,auto"]
+	Line[448750 71250 448750 83200 1000 2000 "clearline,auto"]
+	Line[376485 71250 376485 78311 1000 2000 "clearline,auto"]
+	Line[458441 113200 458441 115000 1000 2000 "clearline,auto"]
+	Line[458441 113200 458250 113200 1000 2000 "clearline,auto"]
+	Line[458250 113200 458250 113200 1000 2000 "clearline,auto"]
+	Line[458250 113200 432250 113200 1000 2000 "clearline,auto"]
+	Line[432250 82566 432250 113200 1000 2000 "clearline,auto"]
+	Line[432250 82566 402250 82566 1000 2000 "clearline,auto"]
+	Line[402250 76161 402250 82566 1000 2000 "clearline,auto"]
+	Line[402250 76161 391838 76161 1000 2000 "clearline,auto"]
+	Line[391838 76161 391838 78311 1000 2000 "clearline,auto"]
+	Line[381603 62000 391838 62000 1000 2000 "clearline"]
+	Line[381603 57386 381603 62000 1000 2000 "clearline"]
+	Line[379044 80614 379044 76000 1000 2000 "clearline"]
+	Line[394397 84566 395831 86000 1000 2000 "clearline"]
+	Line[394397 80614 394397 84566 1000 2000 "clearline"]
+	Line[386720 46279 385941 45500 1000 2000 "clearline"]
+	Line[376485 52855 372441 48811 1000 2000 "clearline"]
+	Line[376485 57386 376485 52855 1000 2000 "clearline"]
+	Line[384162 80614 384162 94000 1000 2000 "clearline"]
+	Line[432000 327882 434882 325000 1000 2000 "clearline"]
+	Line[432000 330000 432000 327882 1000 2000 "clearline"]
+	Line[426882 328441 423441 325000 1000 2000 "clearline"]
+	Line[426882 330000 426882 328441 1000 2000 "clearline"]
+	Line[397497 152944 393135 152944 1000 2000 "clearline"]
+	Line[398441 152000 397497 152944 1000 2000 "clearline"]
+	Line[397615 147826 398441 147000 1000 2000 "clearline"]
+	Line[393135 147826 397615 147826 1000 2000 "clearline"]
+	Line[395831 86000 398441 86000 1000 2000 "clearline"]
+	Line[392949 88882 395831 86000 1000 2000 "clearline"]
+	Line[395441 94000 398441 91000 1000 2000 "clearline"]
+	Line[392949 94000 395441 94000 1000 2000 "clearline"]
+	Line[393441 34059 396441 34059 1000 2000 ""]
+	Line[396441 34059 397941 32559 1000 2000 ""]
+	Line[397441 27000 395441 27000 1000 2000 ""]
+	Line[395441 27000 393441 29000 1000 2000 ""]
+	Line[306581 126060 307716 124925 800 1600 "clearline"]
+	Line[297976 126060 306581 126060 800 1600 "clearline"]
+	Line[297976 128029 308992 128029 800 1600 "clearline"]
+	Line[305390 129997 308872 133478 800 1600 "clearline"]
+	Line[297976 129997 305390 129997 800 1600 "clearline"]
+	Line[291991 92228 298420 92228 800 1600 "clearline"]
+	Line[290035 94185 291991 92228 800 1600 "clearline"]
+	Line[290035 95037 290035 94185 800 1600 "clearline"]
+	Line[295931 100628 297971 98589 800 1600 "clearline"]
+	Line[289428 100628 295931 100628 800 1600 "clearline"]
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+		Connect("C16-2")
+		Connect("C17-2")
+		Connect("U1-15")
+		Connect("U1-16")
+		Connect("U3-1")
+		Connect("U4-1")
+		Connect("U8-51")
+		Connect("U8-52")
+		Connect("X8/C5-2")
+		Connect("X8/U2-11")
+		Connect("X9/C5-2")
+		Connect("X9/U2-11")
+		Connect("X14/C5-2")
+		Connect("X14/C6-2")
+		Connect("X14/R6-2")
+		Connect("X14/R13-1")
+		Connect("X14/U3-7")
+	)
+	Net("+12V" "(unknown)")
+	(
+		Connect("CONN12-2")
+		Connect("R17-1")
+		Connect("X14/C3-2")
+		Connect("X14/C4-2")
+		Connect("X14/R2-1")
+		Connect("X14/R3-1")
+		Connect("X14/U3-1")
+		Connect("X16/C3-2")
+		Connect("X16/C4-2")
+		Connect("X16/R2-1")
+		Connect("X16/R3-1")
+		Connect("X16/U3-1")
+	)
+	Net("DIFFA" "(unknown)")
+	(
+		Connect("R10-1")
+		Connect("R12-1")
+		Connect("X1/U4-2")
+		Connect("X1/U4-6")
+		Connect("X1/U4-10")
+		Connect("X1/U4-14")
+		Connect("X2/U4-2")
+		Connect("X2/U4-6")
+		Connect("X2/U4-10")
+		Connect("X2/U4-14")
+		Connect("X3/U4-2")
+		Connect("X3/U4-6")
+		Connect("X3/U4-10")
+		Connect("X3/U4-14")
+		Connect("X4/U4-2")
+		Connect("X4/U4-6")
+		Connect("X4/U4-10")
+		Connect("X4/U4-14")
+		Connect("X5/U4-2")
+		Connect("X5/U4-6")
+		Connect("X5/U4-10")
+		Connect("X5/U4-14")
+		Connect("X6/U4-2")
+		Connect("X6/U4-6")
+		Connect("X6/U4-10")
+		Connect("X6/U4-14")
+		Connect("X7/U4-2")
+		Connect("X7/U4-6")
+		Connect("X7/U4-10")
+		Connect("X7/U4-14")
+	)
+	Net("GND" "(unknown)")
+	(
+		Connect("C2-2")
+		Connect("C3-2")
+		Connect("C4-1")
+		Connect("C5-1")
+		Connect("C6-1")
+		Connect("C7-1")
+		Connect("C8-1")
+		Connect("C9-1")
+		Connect("C10-1")
+		Connect("C11-1")
+		Connect("C12-1")
+		Connect("C13-1")
+		Connect("C14-1")
+		Connect("C15-1")
+		Connect("C16-1")
+		Connect("C17-1")
+		Connect("C18-1")
+		Connect("C19-1")
+		Connect("C20-1")
+		Connect("C21-1")
+		Connect("C22-1")
+		Connect("C23-1")
+		Connect("C24-1")
+		Connect("C25-1")
+		Connect("C26-1")
+		Connect("C27-1")
+		Connect("C28-1")
+		Connect("C29-1")
+		Connect("C30-1")
+		Connect("C31-1")
+		Connect("C32-1")
+		Connect("CONN1-1")
+		Connect("CONN2-1")
+		Connect("CONN3-1")
+		Connect("CONN4-1")
+		Connect("CONN5-1")
+		Connect("CONN6-1")
+		Connect("CONN7-1")
+		Connect("CONN8-1")
+		Connect("CONN9-1")
+		Connect("CONN12-1")
+		Connect("D7-1")
+		Connect("U1-9")
+		Connect("U1-14")
+		Connect("U2-2")
+		Connect("U2-3")
+		Connect("U2-7")
+		Connect("U2-10")
+		Connect("U2-11")
+		Connect("U2-12")
+		Connect("U2-13")
+		Connect("U3-2")
+		Connect("U3-4")
+		Connect("U4-2")
+		Connect("U4-4")
+		Connect("U6-12")
+		Connect("U6-18")
+		Connect("U6-63")
+		Connect("U8-1")
+		Connect("U8-2")
+		Connect("U8-47")
+		Connect("U8-48")
+		Connect("U9-2")
+		Connect("U9-4")
+		Connect("X1/C1-1")
+		Connect("X1/U4-8")
+		Connect("X1/U4-12")
+		Connect("X2/C1-1")
+		Connect("X2/U4-8")
+		Connect("X2/U4-12")
+		Connect("X3/C1-1")
+		Connect("X3/U4-8")
+		Connect("X3/U4-12")
+		Connect("X4/C1-1")
+		Connect("X4/U4-8")
+		Connect("X4/U4-12")
+		Connect("X5/C1-1")
+		Connect("X5/U4-8")
+		Connect("X5/U4-12")
+		Connect("X6/C1-1")
+		Connect("X6/U4-8")
+		Connect("X6/U4-12")
+		Connect("X7/C1-1")
+		Connect("X7/U4-8")
+		Connect("X7/U4-12")
+		Connect("X8/C1-1")
+		Connect("X8/C2-1")
+		Connect("X8/C3-1")
+		Connect("X8/C4-1")
+		Connect("X8/C5-1")
+		Connect("X8/U2-4")
+		Connect("X9/C1-1")
+		Connect("X9/C2-1")
+		Connect("X9/C3-1")
+		Connect("X9/C4-1")
+		Connect("X9/C5-1")
+		Connect("X9/U2-4")
+		Connect("X14/C2-1")
+		Connect("X14/C3-1")
+		Connect("X14/C4-1")
+		Connect("X14/C6-1")
+		Connect("X14/D1-1")
+		Connect("X14/R4-1")
+		Connect("X14/R5-1")
+		Connect("X14/U3-4")
+		Connect("X14/U3-8")
+	)
+	Net("NRST" "(unknown)")
+	(
+		Connect("C15-2")
+		Connect("CONN1-4")
+		Connect("U6-7")
+		Connect("U8-9")
+	)
+	Net("SGND" "(unknown)")
+	(
+		Connect("R10-2")
+		Connect("X1/X2/C2-2")
+		Connect("X1/X2/CONN4-1")
+		Connect("X1/X4/C2-2")
+		Connect("X1/X4/CONN4-1")
+		Connect("X2/X2/C2-2")
+		Connect("X2/X2/CONN4-1")
+		Connect("X2/X4/C2-2")
+		Connect("X2/X4/CONN4-1")
+		Connect("X3/X2/C2-2")
+		Connect("X3/X2/CONN4-1")
+		Connect("X3/X4/C2-2")
+		Connect("X3/X4/CONN4-1")
+		Connect("X4/X2/C2-2")
+		Connect("X4/X2/CONN4-1")
+		Connect("X4/X4/C2-2")
+		Connect("X4/X4/CONN4-1")
+		Connect("X5/X1/C2-2")
+		Connect("X5/X1/CONN12-1")
+		Connect("X5/X2/C2-2")
+		Connect("X5/X2/CONN12-1")
+		Connect("X5/X3/C2-2")
+		Connect("X5/X3/CONN12-1")
+		Connect("X5/X4/C2-2")
+		Connect("X5/X4/CONN12-1")
+		Connect("X6/X1/C2-2")
+		Connect("X6/X1/CONN12-1")
+		Connect("X6/X2/C2-2")
+		Connect("X6/X2/CONN12-1")
+		Connect("X6/X3/C2-2")
+		Connect("X6/X3/CONN12-1")
+		Connect("X6/X4/C2-2")
+		Connect("X6/X4/CONN12-1")
+		Connect("X7/X1/C2-2")
+		Connect("X7/X1/CONN12-1")
+		Connect("X7/X2/C2-2")
+		Connect("X7/X2/CONN12-1")
+		Connect("X7/X3/C2-2")
+		Connect("X7/X3/CONN12-1")
+		Connect("X7/X4/C2-2")
+		Connect("X7/X4/CONN12-1")
+		Connect("X16/C2-1")
+		Connect("X16/C3-1")
+		Connect("X16/C4-1")
+		Connect("X16/C6-1")
+		Connect("X16/D1-1")
+		Connect("X16/R4-1")
+		Connect("X16/R5-1")
+		Connect("X16/U3-4")
+		Connect("X16/U3-8")
+	)
+	Net("SVCC" "(unknown)")
+	(
+		Connect("C18-2")
+		Connect("C19-2")
+		Connect("C20-2")
+		Connect("C21-2")
+		Connect("C22-2")
+		Connect("C23-2")
+		Connect("C24-2")
+		Connect("C25-2")
+		Connect("CONN2-2")
+		Connect("CONN3-2")
+		Connect("CONN4-2")
+		Connect("CONN5-2")
+		Connect("CONN6-2")
+		Connect("CONN7-2")
+		Connect("CONN8-2")
+		Connect("CONN9-2")
+		Connect("R12-2")
+		Connect("X1/X2/C2-1")
+		Connect("X1/X2/CONN4-2")
+		Connect("X1/X2/R9-2")
+		Connect("X1/X2/R10-2")
+		Connect("X1/X4/C2-1")
+		Connect("X1/X4/CONN4-2")
+		Connect("X1/X4/R9-2")
+		Connect("X1/X4/R10-2")
+		Connect("X2/X2/C2-1")
+		Connect("X2/X2/CONN4-2")
+		Connect("X2/X2/R9-2")
+		Connect("X2/X2/R10-2")
+		Connect("X2/X4/C2-1")
+		Connect("X2/X4/CONN4-2")
+		Connect("X2/X4/R9-2")
+		Connect("X2/X4/R10-2")
+		Connect("X3/X2/C2-1")
+		Connect("X3/X2/CONN4-2")
+		Connect("X3/X2/R9-2")
+		Connect("X3/X2/R10-2")
+		Connect("X3/X4/C2-1")
+		Connect("X3/X4/CONN4-2")
+		Connect("X3/X4/R9-2")
+		Connect("X3/X4/R10-2")
+		Connect("X4/X2/C2-1")
+		Connect("X4/X2/CONN4-2")
+		Connect("X4/X2/R9-2")
+		Connect("X4/X2/R10-2")
+		Connect("X4/X4/C2-1")
+		Connect("X4/X4/CONN4-2")
+		Connect("X4/X4/R9-2")
+		Connect("X4/X4/R10-2")
+		Connect("X5/X1/C2-1")
+		Connect("X5/X1/CONN12-2")
+		Connect("X5/X1/R7-2")
+		Connect("X5/X2/C2-1")
+		Connect("X5/X2/CONN12-2")
+		Connect("X5/X2/R7-2")
+		Connect("X5/X3/C2-1")
+		Connect("X5/X3/CONN12-2")
+		Connect("X5/X3/R7-2")
+		Connect("X5/X4/C2-1")
+		Connect("X5/X4/CONN12-2")
+		Connect("X5/X4/R7-2")
+		Connect("X6/X1/C2-1")
+		Connect("X6/X1/CONN12-2")
+		Connect("X6/X1/R7-2")
+		Connect("X6/X2/C2-1")
+		Connect("X6/X2/CONN12-2")
+		Connect("X6/X2/R7-2")
+		Connect("X6/X3/C2-1")
+		Connect("X6/X3/CONN12-2")
+		Connect("X6/X3/R7-2")
+		Connect("X6/X4/C2-1")
+		Connect("X6/X4/CONN12-2")
+		Connect("X6/X4/R7-2")
+		Connect("X7/X1/C2-1")
+		Connect("X7/X1/CONN12-2")
+		Connect("X7/X1/R7-2")
+		Connect("X7/X2/C2-1")
+		Connect("X7/X2/CONN12-2")
+		Connect("X7/X2/R7-2")
+		Connect("X7/X3/C2-1")
+		Connect("X7/X3/CONN12-2")
+		Connect("X7/X3/R7-2")
+		Connect("X7/X4/C2-1")
+		Connect("X7/X4/CONN12-2")
+		Connect("X7/X4/R7-2")
+		Connect("X16/C5-2")
+		Connect("X16/C6-2")
+		Connect("X16/R6-2")
+		Connect("X16/R13-1")
+		Connect("X16/U3-7")
+	)
+	Net("unnamed_net1" "(unknown)")
+	(
+		Connect("U6-14")
+		Connect("X2/U4-13")
+	)
+	Net("unnamed_net2" "(unknown)")
+	(
+		Connect("U6-15")
+		Connect("X2/U4-11")
+	)
+	Net("unnamed_net3" "(unknown)")
+	(
+		Connect("U6-16")
+		Connect("X2/U4-5")
+	)
+	Net("unnamed_net4" "(unknown)")
+	(
+		Connect("U6-17")
+		Connect("X2/U4-3")
+	)
+	Net("unnamed_net5" "(unknown)")
+	(
+		Connect("U2-4")
+		Connect("U6-20")
+	)
+	Net("unnamed_net6" "(unknown)")
+	(
+		Connect("U6-21")
+		Connect("X3/U4-5")
+	)
+	Net("unnamed_net7" "(unknown)")
+	(
+		Connect("U6-22")
+		Connect("X4/U4-13")
+	)
+	Net("unnamed_net8" "(unknown)")
+	(
+		Connect("U6-23")
+		Connect("X5/U4-11")
+	)
+	Net("unnamed_net9" "(unknown)")
+	(
+		Connect("U6-41")
+		Connect("X3/U4-13")
+	)
+	Net("unnamed_net10" "(unknown)")
+	(
+		Connect("U6-42")
+		Connect("U8-72")
+	)
+	Net("unnamed_net11" "(unknown)")
+	(
+		Connect("U6-43")
+		Connect("U8-70")
+	)
+	Net("unnamed_net12" "(unknown)")
+	(
+		Connect("U6-44")
+		Connect("X5/U4-5")
+	)
+	Net("unnamed_net13" "(unknown)")
+	(
+		Connect("U6-45")
+		Connect("X5/U4-3")
+	)
+	Net("unnamed_net14" "(unknown)")
+	(
+		Connect("CONN1-2")
+		Connect("U6-46")
+	)
+	Net("unnamed_net15" "(unknown)")
+	(
+		Connect("CONN1-3")
+		Connect("U6-49")
+	)
+	Net("unnamed_net16" "(unknown)")
+	(
+		Connect("U6-26")
+		Connect("X3/U4-11")
+	)
+	Net("unnamed_net17" "(unknown)")
+	(
+		Connect("D2-1")
+		Connect("U6-27")
+	)
+	Net("unnamed_net18" "(unknown)")
+	(
+		Connect("U6-28")
+		Connect("X5/U4-13")
+	)
+	Net("unnamed_net19" "(unknown)")
+	(
+		Connect("U6-55")
+		Connect("X3/U4-3")
+	)
+	Net("unnamed_net20" "(unknown)")
+	(
+		Connect("D5-1")
+		Connect("U6-56")
+	)
+	Net("unnamed_net21" "(unknown)")
+	(
+		Connect("U6-57")
+		Connect("X4/U4-11")
+	)
+	Net("unnamed_net22" "(unknown)")
+	(
+		Connect("U6-58")
+		Connect("X4/U4-5")
+	)
+	Net("unnamed_net23" "(unknown)")
+	(
+		Connect("U6-59")
+		Connect("X4/U4-3")
+	)
+	Net("unnamed_net24" "(unknown)")
+	(
+		Connect("U6-61")
+		Connect("X7/U4-13")
+	)
+	Net("unnamed_net25" "(unknown)")
+	(
+		Connect("U6-62")
+		Connect("X7/U4-11")
+	)
+	Net("unnamed_net26" "(unknown)")
+	(
+		Connect("U6-29")
+		Connect("X7/U4-5")
+	)
+	Net("unnamed_net27" "(unknown)")
+	(
+		Connect("D6-1")
+		Connect("U6-30")
+	)
+	Net("unnamed_net28" "(unknown)")
+	(
+		Connect("U1-10")
+		Connect("U6-33")
+	)
+	Net("unnamed_net29" "(unknown)")
+	(
+		Connect("U1-13")
+		Connect("U6-34")
+	)
+	Net("unnamed_net30" "(unknown)")
+	(
+		Connect("U1-12")
+		Connect("U6-35")
+	)
+	Net("unnamed_net31" "(unknown)")
+	(
+		Connect("U1-11")
+		Connect("U6-36")
+	)
+	Net("unnamed_net32" "(unknown)")
+	(
+		Connect("U6-8")
+		Connect("X1/U4-3")
+	)
+	Net("unnamed_net33" "(unknown)")
+	(
+		Connect("U6-9")
+		Connect("X1/U4-5")
+	)
+	Net("unnamed_net34" "(unknown)")
+	(
+		Connect("U6-10")
+		Connect("U8-8")
+	)
+	Net("unnamed_net35" "(unknown)")
+	(
+		Connect("D1-1")
+		Connect("U6-11")
+	)
+	Net("unnamed_net36" "(unknown)")
+	(
+		Connect("U6-24")
+		Connect("X6/U4-3")
+	)
+	Net("unnamed_net37" "(unknown)")
+	(
+		Connect("U6-25")
+		Connect("X6/U4-5")
+	)
+	Net("unnamed_net38" "(unknown)")
+	(
+		Connect("U6-37")
+		Connect("X1/U4-11")
+	)
+	Net("unnamed_net39" "(unknown)")
+	(
+		Connect("U6-38")
+		Connect("X1/U4-13")
+	)
+	Net("unnamed_net40" "(unknown)")
+	(
+		Connect("U6-39")
+		Connect("U8-56")
+	)
+	Net("unnamed_net41" "(unknown)")
+	(
+		Connect("U2-16")
+		Connect("U6-51")
+	)
+	Net("unnamed_net42" "(unknown)")
+	(
+		Connect("U2-5")
+		Connect("U6-52")
+	)
+	Net("unnamed_net43" "(unknown)")
+	(
+		Connect("U2-15")
+		Connect("U6-53")
+	)
+	Net("unnamed_net44" "(unknown)")
+	(
+		Connect("U6-2")
+		Connect("X6/U4-11")
+	)
+	Net("unnamed_net45" "(unknown)")
+	(
+		Connect("U6-3")
+		Connect("X6/U4-13")
+	)
+	Net("unnamed_net46" "(unknown)")
+	(
+		Connect("U6-4")
+		Connect("X7/U4-3")
+	)
+	Net("unnamed_net47" "(unknown)")
+	(
+		Connect("C4-2")
+		Connect("U6-5")
+		Connect("U9-1")
+	)
+	Net("unnamed_net48" "(unknown)")
+	(
+		Connect("C5-2")
+		Connect("U6-6")
+		Connect("U9-3")
+	)
+	Net("unnamed_net49" "(unknown)")
+	(
+		Connect("U6-60")
+		Connect("U8-7")
+	)
+	Net("unnamed_net50" "(unknown)")
+	(
+		Connect("C13-2")
+		Connect("U6-31")
+	)
+	Net("unnamed_net51" "(unknown)")
+	(
+		Connect("C14-2")
+		Connect("U6-47")
+	)
+	Net("unnamed_net253" "(unknown)")
+	(
+		Connect("C3-1")
+		Connect("U2-1")
+	)
+	Net("unnamed_net254" "(unknown)")
+	(
+		Connect("C2-1")
+		Connect("U2-14")
+	)
+	Net("unnamed_net255" "(unknown)")
+	(
+		Connect("C7-2")
+		Connect("C8-2")
+		Connect("C9-2")
+		Connect("L2-2")
+		Connect("U2-6")
+		Connect("U3-3")
+	)
+	Net("unnamed_net256" "(unknown)")
+	(
+		Connect("D4-1")
+		Connect("L2-1")
+		Connect("U2-8")
+	)
+	Net("unnamed_net257" "(unknown)")
+	(
+		Connect("C6-2")
+		Connect("D4-3")
+		Connect("U2-9")
+	)
+	Net("unnamed_net258" "(unknown)")
+	(
+		Connect("U1-1")
+		Connect("X9/C1-2")
+		Connect("X9/R1-2")
+	)
+	Net("unnamed_net259" "(unknown)")
+	(
+		Connect("U1-2")
+		Connect("X9/C2-2")
+		Connect("X9/R2-2")
+	)
+	Net("unnamed_net260" "(unknown)")
+	(
+		Connect("U1-3")
+		Connect("X9/C3-2")
+		Connect("X9/R3-2")
+	)
+	Net("unnamed_net261" "(unknown)")
+	(
+		Connect("U1-4")
+		Connect("X9/C4-2")
+		Connect("X9/R4-2")
+	)
+	Net("unnamed_net262" "(unknown)")
+	(
+		Connect("U1-5")
+		Connect("X8/C1-2")
+		Connect("X8/R1-2")
+	)
+	Net("unnamed_net263" "(unknown)")
+	(
+		Connect("U1-6")
+		Connect("X8/C2-2")
+		Connect("X8/R2-2")
+	)
+	Net("unnamed_net264" "(unknown)")
+	(
+		Connect("U1-7")
+		Connect("X8/C3-2")
+		Connect("X8/R3-2")
+	)
+	Net("unnamed_net265" "(unknown)")
+	(
+		Connect("U1-8")
+		Connect("X8/C4-2")
+		Connect("X8/R4-2")
+	)
+	Net("unnamed_net266" "(unknown)")
+	(
+		Connect("CONN5-3")
+		Connect("X8/U2-3")
+	)
+	Net("unnamed_net267" "(unknown)")
+	(
+		Connect("CONN4-3")
+		Connect("X8/U2-5")
+	)
+	Net("unnamed_net268" "(unknown)")
+	(
+		Connect("CONN3-3")
+		Connect("X8/U2-10")
+	)
+	Net("unnamed_net269" "(unknown)")
+	(
+		Connect("CONN2-3")
+		Connect("X8/U2-12")
+	)
+	Net("unnamed_net284" "(unknown)")
+	(
+		Connect("CONN9-3")
+		Connect("X9/U2-3")
+	)
+	Net("unnamed_net285" "(unknown)")
+	(
+		Connect("CONN8-3")
+		Connect("X9/U2-5")
+	)
+	Net("unnamed_net286" "(unknown)")
+	(
+		Connect("CONN7-3")
+		Connect("X9/U2-10")
+	)
+	Net("unnamed_net287" "(unknown)")
+	(
+		Connect("CONN6-3")
+		Connect("X9/U2-12")
+	)
+	Net("unnamed_net302" "(unknown)")
+	(
+		Connect("D2-2")
+		Connect("R13-2")
+	)
+	Net("unnamed_net303" "(unknown)")
+	(
+		Connect("D5-2")
+		Connect("R14-2")
+	)
+	Net("unnamed_net304" "(unknown)")
+	(
+		Connect("D6-2")
+		Connect("R15-2")
+	)
+	Net("unnamed_net305" "(unknown)")
+	(
+		Connect("D7-2")
+		Connect("R17-2")
+	)
+	Net("unnamed_net306" "(unknown)")
+	(
+		Connect("D1-2")
+		Connect("R1-2")
+	)
+	Net("X1/unnamed_net130" "(unknown)")
+	(
+		Connect("X1/U4-1")
+		Connect("X1/X4/R8-2")
+	)
+	Net("X1/unnamed_net131" "(unknown)")
+	(
+		Connect("X1/U4-7")
+		Connect("X1/X4/R6-2")
+	)
+	Net("X1/unnamed_net132" "(unknown)")
+	(
+		Connect("X1/U4-9")
+		Connect("X1/X2/R8-2")
+	)
+	Net("X1/unnamed_net133" "(unknown)")
+	(
+		Connect("X1/U4-15")
+		Connect("X1/X2/R6-2")
+	)
+	Net("X1/X2/unnamed_net142" "(unknown)")
+	(
+		Connect("X1/X2/CONN4-3")
+		Connect("X1/X2/R6-1")
+		Connect("X1/X2/R9-1")
+	)
+	Net("X1/X2/unnamed_net143" "(unknown)")
+	(
+		Connect("X1/X2/CONN4-4")
+		Connect("X1/X2/R8-1")
+		Connect("X1/X2/R10-1")
+	)
+	Net("X1/X4/unnamed_net148" "(unknown)")
+	(
+		Connect("X1/X4/CONN4-3")
+		Connect("X1/X4/R6-1")
+		Connect("X1/X4/R9-1")
+	)
+	Net("X1/X4/unnamed_net149" "(unknown)")
+	(
+		Connect("X1/X4/CONN4-4")
+		Connect("X1/X4/R8-1")
+		Connect("X1/X4/R10-1")
+	)
+	Net("X2/unnamed_net55" "(unknown)")
+	(
+		Connect("X2/U4-1")
+		Connect("X2/X4/R8-2")
+	)
+	Net("X2/unnamed_net56" "(unknown)")
+	(
+		Connect("X2/U4-7")
+		Connect("X2/X4/R6-2")
+	)
+	Net("X2/unnamed_net57" "(unknown)")
+	(
+		Connect("X2/U4-9")
+		Connect("X2/X2/R8-2")
+	)
+	Net("X2/unnamed_net58" "(unknown)")
+	(
+		Connect("X2/U4-15")
+		Connect("X2/X2/R6-2")
+	)
+	Net("X2/X2/unnamed_net67" "(unknown)")
+	(
+		Connect("X2/X2/CONN4-3")
+		Connect("X2/X2/R6-1")
+		Connect("X2/X2/R9-1")
+	)
+	Net("X2/X2/unnamed_net68" "(unknown)")
+	(
+		Connect("X2/X2/CONN4-4")
+		Connect("X2/X2/R8-1")
+		Connect("X2/X2/R10-1")
+	)
+	Net("X2/X4/unnamed_net73" "(unknown)")
+	(
+		Connect("X2/X4/CONN4-3")
+		Connect("X2/X4/R6-1")
+		Connect("X2/X4/R9-1")
+	)
+	Net("X2/X4/unnamed_net74" "(unknown)")
+	(
+		Connect("X2/X4/CONN4-4")
+		Connect("X2/X4/R8-1")
+		Connect("X2/X4/R10-1")
+	)
+	Net("X3/unnamed_net105" "(unknown)")
+	(
+		Connect("X3/U4-1")
+		Connect("X3/X4/R8-2")
+	)
+	Net("X3/unnamed_net106" "(unknown)")
+	(
+		Connect("X3/U4-7")
+		Connect("X3/X4/R6-2")
+	)
+	Net("X3/unnamed_net107" "(unknown)")
+	(
+		Connect("X3/U4-9")
+		Connect("X3/X2/R8-2")
+	)
+	Net("X3/unnamed_net108" "(unknown)")
+	(
+		Connect("X3/U4-15")
+		Connect("X3/X2/R6-2")
+	)
+	Net("X3/X2/unnamed_net117" "(unknown)")
+	(
+		Connect("X3/X2/CONN4-3")
+		Connect("X3/X2/R6-1")
+		Connect("X3/X2/R9-1")
+	)
+	Net("X3/X2/unnamed_net118" "(unknown)")
+	(
+		Connect("X3/X2/CONN4-4")
+		Connect("X3/X2/R8-1")
+		Connect("X3/X2/R10-1")
+	)
+	Net("X3/X4/unnamed_net123" "(unknown)")
+	(
+		Connect("X3/X4/CONN4-3")
+		Connect("X3/X4/R6-1")
+		Connect("X3/X4/R9-1")
+	)
+	Net("X3/X4/unnamed_net124" "(unknown)")
+	(
+		Connect("X3/X4/CONN4-4")
+		Connect("X3/X4/R8-1")
+		Connect("X3/X4/R10-1")
+	)
+	Net("X4/unnamed_net80" "(unknown)")
+	(
+		Connect("X4/U4-1")
+		Connect("X4/X4/R8-2")
+	)
+	Net("X4/unnamed_net81" "(unknown)")
+	(
+		Connect("X4/U4-7")
+		Connect("X4/X4/R6-2")
+	)
+	Net("X4/unnamed_net82" "(unknown)")
+	(
+		Connect("X4/U4-9")
+		Connect("X4/X2/R8-2")
+	)
+	Net("X4/unnamed_net83" "(unknown)")
+	(
+		Connect("X4/U4-15")
+		Connect("X4/X2/R6-2")
+	)
+	Net("X4/X2/unnamed_net92" "(unknown)")
+	(
+		Connect("X4/X2/CONN4-3")
+		Connect("X4/X2/R6-1")
+		Connect("X4/X2/R9-1")
+	)
+	Net("X4/X2/unnamed_net93" "(unknown)")
+	(
+		Connect("X4/X2/CONN4-4")
+		Connect("X4/X2/R8-1")
+		Connect("X4/X2/R10-1")
+	)
+	Net("X4/X4/unnamed_net98" "(unknown)")
+	(
+		Connect("X4/X4/CONN4-3")
+		Connect("X4/X4/R6-1")
+		Connect("X4/X4/R9-1")
+	)
+	Net("X4/X4/unnamed_net99" "(unknown)")
+	(
+		Connect("X4/X4/CONN4-4")
+		Connect("X4/X4/R8-1")
+		Connect("X4/X4/R10-1")
+	)
+	Net("X5/unnamed_net169" "(unknown)")
+	(
+		Connect("X5/U4-1")
+		Connect("X5/X1/R6-2")
+	)
+	Net("X5/unnamed_net170" "(unknown)")
+	(
+		Connect("X5/U4-7")
+		Connect("X5/X2/R6-2")
+	)
+	Net("X5/unnamed_net171" "(unknown)")
+	(
+		Connect("X5/U4-9")
+		Connect("X5/X3/R6-2")
+	)
+	Net("X5/unnamed_net172" "(unknown)")
+	(
+		Connect("X5/U4-15")
+		Connect("X5/X4/R6-2")
+	)
+	Net("X5/X1/unnamed_net186" "(unknown)")
+	(
+		Connect("X5/X1/CONN12-3")
+		Connect("X5/X1/R6-1")
+		Connect("X5/X1/R7-1")
+	)
+	Net("X5/X2/unnamed_net182" "(unknown)")
+	(
+		Connect("X5/X2/CONN12-3")
+		Connect("X5/X2/R6-1")
+		Connect("X5/X2/R7-1")
+	)
+	Net("X5/X3/unnamed_net190" "(unknown)")
+	(
+		Connect("X5/X3/CONN12-3")
+		Connect("X5/X3/R6-1")
+		Connect("X5/X3/R7-1")
+	)
+	Net("X5/X4/unnamed_net194" "(unknown)")
+	(
+		Connect("X5/X4/CONN12-3")
+		Connect("X5/X4/R6-1")
+		Connect("X5/X4/R7-1")
+	)
+	Net("X6/unnamed_net227" "(unknown)")
+	(
+		Connect("X6/U4-1")
+		Connect("X6/X1/R6-2")
+	)
+	Net("X6/unnamed_net228" "(unknown)")
+	(
+		Connect("X6/U4-7")
+		Connect("X6/X2/R6-2")
+	)
+	Net("X6/unnamed_net229" "(unknown)")
+	(
+		Connect("X6/U4-9")
+		Connect("X6/X3/R6-2")
+	)
+	Net("X6/unnamed_net230" "(unknown)")
+	(
+		Connect("X6/U4-15")
+		Connect("X6/X4/R6-2")
+	)
+	Net("X6/X1/unnamed_net244" "(unknown)")
+	(
+		Connect("X6/X1/CONN12-3")
+		Connect("X6/X1/R6-1")
+		Connect("X6/X1/R7-1")
+	)
+	Net("X6/X2/unnamed_net240" "(unknown)")
+	(
+		Connect("X6/X2/CONN12-3")
+		Connect("X6/X2/R6-1")
+		Connect("X6/X2/R7-1")
+	)
+	Net("X6/X3/unnamed_net248" "(unknown)")
+	(
+		Connect("X6/X3/CONN12-3")
+		Connect("X6/X3/R6-1")
+		Connect("X6/X3/R7-1")
+	)
+	Net("X6/X4/unnamed_net252" "(unknown)")
+	(
+		Connect("X6/X4/CONN12-3")
+		Connect("X6/X4/R6-1")
+		Connect("X6/X4/R7-1")
+	)
+	Net("X7/unnamed_net198" "(unknown)")
+	(
+		Connect("X7/U4-1")
+		Connect("X7/X1/R6-2")
+	)
+	Net("X7/unnamed_net199" "(unknown)")
+	(
+		Connect("X7/U4-7")
+		Connect("X7/X2/R6-2")
+	)
+	Net("X7/unnamed_net200" "(unknown)")
+	(
+		Connect("X7/U4-9")
+		Connect("X7/X3/R6-2")
+	)
+	Net("X7/unnamed_net201" "(unknown)")
+	(
+		Connect("X7/U4-15")
+		Connect("X7/X4/R6-2")
+	)
+	Net("X7/X1/unnamed_net215" "(unknown)")
+	(
+		Connect("X7/X1/CONN12-3")
+		Connect("X7/X1/R6-1")
+		Connect("X7/X1/R7-1")
+	)
+	Net("X7/X2/unnamed_net211" "(unknown)")
+	(
+		Connect("X7/X2/CONN12-3")
+		Connect("X7/X2/R6-1")
+		Connect("X7/X2/R7-1")
+	)
+	Net("X7/X3/unnamed_net219" "(unknown)")
+	(
+		Connect("X7/X3/CONN12-3")
+		Connect("X7/X3/R6-1")
+		Connect("X7/X3/R7-1")
+	)
+	Net("X7/X4/unnamed_net223" "(unknown)")
+	(
+		Connect("X7/X4/CONN12-3")
+		Connect("X7/X4/R6-1")
+		Connect("X7/X4/R7-1")
+	)
+	Net("X8/unnamed_net271" "(unknown)")
+	(
+		Connect("X8/R1-1")
+		Connect("X8/U2-1")
+		Connect("X8/U2-2")
+	)
+	Net("X8/unnamed_net275" "(unknown)")
+	(
+		Connect("X8/R2-1")
+		Connect("X8/U2-6")
+		Connect("X8/U2-7")
+	)
+	Net("X8/unnamed_net277" "(unknown)")
+	(
+		Connect("X8/R3-1")
+		Connect("X8/U2-8")
+		Connect("X8/U2-9")
+	)
+	Net("X8/unnamed_net279" "(unknown)")
+	(
+		Connect("X8/R4-1")
+		Connect("X8/U2-13")
+		Connect("X8/U2-14")
+	)
+	Net("X9/unnamed_net289" "(unknown)")
+	(
+		Connect("X9/R1-1")
+		Connect("X9/U2-1")
+		Connect("X9/U2-2")
+	)
+	Net("X9/unnamed_net293" "(unknown)")
+	(
+		Connect("X9/R2-1")
+		Connect("X9/U2-6")
+		Connect("X9/U2-7")
+	)
+	Net("X9/unnamed_net295" "(unknown)")
+	(
+		Connect("X9/R3-1")
+		Connect("X9/U2-8")
+		Connect("X9/U2-9")
+	)
+	Net("X9/unnamed_net297" "(unknown)")
+	(
+		Connect("X9/R4-1")
+		Connect("X9/U2-13")
+		Connect("X9/U2-14")
+	)
+	Net("X14/unnamed_net153" "(unknown)")
+	(
+		Connect("X14/R3-2")
+		Connect("X14/U3-2")
+	)
+	Net("X14/unnamed_net154" "(unknown)")
+	(
+		Connect("X14/R2-2")
+		Connect("X14/R4-2")
+		Connect("X14/U3-3")
+	)
+	Net("X14/unnamed_net155" "(unknown)")
+	(
+		Connect("X14/C2-2")
+		Connect("X14/U3-5")
+	)
+	Net("X14/unnamed_net156" "(unknown)")
+	(
+		Connect("X14/C5-1")
+		Connect("X14/R5-2")
+		Connect("X14/R6-1")
+		Connect("X14/U3-6")
+	)
+	Net("X14/unnamed_net158" "(unknown)")
+	(
+		Connect("X14/D1-2")
+		Connect("X14/R13-2")
+	)
+	Net("X16/unnamed_net160" "(unknown)")
+	(
+		Connect("X16/R3-2")
+		Connect("X16/U3-2")
+	)
+	Net("X16/unnamed_net161" "(unknown)")
+	(
+		Connect("X16/R2-2")
+		Connect("X16/R4-2")
+		Connect("X16/U3-3")
+	)
+	Net("X16/unnamed_net162" "(unknown)")
+	(
+		Connect("X16/C2-2")
+		Connect("X16/U3-5")
+	)
+	Net("X16/unnamed_net163" "(unknown)")
+	(
+		Connect("X16/C5-1")
+		Connect("X16/R5-2")
+		Connect("X16/R6-1")
+		Connect("X16/U3-6")
+	)
+	Net("X16/unnamed_net165" "(unknown)")
+	(
+		Connect("X16/D1-2")
+		Connect("X16/R13-2")
+	)
+)

diff --git a/bbb_cape/schematic/check_refdes.sh b/bbb_cape/schematic/check_refdes.sh
new file mode 100755
index 0000000..1ebede1
--- /dev/null
+++ b/bbb_cape/schematic/check_refdes.sh

@@ -0,0 +1,15 @@
+#!/bin/bash
+
+if [[ $# -lt 1 ]]; then
+	find $(dirname $0) \( -name '*.sch' -or -name '*.sym' \) -exec $0 {} \;
+	exit $?
+fi
+
+FILE=$1
+
+DUPLICATED=$(grep -F 'refdes=' "${FILE}" | sort | uniq -d)
+
+if [[ -n ${DUPLICATED} ]]; then
+	echo Duplicated lines in ${FILE}:
+	echo ${DUPLICATED}
+fi

diff --git a/bbb_cape/schematic/copy_values.rb b/bbb_cape/schematic/copy_values.rb
new file mode 100755
index 0000000..62d0d05
--- /dev/null
+++ b/bbb_cape/schematic/copy_values.rb

@@ -0,0 +1,37 @@
+#!/usr/bin/env ruby
+
+system 'rm temp.*'
+system 'gsch2pcb cape.gsch2pcb -o temp > /dev/null 2>&1'
+
+$elements = {}
+
+ElementRegex = /[ \t]*(Element[\[(].+) "(.*)" "(.*)" "(.*)" (.*)/
+
+File.open('temp.pcb') do |f|
+	f.readlines.each do |temp_element|
+		match = ElementRegex.match(temp_element)
+		if match
+			refdes = match[3]
+			value = match[4]
+			$elements[refdes] = value
+		end
+	end
+end
+
+File.open('cape.pcb') do |f|
+	$start_lines = f.readlines
+end
+
+File.open('cape.pcb', 'w') do |f|
+	$start_lines.each do |line|
+		match = ElementRegex.match(line)
+		if match
+			footprint = match[2]
+			refdes = match[3]
+			value = match[4]
+			f.puts "#{match[1]} \"#{footprint}\" \"#{refdes}\" \"#{$elements[refdes] || value}\" #{match[5]}"
+		else
+			f.puts line
+		end
+	end
+end

diff --git a/bbb_cape/schematic/digital input.sch b/bbb_cape/schematic/digital input.sch
new file mode 100644
index 0000000..f6a2458
--- /dev/null
+++ b/bbb_cape/schematic/digital input.sch

@@ -0,0 +1,87 @@
+v 20110115 2
+C 46000 48000 1 180 0 in-1.sym
+{
+T 46000 47700 5 10 0 0 180 0 1
+device=INPUT
+T 45900 48100 5 10 1 1 180 0 1
+refdes=SGND
+}
+C 46000 46600 1 180 0 in-1.sym
+{
+T 46000 46300 5 10 0 0 180 0 1
+device=INPUT
+T 45900 46700 5 10 1 1 180 0 1
+refdes=SVCC
+}
+C 45400 45400 1 0 0 out-1.sym
+{
+T 45400 45700 5 10 0 0 0 0 1
+device=OUTPUT
+T 45400 45600 5 10 1 1 0 0 1
+refdes=OUT
+}
+N 44000 46500 45400 46500 4
+N 45400 47900 44100 47900 4
+N 44100 47900 44100 46800 4
+C 44200 45400 1 0 0 resistor-1.sym
+{
+T 44500 45800 5 10 0 0 0 0 1
+device=RESISTOR
+T 44400 45700 5 10 1 1 0 0 1
+refdes=R6
+T 44200 45200 5 10 1 1 0 0 1
+value=500 ohms
+T 44200 45400 5 10 0 0 0 0 1
+footprint=0603
+T 44200 45400 5 10 0 1 0 0 1
+pn=ERJ-3EKF4990V
+}
+N 45100 45500 45400 45500 4
+C 42300 46000 1 0 0 connector3-1.sym
+{
+T 44100 46900 5 10 0 0 0 0 1
+device=CONNECTOR_3
+T 42300 47100 5 10 1 1 0 0 1
+refdes=CONN12
+T 42300 46000 5 10 0 0 0 0 1
+footprint=22-23-2031
+T 42300 46000 5 10 0 1 0 0 1
+pn=22-23-2031
+}
+N 44200 45500 44100 45500 4
+N 44100 45500 44100 46200 4
+N 44100 46200 44000 46200 4
+C 44900 46800 1 90 0 capacitor-1.sym
+{
+T 44200 47000 5 10 0 0 90 0 1
+device=CAPACITOR
+T 44400 47000 5 10 1 1 90 0 1
+refdes=C2
+T 44000 47000 5 10 0 0 90 0 1
+symversion=0.1
+T 45100 46800 5 10 1 1 90 0 1
+value=0.1 uF
+T 44900 46800 5 10 0 0 0 0 1
+footprint=0603
+T 44900 46800 5 10 0 0 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+N 44700 47700 44700 47900 4
+N 44700 46800 44700 46500 4
+N 44000 46800 44100 46800 4
+C 44300 46000 1 0 0 resistor-1.sym
+{
+T 44600 46400 5 10 0 0 0 0 1
+device=RESISTOR
+T 44500 46200 5 10 1 1 0 0 1
+refdes=R7
+T 44300 45900 5 10 1 1 0 0 1
+value=10 kohms
+T 44300 46000 5 10 0 0 0 0 1
+footprint=0603
+T 44300 46000 5 10 0 1 0 0 1
+pn=SG73S1JTTD103J
+}
+N 44300 46100 44100 46100 4
+N 45200 46100 45300 46100 4
+N 45300 46100 45300 46500 4

diff --git a/bbb_cape/schematic/digital inputs x4.sch b/bbb_cape/schematic/digital inputs x4.sch
new file mode 100644
index 0000000..11f3308
--- /dev/null
+++ b/bbb_cape/schematic/digital inputs x4.sch

@@ -0,0 +1,168 @@
+v 20110115 2
+C 37300 45500 1 90 0 in-1.sym
+{
+T 37000 45500 5 10 0 0 90 0 1
+device=INPUT
+T 37000 45500 5 10 1 1 90 0 1
+refdes=SGND
+}
+C 38000 45500 1 90 0 in-1.sym
+{
+T 37700 45500 5 10 0 0 90 0 1
+device=INPUT
+T 37700 45500 5 10 1 1 90 0 1
+refdes=SVCC
+}
+C 43800 48900 1 180 0 AM26LV32E-1.sym
+{
+T 44400 46700 5 10 0 1 180 0 1
+device=AM26LV32E
+T 45200 47200 5 10 0 1 180 0 1
+footprint=TSSOP16
+T 42500 46300 5 10 1 1 180 0 1
+refdes=U4
+T 43800 48900 5 10 0 0 0 0 1
+pn=AM26LV32EIPWR
+}
+N 37900 46100 37900 49600 4
+N 37900 46300 38100 46300 4
+N 37900 47400 38100 47400 4
+N 37200 46100 37200 49900 4
+N 38100 46600 37200 46600 4
+N 38100 47700 37200 47700 4
+C 46000 48200 1 180 0 in-1.sym
+{
+T 46000 47900 5 10 0 0 180 0 1
+device=INPUT
+T 46000 47900 5 10 1 1 180 0 1
+refdes=DGND
+}
+C 46000 49400 1 180 0 in-1.sym
+{
+T 46000 49100 5 10 0 0 180 0 1
+device=INPUT
+T 46000 49100 5 10 1 1 180 0 1
+refdes=DVCC
+}
+C 44200 46100 1 270 0 out-1.sym
+{
+T 44500 46100 5 10 0 0 270 0 1
+device=OUTPUT
+T 44500 46100 5 10 1 1 270 0 1
+refdes=OUT0
+}
+C 44700 46100 1 270 0 out-1.sym
+{
+T 45000 46100 5 10 0 0 270 0 1
+device=OUTPUT
+T 45000 46100 5 10 1 1 270 0 1
+refdes=OUT1
+}
+C 45200 46100 1 270 0 out-1.sym
+{
+T 45500 46100 5 10 0 0 270 0 1
+device=OUTPUT
+T 45500 46100 5 10 1 1 270 0 1
+refdes=OUT2
+}
+C 45700 46100 1 270 0 out-1.sym
+{
+T 46000 46100 5 10 0 0 270 0 1
+device=OUTPUT
+T 46000 46100 5 10 1 1 270 0 1
+refdes=OUT3
+}
+N 43800 46600 44300 46600 4
+N 44300 46600 44300 46100 4
+N 43800 48100 45400 48100 4
+N 44600 48100 44600 48400 4
+N 44600 48400 43800 48400 4
+N 43800 47800 44100 47800 4
+N 44100 47800 44100 49300 4
+N 43800 46900 44800 46900 4
+N 44800 46900 44800 46100 4
+N 43800 47200 45300 47200 4
+N 45300 47200 45300 46100 4
+N 43800 47500 45800 47500 4
+N 45800 47500 45800 46100 4
+C 41500 50300 1 270 0 in-1.sym
+{
+T 41800 50300 5 10 0 0 270 0 1
+device=INPUT
+T 41800 50300 5 10 1 1 270 0 1
+refdes=DIFFA
+}
+N 41600 49700 41600 46600 4
+N 41600 46600 42000 46600 4
+N 42000 47200 41600 47200 4
+N 42000 47800 41600 47800 4
+N 42000 48400 41600 48400 4
+C 38100 47200 1 0 0 digital-input-1.sym
+{
+T 40600 48100 5 10 0 1 0 0 1
+device=encoder-input
+T 39800 48000 5 10 1 1 0 0 1
+refdes=X2
+T 38100 47200 5 10 0 0 0 0 1
+source=digital input.sch
+}
+C 38100 46100 1 0 0 digital-input-1.sym
+{
+T 40600 47000 5 10 0 1 0 0 1
+device=encoder-input
+T 39800 46900 5 10 1 1 0 0 1
+refdes=X1
+T 38100 46100 5 10 0 0 0 0 1
+source=digital input.sch
+}
+N 40400 46400 41000 46400 4
+N 41000 46400 41000 46900 4
+N 41000 46900 42000 46900 4
+N 40400 47500 42000 47500 4
+C 38100 48300 1 0 0 digital-input-1.sym
+{
+T 40600 49200 5 10 0 1 0 0 1
+device=encoder-input
+T 39800 49100 5 10 1 1 0 0 1
+refdes=X3
+T 38100 48300 5 10 0 0 0 0 1
+source=digital input.sch
+}
+C 38100 49400 1 0 0 digital-input-1.sym
+{
+T 40600 50300 5 10 0 1 0 0 1
+device=encoder-input
+T 39800 50200 5 10 1 1 0 0 1
+refdes=X4
+T 38100 49400 5 10 0 0 0 0 1
+source=digital input.sch
+}
+N 41000 48100 42000 48100 4
+N 42000 48700 41300 48700 4
+N 41300 48700 41300 49700 4
+N 41300 49700 40400 49700 4
+N 38100 48500 37900 48500 4
+N 38100 49600 37900 49600 4
+N 38100 48800 37200 48800 4
+N 38100 49900 37200 49900 4
+N 40400 48600 41000 48600 4
+N 41000 48600 41000 48100 4
+C 45300 48200 1 90 0 capacitor-1.sym
+{
+T 44600 48400 5 10 0 0 90 0 1
+device=CAPACITOR
+T 44800 48400 5 10 1 1 90 0 1
+refdes=C1
+T 44400 48400 5 10 0 0 90 0 1
+symversion=0.1
+T 45300 48200 5 10 0 0 90 0 1
+footprint=0603
+T 45500 48400 5 10 1 1 90 0 1
+value=0.1 uF
+T 45300 48200 5 10 0 0 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+N 45100 48200 45100 48100 4
+N 44100 49300 45400 49300 4
+N 45100 49100 45100 49300 4
+N 44100 48700 43800 48700 4

diff --git a/bbb_cape/schematic/encoder input.sch b/bbb_cape/schematic/encoder input.sch
new file mode 100644
index 0000000..04f5214
--- /dev/null
+++ b/bbb_cape/schematic/encoder input.sch

@@ -0,0 +1,126 @@
+v 20110115 2
+C 46700 47900 1 180 0 in-1.sym
+{
+T 46700 47600 5 10 0 0 180 0 1
+device=INPUT
+T 46600 48000 5 10 1 1 180 0 1
+refdes=SGND
+}
+C 46700 46600 1 180 0 in-1.sym
+{
+T 46700 46300 5 10 0 0 180 0 1
+device=INPUT
+T 46600 46700 5 10 1 1 180 0 1
+refdes=SVCC
+}
+C 42300 45700 1 0 0 connector4-1.sym
+{
+T 44100 46600 5 10 0 0 0 0 1
+device=CONNECTOR_4
+T 42300 47100 5 10 1 1 0 0 1
+refdes=CONN4
+T 42300 45700 5 10 0 0 0 0 1
+footprint=22-23-2041
+T 42300 45700 5 10 0 1 0 0 1
+pn=22-23-2041
+}
+C 46100 45600 1 0 0 out-1.sym
+{
+T 46100 45900 5 10 0 0 0 0 1
+device=OUTPUT
+T 46100 45800 5 10 1 1 0 0 1
+refdes=CH1
+}
+C 46100 44600 1 0 0 out-1.sym
+{
+T 46100 44900 5 10 0 0 0 0 1
+device=OUTPUT
+T 46100 44800 5 10 1 1 0 0 1
+refdes=CH2
+}
+N 44000 46500 46100 46500 4
+N 46100 47800 44100 47800 4
+N 44100 46800 44100 47800 4
+C 44900 45600 1 0 0 resistor-1.sym
+{
+T 45200 46000 5 10 0 0 0 0 1
+device=RESISTOR
+T 45100 45800 5 10 1 1 0 0 1
+refdes=R6
+T 44900 45500 5 10 1 1 0 0 1
+value=500 ohms
+T 44900 45600 5 10 0 0 0 0 1
+footprint=0603
+T 44900 45600 5 10 0 1 0 0 1
+pn=ERJ-3EKF4990V
+}
+C 44900 44600 1 0 0 resistor-1.sym
+{
+T 45200 45000 5 10 0 0 0 0 1
+device=RESISTOR
+T 45100 44800 5 10 1 1 0 0 1
+refdes=R8
+T 44900 44500 5 10 1 1 0 0 1
+value=500 ohms
+T 44900 44600 5 10 0 0 0 0 1
+footprint=0603
+T 44900 44600 5 10 0 1 0 0 1
+pn=ERJ-3EKF4990V
+}
+N 44000 45900 44100 45900 4
+N 44100 44700 44100 45900 4
+N 45800 44700 46100 44700 4
+N 45800 45700 46100 45700 4
+C 44900 46700 1 90 0 capacitor-1.sym
+{
+T 44200 46900 5 10 0 0 90 0 1
+device=CAPACITOR
+T 44400 46900 5 10 1 1 90 0 1
+refdes=C2
+T 44000 46900 5 10 0 0 90 0 1
+symversion=0.1
+T 45100 46700 5 10 1 1 90 0 1
+value=0.1 uF
+T 44900 46700 5 10 0 0 0 0 1
+footprint=0603
+T 44900 46700 5 10 0 0 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+N 44000 46800 44100 46800 4
+N 44900 44700 44100 44700 4
+N 44700 47800 44700 47600 4
+N 44700 46700 44700 46500 4
+C 44900 46100 1 0 0 resistor-1.sym
+{
+T 45200 46500 5 10 0 0 0 0 1
+device=RESISTOR
+T 45100 46300 5 10 1 1 0 0 1
+refdes=R9
+T 44900 46000 5 10 1 1 0 0 1
+value=10 kohms
+T 44900 46100 5 10 0 0 0 0 1
+footprint=0603
+T 44900 46100 5 10 0 1 0 0 1
+pn=SG73S1JTTD103J
+}
+C 44900 45100 1 0 0 resistor-1.sym
+{
+T 45200 45500 5 10 0 0 0 0 1
+device=RESISTOR
+T 45100 45300 5 10 1 1 0 0 1
+refdes=R10
+T 44900 45000 5 10 1 1 0 0 1
+value=10 kohms
+T 44900 45100 5 10 0 0 0 0 1
+footprint=0603
+T 44900 45100 5 10 0 1 0 0 1
+pn=SG73S1JTTD103J
+}
+N 44000 46200 44900 46200 4
+N 44600 46200 44600 45700 4
+N 44600 45700 44900 45700 4
+N 44900 45200 44100 45200 4
+N 45800 46200 45900 46200 4
+N 45900 46200 45900 46500 4
+N 45900 46500 45900 45200 4
+N 45900 45200 45800 45200 4

diff --git a/bbb_cape/schematic/encoder inputs x2.sch b/bbb_cape/schematic/encoder inputs x2.sch
new file mode 100644
index 0000000..f2d82d0
--- /dev/null
+++ b/bbb_cape/schematic/encoder inputs x2.sch

@@ -0,0 +1,145 @@
+v 20110115 2
+C 37300 45500 1 90 0 in-1.sym
+{
+T 37000 45500 5 10 0 0 90 0 1
+device=INPUT
+T 37000 45500 5 10 1 1 90 0 1
+refdes=SGND
+}
+C 38000 45500 1 90 0 in-1.sym
+{
+T 37700 45500 5 10 0 0 90 0 1
+device=INPUT
+T 37700 45500 5 10 1 1 90 0 1
+refdes=SVCC
+}
+C 43800 48900 1 180 0 AM26LV32E-1.sym
+{
+T 44400 46700 5 10 0 1 180 0 1
+device=AM26LV32E
+T 45200 47200 5 10 0 1 180 0 1
+footprint=TSSOP16
+T 42500 46300 5 10 1 1 180 0 1
+refdes=U4
+T 43800 48900 5 10 0 1 0 0 1
+pn=AM26LV32EIPWR
+}
+C 38100 47800 1 0 0 encoder-input-1.sym
+{
+T 40600 49000 5 10 0 1 0 0 1
+device=encoder-input
+T 39800 48600 5 10 1 1 0 0 1
+refdes=X2
+}
+C 38100 46400 1 0 0 encoder-input-1.sym
+{
+T 40600 47600 5 10 0 1 0 0 1
+device=encoder-input
+T 39800 47200 5 10 1 1 0 0 1
+refdes=X4
+}
+N 37900 46100 37900 48000 4
+N 37900 46600 38100 46600 4
+N 37900 48000 38100 48000 4
+N 37200 46100 37200 48300 4
+N 38100 46900 37200 46900 4
+N 38100 48300 37200 48300 4
+N 40400 48300 40900 48300 4
+N 40900 48300 40900 48700 4
+N 40900 48700 42000 48700 4
+N 40400 48000 41200 48000 4
+N 41200 48000 41200 48100 4
+N 41200 48100 42000 48100 4
+N 40400 46900 40900 46900 4
+N 40900 46900 40900 47500 4
+N 40900 47500 42000 47500 4
+N 40400 46600 41200 46600 4
+N 41200 46600 41200 46900 4
+N 41200 46900 42000 46900 4
+C 45800 48200 1 180 0 in-1.sym
+{
+T 45800 47900 5 10 0 0 180 0 1
+device=INPUT
+T 45800 47900 5 10 1 1 180 0 1
+refdes=DGND
+}
+C 45900 49400 1 180 0 in-1.sym
+{
+T 45900 49100 5 10 0 0 180 0 1
+device=INPUT
+T 45900 49100 5 10 1 1 180 0 1
+refdes=DVCC
+}
+C 44200 46100 1 270 0 out-1.sym
+{
+T 44500 46100 5 10 0 0 270 0 1
+device=OUTPUT
+T 44500 46100 5 10 1 1 270 0 1
+refdes=OUT0
+}
+C 44700 46100 1 270 0 out-1.sym
+{
+T 45000 46100 5 10 0 0 270 0 1
+device=OUTPUT
+T 45000 46100 5 10 1 1 270 0 1
+refdes=OUT1
+}
+C 45200 46100 1 270 0 out-1.sym
+{
+T 45500 46100 5 10 0 0 270 0 1
+device=OUTPUT
+T 45500 46100 5 10 1 1 270 0 1
+refdes=OUT2
+}
+C 45700 46100 1 270 0 out-1.sym
+{
+T 46000 46100 5 10 0 0 270 0 1
+device=OUTPUT
+T 46000 46100 5 10 1 1 270 0 1
+refdes=OUT3
+}
+N 43800 46600 44300 46600 4
+N 44300 46600 44300 46100 4
+N 43800 48100 45200 48100 4
+N 44600 48100 44600 48400 4
+N 44600 48400 43800 48400 4
+N 43800 47800 44100 47800 4
+N 44100 47800 44100 49300 4
+N 43800 46900 44800 46900 4
+N 44800 46900 44800 46100 4
+N 43800 47200 45300 47200 4
+N 45300 47200 45300 46100 4
+N 43800 47500 45800 47500 4
+N 45800 47500 45800 46100 4
+C 39400 49100 1 0 0 in-1.sym
+{
+T 39400 49400 5 10 0 0 0 0 1
+device=INPUT
+T 39400 49400 5 10 1 1 0 0 1
+refdes=DIFFA
+}
+N 40000 49200 41600 49200 4
+N 41600 49200 41600 46600 4
+N 41600 46600 42000 46600 4
+N 42000 47200 41600 47200 4
+N 42000 47800 41600 47800 4
+N 42000 48400 41600 48400 4
+C 45300 48200 1 90 0 capacitor-1.sym
+{
+T 44600 48400 5 10 0 0 90 0 1
+device=CAPACITOR
+T 44900 48400 5 10 1 1 90 0 1
+refdes=C1
+T 44400 48400 5 10 0 0 90 0 1
+symversion=0.1
+T 45300 48200 5 10 0 0 90 0 1
+footprint=0603
+T 45500 48400 5 10 1 1 90 0 1
+value=0.1 uF
+T 45300 48200 5 10 0 0 0 0 1
+pn=VJ0603Y104JXJPW1BC
+}
+N 44100 49300 45300 49300 4
+N 45100 49100 45100 49300 4
+N 44100 48700 43800 48700 4
+N 45100 48200 45100 48100 4

diff --git a/bbb_cape/schematic/gafrc b/bbb_cape/schematic/gafrc
new file mode 100644
index 0000000..149e5a2
--- /dev/null
+++ b/bbb_cape/schematic/gafrc

@@ -0,0 +1,2 @@
+(component-library "./symbols" "971 Symbols")
+(source-library ".")

diff --git a/bbb_cape/schematic/generate_mouser_bom.rb b/bbb_cape/schematic/generate_mouser_bom.rb
new file mode 100755
index 0000000..8c2c0cd
--- /dev/null
+++ b/bbb_cape/schematic/generate_mouser_bom.rb

@@ -0,0 +1,54 @@
+#!/usr/bin/env ruby
+
+# This generates something designed to be copied into Mouser's BOM creation
+# copy/paste box. It turns out that it's usually easier to just manually add
+# everything to your cart with the "EZBuy" thingie, but it's still a reasonable
+# format.
+#
+# Usage: generate_mouser_bom.rb FILE [COPIES]
+
+lines = File.open(ARGV[0]) do |f|
+  lines = f.readlines
+  lines.shift
+  lines.collect do |line|
+    line.split(', ')
+  end
+end
+
+$parts = {}
+
+def print_part(pn_string)
+	#puts pn + '|1'
+	pn = pn_string.intern
+	if $parts[pn]
+		$parts[pn] = $parts[pn] + 1
+	else
+		$parts[pn] = 1
+	end
+end
+
+lines.each do |line|
+	pn = line[4]
+	if pn.index(';')
+		parts = pn.split('; ')
+		parts.each do |part_string|
+			part = part_string.match(/(.+) x([0-9]+)?/)
+			if part
+				name = part[1]
+				number = part[2]
+				number.to_i.times do
+					print_part name
+				end
+			else
+				print_part part_string
+			end
+		end
+	else
+		print_part pn unless pn.empty?
+	end
+end
+
+times = (ARGV[1] || 1).to_i
+$parts.each do |pn, number|
+	puts "#{pn}|#{number * times}"
+end

diff --git a/bbb_cape/schematic/gerbers/20131204/cape.bottom.gbr b/bbb_cape/schematic/gerbers/20131204/cape.bottom.gbr
new file mode 100644
index 0000000..7a80bff
--- /dev/null
+++ b/bbb_cape/schematic/gerbers/20131204/cape.bottom.gbr

@@ -0,0 +1,4398 @@
+G04 start of page 5 for group 3 idx 3 *

+G04 Title: 971 BBB Cape, bottom *

+G04 Creator: pcb 20110918 *

+G04 CreationDate: Thu Dec  5 05:46:54 2013 UTC *

+G04 For: brians *

+G04 Format: Gerber/RS-274X *

+G04 PCB-Dimensions: 500000 400000 *

+G04 PCB-Coordinate-Origin: lower left *

+%MOIN*%

+%FSLAX25Y25*%

+%LNBOTTOM*%

+%ADD247C,0.0350*%

+%ADD246C,0.0600*%

+%ADD245C,0.0200*%

+%ADD244C,0.0360*%

+%ADD243R,0.0345X0.0345*%

+%ADD242R,0.1220X0.1220*%

+%ADD241R,0.0560X0.0560*%

+%ADD240R,0.0512X0.0512*%

+%ADD239R,0.0180X0.0180*%

+%ADD238R,0.0130X0.0130*%

+%ADD237R,0.0295X0.0295*%

+%ADD236C,0.2100*%

+%ADD235C,0.0660*%

+%ADD234C,0.2200*%

+%ADD233C,0.1830*%

+%ADD232C,0.0650*%

+%ADD231C,0.0480*%

+%ADD230C,0.0380*%

+%ADD229C,0.0500*%

+%ADD228C,0.0250*%

+%ADD227C,0.0080*%

+%ADD226C,0.0100*%

+%ADD225C,0.0001*%

+G54D225*G36*

+X122941Y305000D02*Y331500D01*

+X92941D01*

+Y360000D01*

+X156941D01*

+Y342500D01*

+X130941D01*

+Y305000D01*

+X122941D01*

+G37*

+G36*

+X133441Y318000D02*Y340000D01*

+X155941D01*

+Y318000D01*

+X133441D01*

+G37*

+G36*

+X253098Y217146D02*X261941Y208303D01*

+Y201500D01*

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+Y209121D01*

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+X253402Y209439D01*

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+X253658Y209942D01*

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+X253402Y211561D01*

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+G37*

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+Y225646D02*X261941Y216803D01*

+Y215697D01*

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+G37*

+G36*

+Y230255D02*X261941Y221412D01*

+Y220197D01*

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+G37*

+G36*

+Y247050D02*X261941D01*

+Y224806D01*

+X253098Y233649D01*

+Y247050D01*

+G37*

+G36*

+Y264380D02*X261941D01*

+Y256200D01*

+X253098D01*

+Y259780D01*

+X253101Y259780D01*

+X253423Y259805D01*

+X253736Y259880D01*

+X254035Y260004D01*

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+X254555Y260382D01*

+X254765Y260627D01*

+X254933Y260902D01*

+X255057Y261201D01*

+X255132Y261514D01*

+X255151Y261836D01*

+X255132Y262158D01*

+X255057Y262471D01*

+X254933Y262770D01*

+X254765Y263045D01*

+X254555Y263290D01*

+X254310Y263500D01*

+X254035Y263668D01*

+X253736Y263792D01*

+X253423Y263867D01*

+X253101Y263892D01*

+X253098Y263892D01*

+Y264380D01*

+G37*

+G36*

+Y270771D02*X261941D01*

+Y270656D01*

+X261816Y270604D01*

+X261541Y270436D01*

+X261296Y270226D01*

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+Y266780D01*

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+G37*

+G36*

+Y273875D02*X261941D01*

+Y273171D01*

+X253098D01*

+Y273875D01*

+G37*

+G36*

+Y279016D02*X254239Y277875D01*

+X253098D01*

+Y279016D01*

+G37*

+G36*

+X239299Y247050D02*X253098D01*

+Y233649D01*

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+X248402Y239061D01*

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+X245158Y238282D01*

+X245135Y238000D01*

+X245158Y237718D01*

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diff --git a/bbb_cape/schematic/gerbers/20131204/cape.bottommask.gbr b/bbb_cape/schematic/gerbers/20131204/cape.bottommask.gbr
new file mode 100644
index 0000000..1f47cfd
--- /dev/null
+++ b/bbb_cape/schematic/gerbers/20131204/cape.bottommask.gbr

@@ -0,0 +1,668 @@
+G04 start of page 9 for group -4062 idx -4062 *

+G04 Title: 971 BBB Cape, soldermask *

+G04 Creator: pcb 20110918 *

+G04 CreationDate: Thu Dec  5 05:46:54 2013 UTC *

+G04 For: brians *

+G04 Format: Gerber/RS-274X *

+G04 PCB-Dimensions: 500000 400000 *

+G04 PCB-Coordinate-Origin: lower left *

+%MOIN*%

+%FSLAX25Y25*%

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diff --git a/bbb_cape/schematic/gerbers/20131204/cape.bottompaste.gbr b/bbb_cape/schematic/gerbers/20131204/cape.bottompaste.gbr
new file mode 100644
index 0000000..931d268
--- /dev/null
+++ b/bbb_cape/schematic/gerbers/20131204/cape.bottompaste.gbr

@@ -0,0 +1,295 @@
+G04 start of page 13 for group -4014 idx -4014 *

+G04 Title: 971 BBB Cape, bottompaste *

+G04 Creator: pcb 20110918 *

+G04 CreationDate: Thu Dec  5 05:46:54 2013 UTC *

+G04 For: brians *

+G04 Format: Gerber/RS-274X *

+G04 PCB-Dimensions: 500000 400000 *

+G04 PCB-Coordinate-Origin: lower left *

+%MOIN*%

+%FSLAX25Y25*%

+%LNBOTTOMPASTE*%

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diff --git a/bbb_cape/schematic/gerbers/20131204/cape.bottomsilk.gbr b/bbb_cape/schematic/gerbers/20131204/cape.bottomsilk.gbr
new file mode 100644
index 0000000..63245b3
--- /dev/null
+++ b/bbb_cape/schematic/gerbers/20131204/cape.bottomsilk.gbr

@@ -0,0 +1,60 @@
+G04 start of page 11 for group -4078 idx -4078 *

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diff --git a/bbb_cape/schematic/gerbers/20131204/cape.fab.gbr b/bbb_cape/schematic/gerbers/20131204/cape.fab.gbr
new file mode 100644
index 0000000..f17ed9c
--- /dev/null
+++ b/bbb_cape/schematic/gerbers/20131204/cape.fab.gbr

@@ -0,0 +1,3010 @@
+G04 start of page 14 for group -3984 idx -3984 *

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+G04 Creator: pcb 20110918 *

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diff --git a/bbb_cape/schematic/gerbers/20131204/cape.group1.gbr b/bbb_cape/schematic/gerbers/20131204/cape.group1.gbr
new file mode 100644
index 0000000..07cccd6
--- /dev/null
+++ b/bbb_cape/schematic/gerbers/20131204/cape.group1.gbr

@@ -0,0 +1,26585 @@
+G04 start of page 3 for group 1 idx 2 *

+G04 Title: 971 BBB Cape, ground *

+G04 Creator: pcb 20110918 *

+G04 CreationDate: Thu Dec  5 05:46:53 2013 UTC *

+G04 For: brians *

+G04 Format: Gerber/RS-274X *

+G04 PCB-Dimensions: 500000 400000 *

+G04 PCB-Coordinate-Origin: lower left *

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diff --git a/bbb_cape/schematic/gerbers/20131204/cape.group2.gbr b/bbb_cape/schematic/gerbers/20131204/cape.group2.gbr
new file mode 100644
index 0000000..616aca5
--- /dev/null
+++ b/bbb_cape/schematic/gerbers/20131204/cape.group2.gbr

@@ -0,0 +1,25032 @@
+G04 start of page 4 for group 2 idx 1 *

+G04 Title: 971 BBB Cape, power *

+G04 Creator: pcb 20110918 *

+G04 CreationDate: Thu Dec  5 05:46:54 2013 UTC *

+G04 For: brians *

+G04 Format: Gerber/RS-274X *

+G04 PCB-Dimensions: 500000 400000 *

+G04 PCB-Coordinate-Origin: lower left *

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diff --git a/bbb_cape/schematic/gerbers/20131204/cape.outline.gbr b/bbb_cape/schematic/gerbers/20131204/cape.outline.gbr
new file mode 100644
index 0000000..2220c1d
--- /dev/null
+++ b/bbb_cape/schematic/gerbers/20131204/cape.outline.gbr

@@ -0,0 +1,29 @@
+G04 start of page 6 for group 4 idx 4 *

+G04 Title: 971 BBB Cape, outline *

+G04 Creator: pcb 20110918 *

+G04 CreationDate: Thu Dec  5 05:46:54 2013 UTC *

+G04 For: brians *

+G04 Format: Gerber/RS-274X *

+G04 PCB-Dimensions: 500000 400000 *

+G04 PCB-Coordinate-Origin: lower left *

+%MOIN*%

+%FSLAX25Y25*%

+%LNOUTLINE*%

+%ADD248C,0.0080*%

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new file mode 100644
index 0000000..0de77e1
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diff --git a/bbb_cape/schematic/gerbers/20131204/cape.top.gbr b/bbb_cape/schematic/gerbers/20131204/cape.top.gbr
new file mode 100644
index 0000000..ca29885
--- /dev/null
+++ b/bbb_cape/schematic/gerbers/20131204/cape.top.gbr

@@ -0,0 +1,3523 @@
+G04 start of page 2 for group 0 idx 0 *

+G04 Title: 971 BBB Cape, top *

+G04 Creator: pcb 20110918 *

+G04 CreationDate: Thu Dec  5 05:46:53 2013 UTC *

+G04 For: brians *

+G04 Format: Gerber/RS-274X *

+G04 PCB-Dimensions: 500000 400000 *

+G04 PCB-Coordinate-Origin: lower left *

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diff --git a/bbb_cape/schematic/gerbers/20131204/cape.topmask.gbr b/bbb_cape/schematic/gerbers/20131204/cape.topmask.gbr
new file mode 100644
index 0000000..d66f97a
--- /dev/null
+++ b/bbb_cape/schematic/gerbers/20131204/cape.topmask.gbr

@@ -0,0 +1,724 @@
+G04 start of page 8 for group -4063 idx -4063 *

+G04 Title: 971 BBB Cape, componentmask *

+G04 Creator: pcb 20110918 *

+G04 CreationDate: Thu Dec  5 05:46:54 2013 UTC *

+G04 For: brians *

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diff --git a/bbb_cape/schematic/gerbers/20131204/cape.toppaste.gbr b/bbb_cape/schematic/gerbers/20131204/cape.toppaste.gbr
new file mode 100644
index 0000000..d9aadea
--- /dev/null
+++ b/bbb_cape/schematic/gerbers/20131204/cape.toppaste.gbr

@@ -0,0 +1,351 @@
+G04 start of page 12 for group -4015 idx -4015 *

+G04 Title: 971 BBB Cape, toppaste *

+G04 Creator: pcb 20110918 *

+G04 CreationDate: Thu Dec  5 05:46:54 2013 UTC *

+G04 For: brians *

+G04 Format: Gerber/RS-274X *

+G04 PCB-Dimensions: 500000 400000 *

+G04 PCB-Coordinate-Origin: lower left *

+%MOIN*%

+%FSLAX25Y25*%

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diff --git a/bbb_cape/schematic/gerbers/20131204/cape.topsilk.gbr b/bbb_cape/schematic/gerbers/20131204/cape.topsilk.gbr
new file mode 100644
index 0000000..2880ff7
--- /dev/null
+++ b/bbb_cape/schematic/gerbers/20131204/cape.topsilk.gbr

@@ -0,0 +1,977 @@
+G04 start of page 10 for group -4079 idx -4079 *

+G04 Title: 971 BBB Cape, topsilk *

+G04 Creator: pcb 20110918 *

+G04 CreationDate: Thu Dec  5 05:46:54 2013 UTC *

+G04 For: brians *

+G04 Format: Gerber/RS-274X *

+G04 PCB-Dimensions: 500000 400000 *

+G04 PCB-Coordinate-Origin: lower left *

+%MOIN*%

+%FSLAX25Y25*%

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+M02*


diff --git a/bbb_cape/schematic/gerbers/20131204/cape.zip b/bbb_cape/schematic/gerbers/20131204/cape.zip
new file mode 100644
index 0000000..5598263
--- /dev/null
+++ b/bbb_cape/schematic/gerbers/20131204/cape.zip
Binary files differ

diff --git a/bbb_cape/schematic/gschemrc b/bbb_cape/schematic/gschemrc
new file mode 100644
index 0000000..fcf437d
--- /dev/null
+++ b/bbb_cape/schematic/gschemrc

@@ -0,0 +1,3 @@
+(load (string-append geda-data-path "/scheme/auto-uref.scm")) ; load the autonumbering script
+(add-hook! add-component-hook auto-uref)       ; autonumber when adding a component
+(add-hook! copy-component-hook auto-uref)      ; autonumber when copying a component

diff --git a/bbb_cape/schematic/packages/1812.fp b/bbb_cape/schematic/packages/1812.fp
new file mode 100644
index 0000000..d0210c9
--- /dev/null
+++ b/bbb_cape/schematic/packages/1812.fp

@@ -0,0 +1,11 @@
+Element["" "1812" "1812" "1812" 15.0000mm 1574.80mil -3.7498mm -39.38mil 0 100 ""]
+(
+	Pad[98.43mil -19.68mil 98.43mil 19.69mil 94.80mil 39.37mil 2.5080mm "2" "2" "square"]
+	Pad[-98.42mil -19.68mil -98.42mil 19.69mil 94.80mil 39.37mil 2.5080mm "1" "1" "square"]
+	ElementLine [-157.48mil -59.05mil -137.79mil -2.0000mm 8.00mil]
+	ElementLine [-157.48mil 2.0000mm -157.48mil -59.05mil 8.00mil]
+	ElementLine [157.48mil 2.0000mm -157.48mil 2.0000mm 8.00mil]
+	ElementLine [157.48mil -2.0000mm 157.48mil 2.0000mm 8.00mil]
+	ElementLine [-137.79mil -2.0000mm 157.48mil -2.0000mm 8.00mil]
+
+	)

diff --git a/bbb_cape/schematic/packages/22-23-2031.fp b/bbb_cape/schematic/packages/22-23-2031.fp
new file mode 100644
index 0000000..5b98bc0
--- /dev/null
+++ b/bbb_cape/schematic/packages/22-23-2031.fp

@@ -0,0 +1,14 @@
+Element(0x00 "Molex 22-23-2031 1x3 connector" "" "22-23-2031" 360 0 3 100 0x00)
+(
+	Pin(62 147 65 40 "1" 0x101)
+	Pin(162 147 65 40 "2" 0x01)
+	Pin(262 147 65 40 "3" 0x01)
+	ElementLine(0 0 0 290 10)
+	ElementLine(324 0 324 290 10)
+	ElementLine(324 0 0 0 10)
+	ElementLine(0 90 324 90 10)
+	ElementLine(112 290 112 90 10)
+	ElementLine(212 290 212 90 10)
+	ElementLine(0 290 324 290 10)
+	Mark(162 147)
+)

diff --git a/bbb_cape/schematic/packages/22-23-2041.fp b/bbb_cape/schematic/packages/22-23-2041.fp
new file mode 100644
index 0000000..43ffa87
--- /dev/null
+++ b/bbb_cape/schematic/packages/22-23-2041.fp

@@ -0,0 +1,16 @@
+Element(0x00 "Molex 22-23-2041 1x4 connector" "" "22-23-2041" 360 0 3 100 0x00)
+(
+	Pin(62 147 65 40 "1" 0x101)
+	Pin(162 147 65 40 "2" 0x01)
+	Pin(262 147 65 40 "3" 0x01)
+	Pin(362 147 65 40 "4" 0x01)
+	ElementLine(0 0 0 290 10)
+	ElementLine(424 0 424 290 10)
+	ElementLine(424 0 0 0 10)
+	ElementLine(0 90 424 90 10)
+	ElementLine(112 290 112 90 10)
+	ElementLine(212 290 212 90 10)
+	ElementLine(312 290 312 90 10)
+	ElementLine(0 290 424 290 10)
+	Mark(212 147)
+)

diff --git a/bbb_cape/schematic/packages/4-40_bolt.fp b/bbb_cape/schematic/packages/4-40_bolt.fp
new file mode 100644
index 0000000..dfe3c5f
--- /dev/null
+++ b/bbb_cape/schematic/packages/4-40_bolt.fp

@@ -0,0 +1,4 @@
+Element[0x0 "#4-40 bolt" "" "" 0 0 0 0 0 100 0x0]
+(
+   Pin[0 0 18300 1800 18900 12850 "the_hole" "1" 0x01]
+)

diff --git a/bbb_cape/schematic/packages/ABMM2.fp b/bbb_cape/schematic/packages/ABMM2.fp
new file mode 100644
index 0000000..66d118d
--- /dev/null
+++ b/bbb_cape/schematic/packages/ABMM2.fp

@@ -0,0 +1,12 @@
+# author: Bdale Garbee
+# email: bdale@gag.com
+# dist-license: GPL 2
+# use-license: unlimited
+Element[0x0 "ABM8" "" "" 0 0 0 0 0 100 0x0]
+(
+   Pad[ 5512 -9349 5512 -12007 7480 -3936 8080 "pin2" "2" 0x0100]
+   Pad[ 5512 9350 5512 12008 7480 -3936 8080 "pin1" "1" 0x0100]
+   Pad[ -5511 9350 -5511 12008 7480 -3936 8080 "pin4" "4" 0x0100]
+   Pad[ -5511 -9349 -5511 -12007 7480 -3936 8080 "pin3" "3" 0x0100]
+   ElementArc[ 709 13720 500 500 0 360 1000 ]
+)

diff --git a/bbb_cape/schematic/packages/TOPMOD.fp b/bbb_cape/schematic/packages/TOPMOD.fp
new file mode 100644
index 0000000..3f72817
--- /dev/null
+++ b/bbb_cape/schematic/packages/TOPMOD.fp

@@ -0,0 +1,19 @@
+Element["" "National 7-pin TO switcher module" "" "" 39370 39370 0 0 0 100 "TO-PMOD"]
+(
+	Pad[-15000 26772 -15000 33071 3504 2000 4104 "1" "1" "square,edge2"]
+	Pad[-10000 26772 -10000 33071 3504 2000 4104 "2" "2" "square,edge2"]
+	Pad[-5000 26772 -5000 33071 3504 2000 4104 "3" "3" "square,edge2"]
+	Pad[0 26772 0 33071 3504 2000 4104 "4" "4" "square,edge2"]
+	Pad[5000 26772 5000 33071 3504 2000 4104 "5" "5" "square,edge2"]
+	Pad[10000 26772 10000 33071 3504 2000 4104 "6" "6" "square,edge2"]
+	Pad[15000 26772 15000 33071 3504 2000 4104 "7" "7" "square,edge2"]
+	Pad[0 -6693 0 6693 21063 2000 21663 "8" "8" "square"]
+	ElementLine [-18110 35827 -18110 20079 1000]
+	ElementLine [18110 35827 -18110 35827 1000]
+	ElementLine [18110 20079 18110 35827 1000]
+	ElementLine [-19685 20079 -19685 -20079 1000]
+	ElementLine [19685 20079 19685 -20079 1000]
+	ElementLine [19685 20079 -19685 20079 1000]
+	ElementLine [19685 -20079 -19685 -20079 1000]
+
+	)

diff --git a/bbb_cape/schematic/packages/beaglebone.fp b/bbb_cape/schematic/packages/beaglebone.fp
new file mode 100644
index 0000000..ea013ee
--- /dev/null
+++ b/bbb_cape/schematic/packages/beaglebone.fp

@@ -0,0 +1,116 @@
+Element[0x0 "beaglebone-cape" "" "" 0 0 -112500 -118000 0 100 0x0]
+(
+   ElementArc[155000 -60000 50000 50000 180 90 1000]
+   ElementArc[155000 55000 50000 50000 90 90 1000]
+   ElementArc[-110000 80000 25000 25000 0 90 1000]
+   ElementLine[-112500 -110000 155000 -110000 1000]
+   ElementLine[205000 55000 205000 -60000 1000]
+   ElementLine[-110000 105000 155000 105000 1000]
+   ElementLine[-135000 80000 -135000 22500 1000]
+   ElementLine[-135000 22500 -55000 22500 1000]
+   ElementLine[-55000 22500 -55000 -47500 1000]
+   ElementLine[-55000 -47500 -112500 -47500 1000]
+   ElementLine[-112500 -47500 -112500 -110000 1000]
+   Pin[-77500 92500 18300 1800 18900 12850 "bogus_442" "442" 0x01]
+   Pin[-77500 -97500 18300 1800 18900 12850 "bogus_542" "542" 0x01]
+   Pin[182500 80000 21000 1800 23000 19000 "bogus_642" "642" 0x01]
+   Pin[182500 -85000 18300 1800 18900 12850 "bogus_742" "742" 0x01]
+   Pin[-57500 87500 6600 2000 8600 4600 "" "48" 0x01]
+   Pin[-57500 97500 6600 2000 8600 4600 "" "47" 0x0101]
+   Pin[-47500 87500 6600 2000 8600 4600 "" "50" 0x01]
+   Pin[-47500 97500 6600 2000 8600 4600 "" "49" 0x01]
+   Pin[-37500 87500 6600 2000 8600 4600 "" "52" 0x01]
+   Pin[-37500 97500 6600 2000 8600 4600 "" "51" 0x01]
+   Pin[-27500 87500 6600 2000 8600 4600 "" "54" 0x01]
+   Pin[-27500 97500 6600 2000 8600 4600 "" "53" 0x01]
+   Pin[-17500 87500 6600 2000 8600 4600 "" "56" 0x01]
+   Pin[-17500 97500 6600 2000 8600 4600 "" "55" 0x01]
+   Pin[-7500 87500 6600 2000 8600 4600 "" "58" 0x01]
+   Pin[-7500 97500 6600 2000 8600 4600 "" "57" 0x01]
+   Pin[2500 87500 6600 2000 8600 4600 "" "60" 0x01]
+   Pin[2500 97500 6600 2000 8600 4600 "" "59" 0x01]
+   Pin[12500 87500 6600 2000 8600 4600 "" "62" 0x01]
+   Pin[12500 97500 6600 2000 8600 4600 "" "61" 0x01]
+   Pin[22500 87500 6600 2000 8600 4600 "" "64" 0x01]
+   Pin[22500 97500 6600 2000 8600 4600 "" "63" 0x01]
+   Pin[32500 87500 6600 2000 8600 4600 "" "66" 0x01]
+   Pin[32500 97500 6600 2000 8600 4600 "" "65" 0x01]
+   Pin[42500 87500 6600 2000 8600 4600 "" "68" 0x01]
+   Pin[42500 97500 6600 2000 8600 4600 "" "67" 0x01]
+   Pin[52500 87500 6600 2000 8600 4600 "" "70" 0x01]
+   Pin[52500 97500 6600 2000 8600 4600 "" "69" 0x01]
+   Pin[62500 87500 6600 2000 8600 4600 "" "72" 0x01]
+   Pin[62500 97500 6600 2000 8600 4600 "" "71" 0x01]
+   Pin[72500 87500 6600 2000 8600 4600 "" "74" 0x01]
+   Pin[72500 97500 6600 2000 8600 4600 "" "73" 0x01]
+   Pin[82500 87500 6600 2000 8600 4600 "" "76" 0x01]
+   Pin[82500 97500 6600 2000 8600 4600 "" "75" 0x01]
+   Pin[92500 87500 6600 2000 8600 4600 "" "78" 0x01]
+   Pin[92500 97500 6600 2000 8600 4600 "" "77" 0x01]
+   Pin[102500 87500 6600 2000 8600 4600 "" "80" 0x01]
+   Pin[102500 97500 6600 2000 8600 4600 "" "79" 0x01]
+   Pin[112500 87500 6600 2000 8600 4600 "" "82" 0x01]
+   Pin[112500 97500 6600 2000 8600 4600 "" "81" 0x01]
+   Pin[122500 87500 6600 2000 8600 4600 "" "84" 0x01]
+   Pin[122500 97500 6600 2000 8600 4600 "" "83" 0x01]
+   Pin[132500 87500 6600 2000 8600 4600 "" "86" 0x01]
+   Pin[132500 97500 6600 2000 8600 4600 "" "85" 0x01]
+   Pin[142500 87500 6600 2000 8600 4600 "" "88" 0x01]
+   Pin[142500 97500 6600 2000 8600 4600 "" "87" 0x01]
+   Pin[152500 87500 6600 2000 8600 4600 "" "90" 0x01]
+   Pin[152500 97500 6600 2000 8600 4600 "" "89" 0x01]
+   Pin[162500 87500 6600 2000 8600 4600 "" "92" 0x01]
+   Pin[162500 97500 6600 2000 8600 4600 "" "91" 0x01]
+   Pin[-57500 -102500 6600 2000 8600 4600 "" "2" 0x01]
+   Pin[-57500 -92500 6600 2000 8600 4600 "" "1" 0x0101]
+   Pin[-47500 -102500 6600 2000 8600 4600 "" "4" 0x01]
+   Pin[-47500 -92500 6600 2000 8600 4600 "" "3" 0x01]
+   Pin[-37500 -102500 6600 2000 8600 4600 "" "6" 0x01]
+   Pin[-37500 -92500 6600 2000 8600 4600 "" "5" 0x01]
+   Pin[-27500 -102500 6600 2000 8600 4600 "" "8" 0x01]
+   Pin[-27500 -92500 6600 2000 8600 4600 "" "7" 0x01]
+   Pin[-17500 -102500 6600 2000 8600 4600 "" "10" 0x01]
+   Pin[-17500 -92500 6600 2000 8600 4600 "" "9" 0x01]
+   Pin[-7500 -102500 6600 2000 8600 4600 "" "12" 0x01]
+   Pin[-7500 -92500 6600 2000 8600 4600 "" "11" 0x01]
+   Pin[2500 -102500 6600 2000 8600 4600 "" "14" 0x01]
+   Pin[2500 -92500 6600 2000 8600 4600 "" "13" 0x01]
+   Pin[12500 -102500 6600 2000 8600 4600 "" "16" 0x01]
+   Pin[12500 -92500 6600 2000 8600 4600 "" "15" 0x01]
+   Pin[22500 -102500 6600 2000 8600 4600 "" "18" 0x01]
+   Pin[22500 -92500 6600 2000 8600 4600 "" "17" 0x01]
+   Pin[32500 -102500 6600 2000 8600 4600 "" "20" 0x01]
+   Pin[32500 -92500 6600 2000 8600 4600 "" "19" 0x01]
+   Pin[42500 -102500 6600 2000 8600 4600 "" "22" 0x01]
+   Pin[42500 -92500 6600 2000 8600 4600 "" "21" 0x01]
+   Pin[52500 -102500 6600 2000 8600 4600 "" "24" 0x01]
+   Pin[52500 -92500 6600 2000 8600 4600 "" "23" 0x01]
+   Pin[62500 -102500 6600 2000 8600 4600 "" "26" 0x01]
+   Pin[62500 -92500 6600 2000 8600 4600 "" "25" 0x01]
+   Pin[72500 -102500 6600 2000 8600 4600 "" "28" 0x01]
+   Pin[72500 -92500 6600 2000 8600 4600 "" "27" 0x01]
+   Pin[82500 -102500 6600 2000 8600 4600 "" "30" 0x01]
+   Pin[82500 -92500 6600 2000 8600 4600 "" "29" 0x01]
+   Pin[92500 -102500 6600 2000 8600 4600 "" "32" 0x01]
+   Pin[92500 -92500 6600 2000 8600 4600 "" "31" 0x01]
+   Pin[102500 -102500 6600 2000 8600 4600 "" "34" 0x01]
+   Pin[102500 -92500 6600 2000 8600 4600 "" "33" 0x01]
+   Pin[112500 -102500 6600 2000 8600 4600 "" "36" 0x01]
+   Pin[112500 -92500 6600 2000 8600 4600 "" "35" 0x01]
+   Pin[122500 -102500 6600 2000 8600 4600 "" "38" 0x01]
+   Pin[122500 -92500 6600 2000 8600 4600 "" "37" 0x01]
+   Pin[132500 -102500 6600 2000 8600 4600 "" "40" 0x01]
+   Pin[132500 -92500 6600 2000 8600 4600 "" "39" 0x01]
+   Pin[142500 -102500 6600 2000 8600 4600 "" "42" 0x01]
+   Pin[142500 -92500 6600 2000 8600 4600 "" "41" 0x01]
+   Pin[152500 -102500 6600 2000 8600 4600 "" "44" 0x01]
+   Pin[152500 -92500 6600 2000 8600 4600 "" "43" 0x01]
+   Pin[162500 -102500 6600 2000 8600 4600 "" "46" 0x01]
+   Pin[162500 -92500 6600 2000 8600 4600 "" "45" 0x01]
+   Pin[32500 75000 6600 2000 8600 4600 "" "UART1" 0x101]
+   Pin[42500 75000 6600 2000 8600 4600 "" "UART2" 0x01]
+   Pin[52500 75000 6600 2000 8600 4600 "" "UART3" 0x01]
+   Pin[62500 75000 6600 2000 8600 4600 "" "UART4" 0x01]
+   Pin[72500 75000 6600 2000 8600 4600 "" "UART5" 0x01]
+   Pin[152500 -65000 22000 1800 24000 20000 "bogus_842" "842" 0x01]
+)

diff --git a/bbb_cape/schematic/simple switcher 5V.sch b/bbb_cape/schematic/simple switcher 5V.sch
new file mode 100644
index 0000000..3cf7bc6
--- /dev/null
+++ b/bbb_cape/schematic/simple switcher 5V.sch

@@ -0,0 +1,245 @@
+v 20110115 2
+C 44700 46900 1 0 0 lmz12002-1.sym
+{
+T 45200 47800 5 10 1 1 0 0 1
+device=LMZ12002
+T 46600 47800 5 10 1 1 0 0 1
+refdes=U3
+T 44700 46900 5 10 0 0 0 0 1
+pn=LMZ12002LMZ12002TZ-ADJ/NOPB
+}
+N 46200 44200 46200 46900 4
+N 46200 46700 46500 46700 4
+N 46500 46700 46500 46900 4
+C 47000 45200 1 90 0 capacitor-1.sym
+{
+T 46300 45400 5 10 0 0 90 0 1
+device=CAPACITOR
+T 46500 45400 5 10 1 1 90 0 1
+refdes=C2
+T 46100 45400 5 10 0 0 90 0 1
+symversion=0.1
+T 47000 45200 5 10 0 0 90 0 1
+footprint=0603
+T 47100 45200 5 10 1 1 90 0 1
+value=10 nf
+T 47000 45200 5 10 0 0 0 0 1
+pn=GRM216R71H103KA01D
+}
+C 43600 45400 1 90 0 capacitor-1.sym
+{
+T 42900 45600 5 10 0 0 90 0 1
+device=CAPACITOR
+T 43100 45600 5 10 1 1 90 0 1
+refdes=C3
+T 42700 45600 5 10 0 0 90 0 1
+symversion=0.1
+T 43600 45400 5 10 0 0 90 0 1
+footprint=1210
+T 43700 45400 5 10 1 1 90 0 1
+value=10 uF
+T 43600 45400 5 10 0 0 0 0 1
+pn=C3225X7R1E106MT
+}
+C 42800 45400 1 90 0 capacitor-1.sym
+{
+T 42100 45600 5 10 0 0 90 0 1
+device=CAPACITOR
+T 42300 45600 5 10 1 1 90 0 1
+refdes=C4
+T 41900 45600 5 10 0 0 90 0 1
+symversion=0.1
+T 42800 45400 5 10 0 0 90 0 1
+footprint=1210
+T 42900 45400 5 10 1 1 90 0 1
+value=10 uF
+T 42800 45400 5 10 0 0 0 0 1
+pn=C3225X7R1E106MT
+}
+C 42500 44700 1 0 0 gnd-1.sym
+N 43400 46300 43400 46600 4
+N 41800 46600 45100 46600 4
+N 45100 46600 45100 46900 4
+N 42600 46600 42600 46300 4
+N 42600 45000 42600 45400 4
+N 42600 45200 43400 45200 4
+N 43400 45200 43400 45400 4
+C 49400 45000 1 90 0 capacitor-1.sym
+{
+T 48700 45200 5 10 0 0 90 0 1
+device=CAPACITOR
+T 48900 45200 5 10 1 1 90 0 1
+refdes=C5
+T 48500 45200 5 10 0 0 90 0 1
+symversion=0.1
+T 49400 45000 5 10 0 0 90 0 1
+footprint=0603
+T 49500 45000 5 10 1 1 90 0 1
+value=22 nf
+T 49400 45000 5 10 0 0 0 0 1
+pn=CC0805KRX7R9BB223
+}
+C 44200 45000 1 0 0 resistor-1.sym
+{
+T 44500 45400 5 10 0 0 0 0 1
+device=RESISTOR
+T 44400 45300 5 10 1 1 0 0 1
+refdes=R2
+T 44100 44800 5 10 1 1 0 0 1
+value=34.0 kohm
+T 44200 45000 5 10 0 0 0 0 1
+footprint=0603
+T 44200 45000 5 10 0 0 0 0 1
+pn=CRCW060334K0FKEA
+}
+C 44300 45900 1 0 0 resistor-1.sym
+{
+T 44600 46300 5 10 0 0 0 0 1
+device=RESISTOR
+T 44500 46200 5 10 1 1 0 0 1
+refdes=R3
+T 44100 45700 5 10 1 1 0 0 1
+value=154.0 kohm
+T 44300 45900 5 10 0 0 0 0 1
+footprint=0603
+T 44300 45900 5 10 0 0 0 0 1
+pn=CRCW0603154KFKEA
+}
+N 45400 46900 45400 46000 4
+N 45400 46000 45200 46000 4
+C 44200 44200 1 0 0 resistor-1.sym
+{
+T 44500 44600 5 10 0 0 0 0 1
+device=RESISTOR
+T 44400 44500 5 10 1 1 0 0 1
+refdes=R4
+T 44200 44000 5 10 1 1 0 0 1
+value=9.31 kohm
+T 44200 44200 5 10 0 0 0 0 1
+footprint=0603
+T 44200 44200 5 10 0 0 0 0 1
+pn=CRCW060334K0FKEA
+}
+N 45700 44300 45700 46900 4
+N 45100 45100 45700 45100 4
+N 45700 44300 45100 44300 4
+N 44200 45100 43900 45100 4
+N 43900 45100 43900 46600 4
+C 43900 43800 1 0 0 gnd-1.sym
+N 44200 44300 44000 44300 4
+N 44000 44300 44000 44100 4
+C 46100 43900 1 0 0 gnd-1.sym
+N 46800 45200 46800 45000 4
+N 46800 45000 46200 45000 4
+C 46400 44400 1 0 0 resistor-1.sym
+{
+T 46700 44800 5 10 0 0 0 0 1
+device=RESISTOR
+T 46600 44700 5 10 1 1 0 0 1
+refdes=R5
+T 46400 44200 5 10 1 1 0 0 1
+value=1.27 kohm
+T 46400 44400 5 10 0 0 0 0 1
+footprint=0805
+T 46400 44400 5 10 0 0 0 0 1
+pn=CRCW08051K27FKEA
+}
+N 46200 44500 46400 44500 4
+N 47300 44500 47300 46900 4
+C 47500 46000 1 0 0 resistor-1.sym
+{
+T 47800 46400 5 10 0 0 0 0 1
+device=RESISTOR
+T 47700 46300 5 10 1 1 0 0 1
+refdes=R6
+T 47500 45800 5 10 1 1 0 0 1
+value=6.65 kohm
+T 47500 46000 5 10 0 0 0 0 1
+footprint=0805
+T 47500 46000 5 10 0 0 0 0 1
+pn=CRCW08056K65FKEA
+}
+N 47500 46100 47300 46100 4
+N 47600 46900 47600 46600 4
+N 47600 46600 51400 46600 4
+N 48400 46100 48600 46100 4
+N 48600 46100 48600 46600 4
+N 49200 45900 49200 46600 4
+N 49200 45000 49200 44800 4
+N 49200 44800 47300 44800 4
+C 50300 45000 1 90 0 capacitor-1.sym
+{
+T 49600 45200 5 10 0 0 90 0 1
+device=CAPACITOR
+T 49800 45200 5 10 1 1 90 0 1
+refdes=C6
+T 49400 45200 5 10 0 0 90 0 1
+symversion=0.1
+T 50300 45000 5 10 0 0 90 0 1
+footprint=0603
+T 50400 45000 5 10 1 1 90 0 1
+value=100 uF
+T 50300 45000 5 10 0 0 0 0 1
+pn=C3225X5R0J107MT
+}
+N 50100 46600 50100 45900 4
+C 50000 43900 1 0 0 gnd-1.sym
+N 50100 45000 50100 44200 4
+N 47000 46900 47000 46500 4
+N 47000 46500 46800 46500 4
+N 46800 46500 46800 46100 4
+N 44300 46000 44100 46000 4
+N 44100 46000 44100 46600 4
+C 41200 43900 1 0 0 in-1.sym
+{
+T 41200 44200 5 10 0 0 0 0 1
+device=INPUT
+T 41200 44200 5 10 1 1 0 0 1
+refdes=GND
+}
+C 51400 46500 1 0 0 out-1.sym
+{
+T 51400 46800 5 10 0 0 0 0 1
+device=OUTPUT
+T 51400 46800 5 10 1 1 0 0 1
+refdes=VOUT
+}
+C 42400 43900 1 90 0 gnd-1.sym
+N 41800 44000 42100 44000 4
+C 41200 46500 1 0 0 in-1.sym
+{
+T 41200 46800 5 10 0 0 0 0 1
+device=INPUT
+T 41200 46800 5 10 1 1 0 0 1
+refdes=VIN
+}
+C 51100 46200 1 270 0 resistor-1.sym
+{
+T 51500 45900 5 10 0 0 270 0 1
+device=RESISTOR
+T 51400 46000 5 10 1 1 270 0 1
+refdes=R13
+T 51100 46200 5 10 0 0 270 0 1
+footprint=0603
+T 50900 46200 5 10 1 1 270 0 1
+value=300 ohms
+T 51100 46200 5 10 0 1 0 0 1
+pn=CRCW0603300RFKEAHP
+}
+C 51400 44300 1 90 0 led-3.sym
+{
+T 50750 45250 5 10 0 0 90 0 1
+device=LED
+T 50850 44750 5 10 1 1 90 0 1
+refdes=D1
+T 51400 44300 5 10 0 0 90 0 1
+footprint=0805
+T 51500 44500 5 10 1 1 90 0 1
+value=green
+T 51400 44300 5 10 0 1 0 0 1
+pn=LG R971-KN-1
+}
+N 51200 46600 51200 46200 4
+N 51200 45300 51200 45200 4
+C 51100 43900 1 0 0 gnd-1.sym
+N 51200 44300 51200 44200 4

diff --git a/bbb_cape/schematic/symbols/4-40_bolt-1.sym b/bbb_cape/schematic/symbols/4-40_bolt-1.sym
new file mode 100644
index 0000000..6d6fcfb
--- /dev/null
+++ b/bbb_cape/schematic/symbols/4-40_bolt-1.sym

@@ -0,0 +1,14 @@
+v 20110115 2
+V 600 500 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T -300 1200 8 10 0 1 0 0 1
+device=4-40_bolt
+T 500 1300 8 10 0 1 0 0 1
+description=#4-40 mounting bolt hole
+T 0 1200 8 10 0 1 0 0 1
+footprint=4-40_bolt
+T 500 700 8 10 1 1 0 0 1
+refdes=B?
+T 1100 1400 8 10 0 1 0 0 1
+numslots=1
+T 0 1100 9 10 1 0 0 0 1
+#4-40 bolt hole

diff --git a/bbb_cape/schematic/symbols/ADXRS453-1.sym b/bbb_cape/schematic/symbols/ADXRS453-1.sym
new file mode 100644
index 0000000..299f900
--- /dev/null
+++ b/bbb_cape/schematic/symbols/ADXRS453-1.sym

@@ -0,0 +1,190 @@
+v 20110115 2
+T 600 1800 8 10 0 1 0 0 1
+footprint=SO16W
+B 300 0 1500 2500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 0 2300 300 2300 1 0 0
+{
+T 0 2300 5 10 0 0 0 0 1
+pintype=pwr
+T 355 2295 5 10 1 1 0 0 1
+pinlabel=DVDD
+T 205 2345 5 10 1 1 0 6 1
+pinnumber=1
+T 0 2300 5 10 0 0 0 0 1
+pinseq=1
+}
+P 0 2000 300 2000 1 0 0
+{
+T 0 2000 5 10 0 0 0 0 1
+pintype=pwr
+T 355 1995 5 10 1 1 0 0 1
+pinlabel=DVSS
+T 205 2045 5 10 1 1 0 6 1
+pinnumber=13
+T 0 2000 5 10 0 0 0 0 1
+pinseq=2
+}
+P 0 1700 300 1700 1 0 0
+{
+T 0 1700 5 10 0 0 0 0 1
+pintype=pwr
+T 355 1695 5 10 1 1 0 0 1
+pinlabel=AVDD
+T 205 1745 5 10 1 1 0 6 1
+pinnumber=14
+T 0 1700 5 10 0 0 0 0 1
+pinseq=3
+}
+P 0 1400 300 1400 1 0 0
+{
+T 0 1400 5 10 0 0 0 0 1
+pintype=pwr
+T 355 1395 5 10 1 1 0 0 1
+pinlabel=AVSS
+T 205 1445 5 10 1 1 0 6 1
+pinnumber=11
+T 0 1400 5 10 0 0 0 0 1
+pinseq=4
+}
+P 0 1100 300 1100 1 0 0
+{
+T 0 1100 5 10 0 0 0 0 1
+pintype=in
+T 355 1095 5 10 1 1 0 0 1
+pinlabel=RSVD
+T 205 1145 5 10 1 1 0 6 1
+pinnumber=2
+T 0 1100 5 10 0 0 0 0 1
+pinseq=5
+}
+P 0 800 300 800 1 0 0
+{
+T 0 800 5 10 0 0 0 0 1
+pintype=in
+T 355 795 5 10 1 1 0 0 1
+pinlabel=RSVD
+T 205 845 5 10 1 1 0 6 1
+pinnumber=3
+T 0 800 5 10 0 0 0 0 1
+pinseq=6
+}
+P 0 500 300 500 1 0 0
+{
+T 0 500 5 10 0 0 0 0 1
+pintype=in
+T 355 495 5 10 1 1 0 0 1
+pinlabel=RSVD
+T 205 545 5 10 1 1 0 6 1
+pinnumber=10
+T 0 500 5 10 0 0 0 0 1
+pinseq=7
+}
+P 0 200 300 200 1 0 0
+{
+T 0 200 5 10 0 0 0 0 1
+pintype=in
+T 355 195 5 10 1 1 0 0 1
+pinlabel=RSVD
+T 205 245 5 10 1 1 0 6 1
+pinnumber=12
+T 0 200 5 10 0 0 0 0 1
+pinseq=8
+}
+P 2100 2300 1800 2300 1 0 0
+{
+T 2100 2300 5 10 0 0 0 0 1
+pintype=in
+T 1745 2295 5 10 1 1 0 6 1
+pinlabel=\_CS\_
+T 1895 2345 5 10 1 1 0 0 1
+pinnumber=4
+T 2100 2300 5 10 0 0 0 0 1
+pinseq=9
+}
+P 2100 2000 1800 2000 1 0 0
+{
+T 2100 2000 5 10 0 0 0 0 1
+pintype=in
+T 1745 1995 5 10 1 1 0 6 1
+pinlabel=SCLK
+T 1895 2045 5 10 1 1 0 0 1
+pinnumber=16
+T 2100 2000 5 10 0 0 0 0 1
+pinseq=10
+}
+P 2100 1700 1800 1700 1 0 0
+{
+T 2100 1700 5 10 0 0 0 0 1
+pintype=out
+T 1745 1695 5 10 1 1 0 6 1
+pinlabel=MISO
+T 1895 1745 5 10 1 1 0 0 1
+pinnumber=5
+T 2100 1700 5 10 0 0 0 0 1
+pinseq=11
+}
+P 2100 1400 1800 1400 1 0 0
+{
+T 2100 1400 5 10 0 0 0 0 1
+pintype=in
+T 1745 1395 5 10 1 1 0 6 1
+pinlabel=MOSI
+T 1895 1445 5 10 1 1 0 0 1
+pinnumber=15
+T 2100 1400 5 10 0 0 0 0 1
+pinseq=12
+}
+P 2100 1100 1800 1100 1 0 0
+{
+T 2100 1100 5 10 0 0 0 0 1
+pintype=pwr
+T 1745 1095 5 10 1 1 0 6 1
+pinlabel=PDD
+T 1895 1145 5 10 1 1 0 0 1
+pinnumber=6
+T 2100 1100 5 10 0 0 0 0 1
+pinseq=13
+}
+P 2100 800 1800 800 1 0 0
+{
+T 2100 800 5 10 0 0 0 0 1
+pintype=pwr
+T 1745 795 5 10 1 1 0 6 1
+pinlabel=PSS
+T 1895 845 5 10 1 1 0 0 1
+pinnumber=7
+T 2100 800 5 10 0 0 0 0 1
+pinseq=14
+}
+P 2100 500 1800 500 1 0 0
+{
+T 2100 500 5 10 0 0 0 0 1
+pintype=pas
+T 1745 495 5 10 1 1 0 6 1
+pinlabel=VX
+T 1895 545 5 10 1 1 0 0 1
+pinnumber=8
+T 2100 500 5 10 0 0 0 0 1
+pinseq=15
+}
+P 2100 200 1800 200 1 0 0
+{
+T 2100 200 5 10 0 0 0 0 1
+pintype=pas
+T 1745 195 5 10 1 1 0 6 1
+pinlabel=CP5
+T 1895 245 5 10 1 1 0 0 1
+pinnumber=9
+T 2100 200 5 10 0 0 0 0 1
+pinseq=16
+}
+T 1000 3200 8 10 0 1 0 0 1
+device=ADXRS453
+T 1300 2800 8 10 0 1 0 0 1
+description=Analog Devices ADXRS453 gyro
+T 1500 2600 8 10 1 1 0 0 1
+refdes=U?
+T -400 2900 8 10 0 1 0 0 1
+numslots=1
+T 400 2600 9 10 1 0 0 0 1
+ADXRS453

diff --git a/bbb_cape/schematic/symbols/AM26LV32E-1.sym b/bbb_cape/schematic/symbols/AM26LV32E-1.sym
new file mode 100644
index 0000000..a155259
--- /dev/null
+++ b/bbb_cape/schematic/symbols/AM26LV32E-1.sym

@@ -0,0 +1,190 @@
+v 20110115 2
+P 1800 2300 1500 2300 1 0 0
+{
+T 1800 2300 5 10 0 0 0 0 1
+pintype=in
+T 1445 2295 5 10 1 1 0 6 1
+pinlabel=1A
+T 1595 2345 5 10 1 1 0 0 1
+pinnumber=2
+T 1800 2300 5 10 0 0 0 0 1
+pinseq=7
+}
+P 1800 2000 1500 2000 1 0 0
+{
+T 1800 2000 5 10 0 0 0 0 1
+pintype=in
+T 1445 1995 5 10 1 1 0 6 1
+pinlabel=1B
+T 1595 2045 5 10 1 1 0 0 1
+pinnumber=1
+T 1800 2000 5 10 0 0 0 0 1
+pinseq=9
+}
+P 1800 1700 1500 1700 1 0 0
+{
+T 1800 1700 5 10 0 0 0 0 1
+pintype=in
+T 1445 1695 5 10 1 1 0 6 1
+pinlabel=2A
+T 1595 1745 5 10 1 1 0 0 1
+pinnumber=6
+T 1800 1700 5 10 0 0 0 0 1
+pinseq=11
+}
+P 1800 1400 1500 1400 1 0 0
+{
+T 1800 1400 5 10 0 0 0 0 1
+pintype=in
+T 1445 1395 5 10 1 1 0 6 1
+pinlabel=2B
+T 1595 1445 5 10 1 1 0 0 1
+pinnumber=7
+T 1800 1400 5 10 0 0 0 0 1
+pinseq=12
+}
+P 1800 800 1500 800 1 0 0
+{
+T 1800 800 5 10 0 0 0 0 1
+pintype=in
+T 1445 795 5 10 1 1 0 6 1
+pinlabel=3B
+T 1595 845 5 10 1 1 0 0 1
+pinnumber=9
+T 1800 800 5 10 0 0 0 0 1
+pinseq=14
+}
+P 1800 500 1500 500 1 0 0
+{
+T 1800 500 5 10 0 0 0 0 1
+pintype=in
+T 1445 495 5 10 1 1 0 6 1
+pinlabel=4A
+T 1595 545 5 10 1 1 0 0 1
+pinnumber=14
+T 1800 500 5 10 0 0 0 0 1
+pinseq=15
+}
+P 1800 200 1500 200 1 0 0
+{
+T 1800 200 5 10 0 0 0 0 1
+pintype=in
+T 1445 195 5 10 1 1 0 6 1
+pinlabel=4B
+T 1595 245 5 10 1 1 0 0 1
+pinnumber=15
+T 1800 200 5 10 0 0 0 0 1
+pinseq=16
+}
+P 1800 1100 1500 1100 1 0 0
+{
+T 1800 1100 5 10 0 0 0 0 1
+pintype=in
+T 1445 1095 5 10 1 1 0 6 1
+pinlabel=3A
+T 1595 1145 5 10 1 1 0 0 1
+pinnumber=10
+T 1800 1100 5 10 0 0 0 0 1
+pinseq=13
+}
+B 300 0 1200 2500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 0 2300 300 2300 1 0 0
+{
+T 0 2300 5 10 0 0 0 0 1
+pintype=out
+T 355 2295 5 10 1 1 0 0 1
+pinlabel=1Y
+T 205 2345 5 10 1 1 0 6 1
+pinnumber=3
+T 0 2300 5 10 0 0 0 0 1
+pinseq=1
+}
+P 0 2000 300 2000 1 0 0
+{
+T 0 2000 5 10 0 0 0 0 1
+pintype=out
+T 355 1995 5 10 1 1 0 0 1
+pinlabel=2Y
+T 205 2045 5 10 1 1 0 6 1
+pinnumber=5
+T 0 2000 5 10 0 0 0 0 1
+pinseq=2
+}
+P 0 1700 300 1700 1 0 0
+{
+T 0 1700 5 10 0 0 0 0 1
+pintype=out
+T 355 1695 5 10 1 1 0 0 1
+pinlabel=3Y
+T 205 1745 5 10 1 1 0 6 1
+pinnumber=11
+T 0 1700 5 10 0 0 0 0 1
+pinseq=3
+}
+P 0 1400 300 1400 1 0 0
+{
+T 0 1400 5 10 0 0 0 0 1
+pintype=out
+T 355 1395 5 10 1 1 0 0 1
+pinlabel=4Y
+T 205 1445 5 10 1 1 0 6 1
+pinnumber=13
+T 0 1400 5 10 0 0 0 0 1
+pinseq=4
+}
+P 0 1100 300 1100 1 0 0
+{
+T 0 1100 5 10 0 0 0 0 1
+pintype=in
+T 355 1095 5 10 1 1 0 0 1
+pinlabel=ENABLE
+T 205 1145 5 10 1 1 0 6 1
+pinnumber=4
+T 0 1100 5 10 0 0 0 0 1
+pinseq=5
+}
+P 0 800 300 800 1 0 0
+{
+T 0 800 5 10 0 0 0 0 1
+pintype=in
+T 355 795 5 10 1 1 0 0 1
+pinlabel=\_ENABLE\_
+T 205 845 5 10 1 1 0 6 1
+pinnumber=12
+T 0 800 5 10 0 0 0 0 1
+pinseq=6
+}
+P 0 500 300 500 1 0 0
+{
+T 0 500 5 10 0 0 0 0 1
+pintype=pwr
+T 355 495 5 10 1 1 0 0 1
+pinlabel=GND
+T 205 545 5 10 1 1 0 6 1
+pinnumber=8
+T 0 500 5 10 0 0 0 0 1
+pinseq=8
+}
+P 0 200 300 200 1 0 0
+{
+T 0 200 5 10 0 0 0 0 1
+pintype=pwr
+T 355 195 5 10 1 1 0 0 1
+pinlabel=VCC
+T 205 245 5 10 1 1 0 6 1
+pinnumber=16
+T 0 200 5 10 0 0 0 0 1
+pinseq=10
+}
+T -600 2200 8 10 0 1 0 0 1
+device=AM26LV32E
+T -800 2000 8 10 0 1 0 0 1
+description=TI AM26LV32E LOW-VOLTAGE HIGH-SPEED QUADRUPLE DIFFERENTIAL LINE RECEIVER
+T -1400 1700 8 10 0 1 0 0 1
+footprint=TSSOP16
+T 1300 2600 8 10 1 1 0 0 1
+refdes=U?
+T -600 1200 8 10 0 1 0 0 1
+numslots=0
+T 200 2600 9 10 1 0 0 0 1
+AM26LV32E

diff --git a/bbb_cape/schematic/symbols/MCP3008-ISL-1.sym b/bbb_cape/schematic/symbols/MCP3008-ISL-1.sym
new file mode 100644
index 0000000..2627b4e
--- /dev/null
+++ b/bbb_cape/schematic/symbols/MCP3008-ISL-1.sym

@@ -0,0 +1,190 @@
+v 20110115 2
+B 300 0 1900 2400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 2500 1600 2200 1600 1 0 0
+{
+T 2500 1600 5 10 0 0 0 0 1
+pintype=pwr
+T 2145 1595 5 10 1 1 0 6 1
+pinlabel=DVDD
+T 2295 1645 5 10 1 1 0 0 1
+pinnumber=16
+T 2500 1600 5 10 0 0 0 0 1
+pinseq=0
+}
+P 2500 1300 2200 1300 1 0 0
+{
+T 2500 1300 5 10 0 0 0 0 1
+pintype=pwr
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+pinlabel=DGND
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diff --git a/bbb_cape/schematic/symbols/STM32F2-1.sym b/bbb_cape/schematic/symbols/STM32F2-1.sym
new file mode 100644
index 0000000..aee47d1
--- /dev/null
+++ b/bbb_cape/schematic/symbols/STM32F2-1.sym

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+T 205 2145 5 10 1 1 0 6 1
+pinnumber=19
+T 0 2100 5 10 0 0 0 0 1
+pinseq=59
+}
+P 0 1700 300 1700 1 0 0
+{
+T 0 1700 5 10 0 0 0 0 1
+pintype=pwr
+T 355 1695 5 10 1 1 0 0 1
+pinlabel=VDD 3
+T 205 1745 5 10 1 1 0 6 1
+pinnumber=64
+T 0 1700 5 10 0 0 0 0 1
+pinseq=60
+}
+P 0 1300 300 1300 1 0 0
+{
+T 0 1300 5 10 0 0 0 0 1
+pintype=pwr
+T 355 1295 5 10 1 1 0 0 1
+pinlabel=VSS 3
+T 205 1345 5 10 1 1 0 6 1
+pinnumber=63
+T 0 1300 5 10 0 0 0 0 1
+pinseq=61
+}
+P 0 900 300 900 1 0 0
+{
+T 0 900 5 10 0 0 0 0 1
+pintype=pwr
+T 355 895 5 10 1 1 0 0 1
+pinlabel=VSS 4
+T 205 945 5 10 1 1 0 6 1
+pinnumber=18
+T 0 900 5 10 0 0 0 0 1
+pinseq=62
+}
+P 0 500 300 500 1 0 0
+{
+T 0 500 5 10 0 0 0 0 1
+pintype=pwr
+T 355 495 5 10 1 1 0 0 1
+pinlabel=VDD analog
+T 205 545 5 10 1 1 0 6 1
+pinnumber=13
+T 0 500 5 10 0 0 0 0 1
+pinseq=63
+}
+P 0 100 300 100 1 0 0
+{
+T 0 100 5 10 0 0 0 0 1
+pintype=pwr
+T 355 95 5 10 1 1 0 0 1
+pinlabel=VSS analog
+T 205 145 5 10 1 1 0 6 1
+pinnumber=12
+T 0 100 5 10 0 0 0 0 1
+pinseq=64
+}
+T 13100 11700 8 10 0 1 0 0 1
+device=STM32F2
+T 13100 11700 8 10 0 1 0 0 1
+description=STM32F2 (or STM32F4)
+T 10400 12900 8 10 0 1 0 0 1
+footprint=LQFP64_10
+T 1700 12100 8 10 1 1 0 0 1
+refdes=U?
+T 16000 7300 8 10 0 1 0 0 1
+numslots=0
+T 1400 12400 9 10 1 0 0 0 1
+STM32F2

diff --git a/bbb_cape/schematic/symbols/TC1262-1.sym b/bbb_cape/schematic/symbols/TC1262-1.sym
new file mode 100644
index 0000000..1cdbc5c
--- /dev/null
+++ b/bbb_cape/schematic/symbols/TC1262-1.sym

@@ -0,0 +1,58 @@
+v 20110115 2
+T -8000 4300 8 10 0 1 0 0 1
+footprint=SOT223
+B 300 0 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 0 500 300 500 1 0 0
+{
+T 0 500 5 10 0 0 0 0 1
+pintype=pwr
+T 355 495 5 10 1 1 0 0 1
+pinlabel=VIN
+T 205 545 5 10 1 1 0 6 1
+pinnumber=1
+T 0 500 5 10 0 0 0 0 1
+pinseq=1
+}
+P 0 200 300 200 1 0 0
+{
+T 0 200 5 10 0 0 0 0 1
+pintype=pwr
+T 355 195 5 10 1 1 0 0 1
+pinlabel=VOUT
+T 205 245 5 10 1 1 0 6 1
+pinnumber=3
+T 0 200 5 10 0 0 0 0 1
+pinseq=2
+}
+P 2100 500 1800 500 1 0 0
+{
+T 2100 500 5 10 0 0 0 0 1
+pintype=pwr
+T 1745 495 5 10 1 1 0 6 1
+pinlabel=GND
+T 1895 545 5 10 1 1 0 0 1
+pinnumber=2
+T 2100 500 5 10 0 0 0 0 1
+pinseq=3
+}
+P 2100 200 1800 200 1 0 0
+{
+T 2100 200 5 10 0 0 0 0 1
+pintype=pwr
+T 1745 195 5 10 1 1 0 6 1
+pinlabel=PAD
+T 1895 245 5 10 1 1 0 0 1
+pinnumber=4
+T 2100 200 5 10 0 0 0 0 1
+pinseq=4
+}
+T 1500 900 8 10 0 1 0 0 1
+device=TC1262
+T 1500 900 8 10 0 1 0 0 1
+description=500mA Fixed Output CMOS LDO
+T 1400 800 8 10 1 1 0 0 1
+refdes=U?
+T 1900 1000 8 10 0 1 0 0 1
+numslots=1
+T 500 800 9 10 1 0 0 0 1
+TC1262

diff --git a/bbb_cape/schematic/symbols/adc_buffer-1.sym b/bbb_cape/schematic/symbols/adc_buffer-1.sym
new file mode 100644
index 0000000..d23bea0
--- /dev/null
+++ b/bbb_cape/schematic/symbols/adc_buffer-1.sym

@@ -0,0 +1,124 @@
+v 20110115 2
+B 400 0 1700 1300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 0 1100 400 1100 1 0 0
+{
+T 0 1100 5 10 0 0 0 0 1
+pintype=in
+T 455 1095 5 10 1 1 0 0 1
+pinlabel=IN1
+T 305 1145 5 10 0 1 0 6 1
+pinnumber=IN1
+T 0 1100 5 10 0 0 0 0 1
+pinseq=1
+}
+P 0 800 400 800 1 0 0
+{
+T 0 800 5 10 0 0 0 0 1
+pintype=in
+T 455 795 5 10 1 1 0 0 1
+pinlabel=IN2
+T 305 845 5 10 0 1 0 6 1
+pinnumber=IN2
+T 0 800 5 10 0 0 0 0 1
+pinseq=2
+}
+P 0 500 400 500 1 0 0
+{
+T 0 500 5 10 0 0 0 0 1
+pintype=in
+T 455 495 5 10 1 1 0 0 1
+pinlabel=IN3
+T 305 545 5 10 0 1 0 6 1
+pinnumber=IN3
+T 0 500 5 10 0 0 0 0 1
+pinseq=3
+}
+P 0 200 400 200 1 0 0
+{
+T 0 200 5 10 0 0 0 0 1
+pintype=in
+T 455 195 5 10 1 1 0 0 1
+pinlabel=IN4
+T 305 245 5 10 0 1 0 6 1
+pinnumber=IN4
+T 0 200 5 10 0 0 0 0 1
+pinseq=4
+}
+P 1100 1600 1100 1300 1 0 0
+{
+T 1100 1600 5 10 0 0 0 0 1
+pintype=pwr
+T 1100 1245 5 10 1 1 90 6 1
+pinlabel=GND
+T 1050 1395 5 10 0 1 90 0 1
+pinnumber=GND
+T 1100 1600 5 10 0 0 0 0 1
+pinseq=5
+}
+P 1400 1600 1400 1300 1 0 0
+{
+T 1400 1600 5 10 0 0 0 0 1
+pintype=pwr
+T 1400 1245 5 10 1 1 90 6 1
+pinlabel=VCC
+T 1350 1395 5 10 0 1 90 0 1
+pinnumber=VCC
+T 1400 1600 5 10 0 0 0 0 1
+pinseq=0
+}
+P 2400 1100 2100 1100 1 0 0
+{
+T 2400 1100 5 10 0 0 0 0 1
+pintype=out
+T 2045 1095 5 10 1 1 0 6 1
+pinlabel=OUT1
+T 2195 1145 5 10 0 1 0 0 1
+pinnumber=OUT1
+T 2400 1100 5 10 0 0 0 0 1
+pinseq=7
+}
+P 2400 800 2100 800 1 0 0
+{
+T 2400 800 5 10 0 0 0 0 1
+pintype=out
+T 2045 795 5 10 1 1 0 6 1
+pinlabel=OUT2
+T 2195 845 5 10 0 1 0 0 1
+pinnumber=OUT2
+T 2400 800 5 10 0 0 0 0 1
+pinseq=8
+}
+P 2400 500 2100 500 1 0 0
+{
+T 2400 500 5 10 0 0 0 0 1
+pintype=out
+T 2045 495 5 10 1 1 0 6 1
+pinlabel=OUT3
+T 2195 545 5 10 0 1 0 0 1
+pinnumber=OUT3
+T 2400 500 5 10 0 0 0 0 1
+pinseq=9
+}
+P 2400 200 2100 200 1 0 0
+{
+T 2400 200 5 10 0 0 0 0 1
+pintype=out
+T 2045 195 5 10 1 1 0 6 1
+pinlabel=OUT4
+T 2195 245 5 10 0 1 0 0 1
+pinnumber=OUT4
+T 2400 200 5 10 0 0 0 0 1
+pinseq=10
+}
+T 2700 1500 8 10 0 1 0 0 1
+device=ADC buffer
+T 900 1900 8 10 0 1 0 0 1
+description=buffer for voltage clamping ADC inputs
+T 1200 1900 8 10 0 1 0 0 1
+source=adc_buffer.sch
+T 1700 1400 8 10 1 1 0 0 1
+refdes=X?
+T 1400 1900 8 10 0 1 0 0 1
+numslots=1
+T 100 1400 9 10 1 0 0 0 1
+ADC buffer

diff --git a/bbb_cape/schematic/symbols/beaglebone-1.sym b/bbb_cape/schematic/symbols/beaglebone-1.sym
new file mode 100644
index 0000000..c2f9a56
--- /dev/null
+++ b/bbb_cape/schematic/symbols/beaglebone-1.sym

@@ -0,0 +1,1030 @@
+v 20110115 2
+P 8700 18500 8400 18500 1 0 0
+{
+T 8500 18550 5 8 1 1 0 0 1
+pinnumber=1
+T 8500 18450 5 8 0 1 0 2 1
+pinseq=1
+T 8350 18500 9 8 1 1 0 6 1
+pinlabel=GND
+T 8350 18500 5 8 0 1 0 8 1
+pintype=pwr
+}
+P 8700 18100 8400 18100 1 0 0
+{
+T 8500 18150 5 8 1 1 0 0 1
+pinnumber=2
+T 8500 18050 5 8 0 1 0 2 1
+pinseq=2
+T 8350 18100 9 8 1 1 0 6 1
+pinlabel=GND
+T 8350 18100 5 8 0 1 0 8 1
+pintype=pwr
+}
+P 8700 17700 8400 17700 1 0 0
+{
+T 8500 17750 5 8 1 1 0 0 1
+pinnumber=3
+T 8500 17650 5 8 0 1 0 2 1
+pinseq=3
+T 8350 17700 9 8 1 1 0 6 1
+pinlabel=(R9) GPIO1_6
+T 8350 17700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 17300 8400 17300 1 0 0
+{
+T 8500 17350 5 8 1 1 0 0 1
+pinnumber=4
+T 8500 17250 5 8 0 1 0 2 1
+pinseq=4
+T 8350 17300 9 8 1 1 0 6 1
+pinlabel=(T9) GPIO1_7
+T 8350 17300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 16900 8400 16900 1 0 0
+{
+T 8500 16950 5 8 1 1 0 0 1
+pinnumber=5
+T 8500 16850 5 8 0 1 0 2 1
+pinseq=5
+T 8350 16900 9 8 1 1 0 6 1
+pinlabel=(R8) GPIO1_2
+T 8350 16900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 16500 8400 16500 1 0 0
+{
+T 8500 16550 5 8 1 1 0 0 1
+pinnumber=6
+T 8500 16450 5 8 0 1 0 2 1
+pinseq=6
+T 8350 16500 9 8 1 1 0 6 1
+pinlabel=(T8) GPIO1_3
+T 8350 16500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 16100 8400 16100 1 0 0
+{
+T 8500 16150 5 8 1 1 0 0 1
+pinnumber=7
+T 8500 16050 5 8 0 1 0 2 1
+pinseq=7
+T 8350 16100 9 8 1 1 0 6 1
+pinlabel=(R7) TIMER4
+T 8350 16100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 15700 8400 15700 1 0 0
+{
+T 8500 15750 5 8 1 1 0 0 1
+pinnumber=8
+T 8500 15650 5 8 0 1 0 2 1
+pinseq=8
+T 8350 15700 9 8 1 1 0 6 1
+pinlabel=(T7) TIMER7
+T 8350 15700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 15300 8400 15300 1 0 0
+{
+T 8500 15350 5 8 1 1 0 0 1
+pinnumber=9
+T 8500 15250 5 8 0 1 0 2 1
+pinseq=9
+T 8350 15300 9 8 1 1 0 6 1
+pinlabel=(T6) TIMER5
+T 8350 15300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 14900 8400 14900 1 0 0
+{
+T 8500 14950 5 8 1 1 0 0 1
+pinnumber=10
+T 8500 14850 5 8 0 1 0 2 1
+pinseq=10
+T 8350 14900 9 8 1 1 0 6 1
+pinlabel=(U6) TIMER6
+T 8350 14900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 14500 8400 14500 1 0 0
+{
+T 8500 14550 5 8 1 1 0 0 1
+pinnumber=11
+T 8500 14450 5 8 0 1 0 2 1
+pinseq=11
+T 8350 14500 9 8 1 1 0 6 1
+pinlabel=(R12) GPIO1_13
+T 8350 14500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 14100 8400 14100 1 0 0
+{
+T 8500 14150 5 8 1 1 0 0 1
+pinnumber=12
+T 8500 14050 5 8 0 1 0 2 1
+pinseq=12
+T 8350 14100 9 8 1 1 0 6 1
+pinlabel=(T12) GPIO1_12
+T 8350 14100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 13700 8400 13700 1 0 0
+{
+T 8500 13750 5 8 1 1 0 0 1
+pinnumber=13
+T 8500 13650 5 8 0 1 0 2 1
+pinseq=13
+T 8350 13700 9 8 1 1 0 6 1
+pinlabel=(T10) EHRPWM2B
+T 8350 13700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 13300 8400 13300 1 0 0
+{
+T 8500 13350 5 8 1 1 0 0 1
+pinnumber=14
+T 8500 13250 5 8 0 1 0 2 1
+pinseq=14
+T 8350 13300 9 8 1 1 0 6 1
+pinlabel=(T11) GPIO0_26
+T 8350 13300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 12900 8400 12900 1 0 0
+{
+T 8500 12950 5 8 1 1 0 0 1
+pinnumber=15
+T 8500 12850 5 8 0 1 0 2 1
+pinseq=15
+T 8350 12900 9 8 1 1 0 6 1
+pinlabel=(U13) GPIO1_15
+T 8350 12900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 12500 8400 12500 1 0 0
+{
+T 8500 12550 5 8 1 1 0 0 1
+pinnumber=16
+T 8500 12450 5 8 0 1 0 2 1
+pinseq=16
+T 8350 12500 9 8 1 1 0 6 1
+pinlabel=(V13) GPIO1_14
+T 8350 12500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 12100 8400 12100 1 0 0
+{
+T 8500 12150 5 8 1 1 0 0 1
+pinnumber=17
+T 8500 12050 5 8 0 1 0 2 1
+pinseq=17
+T 8350 12100 9 8 1 1 0 6 1
+pinlabel=(U12) GPIO0_27
+T 8350 12100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 11700 8400 11700 1 0 0
+{
+T 8500 11750 5 8 1 1 0 0 1
+pinnumber=18
+T 8500 11650 5 8 0 1 0 2 1
+pinseq=18
+T 8350 11700 9 8 1 1 0 6 1
+pinlabel=(V12) GPIO2_1
+T 8350 11700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 11300 8400 11300 1 0 0
+{
+T 8500 11350 5 8 1 1 0 0 1
+pinnumber=19
+T 8500 11250 5 8 0 1 0 2 1
+pinseq=19
+T 8350 11300 9 8 1 1 0 6 1
+pinlabel=(U10) EHRPWM2A
+T 8350 11300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 10900 8400 10900 1 0 0
+{
+T 8500 10950 5 8 1 1 0 0 1
+pinnumber=20
+T 8500 10850 5 8 0 1 0 2 1
+pinseq=20
+T 8350 10900 9 8 1 1 0 6 1
+pinlabel=(V9) GPIO1_31
+T 8350 10900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 10500 8400 10500 1 0 0
+{
+T 8500 10550 5 8 1 1 0 0 1
+pinnumber=21
+T 8500 10450 5 8 0 1 0 2 1
+pinseq=21
+T 8350 10500 9 8 1 1 0 6 1
+pinlabel=(U9) GPIO1_30
+T 8350 10500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 10100 8400 10100 1 0 0
+{
+T 8500 10150 5 8 1 1 0 0 1
+pinnumber=22
+T 8500 10050 5 8 0 1 0 2 1
+pinseq=22
+T 8350 10100 9 8 1 1 0 6 1
+pinlabel=(V8) GPIO1_5
+T 8350 10100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 9700 8400 9700 1 0 0
+{
+T 8500 9750 5 8 1 1 0 0 1
+pinnumber=23
+T 8500 9650 5 8 0 1 0 2 1
+pinseq=23
+T 8350 9700 9 8 1 1 0 6 1
+pinlabel=(U8) GPIO1_4
+T 8350 9700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 9300 8400 9300 1 0 0
+{
+T 8500 9350 5 8 1 1 0 0 1
+pinnumber=24
+T 8500 9250 5 8 0 1 0 2 1
+pinseq=24
+T 8350 9300 9 8 1 1 0 6 1
+pinlabel=(V7) GPIO1_1
+T 8350 9300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 8900 8400 8900 1 0 0
+{
+T 8500 8950 5 8 1 1 0 0 1
+pinnumber=25
+T 8500 8850 5 8 0 1 0 2 1
+pinseq=25
+T 8350 8900 9 8 1 1 0 6 1
+pinlabel=(U7) GPIO1_0
+T 8350 8900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 8500 8400 8500 1 0 0
+{
+T 8500 8550 5 8 1 1 0 0 1
+pinnumber=26
+T 8500 8450 5 8 0 1 0 2 1
+pinseq=26
+T 8350 8500 9 8 1 1 0 6 1
+pinlabel=(V6) GPIO1_29
+T 8350 8500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 8100 8400 8100 1 0 0
+{
+T 8500 8150 5 8 1 1 0 0 1
+pinnumber=27
+T 8500 8050 5 8 0 1 0 2 1
+pinseq=27
+T 8350 8100 9 8 1 1 0 6 1
+pinlabel=(U5) GPIO2_22
+T 8350 8100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 7700 8400 7700 1 0 0
+{
+T 8500 7750 5 8 1 1 0 0 1
+pinnumber=28
+T 8500 7650 5 8 0 1 0 2 1
+pinseq=28
+T 8350 7700 9 8 1 1 0 6 1
+pinlabel=(V5) GPIO2_24
+T 8350 7700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 7300 8400 7300 1 0 0
+{
+T 8500 7350 5 8 1 1 0 0 1
+pinnumber=29
+T 8500 7250 5 8 0 1 0 2 1
+pinseq=29
+T 8350 7300 9 8 1 1 0 6 1
+pinlabel=(R5) GPIO2_23
+T 8350 7300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 6900 8400 6900 1 0 0
+{
+T 8500 6950 5 8 1 1 0 0 1
+pinnumber=30
+T 8500 6850 5 8 0 1 0 2 1
+pinseq=30
+T 8350 6900 9 8 1 1 0 6 1
+pinlabel=(R6) GPIO2_25
+T 8350 6900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 6500 8400 6500 1 0 0
+{
+T 8500 6550 5 8 1 1 0 0 1
+pinnumber=31
+T 8500 6450 5 8 0 1 0 2 1
+pinseq=31
+T 8350 6500 9 8 1 1 0 6 1
+pinlabel=(V4) UART5_CTSN
+T 8350 6500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 6100 8400 6100 1 0 0
+{
+T 8500 6150 5 8 1 1 0 0 1
+pinnumber=32
+T 8500 6050 5 8 0 1 0 2 1
+pinseq=32
+T 8350 6100 9 8 1 1 0 6 1
+pinlabel=(T5) UART5_RTSN
+T 8350 6100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 5700 8400 5700 1 0 0
+{
+T 8500 5750 5 8 1 1 0 0 1
+pinnumber=33
+T 8500 5650 5 8 0 1 0 2 1
+pinseq=33
+T 8350 5700 9 8 1 1 0 6 1
+pinlabel=(V3) UART4_RTSN
+T 8350 5700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 5300 8400 5300 1 0 0
+{
+T 8500 5350 5 8 1 1 0 0 1
+pinnumber=34
+T 8500 5250 5 8 0 1 0 2 1
+pinseq=34
+T 8350 5300 9 8 1 1 0 6 1
+pinlabel=(U4) UART3_RTSN
+T 8350 5300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 4900 8400 4900 1 0 0
+{
+T 8500 4950 5 8 1 1 0 0 1
+pinnumber=35
+T 8500 4850 5 8 0 1 0 2 1
+pinseq=35
+T 8350 4900 9 8 1 1 0 6 1
+pinlabel=(V2) UART4_CTSN
+T 8350 4900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 4500 8400 4500 1 0 0
+{
+T 8500 4550 5 8 1 1 0 0 1
+pinnumber=36
+T 8500 4450 5 8 0 1 0 2 1
+pinseq=36
+T 8350 4500 9 8 1 1 0 6 1
+pinlabel=(U3) UART3_CTSN
+T 8350 4500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 4100 8400 4100 1 0 0
+{
+T 8500 4150 5 8 1 1 0 0 1
+pinnumber=37
+T 8500 4050 5 8 0 1 0 2 1
+pinseq=37
+T 8350 4100 9 8 1 1 0 6 1
+pinlabel=(U1) UART5_TXD
+T 8350 4100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 3700 8400 3700 1 0 0
+{
+T 8500 3750 5 8 1 1 0 0 1
+pinnumber=38
+T 8500 3650 5 8 0 1 0 2 1
+pinseq=38
+T 8350 3700 9 8 1 1 0 6 1
+pinlabel=(U2) UART5_RXD
+T 8350 3700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 3300 8400 3300 1 0 0
+{
+T 8500 3350 5 8 1 1 0 0 1
+pinnumber=39
+T 8500 3250 5 8 0 1 0 2 1
+pinseq=39
+T 8350 3300 9 8 1 1 0 6 1
+pinlabel=(T3) GPIO2_12
+T 8350 3300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 2900 8400 2900 1 0 0
+{
+T 8500 2950 5 8 1 1 0 0 1
+pinnumber=40
+T 8500 2850 5 8 0 1 0 2 1
+pinseq=40
+T 8350 2900 9 8 1 1 0 6 1
+pinlabel=(T4) GPIO2_13
+T 8350 2900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 2500 8400 2500 1 0 0
+{
+T 8500 2550 5 8 1 1 0 0 1
+pinnumber=41
+T 8500 2450 5 8 0 1 0 2 1
+pinseq=41
+T 8350 2500 9 8 1 1 0 6 1
+pinlabel=(T1) GPIO2_10
+T 8350 2500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 2100 8400 2100 1 0 0
+{
+T 8500 2150 5 8 1 1 0 0 1
+pinnumber=42
+T 8500 2050 5 8 0 1 0 2 1
+pinseq=42
+T 8350 2100 9 8 1 1 0 6 1
+pinlabel=(T2) GPIO2_11
+T 8350 2100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 1700 8400 1700 1 0 0
+{
+T 8500 1750 5 8 1 1 0 0 1
+pinnumber=43
+T 8500 1650 5 8 0 1 0 2 1
+pinseq=43
+T 8350 1700 9 8 1 1 0 6 1
+pinlabel=(R3) GPIO2_8
+T 8350 1700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 1300 8400 1300 1 0 0
+{
+T 8500 1350 5 8 1 1 0 0 1
+pinnumber=44
+T 8500 1250 5 8 0 1 0 2 1
+pinseq=44
+T 8350 1300 9 8 1 1 0 6 1
+pinlabel=(R4) GPIO2_9
+T 8350 1300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 900 8400 900 1 0 0
+{
+T 8500 950 5 8 1 1 0 0 1
+pinnumber=45
+T 8500 850 5 8 0 1 0 2 1
+pinseq=45
+T 8350 900 9 8 1 1 0 6 1
+pinlabel=(R1) GPIO2_6
+T 8350 900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 500 8400 500 1 0 0
+{
+T 8500 550 5 8 1 1 0 0 1
+pinnumber=46
+T 8500 450 5 8 0 1 0 2 1
+pinseq=46
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+pinlabel=(R2) GPIO2_7
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+pintype=io
+}
+P 100 18500 400 18500 1 0 0
+{
+T 300 18550 5 8 1 1 0 6 1
+pinnumber=47
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+pinlabel=(1) GND
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+}
+P 100 18100 400 18100 1 0 0
+{
+T 300 18150 5 8 1 1 0 6 1
+pinnumber=48
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+pinseq=2
+T 450 18100 9 8 1 1 0 0 1
+pinlabel=(2) GND
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+}
+P 100 17700 400 17700 1 0 0
+{
+T 300 17750 5 8 1 1 0 6 1
+pinnumber=49
+T 300 17650 5 8 0 1 0 8 1
+pinseq=3
+T 450 17700 9 8 1 1 0 0 1
+pinlabel=(3) DC_3.3V
+T 450 17700 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 17300 400 17300 1 0 0
+{
+T 300 17350 5 8 1 1 0 6 1
+pinnumber=50
+T 300 17250 5 8 0 1 0 8 1
+pinseq=4
+T 450 17300 9 8 1 1 0 0 1
+pinlabel=(4) DC_3.3V
+T 450 17300 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 16900 400 16900 1 0 0
+{
+T 300 16950 5 8 1 1 0 6 1
+pinnumber=51
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+pinseq=5
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+pinlabel=(5) VDD_5V
+T 450 16900 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 16500 400 16500 1 0 0
+{
+T 300 16550 5 8 1 1 0 6 1
+pinnumber=52
+T 300 16450 5 8 0 1 0 8 1
+pinseq=6
+T 450 16500 9 8 1 1 0 0 1
+pinlabel=(6) VDD_5V
+T 450 16500 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 16100 400 16100 1 0 0
+{
+T 300 16150 5 8 1 1 0 6 1
+pinnumber=53
+T 300 16050 5 8 0 1 0 8 1
+pinseq=7
+T 450 16100 9 8 1 1 0 0 1
+pinlabel=(7) SYS_5V
+T 450 16100 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 15700 400 15700 1 0 0
+{
+T 300 15750 5 8 1 1 0 6 1
+pinnumber=54
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+pinseq=8
+T 450 15700 9 8 1 1 0 0 1
+pinlabel=(8) SYS_5V
+T 450 15700 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 15300 400 15300 1 0 0
+{
+T 300 15350 5 8 1 1 0 6 1
+pinnumber=55
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+pinseq=9
+T 450 15300 9 8 1 1 0 0 1
+pinlabel=(9) PWR_BUT
+T 450 15300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 14900 400 14900 1 0 0
+{
+T 300 14950 5 8 1 1 0 6 1
+pinnumber=56
+T 300 14850 5 8 0 1 0 8 1
+pinseq=10
+T 450 14900 9 8 1 1 0 0 1
+pinlabel=(10) SYS_RESETn (A10)
+T 450 14900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 14500 400 14500 1 0 0
+{
+T 300 14550 5 8 1 1 0 6 1
+pinnumber=57
+T 300 14450 5 8 0 1 0 8 1
+pinseq=57
+T 450 14500 9 8 1 1 0 0 1
+pinlabel=(11) UART4_RXD (T17)
+T 450 14500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 14100 400 14100 1 0 0
+{
+T 300 14150 5 8 1 1 0 6 1
+pinnumber=58
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+pinseq=58
+T 450 14100 9 8 1 1 0 0 1
+pinlabel=(12) GPIO1_28 (U18)
+T 450 14100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 13700 400 13700 1 0 0
+{
+T 300 13750 5 8 1 1 0 6 1
+pinnumber=59
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+pinseq=59
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+pinlabel=(13) UART4_TXD (U17)
+T 450 13700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 13300 400 13300 1 0 0
+{
+T 300 13350 5 8 1 1 0 6 1
+pinnumber=60
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+pinseq=60
+T 450 13300 9 8 1 1 0 0 1
+pinlabel=(14) EHRPWM1A (U14)
+T 450 13300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 12900 400 12900 1 0 0
+{
+T 300 12950 5 8 1 1 0 6 1
+pinnumber=61
+T 300 12850 5 8 0 1 0 8 1
+pinseq=61
+T 450 12900 9 8 1 1 0 0 1
+pinlabel=(15) GPIO1_16 (R13)
+T 450 12900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 12500 400 12500 1 0 0
+{
+T 300 12550 5 8 1 1 0 6 1
+pinnumber=62
+T 300 12450 5 8 0 1 0 8 1
+pinseq=62
+T 450 12500 9 8 1 1 0 0 1
+pinlabel=(16) EHRPWM1B (T14)
+T 450 12500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 12100 400 12100 1 0 0
+{
+T 300 12150 5 8 1 1 0 6 1
+pinnumber=63
+T 300 12050 5 8 0 1 0 8 1
+pinseq=63
+T 450 12100 9 8 1 1 0 0 1
+pinlabel=(17) I2C1_SCL (A16)
+T 450 12100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 11700 400 11700 1 0 0
+{
+T 300 11750 5 8 1 1 0 6 1
+pinnumber=64
+T 300 11650 5 8 0 1 0 8 1
+pinseq=64
+T 450 11700 9 8 1 1 0 0 1
+pinlabel=(18) I2C1_SDA (B16)
+T 450 11700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 11300 400 11300 1 0 0
+{
+T 300 11350 5 8 1 1 0 6 1
+pinnumber=65
+T 300 11250 5 8 0 1 0 8 1
+pinseq=65
+T 450 11300 9 8 1 1 0 0 1
+pinlabel=(19) I2C2_SCL (D17)
+T 450 11300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 10900 400 10900 1 0 0
+{
+T 300 10950 5 8 1 1 0 6 1
+pinnumber=66
+T 300 10850 5 8 0 1 0 8 1
+pinseq=66
+T 450 10900 9 8 1 1 0 0 1
+pinlabel=(20) I2C2_SDA (D18)
+T 450 10900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 10500 400 10500 1 0 0
+{
+T 300 10550 5 8 1 1 0 6 1
+pinnumber=67
+T 300 10450 5 8 0 1 0 8 1
+pinseq=67
+T 450 10500 9 8 1 1 0 0 1
+pinlabel=(21) UART2_TXD (B17)
+T 450 10500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 10100 400 10100 1 0 0
+{
+T 300 10150 5 8 1 1 0 6 1
+pinnumber=68
+T 300 10050 5 8 0 1 0 8 1
+pinseq=68
+T 450 10100 9 8 1 1 0 0 1
+pinlabel=(22) UART2_RXD (A17)
+T 450 10100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 9700 400 9700 1 0 0
+{
+T 300 9750 5 8 1 1 0 6 1
+pinnumber=69
+T 300 9650 5 8 0 1 0 8 1
+pinseq=69
+T 450 9700 9 8 1 1 0 0 1
+pinlabel=(23) GPIO1_17 (V14)
+T 450 9700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 9300 400 9300 1 0 0
+{
+T 300 9350 5 8 1 1 0 6 1
+pinnumber=70
+T 300 9250 5 8 0 1 0 8 1
+pinseq=70
+T 450 9300 9 8 1 1 0 0 1
+pinlabel=(24) UART1_TXD (D15)
+T 450 9300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 8900 400 8900 1 0 0
+{
+T 300 8950 5 8 1 1 0 6 1
+pinnumber=71
+T 300 8850 5 8 0 1 0 8 1
+pinseq=71
+T 450 8900 9 8 1 1 0 0 1
+pinlabel=(25) GPIO3_21 (A14)
+T 450 8900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 8500 400 8500 1 0 0
+{
+T 300 8550 5 8 1 1 0 6 1
+pinnumber=72
+T 300 8450 5 8 0 1 0 8 1
+pinseq=72
+T 450 8500 9 8 1 1 0 0 1
+pinlabel=(26) UART1_RXD (D16)
+T 450 8500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 8100 400 8100 1 0 0
+{
+T 300 8150 5 8 1 1 0 6 1
+pinnumber=73
+T 300 8050 5 8 0 1 0 8 1
+pinseq=73
+T 450 8100 9 8 1 1 0 0 1
+pinlabel=(27) GPIO3_19 (C13)
+T 450 8100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 7700 400 7700 1 0 0
+{
+T 300 7750 5 8 1 1 0 6 1
+pinnumber=74
+T 300 7650 5 8 0 1 0 8 1
+pinseq=74
+T 450 7700 9 8 1 1 0 0 1
+pinlabel=(28) SPI1_CS0 (C12)
+T 450 7700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 7300 400 7300 1 0 0
+{
+T 300 7350 5 8 1 1 0 6 1
+pinnumber=75
+T 300 7250 5 8 0 1 0 8 1
+pinseq=75
+T 450 7300 9 8 1 1 0 0 1
+pinlabel=(29) SPI1_D0 (B13)
+T 450 7300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 6900 400 6900 1 0 0
+{
+T 300 6950 5 8 1 1 0 6 1
+pinnumber=76
+T 300 6850 5 8 0 1 0 8 1
+pinseq=76
+T 450 6900 9 8 1 1 0 0 1
+pinlabel=(30) SPI1_D1 (D12)
+T 450 6900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 6500 400 6500 1 0 0
+{
+T 300 6550 5 8 1 1 0 6 1
+pinnumber=77
+T 300 6450 5 8 0 1 0 8 1
+pinseq=77
+T 450 6500 9 8 1 1 0 0 1
+pinlabel=(31) SPI1_SCLK (A13)
+T 450 6500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 6100 400 6100 1 0 0
+{
+T 300 6150 5 8 1 1 0 6 1
+pinnumber=78
+T 300 6050 5 8 0 1 0 8 1
+pinseq=78
+T 450 6100 9 8 1 1 0 0 1
+pinlabel=(32) VADC
+T 450 6100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 5700 400 5700 1 0 0
+{
+T 300 5750 5 8 1 1 0 6 1
+pinnumber=79
+T 300 5650 5 8 0 1 0 8 1
+pinseq=79
+T 450 5700 9 8 1 1 0 0 1
+pinlabel=(33) AIN4 (C8)
+T 450 5700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 5300 400 5300 1 0 0
+{
+T 300 5350 5 8 1 1 0 6 1
+pinnumber=80
+T 300 5250 5 8 0 1 0 8 1
+pinseq=80
+T 450 5300 9 8 1 1 0 0 1
+pinlabel=(34) AGND
+T 450 5300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 4900 400 4900 1 0 0
+{
+T 300 4950 5 8 1 1 0 6 1
+pinnumber=81
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+pinseq=81
+T 450 4900 9 8 1 1 0 0 1
+pinlabel=(35) AIN6 (A8)
+T 450 4900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 4500 400 4500 1 0 0
+{
+T 300 4550 5 8 1 1 0 6 1
+pinnumber=82
+T 300 4450 5 8 0 1 0 8 1
+pinseq=82
+T 450 4500 9 8 1 1 0 0 1
+pinlabel=(36) AIN5 (B8)
+T 450 4500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 4100 400 4100 1 0 0
+{
+T 300 4150 5 8 1 1 0 6 1
+pinnumber=83
+T 300 4050 5 8 0 1 0 8 1
+pinseq=83
+T 450 4100 9 8 1 1 0 0 1
+pinlabel=(37) AIN2 (B7)
+T 450 4100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 3700 400 3700 1 0 0
+{
+T 300 3750 5 8 1 1 0 6 1
+pinnumber=84
+T 300 3650 5 8 0 1 0 8 1
+pinseq=84
+T 450 3700 9 8 1 1 0 0 1
+pinlabel=(38) AIN3 (A7)
+T 450 3700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 3300 400 3300 1 0 0
+{
+T 300 3350 5 8 1 1 0 6 1
+pinnumber=85
+T 300 3250 5 8 0 1 0 8 1
+pinseq=85
+T 450 3300 9 8 1 1 0 0 1
+pinlabel=(39) AIN0 (B6)
+T 450 3300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2900 400 2900 1 0 0
+{
+T 300 2950 5 8 1 1 0 6 1
+pinnumber=86
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+pinseq=86
+T 450 2900 9 8 1 1 0 0 1
+pinlabel=(40) AIN1 (C7)
+T 450 2900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2500 400 2500 1 0 0
+{
+T 300 2550 5 8 1 1 0 6 1
+pinnumber=87
+T 300 2450 5 8 0 1 0 8 1
+pinseq=87
+T 450 2500 9 8 1 1 0 0 1
+pinlabel=(41) CLKOUT2 (D14)
+T 450 2500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2100 400 2100 1 0 0
+{
+T 300 2150 5 8 1 1 0 6 1
+pinnumber=88
+T 300 2050 5 8 0 1 0 8 1
+pinseq=88
+T 450 2100 9 8 1 1 0 0 1
+pinlabel=(42) GPIO0_7 (C18)
+T 450 2100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 1700 400 1700 1 0 0
+{
+T 300 1750 5 8 1 1 0 6 1
+pinnumber=89
+T 300 1650 5 8 0 1 0 8 1
+pinseq=89
+T 450 1700 9 8 1 1 0 0 1
+pinlabel=(43) GND
+T 450 1700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 1300 400 1300 1 0 0
+{
+T 300 1350 5 8 1 1 0 6 1
+pinnumber=90
+T 300 1250 5 8 0 1 0 8 1
+pinseq=90
+T 450 1300 9 8 1 1 0 0 1
+pinlabel=(44) GND
+T 450 1300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 900 400 900 1 0 0
+{
+T 300 950 5 8 1 1 0 6 1
+pinnumber=91
+T 300 850 5 8 0 1 0 8 1
+pinseq=91
+T 450 900 9 8 1 1 0 0 1
+pinlabel=(45) GND
+T 450 900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 500 400 500 1 0 0
+{
+T 300 550 5 8 1 1 0 6 1
+pinnumber=92
+T 300 450 5 8 0 1 0 8 1
+pinseq=92
+T 450 500 9 8 1 1 0 0 1
+pinlabel=(46) GND
+T 450 500 5 8 0 1 0 2 1
+pintype=io
+}
+B 400 100 8000 18800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 8400 19000 8 10 1 1 0 6 1
+refdes=U?
+T 3400 18550 9 10 1 0 0 0 1
+BEAGLEBONE BLACK CAPE
+T 4200 9850 5 10 0 0 0 0 1
+device=BEAGLEBOND BLACK CAPE
+T 4200 10050 5 10 0 0 0 0 1
+footprint=beaglebone
+T 4200 10650 5 10 0 0 0 0 1
+description=TI Sitara AM335x powered development board
+T 4200 10850 5 10 0 0 0 0 1
+numslots=0
+T 1300 18500 3 10 1 0 0 0 1
+P9
+T 7500 18500 3 10 1 0 0 0 1
+P8

diff --git a/bbb_cape/schematic/symbols/crystal.sym b/bbb_cape/schematic/symbols/crystal.sym
new file mode 100644
index 0000000..17dcee8
--- /dev/null
+++ b/bbb_cape/schematic/symbols/crystal.sym

@@ -0,0 +1,62 @@
+v 20110115 2
+P 500 400 800 400 1 0 0
+{
+T 650 450 5 8 1 1 0 6 1
+pinnumber=1
+T 750 350 5 8 0 1 0 8 1
+pinseq=1
+T 850 400 9 8 0 1 0 0 1
+pinlabel=1
+T 850 400 5 8 0 1 0 2 1
+pintype=pas
+}
+P 1100 400 1400 400 1 0 1
+{
+T 1250 450 5 8 1 1 0 0 1
+pinnumber=3
+T 1250 350 5 8 0 1 0 2 1
+pinseq=3
+T 1150 400 9 8 0 1 0 6 1
+pinlabel=3
+T 1150 400 5 8 0 1 0 8 1
+pintype=pas
+}
+B 850 300 200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 200 500 5 10 0 0 0 0 1
+device=CRYSTAL
+L 800 540 800 260 3 0 0 0 -1 -1
+L 1100 540 1100 260 3 0 0 0 -1 -1
+T 800 700 8 10 1 1 0 0 1
+refdes=U?
+T 200 1100 5 10 0 0 0 0 1
+description=crystal
+T 200 900 5 10 0 0 0 0 1
+numslots=0
+T 200 700 5 10 0 0 0 0 1
+symversion=0.1
+P 700 200 500 200 1 0 1
+{
+T 656 248 5 8 1 1 0 6 1
+pinnumber=2
+T 650 150 5 8 0 1 0 8 1
+pinseq=2
+T 755 195 9 8 0 1 0 0 1
+pinlabel=2
+T 750 200 5 8 0 1 0 2 1
+pintype=gnd
+}
+L 1200 600 700 600 3 0 0 0 -1 -1
+P 1200 200 1400 200 1 0 1
+{
+T 1250 250 5 8 1 1 0 0 1
+pinnumber=4
+T 1250 150 5 8 0 1 0 2 1
+pinseq=4
+T 1150 200 9 8 0 1 0 6 1
+pinlabel=4
+T 1150 200 5 8 0 1 0 8 1
+pintype=pwr
+}
+L 700 600 700 200 3 0 0 0 -1 -1
+L 700 200 1200 200 3 0 0 0 -1 -1
+L 1200 200 1200 600 3 0 0 0 -1 -1

diff --git a/bbb_cape/schematic/symbols/digital-input-1.sym b/bbb_cape/schematic/symbols/digital-input-1.sym
new file mode 100644
index 0000000..ac015c8
--- /dev/null
+++ b/bbb_cape/schematic/symbols/digital-input-1.sym

@@ -0,0 +1,47 @@
+v 20110115 2
+B 300 0 1700 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 0 500 300 500 1 0 0
+{
+T 0 500 5 10 0 0 0 0 1
+pintype=pwr
+T 355 495 5 10 1 1 0 0 1
+pinlabel=SGND
+T 205 545 5 10 0 1 0 6 1
+pinnumber=SGND
+T 0 500 5 10 0 0 0 0 1
+pinseq=1
+}
+P 0 200 300 200 1 0 0
+{
+T 0 200 5 10 0 0 0 0 1
+pintype=pwr
+T 355 195 5 10 1 1 0 0 1
+pinlabel=SVCC
+T 205 245 5 10 0 1 0 6 1
+pinnumber=SVCC
+T 0 200 5 10 0 0 0 0 1
+pinseq=2
+}
+P 2300 300 2000 300 1 0 0
+{
+T 2300 300 5 10 0 0 0 0 1
+pintype=out
+T 1945 295 5 10 1 1 0 6 1
+pinlabel=OUT
+T 2095 345 5 10 0 1 0 0 1
+pinnumber=OUT
+T 2300 300 5 10 0 0 0 0 1
+pinseq=3
+}
+T 2500 900 8 10 0 1 0 0 1
+device=encoder-input
+T 1400 1000 8 10 0 1 0 0 1
+description=1 encoder input
+T 2900 700 8 10 0 1 0 0 1
+source=encoder input.sch
+T 1700 800 8 10 1 1 0 0 1
+refdes=X?
+T 2900 400 8 10 0 1 0 0 1
+numslots=1
+T 400 800 9 10 1 0 0 0 1
+digital input

diff --git a/bbb_cape/schematic/symbols/digital-input-x4-1.sym b/bbb_cape/schematic/symbols/digital-input-x4-1.sym
new file mode 100644
index 0000000..650855d
--- /dev/null
+++ b/bbb_cape/schematic/symbols/digital-input-x4-1.sym

@@ -0,0 +1,113 @@
+v 20110115 2
+B 300 300 2000 1500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 2600 1400 2300 1400 1 0 0
+{
+T 2600 1400 5 10 0 0 0 0 1
+pintype=out
+T 2245 1395 5 10 1 1 0 6 1
+pinlabel=OUT0
+T 2395 1445 5 10 0 1 0 0 1
+pinnumber=OUT0
+T 2600 1400 5 10 0 0 0 0 1
+pinseq=1
+}
+P 2600 1100 2300 1100 1 0 0
+{
+T 2600 1100 5 10 0 0 0 0 1
+pintype=out
+T 2245 1095 5 10 1 1 0 6 1
+pinlabel=OUT1
+T 2395 1145 5 10 0 1 0 0 1
+pinnumber=OUT1
+T 2600 1100 5 10 0 0 0 0 1
+pinseq=2
+}
+P 2600 800 2300 800 1 0 0
+{
+T 2600 800 5 10 0 0 0 0 1
+pintype=out
+T 2245 795 5 10 1 1 0 6 1
+pinlabel=OUT2
+T 2395 845 5 10 0 1 0 0 1
+pinnumber=OUT2
+T 2600 800 5 10 0 0 0 0 1
+pinseq=3
+}
+P 2600 500 2300 500 1 0 0
+{
+T 2600 500 5 10 0 0 0 0 1
+pintype=out
+T 2245 495 5 10 1 1 0 6 1
+pinlabel=OUT3
+T 2395 545 5 10 0 1 0 0 1
+pinnumber=OUT3
+T 2600 500 5 10 0 0 0 0 1
+pinseq=4
+}
+P 0 1400 300 1400 1 0 0
+{
+T 0 1400 5 10 0 0 0 0 1
+pintype=pwr
+T 355 1395 5 10 1 1 0 0 1
+pinlabel=SGND
+T 205 1445 5 10 0 1 0 6 1
+pinnumber=SGND
+T 0 1400 5 10 0 0 0 0 1
+pinseq=5
+}
+P 0 1100 300 1100 1 0 0
+{
+T 0 1100 5 10 0 0 0 0 1
+pintype=pwr
+T 355 1095 5 10 1 1 0 0 1
+pinlabel=SVCC
+T 205 1145 5 10 0 1 0 6 1
+pinnumber=SVCC
+T 0 1100 5 10 0 0 0 0 1
+pinseq=6
+}
+P 0 800 300 800 1 0 0
+{
+T 0 800 5 10 0 0 0 0 1
+pintype=pwr
+T 355 795 5 10 1 1 0 0 1
+pinlabel=DGND
+T 205 845 5 10 0 1 0 6 1
+pinnumber=DGND
+T 0 800 5 10 0 0 0 0 1
+pinseq=7
+}
+P 0 500 300 500 1 0 0
+{
+T 0 500 5 10 0 0 0 0 1
+pintype=pwr
+T 355 495 5 10 1 1 0 0 1
+pinlabel=DVCC
+T 205 545 5 10 0 1 0 6 1
+pinnumber=DVCC
+T 0 500 5 10 0 0 0 0 1
+pinseq=0
+}
+T 1300 1500 8 10 0 1 0 0 1
+device=digital-input-x4
+T 1900 1600 8 10 0 1 0 0 1
+description=set of 4 digital inputs
+T 400 1600 8 10 1 1 0 0 1
+source=unknown
+T 2000 1900 8 10 1 1 0 0 1
+refdes=X?
+T 1200 1800 8 10 0 1 0 0 1
+numslots=1
+T 400 1900 9 10 1 0 0 0 1
+digital inputs x4
+P 1300 0 1300 300 1 0 0
+{
+T 1300 0 5 10 0 0 0 0 1
+pintype=in
+T 1300 355 5 10 1 1 90 0 1
+pinlabel=DIFFA
+T 1250 205 5 10 0 1 90 6 1
+pinnumber=DIFFA
+T 1300 0 5 10 0 0 0 0 1
+pinseq=9
+}

diff --git a/bbb_cape/schematic/symbols/diode-sot23.sym b/bbb_cape/schematic/symbols/diode-sot23.sym
new file mode 100644
index 0000000..c229137
--- /dev/null
+++ b/bbb_cape/schematic/symbols/diode-sot23.sym

@@ -0,0 +1,35 @@
+v 20110115 2
+L 300 400 300 0 3 0 0 0 -1 -1
+L 300 400 600 200 3 0 0 0 -1 -1
+T 400 600 5 10 0 0 0 0 1
+device=DIODE
+L 600 200 300 0 3 0 0 0 -1 -1
+L 600 400 600 0 3 0 0 0 -1 -1
+P 0 200 200 200 1 0 0
+{
+T 100 250 5 8 0 1 0 0 1
+pinnumber=1
+T 100 250 5 8 0 0 0 0 1
+pinseq=1
+T 100 250 5 8 0 1 0 0 1
+pinlabel=1
+T 100 250 5 8 0 1 0 0 1
+pintype=pas
+}
+P 900 200 700 200 1 0 0
+{
+T 700 250 5 8 0 1 0 0 1
+pinnumber=3
+T 700 250 5 8 0 0 0 0 1
+pinseq=3
+T 700 250 5 8 0 1 0 0 1
+pinlabel=3
+T 700 250 5 8 0 1 0 0 1
+pintype=pas
+}
+L 700 200 600 200 3 0 0 0 -1 -1
+L 300 200 200 200 3 0 0 0 -1 -1
+T 300 500 8 10 1 1 0 0 1
+refdes=D?
+T 195 700 8 10 0 1 0 0 1
+footprint=SOT23

diff --git a/bbb_cape/schematic/symbols/encoder-input-1.sym b/bbb_cape/schematic/symbols/encoder-input-1.sym
new file mode 100644
index 0000000..0db4194
--- /dev/null
+++ b/bbb_cape/schematic/symbols/encoder-input-1.sym

@@ -0,0 +1,58 @@
+v 20110115 2
+B 300 0 1700 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 0 500 300 500 1 0 0
+{
+T 0 500 5 10 0 0 0 0 1
+pintype=pwr
+T 355 495 5 10 1 1 0 0 1
+pinlabel=SGND
+T 205 545 5 10 0 1 0 6 1
+pinnumber=SGND
+T 0 500 5 10 0 0 0 0 1
+pinseq=1
+}
+P 0 200 300 200 1 0 0
+{
+T 0 200 5 10 0 0 0 0 1
+pintype=pwr
+T 355 195 5 10 1 1 0 0 1
+pinlabel=SVCC
+T 205 245 5 10 0 1 0 6 1
+pinnumber=SVCC
+T 0 200 5 10 0 0 0 0 1
+pinseq=2
+}
+P 2300 500 2000 500 1 0 0
+{
+T 2300 500 5 10 0 0 0 0 1
+pintype=out
+T 1945 495 5 10 1 1 0 6 1
+pinlabel=CH1
+T 2095 545 5 10 0 1 0 0 1
+pinnumber=CH1
+T 2300 500 5 10 0 0 0 0 1
+pinseq=3
+}
+T 2500 900 8 10 0 1 0 0 1
+device=encoder-input
+T 1400 1000 8 10 0 1 0 0 1
+description=1 encoder input
+T 2900 700 8 10 0 1 0 0 1
+source=encoder input.sch
+T 1700 800 8 10 1 1 0 0 1
+refdes=X?
+T 2900 400 8 10 0 1 0 0 1
+numslots=1
+T 400 800 9 10 1 0 0 0 1
+encoder input
+P 2300 200 2000 200 1 0 0
+{
+T 2300 200 5 10 0 0 0 0 1
+pintype=out
+T 1945 195 5 10 1 1 0 6 1
+pinlabel=CH2
+T 2095 245 5 10 0 1 0 0 1
+pinnumber=CH2
+T 2300 200 5 10 0 0 0 0 1
+pinseq=4
+}

diff --git a/bbb_cape/schematic/symbols/lmz12002-1.sym b/bbb_cape/schematic/symbols/lmz12002-1.sym
new file mode 100644
index 0000000..07d13f5
--- /dev/null
+++ b/bbb_cape/schematic/symbols/lmz12002-1.sym

@@ -0,0 +1,98 @@
+v 20110115 2
+B 0 200 3100 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 400 0 400 200 1 0 0
+{
+T 400 0 5 10 0 0 0 0 1
+pintype=pwr
+T 400 255 5 10 1 1 90 0 1
+pinlabel=VIN
+T 350 105 5 10 1 1 90 6 1
+pinnumber=1
+T 400 0 5 10 0 0 0 0 1
+pinseq=1
+}
+P 700 0 700 200 1 0 0
+{
+T 700 0 5 10 0 0 0 0 1
+pintype=in
+T 700 255 5 10 1 1 90 0 1
+pinlabel=RON
+T 650 105 5 10 1 1 90 6 1
+pinnumber=2
+T 700 0 5 10 0 0 0 0 1
+pinseq=2
+}
+P 1000 0 1000 200 1 0 0
+{
+T 1000 0 5 10 0 0 0 0 1
+pintype=in
+T 1000 255 5 10 1 1 90 0 1
+pinlabel=EN
+T 950 105 5 10 1 1 90 6 1
+pinnumber=3
+T 1000 0 5 10 0 0 0 0 1
+pinseq=3
+}
+P 1500 0 1500 200 1 0 0
+{
+T 1500 0 5 10 0 0 0 0 1
+pintype=pwr
+T 1500 255 5 10 1 1 90 0 1
+pinlabel=GND
+T 1450 105 5 10 1 1 90 6 1
+pinnumber=4
+T 1500 0 5 10 0 0 0 0 1
+pinseq=4
+}
+P 1800 0 1800 200 1 0 0
+{
+T 1800 0 5 10 0 0 0 0 1
+pintype=pwr
+T 1800 255 5 10 1 1 90 0 1
+pinlabel=PAD
+T 1750 105 5 10 1 1 90 6 1
+pinnumber=8
+T 1800 0 5 10 0 0 0 0 1
+pinseq=8
+}
+P 2300 0 2300 200 1 0 0
+{
+T 2300 0 5 10 0 0 0 0 1
+pintype=in
+T 2300 255 5 10 1 1 90 0 1
+pinlabel=SS
+T 2250 105 5 10 1 1 90 6 1
+pinnumber=5
+T 2300 0 5 10 0 0 0 0 1
+pinseq=5
+}
+P 2600 0 2600 200 1 0 0
+{
+T 2600 0 5 10 0 0 0 0 1
+pintype=in
+T 2600 255 5 10 1 1 90 0 1
+pinlabel=FB
+T 2550 105 5 10 1 1 90 6 1
+pinnumber=6
+T 2600 0 5 10 0 0 0 0 1
+pinseq=6
+}
+P 2900 0 2900 200 1 0 0
+{
+T 2900 0 5 10 0 0 0 0 1
+pintype=out
+T 2900 255 5 10 1 1 90 0 1
+pinlabel=VOUT
+T 2850 105 5 10 1 1 90 6 1
+pinnumber=7
+T 2900 0 5 10 0 0 0 0 1
+pinseq=7
+}
+T 500 900 8 10 1 1 0 0 1
+device=LMZ12002
+T 1900 900 8 10 1 1 0 0 1
+refdes=U?
+T 1100 1295 8 10 0 1 0 0 1
+footprint=TOPMOD
+T 900 1262 8 10 0 1 0 0 1
+numslots=0

diff --git a/bbb_cape/schematic/symbols/max3221-1.sym b/bbb_cape/schematic/symbols/max3221-1.sym
new file mode 100644
index 0000000..b67bd87
--- /dev/null
+++ b/bbb_cape/schematic/symbols/max3221-1.sym

@@ -0,0 +1,193 @@
+v 20110115 2
+T 350 8200 5 10 0 0 0 0 1
+device=MAX3221
+T 350 7900 5 10 0 0 0 0 1
+description=Maxim RS-232 transceiver with autoshutdown and ESD protection
+T 350 5500 5 10 0 0 0 0 1
+footprint=TSSOP16
+T 350 5200 5 10 0 0 0 0 1
+numslots=0
+T 2350 4200 8 10 1 1 0 6 1
+refdes=U?
+T 350 4150 9 10 1 0 0 0 1
+MAX3221
+B 300 0 2000 4100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 300 3700 0 3700 1 0 1
+{
+T 200 3750 5 8 1 1 0 6 1
+pinnumber=13
+T 200 3650 5 8 0 1 0 8 1
+pinseq=1
+T 350 3750 9 8 1 1 0 0 1
+pinlabel=DOUT
+T 350 3650 5 8 0 1 0 2 1
+pintype=out
+}
+P 2300 3700 2600 3700 1 0 1
+{
+T 2800 3750 5 8 1 1 0 6 1
+pinnumber=15
+T 2800 3650 5 8 0 1 0 8 1
+pinseq=2
+T 2950 3750 9 8 1 1 0 0 1
+pinlabel=VCC
+T 2950 3650 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 300 2100 0 2100 1 0 1
+{
+T 200 2150 5 8 1 1 0 6 1
+pinnumber=3
+T 200 2050 5 8 0 1 0 8 1
+pinseq=5
+T 350 2100 9 8 1 1 0 0 1
+pinlabel=V+
+T 350 2050 5 8 0 1 0 2 1
+pintype=pas
+}
+P 2300 2300 2600 2300 1 0 1
+{
+T 2550 2350 5 8 1 1 0 6 1
+pinnumber=9
+T 2550 2250 5 8 0 1 0 8 1
+pinseq=15
+T 2250 2350 9 8 1 1 0 6 1
+pinlabel=ROUT
+T 2250 2250 5 8 0 1 0 8 1
+pintype=out
+}
+P 200 2700 0 2700 1 0 1
+{
+T 200 2750 5 8 1 1 0 6 1
+pinnumber=10
+T 200 2650 5 8 0 1 0 8 1
+pinseq=4
+T 350 2750 9 8 1 1 0 0 1
+pinlabel=\_INVALID\_
+T 350 2650 5 8 0 1 0 2 1
+pintype=out
+}
+P 2300 1300 2600 1300 1 0 1
+{
+T 2550 1350 5 8 1 1 0 6 1
+pinnumber=4
+T 2550 1250 5 8 0 1 0 8 1
+pinseq=13
+T 2250 1300 9 8 1 1 0 6 1
+pinlabel=C1-
+T 2250 1250 5 8 0 1 0 8 1
+pintype=pas
+}
+P 2300 2700 2600 2700 1 0 1
+{
+T 2550 2750 5 8 1 1 0 6 1
+pinnumber=8
+T 2550 2650 5 8 0 1 0 8 1
+pinseq=16
+T 2250 2750 9 8 1 1 0 6 1
+pinlabel=RIN
+T 2250 2650 5 8 0 1 0 8 1
+pintype=in
+}
+P 2300 3300 2600 3300 1 0 1
+{
+T 2800 3350 5 8 1 1 0 6 1
+pinnumber=14
+T 2800 3250 5 8 0 1 0 8 1
+pinseq=3
+T 2950 3350 9 8 1 1 0 0 1
+pinlabel=GND
+T 2950 3250 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 300 1700 0 1700 1 0 1
+{
+T 200 1750 5 8 1 1 0 6 1
+pinnumber=7
+T 200 1650 5 8 0 1 0 8 1
+pinseq=6
+T 350 1700 9 8 1 1 0 0 1
+pinlabel=V-
+T 350 1650 5 8 0 1 0 2 1
+pintype=pas
+}
+V 250 1100 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 200 1100 0 1100 1 0 1
+{
+T 200 1150 5 8 1 1 0 6 1
+pinnumber=1
+T 200 1050 5 8 0 1 0 8 1
+pinseq=7
+T 350 1100 9 8 1 1 0 0 1
+pinlabel=\_EN\_
+T 350 1050 5 8 0 1 0 2 1
+pintype=in
+}
+P 2300 1700 2600 1700 1 0 1
+{
+T 2550 1750 5 8 1 1 0 6 1
+pinnumber=2
+T 2550 1650 5 8 0 1 0 8 1
+pinseq=14
+T 2250 1700 9 8 1 1 0 6 1
+pinlabel=C1+
+T 2250 1650 5 8 0 1 0 8 1
+pintype=pas
+}
+P 2300 500 2600 500 1 0 1
+{
+T 2550 550 5 8 1 1 0 6 1
+pinnumber=6
+T 2550 450 5 8 0 1 0 8 1
+pinseq=11
+T 2250 500 9 8 1 1 0 6 1
+pinlabel=C2-
+T 2250 450 5 8 0 1 0 8 1
+pintype=pas
+}
+P 2300 900 2600 900 1 0 1
+{
+T 2550 950 5 8 1 1 0 6 1
+pinnumber=5
+T 2550 850 5 8 0 1 0 8 1
+pinseq=12
+T 2250 900 9 8 1 1 0 6 1
+pinlabel=C2+
+T 2250 850 5 8 0 1 0 8 1
+pintype=pas
+}
+P 300 700 0 700 1 0 1
+{
+T 200 750 5 8 1 1 0 6 1
+pinnumber=12
+T 200 650 5 8 0 1 0 8 1
+pinseq=8
+T 350 700 9 8 1 1 0 0 1
+pinlabel=FORCEON
+T 350 650 5 8 0 1 0 2 1
+pintype=in
+}
+V 250 300 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 200 300 0 300 1 0 1
+{
+T 200 350 5 8 1 1 0 6 1
+pinnumber=16
+T 200 250 5 8 0 1 0 8 1
+pinseq=9
+T 350 300 9 8 1 1 0 0 1
+pinlabel=\_FORCEOFF\_
+T 350 250 5 8 0 1 0 2 1
+pintype=in
+}
+V 250 2700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 300 3300 0 3300 1 0 1
+{
+T 550 3350 5 8 1 1 0 6 1
+pinnumber=11
+T 550 3250 5 8 0 1 0 8 1
+pinseq=10
+T 250 3300 9 8 1 1 0 6 1
+pinlabel=DIN
+T 250 3250 5 8 0 1 0 8 1
+pintype=in
+}

diff --git a/bbb_cape/schematic/symbols/regulator-1.sym b/bbb_cape/schematic/symbols/regulator-1.sym
new file mode 100644
index 0000000..b08f11c
--- /dev/null
+++ b/bbb_cape/schematic/symbols/regulator-1.sym

@@ -0,0 +1,45 @@
+v 20110115 2
+B 0 500 2000 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 200 1500 9 10 1 0 0 0 1
+Power Regulator
+P 500 200 500 500 1 0 0
+{
+T 500 200 5 10 0 0 0 0 1
+pintype=pwr
+T 500 555 5 10 1 1 90 0 1
+pinlabel=GND
+T 450 405 5 10 0 1 90 6 1
+pinnumber=GND
+T 500 200 5 10 0 0 0 0 1
+pinseq=1
+}
+P 1000 200 1000 500 1 0 0
+{
+T 1000 200 5 10 0 0 0 0 1
+pintype=pwr
+T 1000 555 5 10 1 1 90 0 1
+pinlabel=VIN
+T 950 405 5 10 0 1 90 6 1
+pinnumber=VIN
+T 1000 200 5 10 0 0 0 0 1
+pinseq=2
+}
+T -1100 700 8 10 0 1 0 0 1
+device=regulator
+T -700 1300 8 10 0 1 0 0 1
+description=voltage regulator
+T 800 1300 8 10 1 1 0 0 1
+refdes=X?
+P 1500 200 1500 500 1 0 0
+{
+T 1500 200 5 10 0 0 0 0 1
+pintype=pwr
+T 1500 555 5 10 1 1 90 0 1
+pinlabel=VOUT
+T 1450 405 5 10 0 1 90 6 1
+pinnumber=VOUT
+T 1500 200 5 10 0 0 0 0 1
+pinseq=0
+}
+T 0 1100 8 10 1 1 0 0 1
+source=unknown

diff --git a/bbb_cape/src/bbb/bbb.gyp b/bbb_cape/src/bbb/bbb.gyp
new file mode 100644
index 0000000..a2d62ea
--- /dev/null
+++ b/bbb_cape/src/bbb/bbb.gyp

@@ -0,0 +1,14 @@
+{
+  'targets': [
+    {
+      'target_name': 'crc',
+      'type': 'static_library',
+      'dependencies': [
+        '<(AOS)/common/common.gyp:once',
+      ],
+      'sources': [
+        'crc.cc',
+      ],
+    },
+  ],
+}

diff --git a/bbb_cape/src/bbb/crc.cc b/bbb_cape/src/bbb/crc.cc
new file mode 100644
index 0000000..b770f37
--- /dev/null
+++ b/bbb_cape/src/bbb/crc.cc

@@ -0,0 +1,42 @@
+#include "bbb/crc.h"
+
+#include "aos/common/once.h"
+
+// There are various implementations that look a lot like this scattered around
+// the internet.
+
+namespace cape {
+namespace {
+
+const uint32_t kPolynomial = 0x04c11db7;
+
+const uint32_t *GenerateTable() {
+  static uint32_t table[256];
+
+  for (int i = 0; i < 256; ++i) {
+    uint32_t c = i << 24;
+    for (int j = 8; j > 0; --j) {
+      c = c & 0x80000000 ? ((c << 1) ^ kPolynomial) : (c << 1);
+    }
+    table[i] = c;
+  }
+
+  return table;
+}
+
+}  // namespace
+
+uint32_t CalculateChecksum(uint8_t *data, size_t length) {
+  static ::aos::once<const uint32_t> table_once(GenerateTable);
+  const uint32_t *const table = table_once.Get();
+
+  uint32_t r = 0xFFFFFFFF;
+
+  for (size_t i = 0; i < length; ++i) {
+    r = (r << 8) ^ table[(r >> 24) ^ data[i]];
+  }
+
+  return ~r;
+}
+
+}  // namespace cape

diff --git a/bbb_cape/src/bbb/crc.h b/bbb_cape/src/bbb/crc.h
new file mode 100644
index 0000000..b353efc
--- /dev/null
+++ b/bbb_cape/src/bbb/crc.h

@@ -0,0 +1,14 @@
+#ifndef BBB_CRC_H_
+#define BBB_CRC_H_
+
+#include <stdint.h>
+
+namespace cape {
+
+// Calculates a CRC32 checksum for data. This is definitely the same one as the
+// cape MCU does in hardware which seems to be the same one as Ethernet etc use.
+uint32_t CalculateChecksum(uint8_t *data, size_t length);
+
+}  // namespace cape
+
+#endif  // BBB_CRC_H_

diff --git a/bbb_cape/src/cape/.gitignore b/bbb_cape/src/cape/.gitignore
new file mode 100644
index 0000000..01dd76a
--- /dev/null
+++ b/bbb_cape/src/cape/.gitignore

@@ -0,0 +1 @@
+.obj/

diff --git a/bbb_cape/src/cape/CMSIS/STM32F2XX.h b/bbb_cape/src/cape/CMSIS/STM32F2XX.h
new file mode 100644
index 0000000..0f676b0
--- /dev/null
+++ b/bbb_cape/src/cape/CMSIS/STM32F2XX.h

@@ -0,0 +1,6720 @@
+/**
+  ******************************************************************************
+  * @file    stm32f2xx.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32F2xx devices.
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheralÂ’s registers hardware
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+#ifndef __STM32F2xx_H
+#define __STM32F2xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/**
+ * @brief STM32F2Xxx Standard Peripherals Library version number V1.0.0
+   */
+#define __STM32F2XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  
+#define __STM32F2XX_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
+#define __STM32F2XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F2XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F2XX_STDPERIPH_VERSION        ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__STM32F2XX_STDPERIPH_VERSION_RC))
+                                             
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+#define __MPU_PRESENT             1 /*!< STM32F2XX provide an MPU */
+#define __NVIC_PRIO_BITS          4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @brief STM32F2XX Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */ 
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
+  HASH_RNG_IRQn               = 80      /*!< Hash and Rng global interrupt                                     */
+} IRQn_Type;
+
+#include "core_cm3.h"
+#include <stdint.h>
+
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef const int32_t sc32;  /*!< Read Only */
+typedef const int16_t sc16;  /*!< Read Only */
+typedef const int8_t sc8;   /*!< Read Only */
+
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef __I int32_t vsc32;  /*!< Read Only */
+typedef __I int16_t vsc16;  /*!< Read Only */
+typedef __I int8_t vsc8;   /*!< Read Only */
+
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef const uint32_t uc32;  /*!< Read Only */
+typedef const uint16_t uc16;  /*!< Read Only */
+typedef const uint8_t uc8;   /*!< Read Only */
+
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef __I uint32_t vuc32;  /*!< Read Only */
+typedef __I uint16_t vuc16;  /*!< Read Only */
+typedef __I uint8_t vuc8;   /*!< Read Only */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
+  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
+  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
+  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
+  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
+  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
+  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
+  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
+  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
+  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
+  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
+  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
+                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+  
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+  
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+  
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
+  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
+  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
+  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/** 
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;             /*    8 */
+  uint32_t      RESERVED0[2];
+  __IO uint32_t MACRWUFFR;             /*   11 */
+  __IO uint32_t MACPMTCSR;
+  uint32_t      RESERVED1[2];
+  __IO uint32_t MACSR;                 /*   15 */
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;               /*   24 */
+  uint32_t      RESERVED2[40];
+  __IO uint32_t MMCCR;                 /*   65 */
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;               /*   69 */
+  uint32_t      RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;            /*   84 */
+  __IO uint32_t MMCTGFMSCCR;
+  uint32_t      RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+  uint32_t      RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+  uint32_t      RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+  uint32_t      RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+  __IO uint32_t RESERVED8;
+  __IO uint32_t PTPTSSR;  /* added for STM32F2xx */
+  uint32_t      RESERVED9[565];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+  __IO uint32_t DMARSWTR;  /* added for STM32F2xx */
+  uint32_t      RESERVED10[8];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
+  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
+  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
+  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
+  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;      /*!< FLASH access control register, Address offset: 0x00 */
+  __IO uint32_t KEYR;     /*!< FLASH key register,            Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,     Address offset: 0x08 */
+  __IO uint32_t SR;       /*!< FLASH status register,         Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< FLASH control register,        Address offset: 0x10 */
+  __IO uint32_t OPTCR;    /*!< FLASH option control register, Address offset: 0x14 */
+} FLASH_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
+} FSMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Static Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank2
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
+} FSMC_Bank2_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank3
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
+  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
+  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
+  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
+} FSMC_Bank3_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank4
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
+  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
+  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
+  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
+  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
+} FSMC_Bank4_TypeDef; 
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint16_t BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */
+  __IO uint16_t BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x24-0x28 */
+} GPIO_TypeDef;
+
+/** 
+  * @brief System configuration controller
+  */
+  
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
+  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                   */
+  __IO uint16_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                   */
+  __IO uint16_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                   */
+  __IO uint16_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                   */
+  __IO uint16_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                   */
+  __IO uint16_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                   */
+  __IO uint16_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                   */
+  __IO uint16_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
+  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                   */
+  __IO uint16_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
+  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                   */
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
+  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
+  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
+  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
+  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
+  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
+  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
+  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
+  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
+  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
+  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
+  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
+  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
+  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
+  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
+  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
+  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
+  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
+  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
+  uint32_t RESERVED1;    /*!< Reserved, 0x28                                                                 */
+  uint32_t RESERVED2;    /*!< Reserved, 0x2C                                                                 */
+  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  uint32_t RESERVED3;    /*!< Reserved, 0x38                                                                 */
+  uint32_t RESERVED4;    /*!< Reserved, 0x3C                                                                 */
+  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  uint32_t RESERVED5;    /*!< Reserved, 0x44                                                                 */
+  uint32_t RESERVED6;    /*!< Reserved, 0x48                                                                 */
+  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
+  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
+  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
+  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
+  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
+  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
+  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
+  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
+  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
+  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
+  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
+  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
+  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
+  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
+  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
+  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
+  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
+} RTC_TypeDef;
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                           */
+  __IO uint16_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                           */
+  __IO uint16_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                           */
+  __IO uint16_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                           */
+  __IO uint16_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                           */
+  __IO uint16_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                           */
+  __IO uint16_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                           */
+  __IO uint16_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
+  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                                           */
+  __IO uint16_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
+  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                                           */
+} SPI_TypeDef;
+
+typedef struct
+{
+  __IO uint16_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  uint16_t      RESERVED0;   /*!< Reserved, 0x02                                            */
+  __IO uint16_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  uint16_t      RESERVED1;   /*!< Reserved, 0x06                                            */
+  __IO uint16_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  uint16_t      RESERVED2;   /*!< Reserved, 0x0A                                            */
+  __IO uint16_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  uint16_t      RESERVED3;   /*!< Reserved, 0x0E                                            */
+  __IO uint16_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  uint16_t      RESERVED4;   /*!< Reserved, 0x12                                            */
+  __IO uint16_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  uint16_t      RESERVED5;   /*!< Reserved, 0x16                                            */
+  __IO uint16_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  uint16_t      RESERVED6;   /*!< Reserved, 0x1A                                            */
+  __IO uint16_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  uint16_t      RESERVED7;   /*!< Reserved, 0x1E                                            */
+  __IO uint16_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  uint16_t      RESERVED8;   /*!< Reserved, 0x22                                            */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint16_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  uint16_t      RESERVED9;   /*!< Reserved, 0x2A                                            */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint16_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  uint16_t      RESERVED10;  /*!< Reserved, 0x32                                            */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint16_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  uint16_t      RESERVED11;  /*!< Reserved, 0x46                                            */
+  __IO uint16_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  uint16_t      RESERVED12;  /*!< Reserved, 0x4A                                            */
+  __IO uint16_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  uint16_t      RESERVED13;  /*!< Reserved, 0x4E                                            */
+  __IO uint16_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+  uint16_t      RESERVED14;  /*!< Reserved, 0x52                                            */
+} TIM_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint16_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                */
+  __IO uint16_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                */
+  __IO uint16_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                */
+  __IO uint16_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                */
+  __IO uint16_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                */
+  __IO uint16_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                */
+  __IO uint16_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                */
+} USART_TypeDef;
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** 
+  * @brief Crypto Processor
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< CRYP control register,                            Address offset: 0x00 */
+  __IO uint32_t SR;     /*!< CRYP status register,                             Address offset: 0x04 */
+  __IO uint32_t DR;     /*!< CRYP data input register,                         Address offset: 0x08 */
+  __IO uint32_t DOUT;   /*!< CRYP data output register,                        Address offset: 0x0C */
+  __IO uint32_t DMACR;  /*!< CRYP DMA control register,                        Address offset: 0x10 */
+  __IO uint32_t IMSCR;  /*!< CRYP interrupt mask set/clear register,           Address offset: 0x14 */
+  __IO uint32_t RISR;   /*!< CRYP raw interrupt status register,               Address offset: 0x18 */
+  __IO uint32_t MISR;   /*!< CRYP masked interrupt status register,            Address offset: 0x1C */
+  __IO uint32_t K0LR;   /*!< CRYP key left  register 0,                        Address offset: 0x20 */
+  __IO uint32_t K0RR;   /*!< CRYP key right register 0,                        Address offset: 0x24 */
+  __IO uint32_t K1LR;   /*!< CRYP key left  register 1,                        Address offset: 0x28 */
+  __IO uint32_t K1RR;   /*!< CRYP key right register 1,                        Address offset: 0x2C */
+  __IO uint32_t K2LR;   /*!< CRYP key left  register 2,                        Address offset: 0x30 */
+  __IO uint32_t K2RR;   /*!< CRYP key right register 2,                        Address offset: 0x34 */
+  __IO uint32_t K3LR;   /*!< CRYP key left  register 3,                        Address offset: 0x38 */
+  __IO uint32_t K3RR;   /*!< CRYP key right register 3,                        Address offset: 0x3C */
+  __IO uint32_t IV0LR;  /*!< CRYP initialization vector left-word  register 0, Address offset: 0x40 */
+  __IO uint32_t IV0RR;  /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
+  __IO uint32_t IV1LR;  /*!< CRYP initialization vector left-word  register 1, Address offset: 0x48 */
+  __IO uint32_t IV1RR;  /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
+} CRYP_TypeDef;
+
+typedef struct 
+{
+  __IO uint32_t CR;        /*!< HASH control register,          Address offset: 0x00        */
+  __IO uint32_t DIN;       /*!< HASH data input register,       Address offset: 0x04        */
+  __IO uint32_t STR;       /*!< HASH start register,            Address offset: 0x08        */
+  __IO uint32_t HR[5];     /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
+  __IO uint32_t IMR;       /*!< HASH interrupt enable register, Address offset: 0x20        */
+  __IO uint32_t SR;        /*!< HASH status register,           Address offset: 0x24        */
+  uint32_t  RESERVED[52];  /*!< Reserved, 0x28-0xF4                                         */
+  __IO uint32_t CSR[51];   /*!< HASH context swap registers,    Address offset: 0x0F8-0x1C0 */  
+} HASH_TypeDef;
+
+typedef struct 
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00) 
+#define BKPSRAM_BASE          (AHB1PERIPH_BASE + 0x4000)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)
+#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000)
+#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
+#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060)
+#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080)
+#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           ((uint32_t )0xE0042000)
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH                ((HASH_TypeDef *) HASH_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
+#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!<End of conversion */
+#define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          ((uint8_t)0x20)               /*!<Overrun flag */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         /*!<overrun interrupt enable */
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!<Start Conversion of regular channels */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */
+
+/*******************  Bit definition for ADC_CSR register  ********************/
+#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        /*!<ADC3 DMA overrun  flag */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */
+
+/*******************  Bit definition for ADC_CDR register  ********************/
+#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */
+#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */
+#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */
+#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */
+#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */
+#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */
+#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
+
+#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
+
+#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
+
+#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
+
+#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
+#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
+#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
+#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
+#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
+#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */
+#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */
+#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */
+#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */
+#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */
+#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */
+#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */
+#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */
+#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */
+#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */
+#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */
+#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */
+#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */
+#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */
+#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */
+#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */
+#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */
+#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */
+#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */
+#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */
+#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */
+#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */
+#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */
+#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */
+#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */
+#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */
+#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */
+#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Crypto Processor                                */
+/*                                                                            */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register  ********************/
+#define CRYP_CR_ALGODIR                      ((uint32_t)0x00000004)
+
+#define CRYP_CR_ALGOMODE                     ((uint32_t)0x00000038)
+#define CRYP_CR_ALGOMODE_0                   ((uint32_t)0x00000008)
+#define CRYP_CR_ALGOMODE_1                   ((uint32_t)0x00000010)
+#define CRYP_CR_ALGOMODE_2                   ((uint32_t)0x00000020)
+#define CRYP_CR_ALGOMODE_TDES_ECB            ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_CBC            ((uint32_t)0x00000008)
+#define CRYP_CR_ALGOMODE_DES_ECB             ((uint32_t)0x00000010)
+#define CRYP_CR_ALGOMODE_DES_CBC             ((uint32_t)0x00000018)
+#define CRYP_CR_ALGOMODE_AES_ECB             ((uint32_t)0x00000020)
+#define CRYP_CR_ALGOMODE_AES_CBC             ((uint32_t)0x00000028)
+#define CRYP_CR_ALGOMODE_AES_CTR             ((uint32_t)0x00000030)
+#define CRYP_CR_ALGOMODE_AES_KEY             ((uint32_t)0x00000038)
+
+#define CRYP_CR_DATATYPE                     ((uint32_t)0x000000C0)
+#define CRYP_CR_DATATYPE_0                   ((uint32_t)0x00000040)
+#define CRYP_CR_DATATYPE_1                   ((uint32_t)0x00000080)
+#define CRYP_CR_KEYSIZE                      ((uint32_t)0x00000300)
+#define CRYP_CR_KEYSIZE_0                    ((uint32_t)0x00000100)
+#define CRYP_CR_KEYSIZE_1                    ((uint32_t)0x00000200)
+#define CRYP_CR_FFLUSH                       ((uint32_t)0x00004000)
+#define CRYP_CR_CRYPEN                       ((uint32_t)0x00008000)
+/****************** Bits definition for CRYP_SR register  *********************/
+#define CRYP_SR_IFEM                         ((uint32_t)0x00000001)
+#define CRYP_SR_IFNF                         ((uint32_t)0x00000002)
+#define CRYP_SR_OFNE                         ((uint32_t)0x00000004)
+#define CRYP_SR_OFFU                         ((uint32_t)0x00000008)
+#define CRYP_SR_BUSY                         ((uint32_t)0x00000010)
+/****************** Bits definition for CRYP_DMACR register  ******************/
+#define CRYP_DMACR_DIEN                      ((uint32_t)0x00000001)
+#define CRYP_DMACR_DOEN                      ((uint32_t)0x00000002)
+/*****************  Bits definition for CRYP_IMSCR register  ******************/
+#define CRYP_IMSCR_INIM                      ((uint32_t)0x00000001)
+#define CRYP_IMSCR_OUTIM                     ((uint32_t)0x00000002)
+/****************** Bits definition for CRYP_RISR register  *******************/
+#define CRYP_RISR_OUTRIS                     ((uint32_t)0x00000001)
+#define CRYP_RISR_INRIS                      ((uint32_t)0x00000002)
+/****************** Bits definition for CRYP_MISR register  *******************/
+#define CRYP_MISR_INMIS                      ((uint32_t)0x00000001)
+#define CRYP_MISR_OUTMIS                     ((uint32_t)0x00000002)
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
+
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
+
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
+
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
+
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
+
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001)
+#define DCMI_CR_CM                           ((uint32_t)0x00000002)
+#define DCMI_CR_CROP                         ((uint32_t)0x00000004)
+#define DCMI_CR_JPEG                         ((uint32_t)0x00000008)
+#define DCMI_CR_ESS                          ((uint32_t)0x00000010)
+#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020)
+#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040)
+#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080)
+#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100)
+#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200)
+#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400)
+#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800)
+#define DCMI_CR_CRE                          ((uint32_t)0x00001000)
+#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000)
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001)
+#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002)
+#define DCMI_SR_FNE                          ((uint32_t)0x00000004)
+
+/********************  Bits definition for DCMI_RISR register  ****************/
+#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001)
+#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002)
+#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004)
+#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008)
+#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010)
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001)
+#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002)
+#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004)
+#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008)
+#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010)
+
+/********************  Bits definition for DCMI_MISR register  ****************/
+#define DCMI_MISR_FRAME_MIS                  ((uint32_t)0x00000001)
+#define DCMI_MISR_OVF_MIS                    ((uint32_t)0x00000002)
+#define DCMI_MISR_ERR_MIS                    ((uint32_t)0x00000004)
+#define DCMI_MISR_VSYNC_MIS                  ((uint32_t)0x00000008)
+#define DCMI_MISR_LINE_MIS                   ((uint32_t)0x00000010)
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001)
+#define DCMI_ICR_OVF_ISC                     ((uint32_t)0x00000002)
+#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004)
+#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008)
+#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010)
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/ 
+#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) 
+#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK                         ((uint32_t)0x00100000)
+#define DMA_SxCR_CT                          ((uint32_t)0x00080000)  
+#define DMA_SxCR_DBM                         ((uint32_t)0x00040000)
+#define DMA_SxCR_PL                          ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC                        ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC                        ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)
+#define DMA_SxCR_EN                          ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT                            ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0                          ((uint32_t)0x00000001)
+#define DMA_SxNDT_1                          ((uint32_t)0x00000002)
+#define DMA_SxNDT_2                          ((uint32_t)0x00000004)
+#define DMA_SxNDT_3                          ((uint32_t)0x00000008)
+#define DMA_SxNDT_4                          ((uint32_t)0x00000010)
+#define DMA_SxNDT_5                          ((uint32_t)0x00000020)
+#define DMA_SxNDT_6                          ((uint32_t)0x00000040)
+#define DMA_SxNDT_7                          ((uint32_t)0x00000080)
+#define DMA_SxNDT_8                          ((uint32_t)0x00000100)
+#define DMA_SxNDT_9                          ((uint32_t)0x00000200)
+#define DMA_SxNDT_10                         ((uint32_t)0x00000400)
+#define DMA_SxNDT_11                         ((uint32_t)0x00000800)
+#define DMA_SxNDT_12                         ((uint32_t)0x00001000)
+#define DMA_SxNDT_13                         ((uint32_t)0x00002000)
+#define DMA_SxNDT_14                         ((uint32_t)0x00004000)
+#define DMA_SxNDT_15                         ((uint32_t)0x00008000)
+
+/********************  Bits definition for DMA_SxFCR register  ****************/ 
+#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS                         ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)
+
+/********************  Bits definition for DMA_LISR register  *****************/ 
+#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_HISR register  *****************/ 
+#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_LIFCR register  ****************/ 
+#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/ 
+#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY                    ((uint32_t)0x00000007)
+#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)
+#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)
+#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)
+#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)
+#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)
+#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)
+#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)
+#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)
+
+#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)
+#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200)
+#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400)
+#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800)
+#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000)
+#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00)
+#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03)
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP                         ((uint32_t)0x00000001)
+#define FLASH_SR_SOP                         ((uint32_t)0x00000002)
+#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)
+#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)
+#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)
+#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080)
+#define FLASH_SR_BSY                         ((uint32_t)0x00010000)
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG                          ((uint32_t)0x00000001)
+#define FLASH_CR_SER                         ((uint32_t)0x00000002)
+#define FLASH_CR_MER                         ((uint32_t)0x00000004)
+#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)
+#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)
+#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)
+#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)
+#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)
+#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)
+#define FLASH_CR_STRT                        ((uint32_t)0x00010000)
+#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)
+#define FLASH_CR_LOCK                        ((uint32_t)0x80000000)
+
+/*******************  Bits definition for FLASH_OPTCR register  ***************/
+#define FLASH_OPTCR_OPTLOCK                  ((uint32_t)0x00000001)
+#define FLASH_OPTCR_OPTSTRT                  ((uint32_t)0x00000002)
+#define FLASH_OPTCR_BOR_LEV_0                ((uint32_t)0x00000004)
+#define FLASH_OPTCR_BOR_LEV_1                ((uint32_t)0x00000008)
+#define FLASH_OPTCR_BOR_LEV                  ((uint32_t)0x0000000C)
+#define FLASH_OPTCR_WDG_SW                   ((uint32_t)0x00000020)
+#define FLASH_OPTCR_nRST_STOP                ((uint32_t)0x00000040)
+#define FLASH_OPTCR_nRST_STDBY               ((uint32_t)0x00000080)
+#define FLASH_OPTCR_RDP_0                    ((uint32_t)0x00000100)
+#define FLASH_OPTCR_RDP_1                    ((uint32_t)0x00000200)
+#define FLASH_OPTCR_RDP_2                    ((uint32_t)0x00000400)
+#define FLASH_OPTCR_RDP_3                    ((uint32_t)0x00000800)
+#define FLASH_OPTCR_RDP_4                    ((uint32_t)0x00001000)
+#define FLASH_OPTCR_RDP_5                    ((uint32_t)0x00002000)
+#define FLASH_OPTCR_RDP_6                    ((uint32_t)0x00004000)
+#define FLASH_OPTCR_RDP_7                    ((uint32_t)0x00008000)
+#define FLASH_OPTCR_nWRP_0                   ((uint32_t)0x00010000)
+#define FLASH_OPTCR_nWRP_1                   ((uint32_t)0x00020000)
+#define FLASH_OPTCR_nWRP_2                   ((uint32_t)0x00040000)
+#define FLASH_OPTCR_nWRP_3                   ((uint32_t)0x00080000)
+#define FLASH_OPTCR_nWRP_4                   ((uint32_t)0x00100000)
+#define FLASH_OPTCR_nWRP_5                   ((uint32_t)0x00200000)
+#define FLASH_OPTCR_nWRP_6                   ((uint32_t)0x00400000)
+#define FLASH_OPTCR_nWRP_7                   ((uint32_t)0x00800000)
+#define FLASH_OPTCR_nWRP_8                   ((uint32_t)0x01000000)
+#define FLASH_OPTCR_nWRP_9                   ((uint32_t)0x02000000)
+#define FLASH_OPTCR_nWRP_10                  ((uint32_t)0x04000000)
+#define FLASH_OPTCR_nWRP_11                  ((uint32_t)0x08000000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Flexible Static Memory Controller                    */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FSMC_BCR1 register  *******************/
+#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
+#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit */
+
+#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable */
+#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit */
+#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit */
+#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
+#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration */
+#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit */
+#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit */
+#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable */
+#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait */
+#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable */
+
+/******************  Bit definition for FSMC_BCR2 register  *******************/
+#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
+#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit */
+
+#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable */
+#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit */
+#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit */
+#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
+#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration */
+#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit */
+#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit */
+#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable */
+#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait */
+#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable */
+
+/******************  Bit definition for FSMC_BCR3 register  *******************/
+#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
+#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit */
+
+#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable */
+#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit */
+#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit. */
+#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
+#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration */
+#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit */
+#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit */
+#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable */
+#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait */
+#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable */
+
+/******************  Bit definition for FSMC_BCR4 register  *******************/
+#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */
+#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit */
+
+#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */
+#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */
+
+#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable */
+#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit */
+#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit */
+#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */
+#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration */
+#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit */
+#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit */
+#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable */
+#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait */
+#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable */
+
+/******************  Bit definition for FSMC_BTR1 register  ******************/
+#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FSMC_BTR2 register  *******************/
+#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/*******************  Bit definition for FSMC_BTR3 register  *******************/
+#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FSMC_BTR4 register  *******************/
+#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+
+#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR1 register  ******************/
+#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR2 register  ******************/
+#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/
+#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR3 register  ******************/
+#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR4 register  ******************/
+#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */
+
+#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */
+#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */
+
+#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */
+
+/******************  Bit definition for FSMC_PCR2 register  *******************/
+#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
+#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
+
+#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
+
+#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+
+#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
+#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+
+#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size) */
+#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
+#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
+#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+
+/******************  Bit definition for FSMC_PCR3 register  *******************/
+#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
+#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
+
+#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
+
+#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+
+#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
+#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+
+#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
+#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
+#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
+#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+
+/******************  Bit definition for FSMC_PCR4 register  *******************/
+#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */
+#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */
+
+#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */
+
+#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */
+
+#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */
+
+#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */
+#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */
+
+#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */
+#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */
+#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */
+#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */
+
+/*******************  Bit definition for FSMC_SR2 register  *******************/
+#define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status */
+#define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status */
+#define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status */
+#define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit */
+#define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit */
+#define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
+
+/*******************  Bit definition for FSMC_SR3 register  *******************/
+#define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status */
+#define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status */
+#define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status */
+#define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit */
+#define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit */
+#define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
+
+/*******************  Bit definition for FSMC_SR4 register  *******************/
+#define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status */
+#define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status */
+#define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status */
+#define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit */
+#define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit */
+#define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */
+
+/******************  Bit definition for FSMC_PMEM2 register  ******************/
+#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FSMC_PMEM3 register  ******************/
+#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FSMC_PMEM4 register  ******************/
+#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FSMC_PATT2 register  ******************/
+#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FSMC_PATT3 register  ******************/
+#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FSMC_PATT4 register  ******************/
+#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FSMC_PIO4 register  *******************/
+#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */
+#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */
+#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */
+
+#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */
+#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */
+#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */
+#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */
+
+#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */
+#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */
+#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */
+#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */
+
+#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */
+#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */
+#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */
+#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */
+
+/******************  Bit definition for FSMC_ECCR2 register  ******************/
+#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
+
+/******************  Bit definition for FSMC_ECCR3 register  ******************/
+#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_OTYPER_IDR_0                    ((uint32_t)0x00000001)
+#define GPIO_OTYPER_IDR_1                    ((uint32_t)0x00000002)
+#define GPIO_OTYPER_IDR_2                    ((uint32_t)0x00000004)
+#define GPIO_OTYPER_IDR_3                    ((uint32_t)0x00000008)
+#define GPIO_OTYPER_IDR_4                    ((uint32_t)0x00000010)
+#define GPIO_OTYPER_IDR_5                    ((uint32_t)0x00000020)
+#define GPIO_OTYPER_IDR_6                    ((uint32_t)0x00000040)
+#define GPIO_OTYPER_IDR_7                    ((uint32_t)0x00000080)
+#define GPIO_OTYPER_IDR_8                    ((uint32_t)0x00000100)
+#define GPIO_OTYPER_IDR_9                    ((uint32_t)0x00000200)
+#define GPIO_OTYPER_IDR_10                   ((uint32_t)0x00000400)
+#define GPIO_OTYPER_IDR_11                   ((uint32_t)0x00000800)
+#define GPIO_OTYPER_IDR_12                   ((uint32_t)0x00001000)
+#define GPIO_OTYPER_IDR_13                   ((uint32_t)0x00002000)
+#define GPIO_OTYPER_IDR_14                   ((uint32_t)0x00004000)
+#define GPIO_OTYPER_IDR_15                   ((uint32_t)0x00008000)
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_OTYPER_ODR_0                    ((uint32_t)0x00000001)
+#define GPIO_OTYPER_ODR_1                    ((uint32_t)0x00000002)
+#define GPIO_OTYPER_ODR_2                    ((uint32_t)0x00000004)
+#define GPIO_OTYPER_ODR_3                    ((uint32_t)0x00000008)
+#define GPIO_OTYPER_ODR_4                    ((uint32_t)0x00000010)
+#define GPIO_OTYPER_ODR_5                    ((uint32_t)0x00000020)
+#define GPIO_OTYPER_ODR_6                    ((uint32_t)0x00000040)
+#define GPIO_OTYPER_ODR_7                    ((uint32_t)0x00000080)
+#define GPIO_OTYPER_ODR_8                    ((uint32_t)0x00000100)
+#define GPIO_OTYPER_ODR_9                    ((uint32_t)0x00000200)
+#define GPIO_OTYPER_ODR_10                   ((uint32_t)0x00000400)
+#define GPIO_OTYPER_ODR_11                   ((uint32_t)0x00000800)
+#define GPIO_OTYPER_ODR_12                   ((uint32_t)0x00001000)
+#define GPIO_OTYPER_ODR_13                   ((uint32_t)0x00002000)
+#define GPIO_OTYPER_ODR_14                   ((uint32_t)0x00004000)
+#define GPIO_OTYPER_ODR_15                   ((uint32_t)0x00008000)
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    HASH                                    */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for HASH_CR register  ********************/
+#define HASH_CR_INIT                         ((uint32_t)0x00000004)
+#define HASH_CR_DMAE                         ((uint32_t)0x00000008)
+#define HASH_CR_DATATYPE                     ((uint32_t)0x00000030)
+#define HASH_CR_DATATYPE_0                   ((uint32_t)0x00000010)
+#define HASH_CR_DATATYPE_1                   ((uint32_t)0x00000020)
+#define HASH_CR_MODE                         ((uint32_t)0x00000040)
+#define HASH_CR_ALGO                         ((uint32_t)0x00000080)
+#define HASH_CR_NBW                          ((uint32_t)0x00000F00)
+#define HASH_CR_NBW_0                        ((uint32_t)0x00000100)
+#define HASH_CR_NBW_1                        ((uint32_t)0x00000200)
+#define HASH_CR_NBW_2                        ((uint32_t)0x00000400)
+#define HASH_CR_NBW_3                        ((uint32_t)0x00000800)
+#define HASH_CR_DINNE                        ((uint32_t)0x00001000)
+#define HASH_CR_LKEY                         ((uint32_t)0x00010000)
+
+/******************  Bits definition for HASH_STR register  *******************/
+#define HASH_STR_NBW                         ((uint32_t)0x0000001F)
+#define HASH_STR_NBW_0                       ((uint32_t)0x00000001)
+#define HASH_STR_NBW_1                       ((uint32_t)0x00000002)
+#define HASH_STR_NBW_2                       ((uint32_t)0x00000004)
+#define HASH_STR_NBW_3                       ((uint32_t)0x00000008)
+#define HASH_STR_NBW_4                       ((uint32_t)0x00000010)
+#define HASH_STR_DCAL                        ((uint32_t)0x00000100)
+
+/******************  Bits definition for HASH_IMR register  *******************/
+#define HASH_IMR_DINIM                       ((uint32_t)0x00000001)
+#define HASH_IMR_DCIM                        ((uint32_t)0x00000002)
+
+/******************  Bits definition for HASH_SR register  ********************/
+#define HASH_SR_DINIS                        ((uint32_t)0x00000001)
+#define HASH_SR_DCIS                         ((uint32_t)0x00000002)
+#define HASH_SR_DMAS                         ((uint32_t)0x00000004)
+#define HASH_SR_BUSY                         ((uint32_t)0x00000008)
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  ********************/
+#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!<Peripheral Enable */
+#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!<SMBus Mode */
+#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!<SMBus Type */
+#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!<ARP Enable */
+#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!<PEC Enable */
+#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!<General Call Enable */
+#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!<Clock Stretching Disable (Slave mode) */
+#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!<Start Generation */
+#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!<Stop Generation */
+#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!<Acknowledge Enable */
+#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!<Packet Error Checking */
+#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!<SMBus Alert */
+#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!<Software Reset */
+
+/*******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+
+#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!<Error Interrupt Enable */
+#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!<Event Interrupt Enable */
+#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!<DMA Requests Enable */
+#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!<DMA Last Transfer */
+
+/*******************  Bit definition for I2C_OAR1 register  *******************/
+#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!<Interface Address */
+
+#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!<Bit 9 */
+
+#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!<Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!<Interface address */
+
+/********************  Bit definition for I2C_DR register  ********************/
+#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!<8-bit Data Register */
+
+/*******************  Bit definition for I2C_SR1 register  ********************/
+#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!<Start Bit (Master mode) */
+#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!<Byte Transfer Finished */
+#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!<10-bit header sent (Master mode) */
+#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!<Stop detection (Slave mode) */
+#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!<Data Register not Empty (receivers) */
+#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!<Data Register Empty (transmitters) */
+#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!<Bus Error */
+#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!<Arbitration Lost (master mode) */
+#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!<Acknowledge Failure */
+#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!<Overrun/Underrun */
+#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!<PEC Error in reception */
+#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!<Timeout or Tlow Error */
+#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!<SMBus Alert */
+
+/*******************  Bit definition for I2C_SR2 register  ********************/
+#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!<Master/Slave */
+#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!<Bus Busy */
+#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!<Transmitter/Receiver */
+#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!<General Call Address (Slave mode) */
+#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!<SMBus Host Header (Slave mode) */
+#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!<Dual Flag (Slave mode) */
+#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!<Packet Error Checking Register */
+
+/*******************  Bit definition for I2C_CCR register  ********************/
+#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!<Fast Mode Duty Cycle */
+#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!<I2C Master Mode Selection */
+
+/******************  Bit definition for I2C_TRISE register  *******************/
+#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!<Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!<PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!<Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!<Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!<Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!<Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-Power Deepsleep */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+#define  PWR_CR_FPDS                         ((uint16_t)0x0200)     /*!< Flash power down in Stop mode */
+
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+#define  PWR_CSR_BRR                         ((uint16_t)0x0008)     /*!< Backup regulator ready */
+#define  PWR_CSR_EWUP                        ((uint16_t)0x0100)     /*!< Enable WKUP pin */
+#define  PWR_CSR_BRE                         ((uint16_t)0x0200)     /*!< Backup regulator enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
+
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
+#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
+#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
+#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000)
+#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000)
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)
+#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)
+#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)
+#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)
+#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)
+#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)
+#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)
+
+#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)
+#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)
+#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)
+#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)
+#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)
+#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)
+#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)
+#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)
+#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)
+#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)
+
+#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)
+#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)
+#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)
+
+#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)
+#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)
+#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)
+
+#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)
+#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)
+#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)
+#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
+#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E00)         /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)
+#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)
+#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)
+#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)
+#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)
+#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)
+#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)
+#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)
+
+#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)
+
+#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)
+#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)
+#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)
+#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)
+
+#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)
+#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)
+#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)
+#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)
+
+#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)
+#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)
+#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_CIR register  *******************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)
+#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020)
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)
+#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000)
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)
+#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000)
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)
+#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)
+#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)
+#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008)
+#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010)
+#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020)
+#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040)
+#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)
+#define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100)
+#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)
+#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)
+#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)
+#define  RCC_AHB1RSTR_ETHMACRST              ((uint32_t)0x02000000)
+#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x10000000)
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001)
+#define  RCC_AHB2RSTR_CRYPRST                ((uint32_t)0x00000010)
+#define  RCC_AHB2RSTR_HSAHRST                ((uint32_t)0x00000020)
+#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040)
+#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080)
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+#define  RCC_AHB3RSTR_FSMCRST                ((uint32_t)0x00000001)
+
+/********************  Bit definition for RCC_APB1RSTR register  **************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)
+#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)
+#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)
+#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)
+#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)
+#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)
+#define  RCC_APB1RSTR_WWDGEN                 ((uint32_t)0x00000800)
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00008000)
+#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00010000)
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)
+#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)
+#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)
+#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)
+#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000)
+#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)
+#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)
+#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)
+#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002)
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)
+#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)
+#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)
+#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)
+#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)
+#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000)
+#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)
+#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)
+#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)
+#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008)
+#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010)
+#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020)
+#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040)
+#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)
+#define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100)
+#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)
+#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000)
+#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)
+#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)
+#define  RCC_AHB1ENR_ETHMACEN                ((uint32_t)0x02000000)
+#define  RCC_AHB1ENR_ETHMACTXEN              ((uint32_t)0x04000000)
+#define  RCC_AHB1ENR_ETHMACRXEN              ((uint32_t)0x08000000)
+#define  RCC_AHB1ENR_ETHMACPTPEN             ((uint32_t)0x10000000)
+#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000)
+#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000)
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001)
+#define  RCC_AHB2ENR_CRYPEN                  ((uint32_t)0x00000010)
+#define  RCC_AHB2ENR_HASHEN                  ((uint32_t)0x00000020)
+#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040)
+#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080)
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+#define  RCC_AHB3ENR_FSMCEN                  ((uint32_t)0x00000001)
+
+/********************  Bit definition for RCC_APB1ENR register  ***************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)
+#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)
+#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)
+#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)
+#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)
+#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)
+#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)
+#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)
+#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)
+#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)
+#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000)
+#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)
+#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)
+#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)
+#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002)
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)
+#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)
+#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200)
+#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400)
+#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)
+#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)
+#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)
+#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000)
+#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)
+
+/********************  Bit definition for RCC_AHB1LPENR register  *************/
+#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)
+#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)
+#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)
+#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008)
+#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010)
+#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020)
+#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040)
+#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)
+#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100)
+#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)
+#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)
+#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)
+#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)
+#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)
+#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)
+#define  RCC_AHB1LPENR_ETHMACLPEN            ((uint32_t)0x02000000)
+#define  RCC_AHB1LPENR_ETHMACTXLPEN          ((uint32_t)0x04000000)
+#define  RCC_AHB1LPENR_ETHMACRXLPEN          ((uint32_t)0x08000000)
+#define  RCC_AHB1LPENR_ETHMACPTPLPEN         ((uint32_t)0x10000000)
+#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000)
+#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000)
+
+/********************  Bit definition for RCC_AHB2LPENR register  *************/
+#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001)
+#define  RCC_AHB2LPENR_CRYPLPEN              ((uint32_t)0x00000010)
+#define  RCC_AHB2LPENR_HASHLPEN              ((uint32_t)0x00000020)
+#define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040)
+#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080)
+
+/********************  Bit definition for RCC_AHB3LPENR register  *************/
+#define  RCC_AHB3LPENR_FSMCLPEN              ((uint32_t)0x00000001)
+
+/********************  Bit definition for RCC_APB1LPENR register  *************/
+#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)
+#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)
+#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)
+#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)
+#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)
+#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)
+#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040)
+#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080)
+#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100)
+#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)
+#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)
+#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)
+#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)
+#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)
+#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)
+#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)
+#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)
+#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)
+#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000)
+#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000)
+#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000)
+#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)
+#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)
+
+/********************  Bit definition for RCC_APB2LPENR register  *************/
+#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)
+#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002)
+#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)
+#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)
+#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)
+#define  RCC_APB2LPENR_ADC2PEN               ((uint32_t)0x00000200)
+#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400)
+#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)
+#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)
+#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)
+#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)
+#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000)
+#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)
+
+#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300)
+#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100)
+#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200)
+
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)
+#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)
+#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000)
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)
+#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000)
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_SSCGR register  *****************/
+#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)
+#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)
+#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)
+#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
+#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0)
+#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)
+#define RNG_CR_IE                            ((uint32_t)0x00000008)
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY                          ((uint32_t)0x00000001)
+#define RNG_SR_CECS                          ((uint32_t)0x00000002)
+#define RNG_SR_SECS                          ((uint32_t)0x00000004)
+#define RNG_SR_CEIS                          ((uint32_t)0x00000020)
+#define RNG_SR_SEIS                          ((uint32_t)0x00000040)
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_BCK                           ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+#define RTC_CR_DCE                           ((uint32_t)0x00000080)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00001FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CALIBR register  ***************/
+#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
+#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000)
+#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDIO_POWER register  ******************/
+#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!<Bit 1 */
+
+/******************  Bit definition for SDIO_CLKCR register  ******************/
+#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!<Clock divide factor */
+#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!<Clock enable bit */
+#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!<Power saving configuration bit */
+#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!<Clock divider bypass enable bit */
+
+#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!<Bit 1 */
+
+#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!<HW Flow Control enable */
+
+/*******************  Bit definition for SDIO_ARG register  *******************/
+#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!<Command argument */
+
+/*******************  Bit definition for SDIO_CMD register  *******************/
+#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!<Command Index */
+
+#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!< Bit 1 */
+
+#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!<CPSM Waits for Interrupt Request */
+#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!<Command path state machine (CPSM) Enable bit */
+#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!<SD I/O suspend command */
+#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!<Enable CMD completion */
+#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!<CE-ATA command */
+
+/*****************  Bit definition for SDIO_RESPCMD register  *****************/
+#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!<Response command index */
+
+/******************  Bit definition for SDIO_RESP0 register  ******************/
+#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP1 register  ******************/
+#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP2 register  ******************/
+#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP3 register  ******************/
+#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP4 register  ******************/
+#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_DTIMER register  *****************/
+#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!<Data timeout period. */
+
+/******************  Bit definition for SDIO_DLEN register  *******************/
+#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!<Data length value */
+
+/******************  Bit definition for SDIO_DCTRL register  ******************/
+#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!<Data transfer enabled bit */
+#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!<Data transfer mode selection */
+#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!<DMA enabled bit */
+
+#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!<Read wait start */
+#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!<Read wait stop */
+#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!<Read wait mode */
+#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDIO_DCOUNT register  *****************/
+#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!<Data count value */
+
+/******************  Bit definition for SDIO_STA register  ********************/
+#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!<Command response received (CRC check failed) */
+#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!<Data block sent/received (CRC check failed) */
+#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!<Command response timeout */
+#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!<Data timeout */
+#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!<Transmit FIFO underrun error */
+#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!<Received FIFO overrun error */
+#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!<Command response received (CRC check passed) */
+#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!<Command sent (no response required) */
+#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!<Data block sent/received (CRC check passed) */
+#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!<Command transfer in progress */
+#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!<Data transmit in progress */
+#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!<Data receive in progress */
+#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!<Transmit FIFO full */
+#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!<Receive FIFO full */
+#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!<Transmit FIFO empty */
+#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!<Receive FIFO empty */
+#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!<Data available in transmit FIFO */
+#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!<Data available in receive FIFO */
+#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!<SDIO interrupt received */
+#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received for CMD61 */
+
+/*******************  Bit definition for SDIO_ICR register  *******************/
+#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!<RXOVERR flag clear bit */
+#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!<CMDREND flag clear bit */
+#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!<CMDSENT flag clear bit */
+#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!<DATAEND flag clear bit */
+#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!<DBCKEND flag clear bit */
+#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!<SDIOIT flag clear bit */
+#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!<CEATAEND flag clear bit */
+
+/******************  Bit definition for SDIO_MASK register  *******************/
+#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!<Command CRC Fail Interrupt Enable */
+#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!<Data CRC Fail Interrupt Enable */
+#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!<Command TimeOut Interrupt Enable */
+#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!<Data TimeOut Interrupt Enable */
+#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!<Command Sent Interrupt Enable */
+#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!<Data End Interrupt Enable */
+#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!<Start Bit Error Interrupt Enable */
+#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!<Data Block End Interrupt Enable */
+#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!<CCommand Acting Interrupt Enable */
+#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!<Data Transmit Acting Interrupt Enable */
+#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!<Data receive acting interrupt enabled */
+#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!<Tx FIFO Half Empty interrupt Enable */
+#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!<Rx FIFO Half Full interrupt Enable */
+#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!<Tx FIFO Full interrupt Enable */
+#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!<Rx FIFO Full interrupt Enable */
+#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!<Tx FIFO Empty interrupt Enable */
+#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!<Rx FIFO Empty interrupt Enable */
+#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
+#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDIO_FIFO register  *******************/
+#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!<Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!<Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!<Master Selection */
+
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!<Bit 2 */
+
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!<SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!<Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!<Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!<Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!<Receive only */
+#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!<Data Frame Format */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!<Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!<Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!<Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!<Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!<Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!<SS Output Enable */
+#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!<Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!<Tx buffer Empty Interrupt Enable */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!<Transmit buffer Empty */
+#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!<Channel side */
+#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!<Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!<CRC Error flag */
+#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!<Mode fault */
+#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!<Overrun flag */
+#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!<Busy flag */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!<Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!<Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!<Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
+#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000003) /*!<SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001)
+#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002)
+
+/******************  Bit definition for SYSCFG_PMC register  ******************/
+#define SYSCFG_PMC_MII_RMII            ((uint16_t)0x0080) /*!<Ethernet PHY interface selection */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!<EXTI 3 configuration */
+/** 
+  * @brief   EXTI0 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint16_t)0x0006) /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0007) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint16_t)0x0008) /*!<PI[0] pin */
+/** 
+  * @brief   EXTI1 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint16_t)0x0060) /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0070) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint16_t)0x0080) /*!<PI[1] pin */
+/** 
+  * @brief   EXTI2 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint16_t)0x0600) /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint16_t)0x0700) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint16_t)0x0800) /*!<PI[2] pin */
+/** 
+  * @brief   EXTI3 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint16_t)0x6000) /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint16_t)0x7000) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint16_t)0x8000) /*!<PI[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!<EXTI 7 configuration */
+/** 
+  * @brief   EXTI4 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint16_t)0x0006) /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint16_t)0x0007) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint16_t)0x0008) /*!<PI[4] pin */
+/** 
+  * @brief   EXTI5 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint16_t)0x0060) /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint16_t)0x0070) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint16_t)0x0080) /*!<PI[5] pin */
+/** 
+  * @brief   EXTI6 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint16_t)0x0600) /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint16_t)0x0700) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint16_t)0x0800) /*!<PI[6] pin */
+/** 
+  * @brief   EXTI7 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint16_t)0x6000) /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint16_t)0x7000) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint16_t)0x8000) /*!<PI[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!<EXTI 11 configuration */
+           
+/** 
+  * @brief   EXTI8 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint16_t)0x0005) /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint16_t)0x0006) /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint16_t)0x0007) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint16_t)0x0008) /*!<PI[8] pin */
+/** 
+  * @brief   EXTI9 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint16_t)0x0060) /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint16_t)0x0070) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint16_t)0x0080) /*!<PI[9] pin */
+/** 
+  * @brief   EXTI10 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint16_t)0x0600) /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint16_t)0x0700) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint16_t)0x0800) /*!<PI[10] pin */
+/** 
+  * @brief   EXTI11 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint16_t)0x5000) /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint16_t)0x6000) /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint16_t)0x7000) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint16_t)0x8000) /*!<PI[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!<EXTI 15 configuration */
+/** 
+  * @brief   EXTI12 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint16_t)0x0005) /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint16_t)0x0006) /*!<PG[12] pin */
+#define SYSCFG_EXTICR3_EXTI12_PH        ((uint16_t)0x0007) /*!<PH[12] pin */
+/** 
+  * @brief   EXTI13 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint16_t)0x0050) /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint16_t)0x0060) /*!<PG[13] pin */
+#define SYSCFG_EXTICR3_EXTI13_PH        ((uint16_t)0x0070) /*!<PH[13] pin */
+/** 
+  * @brief   EXTI14 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint16_t)0x0500) /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint16_t)0x0600) /*!<PG[14] pin */
+#define SYSCFG_EXTICR3_EXTI14_PH        ((uint16_t)0x0700) /*!<PH[14] pin */
+/** 
+  * @brief   EXTI15 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint16_t)0x5000) /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint16_t)0x6000) /*!<PG[15] pin */
+#define SYSCFG_EXTICR3_EXTI15_PH        ((uint16_t)0x7000) /*!<PH[15] pin */
+
+/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
+#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM_OR_TI4_RMP                       ((uint16_t)0x00C0)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0                     ((uint16_t)0x0040)            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     ((uint16_t)0x0080)            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      ((uint16_t)0x0C00)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for USART_SR register  *******************/
+#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!<Parity Error */
+#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!<Framing Error */
+#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!<Noise Error Flag */
+#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!<OverRun Error */
+#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!<IDLE line detected */
+#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!<Transmission Complete */
+#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!<LIN Break Detection Flag */
+#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!<CTS Flag */
+
+/*******************  Bit definition for USART_DR register  *******************/
+#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!<Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!<Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!<Send Break */
+#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!<Receiver wakeup */
+#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!<Receiver Enable */
+#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!<Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!<IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!<RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!<PE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!<PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!<Parity Selection */
+#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!<Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!<Wakeup method */
+#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!<Word length */
+#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!<USART Enable */
+#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!<USART Oversampling by 8 enable */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!<Address of the USART node */
+#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!<LIN Break Detection Length */
+#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!<Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!<Clock Phase */
+#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!<Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!<Clock Enable */
+
+#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!<LIN mode enable */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!<Error Interrupt Enable */
+#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!<IrDA mode Enable */
+#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!<IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!<Half-Duplex Selection */
+#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!<Smartcard NACK enable */
+#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!<Smartcard mode enable */
+#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!<DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!<DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!<RTS Enable */
+#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!<CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!<CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!<USART One bit method enable */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!<Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
+#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
+
+#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
+#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP        ((uint32_t)0x00000004)
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP        ((uint32_t)0x00000008)
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP       ((uint32_t)0x00000040)
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP       ((uint32_t)0x00000080)
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)
+
+/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
+#define  DBGMCU_APB1_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
+#define  DBGMCU_APB1_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)
+#define  DBGMCU_APB1_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)
+#define  DBGMCU_APB1_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000)
+#define  DBGMCU_APB1_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
+#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
+#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
+  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
+  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
+  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
+  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        
+  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
+  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
+  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              
+#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
+#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
+#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
+#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
+#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
+#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
+#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
+  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
+  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
+  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
+  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ 
+#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
+#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
+#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ 
+#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ 
+#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ 
+#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
+  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
+  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
+  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM    ((uint32_t)0x00000010)  /* Pass all mutlicast */ 
+#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ 
+#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ 
+#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
+#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ 
+#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ 
+#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ 
+  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+  #define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)  /* HCLK:100-120 MHz; MDC clock= HCLK/62 */
+  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/42 */  
+#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ 
+#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ 
+  
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
+#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
+  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
+  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
+  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
+  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      
+#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
+#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
+                              RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
+#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
+#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ 
+#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
+  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP      ((uint32_t)0x00000020)  /* MMC counter Full-Half preset (Only in STM32F2xx) */
+#define ETH_MMCCR_MCP        ((uint32_t)0x00000010)  /* MMC counter preset (Only in STM32F2xx) */
+#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
+#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT       ((uint32_t)0x00030000)  /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME     ((uint32_t)0x00008000)  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME      ((uint32_t)0x00004000)  /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)  /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)  /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE  ((uint32_t)0x00000800)  /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E  ((uint32_t)0x00000400)  /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR       ((uint32_t)0x00000200)  /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE     ((uint32_t)0x00000100)  /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
+#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR    ((uint32_t)0x00000020)  /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO     ((uint32_t)0x00000010)  /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
+#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
+#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
+  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
+  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE       ((uint32_t)0x00000080)  /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
+#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
+#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
+  /* combination with EBS[2:0] for GetFlagStatus function */
+  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
+#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
+#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
+#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
+#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
+#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
+#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
+#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
+  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
+  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
+#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
+
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F2xx_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

diff --git a/bbb_cape/src/cape/CMSIS/core_cm3.h b/bbb_cape/src/cape/CMSIS/core_cm3.h
new file mode 100644
index 0000000..122c9aa
--- /dev/null
+++ b/bbb_cape/src/cape/CMSIS/core_cm3.h

@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

diff --git a/bbb_cape/src/cape/CMSIS/core_cmFunc.h b/bbb_cape/src/cape/CMSIS/core_cmFunc.h
new file mode 100644
index 0000000..0a18faf
--- /dev/null
+++ b/bbb_cape/src/cape/CMSIS/core_cmFunc.h

@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */

diff --git a/bbb_cape/src/cape/CMSIS/core_cmInstr.h b/bbb_cape/src/cape/CMSIS/core_cmInstr.h
new file mode 100644
index 0000000..d213f0e
--- /dev/null
+++ b/bbb_cape/src/cape/CMSIS/core_cmInstr.h

@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

diff --git a/bbb_cape/src/cape/Makefile b/bbb_cape/src/cape/Makefile
new file mode 100644
index 0000000..5046615
--- /dev/null
+++ b/bbb_cape/src/cape/Makefile

@@ -0,0 +1,96 @@
+OBJDIR := .obj/
+$(shell mkdir -p $(OBJDIR))
+
+ifeq ($(OS),Windows_NT)
+  CROSS_COMPILE := arm-none-eabi-
+else
+  CROSS_COMPILE := /opt/cortex-m3/bin/arm-eabi-
+endif
+
+CC := $(CROSS_COMPILE)gcc
+LD := $(CROSS_COMPILE)ld
+OBJCOPY := $(CROSS_COMPILE)objcopy
+OBJDUMP := $(CROSS_COMPILE)objdump
+AS := $(CROSS_COMPILE)as
+
+CPPFLAGS := -I.. -ICMSIS \
+
+CFLAGS := -nostartfiles -nostdlib -ffreestanding -fbuiltin \
+	-O3 -mcpu=cortex-m3 \
+	-mthumb -Wl,--gc-sections -ffunction-sections -Wl,-static \
+	-Wall -Werror --std=gnu99 \
+	-Wstrict-aliasing=2 -Wcast-qual -Wpointer-arith \
+
+LDFLAGS := -O3 -mcpu=cortex-m3 \
+	-nostartfiles -nostdlib \
+	-T gcc_arm.ld \
+
+ASFLAGS := -O3 -mcpu=cortex-m3 \
+	-nostartfiles -nostdlib \
+	-mthumb \
+
+OBJECTS_main_common := main \
+	uart_common \
+	uart_dma \
+	uart \
+	fill_packet \
+	cows \
+	encoder \
+	crc \
+	gyro \
+	led \
+	analog \
+	digital \
+
+OBJECTS_bootloader := bootloader \
+	uart_common \
+	uart_byte \
+
+OBJECTS_main_test := $(OBJECTS_main_common) \
+	robot_test \
+
+OUTPUTS := main_test bootloader
+
+# The sort is to remove duplicates because Make warns about those.
+OBJECTS := $(sort $(foreach output,$(OUTPUTS),$(OBJECTS_$(output))))
+
+OUTPUTS_elf := $(OUTPUTS:%=$(OBJDIR)%.elf)
+OUTPUTS_hex := $(OUTPUTS:%=$(OBJDIR)%.hex)
+
+.PHONY: all
+all: $(OUTPUTS_hex)
+
+-include $(OBJECTS:%=$(OBJDIR)%.d)
+
+.SECONDEXPANSION:
+PERCENT := %
+
+# "$(OBJDIR)%.elf: $(OBJECTS_%:%=$(OBJDIR)%.o)" with the % signs meaning the
+# right thing in the right places.
+$(OUTPUTS_elf): $(OBJDIR)%.elf: $$(OBJECTS_$$*:$$(PERCENT)=$(OBJDIR)$$(PERCENT).o)
+$(OUTPUTS_elf): $(OBJDIR)%.elf:	gcc_arm.ld %.ld $(OBJDIR)STM32F2XX_startup.o
+	$(CC) $(CPPFLAGS) -T $*.ld $(LDFLAGS) -o $@ \
+		$(OBJDIR)STM32F2XX_startup.o \
+		$(OBJECTS_$*:%=$(OBJDIR)%.o) \
+		-Wa,-Map -Wa,$(OBJDIR)$*.map
+
+$(OBJECTS:%=$(OBJDIR)%.o): $(OBJDIR)%.o: %.c
+	$(CC) $(CPPFLAGS) $(CFLAGS) -MD -MP -MT '$@ $*.s' -c -o $@ $<
+$(OBJDIR)%.o: %.S
+	$(CC) $(CPPFLAGS) $(ASFLAGS) -MD -MP -MT '$@ $*.s' -c -o $@ $<
+
+# So that you can see the assembly for an individual file with any comments etc.
+$(OBJECTS:%=%.s): %.s: %.c
+	$(CC) $(CPPFLAGS) $(CFLAGS) -S -o $@ $<
+%.s: %.S
+	$(CC) $(CPPFLAGS) $(ASFLAGS) -S -o $@ $<
+
+# So that you can see the assembly of the whole .elf file.
+$(OUTPUTS:%=elf_%.s): elf_%.s: $(OBJDIR)%.elf
+	$(OBJDUMP) -d -S $< > $@
+
+$(OUTPUTS_hex): $(OBJDIR)%.hex: $(OBJDIR)%.elf
+	$(OBJCOPY) -O ihex $< $@
+
+clean:
+	rm -rf $(OBJDIR)

diff --git a/bbb_cape/src/cape/README b/bbb_cape/src/cape/README
new file mode 100644
index 0000000..ddda84c
--- /dev/null
+++ b/bbb_cape/src/cape/README

@@ -0,0 +1,16 @@
+[files]
+  Low-level hardware interface files: These are files copied (and tweaked) from
+      other places that deal with the low-level hardware stuff.
+	CMSIS/STM32F2XX.h: This has the declarations for all of the peripherial
+	    registers and other stuff specific to this MCU. It was downloaded from
+		the Rowley Associates STM32 BSP.
+    CMSIS/core_cm3.h: This has the declarations for the generic Cortex-M3
+	    registers. It is a generic file that seems to be dowloadable from lots
+		of places (with slight differences between each, of course). STM32F2XX.h
+		#includes it.
+	STM32FXX_startup.S: This defines the exception vector table and handles
+	    copying data into RAM etc before calling main.
+    *.ld: These are linker scripts. They defines where in memory everything
+	    actually goes and give various locations names so that the startup
+		code (described above) can find them and put the data where it
+		belongs.

diff --git a/bbb_cape/src/cape/STM32F2XX_startup.S b/bbb_cape/src/cape/STM32F2XX_startup.S
new file mode 100644
index 0000000..ace098a
--- /dev/null
+++ b/bbb_cape/src/cape/STM32F2XX_startup.S

@@ -0,0 +1,233 @@
+/* File: startup_ARMCM3.S
+ * Purpose: startup file for Cortex-M3 devices. Should use with
+ *   GCC for ARM Embedded Processors
+ * Version: V1.4
+ * Date: 20 Dezember 2012
+ *
+ */
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+.syntax unified
+.arch armv7-m
+.code 16  
+
+.section .stack
+  .align 3
+
+  .equ  Stack_Size, 0x00000400
+
+ .globl  __StackLimit
+ __StackLimit:
+  .space  Stack_Size
+  .size __StackLimit, . - __StackLimit
+
+ .globl  __StackTop
+ __StackTop:
+  .size __StackTop, . - __StackTop
+
+.section .heap
+  .align 3
+
+ .globl  __HeapBase
+ __HeapBase:
+  .equ  Heap_Size, 0x00000C00
+  .if  Heap_Size
+    .space  Heap_Size
+  .endif
+  .size __HeapBase, . - __HeapBase
+
+ .globl  __HeapLimit
+ __HeapLimit:
+  .size __HeapLimit, . - __HeapLimit
+
+.macro ISR_HANDLER name=
+  .section .vectors, "a"
+    .word \name
+  .section .init, "ax"
+   .thumb_func
+   .weak \name
+   \name:
+    1: b 1b /* endless loop */
+.endm
+
+.macro ISR_RESERVED
+  .section .vectors, "a"
+    .word 0
+.endm
+
+.section .vectors, "a"
+ .global _vectors
+ _vectors:
+  .long  __StackTop
+  .long  Reset_Handler
+  ISR_HANDLER NMI_Handler
+  ISR_HANDLER HardFault_Handler
+  ISR_HANDLER MemManage_Handler 
+  ISR_HANDLER BusFault_Handler
+  ISR_HANDLER UsageFault_Handler
+  ISR_RESERVED
+  ISR_RESERVED
+  ISR_RESERVED
+  ISR_RESERVED
+  ISR_HANDLER SVC_Handler
+  ISR_HANDLER DebugMon_Handler
+  ISR_RESERVED
+  ISR_HANDLER PendSV_Handler
+  ISR_HANDLER SysTick_Handler 
+
+  /* interrupts */
+  ISR_HANDLER WWDG_IRQHandler
+  ISR_HANDLER PVD_IRQHandler
+  ISR_HANDLER TAMP_STAMP_IRQHandler
+  ISR_HANDLER RTC_WKUP_IRQHandler
+  ISR_HANDLER FLASH_IRQHandler
+  ISR_HANDLER RCC_IRQHandler
+  ISR_HANDLER EXTI0_IRQHandler
+  ISR_HANDLER EXTI1_IRQHandler
+  ISR_HANDLER EXTI2_IRQHandler
+  ISR_HANDLER EXTI3_IRQHandler
+  ISR_HANDLER EXTI4_IRQHandler
+  ISR_HANDLER DMA1_Stream0_IRQHandler
+  ISR_HANDLER DMA1_Stream1_IRQHandler
+  ISR_HANDLER DMA1_Stream2_IRQHandler
+  ISR_HANDLER DMA1_Stream3_IRQHandler
+  ISR_HANDLER DMA1_Stream4_IRQHandler
+  ISR_HANDLER DMA1_Stream5_IRQHandler
+  ISR_HANDLER DMA1_Stream6_IRQHandler
+  ISR_HANDLER ADC_IRQHandler
+  ISR_HANDLER CAN1_TX_IRQHandler
+  ISR_HANDLER CAN1_RX0_IRQHandler
+  ISR_HANDLER CAN1_RX1_IRQHandler
+  ISR_HANDLER CAN1_SCE_IRQHandler
+  ISR_HANDLER EXTI9_5_IRQHandler
+  ISR_HANDLER TIM1_BRK_TIM9_IRQHandler
+  ISR_HANDLER TIM1_UP_TIM10_IRQHandler
+  ISR_HANDLER TIM1_TRG_COM_TIM11_IRQHandler
+  ISR_HANDLER TIM1_CC_IRQHandler
+  ISR_HANDLER TIM2_IRQHandler
+  ISR_HANDLER TIM3_IRQHandler
+  ISR_HANDLER TIM4_IRQHandler
+  ISR_HANDLER I2C1_EV_IRQHandler
+  ISR_HANDLER I2C1_ER_IRQHandler
+  ISR_HANDLER I2C2_EV_IRQHandler
+  ISR_HANDLER I2C2_ER_IRQHandler
+  ISR_HANDLER SPI1_IRQHandler
+  ISR_HANDLER SPI2_IRQHandler
+  ISR_HANDLER USART1_IRQHandler
+  ISR_HANDLER USART2_IRQHandler
+  ISR_HANDLER USART3_IRQHandler
+  ISR_HANDLER EXTI15_10_IRQHandler
+  ISR_HANDLER RTC_Alarm_IRQHandler
+  ISR_HANDLER OTG_FS_WKUP_IRQHandler
+  ISR_HANDLER TIM8_BRK_TIM12_IRQHandler
+  ISR_HANDLER TIM8_UP_TIM13_IRQHandler
+  ISR_HANDLER TIM8_TRG_COM_TIM14_IRQHandler
+  ISR_HANDLER TIM8_CC_IRQHandler
+  ISR_HANDLER DMA1_Stream7_IRQHandler
+  ISR_HANDLER FSMC_IRQHandler
+  ISR_HANDLER SDIO_IRQHandler
+  ISR_HANDLER TIM5_IRQHandler
+  ISR_HANDLER SPI3_IRQHandler
+  ISR_HANDLER UART4_IRQHandler
+  ISR_HANDLER UART5_IRQHandler
+  ISR_HANDLER TIM6_DAC_IRQHandler
+  ISR_HANDLER TIM7_IRQHandler
+  ISR_HANDLER DMA2_Stream0_IRQHandler
+  ISR_HANDLER DMA2_Stream1_IRQHandler
+  ISR_HANDLER DMA2_Stream2_IRQHandler
+  ISR_HANDLER DMA2_Stream3_IRQHandler
+  ISR_HANDLER DMA2_Stream4_IRQHandler
+  ISR_HANDLER ETH_IRQHandler
+  ISR_HANDLER ETH_WKUP_IRQHandler
+  ISR_HANDLER CAN2_TX_IRQHandler
+  ISR_HANDLER CAN2_RX0_IRQHandler
+  ISR_HANDLER CAN2_RX1_IRQHandler
+  ISR_HANDLER CAN2_SCE_IRQHandler
+  ISR_HANDLER OTG_FS_IRQHandler
+  ISR_HANDLER DMA2_Stream5_IRQHandler
+  ISR_HANDLER DMA2_Stream6_IRQHandler
+  ISR_HANDLER DMA2_Stream7_IRQHandler
+  ISR_HANDLER USART6_IRQHandler
+  ISR_HANDLER I2C3_EV_IRQHandler
+  ISR_HANDLER I2C3_ER_IRQHandler
+  ISR_HANDLER OTG_HS_EP1_OUT_IRQHandler
+  ISR_HANDLER OTG_HS_EP1_IN_IRQHandler
+  ISR_HANDLER OTG_HS_WKUP_IRQHandler
+  ISR_HANDLER OTG_HS_IRQHandler
+  ISR_HANDLER DCMI_IRQHandler
+  ISR_HANDLER CRYP_IRQHandler
+  ISR_HANDLER HASH_RNG_IRQHandler
+
+.section .vectors, "a"
+ _vectors_end:
+
+.text
+ .thumb_func
+ .align 2
+ .globl  Reset_Handler
+ .type  Reset_Handler, %function
+ Reset_Handler:
+
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+  ldr  r1, =__etext
+  ldr  r2, =__data_start__
+  ldr  r3, =__data_end__
+  subs  r3, r2
+  ble  .LC1
+ .LC0:
+  subs  r3, #4
+  ldr  r0, [r1, r3]
+  str  r0, [r2, r3]
+  bgt  .LC0
+ .LC1:
+
+/*     Loop to zero out BSS section, which uses following symbols
+ *     in linker script:
+ *      __bss_start__: start of BSS section. Must align to 4
+ *      __bss_end__: end of BSS section. Must align to 4
+ */
+  ldr r1, =__bss_start__
+  ldr r2, =__bss_end__
+  movs  r0, 0
+ .LC2:
+  cmp   r1, r2
+  itt  lt
+  strlt   r0, [r1], #4
+  blt  .LC2
+
+  bl  _start
+  1: b 1b /* endless loop if it ever returns */
+
+  .pool
+  .size Reset_Handler, . - Reset_Handler

diff --git a/bbb_cape/src/cape/analog.c b/bbb_cape/src/cape/analog.c
new file mode 100644
index 0000000..0ccd2f0
--- /dev/null
+++ b/bbb_cape/src/cape/analog.c

@@ -0,0 +1,95 @@
+#include "cape/analog.h"
+
+#include <string.h>
+
+#include <STM32F2XX.h>
+
+#include "cape/util.h"
+
+#define SPI SPI2
+#define SPI_IRQHander SPI2_IRQHandler
+#define SPI_IRQn SPI2_IRQn
+#define RCC_APB1ENR_SPIEN RCC_APB1ENR_SPI2EN
+#define TIM TIM14
+#define TIM_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler
+#define TIM_IRQn TIM8_TRG_COM_TIM14_IRQn
+#define RCC_APB1ENR_TIMEN RCC_APB1ENR_TIM14EN
+#define CSEL_GPIO GPIOB
+#define CSEL_NUM 12
+
+#define NUM_CHANNELS 8
+
+uint16_t analog_readings[NUM_CHANNELS] __attribute__((aligned(8)));
+static volatile int current_channel;
+
+static void start_read(int channel) {
+  // This needs to wait 13 cycles between enabling the CSEL pin and starting to
+  // send data.
+  // (100ns+8ns)*120MHz = 12.96
+
+  // Clear the CSEL pin to select it.
+  for (int i = 0; i < 9; ++i) CSEL_GPIO->BSRRH = 1 << CSEL_NUM;
+  current_channel = channel;
+  uint16_t data = 1 << 8 /* start bit */ |
+      0 << 7 /* not differential */ |
+      channel << 4;
+  SPI->DR = data;
+}
+
+void SPI_IRQHandler(void) {
+  uint32_t status = SPI->SR;
+  if (status & SPI_SR_RXNE) {
+    uint16_t value = SPI->DR;
+    // Masking off the high bits is important because there's nothing driving
+    // the MISO line during the time the MCU receives them.
+    analog_readings[current_channel] = value & 0x3FF;
+    CSEL_GPIO->BSRRL = 1 << CSEL_NUM;
+
+    TIM->CR1 = TIM_CR1_UDIS;
+    TIM->CCR1 = 1;
+    TIM->EGR = TIM_EGR_UG;
+    TIM->CR1 |= TIM_CR1_CEN;
+  }
+}
+
+void TIM_IRQHandler(void) {
+  TIM->CR1 &= ~TIM_CR1_CEN;
+  TIM->SR = TIM_SR_CC1IF;
+
+  start_read((current_channel + 1) % NUM_CHANNELS);
+}
+
+void analog_init(void) {
+  memset(analog_readings, 0xFF, sizeof(analog_readings));
+
+  RCC->APB1ENR |= RCC_APB1ENR_SPIEN;
+  RCC->APB1ENR |= RCC_APB1ENR_TIMEN;
+
+  gpio_setup_out(CSEL_GPIO, CSEL_NUM, 3);
+  CSEL_GPIO->BSRRL = 1 << CSEL_NUM;  // make sure it's deselected
+
+  gpio_setup_alt(GPIOB, 13, 5);  // SCK
+  gpio_setup_alt(GPIOB, 14, 5);  // MISO
+  gpio_setup_alt(GPIOB, 15, 5);  // MOSI
+
+  NVIC_SetPriority(SPI_IRQn, 6);
+  NVIC_EnableIRQ(SPI_IRQn);
+  NVIC_SetPriority(TIM_IRQn, 6);
+  NVIC_EnableIRQ(TIM_IRQn);
+
+  TIM->CR1 = TIM_CR1_UDIS;
+  TIM->DIER = TIM_DIER_CC1IE;
+  TIM->CCMR1 = 0;
+  // Make each tick take 500ns.
+  TIM->PSC = (30 * 500 / 1000) - 1;
+
+  SPI->CR1 = 0;  // make sure it's disabled
+  SPI->CR1 =
+      SPI_CR1_DFF /* 16 bit frame */ |
+      1 << 3 /* 30MHz/4 = 7.5MHz */ |
+      SPI_CR1_MSTR /* master mode */;
+  SPI->CR2 = SPI_CR2_RXNEIE;
+  SPI->CR1 |= SPI_CR1_SPE;  // enable it
+
+  start_read(0);
+}

diff --git a/bbb_cape/src/cape/analog.h b/bbb_cape/src/cape/analog.h
new file mode 100644
index 0000000..50038d5
--- /dev/null
+++ b/bbb_cape/src/cape/analog.h

@@ -0,0 +1,17 @@
+#ifndef CAPE_ANALOG_H_
+#define CAPE_ANALOG_H_
+
+#include <stdint.h>
+
+// Starts up constantly reading analog values and storing them in an array to
+// be retrieved by analog_get.
+void analog_init(void);
+
+static inline uint16_t analog_get(int num) {
+  if (num < 0 || num > 7) return 0xFFFF;
+
+  extern uint16_t analog_readings[8] __attribute__((aligned(8)));
+  return analog_readings[num];
+}
+
+#endif  // CAPE_ANALOG_H_

diff --git a/bbb_cape/src/cape/bootloader.c b/bbb_cape/src/cape/bootloader.c
new file mode 100644
index 0000000..1ed6218
--- /dev/null
+++ b/bbb_cape/src/cape/bootloader.c

@@ -0,0 +1,26 @@
+#include <stdint.h>
+
+#include <STM32F2XX.h>
+
+#include "cape/bootloader_handoff.h"
+
+// Sets everything up and then jumps to the main code.
+static void jump_to_main(void) __attribute__((noreturn));
+static void jump_to_main(void) {
+  __asm__ __volatile__(
+      "mov sp, %[stack]\n\t"
+      "bx %[reset]" : :
+      [stack]"r"(RAM_START + RAM_SIZE), [reset]"r"(MAIN_FLASH_START | 1)
+      : "memory");
+  __builtin_unreachable();
+}
+
+void _start(void) {
+  SYSCFG->CMPCR = SYSCFG_CMPCR_CMP_PD;  // enable IO compensation cell
+  while (!(SYSCFG->CMPCR & SYSCFG_CMPCR_READY)) {}  // wait for it to be ready
+
+  // We don't have anything on the 1 port D pin, so don't bother enabling it.
+  RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN;
+
+  jump_to_main();
+}

diff --git a/bbb_cape/src/cape/bootloader.ld b/bbb_cape/src/cape/bootloader.ld
new file mode 100644
index 0000000..21aaa00
--- /dev/null
+++ b/bbb_cape/src/cape/bootloader.ld

@@ -0,0 +1,13 @@
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x08000   /*  32k */
+  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x20000   /* 128k */
+}
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.vectors))
+	} > FLASH
+}

diff --git a/bbb_cape/src/cape/bootloader_handoff.h b/bbb_cape/src/cape/bootloader_handoff.h
new file mode 100644
index 0000000..d0fcde8
--- /dev/null
+++ b/bbb_cape/src/cape/bootloader_handoff.h

@@ -0,0 +1,15 @@
+#ifndef CAPE_BOOTLOADER_HANDOFF_H_
+#define CAPE_BOOTLOADER_HANDOFF_H_
+
+// This file has constants and functions for dealing with the handoff between
+// the bootloader and the main code.
+
+// How much flash the bootloader has (starting at address 0).
+#define BOOTLOADER_FLASH_SIZE 0x8000
+// Where the main code's flash starts.
+#define MAIN_FLASH_START BOOTLOADER_FLASH_SIZE
+
+#define RAM_START 0x20000000
+#define RAM_SIZE 0x20000
+
+#endif  // CAPE_BOOTLOADER_HANDOFF_H_

diff --git a/bbb_cape/src/cape/cows.c b/bbb_cape/src/cape/cows.c
new file mode 100644
index 0000000..b0d168e
--- /dev/null
+++ b/bbb_cape/src/cape/cows.c

@@ -0,0 +1,59 @@
+#include "cape/cows.h"
+
+#include <limits.h>
+
+// This implementation is based on
+// <http://www.jacquesf.com/2011/03/consistent-overhead-byte-stuffing/>.
+
+uint32_t cows_stuff(const void *restrict source_in, size_t source_length,
+                    void *restrict destination_in) {
+  const uint32_t *restrict source = (const uint32_t *)source_in;
+  uint32_t *restrict destination = (uint32_t *)destination_in;
+  size_t source_index = 0;
+  size_t destination_index = 1;
+  size_t code_index = 0;
+  uint32_t code = 1;
+
+  while (source_index < ((source_length - 1) / 4) + 1) {
+    if (source[source_index] == 0) {
+      destination[code_index] = code;
+      code = 1;
+      code_index = destination_index++;
+      ++source_index;
+    } else {
+      destination[destination_index++] = source[source_index++];
+      ++code;
+      if (code == UINT32_MAX) {
+        destination[code_index] = code;
+        code = 1;
+        code_index = destination_index++;
+      }
+    }
+  }
+  destination[code_index] = code;
+  return destination_index;
+}
+
+uint32_t cows_unstuff(const uint32_t *restrict source, size_t source_length,
+                      uint32_t *restrict destination) {
+  size_t source_index = 0;
+  size_t destination_index = 0;
+  uint32_t code;
+
+  while (source_index < ((source_length - 1) / 4) + 1) {
+    code = source[source_index];
+    if (source_index + code > source_length && code != 1) {
+      return 0;
+    }
+
+    ++source_index;
+
+    for (uint32_t i = 1; i < code; ++i) {
+      destination[destination_index++] = source[source_index++];
+    }
+    if (code != UINT32_MAX && source_index != source_length) {
+      destination[destination_index++] = 0;
+    }
+  }
+  return destination_index;
+}

diff --git a/bbb_cape/src/cape/cows.h b/bbb_cape/src/cape/cows.h
new file mode 100644
index 0000000..a589fca
--- /dev/null
+++ b/bbb_cape/src/cape/cows.h

@@ -0,0 +1,33 @@
+#ifndef CAPE_COWS_H_
+#define CAPE_COWS_H_
+
+#include <sys/types.h>
+#include <stdint.h>
+
+// This file implements something very similar to Consistent Overhead Byte
+// Stuffing <http://en.wikipedia.org/wiki/Consistent_Overhead_Byte_Stuffing>. It
+// uses that algorithm except with 4-byte chunks instead of individual bytes
+// because that's more efficient on 32-bit processors. I'm calling it Consistent
+// Overhead Word Stuffing.
+
+// source_length will be rounded up a multiple of 4. That many bytes of source
+// will be read.
+// destination must have at least
+// ([source_length rounded up to a multiple of 4] / (2^32 - 1) rounded up) * 4
+// more bytes than source_length available.
+// source and destination both have to be 4-byte aligned.
+// Returns the total number of words written (not necessarily the maximum given
+// in the above description of destination).
+uint32_t cows_stuff(const void *restrict source, size_t source_length,
+                    void *restrict destination);
+
+// source_length will be rounded up a multiple of 4. That many bytes of source
+// will be read.
+// Destination must be big enough to hold all source_length bytes (see
+// cows_stuff for the exact size it might be).
+// source and destination both have to be 4-byte aligned.
+// Returns the total number of words written to destination or 0 for error.
+uint32_t cows_unstuff(const uint32_t *restrict source, size_t source_length,
+                      uint32_t *restrict destination);
+
+#endif  // CAPE_COWS_H_

diff --git a/bbb_cape/src/cape/crc.c b/bbb_cape/src/cape/crc.c
new file mode 100644
index 0000000..fcce8b9
--- /dev/null
+++ b/bbb_cape/src/cape/crc.c

@@ -0,0 +1,15 @@
+#include "cape/crc.h"
+
+#include <STM32F2XX.h>
+
+void crc_init(void) {
+  RCC->AHB1ENR |= RCC_AHB1ENR_CRCEN;
+}
+
+uint32_t crc_calculate(uint32_t *restrict data, size_t words) {
+  CRC->CR = 1;  // reset it
+  for (; data < data + words; ++data) {
+    CRC->DR = *data;
+  }
+  return CRC->DR;
+}

diff --git a/bbb_cape/src/cape/crc.h b/bbb_cape/src/cape/crc.h
new file mode 100644
index 0000000..2aeed82
--- /dev/null
+++ b/bbb_cape/src/cape/crc.h

@@ -0,0 +1,13 @@
+#ifndef CAPE_CRC_H_
+#define CAPE_CRC_H_
+
+#include <stdint.h>
+#include <sys/types.h>
+
+void crc_init(void);
+
+// The second argument is the number of words to checksum, NOT the number of
+// bytes.
+uint32_t crc_calculate(uint32_t *restrict data, size_t words);
+
+#endif  // CAPE_CRC_H_

diff --git a/bbb_cape/src/cape/data_struct.h b/bbb_cape/src/cape/data_struct.h
new file mode 100644
index 0000000..95992b9
--- /dev/null
+++ b/bbb_cape/src/cape/data_struct.h

@@ -0,0 +1,79 @@
+// This isn't really a header file. It's designed to be #included directly into
+// other code (possibly in a namespace or whatever), so it doesn't have include
+// guards.
+// This means that it can not #include anything else because it (sometimes) gets
+// #included inside a namespace.
+// <stdint.h> must be #included by the containing file.
+// In the cape code, fill_packet.h #includes this file.
+// In the fitpc code, frc971/input/gyro_board_data.h #includes this file.
+
+#pragma pack(push, 1)
+// Be careful with declaration order in here. ARM doesn't like unaligned
+// accesses!
+struct DATA_STRUCT_NAME {
+  int64_t gyro_angle;
+
+  union {
+    struct {
+      // In 1/3us since the cape last reset.
+      uint64_t timestamp;
+
+      // The CRC32 (same algorithm as the checksum for the packet) of the whole
+      // contents of flash for the main code (aka what's in the .hex file).
+      uint32_t flash_checksum;
+
+      struct {
+        // If the current gyro_angle has been not updated because of a bad
+        // reading from the sensor.
+        uint8_t old_gyro_reading : 1;
+        // If the gyro is still initializing.
+        // If this is 1, then all of the other gyro data is invalid.
+        uint8_t uninitialized_gyro : 1;
+        // If the gyro is still zeroing.
+        // If this is 1, then all of the other gyro data is invalid.
+        uint8_t zeroing_gyro : 1;
+        // If we're not going to get any more good gyro_angles.
+        uint8_t bad_gyro : 1;
+      };
+    };
+    struct {
+      uint64_t header1, header2;
+    };
+  };
+
+  // We are 64-bit aligned at this point.
+
+  union {
+    struct {
+      int32_t encoders[8];
+
+      uint16_t analogs[8];
+
+      uint32_t digitals;
+    } main;
+    
+    struct {
+    } bot3;
+  };
+} __attribute__((aligned(8)));
+#pragma pack(pop)
+
+// The number of bytes that we actually send (so it stays consistent) (including
+// the byte-stuffing overhead and the CRC on the end).
+#define DATA_STRUCT_SEND_SIZE 200
+
+#ifdef __cplusplus
+#define STATIC_ASSERT(cond, msg) static_assert(cond, #msg)
+#endif
+// 4 bytes of 0s at the beginning, 4 bytes of byte-stuffing overhead, and 4
+// bytes of CRC on the end.
+STATIC_ASSERT(
+    (sizeof(struct DATA_STRUCT_NAME) + 8 + 4) <= DATA_STRUCT_SEND_SIZE,
+    The_sensor_data_structure_is_too_big);
+// The byte-stuffing and CRC both work in chunks of 4 bytes, so it has to be a
+// multiple of that in size.
+STATIC_ASSERT((sizeof(struct DATA_STRUCT_NAME) % 4) == 0,
+              The_sensor_data_structure_is_not_a_multiple_of_4_bytes);
+#ifdef __cplusplus
+#undef STATIC_ASSERT
+#endif

diff --git a/bbb_cape/src/cape/digital.c b/bbb_cape/src/cape/digital.c
new file mode 100644
index 0000000..a15b00b
--- /dev/null
+++ b/bbb_cape/src/cape/digital.c

@@ -0,0 +1,213 @@
+#include "cape/digital.h"
+
+#include <STM32F2XX.h>
+
+#include "cape/util.h"
+
+static void digital_capture_default(void) {}
+
+void digital_capture_0P(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_0N(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_1P(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_1N(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_2P(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_2N(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_3P(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_3N(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_4P(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_4N(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_5P(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_5N(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_6P(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_6N(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_7P(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_7N(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_8P(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_8N(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_9P(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_9N(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_10P(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_10N(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_11P(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_11N(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_12P(void) ALIAS_WEAK(digital_capture_default);
+void digital_capture_12N(void) ALIAS_WEAK(digital_capture_default);
+
+typedef void (*EXTIHandler)(uint32_t);
+
+void EXTI2_IRQHandler(void) {
+  uint32_t inputs = GPIOB->IDR;
+  EXTI->PR = EXTI_PR_PR2;
+  if (inputs & (1 << 2)) {
+    digital_capture_11N();
+  } else {
+    digital_capture_11P();
+  }
+}
+
+void EXTI4_IRQHandler(void) {
+  uint32_t inputs = GPIOC->IDR;
+  EXTI->PR = EXTI_PR_PR4;
+  if (inputs & (1 << 4)) {
+    digital_capture_0N();
+  } else {
+    digital_capture_0P();
+  }
+}
+
+static void EXTI5_Handler(uint32_t inputs) {
+  if (inputs & (1 << 5)) {
+    digital_capture_1N();
+  } else {
+    digital_capture_1P();
+  }
+}
+
+static void EXTI7_Handler(uint32_t inputs) {
+  if (inputs & (1 << 7)) {
+    digital_capture_10N();
+  } else {
+    digital_capture_10P();
+  }
+}
+
+static void EXTI8_Handler(uint32_t inputs) {
+  if (inputs & (1 << 7)) {
+    digital_capture_7N();
+  } else {
+    digital_capture_7P();
+  }
+}
+
+static void EXTI9_Handler(uint32_t inputs) {
+  if (inputs & (1 << 9)) {
+    digital_capture_6N();
+  } else {
+    digital_capture_6P();
+  }
+}
+
+void EXTI9_5_IRQHandler(void) {
+  uint32_t inputs = GPIOC->IDR;
+  uint32_t exti = __clz(EXTI->PR);
+  EXTI->PR = (1 << 31) >> exti;
+  switch (exti) {
+    case 31 - 5:
+      EXTI5_Handler(inputs);
+      break;
+    case 31 - 7:
+      EXTI7_Handler(inputs);
+      break;
+    case 31 - 8:
+      EXTI8_Handler(inputs);
+      break;
+    case 31 - 9:
+      EXTI9_Handler(inputs);
+      break;
+  }
+}
+
+static void EXTI10_Handler(uint32_t inputs) {
+  if (inputs & (1 << 10)) {
+    digital_capture_5N();
+  } else {
+    digital_capture_5P();
+  }
+}
+
+static void EXTI11_Handler(uint32_t inputs) {
+  if (inputs & (1 << 11)) {
+    digital_capture_9N();
+  } else {
+    digital_capture_9P();
+  }
+}
+
+static void EXTI12_Handler(uint32_t inputs) {
+  if (inputs & (1 << 12)) {
+    digital_capture_8N();
+  } else {
+    digital_capture_8P();
+  }
+}
+
+static void EXTI13_Handler(uint32_t inputs) {
+  if (inputs & (1 << 13)) {
+    digital_capture_2N();
+  } else {
+    digital_capture_2P();
+  }
+}
+
+static void EXTI14_Handler(uint32_t inputs) {
+  if (inputs & (1 << 14)) {
+    digital_capture_3N();
+  } else {
+    digital_capture_3P();
+  }
+}
+
+static void EXTI15_Handler(uint32_t inputs) {
+  if (inputs & (1 << 15)) {
+    digital_capture_4N();
+  } else {
+    digital_capture_4P();
+  }
+}
+
+void EXTI15_10_IRQHandler(void) {
+  uint32_t inputs = GPIOC->IDR;
+  uint32_t exti = __clz(EXTI->PR);
+  EXTI->PR = (1 << 31) >> exti;
+  switch (exti) {
+    case 31 - 10:
+      EXTI10_Handler(inputs);
+      break;
+    case 31 - 11:
+      EXTI11_Handler(inputs);
+      break;
+    case 31 - 12:
+      EXTI12_Handler(inputs);
+      break;
+    case 31 - 13:
+      EXTI13_Handler(inputs);
+      break;
+    case 31 - 14:
+      EXTI14_Handler(inputs);
+      break;
+    case 31 - 15:
+      EXTI15_Handler(inputs);
+      break;
+  }
+}
+
+static void init_exti(int exti, int port) {
+  EXTI_set(exti, port);
+  EXTI->IMR |= 1 << exti;
+  EXTI->RTSR |= 1 << exti;
+  EXTI->FTSR |= 1 << exti;
+}
+
+void digital_init(void) {
+  init_exti(2, 1);
+  init_exti(4, 2);
+  init_exti(5, 2);
+  init_exti(7, 0);
+  init_exti(8, 1);
+  init_exti(9, 1);
+  init_exti(10, 1);
+  init_exti(11, 0);
+  init_exti(12, 0);
+  init_exti(13, 2);
+  init_exti(14, 2);
+  init_exti(15, 2);
+
+  NVIC_SetPriority(EXTI2_IRQn, 1);
+  NVIC_EnableIRQ(EXTI2_IRQn);
+  NVIC_SetPriority(EXTI4_IRQn, 1);
+  NVIC_EnableIRQ(EXTI4_IRQn);
+  NVIC_SetPriority(EXTI9_5_IRQn, 1);
+  NVIC_EnableIRQ(EXTI9_5_IRQn);
+  NVIC_SetPriority(EXTI15_10_IRQn, 1);
+  NVIC_EnableIRQ(EXTI15_10_IRQn);
+}

diff --git a/bbb_cape/src/cape/digital.h b/bbb_cape/src/cape/digital.h
new file mode 100644
index 0000000..4905c23
--- /dev/null
+++ b/bbb_cape/src/cape/digital.h

@@ -0,0 +1,47 @@
+#ifndef CAPE_DIGITAL_H_
+#define CAPE_DIGITAL_H_
+
+#include <STM32F2XX.h>
+
+void digital_init(void);
+
+static inline int digital_read(int num) {
+  switch (num) {
+    case 0:
+      return GPIOC->IDR & (1 << 4);
+    case 1:
+      return GPIOC->IDR & (1 << 5);
+    case 2:
+      return GPIOC->IDR & (1 << 13);
+    case 3:
+      return GPIOC->IDR & (1 << 14);
+    case 4:
+      return GPIOC->IDR & (1 << 15);
+    case 5:
+      return GPIOB->IDR & (1 << 10);
+    case 6:
+      return GPIOB->IDR & (1 << 9);
+    case 7:
+      return GPIOB->IDR & (1 << 8);
+    case 8:
+      return GPIOA->IDR & (1 << 12);
+    case 9:
+      return GPIOA->IDR & (1 << 11);
+    case 10:
+      return GPIOA->IDR & (1 << 7);
+    case 11:
+      return GPIOB->IDR & (1 << 2);
+    default:
+      return 0;
+  }
+}
+
+// These are the functions for handling edges on the inputs. They have
+// default (weak symbol) implementations that do nothing.
+//void digital_capture_0P(void);
+//void digital_capture_0N(void);
+//void digital_capture_1P(void);
+//void digital_capture_1N(void);
+//...
+
+#endif  // CAPE_DIGITAL_H_

diff --git a/bbb_cape/src/cape/encoder.c b/bbb_cape/src/cape/encoder.c
new file mode 100644
index 0000000..31374db
--- /dev/null
+++ b/bbb_cape/src/cape/encoder.c

@@ -0,0 +1,130 @@
+#include "cape/encoder.h"
+
+#include <STM32F2XX.h>
+
+#include "cape/util.h"
+
+// Here is where each encoder is hooked up:
+// 0: PC6,PC7 TIM8
+// 1: PC0,PC1 EXTI0,EXTI1
+// 2: PA0,PA1 TIM5(32)
+// 3: PA2,PA3 EXTI2,EXTI3
+// 4: PA8,PB0 TIM1
+// 5: PA5,PB3 TIM2(32)
+// 6: PA6,PB5 TIM3
+// 7: PB6,PB7 TIM4
+
+volatile int32_t encoder1_value = 0;
+volatile int32_t encoder3_value = 0;
+
+// 1.A
+void EXTI0_IRQHandler(void) {
+  uint32_t inputs = GPIOA->IDR;
+  EXTI->PR = EXTI_PR_PR0;
+  // This looks like a weird way to XOR the 2 inputs, but it compiles down to
+  // just 2 instructions, which is hard to beat.
+  if (((inputs >> 1) ^ inputs) & (1 << 0)) {
+    ++encoder1_value;
+  } else {
+    --encoder1_value;
+  }
+}
+
+// 1.B
+void EXTI1_IRQHandler(void) {
+  uint32_t inputs = GPIOA->IDR;
+  EXTI->PR = EXTI_PR_PR1;
+  if (((inputs >> 1) ^ inputs) & (1 << 0)) {
+    --encoder1_value;
+  } else {
+    ++encoder1_value;
+  }
+}
+
+// 3.A
+void TIM1_TRG_COM_TIM11_IRQHandler(void) {
+  uint32_t inputs = GPIOC->IDR;
+  TIM9->SR = TIM_SR_CC1IF;
+  if (((inputs >> 1) ^ inputs) & (1 << 2)) {
+    ++encoder3_value;
+  } else {
+    --encoder3_value;
+  }
+}
+
+// 3.B
+void EXTI3_IRQHandler(void) {
+  uint32_t inputs = GPIOC->IDR;
+  EXTI->PR = EXTI_PR_PR3;
+  if (((inputs >> 1) ^ inputs) & (1 << 2)) {
+    --encoder3_value;
+  } else {
+    ++encoder3_value;
+  }
+}
+
+static void encoder_setup(TIM_TypeDef *timer) {
+  timer->CR1 = TIM_CR1_UDIS /* wait until we tell it to do anything */ |
+               TIM_CR1_URS /* don't generate spurious update interrupts that
+                              might be shared with other timers */;
+  timer->SMCR = 3;  // 4x quadrature encoder mode
+  timer->CCMR1 =
+      TIM_CCMR1_CC2S_0 | /* input pin 2 -> timer input 2 */
+      TIM_CCMR1_CC1S_0;  /* input pin 1 -> timer input 1*/
+  timer->EGR = TIM_EGR_UG;
+  timer->CR1 |= TIM_CR1_CEN;
+}
+
+void encoder_init(void) {
+  // Set up the 3 simple software encoder inputs.
+  EXTI_set(0, 2);
+  EXTI_set(1, 2);
+  EXTI_set(3, 0);
+  EXTI->IMR |= EXTI_IMR_MR0 | EXTI_IMR_MR1 | EXTI_IMR_MR3;
+  EXTI->RTSR |= EXTI_RTSR_TR0 | EXTI_RTSR_TR1 | EXTI_RTSR_TR3;
+  EXTI->FTSR |= EXTI_FTSR_TR0 | EXTI_FTSR_TR1 | EXTI_FTSR_TR3;
+  NVIC_EnableIRQ(EXTI0_IRQn);
+  NVIC_EnableIRQ(EXTI1_IRQn);
+  NVIC_EnableIRQ(EXTI3_IRQn);
+
+  // Set up the A2 software encoder input through TIM9.
+  gpio_setup_alt(GPIOA, 2, 3);
+  RCC->APB2ENR |= RCC_APB2ENR_TIM9EN;
+  TIM9->CR1 = TIM_CR1_UDIS;
+  TIM9->DIER = TIM_DIER_CC1IE;
+  TIM9->CCMR1 = TIM_CCMR1_CC1S_0; /* input pin 1 -> timer input 1 */
+  TIM9->CCER = TIM_CCER_CC1NP | TIM_CCER_CC1P | TIM_CCER_CC1E;
+  TIM9->EGR = TIM_EGR_UG;
+  TIM9->CR1 |= TIM_CR1_CEN;
+  NVIC_EnableIRQ(TIM1_BRK_TIM9_IRQn);
+
+  gpio_setup_alt(GPIOA, 8, 1);
+  gpio_setup_alt(GPIOB, 0, 1);
+  RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
+  encoder_setup(TIM1);
+
+  gpio_setup_alt(GPIOA, 5, 1);
+  gpio_setup_alt(GPIOB, 3, 1);
+  RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
+  encoder_setup(TIM2);
+
+  gpio_setup_alt(GPIOA, 6, 2);
+  gpio_setup_alt(GPIOB, 5, 2);
+  RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
+  encoder_setup(TIM3);
+
+  gpio_setup_alt(GPIOB, 6, 2);
+  gpio_setup_alt(GPIOB, 7, 2);
+  RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
+  encoder_setup(TIM4);
+
+  gpio_setup_alt(GPIOA, 0, 2);
+  gpio_setup_alt(GPIOA, 1, 2);
+  RCC->APB1ENR |= RCC_APB1ENR_TIM5EN;
+  encoder_setup(TIM5);
+
+  gpio_setup_alt(GPIOC, 6, 3);
+  gpio_setup_alt(GPIOC, 7, 3);
+  RCC->APB2ENR |= RCC_APB2ENR_TIM8EN;
+  encoder_setup(TIM8);
+}

diff --git a/bbb_cape/src/cape/encoder.h b/bbb_cape/src/cape/encoder.h
new file mode 100644
index 0000000..5a69835
--- /dev/null
+++ b/bbb_cape/src/cape/encoder.h

@@ -0,0 +1,80 @@
+#ifndef CAPE_ENCODER_H_
+#define CAPE_ENCODER_H_
+
+#include <stdint.h>
+#include <limits.h>
+
+#include <STM32F2XX.h>
+
+void encoder_init(void);
+
+// Updates a signed 32-bit counter with a new 16-bit value. Assumes that the
+// value will not more than half-wrap between updates.
+// new is 32 bits so it doesn't have to get masked, but the value passed in must
+// be <= UINT16_MAX.
+// Useful for 16-bit encoder counters.
+static inline void counter_update_s32_u16(int32_t *restrict counter,
+                                          uint32_t new) {
+  static const uint16_t kHalf = 0xFFFF / 2;
+  uint16_t old = *counter & 0xFFFF;
+  int32_t counter_top = *counter ^ old;
+  int32_t delta = (int32_t)new - (int32_t)old;
+  int32_t new_counter;
+  if (__builtin_expect(delta < -kHalf, 0)) {
+    new_counter = counter_top - 0x10000;
+  } else if (__builtin_expect(delta > kHalf, 0)) {
+    new_counter = counter_top + 0x10000;
+  } else {
+    new_counter = counter_top;
+  }
+  *counter = new_counter | new;
+}
+
+// Updates an unsigned 64-bit counter with a new 16-bit value. Assumes that the
+// value will not wrap more than once between updates.
+// new is 32 bits so it doesn't have to get masked, but the value passed in must
+// be <= UINT16_MAX.
+// Useful for 16-bit timers being used for absolute timings.
+static inline void counter_update_u64_u16(uint64_t *restrict counter,
+                                          uint32_t new) {
+  uint16_t old = *counter & 0xFFFF;
+  int64_t counter_top = *counter ^ old;
+  if (__builtin_expect(new < old, 0)) {
+    *counter = counter_top + 0x10000;
+  } else {
+    *counter = counter_top;
+  }
+  *counter |= new;
+}
+
+// number is the 0-indexed number on the silkscreen
+static inline int32_t encoder_read(int number) {
+  static int32_t value0, value4, value6, value7;
+  extern volatile int32_t encoder1_value, encoder3_value;
+  switch (number) {
+    case 0:
+      counter_update_s32_u16(&value0, TIM8->CNT);
+      return value0;
+    case 1:
+      return encoder1_value;
+    case 2:
+      return TIM5->CNT;
+    case 3:
+      return encoder3_value;
+    case 4:
+      counter_update_s32_u16(&value4, TIM1->CNT);
+      return value4;
+    case 5:
+      return TIM2->CNT;
+    case 6:
+      counter_update_s32_u16(&value6, TIM3->CNT);
+      return value6;
+    case 7:
+      counter_update_s32_u16(&value7, TIM4->CNT);
+      return value7;
+    default:
+      return INT32_MAX;
+  }
+}
+
+#endif  // CAPE_ENCODER_H_

diff --git a/bbb_cape/src/cape/fill_packet.c b/bbb_cape/src/cape/fill_packet.c
new file mode 100644
index 0000000..700df1d
--- /dev/null
+++ b/bbb_cape/src/cape/fill_packet.c

@@ -0,0 +1,88 @@
+#include "cape/fill_packet.h"
+
+#include <string.h>
+
+#include <STM32F2XX.h>
+
+#include "cape/uart_dma.h"
+#include "cape/uart_common.h"
+#include "cape/cows.h"
+#include "cape/encoder.h"
+#include "cape/crc.h"
+#include "cape/bootloader_handoff.h"
+#include "cape/gyro.h"
+#include "cape/led.h"
+#include "cape/analog.h"
+#include "cape/robot.h"
+#include "cape/digital.h"
+
+#define TIMESTAMP_TIM TIM6
+#define RCC_APB1ENR_TIMESTAMP_TIMEN RCC_APB1ENR_TIM6EN
+
+static uint8_t buffer1[DATA_STRUCT_SEND_SIZE] __attribute__((aligned(4)));
+static uint8_t buffer2[DATA_STRUCT_SEND_SIZE] __attribute__((aligned(4)));
+
+static uint32_t flash_checksum;
+// These aren't really integers; they're (4-byte) variables whose addresses mark
+// various locations.
+extern uint8_t __etext, __data_start__, __data_end__;
+
+static inline void do_fill_packet(struct DataStruct *packet) {
+  static uint64_t timestamp = 0;
+  counter_update_u64_u16(&timestamp, TIMESTAMP_TIM->CNT);
+  packet->timestamp = timestamp;
+
+  packet->flash_checksum = flash_checksum;
+
+  struct GyroOutput gyro_output;
+  gyro_get_output(&gyro_output);
+  packet->gyro_angle = gyro_output.angle;
+  packet->old_gyro_reading = gyro_output.last_reading_bad;
+  packet->uninitialized_gyro = !gyro_output.initialized;
+  packet->zeroing_gyro = !gyro_output.zeroed;
+  packet->bad_gyro = gyro_output.gyro_bad;
+
+  robot_fill_packet(packet);
+}
+
+// Fills the new packet with data.
+void uart_dma_callback(uint8_t *buffer) {
+  struct {
+    struct DataStruct packet;
+    uint8_t padding[DATA_STRUCT_SEND_SIZE - sizeof(struct DataStruct) - 12];
+    uint32_t checksum;
+  } data __attribute__((aligned(4)));
+  STATIC_ASSERT(sizeof(data) == DATA_STRUCT_SEND_SIZE - 8,
+                The_size_of_the_data_is_wrong);
+  struct DataStruct *packet = &data.packet;
+
+  do_fill_packet(packet);
+
+  uint32_t *p;
+  memcpy(&p, &packet, sizeof(void *));
+  data.checksum = crc_calculate(p, sizeof(*packet) / 4);
+
+  ((uint32_t *)buffer)[0] = 0;
+  cows_stuff(&data, sizeof(data), buffer + 4);
+}
+
+void fill_packet_start(void) {
+  RCC->APB1ENR |= RCC_APB1ENR_TIMESTAMP_TIMEN;
+  TIMESTAMP_TIM->CR1 = TIM_CR1_UDIS;
+  TIMESTAMP_TIM->EGR = TIM_EGR_UG;
+  TIMESTAMP_TIM->CR1 |= TIM_CR1_CEN;
+
+  crc_init();
+  led_init();
+  analog_init();
+  encoder_init();
+  gyro_init();
+  digital_init();
+
+  uint8_t *flash_end = &__etext + (&__data_start__ - &__data_end__) + 8;
+  flash_checksum = crc_calculate((void *)MAIN_FLASH_START,
+                                 (size_t)(flash_end - MAIN_FLASH_START) / 4);
+
+  uart_common_configure(3000000);
+  uart_dma_configure(DATA_STRUCT_SEND_SIZE, buffer1, buffer2);
+}

diff --git a/bbb_cape/src/cape/fill_packet.h b/bbb_cape/src/cape/fill_packet.h
new file mode 100644
index 0000000..f3f1543
--- /dev/null
+++ b/bbb_cape/src/cape/fill_packet.h

@@ -0,0 +1,14 @@
+#ifndef CAPE_FILL_PACKET_H_
+#define CAPE_FILL_PACKET_H_
+
+#include <stdint.h>
+
+#include "cape/util.h"
+#define DATA_STRUCT_NAME DataStruct
+#include "cape/data_struct.h"
+#undef DATA_STRUCT_NAME
+
+// Starts writing out sensor packets as fast as the serial port can write them.
+void fill_packet_start(void);
+
+#endif  // CAPE_FILL_PACKET_H_

diff --git a/bbb_cape/src/cape/gcc_arm.ld b/bbb_cape/src/cape/gcc_arm.ld
new file mode 100644
index 0000000..1a1cb27
--- /dev/null
+++ b/bbb_cape/src/cape/gcc_arm.ld

@@ -0,0 +1,145 @@
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+
+		/* bootloader.ld sticks this at the beginning of FLASH before here */
+		KEEP(*(.vectors))
+
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		end = __end__;
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

diff --git a/bbb_cape/src/cape/gyro.c b/bbb_cape/src/cape/gyro.c
new file mode 100644
index 0000000..80accb9
--- /dev/null
+++ b/bbb_cape/src/cape/gyro.c

@@ -0,0 +1,394 @@
+#include "cape/gyro.h"
+
+#include <inttypes.h>
+
+#include <STM32F2XX.h>
+
+#include "cape/util.h"
+#include "cape/led.h"
+
+#define printf(...)
+
+#define SPI SPI3
+#define SPI_IRQHandler SPI3_IRQHandler
+#define SPI_IRQn SPI3_IRQn
+#define RCC_APB1ENR_SPIEN RCC_APB1ENR_SPI3EN
+#define TIM TIM13
+#define TIM_IRQHandler TIM8_UP_TIM13_IRQHandler
+#define TIM_IRQn TIM8_UP_TIM13_IRQn
+#define RCC_APB1ENR_TIMEN RCC_APB1ENR_TIM13EN
+#define CSEL_GPIO GPIOA
+#define CSEL_NUM 4
+// The header file also contains references to TIM in gyro_read.
+
+struct GyroOutput gyro_output;
+
+// Set when a parity error is detected and cleared before starting a read.
+static volatile int parity_error;
+// Which byte we're currently waiting to read.
+static volatile int receive_byte;
+// The first byte that we receive (the most significant one).
+static volatile uint16_t high_value;
+
+// 1 if the latest result is potentially bad and 0 if it's good.
+static volatile int bad_reading;
+// 1 if the gyro is bad adn we're not going to get any more readings.
+static volatile int bad_gyro;
+// The new reading waiting for the next timer cycle to be outputted.
+static volatile int16_t new_reading;
+
+struct GyroOutput gyro_output;
+
+// How many times per second to read the gyro value.
+#define kGyroReadFrequency 200
+// How many times per second to flash the LED.
+// Must evenly divide kGyroReadFrequency.
+#define kFlashFrequency 10
+
+#define kStartupCycles (kGyroReadFrequency * 2)
+#define kZeroingCycles (kGyroReadFrequency * 6)
+
+// An accumulator for all of the values read while zeroing.
+int32_t zero_bias = 0;
+
+int startup_cycles_left = kStartupCycles;
+int zeroing_cycles_left = kZeroingCycles;
+
+// These are a pair that hold the offset calculated while zeroing.
+// full_units_ is the base (in ticks) and remainder_ ranges between 0 and
+// kZeroingCycles (like struct timespec). remainder_ is used to calculate which
+// cycles to add an additional unit to the result.
+int32_t full_units_offset = 0;
+int32_t remainder_offset = 0;
+// This keeps track of when to add 1 to the read value (using _offset).
+int32_t remainder_sum = 0;
+
+int32_t led_flash = 0;
+
+enum State {
+  STATE_SETUP0,
+  STATE_SETUP1,
+  STATE_SETUP2,
+  STATE_SETUP3,
+  STATE_READ,
+};
+static volatile enum State state;
+static int setup_counter;
+
+// Switches to new_state in time TIM milliseconds (aka it shows in the TIM ISR).
+static void switch_state(enum State new_state, int time) {
+  TIM->CR1 = TIM_CR1_UDIS;
+  state = new_state;
+  TIM->CCR1 = time;
+  TIM->EGR = TIM_EGR_UG;
+  TIM->CR1 |= TIM_CR1_CEN;
+}
+
+static void gyro_setup_failed(void) {
+  printf("gyro setup failed. stopping\n");
+  gyro_output.angle = 0;
+  gyro_output.last_reading_bad = gyro_output.gyro_bad = 1;
+  gyro_output.initialized = 1;
+  gyro_output.zeroed = 0;
+}
+
+static void gyro_enable_csel(void) {
+  // Clear the CSEL pin to select it.
+  // Do it 8 times (9 cycles) to wait for the amount of time the gyro datasheet
+  // says we need to.
+  // (1/2/(7.5MHz)+8ns)*120MHz = 8.96
+  for (int i = 0; i < 8; ++i) CSEL_GPIO->BSRRH = 1 << CSEL_NUM;
+}
+
+// Blocks until there is space to enqueue data.
+static void spi_write(uint16_t data) {
+  while (!(SPI->SR & SPI_SR_TXE)) {}
+  SPI->DR = data;
+}
+
+static void do_gyro_read(uint32_t data) {
+  parity_error = 0;
+  receive_byte = 0;
+
+  gyro_enable_csel();
+  spi_write(data >> 16);
+  if (__builtin_parity(data & ~1) == 0) data |= 1;
+  spi_write(data);
+}
+
+// Returns all of the non-data bits in the "header" except the parity from
+// value.
+static uint8_t gyro_status(uint32_t value) {
+  return (value >> 26) & ~4;
+}
+
+// Returns all of the error bits in the "footer" from value.
+static uint8_t gyro_errors(uint32_t value) {
+  return (value >> 1) & 0x7F;
+}
+
+static void process_reading(int16_t reading) {
+  switch (state) {
+    case STATE_SETUP0:
+      if (parity_error) {
+        switch_state(STATE_SETUP0, 100);
+      } else {
+        if (reading != 1) {
+          printf("gyro unexpected initial response 0x%"PRIx32"\n", reading);
+          // There's a chance that we're retrying because of a parity error
+          // previously, so keep going.
+        }
+        // Wait for it to assert the fault conditions before reading them.
+        switch_state(STATE_SETUP1, 50);
+      }
+      break;
+    case STATE_SETUP1:
+      if (parity_error) {
+        switch_state(STATE_SETUP0, 100);
+      } else {
+        // Wait for it to clear the fault conditions before reading again.
+        switch_state(STATE_SETUP2, 50);
+      }
+      break;
+    case STATE_SETUP2:
+      if (parity_error) {
+        switch_state(STATE_SETUP0, 100);
+      } else {
+        // If it's not reporting self test data.
+        if (gyro_status(reading) != 2) {
+          printf("gyro first value 0x%"PRIx32" not self test data\n", reading);
+          switch_state(STATE_SETUP0, 100);
+          break;
+        }
+        // If we don't see all of the errors.
+        if (gyro_errors(reading) != 0x7F) {
+          printf("gyro self test value 0x%"PRIx32" is bad\n", reading);
+          gyro_setup_failed();
+          break;
+        }
+        // Wait for the sequential transfer delay before reading out the last of
+        // the self test data.
+        switch_state(STATE_SETUP3, 1);
+      }
+      break;
+    case STATE_SETUP3:
+      if (parity_error) {
+        switch_state(STATE_SETUP0, 100);
+      } else {
+        // It should still be reporting self test data.
+        if (gyro_status(reading) != 2) {
+          printf("gyro second value 0x%"PRIx32" not self test data\n", reading);
+          switch_state(STATE_SETUP0, 100);
+          break;
+        }
+
+        gyro_output.initialized = 1;
+        gyro_output.angle = 0;
+        gyro_output.last_reading_bad = 1;  // until we're started up
+        gyro_output.gyro_bad = 0;
+        // Start reading values (after the sequential transfer delay).
+        switch_state(STATE_READ, 1);
+      }
+      break;
+    case STATE_READ:
+      new_reading = reading;
+      switch_state(STATE_READ, 1000 / kGyroReadFrequency);
+      break;
+  }
+}
+
+static void reading_received(uint32_t value) {
+  if (parity_error) {
+    bad_reading = 1;
+  } else {
+    // This check assumes that the sequence bits are all 0, but they should be
+    // because that's all we send.
+    if (gyro_status(value) != 1) {
+      uint8_t status = gyro_status(value);
+      if (status == 0) {
+        printf("gyro says sensor data is bad\n");
+      } else {
+        printf("gyro gave weird status 0x%"PRIx8"\n", status);
+      }
+      bad_reading = 1;
+    }
+
+    if (gyro_errors(value) != 0) {
+      uint8_t errors = gyro_errors(value);
+      if (errors & ~(1 << 1)) {
+        bad_reading = 1;
+        // Error 1 (continuous self-test error) will set status to 0 if it's bad
+        // enough by itself.
+      }
+      if (errors & (1 << 6)) {
+        printf("gyro PLL error\n");
+      }
+      if (errors & (1 << 5)) {
+        printf("gyro quadrature error\n");
+      }
+      if (errors & (1 << 4)) {
+        printf("gyro non-volatile memory error\n");
+        bad_gyro = 1;
+      }
+      if (errors & (1 << 3)) {
+        printf("gyro volatile memory error\n");
+        bad_gyro = 1;
+      }
+      if (errors & (1 << 2)) {
+        printf("gyro power error\n");
+      }
+      if (errors & (1 << 1)) {
+        printf("gyro continuous self-test error\n");
+      }
+      if (errors & 1) {
+        printf("gyro unexpected self check mode\n");
+      }
+    }
+    if (bad_gyro) {
+      bad_reading = 1;
+    }
+  }
+  process_reading(-(int16_t)(value >> 10 & 0xFFFF));
+}
+
+void SPI_IRQHandler(void) {
+  uint32_t status = SPI->SR;
+  if (status & SPI_SR_RXNE) {
+    uint16_t value = SPI->DR;
+    if (__builtin_parity(value) != 1) {
+      parity_error = 1;
+    }
+    if (receive_byte == 0) {
+      receive_byte = 1;
+      high_value = value;
+    } else {
+      uint32_t full_value = high_value << 16 | value;
+      // Set the CSEL pin high to deselect it.
+      // The parity calculation etc took long enough that this is safe now.
+      CSEL_GPIO->BSRRL = 1 << CSEL_NUM;
+      reading_received(full_value);
+    }
+  }
+}
+
+void TIM_IRQHandler(void) {
+  TIM->CR1 &= ~TIM_CR1_CEN;
+  TIM->SR = TIM_SR_CC1IF;
+  switch (state) {
+    case STATE_SETUP0:
+      if (setup_counter++ < 100) {
+        // Get it started doing a check.
+        do_gyro_read(0x20000003);
+      } else {
+        gyro_setup_failed();
+      }
+      break;
+    case STATE_SETUP1:  // Dummy read to clear the old latched state.
+    case STATE_SETUP2:  // Read self-test data.
+    case STATE_SETUP3:  // Read the second latched self-test data.
+      do_gyro_read(0x20000000);
+      break;
+    case STATE_READ:
+      ++led_flash;
+      if (led_flash < kGyroReadFrequency / kFlashFrequency / 2) {
+        led_set(LED_HB, 0);
+      } else {
+        led_set(LED_HB, 1);
+      }
+      if (led_flash >= kGyroReadFrequency / kFlashFrequency) {
+        led_flash = 0;
+      }
+
+      if (bad_gyro) {
+        led_set(LED_ERR, 1);
+        printf("gyro reader giving up because of bad gyro\n");
+        gyro_output.gyro_bad = 1;
+        gyro_output.last_reading_bad = 1;
+        gyro_output.angle = 0;
+        break;
+      }
+
+      if (startup_cycles_left) {
+        led_set(LED_Z, 0);
+        --startup_cycles_left;
+        if (bad_reading) {
+          printf("gyro retrying startup wait because of bad reading\n");
+          startup_cycles_left = kStartupCycles;
+        }
+      } else if (zeroing_cycles_left) {
+        led_set(LED_Z, 1);
+        --zeroing_cycles_left;
+        if (bad_reading) {
+          printf("gyro restarting zeroing because of bad reading\n");
+          zeroing_cycles_left = kZeroingCycles;
+          zero_bias = 0;
+        } else {
+          zero_bias -= new_reading;
+          if (zeroing_cycles_left == 0) {
+            // Do all the nice math
+            full_units_offset = zero_bias / kZeroingCycles;
+            remainder_offset = zero_bias % kZeroingCycles;
+            if (remainder_offset < 0) {
+              remainder_offset += kZeroingCycles;
+              --full_units_offset;
+            }
+            gyro_output.zeroed = 1;
+          }
+        }
+      } else {
+        led_set(LED_Z, 0);
+
+        int64_t new_angle = gyro_output.angle;
+        if (!bad_reading) new_angle += new_reading + full_units_offset;
+        if (remainder_sum >= kZeroingCycles) {
+          remainder_sum -= kZeroingCycles;
+          new_angle += 1;
+        }
+        gyro_output.angle = new_angle;
+        gyro_output.last_reading_bad = bad_reading;
+        remainder_sum += remainder_offset;
+      }
+      do_gyro_read(0x20000000);
+      break;
+  }
+}
+
+void gyro_init(void) {
+  gyro_output.initialized = 0;
+  gyro_output.zeroed = 0;
+
+  RCC->APB1ENR |= RCC_APB1ENR_SPIEN;
+  RCC->APB1ENR |= RCC_APB1ENR_TIMEN;
+
+  // Set up CSEL.
+  // It's is just a GPIO pin because we're the master (it would be special if we
+  // were a slave).
+  gpio_setup_out(CSEL_GPIO, CSEL_NUM, 3);
+  CSEL_GPIO->BSRRL = 1 << CSEL_NUM;  // make sure it's deselected
+
+  // Set up SCK, MISO, and MOSI.
+  gpio_setup_alt(GPIOC, 10, 6);  // SCK
+  gpio_setup_alt(GPIOC, 11, 6);  // MISO
+  gpio_setup_alt(GPIOC, 12, 6);  // MOSI
+
+  NVIC_SetPriority(SPI_IRQn, 4);
+  NVIC_EnableIRQ(SPI_IRQn);
+  NVIC_SetPriority(TIM_IRQn, 5);
+  NVIC_EnableIRQ(TIM_IRQn);
+
+  TIM->CR1 = TIM_CR1_UDIS;
+  TIM->DIER = TIM_DIER_CC1IE;
+  TIM->CCMR1 = 0;
+  TIM->PSC = 30000 - 1;
+
+  SPI->CR1 = 0;  // make sure it's disabled
+  SPI->CR1 =
+      SPI_CR1_DFF /* 16 bit frame */ |
+      1 << 3 /* 30MHz/4 = 7.5MHz */ |
+      SPI_CR1_MSTR /* master mode */;
+  SPI->CR2 = SPI_CR2_RXNEIE;
+  SPI->CR1 |= SPI_CR1_SPE;  // enable it
+
+  setup_counter = 0;
+  switch_state(STATE_SETUP0, 100);
+}

diff --git a/bbb_cape/src/cape/gyro.h b/bbb_cape/src/cape/gyro.h
new file mode 100644
index 0000000..1536718
--- /dev/null
+++ b/bbb_cape/src/cape/gyro.h

@@ -0,0 +1,30 @@
+#ifndef GYRO_BOARD_SRC_USB_GYRO_H_
+#define GYRO_BOARD_SRC_USB_GYRO_H_
+
+#include <stdint.h>
+#include <string.h>
+
+#include <STM32F2XX.h>
+
+// Does everything to set up the gyro code, including starting a timer which
+// triggers reads and integrates the gyro values and blinks the LEDs etc.
+void gyro_init(void);
+
+struct GyroOutput {
+  int64_t angle;
+  int last_reading_bad;
+  int gyro_bad;
+  int initialized;
+  int zeroed;
+};
+
+// Reads the most recent output value and avoids race conditions.
+// Must be called from a lower-priority ISR than TIM10's.
+static inline void gyro_get_output(struct GyroOutput *output) {
+  extern struct GyroOutput gyro_output;
+  NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn);
+  memcpy(output, &gyro_output, sizeof(gyro_output));
+  NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);
+}
+
+#endif  // GYRO_BOARD_SRC_USB_GYRO_H_

diff --git a/bbb_cape/src/cape/hardware.notes b/bbb_cape/src/cape/hardware.notes
new file mode 100644
index 0000000..73593b6
--- /dev/null
+++ b/bbb_cape/src/cape/hardware.notes

@@ -0,0 +1,81 @@
+EXTI interrupt groupings:
+  by number in the port
+  0,1,2,3,4,5-9,10-15
+
+
+PA0  TIM5.1
+PA1  TIM5.2
+PA2
+PA3
+PA4  SPI3_NSS (slave select)
+PA5  TIM2.1
+PA6  TIM3.1
+PA7
+PA8  TIM1.1
+PA9  USART1_TX (bootloader)
+PA10 USART1_RX (bootloader)
+PA11 (don't change during reset into bootloader)
+PA12 (don't change during reset into bootloader)
+PA13 SWDIO
+PA14 SWCLK
+PA15 (gets pulled up during reset (JTAG pin))
+PB0  TIM1.2
+PB1
+PB2  BOOT1 (tie to GND)
+PB3  TIM2.2
+PB4  (gets pulled up during reset (JTAG pin))
+PB5  TIM3.2 (don't change during reset into bootloader)
+PB6  TIM4.1
+PB7  TIM4.2
+PB8
+PB9
+PB10
+PB11 (don't change during reset into bootloader)
+PB12 SPI2_NSS (slave select)
+PB13 SPI2_SCK
+PB14 SPI2_MISO
+PB15 SPI2_MOSI
+PC0
+PC1
+PC2
+PC3
+PC4
+PC5
+PC6  TIM8.1
+PC7  TIM8.2
+PC8
+PC9
+PC10 SPI3_SCK
+PC11 SPI3_MISO
+PC12 SPI3_MOSI
+PC13
+PC14
+PC15
+PD2
+
+[GPIOs]
+C0  enc
+C1  enc
+A2  enc (as TIM9.1)
+A3  enc
+
+B2
+C4
+C5
+A7
+B8
+B9
+B10
+A11
+A12
+C13
+C14
+C15
+
+C8  BBB_RST TIM8.3
+
+
+IO compensation cell?
+  controls slew rates
+  increased power draw
+  should probably just enable it?

diff --git a/bbb_cape/src/cape/led.c b/bbb_cape/src/cape/led.c
new file mode 100644
index 0000000..1968f96
--- /dev/null
+++ b/bbb_cape/src/cape/led.c

@@ -0,0 +1,48 @@
+#include "cape/led.h"
+
+#include <STM32F2XX.h>
+
+#include "cape/util.h"
+
+#define LED_SPEED 0
+
+// DB = PC3
+// Z = PB1
+// HB = PB4
+// ERR = PB11
+
+static void do_led_set(GPIO_TypeDef *port, int number, int on) {
+  if (on) {
+    port->BSRRL = 1 << number;
+  } else {
+    port->BSRRH = 1 << number;
+  }
+}
+
+void led_set(enum LED led, int on) {
+  switch (led) {
+    case LED_ERR:
+      do_led_set(GPIOB, 11, on);
+      break;
+    case LED_HB:
+      do_led_set(GPIOB, 4, on);
+      break;
+    case LED_Z:
+      do_led_set(GPIOB, 1, on);
+      break;
+    case LED_DB:
+      do_led_set(GPIOC, 3, on);
+      break;
+  }
+}
+
+void led_init(void) {
+  gpio_setup_out(GPIOB, 11, LED_SPEED);
+  led_set(LED_ERR, 0);
+  gpio_setup_out(GPIOB, 4, LED_SPEED);
+  led_set(LED_HB, 0);
+  gpio_setup_out(GPIOB, 1, LED_SPEED);
+  led_set(LED_Z, 0);
+  gpio_setup_out(GPIOC, 3, LED_SPEED);
+  led_set(LED_DB, 0);
+}

diff --git a/bbb_cape/src/cape/led.h b/bbb_cape/src/cape/led.h
new file mode 100644
index 0000000..ee47853
--- /dev/null
+++ b/bbb_cape/src/cape/led.h

@@ -0,0 +1,17 @@
+#ifndef CAPE_LED_H_
+#define CAPE_LED_H_
+
+// The LEDs as referenced by the silkscreen.
+enum LED {
+  LED_ERR,
+  LED_HB,
+  LED_Z,
+  LED_DB,
+};
+
+// Turns the indicated LED on or off.
+void led_set(enum LED led, int on);
+
+void led_init(void);
+
+#endif  // CAPE_LED_H_

diff --git a/bbb_cape/src/cape/main.c b/bbb_cape/src/cape/main.c
new file mode 100644
index 0000000..411a734
--- /dev/null
+++ b/bbb_cape/src/cape/main.c

@@ -0,0 +1,26 @@
+#include <STM32F2XX.h>
+
+#include "cape/fill_packet.h"
+
+// The startup asm code defines this to the start of our exception vector table.
+extern uint32_t _vectors;
+
+void _start(void) {
+  // Change the vector table offset to use our vector table instead of the
+  // bootloader's.
+  SCB->VTOR = (uint32_t)&_vectors;
+  // Data Memory Barrier to make sure it gets the updated vector table.
+  __asm__ __volatile__("dmb");
+
+  fill_packet_start();
+
+  // Make it go right to sleep after handling all exceptions. This actually
+  // decreses ISR latency a little bit because it doesn't have to stack the
+  // registers for the first one.
+  SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
+  // This seems like the perfect place to use WFI, but Brian on 2013-12-13
+  // couldn't find anything verifying that WFI doesn't increase the latency for
+  // the first interrupt handled, and we should never actually get here anyways,
+  // so it doesn't matter.
+  while (1) {}
+}

diff --git a/bbb_cape/src/cape/main.ld b/bbb_cape/src/cape/main.ld
new file mode 100644
index 0000000..ec39b8f
--- /dev/null
+++ b/bbb_cape/src/cape/main.ld

@@ -0,0 +1,14 @@
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00008000, LENGTH = 0xF8000   /* 1024k - 32k */
+  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x20000   /* 128k */
+}
+
+SECTIONS
+{
+	.text :
+	{
+		/* make sure this stays at the beginning of FLASH */
+		KEEP(*(Reset_Handler))
+	} > FLASH
+}

diff --git a/bbb_cape/src/cape/main_test.ld b/bbb_cape/src/cape/main_test.ld
new file mode 120000
index 0000000..af355cc
--- /dev/null
+++ b/bbb_cape/src/cape/main_test.ld

@@ -0,0 +1 @@
+main.ld
\ No newline at end of file

diff --git a/bbb_cape/src/cape/peripherial_usage.notes b/bbb_cape/src/cape/peripherial_usage.notes
new file mode 100644
index 0000000..5980be0
--- /dev/null
+++ b/bbb_cape/src/cape/peripherial_usage.notes

@@ -0,0 +1,51 @@
+This file documents what code is using which peripherial(s), priorities when
+applicable, and which file(s) the code is in. The purpose is to make assigning
+priorities to everything else easier because the relative priorities of
+everything is what matters; the absolute priority is meaningless. It also helps
+with choosing things like timers.
+
+[BBB communication]
+uart_common
+  USART1
+uart
+  USART1_IRQ:3
+uart_dma
+  DMA2.7:2
+  DMA2.7_IRQ:8
+uart_byte
+  TIM7
+
+[gyro communication]
+gyro
+  SPI3
+  SPI3_IRQ:4
+  TIM13
+  TIM13_IRQ:5 (aka TIM8_UP)
+
+[ADC communication]
+analog
+  SPI2
+  SPI2_IRQ:6
+  TIM14
+  TIM14_IRQ:6 (aka TIM8_TRG_COM)
+
+[encoders]
+encoder
+  TIM1,TIM2,TIM3,TIM4,TIM5,TIM8
+  EXTI0,EXTI1,EXTI3
+  EXTI0_IRQ:0,EXTI1_IRQ:0,EXTI3_IRQ:0
+  TIM9 (for its input capture 1)
+  TIM9_IRQ:0 (aka TIM1_BRK)
+
+[digital inputs]
+digital
+  EXTI2,EXTI4-15
+  EXTI2_IRQ:1,EXTI4-15_IRQ:1
+
+[sensor packet sending]
+fill_packet
+  TIM6
+
+[utilities]
+crc
+  CRC

diff --git a/bbb_cape/src/cape/robot.h b/bbb_cape/src/cape/robot.h
new file mode 100644
index 0000000..02da3e2
--- /dev/null
+++ b/bbb_cape/src/cape/robot.h

@@ -0,0 +1,11 @@
+#ifndef CAPE_ROBOT_H_
+#define CAPE_ROBOT_H_
+
+// This header file is for the robot-specific files which should be named
+// robot_name.c. It documents what functions each robot should implement.
+
+#include "cape/fill_packet.h"
+
+void robot_fill_packet(struct DataStruct *packet);
+
+#endif  // CAPE_ROBOT_H_

diff --git a/bbb_cape/src/cape/robot_test.c b/bbb_cape/src/cape/robot_test.c
new file mode 100644
index 0000000..02c1580
--- /dev/null
+++ b/bbb_cape/src/cape/robot_test.c

@@ -0,0 +1,22 @@
+#include "cape/robot.h"
+
+#include "cape/encoder.h"
+#include "cape/analog.h"
+#include "cape/digital.h"
+
+void robot_fill_packet(struct DataStruct *packet) {
+  packet->main.encoders[0] = encoder_read(0);
+  packet->main.encoders[1] = encoder_read(1);
+  packet->main.encoders[2] = encoder_read(2);
+  packet->main.encoders[3] = encoder_read(3);
+  packet->main.encoders[4] = encoder_read(4);
+  packet->main.encoders[5] = encoder_read(5);
+  packet->main.encoders[6] = encoder_read(6);
+  packet->main.encoders[7] = encoder_read(7);
+
+  for (int i = 0; i < 8; ++i) {
+    packet->main.analogs[i] = analog_get(i);
+  }
+
+  // TODO(brians): digitals
+}

diff --git a/bbb_cape/src/cape/startup.notes b/bbb_cape/src/cape/startup.notes
new file mode 100644
index 0000000..eac1b35
--- /dev/null
+++ b/bbb_cape/src/cape/startup.notes

@@ -0,0 +1,23 @@
+This file describes the processor startup process.
+
+The basic idea is that the bootloader and main code each have their own
+exception handler tables and code. The bootloader's code lives at the bottom
+of flash and the main code is in the rest of it. They both use the same startup
+code (STM32F2XX_startup.S, which deals with copying .data etc into RAM and
+zeroing RAM for .bss etc. This same file also defines the layout of the
+exception table (full of weak symbols). Although they both use the same startup
+code, it gets put into different places by the different linker scripts. The
+main code's exception table is in .data so it gets copied into RAM before being
+used to avoid waiting for flash reads to handle interrupts, but the bootloader's
+just gets put in flash because it has to be there (at address 0) and it doesn't
+care about interrupt performance.
+
+The bootloader code has its exception table starting at address 0, which is
+where the processor goes to start. The processor sets the stack pointer to the
+1st entry in the table and then jumps to the 2nd (the reset handler). Our
+bootloader then checks if it should pass through to the main code. If it does
+that, it then uses the same kind of interface to the main code's startup file.
+The main code's exception table lives in RAM, so the bootloader just uses the
+stack pointer and reset handler values that it knows because they're always the
+same (stack pointer to the top of RAM and reset handler at the beginning of
+the main code's flash).

diff --git a/bbb_cape/src/cape/toolchain-build-notes.txt b/bbb_cape/src/cape/toolchain-build-notes.txt
new file mode 100644
index 0000000..d81c905
--- /dev/null
+++ b/bbb_cape/src/cape/toolchain-build-notes.txt

@@ -0,0 +1,23 @@
+These are Brian's notes from building a toolchain on 2013-03-29.
+It compiles the code successfully and lives in /opt/cortex-m3.
+The flags are from logic, Austin's gcc, and
+  <http://www.coactionos.com/getting-started/43-building-and-installing-a-cortex-m3-compiler-on-ubuntu.html>
+  (for some of the newlib flags).
+This has been uploaded to our package repository for wheezy as arm-eabi-gcc.
+
+binutils
+	../binutils-2.23.2/configure --prefix=/opt/cortex-m3 --target=arm-eabi
+	make -j6
+	make install
+gcc
+	Symlinked in gmp-4.3.2, mpc-0.8.1, and mpfr-2.4.2 first.
+	../gcc-4.5.4/configure --target=arm-eabi --prefix=/opt/cortex-m3 --enable-interwork --enable-multilib --enable-languages=c,c++ --with-newlib --with-headers --disable-shared --with-gnu-as --with-gnu-ld --with-cpu-cortex-m3 --disable-shared --with-float=soft --with-cpu=cortex-m3 --with-tune=cortex-m3 --disable-libmudflap --disable-libgomp --with-mode=thumb
+	make -j6 all-gcc
+	sudo make install-gcc
+newlib
+	../newlib-1.20.0/configure --target=arm-eabi --prefix=/opt/cortex-m3 --enable-interwork --enable-multilib --enable-languages=c,c++ --with-headers --disable-shared --with-gnu-as --with-gnu-ld --with-cpu-cortex-m3 --disable-shared --with-float=soft --with-cpu=cortex-m3 --with-tune=cortex-m3 --disable-libmudflap --disable-libgomp --with-mode=thumb --disable-werror --disable-newlib-supplied-syscalls --disable-nls --enable-target-optspace --disable-libssp --enable-newlib-reent-small --enable-newlib-multithread --disable-libgloss
+	make CFLAGS_FOR_TARGET="-D__IEEE_BIG_ENDIAN -D__IEEE_BYTES_LITTLE_ENDIAN -D__BUFSIZ__=128"
+	sudo make install
+gcc
+	make -j6
+	sudo make install

diff --git a/bbb_cape/src/cape/uart.c b/bbb_cape/src/cape/uart.c
new file mode 100644
index 0000000..63620ab
--- /dev/null
+++ b/bbb_cape/src/cape/uart.c

@@ -0,0 +1,66 @@
+#include "cape/uart.h"
+#include "cape/uart_common_private.h"
+
+#include "cape/util.h"
+#include "cape/uart_common.h"
+
+// TODO(brians): Add error checking.
+
+static void default_callback(int bytes) {}
+
+void uart_transmit_callback(int bytes_transmitted) ALIAS_WEAK(default_callback);
+void uart_receive_callback(int bytes_received) ALIAS_WEAK(default_callback);
+
+static int transmit_bytes, receive_bytes;
+// These actually contain 1 less than the indicated number to make the common
+// path through the ISR faster.
+static int transmitted_bytes, received_bytes;
+static uint8_t *transmit_data, *receive_data;
+
+// Enable the transmitter and interrupt when we can write.
+static const uint32_t kTransmitBits = USART_CR1_TE | USART_CR1_TXEIE;
+// Enable the receive and interrupt when there's data to read.
+static const uint32_t kReceiveBits = USART_CR1_RE | USART_CR1_RXNEIE;
+
+void USART1_IRQHandler(void) {
+  uint32_t status = UART->SR;
+  if (status & USART_SR_TXE) {
+    if ((transmitted_bytes + 1) < transmit_bytes) {
+      UART->DR = transmit_data[++transmitted_bytes];
+    } else {
+      // Get another interrupt when it's done writing that last byte.
+      UART->CR1 = (UART->CR1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;
+    }
+  } else if (status & USART_SR_RXNE) {
+    receive_data[++received_bytes] = UART->DR;
+    if ((received_bytes + 1) >= receive_bytes) {
+      UART->CR1 &= ~kReceiveBits;
+      uart_receive_callback(receive_bytes);
+    }
+  } else if (status & USART_SR_TC) {
+      UART->CR1 &= ~(USART_CR1_TCIE | USART_CR1_TE);
+      uart_transmit_callback(transmit_bytes);
+  }
+}
+
+void uart_configure(void) {
+  NVIC_SetPriority(USART1_IRQn, 3);
+  NVIC_EnableIRQ(USART1_IRQn);
+}
+
+void uart_transmit(int bytes, uint8_t *data) {
+  transmit_bytes = bytes;
+  transmitted_bytes = 0;
+  transmit_data = data;
+  compiler_memory_barrier();
+  UART->CR1 |= kTransmitBits;
+  UART->DR = data[0];
+}
+
+void uart_receive(int bytes, uint8_t *data) {
+  receive_bytes = bytes;
+  received_bytes = -1;
+  receive_data = data;
+  compiler_memory_barrier();
+  UART->CR1 |= kReceiveBits;
+}

diff --git a/bbb_cape/src/cape/uart.h b/bbb_cape/src/cape/uart.h
new file mode 100644
index 0000000..fd43c99
--- /dev/null
+++ b/bbb_cape/src/cape/uart.h

@@ -0,0 +1,22 @@
+#ifndef CAPE_UART_H_
+#define CAPE_UART_H_
+
+#include <stdint.h>
+
+// This file deals with USART1. It sends bytes from a buffer or receives bytes
+// into a buffer and then calls a callback function.
+
+// uart_common_configure must be called before this.
+void uart_configure(void);
+
+// Callbacks to be implemented by the user.
+// Implemented as weak symbols that do nothing by default.
+// The argument is the number of bytes transmitted or received. It will be less
+// than the requested number if there was an error.
+void uart_transmit_callback(int bytes_transmitted);
+void uart_receive_callback(int bytes_received);
+
+void uart_transmit(int bytes, uint8_t *data);
+void uart_receive(int bytes, uint8_t *data);
+
+#endif  // CAPE_UART_H_

diff --git a/bbb_cape/src/cape/uart_byte.c b/bbb_cape/src/cape/uart_byte.c
new file mode 100644
index 0000000..6bafdb6
--- /dev/null
+++ b/bbb_cape/src/cape/uart_byte.c

@@ -0,0 +1,34 @@
+#include "cape/uart_byte.h"
+#include "cape/uart_common_private.h"
+
+#include <STM32F2XX.h>
+
+#define TIMEOUT_TIM TIM7
+#define RCC_APB1ENR_TIMEOUT_TIMEN RCC_APB1ENR_TIM7EN
+
+void uart_byte_configure(void) {
+  RCC->APB1ENR |= RCC_APB1ENR_TIMEOUT_TIMEN;
+
+  TIMEOUT_TIM->CR1 = TIM_CR1_UDIS;
+}
+
+int uart_byte_receive(uint16_t timeout_count, uint16_t timeout_divider) {
+  TIMEOUT_TIM->PSC = timeout_divider;
+  TIMEOUT_TIM->EGR = TIM_EGR_UG;
+  TIMEOUT_TIM->CR1 |= TIM_CR1_CEN;
+
+  while ((UART->SR & USART_SR_RXNE) == 0) {
+    if (TIMEOUT_TIM->CNT >= timeout_count) {
+      TIMEOUT_TIM->CR1 &= ~TIM_CR1_CEN;
+      return -1;
+    }
+  }
+
+  TIMEOUT_TIM->CR1 &= ~TIM_CR1_CEN;
+  return UART->DR;
+}
+
+void uart_byte_send(uint8_t value) {
+  while ((UART->SR & USART_SR_TXE) == 0) {}
+  UART->DR = value;
+}

diff --git a/bbb_cape/src/cape/uart_byte.h b/bbb_cape/src/cape/uart_byte.h
new file mode 100644
index 0000000..7a82e76
--- /dev/null
+++ b/bbb_cape/src/cape/uart_byte.h

@@ -0,0 +1,17 @@
+#ifndef CAPE_UART_BYTE_H_
+#define CAPE_UART_BYTE_H_
+
+#include <stdint.h>
+
+// uart_common_configure must be called before this.
+void uart_byte_configure(void);
+
+// Spins until 1 byte is received or some amount of time. The timeout is
+// timeout_count*(timeout_divider+1)/30MHz.
+// The result is <0 for timeout or the received byte.
+int uart_byte_receive(uint16_t timeout_count, uint16_t timeout_divider);
+
+// Spins until 1 byte can be written out.
+void uart_byte_send(uint8_t value);
+
+#endif  // CAPE_UART_BYTE_H_

diff --git a/bbb_cape/src/cape/uart_common.c b/bbb_cape/src/cape/uart_common.c
new file mode 100644
index 0000000..783c154
--- /dev/null
+++ b/bbb_cape/src/cape/uart_common.c

@@ -0,0 +1,22 @@
+#include "cape/uart_common.h"
+#include "cape/uart_common_private.h"
+
+#include "cape/util.h"
+
+#define FPCLK 60000000
+
+// The UART is on PA9 and PA10.
+void uart_common_configure(int baud) {
+  gpio_setup_alt(GPIOA, 9, 7);
+  gpio_setup_alt(GPIOA, 10, 7);
+  GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR9;  // we want to go FAST!
+  RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
+
+  // baud = 60MHz / (8 * (2 - OVER8) * (mantissa / fraction))
+  int fraction = 8;  // the biggest it can be with OVER8=0
+  int mantissa = FPCLK * (16 /* 8 * (2 - OVER8) */ / fraction) / baud;
+  UART->BRR = (mantissa << 4) | fraction;
+  UART->CR1 = USART_CR1_UE /* enable it */ |
+      USART_CR1_M /* 9th bit for the parity */ |
+      USART_CR1_PCE /* enable parity (even by default) */;
+}

diff --git a/bbb_cape/src/cape/uart_common.h b/bbb_cape/src/cape/uart_common.h
new file mode 100644
index 0000000..bb98a07
--- /dev/null
+++ b/bbb_cape/src/cape/uart_common.h

@@ -0,0 +1,11 @@
+#ifndef CAPE_UART_COMMON_H_
+#define CAPE_UART_COMMON_H_
+
+// Configures it for baud, 1 start bit, 1 stop bit, and 1 even parity bit.
+// baud must be between 57KHz and 3.75MHz. It must be something that the USART can
+// handle exactly (see
+// <http://www.st.com/web/en/resource/technical/document/reference_manual/CD00225773.pdf#page=633>
+// or so for choices (fPCLK = 60MHz, OVER8 = 0 for now)).
+void uart_common_configure(int baud);
+
+#endif  // CAPE_UART_COMMON_H_

diff --git a/bbb_cape/src/cape/uart_common_private.h b/bbb_cape/src/cape/uart_common_private.h
new file mode 100644
index 0000000..3836b29
--- /dev/null
+++ b/bbb_cape/src/cape/uart_common_private.h

@@ -0,0 +1,8 @@
+#ifndef CAPE_UART_COMMON_PRIVATE_H_
+#define CAPE_UART_COMMON_PRIVATE_H_
+
+#include <STM32F2XX.h>
+
+#define UART USART1
+
+#endif  // CAPE_UART_COMMON_PRIVATE_H_

diff --git a/bbb_cape/src/cape/uart_dma.c b/bbb_cape/src/cape/uart_dma.c
new file mode 100644
index 0000000..f5c1967
--- /dev/null
+++ b/bbb_cape/src/cape/uart_dma.c

@@ -0,0 +1,68 @@
+#include "cape/uart_dma.h"
+#include "cape/uart_common_private.h"
+
+#include "cape/util.h"
+#include "cape/uart_common.h"
+
+#define DMA DMA1
+#define DMA_STREAM_NUMBER 7
+#define DMA_Stream DMA1_Stream7
+#define DMA_SR DMA1->HISR
+#define DMA_FCR DMA1->HIFCR
+#define DMA_SR_SHIFT 3
+#define DMA_Stream_IRQHandler DMA1_Stream7_IRQHandler
+#define DMA_Stream_IRQn DMA1_Stream7_IRQn
+#define RCC_AHB1ENR_DMAEN RCC_AHB1ENR_DMA1EN
+
+#define DMA_SR_BIT(bit) (1 << (bit + 6 * DMA_SR_SHIFT))
+
+void uart_dma_callback(uint8_t *new_buffer) __attribute__((weak));
+void uart_dma_callback(uint8_t *new_buffer) {}
+
+static uint8_t *volatile buffer1, *volatile buffer2;
+
+void DMA_Stream_IRQHandler(void) {
+  uint32_t status = DMA_SR;
+  if (status & DMA_SR_BIT(5)) {  // transfer completed
+    DMA_FCR = DMA_SR_BIT(5);
+    uart_dma_callback(((DMA_Stream->CR & DMA_SxCR_CT) == 0) ? buffer2
+                                                            : buffer1);
+  } else if (status & DMA_SR_BIT(3)) {  // transfer error
+    DMA_FCR = DMA_SR_BIT(3);
+    // Somebody probably wrote to the wrong buffer, which disables the DMA, so
+    // we now need to re-enable it.
+    // If we're fighting somebody else writing stuff, we'll do this a bunch of
+    // times, but oh well.
+    DMA_Stream->CR |= DMA_SxCR_EN;
+  }
+}
+
+void uart_dma_configure(int bytes, uint8_t *buffer1_in, uint8_t *buffer2_in) {
+  buffer1 = buffer1_in;
+  buffer2 = buffer2_in;
+  uart_dma_callback(buffer1);
+
+  RCC->AHB1ENR |= RCC_AHB1ENR_DMAEN;
+  DMA_Stream->PAR = (uint32_t)&UART->DR;
+  DMA_Stream->M0AR = (uint32_t)buffer1;
+  DMA_Stream->M1AR = (uint32_t)buffer2;
+  // This is measured in chunks of PSIZE bytes, not MSIZE.
+  DMA_Stream->NDTR = bytes;
+  DMA_FCR = 0xF << DMA_SR_SHIFT;
+  DMA_Stream->CR = DMA_STREAM_NUMBER << 25 |
+      DMA_SxCR_DBM /* enable double buffer mode */ |
+      2 << 16 /* priority */ |
+      2 << 13 /* memory data size = 32 bits */ |
+      0 << 11 /* peripherial data size = 8 bits */ |
+      DMA_SxCR_MINC /* increment memory address */ |
+      1 << 6 /* memory to peripherial */ |
+      DMA_SxCR_TCIE | DMA_SxCR_TEIE;
+  DMA_Stream->FCR =
+      DMA_SxFCR_DMDIS /* disable direct mode (enable the FIFO) */ |
+      1 /* 1/2 full threshold */;
+  DMA_Stream->CR |= DMA_SxCR_EN;  // enable it
+  NVIC_SetPriority(DMA_Stream_IRQn, 8);
+  NVIC_EnableIRQ(DMA_Stream_IRQn);
+
+  uart_dma_callback(buffer2);
+}

diff --git a/bbb_cape/src/cape/uart_dma.h b/bbb_cape/src/cape/uart_dma.h
new file mode 100644
index 0000000..cc68eed
--- /dev/null
+++ b/bbb_cape/src/cape/uart_dma.h

@@ -0,0 +1,20 @@
+#ifndef CAPE_UART_DMA_H_
+#define CAPE_UART_DMA_H_
+
+#include <stdint.h>
+
+// This file deals with USART1 over DMA. It sets the DMA stream to double-buffer
+// mode and calls a function when it's time to fill a new buffer. It only
+// supports sending.
+
+// Callback to be implemented by the user.
+// Implemented as a weak symbol that does nothing by default.
+// new_buffer is the buffer that should be filled out to be written next.
+void uart_dma_callback(uint8_t *new_buffer);
+
+// uart_common_configure must be called before this.
+// bytes is the size off buffer1 and buffer2.
+// Calls uart_dma_callback twice (for each buffer) to get started.
+void uart_dma_configure(int bytes, uint8_t *buffer1, uint8_t *buffer2);
+
+#endif  // CAPE_UART_DMA_H_

diff --git a/bbb_cape/src/cape/util.h b/bbb_cape/src/cape/util.h
new file mode 100644
index 0000000..02e72fb
--- /dev/null
+++ b/bbb_cape/src/cape/util.h

@@ -0,0 +1,60 @@
+#ifndef CAPE_UTIL_H_
+#define CAPE_UTIL_H_
+
+#include <STM32F2XX.h>
+
+#define ALIAS_WEAK(f) __attribute__ ((weak, alias (#f)))
+
+// MSG has to be separated_with_spaces.
+#define STATIC_ASSERT(COND,MSG) typedef char static_assertion_##MSG[(!!(COND))*2-1]
+
+// Prevents the compiler from reordering memory operations around this.
+static inline void compiler_memory_barrier(void) {
+  __asm__ __volatile__("" ::: "memory");
+}
+
+// Count leading zeros.
+// Returns 0 if bit 31 is set etc.
+__attribute__((always_inline)) static __INLINE uint32_t __clz(uint32_t value) {
+  uint32_t result;
+  __asm__("clz %0, %1" : "=r" (result) : "r" (value));
+  return result;
+}
+
+// Sets number_of_bits (shifted left shift number of slots) to value in
+// variable.
+// This means that the total shift is number_bits*shift.
+#define SET_BITS(variable, number_bits, value, shift) do { \
+  variable = (((variable) & \
+               ~(((1 << (number_bits)) - 1) << (shift * (number_bits)))) | \
+              ((value) << (shift * (number_bits)))); \
+} while (0);
+
+// A convenient way to set up a GPIO pin for some alternate function without
+// missing part or messing up which bits need setting to what.
+// pin is the 0-indexed pin number.
+// afr is 0-0xF for the various alternate functions.
+static inline void gpio_setup_alt(GPIO_TypeDef *port, int pin, int afr) {
+  SET_BITS(port->MODER, 2, 2 /* alternate function */, pin);
+  if (pin < 8) {
+    SET_BITS(port->AFR[0], 4, afr, pin);
+  } else {
+    SET_BITS(port->AFR[1], 4, afr, (pin - 8));
+  }
+}
+
+// A convenient way to set up a GPIO pin for output (push-pull) without missing
+// part or messing up which bits need setting to what.
+// speed is 0 (slow) to 3 (fast)
+static inline void gpio_setup_out(GPIO_TypeDef *port, int pin, int speed) {
+  SET_BITS(port->MODER, 2, 1 /* output */, pin);
+  SET_BITS(port->OSPEEDR, 2, speed, pin);
+}
+
+// exti is which EXTI line to set
+// port is 0 for A, 1 for B, etc
+static inline void EXTI_set(int exti, int port) {
+  SET_BITS(SYSCFG->EXTICR[exti / 4], 4, port, exti % 4);
+}
+
+#endif  // CAPE_UTIL_H_

diff --git a/frc971/input/gyro_sensor_receiver.cc b/frc971/input/gyro_sensor_receiver.cc
index ffe538d..1e1ccc4 100644
--- a/frc971/input/gyro_sensor_receiver.cc
+++ b/frc971/input/gyro_sensor_receiver.cc

@@ -88,12 +88,18 @@
   GyroSensorReceiver() : USBReceiver(2) {}
 
   virtual void PacketReceived(const ::aos::time::Time &/*timestamp*/) override {
-    if (data()->bad_gyro) {
+    if (data()->uninitialized_gyro) {
+      LOG(DEBUG, "uninitialized gyro\n");
+      bad_gyro_ = true;
+    } else if (data()->zeroing_gyro) {
+      LOG(DEBUG, "zeroing gyro\n");
+      bad_gyro_ = true;
+    } else if (data()->bad_gyro) {
       LOG(ERROR, "bad gyro\n");
       bad_gyro_ = true;
       gyro.MakeWithBuilder().angle(0).Send();
     } else if (data()->old_gyro_reading) {
-      LOG(WARNING, "old/bad/uninitialized gyro reading\n");
+      LOG(WARNING, "old/bad gyro reading\n");
       bad_gyro_ = true;
     } else {
       bad_gyro_ = false;