commit 6de9b4904a82153379e71f16adc817bf863efb3f
author Ben Fredrickson <ben.fred12345@gmail.com> Sun Feb 23 06:05:19 2014 +0000
committer Ben Fredrickson <ben.fred12345@gmail.com> Sun Feb 23 06:05:19 2014 +0000
tree c37542d3d55b424badb91de50f2263efa6496b90
parent 2f76ddfbdba4241a56a0f7762a7d9da06a45b2de

switched to a capped absolute U controller to handle invalid voltage requests cleanly

frc971/control_loops/claw/claw.cc

diff --git a/frc971/control_loops/claw/claw.cc b/frc971/control_loops/claw/claw.cc
index e1bf8a5..5877226 100755
--- a/frc971/control_loops/claw/claw.cc
+++ b/frc971/control_loops/claw/claw.cc
@@ -685,8 +685,11 @@
   if (output) {
     if (goal) {
       //setup the intake
-      output->intake_voltage = goal->intake;
+      output->intake_voltage = (goal->intake > 12.0) ? 12 :
+	  	  (goal->intake < -12.0) ? -12.0 : goal->intake;
       output->tusk_voltage = goal->centering;
+      output->tusk_voltage = (goal->centering > 12.0) ? 12 :
+	  	  (goal->centering < -12.0) ? -12.0 : goal->centering;
     }
     output->top_claw_voltage = claw_.U(1, 0) + claw_.U(0, 0);
     output->bottom_claw_voltage =  claw_.U(0, 0);