tweaked the zip tie hole etc to make sierra circuits happy
diff --git a/bbb_cape/schematic/cape.pcb b/bbb_cape/schematic/cape.pcb
index 33b97f5..16258ad 100644
--- a/bbb_cape/schematic/cape.pcb
+++ b/bbb_cape/schematic/cape.pcb
@@ -6,7 +6,7 @@
PCB["971 BBB Cape" 500000 400000]
Grid[500.0 441 0 0]
-Cursor[292941 74000 0.000000]
+Cursor[315941 174500 0.000000]
PolyArea[3100.006200]
Thermal[0.500000]
DRC[800 1000 800 10 1000 500]
@@ -3104,7 +3104,7 @@
Pin[62500 75000 6600 2000 8600 4600 "" "UART4" "edge2"]
Pin[72500 75000 6600 2000 8600 4600 "" "UART5" "edge2"]
Pin[152500 -65000 22000 1800 24000 20000 "bogus_842" "842" "edge2"]
- Pin[-70000 -70000 25000 2000 25000 25000 "bogus_942" "742" "lock,edge2"]
+ Pin[-70000 -70000 26600 2000 28600 24600 "bogus_942" "742" "lock,edge2"]
)
@@ -4367,7 +4367,7 @@
Line[255941 279000 255941 270000 800 1600 "clearline"]
Line[255941 270000 249674 263733 800 1600 "clearline"]
Line[249674 263733 247941 263733 800 1600 "clearline"]
- Text[113799 48171 0 120 "20130117" "clearline"]
+ Text[113799 48171 0 120 "20130120" "clearline"]
Polygon("")
(
[182941 79000] [199941 79000] [199941 97500] [182941 97500]
@@ -6114,7 +6114,7 @@
Line[229818 51925 229818 45012 800 1600 "clearline"]
Polygon("")
(
- [122941 95000] [122941 68500] [92941 68500] [92941 40000] [156941 40000]
+ [122941 95000] [122941 68500] [107941 68500] [107941 40000] [156941 40000]
[156941 57500] [130941 57500] [130941 95000]
)
Polygon("")
@@ -6272,7 +6272,7 @@
Text[408938 260015 0 180 "- + D" "clearline"]
Text[404438 245515 0 135 "- + A B" "clearline"]
Text[190941 157500 0 115 "FRC Team 971 BBB Cape" "clearline"]
- Text[202441 170500 0 115 "20140117 2014-1" "clearline"]
+ Text[202441 170500 0 115 "20140120 2014-2" "clearline"]
Text[317250 348504 1 180 "- + A" "clearline"]
Text[78938 316059 0 135 "0 1 2 3 4 5 6 7" "clearline"]
Text[177441 199500 0 115 "GND" "clearline"]