Squashed 'third_party/pico-sdk/lib/tinyusb/' content from commit 868948f67c
Change-Id: I5d33c2566dd597be9d4b1c30d4b3723c5ef4a265
git-subtree-dir: third_party/pico-sdk/lib/tinyusb
git-subtree-split: 868948f67c90fa7c2553cdcd604b52862cf55720
Signed-off-by: Austin Schuh <austin.linux@gmail.com>
diff --git a/hw/mcu/dialog/README.md b/hw/mcu/dialog/README.md
new file mode 100644
index 0000000..69676f0
--- /dev/null
+++ b/hw/mcu/dialog/README.md
@@ -0,0 +1,9 @@
+# Dialog DA1469x MCU
+
+**Dialog Semiconductors** provides SDKs for DA146x MCU family.
+Most of the files there can't be redistributed.
+Registers definition file `DA1469xAB.h` and some **ARM** originated headers are have licenses that allow
+for redistribution.
+Whole SDK repository can be downloaded from Dialog Semiconductor web page `https://www.dialog.com`
+
+
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt
new file mode 100644
index 0000000..b324eb2
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt
@@ -0,0 +1,27 @@
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h
new file mode 100644
index 0000000..fa2ca5d
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h
@@ -0,0 +1,8657 @@
+/*
+ * Copyright (C) 2019 Dialog Semiconductor. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of Dialog Semiconductor nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @file DA1469xAB.h
+ * @brief CMSIS HeaderFile
+ * @version 1.2
+ * @date 22. April 2019
+ * @note Generated by SVDConv V3.3.25 on Monday, 22.04.2019 11:06:30
+ * from File 'DA1469xAB.xml',
+ */
+
+
+
+/** @addtogroup PLA_BSP_REGISTERS
+ * @{
+ */
+
+
+/** @addtogroup DA1469x
+ * @{
+ */
+
+
+#ifndef DA1469X_H
+#define DA1469X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+/* =========================================================================================================================== */
+/* ================ Interrupt Number Definition ================ */
+/* =========================================================================================================================== */
+
+/**
+ * @brief Interrupt Number Definition
+ */
+
+typedef enum {
+/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ and No Match */
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ related Fault */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+/* ========================================== DA1469x Specific Interrupt Numbers =========================================== */
+ SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
+ DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
+ CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
+ CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
+ CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
+ UART_IRQn = 5, /*!< 5 UART interrupt request. */
+ UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
+ UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
+ I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
+ I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
+ SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
+ SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
+ PCM_IRQn = 12, /*!< 12 PCM interrupt request. */
+ SRC_IN_IRQn = 13, /*!< 13 SRC input interrupt request. */
+ SRC_OUT_IRQn = 14, /*!< 14 SRC output interrupt request. */
+ USB_IRQn = 15, /*!< 15 USB interrupt request. */
+ TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
+ TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
+ RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
+ KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
+ PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
+ VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
+ MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
+ MOTOR_CONTROLLER_IRQn = 23, /*!< 23 MOTOR and mailbox interrupt request. */
+ TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
+ DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
+ XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
+ GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
+ SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
+ CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
+ CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
+ RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
+ LCD_CONTROLLER_IRQn = 32, /*!< 32 Parallel LCD Controller interrupt request. */
+ PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
+ TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
+ TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
+ LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
+ RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
+ GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
+ GPIO_P1_IRQn = 39 /*!< 39 GPIO port 1 toggle interrupt request. */
+} IRQn_Type;
+
+
+
+/* =========================================================================================================================== */
+/* ================ Processor and Core Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */
+#define __CM33_REV 0x0000U /*!< CM33 Core Revision */
+#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+#define __MPU_PRESENT 1 /*!< MPU present */
+#define __FPU_PRESENT 1 /*!< FPU present */
+#define __FPU_DP 0 /*!< Double Precision FPU */
+#define __DSP_PRESENT 1 /*!< DSP extension present */
+#define __SAU_REGION_PRESENT 0 /*!< SAU present */
+
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
+#include "system_DA1469x.h" /*!< DA1469x System */
+
+#ifndef __IM /*!< Fallback for older CMSIS versions */
+ #define __IM __I
+#endif
+#ifndef __OM /*!< Fallback for older CMSIS versions */
+ #define __OM __O
+#endif
+#ifndef __IOM /*!< Fallback for older CMSIS versions */
+ #define __IOM __IO
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ AES_HASH ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief AES_HASH registers (AES_HASH)
+ */
+
+typedef struct { /*!< (@ 0x30040000) AES_HASH Structure */
+ __IOM uint32_t CRYPTO_CTRL_REG; /*!< (@ 0x00000000) Crypto Control register */
+ __IOM uint32_t CRYPTO_START_REG; /*!< (@ 0x00000004) Crypto Start calculation */
+ __IOM uint32_t CRYPTO_FETCH_ADDR_REG; /*!< (@ 0x00000008) Crypto DMA fetch register */
+ __IOM uint32_t CRYPTO_LEN_REG; /*!< (@ 0x0000000C) Crypto Length of the input block in bytes */
+ __IOM uint32_t CRYPTO_DEST_ADDR_REG; /*!< (@ 0x00000010) Crypto DMA destination memory */
+ __IOM uint32_t CRYPTO_STATUS_REG; /*!< (@ 0x00000014) Crypto Status register */
+ __IOM uint32_t CRYPTO_CLRIRQ_REG; /*!< (@ 0x00000018) Crypto Clear interrupt request */
+ __IOM uint32_t CRYPTO_MREG0_REG; /*!< (@ 0x0000001C) Crypto Mode depended register 0 */
+ __IOM uint32_t CRYPTO_MREG1_REG; /*!< (@ 0x00000020) Crypto Mode depended register 1 */
+ __IOM uint32_t CRYPTO_MREG2_REG; /*!< (@ 0x00000024) Crypto Mode depended register 2 */
+ __IOM uint32_t CRYPTO_MREG3_REG; /*!< (@ 0x00000028) Crypto Mode depended register 3 */
+ __IM uint32_t RESERVED[53];
+ __IOM uint32_t CRYPTO_KEYS_START; /*!< (@ 0x00000100) Crypto First position of the AES keys storage
+ memory */
+} AES_HASH_Type; /*!< Size = 260 (0x104) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ANAMISC_BIF ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief ANAMISC_BIF registers (ANAMISC_BIF)
+ */
+
+typedef struct { /*!< (@ 0x50030B00) ANAMISC_BIF Structure */
+ __IM uint32_t RESERVED[4];
+ __IOM uint32_t CLK_REF_SEL_REG; /*!< (@ 0x00000010) Select clock for oscillator calibration */
+ __IOM uint32_t CLK_REF_CNT_REG; /*!< (@ 0x00000014) Count value for oscillator calibration */
+ __IOM uint32_t CLK_REF_VAL_REG; /*!< (@ 0x00000018) DIVN reference cycles, lower 16 bits */
+} ANAMISC_BIF_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ APU ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief APU registers (APU)
+ */
+
+typedef struct { /*!< (@ 0x50030600) APU Structure */
+ __IOM uint32_t SRC1_CTRL_REG; /*!< (@ 0x00000000) SRC1 control register */
+ __IOM uint32_t SRC1_IN_FS_REG; /*!< (@ 0x00000004) SRC1 Sample input rate */
+ __IOM uint32_t SRC1_OUT_FS_REG; /*!< (@ 0x00000008) SRC1 Sample output rate */
+ __IOM uint32_t SRC1_IN1_REG; /*!< (@ 0x0000000C) SRC1 data in 1 */
+ __IOM uint32_t SRC1_IN2_REG; /*!< (@ 0x00000010) SRC1 data in 2 */
+ __IOM uint32_t SRC1_OUT1_REG; /*!< (@ 0x00000014) SRC1 data out 1 */
+ __IOM uint32_t SRC1_OUT2_REG; /*!< (@ 0x00000018) SRC1 data out 2 */
+ __IOM uint32_t APU_MUX_REG; /*!< (@ 0x0000001C) APU mux register */
+ __IOM uint32_t COEF10_SET1_REG; /*!< (@ 0x00000020) SRC coefficient 1,0 set 1 */
+ __IOM uint32_t COEF32_SET1_REG; /*!< (@ 0x00000024) SRC coefficient 3,2 set 1 */
+ __IOM uint32_t COEF54_SET1_REG; /*!< (@ 0x00000028) SRC coefficient 5,4 set 1 */
+ __IOM uint32_t COEF76_SET1_REG; /*!< (@ 0x0000002C) SRC coefficient 7,6 set 1 */
+ __IOM uint32_t COEF98_SET1_REG; /*!< (@ 0x00000030) SRC coefficient 9,8 set 1 */
+ __IOM uint32_t COEF0A_SET1_REG; /*!< (@ 0x00000034) SRC coefficient 10 set 1 */
+ __IM uint32_t RESERVED[50];
+ __IOM uint32_t PCM1_CTRL_REG; /*!< (@ 0x00000100) PCM1 Control register */
+ __IOM uint32_t PCM1_IN1_REG; /*!< (@ 0x00000104) PCM1 data in 1 */
+ __IOM uint32_t PCM1_IN2_REG; /*!< (@ 0x00000108) PCM1 data in 2 */
+ __IOM uint32_t PCM1_OUT1_REG; /*!< (@ 0x0000010C) PCM1 data out 1 */
+ __IOM uint32_t PCM1_OUT2_REG; /*!< (@ 0x00000110) PCM1 data out 2 */
+} APU_Type; /*!< Size = 276 (0x114) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CACHE ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CACHE registers (CACHE)
+ */
+
+typedef struct { /*!< (@ 0x100C0000) CACHE Structure */
+ __IOM uint32_t CACHE_CTRL1_REG; /*!< (@ 0x00000000) Cache control register 1 */
+ __IOM uint32_t CACHE_LNSIZECFG_REG; /*!< (@ 0x00000004) Cache line size configuration register */
+ __IOM uint32_t CACHE_ASSOCCFG_REG; /*!< (@ 0x00000008) Cache associativity configuration register */
+ __IM uint32_t RESERVED[5];
+ __IOM uint32_t CACHE_CTRL2_REG; /*!< (@ 0x00000020) Cache control register 2 */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t CACHE_MRM_HITS_REG; /*!< (@ 0x00000028) Cache MRM (Miss Rate Monitor) HITS register */
+ __IOM uint32_t CACHE_MRM_MISSES_REG; /*!< (@ 0x0000002C) Cache MRM (Miss Rate Monitor) MISSES register */
+ __IOM uint32_t CACHE_MRM_CTRL_REG; /*!< (@ 0x00000030) Cache MRM (Miss Rate Monitor) CONTROL register */
+ __IOM uint32_t CACHE_MRM_TINT_REG; /*!< (@ 0x00000034) Cache MRM (Miss Rate Monitor) TIME INTERVAL register */
+ __IOM uint32_t CACHE_MRM_MISSES_THRES_REG; /*!< (@ 0x00000038) Cache MRM (Miss Rate Monitor) THRESHOLD register */
+ __IOM uint32_t CACHE_MRM_HITS_THRES_REG; /*!< (@ 0x0000003C) Cache MRM (Miss Rate Monitor) HITS THRESHOLD
+ register */
+ __IOM uint32_t CACHE_FLASH_REG; /*!< (@ 0x00000040) Cache Flash program size and base address register */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t SWD_RESET_REG; /*!< (@ 0x00000050) SWD HW reset control register */
+} CACHE_Type; /*!< Size = 84 (0x54) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CHARGER ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CHARGER registers (CHARGER)
+ */
+
+typedef struct { /*!< (@ 0x50040400) CHARGER Structure */
+ __IOM uint32_t CHARGER_CTRL_REG; /*!< (@ 0x00000000) Charger main control register */
+ __IOM uint32_t CHARGER_TEST_CTRL_REG; /*!< (@ 0x00000004) Charger test control register */
+ __IOM uint32_t CHARGER_STATUS_REG; /*!< (@ 0x00000008) Charger main status register */
+ __IOM uint32_t CHARGER_VOLTAGE_PARAM_REG; /*!< (@ 0x0000000C) Charger voltage settings register */
+ __IOM uint32_t CHARGER_CURRENT_PARAM_REG; /*!< (@ 0x00000010) Charger current settings register */
+ __IOM uint32_t CHARGER_TEMPSET_PARAM_REG; /*!< (@ 0x00000014) Charger battery temperature settings register */
+ __IOM uint32_t CHARGER_PRE_CHARGE_TIMER_REG; /*!< (@ 0x00000018) Maximum pre-charge time limit register */
+ __IOM uint32_t CHARGER_CC_CHARGE_TIMER_REG; /*!< (@ 0x0000001C) Maximum CC-charge time limit register */
+ __IOM uint32_t CHARGER_CV_CHARGE_TIMER_REG; /*!< (@ 0x00000020) Maximum CV-charge time limit register */
+ __IOM uint32_t CHARGER_TOTAL_CHARGE_TIMER_REG;/*!< (@ 0x00000024) Maximum total charge time limit register */
+ __IOM uint32_t CHARGER_JEITA_V_CHARGE_REG; /*!< (@ 0x00000028) JEITA-compliant Charge voltage settings register */
+ __IOM uint32_t CHARGER_JEITA_V_PRECHARGE_REG;/*!< (@ 0x0000002C) JEITA-compliant Pre-Charge voltage settings register */
+ __IOM uint32_t CHARGER_JEITA_V_REPLENISH_REG;/*!< (@ 0x00000030) JEITA-compliant Replenish settings register */
+ __IOM uint32_t CHARGER_JEITA_V_OVP_REG; /*!< (@ 0x00000034) JEITA-compliant OVP settings register */
+ __IOM uint32_t CHARGER_JEITA_CURRENT_REG; /*!< (@ 0x00000038) JEITA-compliant current settings register */
+ __IOM uint32_t CHARGER_VBAT_COMP_TIMER_REG; /*!< (@ 0x0000003C) Main Vbat comparator timer register */
+ __IOM uint32_t CHARGER_VOVP_COMP_TIMER_REG; /*!< (@ 0x00000040) Vbat OVP comparator timer register */
+ __IOM uint32_t CHARGER_TDIE_COMP_TIMER_REG; /*!< (@ 0x00000044) Die temperature comparator timer register */
+ __IOM uint32_t CHARGER_TBAT_MON_TIMER_REG; /*!< (@ 0x00000048) Battery temperature monitor interval timer */
+ __IOM uint32_t CHARGER_TBAT_COMP_TIMER_REG; /*!< (@ 0x0000004C) Battery temperature (main) comparator timer */
+ __IOM uint32_t CHARGER_THOT_COMP_TIMER_REG; /*!< (@ 0x00000050) Battery temperature comparator timer for 'Hot'
+ zone */
+ __IOM uint32_t CHARGER_PWR_UP_TIMER_REG; /*!< (@ 0x00000054) Charger power-up (settling) timer */
+ __IOM uint32_t CHARGER_STATE_IRQ_MASK_REG; /*!< (@ 0x00000058) Mask register of Charger FSM IRQs */
+ __IOM uint32_t CHARGER_ERROR_IRQ_MASK_REG; /*!< (@ 0x0000005C) Mask register of Charger Error IRQs */
+ __IOM uint32_t CHARGER_STATE_IRQ_STATUS_REG; /*!< (@ 0x00000060) Status register of Charger FSM IRQs */
+ __IOM uint32_t CHARGER_ERROR_IRQ_STATUS_REG; /*!< (@ 0x00000064) Status register of Charger Error IRQs */
+ __IOM uint32_t CHARGER_STATE_IRQ_CLR_REG; /*!< (@ 0x00000068) Interrupt clear register of Charger FSM IRQs */
+ __IOM uint32_t CHARGER_ERROR_IRQ_CLR_REG; /*!< (@ 0x0000006C) Interrupt clear register of Charger Error IRQs */
+} CHARGER_Type; /*!< Size = 112 (0x70) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CHIP_VERSION ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CHIP_VERSION registers (CHIP_VERSION)
+ */
+
+typedef struct { /*!< (@ 0x50040200) CHIP_VERSION Structure */
+ __IOM uint32_t CHIP_ID1_REG; /*!< (@ 0x00000000) Chip identification register 1. */
+ __IOM uint32_t CHIP_ID2_REG; /*!< (@ 0x00000004) Chip identification register 2. */
+ __IOM uint32_t CHIP_ID3_REG; /*!< (@ 0x00000008) Chip identification register 3. */
+ __IOM uint32_t CHIP_ID4_REG; /*!< (@ 0x0000000C) Chip identification register 4. */
+ __IOM uint32_t CHIP_SWC_REG; /*!< (@ 0x00000010) Software compatibility register. */
+ __IOM uint32_t CHIP_REVISION_REG; /*!< (@ 0x00000014) Chip revision register. */
+ __IM uint32_t RESERVED[56];
+ __IOM uint32_t CHIP_TEST1_REG; /*!< (@ 0x000000F8) Chip test register 1. */
+ __IOM uint32_t CHIP_TEST2_REG; /*!< (@ 0x000000FC) Chip test register 2. */
+} CHIP_VERSION_Type; /*!< Size = 256 (0x100) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CRG_COM ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CRG_COM registers (CRG_COM)
+ */
+
+typedef struct { /*!< (@ 0x50020900) CRG_COM Structure */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t CLK_COM_REG; /*!< (@ 0x00000004) Peripheral divider register */
+ __IOM uint32_t SET_CLK_COM_REG; /*!< (@ 0x00000008) Peripheral divider register SET register. Reads
+ back 0x0000 */
+ __IOM uint32_t RESET_CLK_COM_REG; /*!< (@ 0x0000000C) Peripheral divider register RESET register. Reads
+ back 0x0000 */
+} CRG_COM_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CRG_PER ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CRG_PER registers (CRG_PER)
+ */
+
+typedef struct { /*!< (@ 0x50030C00) CRG_PER Structure */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t CLK_PER_REG; /*!< (@ 0x00000004) Peripheral divider register */
+ __IOM uint32_t SET_CLK_PER_REG; /*!< (@ 0x00000008) Peripheral divider register SET register, reads
+ 0x0000 */
+ __IOM uint32_t RESET_CLK_PER_REG; /*!< (@ 0x0000000C) Peripheral divider register RESET register, reads
+ 0x0000 */
+ __IM uint32_t RESERVED1[12];
+ __IOM uint32_t PCM_DIV_REG; /*!< (@ 0x00000040) PCM divider and enables */
+ __IOM uint32_t PCM_FDIV_REG; /*!< (@ 0x00000044) PCM fractional division register */
+ __IOM uint32_t PDM_DIV_REG; /*!< (@ 0x00000048) PDM divider and enables */
+ __IOM uint32_t SRC_DIV_REG; /*!< (@ 0x0000004C) SRC divider and enables */
+} CRG_PER_Type; /*!< Size = 80 (0x50) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CRG_SYS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CRG_SYS registers (CRG_SYS)
+ */
+
+typedef struct { /*!< (@ 0x50040500) CRG_SYS Structure */
+ __IOM uint32_t CLK_SYS_REG; /*!< (@ 0x00000000) Peripheral divider register */
+ __IOM uint32_t BATCHECK_REG; /*!< (@ 0x00000004) BATCHECK_REG */
+} CRG_SYS_Type; /*!< Size = 8 (0x8) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CRG_TOP ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CRG_TOP registers (CRG_TOP)
+ */
+
+typedef struct { /*!< (@ 0x50000000) CRG_TOP Structure */
+ __IOM uint32_t CLK_AMBA_REG; /*!< (@ 0x00000000) HCLK, PCLK, divider and clock gates */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t CLK_RADIO_REG; /*!< (@ 0x00000010) Radio PLL control register */
+ __IOM uint32_t CLK_CTRL_REG; /*!< (@ 0x00000014) Clock control register */
+ __IOM uint32_t CLK_TMR_REG; /*!< (@ 0x00000018) Clock control for the timers */
+ __IOM uint32_t CLK_SWITCH2XTAL_REG; /*!< (@ 0x0000001C) Switches clock from RC32M to XTAL32M */
+ __IOM uint32_t PMU_CTRL_REG; /*!< (@ 0x00000020) Power Management Unit control register */
+ __IOM uint32_t SYS_CTRL_REG; /*!< (@ 0x00000024) System Control register */
+ __IOM uint32_t SYS_STAT_REG; /*!< (@ 0x00000028) System status register */
+ __IM uint32_t RESERVED1[4];
+ __IOM uint32_t CLK_RC32K_REG; /*!< (@ 0x0000003C) 32 kHz RC oscillator register */
+ __IOM uint32_t CLK_XTAL32K_REG; /*!< (@ 0x00000040) 32 kHz XTAL oscillator register */
+ __IOM uint32_t CLK_RC32M_REG; /*!< (@ 0x00000044) Fast RC control register */
+ __IOM uint32_t CLK_RCX_REG; /*!< (@ 0x00000048) RCX-oscillator control register */
+ __IOM uint32_t CLK_RTCDIV_REG; /*!< (@ 0x0000004C) Divisor for RTC 100Hz clock */
+ __IOM uint32_t BANDGAP_REG; /*!< (@ 0x00000050) bandgap trimming */
+ __IOM uint32_t VBUS_IRQ_MASK_REG; /*!< (@ 0x00000054) IRQ masking */
+ __IOM uint32_t VBUS_IRQ_CLEAR_REG; /*!< (@ 0x00000058) Clear pending IRQ register */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t BOD_CTRL_REG; /*!< (@ 0x00000060) Brown Out Detection control register */
+ __IOM uint32_t BOD_LVL_CTRL0_REG; /*!< (@ 0x00000064) BOD_LVL_CTRL0_REG */
+ __IOM uint32_t BOD_LVL_CTRL1_REG; /*!< (@ 0x00000068) BOD_LVL_CTRL1_REG */
+ __IOM uint32_t BOD_LVL_CTRL2_REG; /*!< (@ 0x0000006C) BOD_LVL_CTRL2_REG */
+ __IOM uint32_t P0_PAD_LATCH_REG; /*!< (@ 0x00000070) Control the state retention of the GPIO ports */
+ __IOM uint32_t P0_SET_PAD_LATCH_REG; /*!< (@ 0x00000074) Control the state retention of the GPIO ports */
+ __IOM uint32_t P0_RESET_PAD_LATCH_REG; /*!< (@ 0x00000078) Control the state retention of the GPIO ports */
+ __IOM uint32_t P1_PAD_LATCH_REG; /*!< (@ 0x0000007C) Control the state retention of the GPIO ports */
+ __IOM uint32_t P1_SET_PAD_LATCH_REG; /*!< (@ 0x00000080) Control the state retention of the GPIO ports */
+ __IOM uint32_t P1_RESET_PAD_LATCH_REG; /*!< (@ 0x00000084) Control the state retention of the GPIO ports */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t BOD_STATUS_REG; /*!< (@ 0x00000090) BOD_STATUS_REG */
+ __IOM uint32_t POR_VBAT_CTRL_REG; /*!< (@ 0x00000094) Controls the POR on VBAT */
+ __IOM uint32_t POR_PIN_REG; /*!< (@ 0x00000098) Selects a GPIO pin for POR generation */
+ __IOM uint32_t POR_TIMER_REG; /*!< (@ 0x0000009C) Time for POR to happen */
+ __IOM uint32_t LDO_VDDD_HIGH_CTRL_REG; /*!< (@ 0x000000A0) LDO control register */
+ __IOM uint32_t BIAS_VREF_SEL_REG; /*!< (@ 0x000000A4) BIAS_VREF_SEL_REG */
+ __IM uint32_t RESERVED4[5];
+ __IOM uint32_t RESET_STAT_REG; /*!< (@ 0x000000BC) Reset status register */
+ __IOM uint32_t RAM_PWR_CTRL_REG; /*!< (@ 0x000000C0) Control power state of System RAMS */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t SECURE_BOOT_REG; /*!< (@ 0x000000CC) Controls secure booting */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t DISCHARGE_RAIL_REG; /*!< (@ 0x000000D4) Immediate rail resetting. There is no LDO/DCDC
+ gating */
+ __IM uint32_t RESERVED7[5];
+ __IOM uint32_t ANA_STATUS_REG; /*!< (@ 0x000000EC) Analog Signals Status Register */
+ __IOM uint32_t POWER_CTRL_REG; /*!< (@ 0x000000F0) Power control register */
+ __IOM uint32_t PMU_SLEEP_REG; /*!< (@ 0x000000F4) Configures the sleep/wakeup strategy */
+ __IOM uint32_t PMU_TRIM_REG; /*!< (@ 0x000000F8) LDO trimming register */
+} CRG_TOP_Type; /*!< Size = 252 (0xfc) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CRG_XTAL ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CRG_XTAL registers (CRG_XTAL)
+ */
+
+typedef struct { /*!< (@ 0x50010000) CRG_XTAL Structure */
+ __IOM uint32_t CLK_FREQ_TRIM_REG; /*!< (@ 0x00000000) Xtal frequency trimming register. */
+ __IM uint32_t RESERVED[3];
+ __IOM uint32_t TRIM_CTRL_REG; /*!< (@ 0x00000010) Control trimming of the XTAL32M */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t XTALRDY_CTRL_REG; /*!< (@ 0x00000018) Control register for XTALRDY IRQ */
+ __IOM uint32_t XTALRDY_STAT_REG; /*!< (@ 0x0000001C) Difference between XTAL_OK and XTALRDY_IRQ in
+ LP clock cycles */
+ __IM uint32_t RESERVED2[4];
+ __IOM uint32_t XTAL32M_CTRL0_REG; /*!< (@ 0x00000030) Control register for XTAL32M */
+ __IOM uint32_t XTAL32M_CTRL1_REG; /*!< (@ 0x00000034) Control register for XTAL32M */
+ __IOM uint32_t XTAL32M_CTRL2_REG; /*!< (@ 0x00000038) Control register for XTAL32M */
+ __IOM uint32_t XTAL32M_CTRL3_REG; /*!< (@ 0x0000003C) Control register for XTAL32M */
+ __IOM uint32_t XTAL32M_CTRL4_REG; /*!< (@ 0x00000040) Control register for XTAL32M */
+ __IM uint32_t RESERVED3[3];
+ __IOM uint32_t XTAL32M_STAT0_REG; /*!< (@ 0x00000050) Status register for XTAL32M */
+ __IOM uint32_t XTAL32M_STAT1_REG; /*!< (@ 0x00000054) Status register for XTAL32M */
+ __IM uint32_t RESERVED4[2];
+ __IOM uint32_t PLL_SYS_CTRL1_REG; /*!< (@ 0x00000060) System PLL control register 1. */
+ __IOM uint32_t PLL_SYS_CTRL2_REG; /*!< (@ 0x00000064) System PLL control register 2. */
+ __IOM uint32_t PLL_SYS_CTRL3_REG; /*!< (@ 0x00000068) System PLL control register 3. */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t PLL_SYS_STATUS_REG; /*!< (@ 0x00000070) System PLL status register. */
+} CRG_XTAL_Type; /*!< Size = 116 (0x74) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DCDC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DCDC registers (DCDC)
+ */
+
+typedef struct { /*!< (@ 0x50000300) DCDC Structure */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t DCDC_CTRL1_REG; /*!< (@ 0x00000004) DCDC First Control Register */
+ __IOM uint32_t DCDC_CTRL2_REG; /*!< (@ 0x00000008) DCDC Second Control Register */
+ __IOM uint32_t DCDC_V14_REG; /*!< (@ 0x0000000C) DCDC V14 Control Register */
+ __IOM uint32_t DCDC_VDD_REG; /*!< (@ 0x00000010) DCDC VDD Control Register */
+ __IOM uint32_t DCDC_V18_REG; /*!< (@ 0x00000014) DCDC V18 Control Register */
+ __IOM uint32_t DCDC_V18P_REG; /*!< (@ 0x00000018) DCDC V18P Control Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t DCDC_STATUS1_REG; /*!< (@ 0x00000020) DCDC First Status Register */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t DCDC_IRQ_STATUS_REG; /*!< (@ 0x00000030) DCDC Interrupt Status Register */
+ __IOM uint32_t DCDC_IRQ_CLEAR_REG; /*!< (@ 0x00000034) DCDC Interrupt Clear Register */
+ __IOM uint32_t DCDC_IRQ_MASK_REG; /*!< (@ 0x00000038) DCDC Interrupt Mask Register */
+} DCDC_Type; /*!< Size = 60 (0x3c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DMA ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DMA registers (DMA)
+ */
+
+typedef struct { /*!< (@ 0x50040800) DMA Structure */
+ __IOM uint32_t DMA0_A_START_REG; /*!< (@ 0x00000000) Start address A of DMA channel 0 */
+ __IOM uint32_t DMA0_B_START_REG; /*!< (@ 0x00000004) Start address B of DMA channel 0 */
+ __IOM uint32_t DMA0_INT_REG; /*!< (@ 0x00000008) DMA receive interrupt register channel 0 */
+ __IOM uint32_t DMA0_LEN_REG; /*!< (@ 0x0000000C) DMA receive length register channel 0 */
+ __IOM uint32_t DMA0_CTRL_REG; /*!< (@ 0x00000010) Control register for the DMA channel 0 */
+ __IOM uint32_t DMA0_IDX_REG; /*!< (@ 0x00000014) Index value of DMA channel 0 */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t DMA1_A_START_REG; /*!< (@ 0x00000020) Start address A of DMA channel 1 */
+ __IOM uint32_t DMA1_B_START_REG; /*!< (@ 0x00000024) Start address B of DMA channel 1 */
+ __IOM uint32_t DMA1_INT_REG; /*!< (@ 0x00000028) DMA receive interrupt register channel 1 */
+ __IOM uint32_t DMA1_LEN_REG; /*!< (@ 0x0000002C) DMA receive length register channel 1 */
+ __IOM uint32_t DMA1_CTRL_REG; /*!< (@ 0x00000030) Control register for the DMA channel 1 */
+ __IOM uint32_t DMA1_IDX_REG; /*!< (@ 0x00000034) Index value of DMA channel 1 */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t DMA2_A_START_REG; /*!< (@ 0x00000040) Start address A of DMA channel 2 */
+ __IOM uint32_t DMA2_B_START_REG; /*!< (@ 0x00000044) Start address B of DMA channel 2 */
+ __IOM uint32_t DMA2_INT_REG; /*!< (@ 0x00000048) DMA receive interrupt register channel 2 */
+ __IOM uint32_t DMA2_LEN_REG; /*!< (@ 0x0000004C) DMA receive length register channel 2 */
+ __IOM uint32_t DMA2_CTRL_REG; /*!< (@ 0x00000050) Control register for the DMA channel 2 */
+ __IOM uint32_t DMA2_IDX_REG; /*!< (@ 0x00000054) Index value of DMA channel 2 */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t DMA3_A_START_REG; /*!< (@ 0x00000060) Start address A of DMA channel 3 */
+ __IOM uint32_t DMA3_B_START_REG; /*!< (@ 0x00000064) Start address B of DMA channel 3 */
+ __IOM uint32_t DMA3_INT_REG; /*!< (@ 0x00000068) DMA receive interrupt register channel 3 */
+ __IOM uint32_t DMA3_LEN_REG; /*!< (@ 0x0000006C) DMA receive length register channel 3 */
+ __IOM uint32_t DMA3_CTRL_REG; /*!< (@ 0x00000070) Control register for the DMA channel 3 */
+ __IOM uint32_t DMA3_IDX_REG; /*!< (@ 0x00000074) Index value of DMA channel 3 */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t DMA4_A_START_REG; /*!< (@ 0x00000080) Start address A of DMA channel 4 */
+ __IOM uint32_t DMA4_B_START_REG; /*!< (@ 0x00000084) Start address B of DMA channel 4 */
+ __IOM uint32_t DMA4_INT_REG; /*!< (@ 0x00000088) DMA receive interrupt register channel 4 */
+ __IOM uint32_t DMA4_LEN_REG; /*!< (@ 0x0000008C) DMA receive length register channel 4 */
+ __IOM uint32_t DMA4_CTRL_REG; /*!< (@ 0x00000090) Control register for the DMA channel 4 */
+ __IOM uint32_t DMA4_IDX_REG; /*!< (@ 0x00000094) Index value of DMA channel 4 */
+ __IM uint32_t RESERVED4[2];
+ __IOM uint32_t DMA5_A_START_REG; /*!< (@ 0x000000A0) Start address A of DMA channel 5 */
+ __IOM uint32_t DMA5_B_START_REG; /*!< (@ 0x000000A4) Start address B of DMA channel 5 */
+ __IOM uint32_t DMA5_INT_REG; /*!< (@ 0x000000A8) DMA receive interrupt register channel 5 */
+ __IOM uint32_t DMA5_LEN_REG; /*!< (@ 0x000000AC) DMA receive length register channel 5 */
+ __IOM uint32_t DMA5_CTRL_REG; /*!< (@ 0x000000B0) Control register for the DMA channel 5 */
+ __IOM uint32_t DMA5_IDX_REG; /*!< (@ 0x000000B4) Index value of DMA channel 5 */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t DMA6_A_START_REG; /*!< (@ 0x000000C0) Start address A of DMA channel 6 */
+ __IOM uint32_t DMA6_B_START_REG; /*!< (@ 0x000000C4) Start address B of DMA channel 6 */
+ __IOM uint32_t DMA6_INT_REG; /*!< (@ 0x000000C8) DMA receive interrupt register channel 6 */
+ __IOM uint32_t DMA6_LEN_REG; /*!< (@ 0x000000CC) DMA receive length register channel 6 */
+ __IOM uint32_t DMA6_CTRL_REG; /*!< (@ 0x000000D0) Control register for the DMA channel 6 */
+ __IOM uint32_t DMA6_IDX_REG; /*!< (@ 0x000000D4) Index value of DMA channel 6 */
+ __IM uint32_t RESERVED6[2];
+ __IOM uint32_t DMA7_A_START_REG; /*!< (@ 0x000000E0) Start address A of DMA channel 7 */
+ __IOM uint32_t DMA7_B_START_REG; /*!< (@ 0x000000E4) Start address B of DMA channel 7 */
+ __IOM uint32_t DMA7_INT_REG; /*!< (@ 0x000000E8) DMA receive interrupt register channel 7 */
+ __IOM uint32_t DMA7_LEN_REG; /*!< (@ 0x000000EC) DMA receive length register channel 7 */
+ __IOM uint32_t DMA7_CTRL_REG; /*!< (@ 0x000000F0) Control register for the DMA channel 7 */
+ __IOM uint32_t DMA7_IDX_REG; /*!< (@ 0x000000F4) Index value of DMA channel 7 */
+ __IM uint32_t RESERVED7[2];
+ __IOM uint32_t DMA_REQ_MUX_REG; /*!< (@ 0x00000100) DMA channel assignments */
+ __IOM uint32_t DMA_INT_STATUS_REG; /*!< (@ 0x00000104) DMA interrupt status register */
+ __IOM uint32_t DMA_CLEAR_INT_REG; /*!< (@ 0x00000108) DMA clear interrupt register */
+ __IOM uint32_t DMA_INT_MASK_REG; /*!< (@ 0x0000010C) DMA Interrupt mask register */
+} DMA_Type; /*!< Size = 272 (0x110) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DW ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DW registers (DW)
+ */
+
+typedef struct { /*!< (@ 0x30020000) DW Structure */
+ __IOM uint32_t AHB_DMA_PL1_REG; /*!< (@ 0x00000000) AHB-DMA layer priority level for RFTP (AHB DMA
+ layer only) */
+ __IOM uint32_t AHB_DMA_PL2_REG; /*!< (@ 0x00000004) AHB-DMA layer priority level for LCD (AHB DMA
+ layer only) */
+ __IOM uint32_t AHB_DMA_PL3_REG; /*!< (@ 0x00000008) AHB-DMA layer Priority level for GEN-DMA (AHB
+ DMA layer only) */
+ __IOM uint32_t AHB_DMA_PL4_REG; /*!< (@ 0x0000000C) AHB-DMA layer Priority level for CRYPTO-DMA (AHB
+ DMA layer only) */
+ __IM uint32_t RESERVED[14];
+ __IOM uint32_t AHB_DMA_DFLT_MASTER_REG; /*!< (@ 0x00000048) Default master ID number (AHB DMA layer only) */
+ __IOM uint32_t AHB_DMA_WTEN_REG; /*!< (@ 0x0000004C) Weighted-Token Arbitration Scheme Enable (AHB
+ DMA layer only) */
+ __IOM uint32_t AHB_DMA_TCL_REG; /*!< (@ 0x00000050) Master clock refresh period (AHB DMA layer only) */
+ __IOM uint32_t AHB_DMA_CCLM1_REG; /*!< (@ 0x00000054) USB Master clock tokens (AHB DMA layer only) */
+ __IOM uint32_t AHB_DMA_CCLM2_REG; /*!< (@ 0x00000058) GenDMA Master clock tokens (AHB DMA layer only) */
+ __IOM uint32_t AHB_DMA_CCLM3_REG; /*!< (@ 0x0000005C) CRYPTO Master clock tokens (AHB DMA layer only) */
+ __IOM uint32_t AHB_DMA_CCLM4_REG; /*!< (@ 0x00000060) CRYPTO Master clock tokens (AHB DMA layer only) */
+ __IM uint32_t RESERVED1[11];
+ __IOM uint32_t AHB_DMA_VERSION_REG; /*!< (@ 0x00000090) Version ID (AHB DMA layer only) */
+} DW_Type; /*!< Size = 148 (0x94) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPADC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPADC registers (GPADC)
+ */
+
+typedef struct { /*!< (@ 0x50030900) GPADC Structure */
+ __IOM uint32_t GP_ADC_CTRL_REG; /*!< (@ 0x00000000) General Purpose ADC Control Register */
+ __IOM uint32_t GP_ADC_CTRL2_REG; /*!< (@ 0x00000004) General Purpose ADC Second Control Register */
+ __IOM uint32_t GP_ADC_CTRL3_REG; /*!< (@ 0x00000008) General Purpose ADC Third Control Register */
+ __IOM uint32_t GP_ADC_OFFP_REG; /*!< (@ 0x0000000C) General Purpose ADC Positive Offset Register */
+ __IOM uint32_t GP_ADC_OFFN_REG; /*!< (@ 0x00000010) General Purpose ADC Negative Offset Register */
+ __IOM uint32_t GP_ADC_CLEAR_INT_REG; /*!< (@ 0x00000014) General Purpose ADC Clear Interrupt Register */
+ __IOM uint32_t GP_ADC_RESULT_REG; /*!< (@ 0x00000018) General Purpose ADC Result Register */
+} GPADC_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIO ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIO registers (GPIO)
+ */
+
+typedef struct { /*!< (@ 0x50020A00) GPIO Structure */
+ __IOM uint32_t P0_DATA_REG; /*!< (@ 0x00000000) P0 Data input / output Register */
+ __IOM uint32_t P1_DATA_REG; /*!< (@ 0x00000004) P1 Data input / output Register */
+ __IOM uint32_t P0_SET_DATA_REG; /*!< (@ 0x00000008) P0 Set port pins Register */
+ __IOM uint32_t P1_SET_DATA_REG; /*!< (@ 0x0000000C) P1 Set port pins Register */
+ __IOM uint32_t P0_RESET_DATA_REG; /*!< (@ 0x00000010) P0 Reset port pins Register */
+ __IOM uint32_t P1_RESET_DATA_REG; /*!< (@ 0x00000014) P1 Reset port pins Register */
+ __IOM uint32_t P0_00_MODE_REG; /*!< (@ 0x00000018) P0_00 Mode Register */
+ __IOM uint32_t P0_01_MODE_REG; /*!< (@ 0x0000001C) P0_01 Mode Register */
+ __IOM uint32_t P0_02_MODE_REG; /*!< (@ 0x00000020) P0_02 Mode Register */
+ __IOM uint32_t P0_03_MODE_REG; /*!< (@ 0x00000024) P0_03 Mode Register */
+ __IOM uint32_t P0_04_MODE_REG; /*!< (@ 0x00000028) P0_04 Mode Register */
+ __IOM uint32_t P0_05_MODE_REG; /*!< (@ 0x0000002C) P0_05 Mode Register */
+ __IOM uint32_t P0_06_MODE_REG; /*!< (@ 0x00000030) P0_06 Mode Register */
+ __IOM uint32_t P0_07_MODE_REG; /*!< (@ 0x00000034) P0_07 Mode Register */
+ __IOM uint32_t P0_08_MODE_REG; /*!< (@ 0x00000038) P0_08 Mode Register */
+ __IOM uint32_t P0_09_MODE_REG; /*!< (@ 0x0000003C) P0_09 Mode Register */
+ __IOM uint32_t P0_10_MODE_REG; /*!< (@ 0x00000040) P0_10 Mode Register */
+ __IOM uint32_t P0_11_MODE_REG; /*!< (@ 0x00000044) P0_11 Mode Register */
+ __IOM uint32_t P0_12_MODE_REG; /*!< (@ 0x00000048) P0_12 Mode Register */
+ __IOM uint32_t P0_13_MODE_REG; /*!< (@ 0x0000004C) P0_13 Mode Register */
+ __IOM uint32_t P0_14_MODE_REG; /*!< (@ 0x00000050) P0_14 Mode Register */
+ __IOM uint32_t P0_15_MODE_REG; /*!< (@ 0x00000054) P0_15 Mode Register */
+ __IOM uint32_t P0_16_MODE_REG; /*!< (@ 0x00000058) P0_16 Mode Register */
+ __IOM uint32_t P0_17_MODE_REG; /*!< (@ 0x0000005C) P0_17 Mode Register */
+ __IOM uint32_t P0_18_MODE_REG; /*!< (@ 0x00000060) P0_18 Mode Register */
+ __IOM uint32_t P0_19_MODE_REG; /*!< (@ 0x00000064) P0_19 Mode Register */
+ __IOM uint32_t P0_20_MODE_REG; /*!< (@ 0x00000068) P0_20 Mode Register */
+ __IOM uint32_t P0_21_MODE_REG; /*!< (@ 0x0000006C) P0_21 Mode Register */
+ __IOM uint32_t P0_22_MODE_REG; /*!< (@ 0x00000070) P0_22 Mode Register */
+ __IOM uint32_t P0_23_MODE_REG; /*!< (@ 0x00000074) P0_23 Mode Register */
+ __IOM uint32_t P0_24_MODE_REG; /*!< (@ 0x00000078) P0_24 Mode Register */
+ __IOM uint32_t P0_25_MODE_REG; /*!< (@ 0x0000007C) P0_25 Mode Register */
+ __IOM uint32_t P0_26_MODE_REG; /*!< (@ 0x00000080) P0_26 Mode Register */
+ __IOM uint32_t P0_27_MODE_REG; /*!< (@ 0x00000084) P0_27 Mode Register */
+ __IOM uint32_t P0_28_MODE_REG; /*!< (@ 0x00000088) P0_28 Mode Register */
+ __IOM uint32_t P0_29_MODE_REG; /*!< (@ 0x0000008C) P0_29 Mode Register */
+ __IOM uint32_t P0_30_MODE_REG; /*!< (@ 0x00000090) P0_30 Mode Register */
+ __IOM uint32_t P0_31_MODE_REG; /*!< (@ 0x00000094) P0_31 Mode Register */
+ __IOM uint32_t P1_00_MODE_REG; /*!< (@ 0x00000098) P1_00 Mode Register */
+ __IOM uint32_t P1_01_MODE_REG; /*!< (@ 0x0000009C) P1_01 Mode Register */
+ __IOM uint32_t P1_02_MODE_REG; /*!< (@ 0x000000A0) P1_02 Mode Register */
+ __IOM uint32_t P1_03_MODE_REG; /*!< (@ 0x000000A4) P1_03 Mode Register */
+ __IOM uint32_t P1_04_MODE_REG; /*!< (@ 0x000000A8) P1_04 Mode Register */
+ __IOM uint32_t P1_05_MODE_REG; /*!< (@ 0x000000AC) P1_05 Mode Register */
+ __IOM uint32_t P1_06_MODE_REG; /*!< (@ 0x000000B0) P1_06 Mode Register */
+ __IOM uint32_t P1_07_MODE_REG; /*!< (@ 0x000000B4) P1_07 Mode Register */
+ __IOM uint32_t P1_08_MODE_REG; /*!< (@ 0x000000B8) P1_08 Mode Register */
+ __IOM uint32_t P1_09_MODE_REG; /*!< (@ 0x000000BC) P1_09 Mode Register */
+ __IOM uint32_t P1_10_MODE_REG; /*!< (@ 0x000000C0) P1_10 Mode Register */
+ __IOM uint32_t P1_11_MODE_REG; /*!< (@ 0x000000C4) P1_11 Mode Register */
+ __IOM uint32_t P1_12_MODE_REG; /*!< (@ 0x000000C8) P1_12 Mode Register */
+ __IOM uint32_t P1_13_MODE_REG; /*!< (@ 0x000000CC) P1_13 Mode Register */
+ __IOM uint32_t P1_14_MODE_REG; /*!< (@ 0x000000D0) P1_14 Mode Register */
+ __IOM uint32_t P1_15_MODE_REG; /*!< (@ 0x000000D4) P1_15 Mode Register */
+ __IOM uint32_t P1_16_MODE_REG; /*!< (@ 0x000000D8) P1_16 Mode Register */
+ __IOM uint32_t P1_17_MODE_REG; /*!< (@ 0x000000DC) P1_17 Mode Register */
+ __IOM uint32_t P1_18_MODE_REG; /*!< (@ 0x000000E0) P1_18 Mode Register */
+ __IOM uint32_t P1_19_MODE_REG; /*!< (@ 0x000000E4) P1_19 Mode Register */
+ __IOM uint32_t P1_20_MODE_REG; /*!< (@ 0x000000E8) P1_20 Mode Register */
+ __IOM uint32_t P1_21_MODE_REG; /*!< (@ 0x000000EC) P1_21 Mode Register */
+ __IOM uint32_t P1_22_MODE_REG; /*!< (@ 0x000000F0) P1_22 Mode Register */
+ __IOM uint32_t P0_PADPWR_CTRL_REG; /*!< (@ 0x000000F4) P0 Output Power Control Register */
+ __IOM uint32_t P1_PADPWR_CTRL_REG; /*!< (@ 0x000000F8) P1 Output Power Control Register */
+ __IOM uint32_t GPIO_CLK_SEL_REG; /*!< (@ 0x000000FC) Select which clock to map on ports P0/P1 */
+ __IOM uint32_t PAD_WEAK_CTRL_REG; /*!< (@ 0x00000100) Weak Pads Control Register */
+} GPIO_Type; /*!< Size = 260 (0x104) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPREG ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPREG registers (GPREG)
+ */
+
+typedef struct { /*!< (@ 0x50040300) GPREG Structure */
+ __IOM uint32_t SET_FREEZE_REG; /*!< (@ 0x00000000) Controls freezing of various timers/counters
+ (incl. DMA and USB). */
+ __IOM uint32_t RESET_FREEZE_REG; /*!< (@ 0x00000004) Controls unfreezing of various timers/counters
+ (incl. DMA and USB). */
+ __IOM uint32_t DEBUG_REG; /*!< (@ 0x00000008) Various debug information register. */
+ __IOM uint32_t GP_STATUS_REG; /*!< (@ 0x0000000C) General purpose system status register. */
+ __IOM uint32_t GP_CONTROL_REG; /*!< (@ 0x00000010) General purpose system control register. */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t USBPAD_REG; /*!< (@ 0x00000018) USB pads control register */
+} GPREG_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ I2C ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C registers (I2C)
+ */
+
+typedef struct { /*!< (@ 0x50020600) I2C Structure */
+ __IOM uint32_t I2C_CON_REG; /*!< (@ 0x00000000) I2C Control Register */
+ __IOM uint32_t I2C_TAR_REG; /*!< (@ 0x00000004) I2C Target Address Register */
+ __IOM uint32_t I2C_SAR_REG; /*!< (@ 0x00000008) I2C Slave Address Register */
+ __IOM uint32_t I2C_HS_MADDR_REG; /*!< (@ 0x0000000C) I2C High Speed Master Mode Code Address Register */
+ __IOM uint32_t I2C_DATA_CMD_REG; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register */
+ __IOM uint32_t I2C_SS_SCL_HCNT_REG; /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register */
+ __IOM uint32_t I2C_SS_SCL_LCNT_REG; /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register */
+ __IOM uint32_t I2C_FS_SCL_HCNT_REG; /*!< (@ 0x0000001C) Fast Speed I2C Clock SCL High Count Register */
+ __IOM uint32_t I2C_FS_SCL_LCNT_REG; /*!< (@ 0x00000020) Fast Speed I2C Clock SCL Low Count Register */
+ __IOM uint32_t I2C_HS_SCL_HCNT_REG; /*!< (@ 0x00000024) High Speed I2C Clock SCL High Count Register */
+ __IOM uint32_t I2C_HS_SCL_LCNT_REG; /*!< (@ 0x00000028) High Speed I2C Clock SCL Low Count Register */
+ __IOM uint32_t I2C_INTR_STAT_REG; /*!< (@ 0x0000002C) I2C Interrupt Status Register */
+ __IOM uint32_t I2C_INTR_MASK_REG; /*!< (@ 0x00000030) I2C Interrupt Mask Register */
+ __IOM uint32_t I2C_RAW_INTR_STAT_REG; /*!< (@ 0x00000034) I2C Raw Interrupt Status Register */
+ __IOM uint32_t I2C_RX_TL_REG; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */
+ __IOM uint32_t I2C_TX_TL_REG; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */
+ __IOM uint32_t I2C_CLR_INTR_REG; /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register */
+ __IOM uint32_t I2C_CLR_RX_UNDER_REG; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register */
+ __IOM uint32_t I2C_CLR_RX_OVER_REG; /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register */
+ __IOM uint32_t I2C_CLR_TX_OVER_REG; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register */
+ __IOM uint32_t I2C_CLR_RD_REQ_REG; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */
+ __IOM uint32_t I2C_CLR_TX_ABRT_REG; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register */
+ __IOM uint32_t I2C_CLR_RX_DONE_REG; /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register */
+ __IOM uint32_t I2C_CLR_ACTIVITY_REG; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register */
+ __IOM uint32_t I2C_CLR_STOP_DET_REG; /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register */
+ __IOM uint32_t I2C_CLR_START_DET_REG; /*!< (@ 0x00000064) Clear START_DET Interrupt Register */
+ __IOM uint32_t I2C_CLR_GEN_CALL_REG; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register */
+ __IOM uint32_t I2C_ENABLE_REG; /*!< (@ 0x0000006C) I2C Enable Register */
+ __IOM uint32_t I2C_STATUS_REG; /*!< (@ 0x00000070) I2C Status Register */
+ __IOM uint32_t I2C_TXFLR_REG; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register */
+ __IOM uint32_t I2C_RXFLR_REG; /*!< (@ 0x00000078) I2C Receive FIFO Level Register */
+ __IOM uint32_t I2C_SDA_HOLD_REG; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register */
+ __IOM uint32_t I2C_TX_ABRT_SOURCE_REG; /*!< (@ 0x00000080) I2C Transmit Abort Source Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t I2C_DMA_CR_REG; /*!< (@ 0x00000088) DMA Control Register */
+ __IOM uint32_t I2C_DMA_TDLR_REG; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */
+ __IOM uint32_t I2C_DMA_RDLR_REG; /*!< (@ 0x00000090) I2C Receive Data Level Register */
+ __IOM uint32_t I2C_SDA_SETUP_REG; /*!< (@ 0x00000094) I2C SDA Setup Register */
+ __IOM uint32_t I2C_ACK_GENERAL_CALL_REG; /*!< (@ 0x00000098) I2C ACK General Call Register */
+ __IOM uint32_t I2C_ENABLE_STATUS_REG; /*!< (@ 0x0000009C) I2C Enable Status Register */
+ __IOM uint32_t I2C_IC_FS_SPKLEN_REG; /*!< (@ 0x000000A0) I2C SS and FS spike suppression limit Size */
+ __IOM uint32_t I2C_IC_HS_SPKLEN_REG; /*!< (@ 0x000000A4) I2C HS spike suppression limit Size */
+} I2C_Type; /*!< Size = 168 (0xa8) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ I2C2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C2 registers (I2C2)
+ */
+
+typedef struct { /*!< (@ 0x50020700) I2C2 Structure */
+ __IOM uint32_t I2C2_CON_REG; /*!< (@ 0x00000000) I2C Control Register */
+ __IOM uint32_t I2C2_TAR_REG; /*!< (@ 0x00000004) I2C Target Address Register */
+ __IOM uint32_t I2C2_SAR_REG; /*!< (@ 0x00000008) I2C Slave Address Register */
+ __IOM uint32_t I2C2_HS_MADDR_REG; /*!< (@ 0x0000000C) I2C High Speed Master Mode Code Address Register */
+ __IOM uint32_t I2C2_DATA_CMD_REG; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register */
+ __IOM uint32_t I2C2_SS_SCL_HCNT_REG; /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register */
+ __IOM uint32_t I2C2_SS_SCL_LCNT_REG; /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register */
+ __IOM uint32_t I2C2_FS_SCL_HCNT_REG; /*!< (@ 0x0000001C) Fast Speed I2C Clock SCL High Count Register */
+ __IOM uint32_t I2C2_FS_SCL_LCNT_REG; /*!< (@ 0x00000020) Fast Speed I2C Clock SCL Low Count Register */
+ __IOM uint32_t I2C2_HS_SCL_HCNT_REG; /*!< (@ 0x00000024) High Speed I2C Clock SCL High Count Register */
+ __IOM uint32_t I2C2_HS_SCL_LCNT_REG; /*!< (@ 0x00000028) High Speed I2C Clock SCL Low Count Register */
+ __IOM uint32_t I2C2_INTR_STAT_REG; /*!< (@ 0x0000002C) I2C Interrupt Status Register */
+ __IOM uint32_t I2C2_INTR_MASK_REG; /*!< (@ 0x00000030) I2C Interrupt Mask Register */
+ __IOM uint32_t I2C2_RAW_INTR_STAT_REG; /*!< (@ 0x00000034) I2C Raw Interrupt Status Register */
+ __IOM uint32_t I2C2_RX_TL_REG; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */
+ __IOM uint32_t I2C2_TX_TL_REG; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */
+ __IOM uint32_t I2C2_CLR_INTR_REG; /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register */
+ __IOM uint32_t I2C2_CLR_RX_UNDER_REG; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register */
+ __IOM uint32_t I2C2_CLR_RX_OVER_REG; /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register */
+ __IOM uint32_t I2C2_CLR_TX_OVER_REG; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register */
+ __IOM uint32_t I2C2_CLR_RD_REQ_REG; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */
+ __IOM uint32_t I2C2_CLR_TX_ABRT_REG; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register */
+ __IOM uint32_t I2C2_CLR_RX_DONE_REG; /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register */
+ __IOM uint32_t I2C2_CLR_ACTIVITY_REG; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register */
+ __IOM uint32_t I2C2_CLR_STOP_DET_REG; /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register */
+ __IOM uint32_t I2C2_CLR_START_DET_REG; /*!< (@ 0x00000064) Clear START_DET Interrupt Register */
+ __IOM uint32_t I2C2_CLR_GEN_CALL_REG; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register */
+ __IOM uint32_t I2C2_ENABLE_REG; /*!< (@ 0x0000006C) I2C Enable Register */
+ __IOM uint32_t I2C2_STATUS_REG; /*!< (@ 0x00000070) I2C Status Register */
+ __IOM uint32_t I2C2_TXFLR_REG; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register */
+ __IOM uint32_t I2C2_RXFLR_REG; /*!< (@ 0x00000078) I2C Receive FIFO Level Register */
+ __IOM uint32_t I2C2_SDA_HOLD_REG; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register */
+ __IOM uint32_t I2C2_TX_ABRT_SOURCE_REG; /*!< (@ 0x00000080) I2C Transmit Abort Source Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t I2C2_DMA_CR_REG; /*!< (@ 0x00000088) DMA Control Register */
+ __IOM uint32_t I2C2_DMA_TDLR_REG; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */
+ __IOM uint32_t I2C2_DMA_RDLR_REG; /*!< (@ 0x00000090) I2C Receive Data Level Register */
+ __IOM uint32_t I2C2_SDA_SETUP_REG; /*!< (@ 0x00000094) I2C SDA Setup Register */
+ __IOM uint32_t I2C2_ACK_GENERAL_CALL_REG; /*!< (@ 0x00000098) I2C ACK General Call Register */
+ __IOM uint32_t I2C2_ENABLE_STATUS_REG; /*!< (@ 0x0000009C) I2C Enable Status Register */
+ __IOM uint32_t I2C2_IC_FS_SPKLEN_REG; /*!< (@ 0x000000A0) I2C SS and FS spike suppression limit Size */
+ __IOM uint32_t I2C2_IC_HS_SPKLEN_REG; /*!< (@ 0x000000A4) I2C HS spike suppression limit Size */
+} I2C2_Type; /*!< Size = 168 (0xa8) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ LCDC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief LCDC registers (LCDC)
+ */
+
+typedef struct { /*!< (@ 0x30030000) LCDC Structure */
+ __IOM uint32_t LCDC_MODE_REG; /*!< (@ 0x00000000) Display Mode */
+ __IOM uint32_t LCDC_CLKCTRL_REG; /*!< (@ 0x00000004) Clock Divider */
+ __IOM uint32_t LCDC_BGCOLOR_REG; /*!< (@ 0x00000008) Background Color */
+ __IOM uint32_t LCDC_RESXY_REG; /*!< (@ 0x0000000C) Resolution X,Y */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t LCDC_FRONTPORCHXY_REG; /*!< (@ 0x00000014) Front Porch X and Y */
+ __IOM uint32_t LCDC_BLANKINGXY_REG; /*!< (@ 0x00000018) Blanking X and Y */
+ __IOM uint32_t LCDC_BACKPORCHXY_REG; /*!< (@ 0x0000001C) Back Porch X and Y */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t LCDC_DBIB_CFG_REG; /*!< (@ 0x00000028) MIPI Config Register */
+ __IOM uint32_t LCDC_GPIO_REG; /*!< (@ 0x0000002C) General Purpose IO (2-bits) */
+ __IOM uint32_t LCDC_LAYER0_MODE_REG; /*!< (@ 0x00000030) Layer0 Mode */
+ __IOM uint32_t LCDC_LAYER0_STARTXY_REG; /*!< (@ 0x00000034) Layer0 Start XY */
+ __IOM uint32_t LCDC_LAYER0_SIZEXY_REG; /*!< (@ 0x00000038) Layer0 Size XY */
+ __IOM uint32_t LCDC_LAYER0_BASEADDR_REG; /*!< (@ 0x0000003C) Layer0 Base Addr */
+ __IOM uint32_t LCDC_LAYER0_STRIDE_REG; /*!< (@ 0x00000040) Layer0 Stride */
+ __IOM uint32_t LCDC_LAYER0_RESXY_REG; /*!< (@ 0x00000044) Layer0 Res XY */
+ __IM uint32_t RESERVED2[18];
+ __IOM uint32_t LCDC_JDI_RESXY_REG; /*!< (@ 0x00000090) Resolution XY for the JDI parallel I/F */
+ __IOM uint32_t LCDC_JDI_FBX_BLANKING_REG; /*!< (@ 0x00000094) Horizontal front/back blanking (hck half periods) */
+ __IOM uint32_t LCDC_JDI_FBY_BLANKING_REG; /*!< (@ 0x00000098) Vertical front/back blanking (vck half periods) */
+ __IOM uint32_t LCDC_JDI_HCK_WIDTH_REG; /*!< (@ 0x0000009C) HCK high/low width */
+ __IOM uint32_t LCDC_JDI_XRST_WIDTH_REG; /*!< (@ 0x000000A0) XRST width */
+ __IOM uint32_t LCDC_JDI_VST_DELAY_REG; /*!< (@ 0x000000A4) XRST-to-VST delay */
+ __IOM uint32_t LCDC_JDI_VST_WIDTH_REG; /*!< (@ 0x000000A8) VST width */
+ __IOM uint32_t LCDC_JDI_VCK_DELAY_REG; /*!< (@ 0x000000AC) XRST-to-VCK delay */
+ __IOM uint32_t LCDC_JDI_HST_DELAY_REG; /*!< (@ 0x000000B0) VCK-to-HST delay */
+ __IOM uint32_t LCDC_JDI_HST_WIDTH_REG; /*!< (@ 0x000000B4) HST width */
+ __IOM uint32_t LCDC_JDI_ENB_START_HLINE_REG; /*!< (@ 0x000000B8) ENB start horizontal line */
+ __IOM uint32_t LCDC_JDI_ENB_END_HLINE_REG; /*!< (@ 0x000000BC) ENB end horizontal line */
+ __IOM uint32_t LCDC_JDI_ENB_START_CLK_REG; /*!< (@ 0x000000C0) ENB start delay */
+ __IOM uint32_t LCDC_JDI_ENB_WIDTH_CLK_REG; /*!< (@ 0x000000C4) ENB width */
+ __IM uint32_t RESERVED3[8];
+ __IOM uint32_t LCDC_DBIB_CMD_REG; /*!< (@ 0x000000E8) MIPI DBIB Command Register */
+ __IM uint32_t RESERVED4[2];
+ __IOM uint32_t LCDC_IDREG_REG; /*!< (@ 0x000000F4) Identification Register */
+ __IOM uint32_t LCDC_INTERRUPT_REG; /*!< (@ 0x000000F8) Interrupt Register */
+ __IOM uint32_t LCDC_STATUS_REG; /*!< (@ 0x000000FC) Status Register */
+ __IM uint32_t RESERVED5[33];
+ __IOM uint32_t LCDC_CRC_REG; /*!< (@ 0x00000184) CRC check */
+ __IOM uint32_t LCDC_LAYER0_OFFSETX_REG; /*!< (@ 0x00000188) Layer0 OffsetX and DMA prefetch */
+} LCDC_Type; /*!< Size = 396 (0x18c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ LRA ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief LRA registers (LRA)
+ */
+
+typedef struct { /*!< (@ 0x50030A00) LRA Structure */
+ __IOM uint32_t LRA_CTRL1_REG; /*!< (@ 0x00000000) General Purpose LRA Control Register */
+ __IOM uint32_t LRA_CTRL2_REG; /*!< (@ 0x00000004) General Purpose LRA Control Register */
+ __IOM uint32_t LRA_CTRL3_REG; /*!< (@ 0x00000008) General Purpose LRA Control Register */
+ __IOM uint32_t LRA_FLT_SMP1_REG; /*!< (@ 0x0000000C) LRA Sample Register */
+ __IOM uint32_t LRA_FLT_SMP2_REG; /*!< (@ 0x00000010) LRA Sample Register */
+ __IOM uint32_t LRA_FLT_SMP3_REG; /*!< (@ 0x00000014) LRA Sample Register */
+ __IOM uint32_t LRA_FLT_SMP4_REG; /*!< (@ 0x00000018) LRA Sample Register */
+ __IOM uint32_t LRA_FLT_SMP5_REG; /*!< (@ 0x0000001C) LRA Sample Register */
+ __IOM uint32_t LRA_FLT_SMP6_REG; /*!< (@ 0x00000020) LRA Sample Register */
+ __IOM uint32_t LRA_FLT_SMP7_REG; /*!< (@ 0x00000024) LRA Sample Register */
+ __IOM uint32_t LRA_FLT_SMP8_REG; /*!< (@ 0x00000028) LRA Sample Register */
+ __IOM uint32_t LRA_FLT_COEF1_REG; /*!< (@ 0x0000002C) LRA Filter Coefficient Register */
+ __IOM uint32_t LRA_FLT_COEF2_REG; /*!< (@ 0x00000030) LRA Filter Coefficient Register */
+ __IOM uint32_t LRA_FLT_COEF3_REG; /*!< (@ 0x00000034) LRA Filter Coefficient Register */
+ __IOM uint32_t LRA_BRD_LS_REG; /*!< (@ 0x00000038) LRA Bridge Register */
+ __IOM uint32_t LRA_BRD_HS_REG; /*!< (@ 0x0000003C) LRA Bridge Register */
+ __IOM uint32_t LRA_BRD_STAT_REG; /*!< (@ 0x00000040) LRA Bridge Staus Register */
+ __IOM uint32_t LRA_ADC_CTRL1_REG; /*!< (@ 0x00000044) General Purpose ADC Control Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t LRA_ADC_RESULT_REG; /*!< (@ 0x00000050) General Purpose ADC Result Register */
+ __IOM uint32_t LRA_LDO_REG; /*!< (@ 0x00000054) LRA LDO Regsiter */
+ __IOM uint32_t LRA_DFT_REG; /*!< (@ 0x00000058) LRA test Register */
+} LRA_Type; /*!< Size = 92 (0x5c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ MEMCTRL ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief MEMCTRL registers (MEMCTRL)
+ */
+
+typedef struct { /*!< (@ 0x50050000) MEMCTRL Structure */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t MEM_PRIO_REG; /*!< (@ 0x00000004) Priority Control Register */
+ __IOM uint32_t MEM_STALL_REG; /*!< (@ 0x00000008) Maximum Stall cycles Control Register */
+ __IOM uint32_t MEM_STATUS_REG; /*!< (@ 0x0000000C) Memory Arbiter Status Register */
+ __IOM uint32_t MEM_STATUS2_REG; /*!< (@ 0x00000010) RAM cells Status Register */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t CMI_CODE_BASE_REG; /*!< (@ 0x00000020) CMAC code Base Address Register */
+ __IOM uint32_t CMI_DATA_BASE_REG; /*!< (@ 0x00000024) CMAC data Base Address Register */
+ __IOM uint32_t CMI_SHARED_BASE_REG; /*!< (@ 0x00000028) CMAC shared data Base Address Register */
+ __IOM uint32_t CMI_END_REG; /*!< (@ 0x0000002C) CMAC end Address Register */
+ __IOM uint32_t SNC_BASE_REG; /*!< (@ 0x00000030) Sensor Node Controller Base Address Register */
+ __IM uint32_t RESERVED2[16];
+ __IOM uint32_t BUSY_SET_REG; /*!< (@ 0x00000074) BSR Set Register */
+ __IOM uint32_t BUSY_RESET_REG; /*!< (@ 0x00000078) BSR Reset Register */
+ __IOM uint32_t BUSY_STAT_REG; /*!< (@ 0x0000007C) BSR Status Register */
+} MEMCTRL_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ OTPC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief OTPC registers (OTPC)
+ */
+
+typedef struct { /*!< (@ 0x30070000) OTPC Structure */
+ __IOM uint32_t OTPC_MODE_REG; /*!< (@ 0x00000000) Mode register */
+ __IOM uint32_t OTPC_STAT_REG; /*!< (@ 0x00000004) Status register */
+ __IOM uint32_t OTPC_PADDR_REG; /*!< (@ 0x00000008) The address of the word that will be programmed,
+ when the PROG mode is used. */
+ __IOM uint32_t OTPC_PWORD_REG; /*!< (@ 0x0000000C) The 32-bit word that will be programmed, when
+ the PROG mode is used. */
+ __IOM uint32_t OTPC_TIM1_REG; /*!< (@ 0x00000010) Various timing parameters of the OTP cell. */
+ __IOM uint32_t OTPC_TIM2_REG; /*!< (@ 0x00000014) Various timing parameters of the OTP cell. */
+} OTPC_Type; /*!< Size = 24 (0x18) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PDC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief PDC registers (PDC)
+ */
+
+typedef struct { /*!< (@ 0x50000200) PDC Structure */
+ __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
+ __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
+ __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
+ __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
+ __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
+ __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
+ __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
+ __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
+ __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
+ __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
+ __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
+ __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
+ __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
+ __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
+ __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
+ __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
+ __IM uint32_t RESERVED[16];
+ __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
+ __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
+ __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
+ __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
+} PDC_Type; /*!< Size = 152 (0x98) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PWMLED ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief PWMLED registers (PWMLED)
+ */
+
+typedef struct { /*!< (@ 0x50030500) PWMLED Structure */
+ __IOM uint32_t PWMLED_DUTY_CYCLE_LED1_REG; /*!< (@ 0x00000000) Defines duty cycle for PWM1 */
+ __IOM uint32_t PWMLED_DUTY_CYCLE_LED2_REG; /*!< (@ 0x00000004) Defines duty cycle for PWM2 */
+ __IOM uint32_t PWMLED_FREQUENCY_REG; /*!< (@ 0x00000008) Defines the PWM frequecny */
+ __IOM uint32_t PWMLED_CTRL_REG; /*!< (@ 0x0000000C) PWM Control register */
+} PWMLED_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ QSPIC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief QSPIC registers (QSPIC)
+ */
+
+typedef struct { /*!< (@ 0x38000000) QSPIC Structure */
+ __IOM uint32_t QSPIC_CTRLBUS_REG; /*!< (@ 0x00000000) SPI Bus control register for the Manual mode */
+ __IOM uint32_t QSPIC_CTRLMODE_REG; /*!< (@ 0x00000004) Mode Control register */
+ __IOM uint32_t QSPIC_RECVDATA_REG; /*!< (@ 0x00000008) Received data for the Manual mode */
+ __IOM uint32_t QSPIC_BURSTCMDA_REG; /*!< (@ 0x0000000C) The way of reading in Auto mode (command register
+ A) */
+ __IOM uint32_t QSPIC_BURSTCMDB_REG; /*!< (@ 0x00000010) The way of reading in Auto mode (command register
+ B) */
+ __IOM uint32_t QSPIC_STATUS_REG; /*!< (@ 0x00000014) The status register of the QSPI controller */
+ __IOM uint32_t QSPIC_WRITEDATA_REG; /*!< (@ 0x00000018) Write data to SPI Bus for the Manual mode */
+ __IOM uint32_t QSPIC_READDATA_REG; /*!< (@ 0x0000001C) Read data from SPI Bus for the Manual mode */
+ __IOM uint32_t QSPIC_DUMMYDATA_REG; /*!< (@ 0x00000020) Send dummy clocks to SPI Bus for the Manual mode */
+ __IOM uint32_t QSPIC_ERASECTRL_REG; /*!< (@ 0x00000024) QSPI Erase control register */
+ __IOM uint32_t QSPIC_ERASECMDA_REG; /*!< (@ 0x00000028) The way of erasing in Auto mode (command register
+ A) */
+ __IOM uint32_t QSPIC_ERASECMDB_REG; /*!< (@ 0x0000002C) The way of erasing in Auto mode (command register
+ B) */
+ __IOM uint32_t QSPIC_BURSTBRK_REG; /*!< (@ 0x00000030) Read break sequence in Auto mode */
+ __IOM uint32_t QSPIC_STATUSCMD_REG; /*!< (@ 0x00000034) The way of reading the status of external device
+ in Auto mode */
+ __IOM uint32_t QSPIC_CHCKERASE_REG; /*!< (@ 0x00000038) Check erase progress in Auto mode */
+ __IOM uint32_t QSPIC_GP_REG; /*!< (@ 0x0000003C) QSPI General Purpose control register */
+ __IOM uint32_t QSPIC_UCODE_START; /*!< (@ 0x00000040) QSPIC uCode memory */
+ __IM uint32_t RESERVED[15];
+ __IOM uint32_t QSPIC_CTR_CTRL_REG; /*!< (@ 0x00000080) Control register for the decryption engine of
+ the QSPIC */
+ __IOM uint32_t QSPIC_CTR_SADDR_REG; /*!< (@ 0x00000084) Start address of the encrypted content in the
+ QSPI flash */
+ __IOM uint32_t QSPIC_CTR_EADDR_REG; /*!< (@ 0x00000088) End address of the encrypted content in the QSPI
+ flash */
+ __IOM uint32_t QSPIC_CTR_NONCE_0_3_REG; /*!< (@ 0x0000008C) Nonce bytes 0 to 3 for the AES-CTR algorithm */
+ __IOM uint32_t QSPIC_CTR_NONCE_4_7_REG; /*!< (@ 0x00000090) Nonce bytes 4 to 7 for the AES-CTR algorithm */
+ __IOM uint32_t QSPIC_CTR_KEY_0_3_REG; /*!< (@ 0x00000094) Key bytes 0 to 3 for the AES-CTR algorithm */
+ __IOM uint32_t QSPIC_CTR_KEY_4_7_REG; /*!< (@ 0x00000098) Key bytes 4 to 7 for the AES-CTR algorithm */
+ __IOM uint32_t QSPIC_CTR_KEY_8_11_REG; /*!< (@ 0x0000009C) Key bytes 8 to 11 for the AES-CTR algorithm */
+ __IOM uint32_t QSPIC_CTR_KEY_12_15_REG; /*!< (@ 0x000000A0) Key bytes 12 to 15 for the AES-CTR algorithm */
+ __IOM uint32_t QSPIC_CTR_KEY_16_19_REG; /*!< (@ 0x000000A4) Key bytes 16 to 19 for the AES-CTR algorithm */
+ __IOM uint32_t QSPIC_CTR_KEY_20_23_REG; /*!< (@ 0x000000A8) Key bytes 20 to 23 for the AES-CTR algorithm */
+ __IOM uint32_t QSPIC_CTR_KEY_24_27_REG; /*!< (@ 0x000000AC) Key bytes 24 to 27 for the AES-CTR algorithm */
+ __IOM uint32_t QSPIC_CTR_KEY_28_31_REG; /*!< (@ 0x000000B0) Key bytes 28 to 31 for the AES-CTR algorithm */
+} QSPIC_Type; /*!< Size = 180 (0xb4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ QSPIC2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief QSPIC2 registers (QSPIC2)
+ */
+
+typedef struct { /*!< (@ 0x34000000) QSPIC2 Structure */
+ __IOM uint32_t QSPIC2_CTRLBUS_REG; /*!< (@ 0x00000000) SPI Bus control register for the Manual mode */
+ __IOM uint32_t QSPIC2_CTRLMODE_REG; /*!< (@ 0x00000004) Mode control register */
+ __IOM uint32_t QSPIC2_RECVDATA_REG; /*!< (@ 0x00000008) Received data for the Manual mode */
+ __IOM uint32_t QSPIC2_BURSTCMDA_REG; /*!< (@ 0x0000000C) The way of reading in Auto mode (command register
+ A) */
+ __IOM uint32_t QSPIC2_BURSTCMDB_REG; /*!< (@ 0x00000010) The way of reading in Auto mode (command register
+ B) */
+ __IOM uint32_t QSPIC2_STATUS_REG; /*!< (@ 0x00000014) The status register of the QSPI controller */
+ __IOM uint32_t QSPIC2_WRITEDATA_REG; /*!< (@ 0x00000018) Write data to SPI Bus for the Manual mode */
+ __IOM uint32_t QSPIC2_READDATA_REG; /*!< (@ 0x0000001C) Read data from SPI Bus for the Manual mode */
+ __IOM uint32_t QSPIC2_DUMMYDATA_REG; /*!< (@ 0x00000020) Send dummy clocks to SPI Bus for the Manual mode */
+ __IOM uint32_t QSPIC2_ERASECTRL_REG; /*!< (@ 0x00000024) Erase control register */
+ __IOM uint32_t QSPIC2_ERASECMDA_REG; /*!< (@ 0x00000028) The way of erasing in Auto mode (command register
+ A) */
+ __IOM uint32_t QSPIC2_ERASECMDB_REG; /*!< (@ 0x0000002C) The way of erasing in Auto mode (command register
+ B) */
+ __IOM uint32_t QSPIC2_BURSTBRK_REG; /*!< (@ 0x00000030) Read break sequence in Auto mode */
+ __IOM uint32_t QSPIC2_STATUSCMD_REG; /*!< (@ 0x00000034) The way of reading the status of external device
+ in Auto mode */
+ __IOM uint32_t QSPIC2_CHCKERASE_REG; /*!< (@ 0x00000038) Check erase progress in Auto mode */
+ __IOM uint32_t QSPIC2_GP_REG; /*!< (@ 0x0000003C) General purpose QSPIC2 register */
+ __IOM uint32_t QSPIC2_AWRITECMD_REG; /*!< (@ 0x00000040) The way of writing in Auto mode when the external
+ device is a serial SRAM */
+ __IOM uint32_t QSPIC2_MEMBLEN_REG; /*!< (@ 0x00000044) External memory burst length configuration */
+} QSPIC2_Type; /*!< Size = 72 (0x48) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RFMON ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief RFMON registers (RFMON)
+ */
+
+typedef struct { /*!< (@ 0x50040600) RFMON Structure */
+ __IOM uint32_t RFMON_CTRL_REG; /*!< (@ 0x00000000) Control register */
+ __IOM uint32_t RFMON_ADDR_REG; /*!< (@ 0x00000004) AHB master start address */
+ __IOM uint32_t RFMON_LEN_REG; /*!< (@ 0x00000008) Data length register */
+ __IOM uint32_t RFMON_STAT_REG; /*!< (@ 0x0000000C) Status register */
+ __IOM uint32_t RFMON_CRV_ADDR_REG; /*!< (@ 0x00000010) AHB master current address */
+ __IOM uint32_t RFMON_CRV_LEN_REG; /*!< (@ 0x00000014) The remaining data to be transferred */
+} RFMON_Type; /*!< Size = 24 (0x18) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RTC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief RTC registers (RTC)
+ */
+
+typedef struct { /*!< (@ 0x50000400) RTC Structure */
+ __IOM uint32_t RTC_CONTROL_REG; /*!< (@ 0x00000000) RTC Control Register */
+ __IOM uint32_t RTC_HOUR_MODE_REG; /*!< (@ 0x00000004) RTC Hour Mode Register */
+ __IOM uint32_t RTC_TIME_REG; /*!< (@ 0x00000008) RTC Time Register */
+ __IOM uint32_t RTC_CALENDAR_REG; /*!< (@ 0x0000000C) RTC Calendar Register */
+ __IOM uint32_t RTC_TIME_ALARM_REG; /*!< (@ 0x00000010) RTC Time Alarm Register */
+ __IOM uint32_t RTC_CALENDAR_ALARM_REG; /*!< (@ 0x00000014) RTC Calendar Alram Register */
+ __IOM uint32_t RTC_ALARM_ENABLE_REG; /*!< (@ 0x00000018) RTC Alarm Enable Register */
+ __IOM uint32_t RTC_EVENT_FLAGS_REG; /*!< (@ 0x0000001C) RTC Event Flags Register */
+ __IOM uint32_t RTC_INTERRUPT_ENABLE_REG; /*!< (@ 0x00000020) RTC Interrupt Enable Register */
+ __IOM uint32_t RTC_INTERRUPT_DISABLE_REG; /*!< (@ 0x00000024) RTC Interrupt Disable Register */
+ __IOM uint32_t RTC_INTERRUPT_MASK_REG; /*!< (@ 0x00000028) RTC Interrupt Mask Register */
+ __IOM uint32_t RTC_STATUS_REG; /*!< (@ 0x0000002C) RTC Status Register */
+ __IOM uint32_t RTC_KEEP_RTC_REG; /*!< (@ 0x00000030) RTC Keep RTC Register */
+ __IM uint32_t RESERVED[19];
+ __IOM uint32_t RTC_EVENT_CTRL_REG; /*!< (@ 0x00000080) RTC Event Control Register */
+ __IOM uint32_t RTC_MOTOR_EVENT_PERIOD_REG; /*!< (@ 0x00000084) RTC Motor Event Period Register */
+ __IOM uint32_t RTC_PDC_EVENT_PERIOD_REG; /*!< (@ 0x00000088) RTC PDC Event Period Register */
+ __IOM uint32_t RTC_PDC_EVENT_CLEAR_REG; /*!< (@ 0x0000008C) RTC PDC Event Clear Register */
+ __IOM uint32_t RTC_MOTOR_EVENT_CNT_REG; /*!< (@ 0x00000090) RTC Motor Event Counter Register */
+ __IOM uint32_t RTC_PDC_EVENT_CNT_REG; /*!< (@ 0x00000094) RTC PDC Event Counter Register */
+} RTC_Type; /*!< Size = 152 (0x98) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SDADC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SDADC registers (SDADC)
+ */
+
+typedef struct { /*!< (@ 0x50020800) SDADC Structure */
+ __IOM uint32_t SDADC_CTRL_REG; /*!< (@ 0x00000000) Sigma Delta ADC Control Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t SDADC_TEST_REG; /*!< (@ 0x00000008) Sigma Delta ADC Test Register */
+ __IOM uint32_t SDADC_GAIN_CORR_REG; /*!< (@ 0x0000000C) Sigma Delta ADC Gain Correction Register */
+ __IOM uint32_t SDADC_OFFS_CORR_REG; /*!< (@ 0x00000010) Sigma Delta ADC Offset Correction Register */
+ __IOM uint32_t SDADC_CLEAR_INT_REG; /*!< (@ 0x00000014) Sigma Delta ADC Clear Interrupt Register */
+ __IOM uint32_t SDADC_RESULT_REG; /*!< (@ 0x00000018) Sigma Delta ADC Result Register */
+} SDADC_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SMOTOR ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SMOTOR registers (SMOTOR)
+ */
+
+typedef struct { /*!< (@ 0x50030E00) SMOTOR Structure */
+ __IOM uint32_t SMOTOR_CTRL_REG; /*!< (@ 0x00000000) Motor control register */
+ __IOM uint32_t PG0_CTRL_REG; /*!< (@ 0x00000004) Pattern generator 0 control register */
+ __IOM uint32_t PG1_CTRL_REG; /*!< (@ 0x00000008) Pattern generator 1 control register */
+ __IOM uint32_t PG2_CTRL_REG; /*!< (@ 0x0000000C) Pattern generator 2 control register */
+ __IOM uint32_t PG3_CTRL_REG; /*!< (@ 0x00000010) Pattern generator 3 control register */
+ __IOM uint32_t PG4_CTRL_REG; /*!< (@ 0x00000014) Pattern generator 4 control register */
+ __IOM uint32_t SMOTOR_TRIGGER_REG; /*!< (@ 0x00000018) Motor controller trigger register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t SMOTOR_CMD_FIFO_REG; /*!< (@ 0x00000020) Motor control command FIFO register */
+ __IOM uint32_t SMOTOR_CMD_READ_PTR_REG; /*!< (@ 0x00000024) Command read pointer register */
+ __IOM uint32_t SMOTOR_CMD_WRITE_PTR_REG; /*!< (@ 0x00000028) Command write pointer register */
+ __IOM uint32_t SMOTOR_STATUS_REG; /*!< (@ 0x0000002C) Motor controller status register */
+ __IOM uint32_t SMOTOR_IRQ_CLEAR_REG; /*!< (@ 0x00000030) Motor control IRQ clear register */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t WAVETABLE_BASE; /*!< (@ 0x00000040) Base address of the wavetable */
+ __IM uint32_t RESERVED2[15];
+ __IOM uint32_t CMD_TABLE_BASE; /*!< (@ 0x00000080) Base address of the command table */
+} SMOTOR_Type; /*!< Size = 132 (0x84) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SNC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SNC registers (SNC)
+ */
+
+typedef struct { /*!< (@ 0x50020C00) SNC Structure */
+ __IOM uint32_t SNC_CTRL_REG; /*!< (@ 0x00000000) Sensor Node Control Register */
+ __IOM uint32_t SNC_STATUS_REG; /*!< (@ 0x00000004) Sensor Node Status Register */
+ __IOM uint32_t SNC_LP_TIMER_REG; /*!< (@ 0x00000008) Sensor Node Low-Power Timer Register */
+ __IOM uint32_t SNC_PC_REG; /*!< (@ 0x0000000C) Sensor Node Program Counter */
+ __IOM uint32_t SNC_R1_REG; /*!< (@ 0x00000010) Sensor Node core - Operand 1 Register */
+ __IOM uint32_t SNC_R2_REG; /*!< (@ 0x00000014) Sensor Node core - Operand 2 Register */
+ __IOM uint32_t SNC_TMP1_REG; /*!< (@ 0x00000018) Sensor Node core - Temporary Register 1 */
+ __IOM uint32_t SNC_TMP2_REG; /*!< (@ 0x0000001C) Sensor Node core - Temporary Register 2 */
+} SNC_Type; /*!< Size = 32 (0x20) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPI ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SPI registers (SPI)
+ */
+
+typedef struct { /*!< (@ 0x50020300) SPI Structure */
+ __IOM uint32_t SPI_CTRL_REG; /*!< (@ 0x00000000) SPI control register 0 */
+ __IOM uint32_t SPI_RX_TX_REG; /*!< (@ 0x00000004) SPI RX/TX register0 */
+ __IOM uint32_t SPI_CLEAR_INT_REG; /*!< (@ 0x00000008) SPI clear interrupt register */
+} SPI_Type; /*!< Size = 12 (0xc) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPI2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SPI2 registers (SPI2)
+ */
+
+typedef struct { /*!< (@ 0x50020400) SPI2 Structure */
+ __IOM uint32_t SPI2_CTRL_REG; /*!< (@ 0x00000000) SPI control register 0 */
+ __IOM uint32_t SPI2_RX_TX_REG; /*!< (@ 0x00000004) SPI RX/TX register0 */
+ __IOM uint32_t SPI2_CLEAR_INT_REG; /*!< (@ 0x00000008) SPI clear interrupt register */
+} SPI2_Type; /*!< Size = 12 (0xc) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SYS_WDOG ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SYS_WDOG registers (SYS_WDOG)
+ */
+
+typedef struct { /*!< (@ 0x50000700) SYS_WDOG Structure */
+ __IOM uint32_t WATCHDOG_REG; /*!< (@ 0x00000000) Watchdog timer register. */
+ __IOM uint32_t WATCHDOG_CTRL_REG; /*!< (@ 0x00000004) Watchdog control register. */
+} SYS_WDOG_Type; /*!< Size = 8 (0x8) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TIMER ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TIMER registers (TIMER)
+ */
+
+typedef struct { /*!< (@ 0x50010200) TIMER Structure */
+ __IOM uint32_t TIMER_CTRL_REG; /*!< (@ 0x00000000) Timer control register */
+ __IOM uint32_t TIMER_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer counter value */
+ __IOM uint32_t TIMER_STATUS_REG; /*!< (@ 0x00000008) Timer status register */
+ __IOM uint32_t TIMER_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */
+ __IOM uint32_t TIMER_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */
+ __IOM uint32_t TIMER_RELOAD_REG; /*!< (@ 0x00000014) Timer reload value and Delay in shot mode */
+ __IOM uint32_t TIMER_SHOTWIDTH_REG; /*!< (@ 0x00000018) Timer Shot duration in shot mode */
+ __IOM uint32_t TIMER_PRESCALER_REG; /*!< (@ 0x0000001C) Timer prescaler value */
+ __IOM uint32_t TIMER_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer value for event on GPIO1 */
+ __IOM uint32_t TIMER_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer value for event on GPIO2 */
+ __IOM uint32_t TIMER_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer prescaler counter valuew */
+ __IOM uint32_t TIMER_PWM_FREQ_REG; /*!< (@ 0x0000002C) Timer pwm frequency register */
+ __IOM uint32_t TIMER_PWM_DC_REG; /*!< (@ 0x00000030) Timer pwm dc register */
+ __IOM uint32_t TIMER_GPIO3_CONF_REG; /*!< (@ 0x00000034) Timer gpio3 selection */
+ __IOM uint32_t TIMER_GPIO4_CONF_REG; /*!< (@ 0x00000038) Timer gpio4 selection */
+ __IOM uint32_t TIMER_CAPTURE_GPIO3_REG; /*!< (@ 0x0000003C) Timer value for event on GPIO1 */
+ __IOM uint32_t TIMER_CAPTURE_GPIO4_REG; /*!< (@ 0x00000040) Timer value for event on GPIO1 */
+ __IOM uint32_t TIMER_CLEAR_GPIO_EVENT_REG; /*!< (@ 0x00000044) Timer clear gpio event register */
+ __IOM uint32_t TIMER_CLEAR_IRQ_REG; /*!< (@ 0x00000048) Timer clear interrupt */
+} TIMER_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TIMER2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TIMER2 registers (TIMER2)
+ */
+
+typedef struct { /*!< (@ 0x50010300) TIMER2 Structure */
+ __IOM uint32_t TIMER2_CTRL_REG; /*!< (@ 0x00000000) Timer control register */
+ __IOM uint32_t TIMER2_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer counter value */
+ __IOM uint32_t TIMER2_STATUS_REG; /*!< (@ 0x00000008) Timer status register */
+ __IOM uint32_t TIMER2_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */
+ __IOM uint32_t TIMER2_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */
+ __IOM uint32_t TIMER2_RELOAD_REG; /*!< (@ 0x00000014) Timer reload value and Delay in shot mode */
+ __IOM uint32_t TIMER2_SHOTWIDTH_REG; /*!< (@ 0x00000018) Timer Shot duration in shot mode */
+ __IOM uint32_t TIMER2_PRESCALER_REG; /*!< (@ 0x0000001C) Timer prescaler value */
+ __IOM uint32_t TIMER2_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer value for event on GPIO1 */
+ __IOM uint32_t TIMER2_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer value for event on GPIO2 */
+ __IOM uint32_t TIMER2_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer prescaler counter valuew */
+ __IOM uint32_t TIMER2_PWM_FREQ_REG; /*!< (@ 0x0000002C) Timer pwm frequency register */
+ __IOM uint32_t TIMER2_PWM_DC_REG; /*!< (@ 0x00000030) Timer pwm dc register */
+ __IOM uint32_t TIMER2_CLEAR_IRQ_REG; /*!< (@ 0x00000034) Timer clear interrupt */
+} TIMER2_Type; /*!< Size = 56 (0x38) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TIMER3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TIMER3 registers (TIMER3)
+ */
+
+typedef struct { /*!< (@ 0x50040A00) TIMER3 Structure */
+ __IOM uint32_t TIMER3_CTRL_REG; /*!< (@ 0x00000000) Timer control register */
+ __IOM uint32_t TIMER3_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer counter value */
+ __IOM uint32_t TIMER3_STATUS_REG; /*!< (@ 0x00000008) Timer status register */
+ __IOM uint32_t TIMER3_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */
+ __IOM uint32_t TIMER3_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */
+ __IOM uint32_t TIMER3_RELOAD_REG; /*!< (@ 0x00000014) Timer reload value and Delay in shot mode */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t TIMER3_PRESCALER_REG; /*!< (@ 0x0000001C) Timer prescaler value */
+ __IOM uint32_t TIMER3_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer value for event on GPIO1 */
+ __IOM uint32_t TIMER3_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer value for event on GPIO2 */
+ __IOM uint32_t TIMER3_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer prescaler counter valuew */
+ __IOM uint32_t TIMER3_PWM_FREQ_REG; /*!< (@ 0x0000002C) Timer pwm frequency register */
+ __IOM uint32_t TIMER3_PWM_DC_REG; /*!< (@ 0x00000030) Timer pwm dc register */
+ __IOM uint32_t TIMER3_CLEAR_IRQ_REG; /*!< (@ 0x00000034) Timer clear interrupt */
+} TIMER3_Type; /*!< Size = 56 (0x38) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TIMER4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TIMER4 registers (TIMER4)
+ */
+
+typedef struct { /*!< (@ 0x50040B00) TIMER4 Structure */
+ __IOM uint32_t TIMER4_CTRL_REG; /*!< (@ 0x00000000) Timer control register */
+ __IOM uint32_t TIMER4_TIMER_VAL_REG; /*!< (@ 0x00000004) Timer counter value */
+ __IOM uint32_t TIMER4_STATUS_REG; /*!< (@ 0x00000008) Timer status register */
+ __IOM uint32_t TIMER4_GPIO1_CONF_REG; /*!< (@ 0x0000000C) Timer gpio1 selection */
+ __IOM uint32_t TIMER4_GPIO2_CONF_REG; /*!< (@ 0x00000010) Timer gpio2 selection */
+ __IOM uint32_t TIMER4_RELOAD_REG; /*!< (@ 0x00000014) Timer reload value and Delay in shot mode */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t TIMER4_PRESCALER_REG; /*!< (@ 0x0000001C) Timer prescaler value */
+ __IOM uint32_t TIMER4_CAPTURE_GPIO1_REG; /*!< (@ 0x00000020) Timer value for event on GPIO1 */
+ __IOM uint32_t TIMER4_CAPTURE_GPIO2_REG; /*!< (@ 0x00000024) Timer value for event on GPIO2 */
+ __IOM uint32_t TIMER4_PRESCALER_VAL_REG; /*!< (@ 0x00000028) Timer prescaler counter valuew */
+ __IOM uint32_t TIMER4_PWM_FREQ_REG; /*!< (@ 0x0000002C) Timer pwm frequency register */
+ __IOM uint32_t TIMER4_PWM_DC_REG; /*!< (@ 0x00000030) Timer pwm dc register */
+ __IOM uint32_t TIMER4_CLEAR_IRQ_REG; /*!< (@ 0x00000034) Timer clear interrupt */
+} TIMER4_Type; /*!< Size = 56 (0x38) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TRNG ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TRNG registers (TRNG)
+ */
+
+typedef struct { /*!< (@ 0x50040C00) TRNG Structure */
+ __IOM uint32_t TRNG_CTRL_REG; /*!< (@ 0x00000000) TRNG control register */
+ __IOM uint32_t TRNG_FIFOLVL_REG; /*!< (@ 0x00000004) TRNG FIFO level register */
+ __IOM uint32_t TRNG_VER_REG; /*!< (@ 0x00000008) TRNG Version register */
+} TRNG_Type; /*!< Size = 12 (0xc) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART registers (UART)
+ */
+
+typedef struct { /*!< (@ 0x50020000) UART Structure */
+ __IOM uint32_t UART_RBR_THR_DLL_REG; /*!< (@ 0x00000000) Receive Buffer Register */
+ __IOM uint32_t UART_IER_DLH_REG; /*!< (@ 0x00000004) Interrupt Enable Register */
+ __IOM uint32_t UART_IIR_FCR_REG; /*!< (@ 0x00000008) Interrupt Identification Register/FIFO Control
+ Register */
+ __IOM uint32_t UART_LCR_REG; /*!< (@ 0x0000000C) Line Control Register */
+ __IOM uint32_t UART_MCR_REG; /*!< (@ 0x00000010) Modem Control Register */
+ __IOM uint32_t UART_LSR_REG; /*!< (@ 0x00000014) Line Status Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t UART_SCR_REG; /*!< (@ 0x0000001C) Scratchpad Register */
+ __IM uint32_t RESERVED1[4];
+ __IOM uint32_t UART_SRBR_STHR0_REG; /*!< (@ 0x00000030) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR1_REG; /*!< (@ 0x00000034) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR2_REG; /*!< (@ 0x00000038) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR3_REG; /*!< (@ 0x0000003C) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR4_REG; /*!< (@ 0x00000040) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR5_REG; /*!< (@ 0x00000044) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR6_REG; /*!< (@ 0x00000048) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR7_REG; /*!< (@ 0x0000004C) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR8_REG; /*!< (@ 0x00000050) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR9_REG; /*!< (@ 0x00000054) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR10_REG; /*!< (@ 0x00000058) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR11_REG; /*!< (@ 0x0000005C) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR12_REG; /*!< (@ 0x00000060) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR13_REG; /*!< (@ 0x00000064) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR14_REG; /*!< (@ 0x00000068) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART_SRBR_STHR15_REG; /*!< (@ 0x0000006C) Shadow Receive/Transmit Buffer Register */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t UART_USR_REG; /*!< (@ 0x0000007C) UART Status register. */
+ __IOM uint32_t UART_TFL_REG; /*!< (@ 0x00000080) Transmit FIFO Level */
+ __IOM uint32_t UART_RFL_REG; /*!< (@ 0x00000084) Receive FIFO Level. */
+ __IOM uint32_t UART_SRR_REG; /*!< (@ 0x00000088) Software Reset Register. */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t UART_SBCR_REG; /*!< (@ 0x00000090) Shadow Break Control Register */
+ __IOM uint32_t UART_SDMAM_REG; /*!< (@ 0x00000094) Shadow DMA Mode */
+ __IOM uint32_t UART_SFE_REG; /*!< (@ 0x00000098) Shadow FIFO Enable */
+ __IOM uint32_t UART_SRT_REG; /*!< (@ 0x0000009C) Shadow RCVR Trigger */
+ __IOM uint32_t UART_STET_REG; /*!< (@ 0x000000A0) Shadow TX Empty Trigger */
+ __IOM uint32_t UART_HTX_REG; /*!< (@ 0x000000A4) Halt TX */
+ __IOM uint32_t UART_DMASA_REG; /*!< (@ 0x000000A8) DMA Software Acknowledge */
+ __IM uint32_t RESERVED4[5];
+ __IOM uint32_t UART_DLF_REG; /*!< (@ 0x000000C0) Divisor Latch Fraction Register */
+ __IM uint32_t RESERVED5[13];
+ __IOM uint32_t UART_UCV_REG; /*!< (@ 0x000000F8) Component Version */
+ __IOM uint32_t UART_CTR_REG; /*!< (@ 0x000000FC) Component Type Register */
+} UART_Type; /*!< Size = 256 (0x100) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART2 registers (UART2)
+ */
+
+typedef struct { /*!< (@ 0x50020100) UART2 Structure */
+ __IOM uint32_t UART2_RBR_THR_DLL_REG; /*!< (@ 0x00000000) Receive Buffer Register */
+ __IOM uint32_t UART2_IER_DLH_REG; /*!< (@ 0x00000004) Interrupt Enable Register */
+ __IOM uint32_t UART2_IIR_FCR_REG; /*!< (@ 0x00000008) Interrupt Identification Register/FIFO Control
+ Register */
+ __IOM uint32_t UART2_LCR_REG; /*!< (@ 0x0000000C) Line Control Register */
+ __IOM uint32_t UART2_MCR_REG; /*!< (@ 0x00000010) Modem Control Register */
+ __IOM uint32_t UART2_LSR_REG; /*!< (@ 0x00000014) Line Status Register */
+ __IOM uint32_t UART2_MSR_REG; /*!< (@ 0x00000018) Modem Status Register */
+ __IOM uint32_t UART2_SCR_REG; /*!< (@ 0x0000001C) Scratchpad Register */
+ __IM uint32_t RESERVED[4];
+ __IOM uint32_t UART2_SRBR_STHR0_REG; /*!< (@ 0x00000030) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR1_REG; /*!< (@ 0x00000034) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR2_REG; /*!< (@ 0x00000038) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR3_REG; /*!< (@ 0x0000003C) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR4_REG; /*!< (@ 0x00000040) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR5_REG; /*!< (@ 0x00000044) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR6_REG; /*!< (@ 0x00000048) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR7_REG; /*!< (@ 0x0000004C) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR8_REG; /*!< (@ 0x00000050) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR9_REG; /*!< (@ 0x00000054) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR10_REG; /*!< (@ 0x00000058) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR11_REG; /*!< (@ 0x0000005C) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR12_REG; /*!< (@ 0x00000060) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR13_REG; /*!< (@ 0x00000064) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR14_REG; /*!< (@ 0x00000068) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART2_SRBR_STHR15_REG; /*!< (@ 0x0000006C) Shadow Receive/Transmit Buffer Register */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t UART2_USR_REG; /*!< (@ 0x0000007C) UART Status register. */
+ __IOM uint32_t UART2_TFL_REG; /*!< (@ 0x00000080) Transmit FIFO Level */
+ __IOM uint32_t UART2_RFL_REG; /*!< (@ 0x00000084) Receive FIFO Level. */
+ __IOM uint32_t UART2_SRR_REG; /*!< (@ 0x00000088) Software Reset Register. */
+ __IOM uint32_t UART2_SRTS_REG; /*!< (@ 0x0000008C) Shadow Request to Send */
+ __IOM uint32_t UART2_SBCR_REG; /*!< (@ 0x00000090) Shadow Break Control Register */
+ __IOM uint32_t UART2_SDMAM_REG; /*!< (@ 0x00000094) Shadow DMA Mode */
+ __IOM uint32_t UART2_SFE_REG; /*!< (@ 0x00000098) Shadow FIFO Enable */
+ __IOM uint32_t UART2_SRT_REG; /*!< (@ 0x0000009C) Shadow RCVR Trigger */
+ __IOM uint32_t UART2_STET_REG; /*!< (@ 0x000000A0) Shadow TX Empty Trigger */
+ __IOM uint32_t UART2_HTX_REG; /*!< (@ 0x000000A4) Halt TX */
+ __IOM uint32_t UART2_DMASA_REG; /*!< (@ 0x000000A8) DMA Software Acknowledge */
+ __IM uint32_t RESERVED2[5];
+ __IOM uint32_t UART2_DLF_REG; /*!< (@ 0x000000C0) Divisor Latch Fraction Register */
+ __IOM uint32_t UART2_RAR_REG; /*!< (@ 0x000000C4) Receive Address Register */
+ __IOM uint32_t UART2_TAR_REG; /*!< (@ 0x000000C8) Transmit Address Register */
+ __IOM uint32_t UART2_LCR_EXT; /*!< (@ 0x000000CC) Line Extended Control Register */
+ __IM uint32_t RESERVED3[10];
+ __IOM uint32_t UART2_UCV_REG; /*!< (@ 0x000000F8) Component Version */
+ __IOM uint32_t UART2_CTR_REG; /*!< (@ 0x000000FC) Component Type Register */
+} UART2_Type; /*!< Size = 256 (0x100) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART3 registers (UART3)
+ */
+
+typedef struct { /*!< (@ 0x50020200) UART3 Structure */
+ __IOM uint32_t UART3_RBR_THR_DLL_REG; /*!< (@ 0x00000000) Receive Buffer Register */
+ __IOM uint32_t UART3_IER_DLH_REG; /*!< (@ 0x00000004) Interrupt Enable Register */
+ __IOM uint32_t UART3_IIR_FCR_REG; /*!< (@ 0x00000008) Interrupt Identification Register/FIFO Control
+ Register */
+ __IOM uint32_t UART3_LCR_REG; /*!< (@ 0x0000000C) Line Control Register */
+ __IOM uint32_t UART3_MCR_REG; /*!< (@ 0x00000010) Modem Control Register */
+ __IOM uint32_t UART3_LSR_REG; /*!< (@ 0x00000014) Line Status Register */
+ __IOM uint32_t UART3_MSR_REG; /*!< (@ 0x00000018) Modem Status Register */
+ __IOM uint32_t UART3_CONFIG_REG; /*!< (@ 0x0000001C) ISO7816 Config Register */
+ __IM uint32_t RESERVED[4];
+ __IOM uint32_t UART3_SRBR_STHR0_REG; /*!< (@ 0x00000030) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR1_REG; /*!< (@ 0x00000034) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR2_REG; /*!< (@ 0x00000038) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR3_REG; /*!< (@ 0x0000003C) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR4_REG; /*!< (@ 0x00000040) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR5_REG; /*!< (@ 0x00000044) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR6_REG; /*!< (@ 0x00000048) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR7_REG; /*!< (@ 0x0000004C) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR8_REG; /*!< (@ 0x00000050) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR9_REG; /*!< (@ 0x00000054) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR10_REG; /*!< (@ 0x00000058) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR11_REG; /*!< (@ 0x0000005C) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR12_REG; /*!< (@ 0x00000060) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR13_REG; /*!< (@ 0x00000064) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR14_REG; /*!< (@ 0x00000068) Shadow Receive/Transmit Buffer Register */
+ __IOM uint32_t UART3_SRBR_STHR15_REG; /*!< (@ 0x0000006C) Shadow Receive/Transmit Buffer Register */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t UART3_USR_REG; /*!< (@ 0x0000007C) UART Status register. */
+ __IOM uint32_t UART3_TFL_REG; /*!< (@ 0x00000080) Transmit FIFO Level */
+ __IOM uint32_t UART3_RFL_REG; /*!< (@ 0x00000084) Receive FIFO Level. */
+ __IOM uint32_t UART3_SRR_REG; /*!< (@ 0x00000088) Software Reset Register. */
+ __IOM uint32_t UART3_SRTS_REG; /*!< (@ 0x0000008C) Shadow Request to Send */
+ __IOM uint32_t UART3_SBCR_REG; /*!< (@ 0x00000090) Shadow Break Control Register */
+ __IOM uint32_t UART3_SDMAM_REG; /*!< (@ 0x00000094) Shadow DMA Mode */
+ __IOM uint32_t UART3_SFE_REG; /*!< (@ 0x00000098) Shadow FIFO Enable */
+ __IOM uint32_t UART3_SRT_REG; /*!< (@ 0x0000009C) Shadow RCVR Trigger */
+ __IOM uint32_t UART3_STET_REG; /*!< (@ 0x000000A0) Shadow TX Empty Trigger */
+ __IOM uint32_t UART3_HTX_REG; /*!< (@ 0x000000A4) Halt TX */
+ __IOM uint32_t UART3_DMASA_REG; /*!< (@ 0x000000A8) DMA Software Acknowledge */
+ __IM uint32_t RESERVED2[5];
+ __IOM uint32_t UART3_DLF_REG; /*!< (@ 0x000000C0) Divisor Latch Fraction Register */
+ __IOM uint32_t UART3_RAR_REG; /*!< (@ 0x000000C4) Receive Address Register */
+ __IOM uint32_t UART3_TAR_REG; /*!< (@ 0x000000C8) Transmit Address Register */
+ __IOM uint32_t UART3_LCR_EXT; /*!< (@ 0x000000CC) Line Extended Control Register */
+ __IM uint32_t RESERVED3[4];
+ __IOM uint32_t UART3_CTRL_REG; /*!< (@ 0x000000E0) ISO7816 Control Register */
+ __IOM uint32_t UART3_TIMER_REG; /*!< (@ 0x000000E4) ISO7816 Timer Register */
+ __IOM uint32_t UART3_ERR_CTRL_REG; /*!< (@ 0x000000E8) ISO7816 Error Signal Control Register */
+ __IOM uint32_t UART3_IRQ_STATUS_REG; /*!< (@ 0x000000EC) ISO7816 Interrupt Status Register */
+ __IM uint32_t RESERVED4[2];
+ __IOM uint32_t UART3_UCV_REG; /*!< (@ 0x000000F8) Component Version */
+ __IOM uint32_t UART3_CTR_REG; /*!< (@ 0x000000FC) Component Type Register */
+} UART3_Type; /*!< Size = 256 (0x100) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ USB ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief USB registers (USB)
+ */
+
+typedef struct { /*!< (@ 0x50040000) USB Structure */
+ __IOM uint32_t USB_MCTRL_REG; /*!< (@ 0x00000000) Main Control Register) */
+ __IOM uint32_t USB_XCVDIAG_REG; /*!< (@ 0x00000004) Transceiver diagnostic Register (for test purpose
+ only) */
+ __IOM uint32_t USB_TCR_REG; /*!< (@ 0x00000008) Transceiver configuration Register */
+ __IOM uint32_t USB_UTR_REG; /*!< (@ 0x0000000C) USB test Register (for test purpose only) */
+ __IOM uint32_t USB_FAR_REG; /*!< (@ 0x00000010) Function Address Register */
+ __IOM uint32_t USB_NFSR_REG; /*!< (@ 0x00000014) Node Functional State Register */
+ __IOM uint32_t USB_MAEV_REG; /*!< (@ 0x00000018) Main Event Register */
+ __IOM uint32_t USB_MAMSK_REG; /*!< (@ 0x0000001C) Main Mask Register */
+ __IOM uint32_t USB_ALTEV_REG; /*!< (@ 0x00000020) Alternate Event Register */
+ __IOM uint32_t USB_ALTMSK_REG; /*!< (@ 0x00000024) Alternate Mask Register */
+ __IOM uint32_t USB_TXEV_REG; /*!< (@ 0x00000028) Transmit Event Register */
+ __IOM uint32_t USB_TXMSK_REG; /*!< (@ 0x0000002C) Transmit Mask Register */
+ __IOM uint32_t USB_RXEV_REG; /*!< (@ 0x00000030) Receive Event Register */
+ __IOM uint32_t USB_RXMSK_REG; /*!< (@ 0x00000034) Receive Mask Register */
+ __IOM uint32_t USB_NAKEV_REG; /*!< (@ 0x00000038) NAK Event Register */
+ __IOM uint32_t USB_NAKMSK_REG; /*!< (@ 0x0000003C) NAK Mask Register */
+ __IOM uint32_t USB_FWEV_REG; /*!< (@ 0x00000040) FIFO Warning Event Register */
+ __IOM uint32_t USB_FWMSK_REG; /*!< (@ 0x00000044) FIFO Warning Mask Register */
+ __IOM uint32_t USB_FNH_REG; /*!< (@ 0x00000048) Frame Number High Byte Register */
+ __IOM uint32_t USB_FNL_REG; /*!< (@ 0x0000004C) Frame Number Low Byte Register */
+ __IM uint32_t RESERVED[11];
+ __IOM uint32_t USB_UX20CDR_REG; /*!< (@ 0x0000007C) Transceiver 2.0 Configuration and Diagnostics
+ Register(for test purpose only) */
+ __IOM uint32_t USB_EPC0_REG; /*!< (@ 0x00000080) Endpoint Control 0 Register */
+ __IOM uint32_t USB_TXD0_REG; /*!< (@ 0x00000084) Transmit Data 0 Register */
+ __IOM uint32_t USB_TXS0_REG; /*!< (@ 0x00000088) Transmit Status 0 Register */
+ __IOM uint32_t USB_TXC0_REG; /*!< (@ 0x0000008C) Transmit command 0 Register */
+ __IOM uint32_t USB_EP0_NAK_REG; /*!< (@ 0x00000090) EP0 INNAK and OUTNAK Register */
+ __IOM uint32_t USB_RXD0_REG; /*!< (@ 0x00000094) Receive Data 0 Register */
+ __IOM uint32_t USB_RXS0_REG; /*!< (@ 0x00000098) Receive Status 0 Register */
+ __IOM uint32_t USB_RXC0_REG; /*!< (@ 0x0000009C) Receive Command 0 Register */
+ __IOM uint32_t USB_EPC1_REG; /*!< (@ 0x000000A0) Endpoint Control Register 1 */
+ __IOM uint32_t USB_TXD1_REG; /*!< (@ 0x000000A4) Transmit Data Register 1 */
+ __IOM uint32_t USB_TXS1_REG; /*!< (@ 0x000000A8) Transmit Status Register 1 */
+ __IOM uint32_t USB_TXC1_REG; /*!< (@ 0x000000AC) Transmit Command Register 1 */
+ __IOM uint32_t USB_EPC2_REG; /*!< (@ 0x000000B0) Endpoint Control Register 2 */
+ __IOM uint32_t USB_RXD1_REG; /*!< (@ 0x000000B4) Receive Data Register,1 */
+ __IOM uint32_t USB_RXS1_REG; /*!< (@ 0x000000B8) Receive Status Register 1 */
+ __IOM uint32_t USB_RXC1_REG; /*!< (@ 0x000000BC) Receive Command Register 1 */
+ __IOM uint32_t USB_EPC3_REG; /*!< (@ 0x000000C0) Endpoint Control Register 3 */
+ __IOM uint32_t USB_TXD2_REG; /*!< (@ 0x000000C4) Transmit Data Register 2 */
+ __IOM uint32_t USB_TXS2_REG; /*!< (@ 0x000000C8) Transmit Status Register 2 */
+ __IOM uint32_t USB_TXC2_REG; /*!< (@ 0x000000CC) Transmit Command Register 2 */
+ __IOM uint32_t USB_EPC4_REG; /*!< (@ 0x000000D0) Endpoint Control Register 4 */
+ __IOM uint32_t USB_RXD2_REG; /*!< (@ 0x000000D4) Receive Data Register 2 */
+ __IOM uint32_t USB_RXS2_REG; /*!< (@ 0x000000D8) Receive Status Register 2 */
+ __IOM uint32_t USB_RXC2_REG; /*!< (@ 0x000000DC) Receive Command Register 2 */
+ __IOM uint32_t USB_EPC5_REG; /*!< (@ 0x000000E0) Endpoint Control Register 5 */
+ __IOM uint32_t USB_TXD3_REG; /*!< (@ 0x000000E4) Transmit Data Register 3 */
+ __IOM uint32_t USB_TXS3_REG; /*!< (@ 0x000000E8) Transmit Status Register 3 */
+ __IOM uint32_t USB_TXC3_REG; /*!< (@ 0x000000EC) Transmit Command Register 3 */
+ __IOM uint32_t USB_EPC6_REG; /*!< (@ 0x000000F0) Endpoint Control Register 6 */
+ __IOM uint32_t USB_RXD3_REG; /*!< (@ 0x000000F4) Receive Data Register 3 */
+ __IOM uint32_t USB_RXS3_REG; /*!< (@ 0x000000F8) Receive Status Register 3 */
+ __IOM uint32_t USB_RXC3_REG; /*!< (@ 0x000000FC) Receive Command Register 3 */
+ __IM uint32_t RESERVED1[40];
+ __IOM uint32_t USB_DMA_CTRL_REG; /*!< (@ 0x000001A0) USB DMA control register */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t USB_CHARGER_CTRL_REG; /*!< (@ 0x000001A8) USB Charger Control Register */
+ __IOM uint32_t USB_CHARGER_STAT_REG; /*!< (@ 0x000001AC) USB Charger Status Register */
+} USB_Type; /*!< Size = 432 (0x1b0) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ WAKEUP ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief WAKEUP registers (WAKEUP)
+ */
+
+typedef struct { /*!< (@ 0x50000100) WAKEUP Structure */
+ __IOM uint32_t WKUP_CTRL_REG; /*!< (@ 0x00000000) Control register for the wakeup counter */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t WKUP_RESET_IRQ_REG; /*!< (@ 0x00000008) Reset wakeup interrupt */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t WKUP_SELECT_P0_REG; /*!< (@ 0x00000014) select which inputs from P0 port can trigger
+ wkup counter */
+ __IOM uint32_t WKUP_SELECT_P1_REG; /*!< (@ 0x00000018) select which inputs from P1 port can trigger
+ wkup counter */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t WKUP_POL_P0_REG; /*!< (@ 0x00000028) select the sesitivity polarity for each P0 input */
+ __IOM uint32_t WKUP_POL_P1_REG; /*!< (@ 0x0000002C) select the sesitivity polarity for each P1 input */
+ __IM uint32_t RESERVED3[3];
+ __IOM uint32_t WKUP_STATUS_P0_REG; /*!< (@ 0x0000003C) Event status register for P0 */
+ __IOM uint32_t WKUP_STATUS_P1_REG; /*!< (@ 0x00000040) Event status register for P1 */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t WKUP_CLEAR_P0_REG; /*!< (@ 0x00000048) Clear event register for P0 */
+ __IOM uint32_t WKUP_CLEAR_P1_REG; /*!< (@ 0x0000004C) Clear event register for P1 */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t WKUP_SEL_GPIO_P0_REG; /*!< (@ 0x00000054) select which inputs from P0 port can trigger
+ interrupt */
+ __IOM uint32_t WKUP_SEL_GPIO_P1_REG; /*!< (@ 0x00000058) select which inputs from P1 port can trigger
+ interrupt */
+} WAKEUP_Type; /*!< Size = 92 (0x5c) */
+
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+
+#define AES_HASH_BASE 0x30040000UL
+#define ANAMISC_BIF_BASE 0x50030B00UL
+#define APU_BASE 0x50030600UL
+#define CACHE_BASE 0x100C0000UL
+#define CHARGER_BASE 0x50040400UL
+#define CHIP_VERSION_BASE 0x50040200UL
+#define CRG_COM_BASE 0x50020900UL
+#define CRG_PER_BASE 0x50030C00UL
+#define CRG_SYS_BASE 0x50040500UL
+#define CRG_TOP_BASE 0x50000000UL
+#define CRG_XTAL_BASE 0x50010000UL
+#define DCDC_BASE 0x50000300UL
+#define DMA_BASE 0x50040800UL
+#define DW_BASE 0x30020000UL
+#define GPADC_BASE 0x50030900UL
+#define GPIO_BASE 0x50020A00UL
+#define GPREG_BASE 0x50040300UL
+#define I2C_BASE 0x50020600UL
+#define I2C2_BASE 0x50020700UL
+#define LCDC_BASE 0x30030000UL
+#define LRA_BASE 0x50030A00UL
+#define MEMCTRL_BASE 0x50050000UL
+#define OTPC_BASE 0x30070000UL
+#define PDC_BASE 0x50000200UL
+#define PWMLED_BASE 0x50030500UL
+#define QSPIC_BASE 0x38000000UL
+#define QSPIC2_BASE 0x34000000UL
+#define RFMON_BASE 0x50040600UL
+#define RTC_BASE 0x50000400UL
+#define SDADC_BASE 0x50020800UL
+#define SMOTOR_BASE 0x50030E00UL
+#define SNC_BASE 0x50020C00UL
+#define SPI_BASE 0x50020300UL
+#define SPI2_BASE 0x50020400UL
+#define SYS_WDOG_BASE 0x50000700UL
+#define TIMER_BASE 0x50010200UL
+#define TIMER2_BASE 0x50010300UL
+#define TIMER3_BASE 0x50040A00UL
+#define TIMER4_BASE 0x50040B00UL
+#define TRNG_BASE 0x50040C00UL
+#define UART_BASE 0x50020000UL
+#define UART2_BASE 0x50020100UL
+#define UART3_BASE 0x50020200UL
+#define USB_BASE 0x50040000UL
+#define WAKEUP_BASE 0x50000100UL
+
+
+/* =========================================================================================================================== */
+/* ================ Peripheral declaration ================ */
+/* =========================================================================================================================== */
+
+
+#define AES_HASH ((AES_HASH_Type*) AES_HASH_BASE)
+#define ANAMISC_BIF ((ANAMISC_BIF_Type*) ANAMISC_BIF_BASE)
+#define APU ((APU_Type*) APU_BASE)
+#define CACHE ((CACHE_Type*) CACHE_BASE)
+#define CHARGER ((CHARGER_Type*) CHARGER_BASE)
+#define CHIP_VERSION ((CHIP_VERSION_Type*) CHIP_VERSION_BASE)
+#define CRG_COM ((CRG_COM_Type*) CRG_COM_BASE)
+#define CRG_PER ((CRG_PER_Type*) CRG_PER_BASE)
+#define CRG_SYS ((CRG_SYS_Type*) CRG_SYS_BASE)
+#define CRG_TOP ((CRG_TOP_Type*) CRG_TOP_BASE)
+#define CRG_XTAL ((CRG_XTAL_Type*) CRG_XTAL_BASE)
+#define DCDC ((DCDC_Type*) DCDC_BASE)
+#define DMA ((DMA_Type*) DMA_BASE)
+#define DW ((DW_Type*) DW_BASE)
+#define GPADC ((GPADC_Type*) GPADC_BASE)
+#define GPIO ((GPIO_Type*) GPIO_BASE)
+#define GPREG ((GPREG_Type*) GPREG_BASE)
+#define I2C ((I2C_Type*) I2C_BASE)
+#define I2C2 ((I2C2_Type*) I2C2_BASE)
+#define LCDC ((LCDC_Type*) LCDC_BASE)
+#define LRA ((LRA_Type*) LRA_BASE)
+#define MEMCTRL ((MEMCTRL_Type*) MEMCTRL_BASE)
+#define OTPC ((OTPC_Type*) OTPC_BASE)
+#define PDC ((PDC_Type*) PDC_BASE)
+#define PWMLED ((PWMLED_Type*) PWMLED_BASE)
+#define QSPIC ((QSPIC_Type*) QSPIC_BASE)
+#define QSPIC2 ((QSPIC2_Type*) QSPIC2_BASE)
+#define RFMON ((RFMON_Type*) RFMON_BASE)
+#define RTC ((RTC_Type*) RTC_BASE)
+#define SDADC ((SDADC_Type*) SDADC_BASE)
+#define SMOTOR ((SMOTOR_Type*) SMOTOR_BASE)
+#define SNC ((SNC_Type*) SNC_BASE)
+#define SPI ((SPI_Type*) SPI_BASE)
+#define SPI2 ((SPI2_Type*) SPI2_BASE)
+#define SYS_WDOG ((SYS_WDOG_Type*) SYS_WDOG_BASE)
+#define TIMER ((TIMER_Type*) TIMER_BASE)
+#define TIMER2 ((TIMER2_Type*) TIMER2_BASE)
+#define TIMER3 ((TIMER3_Type*) TIMER3_BASE)
+#define TIMER4 ((TIMER4_Type*) TIMER4_BASE)
+#define TRNG ((TRNG_Type*) TRNG_BASE)
+#define UART ((UART_Type*) UART_BASE)
+#define UART2 ((UART2_Type*) UART2_BASE)
+#define UART3 ((UART3_Type*) UART3_BASE)
+#define USB ((USB_Type*) USB_BASE)
+#define WAKEUP ((WAKEUP_Type*) WAKEUP_BASE)
+
+
+/* =========================================================================================================================== */
+/* ================ Pos/Mask Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup PosMask_peripherals
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ AES_HASH ================ */
+/* =========================================================================================================================== */
+
+/* =================================================== CRYPTO_CLRIRQ_REG =================================================== */
+#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Pos (0UL) /*!< CRYPTO_CLRIRQ (Bit 0) */
+#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Msk (0x1UL) /*!< CRYPTO_CLRIRQ (Bitfield-Mask: 0x01) */
+/* ==================================================== CRYPTO_CTRL_REG ==================================================== */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Pos (17UL) /*!< CRYPTO_AES_KEXP (Bit 17) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Msk (0x20000UL) /*!< CRYPTO_AES_KEXP (Bitfield-Mask: 0x01) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Pos (16UL) /*!< CRYPTO_MORE_IN (Bit 16) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Msk (0x10000UL) /*!< CRYPTO_MORE_IN (Bitfield-Mask: 0x01) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Pos (10UL) /*!< CRYPTO_HASH_OUT_LEN (Bit 10) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Msk (0xfc00UL) /*!< CRYPTO_HASH_OUT_LEN (Bitfield-Mask: 0x3f) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Pos (9UL) /*!< CRYPTO_HASH_SEL (Bit 9) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Msk (0x200UL) /*!< CRYPTO_HASH_SEL (Bitfield-Mask: 0x01) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Pos (8UL) /*!< CRYPTO_IRQ_EN (Bit 8) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Msk (0x100UL) /*!< CRYPTO_IRQ_EN (Bitfield-Mask: 0x01) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Pos (7UL) /*!< CRYPTO_ENCDEC (Bit 7) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Msk (0x80UL) /*!< CRYPTO_ENCDEC (Bitfield-Mask: 0x01) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Pos (5UL) /*!< CRYPTO_AES_KEY_SZ (Bit 5) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Msk (0x60UL) /*!< CRYPTO_AES_KEY_SZ (Bitfield-Mask: 0x03) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Pos (4UL) /*!< CRYPTO_OUT_MD (Bit 4) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Msk (0x10UL) /*!< CRYPTO_OUT_MD (Bitfield-Mask: 0x01) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Pos (2UL) /*!< CRYPTO_ALG_MD (Bit 2) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk (0xcUL) /*!< CRYPTO_ALG_MD (Bitfield-Mask: 0x03) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Pos (0UL) /*!< CRYPTO_ALG (Bit 0) */
+#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Msk (0x3UL) /*!< CRYPTO_ALG (Bitfield-Mask: 0x03) */
+/* ================================================= CRYPTO_DEST_ADDR_REG ================================================== */
+#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Pos (0UL) /*!< CRYPTO_DEST_ADDR (Bit 0) */
+#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Msk (0xffffffffUL) /*!< CRYPTO_DEST_ADDR (Bitfield-Mask: 0xffffffff) */
+/* ================================================= CRYPTO_FETCH_ADDR_REG ================================================= */
+#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Pos (0UL) /*!< CRYPTO_FETCH_ADDR (Bit 0) */
+#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Msk (0xffffffffUL) /*!< CRYPTO_FETCH_ADDR (Bitfield-Mask: 0xffffffff) */
+/* =================================================== CRYPTO_KEYS_START =================================================== */
+#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Pos (0UL) /*!< CRYPTO_KEY_X (Bit 0) */
+#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Msk (0xffffffffUL) /*!< CRYPTO_KEY_X (Bitfield-Mask: 0xffffffff) */
+/* ==================================================== CRYPTO_LEN_REG ===================================================== */
+#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Pos (0UL) /*!< CRYPTO_LEN (Bit 0) */
+#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Msk (0xffffffUL) /*!< CRYPTO_LEN (Bitfield-Mask: 0xffffff) */
+/* =================================================== CRYPTO_MREG0_REG ==================================================== */
+#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Pos (0UL) /*!< CRYPTO_MREG0 (Bit 0) */
+#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Msk (0xffffffffUL) /*!< CRYPTO_MREG0 (Bitfield-Mask: 0xffffffff) */
+/* =================================================== CRYPTO_MREG1_REG ==================================================== */
+#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Pos (0UL) /*!< CRYPTO_MREG1 (Bit 0) */
+#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Msk (0xffffffffUL) /*!< CRYPTO_MREG1 (Bitfield-Mask: 0xffffffff) */
+/* =================================================== CRYPTO_MREG2_REG ==================================================== */
+#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Pos (0UL) /*!< CRYPTO_MREG2 (Bit 0) */
+#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Msk (0xffffffffUL) /*!< CRYPTO_MREG2 (Bitfield-Mask: 0xffffffff) */
+/* =================================================== CRYPTO_MREG3_REG ==================================================== */
+#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Pos (0UL) /*!< CRYPTO_MREG3 (Bit 0) */
+#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Msk (0xffffffffUL) /*!< CRYPTO_MREG3 (Bitfield-Mask: 0xffffffff) */
+/* =================================================== CRYPTO_START_REG ==================================================== */
+#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Pos (0UL) /*!< CRYPTO_START (Bit 0) */
+#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Msk (0x1UL) /*!< CRYPTO_START (Bitfield-Mask: 0x01) */
+/* =================================================== CRYPTO_STATUS_REG =================================================== */
+#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Pos (2UL) /*!< CRYPTO_IRQ_ST (Bit 2) */
+#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Msk (0x4UL) /*!< CRYPTO_IRQ_ST (Bitfield-Mask: 0x01) */
+#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Pos (1UL) /*!< CRYPTO_WAIT_FOR_IN (Bit 1) */
+#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Msk (0x2UL) /*!< CRYPTO_WAIT_FOR_IN (Bitfield-Mask: 0x01) */
+#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Pos (0UL) /*!< CRYPTO_INACTIVE (Bit 0) */
+#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Msk (0x1UL) /*!< CRYPTO_INACTIVE (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ ANAMISC_BIF ================ */
+/* =========================================================================================================================== */
+
+/* ==================================================== CLK_REF_CNT_REG ==================================================== */
+#define ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Pos (0UL) /*!< REF_CNT_VAL (Bit 0) */
+#define ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Msk (0xffffUL) /*!< REF_CNT_VAL (Bitfield-Mask: 0xffff) */
+/* ==================================================== CLK_REF_SEL_REG ==================================================== */
+#define ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Pos (5UL) /*!< CAL_CLK_SEL (Bit 5) */
+#define ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Msk (0xe0UL) /*!< CAL_CLK_SEL (Bitfield-Mask: 0x07) */
+#define ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Pos (4UL) /*!< EXT_CNT_EN_SEL (Bit 4) */
+#define ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Msk (0x10UL) /*!< EXT_CNT_EN_SEL (Bitfield-Mask: 0x01) */
+#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Pos (3UL) /*!< REF_CAL_START (Bit 3) */
+#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Msk (0x8UL) /*!< REF_CAL_START (Bitfield-Mask: 0x01) */
+#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Pos (0UL) /*!< REF_CLK_SEL (Bit 0) */
+#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Msk (0x7UL) /*!< REF_CLK_SEL (Bitfield-Mask: 0x07) */
+/* ==================================================== CLK_REF_VAL_REG ==================================================== */
+#define ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Pos (0UL) /*!< XTAL_CNT_VAL (Bit 0) */
+#define ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Msk (0xffffffffUL) /*!< XTAL_CNT_VAL (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ APU ================ */
+/* =========================================================================================================================== */
+
+/* ====================================================== APU_MUX_REG ====================================================== */
+#define APU_APU_MUX_REG_PDM1_MUX_IN_Pos (6UL) /*!< PDM1_MUX_IN (Bit 6) */
+#define APU_APU_MUX_REG_PDM1_MUX_IN_Msk (0x40UL) /*!< PDM1_MUX_IN (Bitfield-Mask: 0x01) */
+#define APU_APU_MUX_REG_PCM1_MUX_IN_Pos (3UL) /*!< PCM1_MUX_IN (Bit 3) */
+#define APU_APU_MUX_REG_PCM1_MUX_IN_Msk (0x38UL) /*!< PCM1_MUX_IN (Bitfield-Mask: 0x07) */
+#define APU_APU_MUX_REG_SRC1_MUX_IN_Pos (0UL) /*!< SRC1_MUX_IN (Bit 0) */
+#define APU_APU_MUX_REG_SRC1_MUX_IN_Msk (0x7UL) /*!< SRC1_MUX_IN (Bitfield-Mask: 0x07) */
+/* ==================================================== COEF0A_SET1_REG ==================================================== */
+#define APU_COEF0A_SET1_REG_SRC_COEF10_Pos (0UL) /*!< SRC_COEF10 (Bit 0) */
+#define APU_COEF0A_SET1_REG_SRC_COEF10_Msk (0xffffUL) /*!< SRC_COEF10 (Bitfield-Mask: 0xffff) */
+/* ==================================================== COEF10_SET1_REG ==================================================== */
+#define APU_COEF10_SET1_REG_SRC_COEF1_Pos (16UL) /*!< SRC_COEF1 (Bit 16) */
+#define APU_COEF10_SET1_REG_SRC_COEF1_Msk (0xffff0000UL) /*!< SRC_COEF1 (Bitfield-Mask: 0xffff) */
+#define APU_COEF10_SET1_REG_SRC_COEF0_Pos (0UL) /*!< SRC_COEF0 (Bit 0) */
+#define APU_COEF10_SET1_REG_SRC_COEF0_Msk (0xffffUL) /*!< SRC_COEF0 (Bitfield-Mask: 0xffff) */
+/* ==================================================== COEF32_SET1_REG ==================================================== */
+#define APU_COEF32_SET1_REG_SRC_COEF3_Pos (16UL) /*!< SRC_COEF3 (Bit 16) */
+#define APU_COEF32_SET1_REG_SRC_COEF3_Msk (0xffff0000UL) /*!< SRC_COEF3 (Bitfield-Mask: 0xffff) */
+#define APU_COEF32_SET1_REG_SRC_COEF2_Pos (0UL) /*!< SRC_COEF2 (Bit 0) */
+#define APU_COEF32_SET1_REG_SRC_COEF2_Msk (0xffffUL) /*!< SRC_COEF2 (Bitfield-Mask: 0xffff) */
+/* ==================================================== COEF54_SET1_REG ==================================================== */
+#define APU_COEF54_SET1_REG_SRC_COEF5_Pos (16UL) /*!< SRC_COEF5 (Bit 16) */
+#define APU_COEF54_SET1_REG_SRC_COEF5_Msk (0xffff0000UL) /*!< SRC_COEF5 (Bitfield-Mask: 0xffff) */
+#define APU_COEF54_SET1_REG_SRC_COEF4_Pos (0UL) /*!< SRC_COEF4 (Bit 0) */
+#define APU_COEF54_SET1_REG_SRC_COEF4_Msk (0xffffUL) /*!< SRC_COEF4 (Bitfield-Mask: 0xffff) */
+/* ==================================================== COEF76_SET1_REG ==================================================== */
+#define APU_COEF76_SET1_REG_SRC_COEF7_Pos (16UL) /*!< SRC_COEF7 (Bit 16) */
+#define APU_COEF76_SET1_REG_SRC_COEF7_Msk (0xffff0000UL) /*!< SRC_COEF7 (Bitfield-Mask: 0xffff) */
+#define APU_COEF76_SET1_REG_SRC_COEF6_Pos (0UL) /*!< SRC_COEF6 (Bit 0) */
+#define APU_COEF76_SET1_REG_SRC_COEF6_Msk (0xffffUL) /*!< SRC_COEF6 (Bitfield-Mask: 0xffff) */
+/* ==================================================== COEF98_SET1_REG ==================================================== */
+#define APU_COEF98_SET1_REG_SRC_COEF9_Pos (16UL) /*!< SRC_COEF9 (Bit 16) */
+#define APU_COEF98_SET1_REG_SRC_COEF9_Msk (0xffff0000UL) /*!< SRC_COEF9 (Bitfield-Mask: 0xffff) */
+#define APU_COEF98_SET1_REG_SRC_COEF8_Pos (0UL) /*!< SRC_COEF8 (Bit 0) */
+#define APU_COEF98_SET1_REG_SRC_COEF8_Msk (0xffffUL) /*!< SRC_COEF8 (Bitfield-Mask: 0xffff) */
+/* ===================================================== PCM1_CTRL_REG ===================================================== */
+#define APU_PCM1_CTRL_REG_PCM_FSC_DIV_Pos (20UL) /*!< PCM_FSC_DIV (Bit 20) */
+#define APU_PCM1_CTRL_REG_PCM_FSC_DIV_Msk (0xfff00000UL) /*!< PCM_FSC_DIV (Bitfield-Mask: 0xfff) */
+#define APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Pos (16UL) /*!< PCM_FSC_EDGE (Bit 16) */
+#define APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Msk (0x10000UL) /*!< PCM_FSC_EDGE (Bitfield-Mask: 0x01) */
+#define APU_PCM1_CTRL_REG_PCM_CH_DEL_Pos (11UL) /*!< PCM_CH_DEL (Bit 11) */
+#define APU_PCM1_CTRL_REG_PCM_CH_DEL_Msk (0xf800UL) /*!< PCM_CH_DEL (Bitfield-Mask: 0x1f) */
+#define APU_PCM1_CTRL_REG_PCM_CLK_BIT_Pos (10UL) /*!< PCM_CLK_BIT (Bit 10) */
+#define APU_PCM1_CTRL_REG_PCM_CLK_BIT_Msk (0x400UL) /*!< PCM_CLK_BIT (Bitfield-Mask: 0x01) */
+#define APU_PCM1_CTRL_REG_PCM_FSCINV_Pos (9UL) /*!< PCM_FSCINV (Bit 9) */
+#define APU_PCM1_CTRL_REG_PCM_FSCINV_Msk (0x200UL) /*!< PCM_FSCINV (Bitfield-Mask: 0x01) */
+#define APU_PCM1_CTRL_REG_PCM_CLKINV_Pos (8UL) /*!< PCM_CLKINV (Bit 8) */
+#define APU_PCM1_CTRL_REG_PCM_CLKINV_Msk (0x100UL) /*!< PCM_CLKINV (Bitfield-Mask: 0x01) */
+#define APU_PCM1_CTRL_REG_PCM_PPOD_Pos (7UL) /*!< PCM_PPOD (Bit 7) */
+#define APU_PCM1_CTRL_REG_PCM_PPOD_Msk (0x80UL) /*!< PCM_PPOD (Bitfield-Mask: 0x01) */
+#define APU_PCM1_CTRL_REG_PCM_FSCDEL_Pos (6UL) /*!< PCM_FSCDEL (Bit 6) */
+#define APU_PCM1_CTRL_REG_PCM_FSCDEL_Msk (0x40UL) /*!< PCM_FSCDEL (Bitfield-Mask: 0x01) */
+#define APU_PCM1_CTRL_REG_PCM_FSCLEN_Pos (2UL) /*!< PCM_FSCLEN (Bit 2) */
+#define APU_PCM1_CTRL_REG_PCM_FSCLEN_Msk (0x3cUL) /*!< PCM_FSCLEN (Bitfield-Mask: 0x0f) */
+#define APU_PCM1_CTRL_REG_PCM_MASTER_Pos (1UL) /*!< PCM_MASTER (Bit 1) */
+#define APU_PCM1_CTRL_REG_PCM_MASTER_Msk (0x2UL) /*!< PCM_MASTER (Bitfield-Mask: 0x01) */
+#define APU_PCM1_CTRL_REG_PCM_EN_Pos (0UL) /*!< PCM_EN (Bit 0) */
+#define APU_PCM1_CTRL_REG_PCM_EN_Msk (0x1UL) /*!< PCM_EN (Bitfield-Mask: 0x01) */
+/* ===================================================== PCM1_IN1_REG ====================================================== */
+#define APU_PCM1_IN1_REG_PCM_IN_Pos (0UL) /*!< PCM_IN (Bit 0) */
+#define APU_PCM1_IN1_REG_PCM_IN_Msk (0xffffffffUL) /*!< PCM_IN (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== PCM1_IN2_REG ====================================================== */
+#define APU_PCM1_IN2_REG_PCM_IN_Pos (0UL) /*!< PCM_IN (Bit 0) */
+#define APU_PCM1_IN2_REG_PCM_IN_Msk (0xffffffffUL) /*!< PCM_IN (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== PCM1_OUT1_REG ===================================================== */
+#define APU_PCM1_OUT1_REG_PCM_OUT_Pos (0UL) /*!< PCM_OUT (Bit 0) */
+#define APU_PCM1_OUT1_REG_PCM_OUT_Msk (0xffffffffUL) /*!< PCM_OUT (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== PCM1_OUT2_REG ===================================================== */
+#define APU_PCM1_OUT2_REG_PCM_OUT_Pos (0UL) /*!< PCM_OUT (Bit 0) */
+#define APU_PCM1_OUT2_REG_PCM_OUT_Msk (0xffffffffUL) /*!< PCM_OUT (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== SRC1_CTRL_REG ===================================================== */
+#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Pos (30UL) /*!< SRC_PDM_DO_DEL (Bit 30) */
+#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Msk (0xc0000000UL) /*!< SRC_PDM_DO_DEL (Bitfield-Mask: 0x03) */
+#define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Pos (28UL) /*!< SRC_PDM_MODE (Bit 28) */
+#define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Msk (0x30000000UL) /*!< SRC_PDM_MODE (Bitfield-Mask: 0x03) */
+#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Pos (26UL) /*!< SRC_PDM_DI_DEL (Bit 26) */
+#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Msk (0xc000000UL) /*!< SRC_PDM_DI_DEL (Bitfield-Mask: 0x03) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Pos (25UL) /*!< SRC_OUT_FLOWCLR (Bit 25) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Msk (0x2000000UL) /*!< SRC_OUT_FLOWCLR (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Pos (24UL) /*!< SRC_IN_FLOWCLR (Bit 24) */
+#define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Msk (0x1000000UL) /*!< SRC_IN_FLOWCLR (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Pos (23UL) /*!< SRC_OUT_UNFLOW (Bit 23) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Msk (0x800000UL) /*!< SRC_OUT_UNFLOW (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Pos (22UL) /*!< SRC_OUT_OVFLOW (Bit 22) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Msk (0x400000UL) /*!< SRC_OUT_OVFLOW (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Pos (21UL) /*!< SRC_IN_UNFLOW (Bit 21) */
+#define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Msk (0x200000UL) /*!< SRC_IN_UNFLOW (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Pos (20UL) /*!< SRC_IN_OVFLOW (Bit 20) */
+#define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Msk (0x100000UL) /*!< SRC_IN_OVFLOW (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_RESYNC_Pos (19UL) /*!< SRC_RESYNC (Bit 19) */
+#define APU_SRC1_CTRL_REG_SRC_RESYNC_Msk (0x80000UL) /*!< SRC_RESYNC (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_OK_Pos (18UL) /*!< SRC_OUT_OK (Bit 18) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_OK_Msk (0x40000UL) /*!< SRC_OUT_OK (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_US_Pos (16UL) /*!< SRC_OUT_US (Bit 16) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_US_Msk (0x30000UL) /*!< SRC_OUT_US (Bitfield-Mask: 0x03) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos (14UL) /*!< SRC_OUT_CAL_BYPASS (Bit 14) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk (0x4000UL) /*!< SRC_OUT_CAL_BYPASS (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Pos (13UL) /*!< SRC_OUT_AMODE (Bit 13) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Msk (0x2000UL) /*!< SRC_OUT_AMODE (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_PDM_OUT_INV_Pos (12UL) /*!< SRC_PDM_OUT_INV (Bit 12) */
+#define APU_SRC1_CTRL_REG_SRC_PDM_OUT_INV_Msk (0x1000UL) /*!< SRC_PDM_OUT_INV (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_FIFO_DIRECTION_Pos (11UL) /*!< SRC_FIFO_DIRECTION (Bit 11) */
+#define APU_SRC1_CTRL_REG_SRC_FIFO_DIRECTION_Msk (0x800UL) /*!< SRC_FIFO_DIRECTION (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_FIFO_ENABLE_Pos (10UL) /*!< SRC_FIFO_ENABLE (Bit 10) */
+#define APU_SRC1_CTRL_REG_SRC_FIFO_ENABLE_Msk (0x400UL) /*!< SRC_FIFO_ENABLE (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_DSD_MODE_Pos (9UL) /*!< SRC_OUT_DSD_MODE (Bit 9) */
+#define APU_SRC1_CTRL_REG_SRC_OUT_DSD_MODE_Msk (0x200UL) /*!< SRC_OUT_DSD_MODE (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_IN_DSD_MODE_Pos (8UL) /*!< SRC_IN_DSD_MODE (Bit 8) */
+#define APU_SRC1_CTRL_REG_SRC_IN_DSD_MODE_Msk (0x100UL) /*!< SRC_IN_DSD_MODE (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Pos (7UL) /*!< SRC_DITHER_DISABLE (Bit 7) */
+#define APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Msk (0x80UL) /*!< SRC_DITHER_DISABLE (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_IN_OK_Pos (6UL) /*!< SRC_IN_OK (Bit 6) */
+#define APU_SRC1_CTRL_REG_SRC_IN_OK_Msk (0x40UL) /*!< SRC_IN_OK (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_IN_DS_Pos (4UL) /*!< SRC_IN_DS (Bit 4) */
+#define APU_SRC1_CTRL_REG_SRC_IN_DS_Msk (0x30UL) /*!< SRC_IN_DS (Bitfield-Mask: 0x03) */
+#define APU_SRC1_CTRL_REG_SRC_PDM_IN_INV_Pos (3UL) /*!< SRC_PDM_IN_INV (Bit 3) */
+#define APU_SRC1_CTRL_REG_SRC_PDM_IN_INV_Msk (0x8UL) /*!< SRC_PDM_IN_INV (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Pos (2UL) /*!< SRC_IN_CAL_BYPASS (Bit 2) */
+#define APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Msk (0x4UL) /*!< SRC_IN_CAL_BYPASS (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_IN_AMODE_Pos (1UL) /*!< SRC_IN_AMODE (Bit 1) */
+#define APU_SRC1_CTRL_REG_SRC_IN_AMODE_Msk (0x2UL) /*!< SRC_IN_AMODE (Bitfield-Mask: 0x01) */
+#define APU_SRC1_CTRL_REG_SRC_EN_Pos (0UL) /*!< SRC_EN (Bit 0) */
+#define APU_SRC1_CTRL_REG_SRC_EN_Msk (0x1UL) /*!< SRC_EN (Bitfield-Mask: 0x01) */
+/* ===================================================== SRC1_IN1_REG ====================================================== */
+#define APU_SRC1_IN1_REG_SRC_IN_Pos (0UL) /*!< SRC_IN (Bit 0) */
+#define APU_SRC1_IN1_REG_SRC_IN_Msk (0xffffffffUL) /*!< SRC_IN (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== SRC1_IN2_REG ====================================================== */
+#define APU_SRC1_IN2_REG_SRC_IN_Pos (0UL) /*!< SRC_IN (Bit 0) */
+#define APU_SRC1_IN2_REG_SRC_IN_Msk (0xffffffffUL) /*!< SRC_IN (Bitfield-Mask: 0xffffffff) */
+/* ==================================================== SRC1_IN_FS_REG ===================================================== */
+#define APU_SRC1_IN_FS_REG_SRC_IN_FS_Pos (0UL) /*!< SRC_IN_FS (Bit 0) */
+#define APU_SRC1_IN_FS_REG_SRC_IN_FS_Msk (0xffffffUL) /*!< SRC_IN_FS (Bitfield-Mask: 0xffffff) */
+/* ===================================================== SRC1_OUT1_REG ===================================================== */
+#define APU_SRC1_OUT1_REG_SRC_OUT_Pos (0UL) /*!< SRC_OUT (Bit 0) */
+#define APU_SRC1_OUT1_REG_SRC_OUT_Msk (0xffffffffUL) /*!< SRC_OUT (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== SRC1_OUT2_REG ===================================================== */
+#define APU_SRC1_OUT2_REG_SRC_OUT_Pos (0UL) /*!< SRC_OUT (Bit 0) */
+#define APU_SRC1_OUT2_REG_SRC_OUT_Msk (0xffffffffUL) /*!< SRC_OUT (Bitfield-Mask: 0xffffffff) */
+/* ==================================================== SRC1_OUT_FS_REG ==================================================== */
+#define APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Pos (0UL) /*!< SRC_OUT_FS (Bit 0) */
+#define APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Msk (0xffffffUL) /*!< SRC_OUT_FS (Bitfield-Mask: 0xffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ CACHE ================ */
+/* =========================================================================================================================== */
+
+/* ================================================== CACHE_ASSOCCFG_REG =================================================== */
+#define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Pos (0UL) /*!< CACHE_ASSOC (Bit 0) */
+#define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Msk (0x3UL) /*!< CACHE_ASSOC (Bitfield-Mask: 0x03) */
+/* ==================================================== CACHE_CTRL1_REG ==================================================== */
+#define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Pos (1UL) /*!< CACHE_RES1 (Bit 1) */
+#define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Msk (0x2UL) /*!< CACHE_RES1 (Bitfield-Mask: 0x01) */
+#define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Pos (0UL) /*!< CACHE_FLUSH (Bit 0) */
+#define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Msk (0x1UL) /*!< CACHE_FLUSH (Bitfield-Mask: 0x01) */
+/* ==================================================== CACHE_CTRL2_REG ==================================================== */
+#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Pos (10UL) /*!< CACHE_CGEN (Bit 10) */
+#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Msk (0x400UL) /*!< CACHE_CGEN (Bitfield-Mask: 0x01) */
+#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Pos (9UL) /*!< CACHE_WEN (Bit 9) */
+#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Msk (0x200UL) /*!< CACHE_WEN (Bitfield-Mask: 0x01) */
+#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Pos (0UL) /*!< CACHE_LEN (Bit 0) */
+#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk (0x1ffUL) /*!< CACHE_LEN (Bitfield-Mask: 0x1ff) */
+/* ==================================================== CACHE_FLASH_REG ==================================================== */
+#define CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Pos (16UL) /*!< FLASH_REGION_BASE (Bit 16) */
+#define CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Msk (0xffff0000UL) /*!< FLASH_REGION_BASE (Bitfield-Mask: 0xffff) */
+#define CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Pos (4UL) /*!< FLASH_REGION_OFFSET (Bit 4) */
+#define CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Msk (0xfff0UL) /*!< FLASH_REGION_OFFSET (Bitfield-Mask: 0xfff) */
+#define CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Pos (0UL) /*!< FLASH_REGION_SIZE (Bit 0) */
+#define CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Msk (0x7UL) /*!< FLASH_REGION_SIZE (Bitfield-Mask: 0x07) */
+/* ================================================== CACHE_LNSIZECFG_REG ================================================== */
+#define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Pos (0UL) /*!< CACHE_LINE (Bit 0) */
+#define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Msk (0x3UL) /*!< CACHE_LINE (Bitfield-Mask: 0x03) */
+/* ================================================== CACHE_MRM_CTRL_REG =================================================== */
+#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Pos (4UL) /*!< MRM_IRQ_HITS_THRES_STATUS (Bit 4) */
+#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Msk (0x10UL) /*!< MRM_IRQ_HITS_THRES_STATUS (Bitfield-Mask: 0x01) */
+#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Pos (3UL) /*!< MRM_IRQ_MISSES_THRES_STATUS (Bit 3) */
+#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Msk (0x8UL) /*!< MRM_IRQ_MISSES_THRES_STATUS (Bitfield-Mask: 0x01) */
+#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos (2UL) /*!< MRM_IRQ_TINT_STATUS (Bit 2) */
+#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk (0x4UL) /*!< MRM_IRQ_TINT_STATUS (Bitfield-Mask: 0x01) */
+#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos (1UL) /*!< MRM_IRQ_MASK (Bit 1) */
+#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk (0x2UL) /*!< MRM_IRQ_MASK (Bitfield-Mask: 0x01) */
+#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Pos (0UL) /*!< MRM_START (Bit 0) */
+#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Msk (0x1UL) /*!< MRM_START (Bitfield-Mask: 0x01) */
+/* ================================================== CACHE_MRM_HITS_REG =================================================== */
+#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Pos (0UL) /*!< MRM_HITS (Bit 0) */
+#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Msk (0xffffffffUL) /*!< MRM_HITS (Bitfield-Mask: 0xffffffff) */
+/* =============================================== CACHE_MRM_HITS_THRES_REG ================================================ */
+#define CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Pos (0UL) /*!< MRM_HITS_THRES (Bit 0) */
+#define CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Msk (0xffffffffUL) /*!< MRM_HITS_THRES (Bitfield-Mask: 0xffffffff) */
+/* ================================================= CACHE_MRM_MISSES_REG ================================================== */
+#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos (0UL) /*!< MRM_MISSES (Bit 0) */
+#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk (0xffffffffUL) /*!< MRM_MISSES (Bitfield-Mask: 0xffffffff) */
+/* ============================================== CACHE_MRM_MISSES_THRES_REG =============================================== */
+#define CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Pos (0UL) /*!< MRM_MISSES_THRES (Bit 0) */
+#define CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Msk (0xffffffffUL) /*!< MRM_MISSES_THRES (Bitfield-Mask: 0xffffffff) */
+/* ================================================== CACHE_MRM_TINT_REG =================================================== */
+#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Pos (0UL) /*!< MRM_TINT (Bit 0) */
+#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk (0x7ffffUL) /*!< MRM_TINT (Bitfield-Mask: 0x7ffff) */
+/* ===================================================== SWD_RESET_REG ===================================================== */
+#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Pos (0UL) /*!< SWD_HW_RESET_REQ (Bit 0) */
+#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Msk (0x1UL) /*!< SWD_HW_RESET_REQ (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CHARGER ================ */
+/* =========================================================================================================================== */
+
+/* ============================================== CHARGER_CC_CHARGE_TIMER_REG ============================================== */
+#define CHARGER_CHARGER_CC_CHARGE_TIMER_REG_CC_CHARGE_TIMER_Pos (16UL) /*!< CC_CHARGE_TIMER (Bit 16) */
+#define CHARGER_CHARGER_CC_CHARGE_TIMER_REG_CC_CHARGE_TIMER_Msk (0x7fff0000UL) /*!< CC_CHARGE_TIMER (Bitfield-Mask: 0x7fff) */
+#define CHARGER_CHARGER_CC_CHARGE_TIMER_REG_MAX_CC_CHARGE_TIME_Pos (0UL) /*!< MAX_CC_CHARGE_TIME (Bit 0) */
+#define CHARGER_CHARGER_CC_CHARGE_TIMER_REG_MAX_CC_CHARGE_TIME_Msk (0x7fffUL) /*!< MAX_CC_CHARGE_TIME (Bitfield-Mask: 0x7fff) */
+/* =================================================== CHARGER_CTRL_REG ==================================================== */
+#define CHARGER_CHARGER_CTRL_REG_EOC_INTERVAL_CHECK_TIMER_Pos (22UL) /*!< EOC_INTERVAL_CHECK_TIMER (Bit 22) */
+#define CHARGER_CHARGER_CTRL_REG_EOC_INTERVAL_CHECK_TIMER_Msk (0xfc00000UL) /*!< EOC_INTERVAL_CHECK_TIMER (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_CTRL_REG_EOC_INTERVAL_CHECK_THRES_Pos (16UL) /*!< EOC_INTERVAL_CHECK_THRES (Bit 16) */
+#define CHARGER_CHARGER_CTRL_REG_EOC_INTERVAL_CHECK_THRES_Msk (0x3f0000UL) /*!< EOC_INTERVAL_CHECK_THRES (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_CTRL_REG_REPLENISH_MODE_Pos (15UL) /*!< REPLENISH_MODE (Bit 15) */
+#define CHARGER_CHARGER_CTRL_REG_REPLENISH_MODE_Msk (0x8000UL) /*!< REPLENISH_MODE (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_CTRL_REG_PRE_CHARGE_MODE_Pos (14UL) /*!< PRE_CHARGE_MODE (Bit 14) */
+#define CHARGER_CHARGER_CTRL_REG_PRE_CHARGE_MODE_Msk (0x4000UL) /*!< PRE_CHARGE_MODE (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_CTRL_REG_CHARGE_LOOP_HOLD_Pos (13UL) /*!< CHARGE_LOOP_HOLD (Bit 13) */
+#define CHARGER_CHARGER_CTRL_REG_CHARGE_LOOP_HOLD_Msk (0x2000UL) /*!< CHARGE_LOOP_HOLD (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_CTRL_REG_JEITA_SUPPORT_DISABLED_Pos (12UL) /*!< JEITA_SUPPORT_DISABLED (Bit 12) */
+#define CHARGER_CHARGER_CTRL_REG_JEITA_SUPPORT_DISABLED_Msk (0x1000UL) /*!< JEITA_SUPPORT_DISABLED (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_CTRL_REG_TBAT_MONITOR_MODE_Pos (10UL) /*!< TBAT_MONITOR_MODE (Bit 10) */
+#define CHARGER_CHARGER_CTRL_REG_TBAT_MONITOR_MODE_Msk (0xc00UL) /*!< TBAT_MONITOR_MODE (Bitfield-Mask: 0x03) */
+#define CHARGER_CHARGER_CTRL_REG_CHARGE_TIMERS_HALT_ENABLE_Pos (9UL) /*!< CHARGE_TIMERS_HALT_ENABLE (Bit 9) */
+#define CHARGER_CHARGER_CTRL_REG_CHARGE_TIMERS_HALT_ENABLE_Msk (0x200UL) /*!< CHARGE_TIMERS_HALT_ENABLE (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_CTRL_REG_NTC_LOW_DISABLE_Pos (7UL) /*!< NTC_LOW_DISABLE (Bit 7) */
+#define CHARGER_CHARGER_CTRL_REG_NTC_LOW_DISABLE_Msk (0x80UL) /*!< NTC_LOW_DISABLE (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_CTRL_REG_TBAT_PROT_ENABLE_Pos (6UL) /*!< TBAT_PROT_ENABLE (Bit 6) */
+#define CHARGER_CHARGER_CTRL_REG_TBAT_PROT_ENABLE_Msk (0x40UL) /*!< TBAT_PROT_ENABLE (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_CTRL_REG_TDIE_ERROR_RESUME_Pos (5UL) /*!< TDIE_ERROR_RESUME (Bit 5) */
+#define CHARGER_CHARGER_CTRL_REG_TDIE_ERROR_RESUME_Msk (0x20UL) /*!< TDIE_ERROR_RESUME (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_CTRL_REG_TDIE_PROT_ENABLE_Pos (4UL) /*!< TDIE_PROT_ENABLE (Bit 4) */
+#define CHARGER_CHARGER_CTRL_REG_TDIE_PROT_ENABLE_Msk (0x10UL) /*!< TDIE_PROT_ENABLE (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_CTRL_REG_CHARGER_RESUME_Pos (3UL) /*!< CHARGER_RESUME (Bit 3) */
+#define CHARGER_CHARGER_CTRL_REG_CHARGER_RESUME_Msk (0x8UL) /*!< CHARGER_RESUME (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_CTRL_REG_CHARGER_BYPASS_Pos (2UL) /*!< CHARGER_BYPASS (Bit 2) */
+#define CHARGER_CHARGER_CTRL_REG_CHARGER_BYPASS_Msk (0x4UL) /*!< CHARGER_BYPASS (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_CTRL_REG_CHARGE_START_Pos (1UL) /*!< CHARGE_START (Bit 1) */
+#define CHARGER_CHARGER_CTRL_REG_CHARGE_START_Msk (0x2UL) /*!< CHARGE_START (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_CTRL_REG_CHARGER_ENABLE_Pos (0UL) /*!< CHARGER_ENABLE (Bit 0) */
+#define CHARGER_CHARGER_CTRL_REG_CHARGER_ENABLE_Msk (0x1UL) /*!< CHARGER_ENABLE (Bitfield-Mask: 0x01) */
+/* =============================================== CHARGER_CURRENT_PARAM_REG =============================================== */
+#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_EOC_DOUBLE_RANGE_Pos (15UL) /*!< I_EOC_DOUBLE_RANGE (Bit 15) */
+#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_EOC_DOUBLE_RANGE_Msk (0x8000UL) /*!< I_EOC_DOUBLE_RANGE (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_END_OF_CHARGE_Pos (12UL) /*!< I_END_OF_CHARGE (Bit 12) */
+#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_END_OF_CHARGE_Msk (0x7000UL) /*!< I_END_OF_CHARGE (Bitfield-Mask: 0x07) */
+#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_PRECHARGE_Pos (6UL) /*!< I_PRECHARGE (Bit 6) */
+#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_PRECHARGE_Msk (0xfc0UL) /*!< I_PRECHARGE (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_CHARGE_Pos (0UL) /*!< I_CHARGE (Bit 0) */
+#define CHARGER_CHARGER_CURRENT_PARAM_REG_I_CHARGE_Msk (0x3fUL) /*!< I_CHARGE (Bitfield-Mask: 0x3f) */
+/* ============================================== CHARGER_CV_CHARGE_TIMER_REG ============================================== */
+#define CHARGER_CHARGER_CV_CHARGE_TIMER_REG_CV_CHARGE_TIMER_Pos (16UL) /*!< CV_CHARGE_TIMER (Bit 16) */
+#define CHARGER_CHARGER_CV_CHARGE_TIMER_REG_CV_CHARGE_TIMER_Msk (0x7fff0000UL) /*!< CV_CHARGE_TIMER (Bitfield-Mask: 0x7fff) */
+#define CHARGER_CHARGER_CV_CHARGE_TIMER_REG_MAX_CV_CHARGE_TIME_Pos (0UL) /*!< MAX_CV_CHARGE_TIME (Bit 0) */
+#define CHARGER_CHARGER_CV_CHARGE_TIMER_REG_MAX_CV_CHARGE_TIME_Msk (0x7fffUL) /*!< MAX_CV_CHARGE_TIME (Bitfield-Mask: 0x7fff) */
+/* =============================================== CHARGER_ERROR_IRQ_CLR_REG =============================================== */
+#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TBAT_ERROR_IRQ_CLR_Pos (6UL) /*!< TBAT_ERROR_IRQ_CLR (Bit 6) */
+#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TBAT_ERROR_IRQ_CLR_Msk (0x40UL) /*!< TBAT_ERROR_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TDIE_ERROR_IRQ_CLR_Pos (5UL) /*!< TDIE_ERROR_IRQ_CLR (Bit 5) */
+#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TDIE_ERROR_IRQ_CLR_Msk (0x20UL) /*!< TDIE_ERROR_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_VBAT_OVP_ERROR_IRQ_CLR_Pos (4UL) /*!< VBAT_OVP_ERROR_IRQ_CLR (Bit 4) */
+#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_VBAT_OVP_ERROR_IRQ_CLR_Msk (0x10UL) /*!< VBAT_OVP_ERROR_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TOTAL_CHARGE_TIMEOUT_IRQ_CLR_Pos (3UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ_CLR (Bit 3) */
+#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_TOTAL_CHARGE_TIMEOUT_IRQ_CLR_Msk (0x8UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_CV_CHARGE_TIMEOUT_IRQ_CLR_Pos (2UL) /*!< CV_CHARGE_TIMEOUT_IRQ_CLR (Bit 2) */
+#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_CV_CHARGE_TIMEOUT_IRQ_CLR_Msk (0x4UL) /*!< CV_CHARGE_TIMEOUT_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_CC_CHARGE_TIMEOUT_IRQ_CLR_Pos (1UL) /*!< CC_CHARGE_TIMEOUT_IRQ_CLR (Bit 1) */
+#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_CC_CHARGE_TIMEOUT_IRQ_CLR_Msk (0x2UL) /*!< CC_CHARGE_TIMEOUT_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_PRECHARGE_TIMEOUT_IRQ_CLR_Pos (0UL) /*!< PRECHARGE_TIMEOUT_IRQ_CLR (Bit 0) */
+#define CHARGER_CHARGER_ERROR_IRQ_CLR_REG_PRECHARGE_TIMEOUT_IRQ_CLR_Msk (0x1UL) /*!< PRECHARGE_TIMEOUT_IRQ_CLR (Bitfield-Mask: 0x01) */
+/* ============================================== CHARGER_ERROR_IRQ_MASK_REG =============================================== */
+#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TBAT_ERROR_IRQ_EN_Pos (6UL) /*!< TBAT_ERROR_IRQ_EN (Bit 6) */
+#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TBAT_ERROR_IRQ_EN_Msk (0x40UL) /*!< TBAT_ERROR_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TDIE_ERROR_IRQ_EN_Pos (5UL) /*!< TDIE_ERROR_IRQ_EN (Bit 5) */
+#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TDIE_ERROR_IRQ_EN_Msk (0x20UL) /*!< TDIE_ERROR_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_VBAT_OVP_ERROR_IRQ_EN_Pos (4UL) /*!< VBAT_OVP_ERROR_IRQ_EN (Bit 4) */
+#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_VBAT_OVP_ERROR_IRQ_EN_Msk (0x10UL) /*!< VBAT_OVP_ERROR_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TOTAL_CHARGE_TIMEOUT_IRQ_EN_Pos (3UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ_EN (Bit 3) */
+#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_TOTAL_CHARGE_TIMEOUT_IRQ_EN_Msk (0x8UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_CV_CHARGE_TIMEOUT_IRQ_EN_Pos (2UL) /*!< CV_CHARGE_TIMEOUT_IRQ_EN (Bit 2) */
+#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_CV_CHARGE_TIMEOUT_IRQ_EN_Msk (0x4UL) /*!< CV_CHARGE_TIMEOUT_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_CC_CHARGE_TIMEOUT_IRQ_EN_Pos (1UL) /*!< CC_CHARGE_TIMEOUT_IRQ_EN (Bit 1) */
+#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_CC_CHARGE_TIMEOUT_IRQ_EN_Msk (0x2UL) /*!< CC_CHARGE_TIMEOUT_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_PRECHARGE_TIMEOUT_IRQ_EN_Pos (0UL) /*!< PRECHARGE_TIMEOUT_IRQ_EN (Bit 0) */
+#define CHARGER_CHARGER_ERROR_IRQ_MASK_REG_PRECHARGE_TIMEOUT_IRQ_EN_Msk (0x1UL) /*!< PRECHARGE_TIMEOUT_IRQ_EN (Bitfield-Mask: 0x01) */
+/* ============================================= CHARGER_ERROR_IRQ_STATUS_REG ============================================== */
+#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TBAT_ERROR_IRQ_Pos (6UL) /*!< TBAT_ERROR_IRQ (Bit 6) */
+#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TBAT_ERROR_IRQ_Msk (0x40UL) /*!< TBAT_ERROR_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TDIE_ERROR_IRQ_Pos (5UL) /*!< TDIE_ERROR_IRQ (Bit 5) */
+#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TDIE_ERROR_IRQ_Msk (0x20UL) /*!< TDIE_ERROR_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_VBAT_OVP_ERROR_IRQ_Pos (4UL) /*!< VBAT_OVP_ERROR_IRQ (Bit 4) */
+#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_VBAT_OVP_ERROR_IRQ_Msk (0x10UL) /*!< VBAT_OVP_ERROR_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TOTAL_CHARGE_TIMEOUT_IRQ_Pos (3UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ (Bit 3) */
+#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_TOTAL_CHARGE_TIMEOUT_IRQ_Msk (0x8UL) /*!< TOTAL_CHARGE_TIMEOUT_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_CV_CHARGE_TIMEOUT_IRQ_Pos (2UL) /*!< CV_CHARGE_TIMEOUT_IRQ (Bit 2) */
+#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_CV_CHARGE_TIMEOUT_IRQ_Msk (0x4UL) /*!< CV_CHARGE_TIMEOUT_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_CC_CHARGE_TIMEOUT_IRQ_Pos (1UL) /*!< CC_CHARGE_TIMEOUT_IRQ (Bit 1) */
+#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_CC_CHARGE_TIMEOUT_IRQ_Msk (0x2UL) /*!< CC_CHARGE_TIMEOUT_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_PRECHARGE_TIMEOUT_IRQ_Pos (0UL) /*!< PRECHARGE_TIMEOUT_IRQ (Bit 0) */
+#define CHARGER_CHARGER_ERROR_IRQ_STATUS_REG_PRECHARGE_TIMEOUT_IRQ_Msk (0x1UL) /*!< PRECHARGE_TIMEOUT_IRQ (Bitfield-Mask: 0x01) */
+/* =============================================== CHARGER_JEITA_CURRENT_REG =============================================== */
+#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_PRECHARGE_TWARM_Pos (18UL) /*!< I_PRECHARGE_TWARM (Bit 18) */
+#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_PRECHARGE_TWARM_Msk (0xfc0000UL) /*!< I_PRECHARGE_TWARM (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_PRECHARGE_TCOOL_Pos (12UL) /*!< I_PRECHARGE_TCOOL (Bit 12) */
+#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_PRECHARGE_TCOOL_Msk (0x3f000UL) /*!< I_PRECHARGE_TCOOL (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_CHARGE_TWARM_Pos (6UL) /*!< I_CHARGE_TWARM (Bit 6) */
+#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_CHARGE_TWARM_Msk (0xfc0UL) /*!< I_CHARGE_TWARM (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_CHARGE_TCOOL_Pos (0UL) /*!< I_CHARGE_TCOOL (Bit 0) */
+#define CHARGER_CHARGER_JEITA_CURRENT_REG_I_CHARGE_TCOOL_Msk (0x3fUL) /*!< I_CHARGE_TCOOL (Bitfield-Mask: 0x3f) */
+/* ============================================== CHARGER_JEITA_V_CHARGE_REG =============================================== */
+#define CHARGER_CHARGER_JEITA_V_CHARGE_REG_V_CHARGE_TWARM_Pos (6UL) /*!< V_CHARGE_TWARM (Bit 6) */
+#define CHARGER_CHARGER_JEITA_V_CHARGE_REG_V_CHARGE_TWARM_Msk (0xfc0UL) /*!< V_CHARGE_TWARM (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_JEITA_V_CHARGE_REG_V_CHARGE_TCOOL_Pos (0UL) /*!< V_CHARGE_TCOOL (Bit 0) */
+#define CHARGER_CHARGER_JEITA_V_CHARGE_REG_V_CHARGE_TCOOL_Msk (0x3fUL) /*!< V_CHARGE_TCOOL (Bitfield-Mask: 0x3f) */
+/* ================================================ CHARGER_JEITA_V_OVP_REG ================================================ */
+#define CHARGER_CHARGER_JEITA_V_OVP_REG_V_OVP_TWARM_Pos (6UL) /*!< V_OVP_TWARM (Bit 6) */
+#define CHARGER_CHARGER_JEITA_V_OVP_REG_V_OVP_TWARM_Msk (0xfc0UL) /*!< V_OVP_TWARM (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_JEITA_V_OVP_REG_V_OVP_TCOOL_Pos (0UL) /*!< V_OVP_TCOOL (Bit 0) */
+#define CHARGER_CHARGER_JEITA_V_OVP_REG_V_OVP_TCOOL_Msk (0x3fUL) /*!< V_OVP_TCOOL (Bitfield-Mask: 0x3f) */
+/* ============================================= CHARGER_JEITA_V_PRECHARGE_REG ============================================= */
+#define CHARGER_CHARGER_JEITA_V_PRECHARGE_REG_V_PRECHARGE_TWARM_Pos (6UL) /*!< V_PRECHARGE_TWARM (Bit 6) */
+#define CHARGER_CHARGER_JEITA_V_PRECHARGE_REG_V_PRECHARGE_TWARM_Msk (0xfc0UL) /*!< V_PRECHARGE_TWARM (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_JEITA_V_PRECHARGE_REG_V_PRECHARGE_TCOOL_Pos (0UL) /*!< V_PRECHARGE_TCOOL (Bit 0) */
+#define CHARGER_CHARGER_JEITA_V_PRECHARGE_REG_V_PRECHARGE_TCOOL_Msk (0x3fUL) /*!< V_PRECHARGE_TCOOL (Bitfield-Mask: 0x3f) */
+/* ============================================= CHARGER_JEITA_V_REPLENISH_REG ============================================= */
+#define CHARGER_CHARGER_JEITA_V_REPLENISH_REG_V_REPLENISH_TWARM_Pos (6UL) /*!< V_REPLENISH_TWARM (Bit 6) */
+#define CHARGER_CHARGER_JEITA_V_REPLENISH_REG_V_REPLENISH_TWARM_Msk (0xfc0UL) /*!< V_REPLENISH_TWARM (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_JEITA_V_REPLENISH_REG_V_REPLENISH_TCOOL_Pos (0UL) /*!< V_REPLENISH_TCOOL (Bit 0) */
+#define CHARGER_CHARGER_JEITA_V_REPLENISH_REG_V_REPLENISH_TCOOL_Msk (0x3fUL) /*!< V_REPLENISH_TCOOL (Bitfield-Mask: 0x3f) */
+/* ============================================= CHARGER_PRE_CHARGE_TIMER_REG ============================================== */
+#define CHARGER_CHARGER_PRE_CHARGE_TIMER_REG_PRE_CHARGE_TIMER_Pos (16UL) /*!< PRE_CHARGE_TIMER (Bit 16) */
+#define CHARGER_CHARGER_PRE_CHARGE_TIMER_REG_PRE_CHARGE_TIMER_Msk (0x7fff0000UL) /*!< PRE_CHARGE_TIMER (Bitfield-Mask: 0x7fff) */
+#define CHARGER_CHARGER_PRE_CHARGE_TIMER_REG_MAX_PRE_CHARGE_TIME_Pos (0UL) /*!< MAX_PRE_CHARGE_TIME (Bit 0) */
+#define CHARGER_CHARGER_PRE_CHARGE_TIMER_REG_MAX_PRE_CHARGE_TIME_Msk (0x7fffUL) /*!< MAX_PRE_CHARGE_TIME (Bitfield-Mask: 0x7fff) */
+/* =============================================== CHARGER_PWR_UP_TIMER_REG ================================================ */
+#define CHARGER_CHARGER_PWR_UP_TIMER_REG_CHARGER_PWR_UP_TIMER_Pos (16UL) /*!< CHARGER_PWR_UP_TIMER (Bit 16) */
+#define CHARGER_CHARGER_PWR_UP_TIMER_REG_CHARGER_PWR_UP_TIMER_Msk (0x3ff0000UL) /*!< CHARGER_PWR_UP_TIMER (Bitfield-Mask: 0x3ff) */
+#define CHARGER_CHARGER_PWR_UP_TIMER_REG_CHARGER_PWR_UP_SETTLING_Pos (0UL) /*!< CHARGER_PWR_UP_SETTLING (Bit 0) */
+#define CHARGER_CHARGER_PWR_UP_TIMER_REG_CHARGER_PWR_UP_SETTLING_Msk (0x3ffUL) /*!< CHARGER_PWR_UP_SETTLING (Bitfield-Mask: 0x3ff) */
+/* =============================================== CHARGER_STATE_IRQ_CLR_REG =============================================== */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_PRECHARGE_IRQ_CLR_Pos (11UL) /*!< CV_TO_PRECHARGE_IRQ_CLR (Bit 11) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_PRECHARGE_IRQ_CLR_Msk (0x800UL) /*!< CV_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_PRECHARGE_IRQ_CLR_Pos (10UL) /*!< CC_TO_PRECHARGE_IRQ_CLR (Bit 10) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_PRECHARGE_IRQ_CLR_Msk (0x400UL) /*!< CC_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_CC_IRQ_CLR_Pos (9UL) /*!< CV_TO_CC_IRQ_CLR (Bit 9) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_CC_IRQ_CLR_Msk (0x200UL) /*!< CV_TO_CC_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TBAT_STATUS_UPDATE_IRQ_CLR_Pos (8UL) /*!< TBAT_STATUS_UPDATE_IRQ_CLR (Bit 8) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TBAT_STATUS_UPDATE_IRQ_CLR_Msk (0x100UL) /*!< TBAT_STATUS_UPDATE_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TBAT_PROT_TO_PRECHARGE_IRQ_CLR_Pos (7UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ_CLR (Bit 7) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TBAT_PROT_TO_PRECHARGE_IRQ_CLR_Msk (0x80UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TDIE_PROT_TO_PRECHARGE_IRQ_CLR_Pos (6UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ_CLR (Bit 6) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_TDIE_PROT_TO_PRECHARGE_IRQ_CLR_Msk (0x40UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_EOC_TO_PRECHARGE_IRQ_CLR_Pos (5UL) /*!< EOC_TO_PRECHARGE_IRQ_CLR (Bit 5) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_EOC_TO_PRECHARGE_IRQ_CLR_Msk (0x20UL) /*!< EOC_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_EOC_IRQ_CLR_Pos (4UL) /*!< CV_TO_EOC_IRQ_CLR (Bit 4) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CV_TO_EOC_IRQ_CLR_Msk (0x10UL) /*!< CV_TO_EOC_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_EOC_IRQ_CLR_Pos (3UL) /*!< CC_TO_EOC_IRQ_CLR (Bit 3) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_EOC_IRQ_CLR_Msk (0x8UL) /*!< CC_TO_EOC_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_CV_IRQ_CLR_Pos (2UL) /*!< CC_TO_CV_IRQ_CLR (Bit 2) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_CC_TO_CV_IRQ_CLR_Msk (0x4UL) /*!< CC_TO_CV_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_PRECHARGE_TO_CC_IRQ_CLR_Pos (1UL) /*!< PRECHARGE_TO_CC_IRQ_CLR (Bit 1) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_PRECHARGE_TO_CC_IRQ_CLR_Msk (0x2UL) /*!< PRECHARGE_TO_CC_IRQ_CLR (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_DISABLED_TO_PRECHARGE_IRQ_CLR_Pos (0UL) /*!< DISABLED_TO_PRECHARGE_IRQ_CLR (Bit 0) */
+#define CHARGER_CHARGER_STATE_IRQ_CLR_REG_DISABLED_TO_PRECHARGE_IRQ_CLR_Msk (0x1UL) /*!< DISABLED_TO_PRECHARGE_IRQ_CLR (Bitfield-Mask: 0x01) */
+/* ============================================== CHARGER_STATE_IRQ_MASK_REG =============================================== */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_PRECHARGE_IRQ_EN_Pos (11UL) /*!< CV_TO_PRECHARGE_IRQ_EN (Bit 11) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_PRECHARGE_IRQ_EN_Msk (0x800UL) /*!< CV_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_PRECHARGE_IRQ_EN_Pos (10UL) /*!< CC_TO_PRECHARGE_IRQ_EN (Bit 10) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_PRECHARGE_IRQ_EN_Msk (0x400UL) /*!< CC_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_CC_IRQ_EN_Pos (9UL) /*!< CV_TO_CC_IRQ_EN (Bit 9) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_CC_IRQ_EN_Msk (0x200UL) /*!< CV_TO_CC_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TBAT_STATUS_UPDATE_IRQ_EN_Pos (8UL) /*!< TBAT_STATUS_UPDATE_IRQ_EN (Bit 8) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TBAT_STATUS_UPDATE_IRQ_EN_Msk (0x100UL) /*!< TBAT_STATUS_UPDATE_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TBAT_PROT_TO_PRECHARGE_IRQ_EN_Pos (7UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ_EN (Bit 7) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TBAT_PROT_TO_PRECHARGE_IRQ_EN_Msk (0x80UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TDIE_PROT_TO_PRECHARGE_IRQ_EN_Pos (6UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ_EN (Bit 6) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_TDIE_PROT_TO_PRECHARGE_IRQ_EN_Msk (0x40UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_EOC_TO_PRECHARGE_IRQ_EN_Pos (5UL) /*!< EOC_TO_PRECHARGE_IRQ_EN (Bit 5) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_EOC_TO_PRECHARGE_IRQ_EN_Msk (0x20UL) /*!< EOC_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_EOC_IRQ_EN_Pos (4UL) /*!< CV_TO_EOC_IRQ_EN (Bit 4) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CV_TO_EOC_IRQ_EN_Msk (0x10UL) /*!< CV_TO_EOC_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_EOC_IRQ_EN_Pos (3UL) /*!< CC_TO_EOC_IRQ_EN (Bit 3) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_EOC_IRQ_EN_Msk (0x8UL) /*!< CC_TO_EOC_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_CV_IRQ_EN_Pos (2UL) /*!< CC_TO_CV_IRQ_EN (Bit 2) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_CC_TO_CV_IRQ_EN_Msk (0x4UL) /*!< CC_TO_CV_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_PRECHARGE_TO_CC_IRQ_EN_Pos (1UL) /*!< PRECHARGE_TO_CC_IRQ_EN (Bit 1) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_PRECHARGE_TO_CC_IRQ_EN_Msk (0x2UL) /*!< PRECHARGE_TO_CC_IRQ_EN (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_DISABLED_TO_PRECHARGE_IRQ_EN_Pos (0UL) /*!< DISABLED_TO_PRECHARGE_IRQ_EN (Bit 0) */
+#define CHARGER_CHARGER_STATE_IRQ_MASK_REG_DISABLED_TO_PRECHARGE_IRQ_EN_Msk (0x1UL) /*!< DISABLED_TO_PRECHARGE_IRQ_EN (Bitfield-Mask: 0x01) */
+/* ============================================= CHARGER_STATE_IRQ_STATUS_REG ============================================== */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_PRECHARGE_IRQ_Pos (11UL) /*!< CV_TO_PRECHARGE_IRQ (Bit 11) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_PRECHARGE_IRQ_Msk (0x800UL) /*!< CV_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_PRECHARGE_IRQ_Pos (10UL) /*!< CC_TO_PRECHARGE_IRQ (Bit 10) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_PRECHARGE_IRQ_Msk (0x400UL) /*!< CC_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_CC_IRQ_Pos (9UL) /*!< CV_TO_CC_IRQ (Bit 9) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_CC_IRQ_Msk (0x200UL) /*!< CV_TO_CC_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TBAT_STATUS_UPDATE_IRQ_Pos (8UL) /*!< TBAT_STATUS_UPDATE_IRQ (Bit 8) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TBAT_STATUS_UPDATE_IRQ_Msk (0x100UL) /*!< TBAT_STATUS_UPDATE_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TBAT_PROT_TO_PRECHARGE_IRQ_Pos (7UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ (Bit 7) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TBAT_PROT_TO_PRECHARGE_IRQ_Msk (0x80UL) /*!< TBAT_PROT_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TDIE_PROT_TO_PRECHARGE_IRQ_Pos (6UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ (Bit 6) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_TDIE_PROT_TO_PRECHARGE_IRQ_Msk (0x40UL) /*!< TDIE_PROT_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_EOC_TO_PRECHARGE_IRQ_Pos (5UL) /*!< EOC_TO_PRECHARGE_IRQ (Bit 5) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_EOC_TO_PRECHARGE_IRQ_Msk (0x20UL) /*!< EOC_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_EOC_IRQ_Pos (4UL) /*!< CV_TO_EOC_IRQ (Bit 4) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CV_TO_EOC_IRQ_Msk (0x10UL) /*!< CV_TO_EOC_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_EOC_IRQ_Pos (3UL) /*!< CC_TO_EOC_IRQ (Bit 3) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_EOC_IRQ_Msk (0x8UL) /*!< CC_TO_EOC_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_CV_IRQ_Pos (2UL) /*!< CC_TO_CV_IRQ (Bit 2) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_CC_TO_CV_IRQ_Msk (0x4UL) /*!< CC_TO_CV_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_PRECHARGE_TO_CC_IRQ_Pos (1UL) /*!< PRECHARGE_TO_CC_IRQ (Bit 1) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_PRECHARGE_TO_CC_IRQ_Msk (0x2UL) /*!< PRECHARGE_TO_CC_IRQ (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_DISABLED_TO_PRECHARGE_IRQ_Pos (0UL) /*!< DISABLED_TO_PRECHARGE_IRQ (Bit 0) */
+#define CHARGER_CHARGER_STATE_IRQ_STATUS_REG_DISABLED_TO_PRECHARGE_IRQ_Msk (0x1UL) /*!< DISABLED_TO_PRECHARGE_IRQ (Bitfield-Mask: 0x01) */
+/* ================================================== CHARGER_STATUS_REG =================================================== */
+#define CHARGER_CHARGER_STATUS_REG_OVP_EVENTS_DEBOUNCE_CNT_Pos (27UL) /*!< OVP_EVENTS_DEBOUNCE_CNT (Bit 27) */
+#define CHARGER_CHARGER_STATUS_REG_OVP_EVENTS_DEBOUNCE_CNT_Msk (0x38000000UL) /*!< OVP_EVENTS_DEBOUNCE_CNT (Bitfield-Mask: 0x07) */
+#define CHARGER_CHARGER_STATUS_REG_EOC_EVENTS_DEBOUNCE_CNT_Pos (24UL) /*!< EOC_EVENTS_DEBOUNCE_CNT (Bit 24) */
+#define CHARGER_CHARGER_STATUS_REG_EOC_EVENTS_DEBOUNCE_CNT_Msk (0x7000000UL) /*!< EOC_EVENTS_DEBOUNCE_CNT (Bitfield-Mask: 0x07) */
+#define CHARGER_CHARGER_STATUS_REG_TDIE_ERROR_DEBOUNCE_CNT_Pos (21UL) /*!< TDIE_ERROR_DEBOUNCE_CNT (Bit 21) */
+#define CHARGER_CHARGER_STATUS_REG_TDIE_ERROR_DEBOUNCE_CNT_Msk (0xe00000UL) /*!< TDIE_ERROR_DEBOUNCE_CNT (Bitfield-Mask: 0x07) */
+#define CHARGER_CHARGER_STATUS_REG_CHARGER_JEITA_STATE_Pos (18UL) /*!< CHARGER_JEITA_STATE (Bit 18) */
+#define CHARGER_CHARGER_STATUS_REG_CHARGER_JEITA_STATE_Msk (0x1c0000UL) /*!< CHARGER_JEITA_STATE (Bitfield-Mask: 0x07) */
+#define CHARGER_CHARGER_STATUS_REG_CHARGER_STATE_Pos (14UL) /*!< CHARGER_STATE (Bit 14) */
+#define CHARGER_CHARGER_STATUS_REG_CHARGER_STATE_Msk (0x3c000UL) /*!< CHARGER_STATE (Bitfield-Mask: 0x0f) */
+#define CHARGER_CHARGER_STATUS_REG_TBAT_STATUS_Pos (9UL) /*!< TBAT_STATUS (Bit 9) */
+#define CHARGER_CHARGER_STATUS_REG_TBAT_STATUS_Msk (0x3e00UL) /*!< TBAT_STATUS (Bitfield-Mask: 0x1f) */
+#define CHARGER_CHARGER_STATUS_REG_MAIN_TBAT_COMP_OUT_Pos (8UL) /*!< MAIN_TBAT_COMP_OUT (Bit 8) */
+#define CHARGER_CHARGER_STATUS_REG_MAIN_TBAT_COMP_OUT_Msk (0x100UL) /*!< MAIN_TBAT_COMP_OUT (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATUS_REG_TBAT_HOT_COMP_OUT_Pos (7UL) /*!< TBAT_HOT_COMP_OUT (Bit 7) */
+#define CHARGER_CHARGER_STATUS_REG_TBAT_HOT_COMP_OUT_Msk (0x80UL) /*!< TBAT_HOT_COMP_OUT (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATUS_REG_TDIE_COMP_OUT_Pos (6UL) /*!< TDIE_COMP_OUT (Bit 6) */
+#define CHARGER_CHARGER_STATUS_REG_TDIE_COMP_OUT_Msk (0x40UL) /*!< TDIE_COMP_OUT (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATUS_REG_VBAT_OVP_COMP_OUT_Pos (5UL) /*!< VBAT_OVP_COMP_OUT (Bit 5) */
+#define CHARGER_CHARGER_STATUS_REG_VBAT_OVP_COMP_OUT_Msk (0x20UL) /*!< VBAT_OVP_COMP_OUT (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATUS_REG_MAIN_VBAT_COMP_OUT_Pos (4UL) /*!< MAIN_VBAT_COMP_OUT (Bit 4) */
+#define CHARGER_CHARGER_STATUS_REG_MAIN_VBAT_COMP_OUT_Msk (0x10UL) /*!< MAIN_VBAT_COMP_OUT (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATUS_REG_END_OF_CHARGE_Pos (3UL) /*!< END_OF_CHARGE (Bit 3) */
+#define CHARGER_CHARGER_STATUS_REG_END_OF_CHARGE_Msk (0x8UL) /*!< END_OF_CHARGE (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATUS_REG_CHARGER_CV_MODE_Pos (2UL) /*!< CHARGER_CV_MODE (Bit 2) */
+#define CHARGER_CHARGER_STATUS_REG_CHARGER_CV_MODE_Msk (0x4UL) /*!< CHARGER_CV_MODE (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATUS_REG_CHARGER_CC_MODE_Pos (1UL) /*!< CHARGER_CC_MODE (Bit 1) */
+#define CHARGER_CHARGER_STATUS_REG_CHARGER_CC_MODE_Msk (0x2UL) /*!< CHARGER_CC_MODE (Bitfield-Mask: 0x01) */
+#define CHARGER_CHARGER_STATUS_REG_CHARGER_IS_POWERED_UP_Pos (0UL) /*!< CHARGER_IS_POWERED_UP (Bit 0) */
+#define CHARGER_CHARGER_STATUS_REG_CHARGER_IS_POWERED_UP_Msk (0x1UL) /*!< CHARGER_IS_POWERED_UP (Bitfield-Mask: 0x01) */
+/* ============================================== CHARGER_TBAT_COMP_TIMER_REG ============================================== */
+#define CHARGER_CHARGER_TBAT_COMP_TIMER_REG_TBAT_COMP_TIMER_Pos (16UL) /*!< TBAT_COMP_TIMER (Bit 16) */
+#define CHARGER_CHARGER_TBAT_COMP_TIMER_REG_TBAT_COMP_TIMER_Msk (0x3ff0000UL) /*!< TBAT_COMP_TIMER (Bitfield-Mask: 0x3ff) */
+#define CHARGER_CHARGER_TBAT_COMP_TIMER_REG_TBAT_COMP_SETTLING_Pos (0UL) /*!< TBAT_COMP_SETTLING (Bit 0) */
+#define CHARGER_CHARGER_TBAT_COMP_TIMER_REG_TBAT_COMP_SETTLING_Msk (0x3ffUL) /*!< TBAT_COMP_SETTLING (Bitfield-Mask: 0x3ff) */
+/* ============================================== CHARGER_TBAT_MON_TIMER_REG =============================================== */
+#define CHARGER_CHARGER_TBAT_MON_TIMER_REG_TBAT_MON_TIMER_Pos (16UL) /*!< TBAT_MON_TIMER (Bit 16) */
+#define CHARGER_CHARGER_TBAT_MON_TIMER_REG_TBAT_MON_TIMER_Msk (0x3ff0000UL) /*!< TBAT_MON_TIMER (Bitfield-Mask: 0x3ff) */
+#define CHARGER_CHARGER_TBAT_MON_TIMER_REG_TBAT_MON_INTERVAL_Pos (0UL) /*!< TBAT_MON_INTERVAL (Bit 0) */
+#define CHARGER_CHARGER_TBAT_MON_TIMER_REG_TBAT_MON_INTERVAL_Msk (0x3ffUL) /*!< TBAT_MON_INTERVAL (Bitfield-Mask: 0x3ff) */
+/* ============================================== CHARGER_TDIE_COMP_TIMER_REG ============================================== */
+#define CHARGER_CHARGER_TDIE_COMP_TIMER_REG_TDIE_COMP_TIMER_Pos (16UL) /*!< TDIE_COMP_TIMER (Bit 16) */
+#define CHARGER_CHARGER_TDIE_COMP_TIMER_REG_TDIE_COMP_TIMER_Msk (0x3ff0000UL) /*!< TDIE_COMP_TIMER (Bitfield-Mask: 0x3ff) */
+#define CHARGER_CHARGER_TDIE_COMP_TIMER_REG_TDIE_COMP_SETTLING_Pos (0UL) /*!< TDIE_COMP_SETTLING (Bit 0) */
+#define CHARGER_CHARGER_TDIE_COMP_TIMER_REG_TDIE_COMP_SETTLING_Msk (0x3ffUL) /*!< TDIE_COMP_SETTLING (Bitfield-Mask: 0x3ff) */
+/* =============================================== CHARGER_TEMPSET_PARAM_REG =============================================== */
+#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TDIE_MAX_Pos (24UL) /*!< TDIE_MAX (Bit 24) */
+#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TDIE_MAX_Msk (0x7000000UL) /*!< TDIE_MAX (Bitfield-Mask: 0x07) */
+#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_HOT_Pos (18UL) /*!< TBAT_HOT (Bit 18) */
+#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_HOT_Msk (0xfc0000UL) /*!< TBAT_HOT (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_WARM_Pos (12UL) /*!< TBAT_WARM (Bit 12) */
+#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_WARM_Msk (0x3f000UL) /*!< TBAT_WARM (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_COOL_Pos (6UL) /*!< TBAT_COOL (Bit 6) */
+#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_COOL_Msk (0xfc0UL) /*!< TBAT_COOL (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_COLD_Pos (0UL) /*!< TBAT_COLD (Bit 0) */
+#define CHARGER_CHARGER_TEMPSET_PARAM_REG_TBAT_COLD_Msk (0x3fUL) /*!< TBAT_COLD (Bitfield-Mask: 0x3f) */
+/* ================================================= CHARGER_TEST_CTRL_REG ================================================= */
+/* ============================================== CHARGER_THOT_COMP_TIMER_REG ============================================== */
+#define CHARGER_CHARGER_THOT_COMP_TIMER_REG_THOT_COMP_TIMER_Pos (16UL) /*!< THOT_COMP_TIMER (Bit 16) */
+#define CHARGER_CHARGER_THOT_COMP_TIMER_REG_THOT_COMP_TIMER_Msk (0x3ff0000UL) /*!< THOT_COMP_TIMER (Bitfield-Mask: 0x3ff) */
+#define CHARGER_CHARGER_THOT_COMP_TIMER_REG_THOT_COMP_SETTLING_Pos (0UL) /*!< THOT_COMP_SETTLING (Bit 0) */
+#define CHARGER_CHARGER_THOT_COMP_TIMER_REG_THOT_COMP_SETTLING_Msk (0x3ffUL) /*!< THOT_COMP_SETTLING (Bitfield-Mask: 0x3ff) */
+/* ============================================ CHARGER_TOTAL_CHARGE_TIMER_REG ============================================= */
+#define CHARGER_CHARGER_TOTAL_CHARGE_TIMER_REG_TOTAL_CHARGE_TIMER_Pos (16UL) /*!< TOTAL_CHARGE_TIMER (Bit 16) */
+#define CHARGER_CHARGER_TOTAL_CHARGE_TIMER_REG_TOTAL_CHARGE_TIMER_Msk (0xffff0000UL) /*!< TOTAL_CHARGE_TIMER (Bitfield-Mask: 0xffff) */
+#define CHARGER_CHARGER_TOTAL_CHARGE_TIMER_REG_MAX_TOTAL_CHARGE_TIME_Pos (0UL) /*!< MAX_TOTAL_CHARGE_TIME (Bit 0) */
+#define CHARGER_CHARGER_TOTAL_CHARGE_TIMER_REG_MAX_TOTAL_CHARGE_TIME_Msk (0xffffUL) /*!< MAX_TOTAL_CHARGE_TIME (Bitfield-Mask: 0xffff) */
+/* ============================================== CHARGER_VBAT_COMP_TIMER_REG ============================================== */
+#define CHARGER_CHARGER_VBAT_COMP_TIMER_REG_VBAT_COMP_TIMER_Pos (16UL) /*!< VBAT_COMP_TIMER (Bit 16) */
+#define CHARGER_CHARGER_VBAT_COMP_TIMER_REG_VBAT_COMP_TIMER_Msk (0x3ff0000UL) /*!< VBAT_COMP_TIMER (Bitfield-Mask: 0x3ff) */
+#define CHARGER_CHARGER_VBAT_COMP_TIMER_REG_VBAT_COMP_SETTLING_Pos (0UL) /*!< VBAT_COMP_SETTLING (Bit 0) */
+#define CHARGER_CHARGER_VBAT_COMP_TIMER_REG_VBAT_COMP_SETTLING_Msk (0x3ffUL) /*!< VBAT_COMP_SETTLING (Bitfield-Mask: 0x3ff) */
+/* =============================================== CHARGER_VOLTAGE_PARAM_REG =============================================== */
+#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_OVP_Pos (18UL) /*!< V_OVP (Bit 18) */
+#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_OVP_Msk (0xfc0000UL) /*!< V_OVP (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_REPLENISH_Pos (12UL) /*!< V_REPLENISH (Bit 12) */
+#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_REPLENISH_Msk (0x3f000UL) /*!< V_REPLENISH (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_PRECHARGE_Pos (6UL) /*!< V_PRECHARGE (Bit 6) */
+#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_PRECHARGE_Msk (0xfc0UL) /*!< V_PRECHARGE (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_CHARGE_Pos (0UL) /*!< V_CHARGE (Bit 0) */
+#define CHARGER_CHARGER_VOLTAGE_PARAM_REG_V_CHARGE_Msk (0x3fUL) /*!< V_CHARGE (Bitfield-Mask: 0x3f) */
+/* ============================================== CHARGER_VOVP_COMP_TIMER_REG ============================================== */
+#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_OVP_INTERVAL_CHECK_TIMER_Pos (26UL) /*!< OVP_INTERVAL_CHECK_TIMER (Bit 26) */
+#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_OVP_INTERVAL_CHECK_TIMER_Msk (0xfc000000UL) /*!< OVP_INTERVAL_CHECK_TIMER (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_VBAT_OVP_COMP_TIMER_Pos (16UL) /*!< VBAT_OVP_COMP_TIMER (Bit 16) */
+#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_VBAT_OVP_COMP_TIMER_Msk (0x3ff0000UL) /*!< VBAT_OVP_COMP_TIMER (Bitfield-Mask: 0x3ff) */
+#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_OVP_INTERVAL_CHECK_THRES_Pos (10UL) /*!< OVP_INTERVAL_CHECK_THRES (Bit 10) */
+#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_OVP_INTERVAL_CHECK_THRES_Msk (0xfc00UL) /*!< OVP_INTERVAL_CHECK_THRES (Bitfield-Mask: 0x3f) */
+#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_VBAT_OVP_COMP_SETTLING_Pos (0UL) /*!< VBAT_OVP_COMP_SETTLING (Bit 0) */
+#define CHARGER_CHARGER_VOVP_COMP_TIMER_REG_VBAT_OVP_COMP_SETTLING_Msk (0x3ffUL) /*!< VBAT_OVP_COMP_SETTLING (Bitfield-Mask: 0x3ff) */
+
+
+/* =========================================================================================================================== */
+/* ================ CHIP_VERSION ================ */
+/* =========================================================================================================================== */
+
+/* ===================================================== CHIP_ID1_REG ====================================================== */
+#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Pos (0UL) /*!< CHIP_ID1 (Bit 0) */
+#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Msk (0xffUL) /*!< CHIP_ID1 (Bitfield-Mask: 0xff) */
+/* ===================================================== CHIP_ID2_REG ====================================================== */
+#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Pos (0UL) /*!< CHIP_ID2 (Bit 0) */
+#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Msk (0xffUL) /*!< CHIP_ID2 (Bitfield-Mask: 0xff) */
+/* ===================================================== CHIP_ID3_REG ====================================================== */
+#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Pos (0UL) /*!< CHIP_ID3 (Bit 0) */
+#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Msk (0xffUL) /*!< CHIP_ID3 (Bitfield-Mask: 0xff) */
+/* ===================================================== CHIP_ID4_REG ====================================================== */
+#define CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Pos (0UL) /*!< CHIP_ID4 (Bit 0) */
+#define CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Msk (0xffUL) /*!< CHIP_ID4 (Bitfield-Mask: 0xff) */
+/* =================================================== CHIP_REVISION_REG =================================================== */
+#define CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Pos (0UL) /*!< CHIP_REVISION (Bit 0) */
+#define CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Msk (0xffUL) /*!< CHIP_REVISION (Bitfield-Mask: 0xff) */
+/* ===================================================== CHIP_SWC_REG ====================================================== */
+#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Pos (0UL) /*!< CHIP_SWC (Bit 0) */
+#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Msk (0xfUL) /*!< CHIP_SWC (Bitfield-Mask: 0x0f) */
+/* ==================================================== CHIP_TEST1_REG ===================================================== */
+#define CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Pos (0UL) /*!< CHIP_LAYOUT_REVISION (Bit 0) */
+#define CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Msk (0xffUL) /*!< CHIP_LAYOUT_REVISION (Bitfield-Mask: 0xff) */
+/* ==================================================== CHIP_TEST2_REG ===================================================== */
+#define CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Pos (0UL) /*!< CHIP_METAL_OPTION (Bit 0) */
+#define CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Msk (0xfUL) /*!< CHIP_METAL_OPTION (Bitfield-Mask: 0x0f) */
+
+
+/* =========================================================================================================================== */
+/* ================ CRG_COM ================ */
+/* =========================================================================================================================== */
+
+/* ====================================================== CLK_COM_REG ====================================================== */
+#define CRG_COM_CLK_COM_REG_LCD_EXT_CLK_SEL_Pos (16UL) /*!< LCD_EXT_CLK_SEL (Bit 16) */
+#define CRG_COM_CLK_COM_REG_LCD_EXT_CLK_SEL_Msk (0x30000UL) /*!< LCD_EXT_CLK_SEL (Bitfield-Mask: 0x03) */
+#define CRG_COM_CLK_COM_REG_SNC_DIV_Pos (14UL) /*!< SNC_DIV (Bit 14) */
+#define CRG_COM_CLK_COM_REG_SNC_DIV_Msk (0xc000UL) /*!< SNC_DIV (Bitfield-Mask: 0x03) */
+#define CRG_COM_CLK_COM_REG_I2C2_CLK_SEL_Pos (12UL) /*!< I2C2_CLK_SEL (Bit 12) */
+#define CRG_COM_CLK_COM_REG_I2C2_CLK_SEL_Msk (0x1000UL) /*!< I2C2_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_CLK_COM_REG_I2C2_ENABLE_Pos (11UL) /*!< I2C2_ENABLE (Bit 11) */
+#define CRG_COM_CLK_COM_REG_I2C2_ENABLE_Msk (0x800UL) /*!< I2C2_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_CLK_COM_REG_I2C_CLK_SEL_Pos (10UL) /*!< I2C_CLK_SEL (Bit 10) */
+#define CRG_COM_CLK_COM_REG_I2C_CLK_SEL_Msk (0x400UL) /*!< I2C_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_CLK_COM_REG_I2C_ENABLE_Pos (9UL) /*!< I2C_ENABLE (Bit 9) */
+#define CRG_COM_CLK_COM_REG_I2C_ENABLE_Msk (0x200UL) /*!< I2C_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_CLK_COM_REG_SPI2_CLK_SEL_Pos (8UL) /*!< SPI2_CLK_SEL (Bit 8) */
+#define CRG_COM_CLK_COM_REG_SPI2_CLK_SEL_Msk (0x100UL) /*!< SPI2_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_CLK_COM_REG_SPI2_ENABLE_Pos (7UL) /*!< SPI2_ENABLE (Bit 7) */
+#define CRG_COM_CLK_COM_REG_SPI2_ENABLE_Msk (0x80UL) /*!< SPI2_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_CLK_COM_REG_SPI_CLK_SEL_Pos (6UL) /*!< SPI_CLK_SEL (Bit 6) */
+#define CRG_COM_CLK_COM_REG_SPI_CLK_SEL_Msk (0x40UL) /*!< SPI_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_CLK_COM_REG_SPI_ENABLE_Pos (5UL) /*!< SPI_ENABLE (Bit 5) */
+#define CRG_COM_CLK_COM_REG_SPI_ENABLE_Msk (0x20UL) /*!< SPI_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_CLK_COM_REG_UART3_CLK_SEL_Pos (4UL) /*!< UART3_CLK_SEL (Bit 4) */
+#define CRG_COM_CLK_COM_REG_UART3_CLK_SEL_Msk (0x10UL) /*!< UART3_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_CLK_COM_REG_UART3_ENABLE_Pos (3UL) /*!< UART3_ENABLE (Bit 3) */
+#define CRG_COM_CLK_COM_REG_UART3_ENABLE_Msk (0x8UL) /*!< UART3_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_CLK_COM_REG_UART2_CLK_SEL_Pos (2UL) /*!< UART2_CLK_SEL (Bit 2) */
+#define CRG_COM_CLK_COM_REG_UART2_CLK_SEL_Msk (0x4UL) /*!< UART2_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_CLK_COM_REG_UART2_ENABLE_Pos (1UL) /*!< UART2_ENABLE (Bit 1) */
+#define CRG_COM_CLK_COM_REG_UART2_ENABLE_Msk (0x2UL) /*!< UART2_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_CLK_COM_REG_UART_ENABLE_Pos (0UL) /*!< UART_ENABLE (Bit 0) */
+#define CRG_COM_CLK_COM_REG_UART_ENABLE_Msk (0x1UL) /*!< UART_ENABLE (Bitfield-Mask: 0x01) */
+/* =================================================== RESET_CLK_COM_REG =================================================== */
+#define CRG_COM_RESET_CLK_COM_REG_LCD_EXT_CLK_SEL_Pos (16UL) /*!< LCD_EXT_CLK_SEL (Bit 16) */
+#define CRG_COM_RESET_CLK_COM_REG_LCD_EXT_CLK_SEL_Msk (0x30000UL) /*!< LCD_EXT_CLK_SEL (Bitfield-Mask: 0x03) */
+#define CRG_COM_RESET_CLK_COM_REG_SNC_DIV_Pos (14UL) /*!< SNC_DIV (Bit 14) */
+#define CRG_COM_RESET_CLK_COM_REG_SNC_DIV_Msk (0xc000UL) /*!< SNC_DIV (Bitfield-Mask: 0x03) */
+#define CRG_COM_RESET_CLK_COM_REG_I2C2_CLK_SEL_Pos (12UL) /*!< I2C2_CLK_SEL (Bit 12) */
+#define CRG_COM_RESET_CLK_COM_REG_I2C2_CLK_SEL_Msk (0x1000UL) /*!< I2C2_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_RESET_CLK_COM_REG_I2C2_ENABLE_Pos (11UL) /*!< I2C2_ENABLE (Bit 11) */
+#define CRG_COM_RESET_CLK_COM_REG_I2C2_ENABLE_Msk (0x800UL) /*!< I2C2_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Pos (10UL) /*!< I2C_CLK_SEL (Bit 10) */
+#define CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Msk (0x400UL) /*!< I2C_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Pos (9UL) /*!< I2C_ENABLE (Bit 9) */
+#define CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Msk (0x200UL) /*!< I2C_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_RESET_CLK_COM_REG_SPI2_CLK_SEL_Pos (8UL) /*!< SPI2_CLK_SEL (Bit 8) */
+#define CRG_COM_RESET_CLK_COM_REG_SPI2_CLK_SEL_Msk (0x100UL) /*!< SPI2_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_RESET_CLK_COM_REG_SPI2_ENABLE_Pos (7UL) /*!< SPI2_ENABLE (Bit 7) */
+#define CRG_COM_RESET_CLK_COM_REG_SPI2_ENABLE_Msk (0x80UL) /*!< SPI2_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Pos (6UL) /*!< SPI_CLK_SEL (Bit 6) */
+#define CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Msk (0x40UL) /*!< SPI_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Pos (5UL) /*!< SPI_ENABLE (Bit 5) */
+#define CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Msk (0x20UL) /*!< SPI_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_RESET_CLK_COM_REG_UART3_CLK_SEL_Pos (4UL) /*!< UART3_CLK_SEL (Bit 4) */
+#define CRG_COM_RESET_CLK_COM_REG_UART3_CLK_SEL_Msk (0x10UL) /*!< UART3_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_RESET_CLK_COM_REG_UART3_ENABLE_Pos (3UL) /*!< UART3_ENABLE (Bit 3) */
+#define CRG_COM_RESET_CLK_COM_REG_UART3_ENABLE_Msk (0x8UL) /*!< UART3_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_RESET_CLK_COM_REG_UART2_CLK_SEL_Pos (2UL) /*!< UART2_CLK_SEL (Bit 2) */
+#define CRG_COM_RESET_CLK_COM_REG_UART2_CLK_SEL_Msk (0x4UL) /*!< UART2_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_RESET_CLK_COM_REG_UART2_ENABLE_Pos (1UL) /*!< UART2_ENABLE (Bit 1) */
+#define CRG_COM_RESET_CLK_COM_REG_UART2_ENABLE_Msk (0x2UL) /*!< UART2_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_RESET_CLK_COM_REG_UART_ENABLE_Pos (0UL) /*!< UART_ENABLE (Bit 0) */
+#define CRG_COM_RESET_CLK_COM_REG_UART_ENABLE_Msk (0x1UL) /*!< UART_ENABLE (Bitfield-Mask: 0x01) */
+/* ==================================================== SET_CLK_COM_REG ==================================================== */
+#define CRG_COM_SET_CLK_COM_REG_LCD_EXT_CLK_SEL_Pos (16UL) /*!< LCD_EXT_CLK_SEL (Bit 16) */
+#define CRG_COM_SET_CLK_COM_REG_LCD_EXT_CLK_SEL_Msk (0x30000UL) /*!< LCD_EXT_CLK_SEL (Bitfield-Mask: 0x03) */
+#define CRG_COM_SET_CLK_COM_REG_SNC_DIV_Pos (14UL) /*!< SNC_DIV (Bit 14) */
+#define CRG_COM_SET_CLK_COM_REG_SNC_DIV_Msk (0xc000UL) /*!< SNC_DIV (Bitfield-Mask: 0x03) */
+#define CRG_COM_SET_CLK_COM_REG_I2C2_CLK_SEL_Pos (12UL) /*!< I2C2_CLK_SEL (Bit 12) */
+#define CRG_COM_SET_CLK_COM_REG_I2C2_CLK_SEL_Msk (0x1000UL) /*!< I2C2_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_SET_CLK_COM_REG_I2C2_ENABLE_Pos (11UL) /*!< I2C2_ENABLE (Bit 11) */
+#define CRG_COM_SET_CLK_COM_REG_I2C2_ENABLE_Msk (0x800UL) /*!< I2C2_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Pos (10UL) /*!< I2C_CLK_SEL (Bit 10) */
+#define CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Msk (0x400UL) /*!< I2C_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Pos (9UL) /*!< I2C_ENABLE (Bit 9) */
+#define CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Msk (0x200UL) /*!< I2C_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_SET_CLK_COM_REG_SPI2_CLK_SEL_Pos (8UL) /*!< SPI2_CLK_SEL (Bit 8) */
+#define CRG_COM_SET_CLK_COM_REG_SPI2_CLK_SEL_Msk (0x100UL) /*!< SPI2_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_SET_CLK_COM_REG_SPI2_ENABLE_Pos (7UL) /*!< SPI2_ENABLE (Bit 7) */
+#define CRG_COM_SET_CLK_COM_REG_SPI2_ENABLE_Msk (0x80UL) /*!< SPI2_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Pos (6UL) /*!< SPI_CLK_SEL (Bit 6) */
+#define CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Msk (0x40UL) /*!< SPI_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Pos (5UL) /*!< SPI_ENABLE (Bit 5) */
+#define CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Msk (0x20UL) /*!< SPI_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_SET_CLK_COM_REG_UART3_CLK_SEL_Pos (4UL) /*!< UART3_CLK_SEL (Bit 4) */
+#define CRG_COM_SET_CLK_COM_REG_UART3_CLK_SEL_Msk (0x10UL) /*!< UART3_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_SET_CLK_COM_REG_UART3_ENABLE_Pos (3UL) /*!< UART3_ENABLE (Bit 3) */
+#define CRG_COM_SET_CLK_COM_REG_UART3_ENABLE_Msk (0x8UL) /*!< UART3_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_SET_CLK_COM_REG_UART2_CLK_SEL_Pos (2UL) /*!< UART2_CLK_SEL (Bit 2) */
+#define CRG_COM_SET_CLK_COM_REG_UART2_CLK_SEL_Msk (0x4UL) /*!< UART2_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_COM_SET_CLK_COM_REG_UART2_ENABLE_Pos (1UL) /*!< UART2_ENABLE (Bit 1) */
+#define CRG_COM_SET_CLK_COM_REG_UART2_ENABLE_Msk (0x2UL) /*!< UART2_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_COM_SET_CLK_COM_REG_UART_ENABLE_Pos (0UL) /*!< UART_ENABLE (Bit 0) */
+#define CRG_COM_SET_CLK_COM_REG_UART_ENABLE_Msk (0x1UL) /*!< UART_ENABLE (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CRG_PER ================ */
+/* =========================================================================================================================== */
+
+/* ====================================================== CLK_PER_REG ====================================================== */
+#define CRG_PER_CLK_PER_REG_MC_TRIG_DIV_Pos (8UL) /*!< MC_TRIG_DIV (Bit 8) */
+#define CRG_PER_CLK_PER_REG_MC_TRIG_DIV_Msk (0x1f00UL) /*!< MC_TRIG_DIV (Bitfield-Mask: 0x1f) */
+#define CRG_PER_CLK_PER_REG_MC_CLK_DIV_Pos (3UL) /*!< MC_CLK_DIV (Bit 3) */
+#define CRG_PER_CLK_PER_REG_MC_CLK_DIV_Msk (0xf8UL) /*!< MC_CLK_DIV (Bitfield-Mask: 0x1f) */
+#define CRG_PER_CLK_PER_REG_MC_CLK_EN_Pos (2UL) /*!< MC_CLK_EN (Bit 2) */
+#define CRG_PER_CLK_PER_REG_MC_CLK_EN_Msk (0x4UL) /*!< MC_CLK_EN (Bitfield-Mask: 0x01) */
+#define CRG_PER_CLK_PER_REG_LRA_CLK_EN_Pos (1UL) /*!< LRA_CLK_EN (Bit 1) */
+#define CRG_PER_CLK_PER_REG_LRA_CLK_EN_Msk (0x2UL) /*!< LRA_CLK_EN (Bitfield-Mask: 0x01) */
+#define CRG_PER_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL) /*!< GPADC_CLK_SEL (Bit 0) */
+#define CRG_PER_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL) /*!< GPADC_CLK_SEL (Bitfield-Mask: 0x01) */
+/* ====================================================== PCM_DIV_REG ====================================================== */
+#define CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Pos (13UL) /*!< PCM_SRC_SEL (Bit 13) */
+#define CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Msk (0x2000UL) /*!< PCM_SRC_SEL (Bitfield-Mask: 0x01) */
+#define CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Pos (12UL) /*!< CLK_PCM_EN (Bit 12) */
+#define CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Msk (0x1000UL) /*!< CLK_PCM_EN (Bitfield-Mask: 0x01) */
+#define CRG_PER_PCM_DIV_REG_PCM_DIV_Pos (0UL) /*!< PCM_DIV (Bit 0) */
+#define CRG_PER_PCM_DIV_REG_PCM_DIV_Msk (0xfffUL) /*!< PCM_DIV (Bitfield-Mask: 0xfff) */
+/* ===================================================== PCM_FDIV_REG ====================================================== */
+#define CRG_PER_PCM_FDIV_REG_PCM_FDIV_Pos (0UL) /*!< PCM_FDIV (Bit 0) */
+#define CRG_PER_PCM_FDIV_REG_PCM_FDIV_Msk (0xffffUL) /*!< PCM_FDIV (Bitfield-Mask: 0xffff) */
+/* ====================================================== PDM_DIV_REG ====================================================== */
+#define CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Pos (9UL) /*!< PDM_MASTER_MODE (Bit 9) */
+#define CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Msk (0x200UL) /*!< PDM_MASTER_MODE (Bitfield-Mask: 0x01) */
+#define CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Pos (8UL) /*!< CLK_PDM_EN (Bit 8) */
+#define CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Msk (0x100UL) /*!< CLK_PDM_EN (Bitfield-Mask: 0x01) */
+#define CRG_PER_PDM_DIV_REG_PDM_DIV_Pos (0UL) /*!< PDM_DIV (Bit 0) */
+#define CRG_PER_PDM_DIV_REG_PDM_DIV_Msk (0xffUL) /*!< PDM_DIV (Bitfield-Mask: 0xff) */
+/* =================================================== RESET_CLK_PER_REG =================================================== */
+#define CRG_PER_RESET_CLK_PER_REG_MC_TRIG_DIV_Pos (8UL) /*!< MC_TRIG_DIV (Bit 8) */
+#define CRG_PER_RESET_CLK_PER_REG_MC_TRIG_DIV_Msk (0x1f00UL) /*!< MC_TRIG_DIV (Bitfield-Mask: 0x1f) */
+#define CRG_PER_RESET_CLK_PER_REG_MC_CLK_DIV_Pos (3UL) /*!< MC_CLK_DIV (Bit 3) */
+#define CRG_PER_RESET_CLK_PER_REG_MC_CLK_DIV_Msk (0xf8UL) /*!< MC_CLK_DIV (Bitfield-Mask: 0x1f) */
+#define CRG_PER_RESET_CLK_PER_REG_MC_CLK_EN_Pos (2UL) /*!< MC_CLK_EN (Bit 2) */
+#define CRG_PER_RESET_CLK_PER_REG_MC_CLK_EN_Msk (0x4UL) /*!< MC_CLK_EN (Bitfield-Mask: 0x01) */
+#define CRG_PER_RESET_CLK_PER_REG_LRA_CLK_EN_Pos (1UL) /*!< LRA_CLK_EN (Bit 1) */
+#define CRG_PER_RESET_CLK_PER_REG_LRA_CLK_EN_Msk (0x2UL) /*!< LRA_CLK_EN (Bitfield-Mask: 0x01) */
+#define CRG_PER_RESET_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL) /*!< GPADC_CLK_SEL (Bit 0) */
+#define CRG_PER_RESET_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL) /*!< GPADC_CLK_SEL (Bitfield-Mask: 0x01) */
+/* ==================================================== SET_CLK_PER_REG ==================================================== */
+#define CRG_PER_SET_CLK_PER_REG_MC_TRIG_DIV_Pos (8UL) /*!< MC_TRIG_DIV (Bit 8) */
+#define CRG_PER_SET_CLK_PER_REG_MC_TRIG_DIV_Msk (0x1f00UL) /*!< MC_TRIG_DIV (Bitfield-Mask: 0x1f) */
+#define CRG_PER_SET_CLK_PER_REG_MC_CLK_DIV_Pos (3UL) /*!< MC_CLK_DIV (Bit 3) */
+#define CRG_PER_SET_CLK_PER_REG_MC_CLK_DIV_Msk (0xf8UL) /*!< MC_CLK_DIV (Bitfield-Mask: 0x1f) */
+#define CRG_PER_SET_CLK_PER_REG_MC_CLK_EN_Pos (2UL) /*!< MC_CLK_EN (Bit 2) */
+#define CRG_PER_SET_CLK_PER_REG_MC_CLK_EN_Msk (0x4UL) /*!< MC_CLK_EN (Bitfield-Mask: 0x01) */
+#define CRG_PER_SET_CLK_PER_REG_LRA_CLK_EN_Pos (1UL) /*!< LRA_CLK_EN (Bit 1) */
+#define CRG_PER_SET_CLK_PER_REG_LRA_CLK_EN_Msk (0x2UL) /*!< LRA_CLK_EN (Bitfield-Mask: 0x01) */
+#define CRG_PER_SET_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL) /*!< GPADC_CLK_SEL (Bit 0) */
+#define CRG_PER_SET_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL) /*!< GPADC_CLK_SEL (Bitfield-Mask: 0x01) */
+/* ====================================================== SRC_DIV_REG ====================================================== */
+#define CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Pos (8UL) /*!< CLK_SRC_EN (Bit 8) */
+#define CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Msk (0x100UL) /*!< CLK_SRC_EN (Bitfield-Mask: 0x01) */
+#define CRG_PER_SRC_DIV_REG_SRC_DIV_Pos (0UL) /*!< SRC_DIV (Bit 0) */
+#define CRG_PER_SRC_DIV_REG_SRC_DIV_Msk (0xffUL) /*!< SRC_DIV (Bitfield-Mask: 0xff) */
+
+
+/* =========================================================================================================================== */
+/* ================ CRG_SYS ================ */
+/* =========================================================================================================================== */
+
+/* ===================================================== BATCHECK_REG ====================================================== */
+#define CRG_SYS_BATCHECK_REG_BATCHECK_LOAD_ENABLE_Pos (7UL) /*!< BATCHECK_LOAD_ENABLE (Bit 7) */
+#define CRG_SYS_BATCHECK_REG_BATCHECK_LOAD_ENABLE_Msk (0x80UL) /*!< BATCHECK_LOAD_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_SYS_BATCHECK_REG_BATCHECK_ILOAD_Pos (4UL) /*!< BATCHECK_ILOAD (Bit 4) */
+#define CRG_SYS_BATCHECK_REG_BATCHECK_ILOAD_Msk (0x70UL) /*!< BATCHECK_ILOAD (Bitfield-Mask: 0x07) */
+#define CRG_SYS_BATCHECK_REG_BATCHECK_TRIM_Pos (0UL) /*!< BATCHECK_TRIM (Bit 0) */
+#define CRG_SYS_BATCHECK_REG_BATCHECK_TRIM_Msk (0xfUL) /*!< BATCHECK_TRIM (Bitfield-Mask: 0x0f) */
+/* ====================================================== CLK_SYS_REG ====================================================== */
+#define CRG_SYS_CLK_SYS_REG_CLK_CHG_EN_Pos (5UL) /*!< CLK_CHG_EN (Bit 5) */
+#define CRG_SYS_CLK_SYS_REG_CLK_CHG_EN_Msk (0x20UL) /*!< CLK_CHG_EN (Bitfield-Mask: 0x01) */
+#define CRG_SYS_CLK_SYS_REG_LCD_RESET_REQ_Pos (4UL) /*!< LCD_RESET_REQ (Bit 4) */
+#define CRG_SYS_CLK_SYS_REG_LCD_RESET_REQ_Msk (0x10UL) /*!< LCD_RESET_REQ (Bitfield-Mask: 0x01) */
+#define CRG_SYS_CLK_SYS_REG_LCD_CLK_SEL_Pos (1UL) /*!< LCD_CLK_SEL (Bit 1) */
+#define CRG_SYS_CLK_SYS_REG_LCD_CLK_SEL_Msk (0x2UL) /*!< LCD_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_SYS_CLK_SYS_REG_LCD_ENABLE_Pos (0UL) /*!< LCD_ENABLE (Bit 0) */
+#define CRG_SYS_CLK_SYS_REG_LCD_ENABLE_Msk (0x1UL) /*!< LCD_ENABLE (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CRG_TOP ================ */
+/* =========================================================================================================================== */
+
+/* ==================================================== ANA_STATUS_REG ===================================================== */
+#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Pos (14UL) /*!< COMP_VBUS_HIGH (Bit 14) */
+#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Msk (0x4000UL) /*!< COMP_VBUS_HIGH (Bitfield-Mask: 0x01) */
+#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Pos (13UL) /*!< COMP_VBUS_LOW (Bit 13) */
+#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Msk (0x2000UL) /*!< COMP_VBUS_LOW (Bitfield-Mask: 0x01) */
+#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_HIGH_Pos (12UL) /*!< COMP_VBAT_HIGH (Bit 12) */
+#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_HIGH_Msk (0x1000UL) /*!< COMP_VBAT_HIGH (Bitfield-Mask: 0x01) */
+#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_LOW_Pos (11UL) /*!< COMP_VBAT_LOW (Bit 11) */
+#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_LOW_Msk (0x800UL) /*!< COMP_VBAT_LOW (Bitfield-Mask: 0x01) */
+#define CRG_TOP_ANA_STATUS_REG_COMP_VDD_OK_Pos (10UL) /*!< COMP_VDD_OK (Bit 10) */
+#define CRG_TOP_ANA_STATUS_REG_COMP_VDD_OK_Msk (0x400UL) /*!< COMP_VDD_OK (Bitfield-Mask: 0x01) */
+#define CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Pos (9UL) /*!< VBUS_AVAILABLE (Bit 9) */
+#define CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk (0x200UL) /*!< VBUS_AVAILABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Pos (8UL) /*!< BANDGAP_OK (Bit 8) */
+#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Msk (0x100UL) /*!< BANDGAP_OK (Bitfield-Mask: 0x01) */
+#define CRG_TOP_ANA_STATUS_REG_LDO_3V0_VBAT_OK_Pos (7UL) /*!< LDO_3V0_VBAT_OK (Bit 7) */
+#define CRG_TOP_ANA_STATUS_REG_LDO_3V0_VBAT_OK_Msk (0x80UL) /*!< LDO_3V0_VBAT_OK (Bitfield-Mask: 0x01) */
+#define CRG_TOP_ANA_STATUS_REG_LDO_3V0_VBUS_OK_Pos (6UL) /*!< LDO_3V0_VBUS_OK (Bit 6) */
+#define CRG_TOP_ANA_STATUS_REG_LDO_3V0_VBUS_OK_Msk (0x40UL) /*!< LDO_3V0_VBUS_OK (Bitfield-Mask: 0x01) */
+#define CRG_TOP_ANA_STATUS_REG_LDO_1V8P_OK_Pos (5UL) /*!< LDO_1V8P_OK (Bit 5) */
+#define CRG_TOP_ANA_STATUS_REG_LDO_1V8P_OK_Msk (0x20UL) /*!< LDO_1V8P_OK (Bitfield-Mask: 0x01) */
+#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_OK_Pos (4UL) /*!< LDO_1V8_OK (Bit 4) */
+#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_OK_Msk (0x10UL) /*!< LDO_1V8_OK (Bitfield-Mask: 0x01) */
+#define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Pos (3UL) /*!< LDO_RADIO_OK (Bit 3) */
+#define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Msk (0x8UL) /*!< LDO_RADIO_OK (Bitfield-Mask: 0x01) */
+#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Pos (2UL) /*!< LDO_CORE_OK (Bit 2) */
+#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Msk (0x4UL) /*!< LDO_CORE_OK (Bitfield-Mask: 0x01) */
+#define CRG_TOP_ANA_STATUS_REG_LDO_VDD_HIGH_OK_Pos (1UL) /*!< LDO_VDD_HIGH_OK (Bit 1) */
+#define CRG_TOP_ANA_STATUS_REG_LDO_VDD_HIGH_OK_Msk (0x2UL) /*!< LDO_VDD_HIGH_OK (Bitfield-Mask: 0x01) */
+#define CRG_TOP_ANA_STATUS_REG_BOD_VIN_NOK_Pos (0UL) /*!< BOD_VIN_NOK (Bit 0) */
+#define CRG_TOP_ANA_STATUS_REG_BOD_VIN_NOK_Msk (0x1UL) /*!< BOD_VIN_NOK (Bitfield-Mask: 0x01) */
+/* ====================================================== BANDGAP_REG ====================================================== */
+#define CRG_TOP_BANDGAP_REG_BANDGAP_ENABLE_CLAMP_Pos (12UL) /*!< BANDGAP_ENABLE_CLAMP (Bit 12) */
+#define CRG_TOP_BANDGAP_REG_BANDGAP_ENABLE_CLAMP_Msk (0x1000UL) /*!< BANDGAP_ENABLE_CLAMP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Pos (6UL) /*!< BGR_ITRIM (Bit 6) */
+#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Msk (0xfc0UL) /*!< BGR_ITRIM (Bitfield-Mask: 0x3f) */
+#define CRG_TOP_BANDGAP_REG_SYSRAM_LPMX_Pos (5UL) /*!< SYSRAM_LPMX (Bit 5) */
+#define CRG_TOP_BANDGAP_REG_SYSRAM_LPMX_Msk (0x20UL) /*!< SYSRAM_LPMX (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Pos (0UL) /*!< BGR_TRIM (Bit 0) */
+#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Msk (0x1fUL) /*!< BGR_TRIM (Bitfield-Mask: 0x1f) */
+/* =================================================== BIAS_VREF_SEL_REG =================================================== */
+#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF2_SEL_Pos (4UL) /*!< BIAS_VREF_RF2_SEL (Bit 4) */
+#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF2_SEL_Msk (0xf0UL) /*!< BIAS_VREF_RF2_SEL (Bitfield-Mask: 0x0f) */
+#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF1_SEL_Pos (0UL) /*!< BIAS_VREF_RF1_SEL (Bit 0) */
+#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF1_SEL_Msk (0xfUL) /*!< BIAS_VREF_RF1_SEL (Bitfield-Mask: 0x0f) */
+/* ===================================================== BOD_CTRL_REG ====================================================== */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V14_RST_EN_Pos (16UL) /*!< BOD_V14_RST_EN (Bit 16) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V14_RST_EN_Msk (0x10000UL) /*!< BOD_V14_RST_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V18F_RST_EN_Pos (15UL) /*!< BOD_V18F_RST_EN (Bit 15) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V18F_RST_EN_Msk (0x8000UL) /*!< BOD_V18F_RST_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_RST_EN_Pos (14UL) /*!< BOD_VDD_RST_EN (Bit 14) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_RST_EN_Msk (0x4000UL) /*!< BOD_VDD_RST_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V18P_RST_EN_Pos (13UL) /*!< BOD_V18P_RST_EN (Bit 13) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V18P_RST_EN_Msk (0x2000UL) /*!< BOD_V18P_RST_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V18_RST_EN_Pos (12UL) /*!< BOD_V18_RST_EN (Bit 12) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V18_RST_EN_Msk (0x1000UL) /*!< BOD_V18_RST_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V30_RST_EN_Pos (11UL) /*!< BOD_V30_RST_EN (Bit 11) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V30_RST_EN_Msk (0x800UL) /*!< BOD_V30_RST_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_VBAT_RST_EN_Pos (10UL) /*!< BOD_VBAT_RST_EN (Bit 10) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_VBAT_RST_EN_Msk (0x400UL) /*!< BOD_VBAT_RST_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V14_EN_Pos (9UL) /*!< BOD_V14_EN (Bit 9) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V14_EN_Msk (0x200UL) /*!< BOD_V14_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V18F_EN_Pos (8UL) /*!< BOD_V18F_EN (Bit 8) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V18F_EN_Msk (0x100UL) /*!< BOD_V18F_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_EN_Pos (7UL) /*!< BOD_VDD_EN (Bit 7) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_EN_Msk (0x80UL) /*!< BOD_VDD_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V18P_EN_Pos (6UL) /*!< BOD_V18P_EN (Bit 6) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V18P_EN_Msk (0x40UL) /*!< BOD_V18P_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V18_EN_Pos (5UL) /*!< BOD_V18_EN (Bit 5) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V18_EN_Msk (0x20UL) /*!< BOD_V18_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V30_EN_Pos (4UL) /*!< BOD_V30_EN (Bit 4) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_V30_EN_Msk (0x10UL) /*!< BOD_V30_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_VBAT_EN_Pos (3UL) /*!< BOD_VBAT_EN (Bit 3) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_VBAT_EN_Msk (0x8UL) /*!< BOD_VBAT_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_STATUS_CLEAR_Pos (2UL) /*!< BOD_STATUS_CLEAR (Bit 2) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_STATUS_CLEAR_Msk (0x4UL) /*!< BOD_STATUS_CLEAR (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_CLK_DIV_Pos (0UL) /*!< BOD_CLK_DIV (Bit 0) */
+#define CRG_TOP_BOD_CTRL_REG_BOD_CLK_DIV_Msk (0x3UL) /*!< BOD_CLK_DIV (Bitfield-Mask: 0x03) */
+/* =================================================== BOD_LVL_CTRL0_REG =================================================== */
+#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_V18_Pos (18UL) /*!< BOD_LVL_V18 (Bit 18) */
+#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_V18_Msk (0x7fc0000UL) /*!< BOD_LVL_V18 (Bitfield-Mask: 0x1ff) */
+#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_V30_Pos (9UL) /*!< BOD_LVL_V30 (Bit 9) */
+#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_V30_Msk (0x3fe00UL) /*!< BOD_LVL_V30 (Bitfield-Mask: 0x1ff) */
+#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_VBAT_Pos (0UL) /*!< BOD_LVL_VBAT (Bit 0) */
+#define CRG_TOP_BOD_LVL_CTRL0_REG_BOD_LVL_VBAT_Msk (0x1ffUL) /*!< BOD_LVL_VBAT (Bitfield-Mask: 0x1ff) */
+/* =================================================== BOD_LVL_CTRL1_REG =================================================== */
+#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_VDD_RET_Pos (17UL) /*!< BOD_LVL_VDD_RET (Bit 17) */
+#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_VDD_RET_Msk (0x1fe0000UL) /*!< BOD_LVL_VDD_RET (Bitfield-Mask: 0xff) */
+#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_VDD_ON_Pos (9UL) /*!< BOD_LVL_VDD_ON (Bit 9) */
+#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_VDD_ON_Msk (0x1fe00UL) /*!< BOD_LVL_VDD_ON (Bitfield-Mask: 0xff) */
+#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_V18P_Pos (0UL) /*!< BOD_LVL_V18P (Bit 0) */
+#define CRG_TOP_BOD_LVL_CTRL1_REG_BOD_LVL_V18P_Msk (0x1ffUL) /*!< BOD_LVL_V18P (Bitfield-Mask: 0x1ff) */
+/* =================================================== BOD_LVL_CTRL2_REG =================================================== */
+#define CRG_TOP_BOD_LVL_CTRL2_REG_BOD_LVL_V14_Pos (9UL) /*!< BOD_LVL_V14 (Bit 9) */
+#define CRG_TOP_BOD_LVL_CTRL2_REG_BOD_LVL_V14_Msk (0x3fe00UL) /*!< BOD_LVL_V14 (Bitfield-Mask: 0x1ff) */
+#define CRG_TOP_BOD_LVL_CTRL2_REG_BOD_LVL_V18F_Pos (0UL) /*!< BOD_LVL_V18F (Bit 0) */
+#define CRG_TOP_BOD_LVL_CTRL2_REG_BOD_LVL_V18F_Msk (0x1ffUL) /*!< BOD_LVL_V18F (Bitfield-Mask: 0x1ff) */
+/* ==================================================== BOD_STATUS_REG ===================================================== */
+#define CRG_TOP_BOD_STATUS_REG_BOD_V14_Pos (6UL) /*!< BOD_V14 (Bit 6) */
+#define CRG_TOP_BOD_STATUS_REG_BOD_V14_Msk (0x40UL) /*!< BOD_V14 (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_STATUS_REG_BOD_V18F_Pos (5UL) /*!< BOD_V18F (Bit 5) */
+#define CRG_TOP_BOD_STATUS_REG_BOD_V18F_Msk (0x20UL) /*!< BOD_V18F (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_STATUS_REG_BOD_VDD_Pos (4UL) /*!< BOD_VDD (Bit 4) */
+#define CRG_TOP_BOD_STATUS_REG_BOD_VDD_Msk (0x10UL) /*!< BOD_VDD (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_STATUS_REG_BOD_V18P_Pos (3UL) /*!< BOD_V18P (Bit 3) */
+#define CRG_TOP_BOD_STATUS_REG_BOD_V18P_Msk (0x8UL) /*!< BOD_V18P (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_STATUS_REG_BOD_V18_Pos (2UL) /*!< BOD_V18 (Bit 2) */
+#define CRG_TOP_BOD_STATUS_REG_BOD_V18_Msk (0x4UL) /*!< BOD_V18 (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_STATUS_REG_BOD_V30_Pos (1UL) /*!< BOD_V30 (Bit 1) */
+#define CRG_TOP_BOD_STATUS_REG_BOD_V30_Msk (0x2UL) /*!< BOD_V30 (Bitfield-Mask: 0x01) */
+#define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_Pos (0UL) /*!< BOD_VBAT (Bit 0) */
+#define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_Msk (0x1UL) /*!< BOD_VBAT (Bitfield-Mask: 0x01) */
+/* ===================================================== CLK_AMBA_REG ====================================================== */
+#define CRG_TOP_CLK_AMBA_REG_QSPI2_ENABLE_Pos (15UL) /*!< QSPI2_ENABLE (Bit 15) */
+#define CRG_TOP_CLK_AMBA_REG_QSPI2_ENABLE_Msk (0x8000UL) /*!< QSPI2_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_AMBA_REG_QSPI2_DIV_Pos (13UL) /*!< QSPI2_DIV (Bit 13) */
+#define CRG_TOP_CLK_AMBA_REG_QSPI2_DIV_Msk (0x6000UL) /*!< QSPI2_DIV (Bitfield-Mask: 0x03) */
+#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Pos (12UL) /*!< QSPI_ENABLE (Bit 12) */
+#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Msk (0x1000UL) /*!< QSPI_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Pos (10UL) /*!< QSPI_DIV (Bit 10) */
+#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Msk (0xc00UL) /*!< QSPI_DIV (Bitfield-Mask: 0x03) */
+#define CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Pos (9UL) /*!< OTP_ENABLE (Bit 9) */
+#define CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk (0x200UL) /*!< OTP_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Pos (8UL) /*!< TRNG_CLK_ENABLE (Bit 8) */
+#define CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Msk (0x100UL) /*!< TRNG_CLK_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Pos (6UL) /*!< AES_CLK_ENABLE (Bit 6) */
+#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Msk (0x40UL) /*!< AES_CLK_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Pos (4UL) /*!< PCLK_DIV (Bit 4) */
+#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk (0x30UL) /*!< PCLK_DIV (Bitfield-Mask: 0x03) */
+#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Pos (0UL) /*!< HCLK_DIV (Bit 0) */
+#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk (0x7UL) /*!< HCLK_DIV (Bitfield-Mask: 0x07) */
+/* ===================================================== CLK_CTRL_REG ====================================================== */
+#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Pos (15UL) /*!< RUNNING_AT_PLL96M (Bit 15) */
+#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk (0x8000UL) /*!< RUNNING_AT_PLL96M (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Pos (14UL) /*!< RUNNING_AT_XTAL32M (Bit 14) */
+#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk (0x4000UL) /*!< RUNNING_AT_XTAL32M (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Pos (13UL) /*!< RUNNING_AT_RC32M (Bit 13) */
+#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk (0x2000UL) /*!< RUNNING_AT_RC32M (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Pos (12UL) /*!< RUNNING_AT_LP_CLK (Bit 12) */
+#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Msk (0x1000UL) /*!< RUNNING_AT_LP_CLK (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Pos (4UL) /*!< USB_CLK_SRC (Bit 4) */
+#define CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk (0x10UL) /*!< USB_CLK_SRC (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos (2UL) /*!< LP_CLK_SEL (Bit 2) */
+#define CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk (0xcUL) /*!< LP_CLK_SEL (Bitfield-Mask: 0x03) */
+#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos (0UL) /*!< SYS_CLK_SEL (Bit 0) */
+#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk (0x3UL) /*!< SYS_CLK_SEL (Bitfield-Mask: 0x03) */
+/* ===================================================== CLK_RADIO_REG ===================================================== */
+#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Pos (5UL) /*!< RFCU_ENABLE (Bit 5) */
+#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Msk (0x20UL) /*!< RFCU_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Pos (4UL) /*!< CMAC_SYNCH_RESET (Bit 4) */
+#define CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Msk (0x10UL) /*!< CMAC_SYNCH_RESET (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Pos (3UL) /*!< CMAC_CLK_SEL (Bit 3) */
+#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Msk (0x8UL) /*!< CMAC_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Pos (2UL) /*!< CMAC_CLK_ENABLE (Bit 2) */
+#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Msk (0x4UL) /*!< CMAC_CLK_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_RADIO_REG_CMAC_DIV_Pos (0UL) /*!< CMAC_DIV (Bit 0) */
+#define CRG_TOP_CLK_RADIO_REG_CMAC_DIV_Msk (0x3UL) /*!< CMAC_DIV (Bitfield-Mask: 0x03) */
+/* ===================================================== CLK_RC32K_REG ===================================================== */
+#define CRG_TOP_CLK_RC32K_REG_RC32K_TRIM_Pos (1UL) /*!< RC32K_TRIM (Bit 1) */
+#define CRG_TOP_CLK_RC32K_REG_RC32K_TRIM_Msk (0x1eUL) /*!< RC32K_TRIM (Bitfield-Mask: 0x0f) */
+#define CRG_TOP_CLK_RC32K_REG_RC32K_ENABLE_Pos (0UL) /*!< RC32K_ENABLE (Bit 0) */
+#define CRG_TOP_CLK_RC32K_REG_RC32K_ENABLE_Msk (0x1UL) /*!< RC32K_ENABLE (Bitfield-Mask: 0x01) */
+/* ===================================================== CLK_RC32M_REG ===================================================== */
+#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_RANGE_Pos (20UL) /*!< RC32M_INIT_RANGE (Bit 20) */
+#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_RANGE_Msk (0x300000UL) /*!< RC32M_INIT_RANGE (Bitfield-Mask: 0x03) */
+#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DEL_Pos (12UL) /*!< RC32M_INIT_DEL (Bit 12) */
+#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DEL_Msk (0xff000UL) /*!< RC32M_INIT_DEL (Bitfield-Mask: 0xff) */
+#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DTCF_Pos (9UL) /*!< RC32M_INIT_DTCF (Bit 9) */
+#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DTCF_Msk (0xe00UL) /*!< RC32M_INIT_DTCF (Bitfield-Mask: 0x07) */
+#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DTC_Pos (5UL) /*!< RC32M_INIT_DTC (Bit 5) */
+#define CRG_TOP_CLK_RC32M_REG_RC32M_INIT_DTC_Msk (0x1e0UL) /*!< RC32M_INIT_DTC (Bitfield-Mask: 0x0f) */
+#define CRG_TOP_CLK_RC32M_REG_RC32M_BIAS_Pos (1UL) /*!< RC32M_BIAS (Bit 1) */
+#define CRG_TOP_CLK_RC32M_REG_RC32M_BIAS_Msk (0x1eUL) /*!< RC32M_BIAS (Bitfield-Mask: 0x0f) */
+#define CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Pos (0UL) /*!< RC32M_ENABLE (Bit 0) */
+#define CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk (0x1UL) /*!< RC32M_ENABLE (Bitfield-Mask: 0x01) */
+/* ====================================================== CLK_RCX_REG ====================================================== */
+#define CRG_TOP_CLK_RCX_REG_RCX_BIAS_Pos (8UL) /*!< RCX_BIAS (Bit 8) */
+#define CRG_TOP_CLK_RCX_REG_RCX_BIAS_Msk (0xf00UL) /*!< RCX_BIAS (Bitfield-Mask: 0x0f) */
+#define CRG_TOP_CLK_RCX_REG_RCX_C0_Pos (7UL) /*!< RCX_C0 (Bit 7) */
+#define CRG_TOP_CLK_RCX_REG_RCX_C0_Msk (0x80UL) /*!< RCX_C0 (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_RCX_REG_RCX_CADJUST_Pos (2UL) /*!< RCX_CADJUST (Bit 2) */
+#define CRG_TOP_CLK_RCX_REG_RCX_CADJUST_Msk (0x7cUL) /*!< RCX_CADJUST (Bitfield-Mask: 0x1f) */
+#define CRG_TOP_CLK_RCX_REG_RCX_RADJUST_Pos (1UL) /*!< RCX_RADJUST (Bit 1) */
+#define CRG_TOP_CLK_RCX_REG_RCX_RADJUST_Msk (0x2UL) /*!< RCX_RADJUST (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Pos (0UL) /*!< RCX_ENABLE (Bit 0) */
+#define CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk (0x1UL) /*!< RCX_ENABLE (Bitfield-Mask: 0x01) */
+/* ==================================================== CLK_RTCDIV_REG ===================================================== */
+#define CRG_TOP_CLK_RTCDIV_REG_RTC_RESET_REQ_Pos (21UL) /*!< RTC_RESET_REQ (Bit 21) */
+#define CRG_TOP_CLK_RTCDIV_REG_RTC_RESET_REQ_Msk (0x200000UL) /*!< RTC_RESET_REQ (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Pos (20UL) /*!< RTC_DIV_ENABLE (Bit 20) */
+#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Msk (0x100000UL) /*!< RTC_DIV_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_DENOM_Pos (19UL) /*!< RTC_DIV_DENOM (Bit 19) */
+#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_DENOM_Msk (0x80000UL) /*!< RTC_DIV_DENOM (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_INT_Pos (10UL) /*!< RTC_DIV_INT (Bit 10) */
+#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_INT_Msk (0x7fc00UL) /*!< RTC_DIV_INT (Bitfield-Mask: 0x1ff) */
+#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_FRAC_Pos (0UL) /*!< RTC_DIV_FRAC (Bit 0) */
+#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_FRAC_Msk (0x3ffUL) /*!< RTC_DIV_FRAC (Bitfield-Mask: 0x3ff) */
+/* ================================================== CLK_SWITCH2XTAL_REG ================================================== */
+#define CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Pos (0UL) /*!< SWITCH2XTAL (Bit 0) */
+#define CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk (0x1UL) /*!< SWITCH2XTAL (Bitfield-Mask: 0x01) */
+/* ====================================================== CLK_TMR_REG ====================================================== */
+#define CRG_TOP_CLK_TMR_REG_TMR2_PWM_AON_MODE_Pos (2UL) /*!< TMR2_PWM_AON_MODE (Bit 2) */
+#define CRG_TOP_CLK_TMR_REG_TMR2_PWM_AON_MODE_Msk (0x4UL) /*!< TMR2_PWM_AON_MODE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_TMR_REG_TMR_PWM_AON_MODE_Pos (1UL) /*!< TMR_PWM_AON_MODE (Bit 1) */
+#define CRG_TOP_CLK_TMR_REG_TMR_PWM_AON_MODE_Msk (0x2UL) /*!< TMR_PWM_AON_MODE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Pos (0UL) /*!< WAKEUPCT_ENABLE (Bit 0) */
+#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk (0x1UL) /*!< WAKEUPCT_ENABLE (Bitfield-Mask: 0x01) */
+/* ==================================================== CLK_XTAL32K_REG ==================================================== */
+#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_OUTPUT_Pos (9UL) /*!< XTAL32K_DISABLE_OUTPUT (Bit 9) */
+#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_OUTPUT_Msk (0x200UL) /*!< XTAL32K_DISABLE_OUTPUT (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_AMPREG_Pos (7UL) /*!< XTAL32K_DISABLE_AMPREG (Bit 7) */
+#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_AMPREG_Msk (0x80UL) /*!< XTAL32K_DISABLE_AMPREG (Bitfield-Mask: 0x01) */
+#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_CUR_Pos (3UL) /*!< XTAL32K_CUR (Bit 3) */
+#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_CUR_Msk (0x78UL) /*!< XTAL32K_CUR (Bitfield-Mask: 0x0f) */
+#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_RBIAS_Pos (1UL) /*!< XTAL32K_RBIAS (Bit 1) */
+#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_RBIAS_Msk (0x6UL) /*!< XTAL32K_RBIAS (Bitfield-Mask: 0x03) */
+#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Pos (0UL) /*!< XTAL32K_ENABLE (Bit 0) */
+#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Msk (0x1UL) /*!< XTAL32K_ENABLE (Bitfield-Mask: 0x01) */
+/* ================================================== DISCHARGE_RAIL_REG =================================================== */
+#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Pos (2UL) /*!< RESET_V18P (Bit 2) */
+#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Msk (0x4UL) /*!< RESET_V18P (Bitfield-Mask: 0x01) */
+#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Pos (1UL) /*!< RESET_V18 (Bit 1) */
+#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Msk (0x2UL) /*!< RESET_V18 (Bitfield-Mask: 0x01) */
+#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Pos (0UL) /*!< RESET_V14 (Bit 0) */
+#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Msk (0x1UL) /*!< RESET_V14 (Bitfield-Mask: 0x01) */
+/* ================================================ LDO_VDDD_HIGH_CTRL_REG ================================================= */
+#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_LOW_ZOUT_DISABLE_Pos (3UL) /*!< LDO_VDDD_HIGH_LOW_ZOUT_DISABLE (Bit 3) */
+#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_LOW_ZOUT_DISABLE_Msk (0x8UL) /*!< LDO_VDDD_HIGH_LOW_ZOUT_DISABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_STATIC_LOAD_ENABLE_Pos (2UL) /*!< LDO_VDDD_HIGH_STATIC_LOAD_ENABLE (Bit 2) */
+#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_STATIC_LOAD_ENABLE_Msk (0x4UL) /*!< LDO_VDDD_HIGH_STATIC_LOAD_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_ENABLE_Pos (1UL) /*!< LDO_VDDD_HIGH_ENABLE (Bit 1) */
+#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_ENABLE_Msk (0x2UL) /*!< LDO_VDDD_HIGH_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_VREF_HOLD_Pos (0UL) /*!< LDO_VDDD_HIGH_VREF_HOLD (Bit 0) */
+#define CRG_TOP_LDO_VDDD_HIGH_CTRL_REG_LDO_VDDD_HIGH_VREF_HOLD_Msk (0x1UL) /*!< LDO_VDDD_HIGH_VREF_HOLD (Bitfield-Mask: 0x01) */
+/* =================================================== P0_PAD_LATCH_REG ==================================================== */
+#define CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Pos (0UL) /*!< P0_LATCH_EN (Bit 0) */
+#define CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk (0xffffffffUL) /*!< P0_LATCH_EN (Bitfield-Mask: 0xffffffff) */
+/* ================================================ P0_RESET_PAD_LATCH_REG ================================================= */
+#define CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_EN_Pos (0UL) /*!< P0_RESET_LATCH_EN (Bit 0) */
+#define CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_EN_Msk (0xffffffffUL) /*!< P0_RESET_LATCH_EN (Bitfield-Mask: 0xffffffff) */
+/* ================================================= P0_SET_PAD_LATCH_REG ================================================== */
+#define CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_EN_Pos (0UL) /*!< P0_SET_LATCH_EN (Bit 0) */
+#define CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_EN_Msk (0xffffffffUL) /*!< P0_SET_LATCH_EN (Bitfield-Mask: 0xffffffff) */
+/* =================================================== P1_PAD_LATCH_REG ==================================================== */
+#define CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Pos (0UL) /*!< P1_LATCH_EN (Bit 0) */
+#define CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk (0x7fffffUL) /*!< P1_LATCH_EN (Bitfield-Mask: 0x7fffff) */
+/* ================================================ P1_RESET_PAD_LATCH_REG ================================================= */
+#define CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_EN_Pos (0UL) /*!< P1_RESET_LATCH_EN (Bit 0) */
+#define CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_EN_Msk (0x7fffffUL) /*!< P1_RESET_LATCH_EN (Bitfield-Mask: 0x7fffff) */
+/* ================================================= P1_SET_PAD_LATCH_REG ================================================== */
+#define CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_EN_Pos (0UL) /*!< P1_SET_LATCH_EN (Bit 0) */
+#define CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_EN_Msk (0x7fffffUL) /*!< P1_SET_LATCH_EN (Bitfield-Mask: 0x7fffff) */
+/* ===================================================== PMU_CTRL_REG ====================================================== */
+#define CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Pos (8UL) /*!< ENABLE_CLKLESS (Bit 8) */
+#define CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Msk (0x100UL) /*!< ENABLE_CLKLESS (Bitfield-Mask: 0x01) */
+#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Pos (7UL) /*!< RETAIN_CACHE (Bit 7) */
+#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Msk (0x80UL) /*!< RETAIN_CACHE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Pos (6UL) /*!< SYS_SLEEP (Bit 6) */
+#define CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Msk (0x40UL) /*!< SYS_SLEEP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Pos (5UL) /*!< RESET_ON_WAKEUP (Bit 5) */
+#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Msk (0x20UL) /*!< RESET_ON_WAKEUP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Pos (4UL) /*!< MAP_BANDGAP_EN (Bit 4) */
+#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Msk (0x10UL) /*!< MAP_BANDGAP_EN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Pos (3UL) /*!< COM_SLEEP (Bit 3) */
+#define CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Msk (0x8UL) /*!< COM_SLEEP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Pos (2UL) /*!< TIM_SLEEP (Bit 2) */
+#define CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Msk (0x4UL) /*!< TIM_SLEEP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos (1UL) /*!< RADIO_SLEEP (Bit 1) */
+#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk (0x2UL) /*!< RADIO_SLEEP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos (0UL) /*!< PERIPH_SLEEP (Bit 0) */
+#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk (0x1UL) /*!< PERIPH_SLEEP (Bitfield-Mask: 0x01) */
+/* ===================================================== PMU_SLEEP_REG ===================================================== */
+#define CRG_TOP_PMU_SLEEP_REG_CLAMP_VDD_WKUP_MAX_Pos (18UL) /*!< CLAMP_VDD_WKUP_MAX (Bit 18) */
+#define CRG_TOP_PMU_SLEEP_REG_CLAMP_VDD_WKUP_MAX_Msk (0x40000UL) /*!< CLAMP_VDD_WKUP_MAX (Bitfield-Mask: 0x01) */
+#define CRG_TOP_PMU_SLEEP_REG_ULTRA_FAST_WAKEUP_Pos (17UL) /*!< ULTRA_FAST_WAKEUP (Bit 17) */
+#define CRG_TOP_PMU_SLEEP_REG_ULTRA_FAST_WAKEUP_Msk (0x20000UL) /*!< ULTRA_FAST_WAKEUP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_Pos (16UL) /*!< FAST_WAKEUP (Bit 16) */
+#define CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_Msk (0x10000UL) /*!< FAST_WAKEUP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_PMU_SLEEP_REG_BOD_SLEEP_INTERVAL_Pos (12UL) /*!< BOD_SLEEP_INTERVAL (Bit 12) */
+#define CRG_TOP_PMU_SLEEP_REG_BOD_SLEEP_INTERVAL_Msk (0xf000UL) /*!< BOD_SLEEP_INTERVAL (Bitfield-Mask: 0x0f) */
+#define CRG_TOP_PMU_SLEEP_REG_BG_REFRESH_INTERVAL_Pos (0UL) /*!< BG_REFRESH_INTERVAL (Bit 0) */
+#define CRG_TOP_PMU_SLEEP_REG_BG_REFRESH_INTERVAL_Msk (0xfffUL) /*!< BG_REFRESH_INTERVAL (Bitfield-Mask: 0xfff) */
+/* ===================================================== PMU_TRIM_REG ====================================================== */
+#define CRG_TOP_PMU_TRIM_REG_LDO_1V8_TRIM_Pos (12UL) /*!< LDO_1V8_TRIM (Bit 12) */
+#define CRG_TOP_PMU_TRIM_REG_LDO_1V8_TRIM_Msk (0xf000UL) /*!< LDO_1V8_TRIM (Bitfield-Mask: 0x0f) */
+#define CRG_TOP_PMU_TRIM_REG_LDO_1V8P_TRIM_Pos (8UL) /*!< LDO_1V8P_TRIM (Bit 8) */
+#define CRG_TOP_PMU_TRIM_REG_LDO_1V8P_TRIM_Msk (0xf00UL) /*!< LDO_1V8P_TRIM (Bitfield-Mask: 0x0f) */
+#define CRG_TOP_PMU_TRIM_REG_LDO_SUPPLY_VBAT_TRIM_Pos (4UL) /*!< LDO_SUPPLY_VBAT_TRIM (Bit 4) */
+#define CRG_TOP_PMU_TRIM_REG_LDO_SUPPLY_VBAT_TRIM_Msk (0xf0UL) /*!< LDO_SUPPLY_VBAT_TRIM (Bitfield-Mask: 0x0f) */
+#define CRG_TOP_PMU_TRIM_REG_LDO_SUPPLY_VBUS_TRIM_Pos (0UL) /*!< LDO_SUPPLY_VBUS_TRIM (Bit 0) */
+#define CRG_TOP_PMU_TRIM_REG_LDO_SUPPLY_VBUS_TRIM_Msk (0xfUL) /*!< LDO_SUPPLY_VBUS_TRIM (Bitfield-Mask: 0x0f) */
+/* ====================================================== POR_PIN_REG ====================================================== */
+#define CRG_TOP_POR_PIN_REG_POR_PIN_POLARITY_Pos (7UL) /*!< POR_PIN_POLARITY (Bit 7) */
+#define CRG_TOP_POR_PIN_REG_POR_PIN_POLARITY_Msk (0x80UL) /*!< POR_PIN_POLARITY (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POR_PIN_REG_POR_PIN_SELECT_Pos (0UL) /*!< POR_PIN_SELECT (Bit 0) */
+#define CRG_TOP_POR_PIN_REG_POR_PIN_SELECT_Msk (0x3fUL) /*!< POR_PIN_SELECT (Bitfield-Mask: 0x3f) */
+/* ===================================================== POR_TIMER_REG ===================================================== */
+#define CRG_TOP_POR_TIMER_REG_POR_TIME_Pos (0UL) /*!< POR_TIME (Bit 0) */
+#define CRG_TOP_POR_TIMER_REG_POR_TIME_Msk (0x7fUL) /*!< POR_TIME (Bitfield-Mask: 0x7f) */
+/* =================================================== POR_VBAT_CTRL_REG =================================================== */
+#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Pos (13UL) /*!< POR_VBAT_MASK_N (Bit 13) */
+#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Msk (0x2000UL) /*!< POR_VBAT_MASK_N (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Pos (12UL) /*!< POR_VBAT_ENABLE (Bit 12) */
+#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Msk (0x1000UL) /*!< POR_VBAT_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Pos (8UL) /*!< POR_VBAT_HYST_LOW (Bit 8) */
+#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Msk (0xf00UL) /*!< POR_VBAT_HYST_LOW (Bitfield-Mask: 0x0f) */
+#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Pos (4UL) /*!< POR_VBAT_THRES_HIGH (Bit 4) */
+#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Msk (0xf0UL) /*!< POR_VBAT_THRES_HIGH (Bitfield-Mask: 0x0f) */
+#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Pos (0UL) /*!< POR_VBAT_THRES_LOW (Bit 0) */
+#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Msk (0xfUL) /*!< POR_VBAT_THRES_LOW (Bitfield-Mask: 0x0f) */
+/* ==================================================== POWER_CTRL_REG ===================================================== */
+#define CRG_TOP_POWER_CTRL_REG_VDD_SLEEP_LEVEL_Pos (29UL) /*!< VDD_SLEEP_LEVEL (Bit 29) */
+#define CRG_TOP_POWER_CTRL_REG_VDD_SLEEP_LEVEL_Msk (0xe0000000UL) /*!< VDD_SLEEP_LEVEL (Bitfield-Mask: 0x07) */
+#define CRG_TOP_POWER_CTRL_REG_VDD_CLAMP_LEVEL_Pos (25UL) /*!< VDD_CLAMP_LEVEL (Bit 25) */
+#define CRG_TOP_POWER_CTRL_REG_VDD_CLAMP_LEVEL_Msk (0x1e000000UL) /*!< VDD_CLAMP_LEVEL (Bitfield-Mask: 0x0f) */
+#define CRG_TOP_POWER_CTRL_REG_CLAMP_3V0_VBAT_ENABLE_Pos (24UL) /*!< CLAMP_3V0_VBAT_ENABLE (Bit 24) */
+#define CRG_TOP_POWER_CTRL_REG_CLAMP_3V0_VBAT_ENABLE_Msk (0x1000000UL) /*!< CLAMP_3V0_VBAT_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_V18_LEVEL_Pos (23UL) /*!< V18_LEVEL (Bit 23) */
+#define CRG_TOP_POWER_CTRL_REG_V18_LEVEL_Msk (0x800000UL) /*!< V18_LEVEL (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_V14_LEVEL_Pos (20UL) /*!< V14_LEVEL (Bit 20) */
+#define CRG_TOP_POWER_CTRL_REG_V14_LEVEL_Msk (0x700000UL) /*!< V14_LEVEL (Bitfield-Mask: 0x07) */
+#define CRG_TOP_POWER_CTRL_REG_V30_LEVEL_Pos (18UL) /*!< V30_LEVEL (Bit 18) */
+#define CRG_TOP_POWER_CTRL_REG_V30_LEVEL_Msk (0xc0000UL) /*!< V30_LEVEL (Bitfield-Mask: 0x03) */
+#define CRG_TOP_POWER_CTRL_REG_VDD_LEVEL_Pos (16UL) /*!< VDD_LEVEL (Bit 16) */
+#define CRG_TOP_POWER_CTRL_REG_VDD_LEVEL_Msk (0x30000UL) /*!< VDD_LEVEL (Bitfield-Mask: 0x03) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_REF_Pos (15UL) /*!< LDO_3V0_REF (Bit 15) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_REF_Msk (0x8000UL) /*!< LDO_3V0_REF (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Pos (14UL) /*!< LDO_CORE_RET_ENABLE_SLEEP (Bit 14) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Msk (0x4000UL) /*!< LDO_CORE_RET_ENABLE_SLEEP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_ACTIVE_Pos (13UL) /*!< LDO_CORE_RET_ENABLE_ACTIVE (Bit 13) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_ACTIVE_Msk (0x2000UL) /*!< LDO_CORE_RET_ENABLE_ACTIVE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Pos (12UL) /*!< LDO_CORE_ENABLE (Bit 12) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Msk (0x1000UL) /*!< LDO_CORE_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_RET_ENABLE_SLEEP_Pos (11UL) /*!< LDO_3V0_RET_ENABLE_SLEEP (Bit 11) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_RET_ENABLE_SLEEP_Msk (0x800UL) /*!< LDO_3V0_RET_ENABLE_SLEEP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_RET_ENABLE_ACTIVE_Pos (10UL) /*!< LDO_3V0_RET_ENABLE_ACTIVE (Bit 10) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_RET_ENABLE_ACTIVE_Msk (0x400UL) /*!< LDO_3V0_RET_ENABLE_ACTIVE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_MODE_Pos (8UL) /*!< LDO_3V0_MODE (Bit 8) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_3V0_MODE_Msk (0x300UL) /*!< LDO_3V0_MODE (Bitfield-Mask: 0x03) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_RADIO_ENABLE_Pos (7UL) /*!< LDO_RADIO_ENABLE (Bit 7) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_RADIO_ENABLE_Msk (0x80UL) /*!< LDO_RADIO_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_RET_ENABLE_SLEEP_Pos (6UL) /*!< LDO_1V8_RET_ENABLE_SLEEP (Bit 6) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_RET_ENABLE_SLEEP_Msk (0x40UL) /*!< LDO_1V8_RET_ENABLE_SLEEP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_RET_ENABLE_ACTIVE_Pos (5UL) /*!< LDO_1V8_RET_ENABLE_ACTIVE (Bit 5) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_RET_ENABLE_ACTIVE_Msk (0x20UL) /*!< LDO_1V8_RET_ENABLE_ACTIVE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_ENABLE_Pos (4UL) /*!< LDO_1V8_ENABLE (Bit 4) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_1V8_ENABLE_Msk (0x10UL) /*!< LDO_1V8_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_SW_1V8F_ENABLE_FORCE_Pos (3UL) /*!< SW_1V8F_ENABLE_FORCE (Bit 3) */
+#define CRG_TOP_POWER_CTRL_REG_SW_1V8F_ENABLE_FORCE_Msk (0x8UL) /*!< SW_1V8F_ENABLE_FORCE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_RET_ENABLE_SLEEP_Pos (2UL) /*!< LDO_1V8P_RET_ENABLE_SLEEP (Bit 2) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_RET_ENABLE_SLEEP_Msk (0x4UL) /*!< LDO_1V8P_RET_ENABLE_SLEEP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_RET_ENABLE_ACTIVE_Pos (1UL) /*!< LDO_1V8P_RET_ENABLE_ACTIVE (Bit 1) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_RET_ENABLE_ACTIVE_Msk (0x2UL) /*!< LDO_1V8P_RET_ENABLE_ACTIVE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_ENABLE_Pos (0UL) /*!< LDO_1V8P_ENABLE (Bit 0) */
+#define CRG_TOP_POWER_CTRL_REG_LDO_1V8P_ENABLE_Msk (0x1UL) /*!< LDO_1V8P_ENABLE (Bitfield-Mask: 0x01) */
+/* =================================================== RAM_PWR_CTRL_REG ==================================================== */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM8_PWR_CTRL_Pos (14UL) /*!< RAM8_PWR_CTRL (Bit 14) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM8_PWR_CTRL_Msk (0xc000UL) /*!< RAM8_PWR_CTRL (Bitfield-Mask: 0x03) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM7_PWR_CTRL_Pos (12UL) /*!< RAM7_PWR_CTRL (Bit 12) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM7_PWR_CTRL_Msk (0x3000UL) /*!< RAM7_PWR_CTRL (Bitfield-Mask: 0x03) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM6_PWR_CTRL_Pos (10UL) /*!< RAM6_PWR_CTRL (Bit 10) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM6_PWR_CTRL_Msk (0xc00UL) /*!< RAM6_PWR_CTRL (Bitfield-Mask: 0x03) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM5_PWR_CTRL_Pos (8UL) /*!< RAM5_PWR_CTRL (Bit 8) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM5_PWR_CTRL_Msk (0x300UL) /*!< RAM5_PWR_CTRL (Bitfield-Mask: 0x03) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM4_PWR_CTRL_Pos (6UL) /*!< RAM4_PWR_CTRL (Bit 6) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM4_PWR_CTRL_Msk (0xc0UL) /*!< RAM4_PWR_CTRL (Bitfield-Mask: 0x03) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM3_PWR_CTRL_Pos (4UL) /*!< RAM3_PWR_CTRL (Bit 4) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM3_PWR_CTRL_Msk (0x30UL) /*!< RAM3_PWR_CTRL (Bitfield-Mask: 0x03) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM2_PWR_CTRL_Pos (2UL) /*!< RAM2_PWR_CTRL (Bit 2) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM2_PWR_CTRL_Msk (0xcUL) /*!< RAM2_PWR_CTRL (Bitfield-Mask: 0x03) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM1_PWR_CTRL_Pos (0UL) /*!< RAM1_PWR_CTRL (Bit 0) */
+#define CRG_TOP_RAM_PWR_CTRL_REG_RAM1_PWR_CTRL_Msk (0x3UL) /*!< RAM1_PWR_CTRL (Bitfield-Mask: 0x03) */
+/* ==================================================== RESET_STAT_REG ===================================================== */
+#define CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Pos (5UL) /*!< CMAC_WDOGRESET_STAT (Bit 5) */
+#define CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Msk (0x20UL) /*!< CMAC_WDOGRESET_STAT (Bitfield-Mask: 0x01) */
+#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Pos (4UL) /*!< SWD_HWRESET_STAT (Bit 4) */
+#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk (0x10UL) /*!< SWD_HWRESET_STAT (Bitfield-Mask: 0x01) */
+#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Pos (3UL) /*!< WDOGRESET_STAT (Bit 3) */
+#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk (0x8UL) /*!< WDOGRESET_STAT (Bitfield-Mask: 0x01) */
+#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Pos (2UL) /*!< SWRESET_STAT (Bit 2) */
+#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk (0x4UL) /*!< SWRESET_STAT (Bitfield-Mask: 0x01) */
+#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Pos (1UL) /*!< HWRESET_STAT (Bit 1) */
+#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk (0x2UL) /*!< HWRESET_STAT (Bitfield-Mask: 0x01) */
+#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Pos (0UL) /*!< PORESET_STAT (Bit 0) */
+#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk (0x1UL) /*!< PORESET_STAT (Bitfield-Mask: 0x01) */
+/* ==================================================== SECURE_BOOT_REG ==================================================== */
+#define CRG_TOP_SECURE_BOOT_REG_PROT_QSPI_KEY_READ_Pos (7UL) /*!< PROT_QSPI_KEY_READ (Bit 7) */
+#define CRG_TOP_SECURE_BOOT_REG_PROT_QSPI_KEY_READ_Msk (0x80UL) /*!< PROT_QSPI_KEY_READ (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SECURE_BOOT_REG_PROT_QSPI_KEY_WRITE_Pos (6UL) /*!< PROT_QSPI_KEY_WRITE (Bit 6) */
+#define CRG_TOP_SECURE_BOOT_REG_PROT_QSPI_KEY_WRITE_Msk (0x40UL) /*!< PROT_QSPI_KEY_WRITE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SECURE_BOOT_REG_PROT_AES_KEY_READ_Pos (5UL) /*!< PROT_AES_KEY_READ (Bit 5) */
+#define CRG_TOP_SECURE_BOOT_REG_PROT_AES_KEY_READ_Msk (0x20UL) /*!< PROT_AES_KEY_READ (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SECURE_BOOT_REG_PROT_AES_KEY_WRITE_Pos (4UL) /*!< PROT_AES_KEY_WRITE (Bit 4) */
+#define CRG_TOP_SECURE_BOOT_REG_PROT_AES_KEY_WRITE_Msk (0x10UL) /*!< PROT_AES_KEY_WRITE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SECURE_BOOT_REG_PROT_SIG_KEY_WRITE_Pos (3UL) /*!< PROT_SIG_KEY_WRITE (Bit 3) */
+#define CRG_TOP_SECURE_BOOT_REG_PROT_SIG_KEY_WRITE_Msk (0x8UL) /*!< PROT_SIG_KEY_WRITE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SECURE_BOOT_REG_FORCE_CMAC_DEBUGGER_OFF_Pos (2UL) /*!< FORCE_CMAC_DEBUGGER_OFF (Bit 2) */
+#define CRG_TOP_SECURE_BOOT_REG_FORCE_CMAC_DEBUGGER_OFF_Msk (0x4UL) /*!< FORCE_CMAC_DEBUGGER_OFF (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Pos (1UL) /*!< FORCE_DEBUGGER_OFF (Bit 1) */
+#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Msk (0x2UL) /*!< FORCE_DEBUGGER_OFF (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Pos (0UL) /*!< SECURE_BOOT (Bit 0) */
+#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Msk (0x1UL) /*!< SECURE_BOOT (Bitfield-Mask: 0x01) */
+/* ===================================================== SYS_CTRL_REG ====================================================== */
+#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Pos (15UL) /*!< SW_RESET (Bit 15) */
+#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Msk (0x8000UL) /*!< SW_RESET (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Pos (10UL) /*!< CACHERAM_MUX (Bit 10) */
+#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk (0x400UL) /*!< CACHERAM_MUX (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Pos (9UL) /*!< TIMEOUT_DISABLE (Bit 9) */
+#define CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Msk (0x200UL) /*!< TIMEOUT_DISABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Pos (7UL) /*!< DEBUGGER_ENABLE (Bit 7) */
+#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk (0x80UL) /*!< DEBUGGER_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Pos (4UL) /*!< QSPI_INIT (Bit 4) */
+#define CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Msk (0x10UL) /*!< QSPI_INIT (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Pos (3UL) /*!< REMAP_INTVECT (Bit 3) */
+#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Msk (0x8UL) /*!< REMAP_INTVECT (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Pos (0UL) /*!< REMAP_ADR0 (Bit 0) */
+#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk (0x7UL) /*!< REMAP_ADR0 (Bitfield-Mask: 0x07) */
+/* ===================================================== SYS_STAT_REG ====================================================== */
+#define CRG_TOP_SYS_STAT_REG_POWER_IS_UP_Pos (13UL) /*!< POWER_IS_UP (Bit 13) */
+#define CRG_TOP_SYS_STAT_REG_POWER_IS_UP_Msk (0x2000UL) /*!< POWER_IS_UP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Pos (12UL) /*!< DBG_IS_ACTIVE (Bit 12) */
+#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk (0x1000UL) /*!< DBG_IS_ACTIVE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_STAT_REG_COM_IS_UP_Pos (11UL) /*!< COM_IS_UP (Bit 11) */
+#define CRG_TOP_SYS_STAT_REG_COM_IS_UP_Msk (0x800UL) /*!< COM_IS_UP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_STAT_REG_COM_IS_DOWN_Pos (10UL) /*!< COM_IS_DOWN (Bit 10) */
+#define CRG_TOP_SYS_STAT_REG_COM_IS_DOWN_Msk (0x400UL) /*!< COM_IS_DOWN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Pos (9UL) /*!< TIM_IS_UP (Bit 9) */
+#define CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Msk (0x200UL) /*!< TIM_IS_UP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_STAT_REG_TIM_IS_DOWN_Pos (8UL) /*!< TIM_IS_DOWN (Bit 8) */
+#define CRG_TOP_SYS_STAT_REG_TIM_IS_DOWN_Msk (0x100UL) /*!< TIM_IS_DOWN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_STAT_REG_MEM_IS_UP_Pos (7UL) /*!< MEM_IS_UP (Bit 7) */
+#define CRG_TOP_SYS_STAT_REG_MEM_IS_UP_Msk (0x80UL) /*!< MEM_IS_UP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_STAT_REG_MEM_IS_DOWN_Pos (6UL) /*!< MEM_IS_DOWN (Bit 6) */
+#define CRG_TOP_SYS_STAT_REG_MEM_IS_DOWN_Msk (0x40UL) /*!< MEM_IS_DOWN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_STAT_REG_SYS_IS_UP_Pos (5UL) /*!< SYS_IS_UP (Bit 5) */
+#define CRG_TOP_SYS_STAT_REG_SYS_IS_UP_Msk (0x20UL) /*!< SYS_IS_UP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_STAT_REG_SYS_IS_DOWN_Pos (4UL) /*!< SYS_IS_DOWN (Bit 4) */
+#define CRG_TOP_SYS_STAT_REG_SYS_IS_DOWN_Msk (0x10UL) /*!< SYS_IS_DOWN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Pos (3UL) /*!< PER_IS_UP (Bit 3) */
+#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Msk (0x8UL) /*!< PER_IS_UP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Pos (2UL) /*!< PER_IS_DOWN (Bit 2) */
+#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Msk (0x4UL) /*!< PER_IS_DOWN (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Pos (1UL) /*!< RAD_IS_UP (Bit 1) */
+#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Msk (0x2UL) /*!< RAD_IS_UP (Bitfield-Mask: 0x01) */
+#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Pos (0UL) /*!< RAD_IS_DOWN (Bit 0) */
+#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Msk (0x1UL) /*!< RAD_IS_DOWN (Bitfield-Mask: 0x01) */
+/* ================================================== VBUS_IRQ_CLEAR_REG =================================================== */
+#define CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Pos (0UL) /*!< VBUS_IRQ_CLEAR (Bit 0) */
+#define CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Msk (0xffffUL) /*!< VBUS_IRQ_CLEAR (Bitfield-Mask: 0xffff) */
+/* =================================================== VBUS_IRQ_MASK_REG =================================================== */
+#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Pos (1UL) /*!< VBUS_IRQ_EN_RISE (Bit 1) */
+#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk (0x2UL) /*!< VBUS_IRQ_EN_RISE (Bitfield-Mask: 0x01) */
+#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Pos (0UL) /*!< VBUS_IRQ_EN_FALL (Bit 0) */
+#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk (0x1UL) /*!< VBUS_IRQ_EN_FALL (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CRG_XTAL ================ */
+/* =========================================================================================================================== */
+
+/* =================================================== CLK_FREQ_TRIM_REG =================================================== */
+#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_START_Pos (20UL) /*!< XTAL32M_START (Bit 20) */
+#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_START_Msk (0x3ff00000UL) /*!< XTAL32M_START (Bitfield-Mask: 0x3ff) */
+#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_RAMP_Pos (10UL) /*!< XTAL32M_RAMP (Bit 10) */
+#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_RAMP_Msk (0xffc00UL) /*!< XTAL32M_RAMP (Bitfield-Mask: 0x3ff) */
+#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_TRIM_Pos (0UL) /*!< XTAL32M_TRIM (Bit 0) */
+#define CRG_XTAL_CLK_FREQ_TRIM_REG_XTAL32M_TRIM_Msk (0x3ffUL) /*!< XTAL32M_TRIM (Bitfield-Mask: 0x3ff) */
+/* =================================================== PLL_SYS_CTRL1_REG =================================================== */
+#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_SEL_MIN_CUR_INT_Pos (14UL) /*!< PLL_SEL_MIN_CUR_INT (Bit 14) */
+#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_SEL_MIN_CUR_INT_Msk (0x4000UL) /*!< PLL_SEL_MIN_CUR_INT (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_PRE_DIV_Pos (11UL) /*!< PLL_PRE_DIV (Bit 11) */
+#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_PRE_DIV_Msk (0x800UL) /*!< PLL_PRE_DIV (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_N_DIV_Pos (4UL) /*!< PLL_N_DIV (Bit 4) */
+#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_N_DIV_Msk (0x7f0UL) /*!< PLL_N_DIV (Bitfield-Mask: 0x7f) */
+#define CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Pos (3UL) /*!< LDO_PLL_VREF_HOLD (Bit 3) */
+#define CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Msk (0x8UL) /*!< LDO_PLL_VREF_HOLD (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Pos (2UL) /*!< LDO_PLL_ENABLE (Bit 2) */
+#define CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Msk (0x4UL) /*!< LDO_PLL_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_EN_Pos (1UL) /*!< PLL_EN (Bit 1) */
+#define CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_EN_Msk (0x2UL) /*!< PLL_EN (Bitfield-Mask: 0x01) */
+/* =================================================== PLL_SYS_CTRL2_REG =================================================== */
+#define CRG_XTAL_PLL_SYS_CTRL2_REG_PLL_RECALIB_Pos (15UL) /*!< PLL_RECALIB (Bit 15) */
+#define CRG_XTAL_PLL_SYS_CTRL2_REG_PLL_RECALIB_Msk (0x8000UL) /*!< PLL_RECALIB (Bitfield-Mask: 0x01) */
+/* =================================================== PLL_SYS_CTRL3_REG =================================================== */
+#define CRG_XTAL_PLL_SYS_CTRL3_REG_PLL_TEST_VCTR_Pos (7UL) /*!< PLL_TEST_VCTR (Bit 7) */
+#define CRG_XTAL_PLL_SYS_CTRL3_REG_PLL_TEST_VCTR_Msk (0x80UL) /*!< PLL_TEST_VCTR (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_PLL_SYS_CTRL3_REG_PLL_MIN_CURRENT_Pos (1UL) /*!< PLL_MIN_CURRENT (Bit 1) */
+#define CRG_XTAL_PLL_SYS_CTRL3_REG_PLL_MIN_CURRENT_Msk (0x7eUL) /*!< PLL_MIN_CURRENT (Bitfield-Mask: 0x3f) */
+/* ================================================== PLL_SYS_STATUS_REG =================================================== */
+#define CRG_XTAL_PLL_SYS_STATUS_REG_LDO_PLL_OK_Pos (15UL) /*!< LDO_PLL_OK (Bit 15) */
+#define CRG_XTAL_PLL_SYS_STATUS_REG_LDO_PLL_OK_Msk (0x8000UL) /*!< LDO_PLL_OK (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_CALIBRATION_END_Pos (11UL) /*!< PLL_CALIBRATION_END (Bit 11) */
+#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_CALIBRATION_END_Msk (0x800UL) /*!< PLL_CALIBRATION_END (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_BEST_MIN_CUR_Pos (5UL) /*!< PLL_BEST_MIN_CUR (Bit 5) */
+#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_BEST_MIN_CUR_Msk (0x7e0UL) /*!< PLL_BEST_MIN_CUR (Bitfield-Mask: 0x3f) */
+#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Pos (0UL) /*!< PLL_LOCK_FINE (Bit 0) */
+#define CRG_XTAL_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Msk (0x1UL) /*!< PLL_LOCK_FINE (Bitfield-Mask: 0x01) */
+/* ===================================================== TRIM_CTRL_REG ===================================================== */
+#define CRG_XTAL_TRIM_CTRL_REG_XTAL_SETTLE_N_Pos (8UL) /*!< XTAL_SETTLE_N (Bit 8) */
+#define CRG_XTAL_TRIM_CTRL_REG_XTAL_SETTLE_N_Msk (0x3f00UL) /*!< XTAL_SETTLE_N (Bitfield-Mask: 0x3f) */
+#define CRG_XTAL_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Pos (6UL) /*!< XTAL_TRIM_SELECT (Bit 6) */
+#define CRG_XTAL_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Msk (0xc0UL) /*!< XTAL_TRIM_SELECT (Bitfield-Mask: 0x03) */
+#define CRG_XTAL_TRIM_CTRL_REG_XTAL_COUNT_N_Pos (0UL) /*!< XTAL_COUNT_N (Bit 0) */
+#define CRG_XTAL_TRIM_CTRL_REG_XTAL_COUNT_N_Msk (0x3fUL) /*!< XTAL_COUNT_N (Bitfield-Mask: 0x3f) */
+/* =================================================== XTAL32M_CTRL0_REG =================================================== */
+#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_DXTAL_SYSPLL_ENABLE_Pos (30UL) /*!< XTAL32M_DXTAL_SYSPLL_ENABLE (Bit 30) */
+#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_DXTAL_SYSPLL_ENABLE_Msk (0x40000000UL) /*!< XTAL32M_DXTAL_SYSPLL_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_CORE_CUR_SET_Pos (15UL) /*!< XTAL32M_CORE_CUR_SET (Bit 15) */
+#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_CORE_CUR_SET_Msk (0x38000UL) /*!< XTAL32M_CORE_CUR_SET (Bitfield-Mask: 0x07) */
+#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_RCOSC_CALIBRATE_Pos (3UL) /*!< XTAL32M_RCOSC_CALIBRATE (Bit 3) */
+#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_RCOSC_CALIBRATE_Msk (0x8UL) /*!< XTAL32M_RCOSC_CALIBRATE (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_RCOSC_XTAL_DRIVE_Pos (1UL) /*!< XTAL32M_RCOSC_XTAL_DRIVE (Bit 1) */
+#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_RCOSC_XTAL_DRIVE_Msk (0x2UL) /*!< XTAL32M_RCOSC_XTAL_DRIVE (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_CXCOMP_ENABLE_Pos (0UL) /*!< XTAL32M_CXCOMP_ENABLE (Bit 0) */
+#define CRG_XTAL_XTAL32M_CTRL0_REG_XTAL32M_CXCOMP_ENABLE_Msk (0x1UL) /*!< XTAL32M_CXCOMP_ENABLE (Bitfield-Mask: 0x01) */
+/* =================================================== XTAL32M_CTRL1_REG =================================================== */
+#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDISCHARGE_Pos (28UL) /*!< XTAL32M_STARTUP_TDISCHARGE (Bit 28) */
+#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDISCHARGE_Msk (0x70000000UL) /*!< XTAL32M_STARTUP_TDISCHARGE (Bitfield-Mask: 0x07) */
+#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TSETTLE_Pos (24UL) /*!< XTAL32M_STARTUP_TSETTLE (Bit 24) */
+#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TSETTLE_Msk (0x7000000UL) /*!< XTAL32M_STARTUP_TSETTLE (Bitfield-Mask: 0x07) */
+#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_XTAL_ENABLE_Pos (23UL) /*!< XTAL32M_XTAL_ENABLE (Bit 23) */
+#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_XTAL_ENABLE_Msk (0x800000UL) /*!< XTAL32M_XTAL_ENABLE (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDRIVE_LSB_Pos (13UL) /*!< XTAL32M_STARTUP_TDRIVE_LSB (Bit 13) */
+#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDRIVE_LSB_Msk (0x7fe000UL) /*!< XTAL32M_STARTUP_TDRIVE_LSB (Bitfield-Mask: 0x3ff) */
+#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_DRIVE_CYCLES_Pos (8UL) /*!< XTAL32M_DRIVE_CYCLES (Bit 8) */
+#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_DRIVE_CYCLES_Msk (0x1f00UL) /*!< XTAL32M_DRIVE_CYCLES (Bitfield-Mask: 0x1f) */
+#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDRIVE_Pos (5UL) /*!< XTAL32M_STARTUP_TDRIVE (Bit 5) */
+#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_STARTUP_TDRIVE_Msk (0xe0UL) /*!< XTAL32M_STARTUP_TDRIVE (Bitfield-Mask: 0x07) */
+#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_RCOSC_SYNC_DELAY_TRIM_Pos (0UL) /*!< XTAL32M_RCOSC_SYNC_DELAY_TRIM (Bit 0) */
+#define CRG_XTAL_XTAL32M_CTRL1_REG_XTAL32M_RCOSC_SYNC_DELAY_TRIM_Msk (0x1fUL) /*!< XTAL32M_RCOSC_SYNC_DELAY_TRIM (Bitfield-Mask: 0x1f) */
+/* =================================================== XTAL32M_CTRL2_REG =================================================== */
+#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_RCOSC_TRIM_SNS_Pos (14UL) /*!< XTAL32M_RCOSC_TRIM_SNS (Bit 14) */
+#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_RCOSC_TRIM_SNS_Msk (0x3fc000UL) /*!< XTAL32M_RCOSC_TRIM_SNS (Bitfield-Mask: 0xff) */
+#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_CXCOMP_PHI_TRIM_Pos (12UL) /*!< XTAL32M_CXCOMP_PHI_TRIM (Bit 12) */
+#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_CXCOMP_PHI_TRIM_Msk (0x3000UL) /*!< XTAL32M_CXCOMP_PHI_TRIM (Bitfield-Mask: 0x03) */
+#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_CXCOMP_TRIM_CAP_Pos (3UL) /*!< XTAL32M_CXCOMP_TRIM_CAP (Bit 3) */
+#define CRG_XTAL_XTAL32M_CTRL2_REG_XTAL32M_CXCOMP_TRIM_CAP_Msk (0xff8UL) /*!< XTAL32M_CXCOMP_TRIM_CAP (Bitfield-Mask: 0x1ff) */
+/* =================================================== XTAL32M_CTRL3_REG =================================================== */
+#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_TRIM_STROBE_Pos (30UL) /*!< XTAL32M_RCOSC_TRIM_STROBE (Bit 30) */
+#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_TRIM_STROBE_Msk (0x40000000UL) /*!< XTAL32M_RCOSC_TRIM_STROBE (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_FREQ_DET_START_Pos (22UL) /*!< XTAL32M_FREQ_DET_START (Bit 22) */
+#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_FREQ_DET_START_Msk (0x400000UL) /*!< XTAL32M_FREQ_DET_START (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_SW_CTRL_MODE_Pos (18UL) /*!< XTAL32M_SW_CTRL_MODE (Bit 18) */
+#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_SW_CTRL_MODE_Msk (0x40000UL) /*!< XTAL32M_SW_CTRL_MODE (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_BAND_SELECT_Pos (14UL) /*!< XTAL32M_RCOSC_BAND_SELECT (Bit 14) */
+#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_BAND_SELECT_Msk (0x3c000UL) /*!< XTAL32M_RCOSC_BAND_SELECT (Bitfield-Mask: 0x0f) */
+#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_TRIM_Pos (4UL) /*!< XTAL32M_RCOSC_TRIM (Bit 4) */
+#define CRG_XTAL_XTAL32M_CTRL3_REG_XTAL32M_RCOSC_TRIM_Msk (0x3ff0UL) /*!< XTAL32M_RCOSC_TRIM (Bitfield-Mask: 0x3ff) */
+/* =================================================== XTAL32M_CTRL4_REG =================================================== */
+/* =================================================== XTAL32M_STAT0_REG =================================================== */
+#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_RCOSC_BAND_SELECT_STAT_Pos (28UL) /*!< XTAL32M_RCOSC_BAND_SELECT_STAT (Bit 28) */
+#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_RCOSC_BAND_SELECT_STAT_Msk (0xf0000000UL) /*!< XTAL32M_RCOSC_BAND_SELECT_STAT (Bitfield-Mask: 0x0f) */
+#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_RCOSC_CALIBRATION_DONE_Pos (15UL) /*!< XTAL32M_RCOSC_CALIBRATION_DONE (Bit 15) */
+#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_RCOSC_CALIBRATION_DONE_Msk (0x8000UL) /*!< XTAL32M_RCOSC_CALIBRATION_DONE (Bitfield-Mask: 0x01) */
+/* =================================================== XTAL32M_STAT1_REG =================================================== */
+#define CRG_XTAL_XTAL32M_STAT1_REG_XTAL32M_CAL_STATE_Pos (4UL) /*!< XTAL32M_CAL_STATE (Bit 4) */
+#define CRG_XTAL_XTAL32M_STAT1_REG_XTAL32M_CAL_STATE_Msk (0xf0UL) /*!< XTAL32M_CAL_STATE (Bitfield-Mask: 0x0f) */
+#define CRG_XTAL_XTAL32M_STAT1_REG_XTAL32M_STATE_Pos (0UL) /*!< XTAL32M_STATE (Bit 0) */
+#define CRG_XTAL_XTAL32M_STAT1_REG_XTAL32M_STATE_Msk (0xfUL) /*!< XTAL32M_STATE (Bitfield-Mask: 0x0f) */
+/* =================================================== XTALRDY_CTRL_REG ==================================================== */
+#define CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CLK_SEL_Pos (8UL) /*!< XTALRDY_CLK_SEL (Bit 8) */
+#define CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CLK_SEL_Msk (0x100UL) /*!< XTALRDY_CLK_SEL (Bitfield-Mask: 0x01) */
+#define CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CNT_Pos (0UL) /*!< XTALRDY_CNT (Bit 0) */
+#define CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CNT_Msk (0xffUL) /*!< XTALRDY_CNT (Bitfield-Mask: 0xff) */
+/* =================================================== XTALRDY_STAT_REG ==================================================== */
+#define CRG_XTAL_XTALRDY_STAT_REG_XTALRDY_COUNT_Pos (8UL) /*!< XTALRDY_COUNT (Bit 8) */
+#define CRG_XTAL_XTALRDY_STAT_REG_XTALRDY_COUNT_Msk (0xff00UL) /*!< XTALRDY_COUNT (Bitfield-Mask: 0xff) */
+#define CRG_XTAL_XTALRDY_STAT_REG_XTALRDY_STAT_Pos (0UL) /*!< XTALRDY_STAT (Bit 0) */
+#define CRG_XTAL_XTALRDY_STAT_REG_XTALRDY_STAT_Msk (0xffUL) /*!< XTALRDY_STAT (Bitfield-Mask: 0xff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DCDC ================ */
+/* =========================================================================================================================== */
+
+/* ==================================================== DCDC_CTRL1_REG ===================================================== */
+#define DCDC_DCDC_CTRL1_REG_DCDC_SH_ENABLE_Pos (31UL) /*!< DCDC_SH_ENABLE (Bit 31) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_SH_ENABLE_Msk (0x80000000UL) /*!< DCDC_SH_ENABLE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_STARTUP_DELAY_Pos (26UL) /*!< DCDC_STARTUP_DELAY (Bit 26) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_STARTUP_DELAY_Msk (0x7c000000UL) /*!< DCDC_STARTUP_DELAY (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_IDLE_MAX_FAST_DOWNRAMP_Pos (20UL) /*!< DCDC_IDLE_MAX_FAST_DOWNRAMP (Bit 20) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_IDLE_MAX_FAST_DOWNRAMP_Msk (0x3f00000UL) /*!< DCDC_IDLE_MAX_FAST_DOWNRAMP (Bitfield-Mask: 0x3f) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_SW_TIMEOUT_Pos (15UL) /*!< DCDC_SW_TIMEOUT (Bit 15) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_SW_TIMEOUT_Msk (0xf8000UL) /*!< DCDC_SW_TIMEOUT (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_FAST_STARTUP_Pos (14UL) /*!< DCDC_FAST_STARTUP (Bit 14) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_FAST_STARTUP_Msk (0x4000UL) /*!< DCDC_FAST_STARTUP (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_MAN_LV_MODE_Pos (13UL) /*!< DCDC_MAN_LV_MODE (Bit 13) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_MAN_LV_MODE_Msk (0x2000UL) /*!< DCDC_MAN_LV_MODE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_AUTO_LV_MODE_Pos (12UL) /*!< DCDC_AUTO_LV_MODE (Bit 12) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_AUTO_LV_MODE_Msk (0x1000UL) /*!< DCDC_AUTO_LV_MODE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_IDLE_CLK_DIV_Pos (10UL) /*!< DCDC_IDLE_CLK_DIV (Bit 10) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_IDLE_CLK_DIV_Msk (0xc00UL) /*!< DCDC_IDLE_CLK_DIV (Bitfield-Mask: 0x03) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_PRIORITY_Pos (2UL) /*!< DCDC_PRIORITY (Bit 2) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_PRIORITY_Msk (0x3fcUL) /*!< DCDC_PRIORITY (Bitfield-Mask: 0xff) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_FW_ENABLE_Pos (1UL) /*!< DCDC_FW_ENABLE (Bit 1) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_FW_ENABLE_Msk (0x2UL) /*!< DCDC_FW_ENABLE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_ENABLE_Pos (0UL) /*!< DCDC_ENABLE (Bit 0) */
+#define DCDC_DCDC_CTRL1_REG_DCDC_ENABLE_Msk (0x1UL) /*!< DCDC_ENABLE (Bitfield-Mask: 0x01) */
+/* ==================================================== DCDC_CTRL2_REG ===================================================== */
+#define DCDC_DCDC_CTRL2_REG_DCDC_V_NOK_CNT_MAX_Pos (24UL) /*!< DCDC_V_NOK_CNT_MAX (Bit 24) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_V_NOK_CNT_MAX_Msk (0xf000000UL) /*!< DCDC_V_NOK_CNT_MAX (Bitfield-Mask: 0x0f) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_N_COMP_TRIM_MAN_Pos (22UL) /*!< DCDC_N_COMP_TRIM_MAN (Bit 22) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_N_COMP_TRIM_MAN_Msk (0x400000UL) /*!< DCDC_N_COMP_TRIM_MAN (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_N_COMP_TRIM_VAL_Pos (16UL) /*!< DCDC_N_COMP_TRIM_VAL (Bit 16) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_N_COMP_TRIM_VAL_Msk (0x3f0000UL) /*!< DCDC_N_COMP_TRIM_VAL (Bitfield-Mask: 0x3f) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_TIMEOUT_IRQ_TRIG_Pos (12UL) /*!< DCDC_TIMEOUT_IRQ_TRIG (Bit 12) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_TIMEOUT_IRQ_TRIG_Msk (0xf000UL) /*!< DCDC_TIMEOUT_IRQ_TRIG (Bitfield-Mask: 0x0f) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_TIMEOUT_IRQ_RES_Pos (8UL) /*!< DCDC_TIMEOUT_IRQ_RES (Bit 8) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_TIMEOUT_IRQ_RES_Msk (0xf00UL) /*!< DCDC_TIMEOUT_IRQ_RES (Bitfield-Mask: 0x0f) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_SLOPE_CONTROL_Pos (6UL) /*!< DCDC_SLOPE_CONTROL (Bit 6) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_SLOPE_CONTROL_Msk (0xc0UL) /*!< DCDC_SLOPE_CONTROL (Bitfield-Mask: 0x03) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_VBTSTRP_TRIM_Pos (4UL) /*!< DCDC_VBTSTRP_TRIM (Bit 4) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_VBTSTRP_TRIM_Msk (0x30UL) /*!< DCDC_VBTSTRP_TRIM (Bitfield-Mask: 0x03) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_LSSUP_TRIM_Pos (2UL) /*!< DCDC_LSSUP_TRIM (Bit 2) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_LSSUP_TRIM_Msk (0xcUL) /*!< DCDC_LSSUP_TRIM (Bitfield-Mask: 0x03) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_HSGND_TRIM_Pos (0UL) /*!< DCDC_HSGND_TRIM (Bit 0) */
+#define DCDC_DCDC_CTRL2_REG_DCDC_HSGND_TRIM_Msk (0x3UL) /*!< DCDC_HSGND_TRIM (Bitfield-Mask: 0x03) */
+/* ================================================== DCDC_IRQ_CLEAR_REG =================================================== */
+#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_LOW_VBAT_IRQ_CLEAR_Pos (4UL) /*!< DCDC_LOW_VBAT_IRQ_CLEAR (Bit 4) */
+#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_LOW_VBAT_IRQ_CLEAR_Msk (0x10UL) /*!< DCDC_LOW_VBAT_IRQ_CLEAR (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Pos (3UL) /*!< DCDC_V18P_TIMEOUT_IRQ_CLEAR (Bit 3) */
+#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Msk (0x8UL) /*!< DCDC_V18P_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Pos (2UL) /*!< DCDC_VDD_TIMEOUT_IRQ_CLEAR (Bit 2) */
+#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Msk (0x4UL) /*!< DCDC_VDD_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Pos (1UL) /*!< DCDC_V18_TIMEOUT_IRQ_CLEAR (Bit 1) */
+#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Msk (0x2UL) /*!< DCDC_V18_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Pos (0UL) /*!< DCDC_V14_TIMEOUT_IRQ_CLEAR (Bit 0) */
+#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Msk (0x1UL) /*!< DCDC_V14_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01) */
+/* =================================================== DCDC_IRQ_MASK_REG =================================================== */
+#define DCDC_DCDC_IRQ_MASK_REG_DCDC_LOW_VBAT_IRQ_MASK_Pos (4UL) /*!< DCDC_LOW_VBAT_IRQ_MASK (Bit 4) */
+#define DCDC_DCDC_IRQ_MASK_REG_DCDC_LOW_VBAT_IRQ_MASK_Msk (0x10UL) /*!< DCDC_LOW_VBAT_IRQ_MASK (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Pos (3UL) /*!< DCDC_V18P_TIMEOUT_IRQ_MASK (Bit 3) */
+#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Msk (0x8UL) /*!< DCDC_V18P_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Pos (2UL) /*!< DCDC_VDD_TIMEOUT_IRQ_MASK (Bit 2) */
+#define DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Msk (0x4UL) /*!< DCDC_VDD_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Pos (1UL) /*!< DCDC_V18_TIMEOUT_IRQ_MASK (Bit 1) */
+#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Msk (0x2UL) /*!< DCDC_V18_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Pos (0UL) /*!< DCDC_V14_TIMEOUT_IRQ_MASK (Bit 0) */
+#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Msk (0x1UL) /*!< DCDC_V14_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01) */
+/* ================================================== DCDC_IRQ_STATUS_REG ================================================== */
+#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_LOW_VBAT_IRQ_STATUS_Pos (4UL) /*!< DCDC_LOW_VBAT_IRQ_STATUS (Bit 4) */
+#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_LOW_VBAT_IRQ_STATUS_Msk (0x10UL) /*!< DCDC_LOW_VBAT_IRQ_STATUS (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Pos (3UL) /*!< DCDC_V18P_TIMEOUT_IRQ_STATUS (Bit 3) */
+#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Msk (0x8UL) /*!< DCDC_V18P_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Pos (2UL) /*!< DCDC_VDD_TIMEOUT_IRQ_STATUS (Bit 2) */
+#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Msk (0x4UL) /*!< DCDC_VDD_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Pos (1UL) /*!< DCDC_V18_TIMEOUT_IRQ_STATUS (Bit 1) */
+#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Msk (0x2UL) /*!< DCDC_V18_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Pos (0UL) /*!< DCDC_V14_TIMEOUT_IRQ_STATUS (Bit 0) */
+#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Msk (0x1UL) /*!< DCDC_V14_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01) */
+/* =================================================== DCDC_STATUS1_REG ==================================================== */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_AVAILABLE_Pos (27UL) /*!< DCDC_V18P_AVAILABLE (Bit 27) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_AVAILABLE_Msk (0x8000000UL) /*!< DCDC_V18P_AVAILABLE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_AVAILABLE_Pos (26UL) /*!< DCDC_VDD_AVAILABLE (Bit 26) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_AVAILABLE_Msk (0x4000000UL) /*!< DCDC_VDD_AVAILABLE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18_AVAILABLE_Pos (25UL) /*!< DCDC_V18_AVAILABLE (Bit 25) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18_AVAILABLE_Msk (0x2000000UL) /*!< DCDC_V18_AVAILABLE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V14_AVAILABLE_Pos (24UL) /*!< DCDC_V14_AVAILABLE (Bit 24) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V14_AVAILABLE_Msk (0x1000000UL) /*!< DCDC_V14_AVAILABLE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_COMP_OK_Pos (23UL) /*!< DCDC_V18P_COMP_OK (Bit 23) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_COMP_OK_Msk (0x800000UL) /*!< DCDC_V18P_COMP_OK (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_COMP_OK_Pos (22UL) /*!< DCDC_VDD_COMP_OK (Bit 22) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_COMP_OK_Msk (0x400000UL) /*!< DCDC_VDD_COMP_OK (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18_COMP_OK_Pos (21UL) /*!< DCDC_V18_COMP_OK (Bit 21) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18_COMP_OK_Msk (0x200000UL) /*!< DCDC_V18_COMP_OK (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V14_COMP_OK_Pos (20UL) /*!< DCDC_V14_COMP_OK (Bit 20) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V14_COMP_OK_Msk (0x100000UL) /*!< DCDC_V14_COMP_OK (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_COMP_NOK_Pos (19UL) /*!< DCDC_V18P_COMP_NOK (Bit 19) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_COMP_NOK_Msk (0x80000UL) /*!< DCDC_V18P_COMP_NOK (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_COMP_NOK_Pos (18UL) /*!< DCDC_VDD_COMP_NOK (Bit 18) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_COMP_NOK_Msk (0x40000UL) /*!< DCDC_VDD_COMP_NOK (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18_COMP_NOK_Pos (17UL) /*!< DCDC_V18_COMP_NOK (Bit 17) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18_COMP_NOK_Msk (0x20000UL) /*!< DCDC_V18_COMP_NOK (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V14_COMP_NOK_Pos (16UL) /*!< DCDC_V14_COMP_NOK (Bit 16) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V14_COMP_NOK_Msk (0x10000UL) /*!< DCDC_V14_COMP_NOK (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_P_Pos (11UL) /*!< DCDC_N_COMP_P (Bit 11) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_P_Msk (0x800UL) /*!< DCDC_N_COMP_P (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_N_Pos (10UL) /*!< DCDC_N_COMP_N (Bit 10) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_N_Msk (0x400UL) /*!< DCDC_N_COMP_N (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_P_COMP_Pos (9UL) /*!< DCDC_P_COMP (Bit 9) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_P_COMP_Msk (0x200UL) /*!< DCDC_P_COMP (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_Pos (8UL) /*!< DCDC_N_COMP (Bit 8) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_N_COMP_Msk (0x100UL) /*!< DCDC_N_COMP (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_LV_MODE_Pos (7UL) /*!< DCDC_LV_MODE (Bit 7) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_LV_MODE_Msk (0x80UL) /*!< DCDC_LV_MODE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_SW_STATE_Pos (6UL) /*!< DCDC_V18P_SW_STATE (Bit 6) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18P_SW_STATE_Msk (0x40UL) /*!< DCDC_V18P_SW_STATE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_SW_STATE_Pos (5UL) /*!< DCDC_VDD_SW_STATE (Bit 5) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_VDD_SW_STATE_Msk (0x20UL) /*!< DCDC_VDD_SW_STATE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18_SW_STATE_Pos (4UL) /*!< DCDC_V18_SW_STATE (Bit 4) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V18_SW_STATE_Msk (0x10UL) /*!< DCDC_V18_SW_STATE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V14_SW_STATE_Pos (3UL) /*!< DCDC_V14_SW_STATE (Bit 3) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_V14_SW_STATE_Msk (0x8UL) /*!< DCDC_V14_SW_STATE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_N_SW_STATE_Pos (2UL) /*!< DCDC_N_SW_STATE (Bit 2) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_N_SW_STATE_Msk (0x4UL) /*!< DCDC_N_SW_STATE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_P_SW_STATE_Pos (1UL) /*!< DCDC_P_SW_STATE (Bit 1) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_P_SW_STATE_Msk (0x2UL) /*!< DCDC_P_SW_STATE (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_STARTUP_COMPLETE_Pos (0UL) /*!< DCDC_STARTUP_COMPLETE (Bit 0) */
+#define DCDC_DCDC_STATUS1_REG_DCDC_STARTUP_COMPLETE_Msk (0x1UL) /*!< DCDC_STARTUP_COMPLETE (Bitfield-Mask: 0x01) */
+/* ===================================================== DCDC_V14_REG ====================================================== */
+#define DCDC_DCDC_V14_REG_DCDC_V14_FAST_RAMPING_Pos (31UL) /*!< DCDC_V14_FAST_RAMPING (Bit 31) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_FAST_RAMPING_Msk (0x80000000UL) /*!< DCDC_V14_FAST_RAMPING (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_TRIM_Pos (27UL) /*!< DCDC_V14_TRIM (Bit 27) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_TRIM_Msk (0x8000000UL) /*!< DCDC_V14_TRIM (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_HV_Pos (22UL) /*!< DCDC_V14_CUR_LIM_MAX_HV (Bit 22) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_HV_Msk (0x7c00000UL) /*!< DCDC_V14_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_LV_Pos (17UL) /*!< DCDC_V14_CUR_LIM_MAX_LV (Bit 17) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MAX_LV_Msk (0x3e0000UL) /*!< DCDC_V14_CUR_LIM_MAX_LV (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MIN_Pos (12UL) /*!< DCDC_V14_CUR_LIM_MIN (Bit 12) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_CUR_LIM_MIN_Msk (0x1f000UL) /*!< DCDC_V14_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_IDLE_HYST_Pos (7UL) /*!< DCDC_V14_IDLE_HYST (Bit 7) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_IDLE_HYST_Msk (0xf80UL) /*!< DCDC_V14_IDLE_HYST (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_IDLE_MIN_Pos (2UL) /*!< DCDC_V14_IDLE_MIN (Bit 2) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_IDLE_MIN_Msk (0x7cUL) /*!< DCDC_V14_IDLE_MIN (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_HV_Pos (1UL) /*!< DCDC_V14_ENABLE_HV (Bit 1) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_HV_Msk (0x2UL) /*!< DCDC_V14_ENABLE_HV (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_LV_Pos (0UL) /*!< DCDC_V14_ENABLE_LV (Bit 0) */
+#define DCDC_DCDC_V14_REG_DCDC_V14_ENABLE_LV_Msk (0x1UL) /*!< DCDC_V14_ENABLE_LV (Bitfield-Mask: 0x01) */
+/* ===================================================== DCDC_V18P_REG ===================================================== */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_FAST_RAMPING_Pos (31UL) /*!< DCDC_V18P_FAST_RAMPING (Bit 31) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_FAST_RAMPING_Msk (0x80000000UL) /*!< DCDC_V18P_FAST_RAMPING (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_TRIM_Pos (27UL) /*!< DCDC_V18P_TRIM (Bit 27) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_TRIM_Msk (0x78000000UL) /*!< DCDC_V18P_TRIM (Bitfield-Mask: 0x0f) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MAX_HV_Pos (22UL) /*!< DCDC_V18P_CUR_LIM_MAX_HV (Bit 22) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MAX_HV_Msk (0x7c00000UL) /*!< DCDC_V18P_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MAX_LV_Pos (17UL) /*!< DCDC_V18P_CUR_LIM_MAX_LV (Bit 17) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MAX_LV_Msk (0x3e0000UL) /*!< DCDC_V18P_CUR_LIM_MAX_LV (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MIN_Pos (12UL) /*!< DCDC_V18P_CUR_LIM_MIN (Bit 12) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_CUR_LIM_MIN_Msk (0x1f000UL) /*!< DCDC_V18P_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_IDLE_HYST_Pos (7UL) /*!< DCDC_V18P_IDLE_HYST (Bit 7) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_IDLE_HYST_Msk (0xf80UL) /*!< DCDC_V18P_IDLE_HYST (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_IDLE_MIN_Pos (2UL) /*!< DCDC_V18P_IDLE_MIN (Bit 2) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_IDLE_MIN_Msk (0x7cUL) /*!< DCDC_V18P_IDLE_MIN (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_HV_Pos (1UL) /*!< DCDC_V18P_ENABLE_HV (Bit 1) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_HV_Msk (0x2UL) /*!< DCDC_V18P_ENABLE_HV (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_LV_Pos (0UL) /*!< DCDC_V18P_ENABLE_LV (Bit 0) */
+#define DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_LV_Msk (0x1UL) /*!< DCDC_V18P_ENABLE_LV (Bitfield-Mask: 0x01) */
+/* ===================================================== DCDC_V18_REG ====================================================== */
+#define DCDC_DCDC_V18_REG_DCDC_V18_FAST_RAMPING_Pos (31UL) /*!< DCDC_V18_FAST_RAMPING (Bit 31) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_FAST_RAMPING_Msk (0x80000000UL) /*!< DCDC_V18_FAST_RAMPING (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_TRIM_Pos (27UL) /*!< DCDC_V18_TRIM (Bit 27) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_TRIM_Msk (0x78000000UL) /*!< DCDC_V18_TRIM (Bitfield-Mask: 0x0f) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MAX_HV_Pos (22UL) /*!< DCDC_V18_CUR_LIM_MAX_HV (Bit 22) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MAX_HV_Msk (0x7c00000UL) /*!< DCDC_V18_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MAX_LV_Pos (17UL) /*!< DCDC_V18_CUR_LIM_MAX_LV (Bit 17) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MAX_LV_Msk (0x3e0000UL) /*!< DCDC_V18_CUR_LIM_MAX_LV (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MIN_Pos (12UL) /*!< DCDC_V18_CUR_LIM_MIN (Bit 12) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_CUR_LIM_MIN_Msk (0x1f000UL) /*!< DCDC_V18_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_IDLE_HYST_Pos (7UL) /*!< DCDC_V18_IDLE_HYST (Bit 7) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_IDLE_HYST_Msk (0xf80UL) /*!< DCDC_V18_IDLE_HYST (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_IDLE_MIN_Pos (2UL) /*!< DCDC_V18_IDLE_MIN (Bit 2) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_IDLE_MIN_Msk (0x7cUL) /*!< DCDC_V18_IDLE_MIN (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_HV_Pos (1UL) /*!< DCDC_V18_ENABLE_HV (Bit 1) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_HV_Msk (0x2UL) /*!< DCDC_V18_ENABLE_HV (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_LV_Pos (0UL) /*!< DCDC_V18_ENABLE_LV (Bit 0) */
+#define DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_LV_Msk (0x1UL) /*!< DCDC_V18_ENABLE_LV (Bitfield-Mask: 0x01) */
+/* ===================================================== DCDC_VDD_REG ====================================================== */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_FAST_RAMPING_Pos (31UL) /*!< DCDC_VDD_FAST_RAMPING (Bit 31) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_FAST_RAMPING_Msk (0x80000000UL) /*!< DCDC_VDD_FAST_RAMPING (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_TRIM_Pos (27UL) /*!< DCDC_VDD_TRIM (Bit 27) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_TRIM_Msk (0x38000000UL) /*!< DCDC_VDD_TRIM (Bitfield-Mask: 0x07) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MAX_HV_Pos (22UL) /*!< DCDC_VDD_CUR_LIM_MAX_HV (Bit 22) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MAX_HV_Msk (0x7c00000UL) /*!< DCDC_VDD_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MAX_LV_Pos (17UL) /*!< DCDC_VDD_CUR_LIM_MAX_LV (Bit 17) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MAX_LV_Msk (0x3e0000UL) /*!< DCDC_VDD_CUR_LIM_MAX_LV (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MIN_Pos (12UL) /*!< DCDC_VDD_CUR_LIM_MIN (Bit 12) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_CUR_LIM_MIN_Msk (0x1f000UL) /*!< DCDC_VDD_CUR_LIM_MIN (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_IDLE_HYST_Pos (7UL) /*!< DCDC_VDD_IDLE_HYST (Bit 7) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_IDLE_HYST_Msk (0xf80UL) /*!< DCDC_VDD_IDLE_HYST (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_IDLE_MIN_Pos (2UL) /*!< DCDC_VDD_IDLE_MIN (Bit 2) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_IDLE_MIN_Msk (0x7cUL) /*!< DCDC_VDD_IDLE_MIN (Bitfield-Mask: 0x1f) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_HV_Pos (1UL) /*!< DCDC_VDD_ENABLE_HV (Bit 1) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_HV_Msk (0x2UL) /*!< DCDC_VDD_ENABLE_HV (Bitfield-Mask: 0x01) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_LV_Pos (0UL) /*!< DCDC_VDD_ENABLE_LV (Bit 0) */
+#define DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_LV_Msk (0x1UL) /*!< DCDC_VDD_ENABLE_LV (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DMA ================ */
+/* =========================================================================================================================== */
+
+/* =================================================== DMA0_A_START_REG ==================================================== */
+#define DMA_DMA0_A_START_REG_DMA0_A_START_Pos (0UL) /*!< DMA0_A_START (Bit 0) */
+#define DMA_DMA0_A_START_REG_DMA0_A_START_Msk (0xffffffffUL) /*!< DMA0_A_START (Bitfield-Mask: 0xffffffff) */
+/* =================================================== DMA0_B_START_REG ==================================================== */
+#define DMA_DMA0_B_START_REG_DMA0_B_START_Pos (0UL) /*!< DMA0_B_START (Bit 0) */
+#define DMA_DMA0_B_START_REG_DMA0_B_START_Msk (0xffffffffUL) /*!< DMA0_B_START (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== DMA0_CTRL_REG ===================================================== */
+#define DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */
+#define DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */
+#define DMA_DMA0_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */
+#define DMA_DMA0_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */
+#define DMA_DMA0_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */
+#define DMA_DMA0_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */
+#define DMA_DMA0_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */
+#define DMA_DMA0_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */
+#define DMA_DMA0_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */
+#define DMA_DMA0_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */
+#define DMA_DMA0_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */
+#define DMA_DMA0_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */
+#define DMA_DMA0_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */
+#define DMA_DMA0_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */
+#define DMA_DMA0_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */
+#define DMA_DMA0_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA0_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */
+#define DMA_DMA0_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA0_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */
+#define DMA_DMA0_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */
+#define DMA_DMA0_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */
+#define DMA_DMA0_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */
+#define DMA_DMA0_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */
+#define DMA_DMA0_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */
+/* ===================================================== DMA0_IDX_REG ====================================================== */
+#define DMA_DMA0_IDX_REG_DMA0_IDX_Pos (0UL) /*!< DMA0_IDX (Bit 0) */
+#define DMA_DMA0_IDX_REG_DMA0_IDX_Msk (0xffffUL) /*!< DMA0_IDX (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA0_INT_REG ====================================================== */
+#define DMA_DMA0_INT_REG_DMA0_INT_Pos (0UL) /*!< DMA0_INT (Bit 0) */
+#define DMA_DMA0_INT_REG_DMA0_INT_Msk (0xffffUL) /*!< DMA0_INT (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA0_LEN_REG ====================================================== */
+#define DMA_DMA0_LEN_REG_DMA0_LEN_Pos (0UL) /*!< DMA0_LEN (Bit 0) */
+#define DMA_DMA0_LEN_REG_DMA0_LEN_Msk (0xffffUL) /*!< DMA0_LEN (Bitfield-Mask: 0xffff) */
+/* =================================================== DMA1_A_START_REG ==================================================== */
+#define DMA_DMA1_A_START_REG_DMA1_A_START_Pos (0UL) /*!< DMA1_A_START (Bit 0) */
+#define DMA_DMA1_A_START_REG_DMA1_A_START_Msk (0xffffffffUL) /*!< DMA1_A_START (Bitfield-Mask: 0xffffffff) */
+/* =================================================== DMA1_B_START_REG ==================================================== */
+#define DMA_DMA1_B_START_REG_DMA1_B_START_Pos (0UL) /*!< DMA1_B_START (Bit 0) */
+#define DMA_DMA1_B_START_REG_DMA1_B_START_Msk (0xffffffffUL) /*!< DMA1_B_START (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== DMA1_CTRL_REG ===================================================== */
+#define DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */
+#define DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */
+#define DMA_DMA1_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */
+#define DMA_DMA1_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */
+#define DMA_DMA1_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */
+#define DMA_DMA1_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */
+#define DMA_DMA1_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */
+#define DMA_DMA1_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */
+#define DMA_DMA1_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */
+#define DMA_DMA1_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */
+#define DMA_DMA1_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */
+#define DMA_DMA1_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */
+#define DMA_DMA1_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */
+#define DMA_DMA1_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */
+#define DMA_DMA1_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */
+#define DMA_DMA1_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA1_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */
+#define DMA_DMA1_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA1_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */
+#define DMA_DMA1_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */
+#define DMA_DMA1_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */
+#define DMA_DMA1_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */
+#define DMA_DMA1_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */
+#define DMA_DMA1_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */
+/* ===================================================== DMA1_IDX_REG ====================================================== */
+#define DMA_DMA1_IDX_REG_DMA1_IDX_Pos (0UL) /*!< DMA1_IDX (Bit 0) */
+#define DMA_DMA1_IDX_REG_DMA1_IDX_Msk (0xffffUL) /*!< DMA1_IDX (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA1_INT_REG ====================================================== */
+#define DMA_DMA1_INT_REG_DMA1_INT_Pos (0UL) /*!< DMA1_INT (Bit 0) */
+#define DMA_DMA1_INT_REG_DMA1_INT_Msk (0xffffUL) /*!< DMA1_INT (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA1_LEN_REG ====================================================== */
+#define DMA_DMA1_LEN_REG_DMA1_LEN_Pos (0UL) /*!< DMA1_LEN (Bit 0) */
+#define DMA_DMA1_LEN_REG_DMA1_LEN_Msk (0xffffUL) /*!< DMA1_LEN (Bitfield-Mask: 0xffff) */
+/* =================================================== DMA2_A_START_REG ==================================================== */
+#define DMA_DMA2_A_START_REG_DMA2_A_START_Pos (0UL) /*!< DMA2_A_START (Bit 0) */
+#define DMA_DMA2_A_START_REG_DMA2_A_START_Msk (0xffffffffUL) /*!< DMA2_A_START (Bitfield-Mask: 0xffffffff) */
+/* =================================================== DMA2_B_START_REG ==================================================== */
+#define DMA_DMA2_B_START_REG_DMA2_B_START_Pos (0UL) /*!< DMA2_B_START (Bit 0) */
+#define DMA_DMA2_B_START_REG_DMA2_B_START_Msk (0xffffffffUL) /*!< DMA2_B_START (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== DMA2_CTRL_REG ===================================================== */
+#define DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */
+#define DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */
+#define DMA_DMA2_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */
+#define DMA_DMA2_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */
+#define DMA_DMA2_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */
+#define DMA_DMA2_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */
+#define DMA_DMA2_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */
+#define DMA_DMA2_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */
+#define DMA_DMA2_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */
+#define DMA_DMA2_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */
+#define DMA_DMA2_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */
+#define DMA_DMA2_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */
+#define DMA_DMA2_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */
+#define DMA_DMA2_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */
+#define DMA_DMA2_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */
+#define DMA_DMA2_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA2_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */
+#define DMA_DMA2_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA2_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */
+#define DMA_DMA2_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */
+#define DMA_DMA2_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */
+#define DMA_DMA2_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */
+#define DMA_DMA2_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */
+#define DMA_DMA2_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */
+/* ===================================================== DMA2_IDX_REG ====================================================== */
+#define DMA_DMA2_IDX_REG_DMA2_IDX_Pos (0UL) /*!< DMA2_IDX (Bit 0) */
+#define DMA_DMA2_IDX_REG_DMA2_IDX_Msk (0xffffUL) /*!< DMA2_IDX (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA2_INT_REG ====================================================== */
+#define DMA_DMA2_INT_REG_DMA2_INT_Pos (0UL) /*!< DMA2_INT (Bit 0) */
+#define DMA_DMA2_INT_REG_DMA2_INT_Msk (0xffffUL) /*!< DMA2_INT (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA2_LEN_REG ====================================================== */
+#define DMA_DMA2_LEN_REG_DMA2_LEN_Pos (0UL) /*!< DMA2_LEN (Bit 0) */
+#define DMA_DMA2_LEN_REG_DMA2_LEN_Msk (0xffffUL) /*!< DMA2_LEN (Bitfield-Mask: 0xffff) */
+/* =================================================== DMA3_A_START_REG ==================================================== */
+#define DMA_DMA3_A_START_REG_DMA3_A_START_Pos (0UL) /*!< DMA3_A_START (Bit 0) */
+#define DMA_DMA3_A_START_REG_DMA3_A_START_Msk (0xffffffffUL) /*!< DMA3_A_START (Bitfield-Mask: 0xffffffff) */
+/* =================================================== DMA3_B_START_REG ==================================================== */
+#define DMA_DMA3_B_START_REG_DMA3_B_START_Pos (0UL) /*!< DMA3_B_START (Bit 0) */
+#define DMA_DMA3_B_START_REG_DMA3_B_START_Msk (0xffffffffUL) /*!< DMA3_B_START (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== DMA3_CTRL_REG ===================================================== */
+#define DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */
+#define DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */
+#define DMA_DMA3_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */
+#define DMA_DMA3_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */
+#define DMA_DMA3_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */
+#define DMA_DMA3_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */
+#define DMA_DMA3_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */
+#define DMA_DMA3_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */
+#define DMA_DMA3_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */
+#define DMA_DMA3_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */
+#define DMA_DMA3_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */
+#define DMA_DMA3_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */
+#define DMA_DMA3_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */
+#define DMA_DMA3_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */
+#define DMA_DMA3_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */
+#define DMA_DMA3_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA3_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */
+#define DMA_DMA3_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA3_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */
+#define DMA_DMA3_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */
+#define DMA_DMA3_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */
+#define DMA_DMA3_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */
+#define DMA_DMA3_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */
+#define DMA_DMA3_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */
+/* ===================================================== DMA3_IDX_REG ====================================================== */
+#define DMA_DMA3_IDX_REG_DMA3_IDX_Pos (0UL) /*!< DMA3_IDX (Bit 0) */
+#define DMA_DMA3_IDX_REG_DMA3_IDX_Msk (0xffffUL) /*!< DMA3_IDX (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA3_INT_REG ====================================================== */
+#define DMA_DMA3_INT_REG_DMA3_INT_Pos (0UL) /*!< DMA3_INT (Bit 0) */
+#define DMA_DMA3_INT_REG_DMA3_INT_Msk (0xffffUL) /*!< DMA3_INT (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA3_LEN_REG ====================================================== */
+#define DMA_DMA3_LEN_REG_DMA3_LEN_Pos (0UL) /*!< DMA3_LEN (Bit 0) */
+#define DMA_DMA3_LEN_REG_DMA3_LEN_Msk (0xffffUL) /*!< DMA3_LEN (Bitfield-Mask: 0xffff) */
+/* =================================================== DMA4_A_START_REG ==================================================== */
+#define DMA_DMA4_A_START_REG_DMA4_A_START_Pos (0UL) /*!< DMA4_A_START (Bit 0) */
+#define DMA_DMA4_A_START_REG_DMA4_A_START_Msk (0xffffffffUL) /*!< DMA4_A_START (Bitfield-Mask: 0xffffffff) */
+/* =================================================== DMA4_B_START_REG ==================================================== */
+#define DMA_DMA4_B_START_REG_DMA4_B_START_Pos (0UL) /*!< DMA4_B_START (Bit 0) */
+#define DMA_DMA4_B_START_REG_DMA4_B_START_Msk (0xffffffffUL) /*!< DMA4_B_START (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== DMA4_CTRL_REG ===================================================== */
+#define DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */
+#define DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */
+#define DMA_DMA4_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */
+#define DMA_DMA4_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */
+#define DMA_DMA4_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */
+#define DMA_DMA4_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */
+#define DMA_DMA4_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */
+#define DMA_DMA4_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */
+#define DMA_DMA4_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */
+#define DMA_DMA4_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */
+#define DMA_DMA4_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */
+#define DMA_DMA4_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */
+#define DMA_DMA4_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */
+#define DMA_DMA4_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */
+#define DMA_DMA4_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */
+#define DMA_DMA4_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA4_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */
+#define DMA_DMA4_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA4_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */
+#define DMA_DMA4_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */
+#define DMA_DMA4_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */
+#define DMA_DMA4_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */
+#define DMA_DMA4_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */
+#define DMA_DMA4_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */
+/* ===================================================== DMA4_IDX_REG ====================================================== */
+#define DMA_DMA4_IDX_REG_DMA4_IDX_Pos (0UL) /*!< DMA4_IDX (Bit 0) */
+#define DMA_DMA4_IDX_REG_DMA4_IDX_Msk (0xffffUL) /*!< DMA4_IDX (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA4_INT_REG ====================================================== */
+#define DMA_DMA4_INT_REG_DMA4_INT_Pos (0UL) /*!< DMA4_INT (Bit 0) */
+#define DMA_DMA4_INT_REG_DMA4_INT_Msk (0xffffUL) /*!< DMA4_INT (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA4_LEN_REG ====================================================== */
+#define DMA_DMA4_LEN_REG_DMA4_LEN_Pos (0UL) /*!< DMA4_LEN (Bit 0) */
+#define DMA_DMA4_LEN_REG_DMA4_LEN_Msk (0xffffUL) /*!< DMA4_LEN (Bitfield-Mask: 0xffff) */
+/* =================================================== DMA5_A_START_REG ==================================================== */
+#define DMA_DMA5_A_START_REG_DMA5_A_START_Pos (0UL) /*!< DMA5_A_START (Bit 0) */
+#define DMA_DMA5_A_START_REG_DMA5_A_START_Msk (0xffffffffUL) /*!< DMA5_A_START (Bitfield-Mask: 0xffffffff) */
+/* =================================================== DMA5_B_START_REG ==================================================== */
+#define DMA_DMA5_B_START_REG_DMA5_B_START_Pos (0UL) /*!< DMA5_B_START (Bit 0) */
+#define DMA_DMA5_B_START_REG_DMA5_B_START_Msk (0xffffffffUL) /*!< DMA5_B_START (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== DMA5_CTRL_REG ===================================================== */
+#define DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */
+#define DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */
+#define DMA_DMA5_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */
+#define DMA_DMA5_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */
+#define DMA_DMA5_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */
+#define DMA_DMA5_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */
+#define DMA_DMA5_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */
+#define DMA_DMA5_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */
+#define DMA_DMA5_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */
+#define DMA_DMA5_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */
+#define DMA_DMA5_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */
+#define DMA_DMA5_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */
+#define DMA_DMA5_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */
+#define DMA_DMA5_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */
+#define DMA_DMA5_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */
+#define DMA_DMA5_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA5_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */
+#define DMA_DMA5_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA5_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */
+#define DMA_DMA5_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */
+#define DMA_DMA5_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */
+#define DMA_DMA5_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */
+#define DMA_DMA5_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */
+#define DMA_DMA5_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */
+/* ===================================================== DMA5_IDX_REG ====================================================== */
+#define DMA_DMA5_IDX_REG_DMA5_IDX_Pos (0UL) /*!< DMA5_IDX (Bit 0) */
+#define DMA_DMA5_IDX_REG_DMA5_IDX_Msk (0xffffUL) /*!< DMA5_IDX (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA5_INT_REG ====================================================== */
+#define DMA_DMA5_INT_REG_DMA5_INT_Pos (0UL) /*!< DMA5_INT (Bit 0) */
+#define DMA_DMA5_INT_REG_DMA5_INT_Msk (0xffffUL) /*!< DMA5_INT (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA5_LEN_REG ====================================================== */
+#define DMA_DMA5_LEN_REG_DMA5_LEN_Pos (0UL) /*!< DMA5_LEN (Bit 0) */
+#define DMA_DMA5_LEN_REG_DMA5_LEN_Msk (0xffffUL) /*!< DMA5_LEN (Bitfield-Mask: 0xffff) */
+/* =================================================== DMA6_A_START_REG ==================================================== */
+#define DMA_DMA6_A_START_REG_DMA6_A_START_Pos (0UL) /*!< DMA6_A_START (Bit 0) */
+#define DMA_DMA6_A_START_REG_DMA6_A_START_Msk (0xffffffffUL) /*!< DMA6_A_START (Bitfield-Mask: 0xffffffff) */
+/* =================================================== DMA6_B_START_REG ==================================================== */
+#define DMA_DMA6_B_START_REG_DMA6_B_START_Pos (0UL) /*!< DMA6_B_START (Bit 0) */
+#define DMA_DMA6_B_START_REG_DMA6_B_START_Msk (0xffffffffUL) /*!< DMA6_B_START (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== DMA6_CTRL_REG ===================================================== */
+#define DMA_DMA6_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */
+#define DMA_DMA6_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */
+#define DMA_DMA6_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */
+#define DMA_DMA6_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */
+#define DMA_DMA6_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */
+#define DMA_DMA6_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */
+#define DMA_DMA6_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */
+#define DMA_DMA6_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */
+#define DMA_DMA6_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */
+#define DMA_DMA6_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */
+#define DMA_DMA6_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */
+#define DMA_DMA6_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */
+#define DMA_DMA6_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */
+#define DMA_DMA6_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */
+#define DMA_DMA6_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */
+#define DMA_DMA6_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA6_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */
+#define DMA_DMA6_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA6_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */
+#define DMA_DMA6_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */
+#define DMA_DMA6_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */
+#define DMA_DMA6_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */
+#define DMA_DMA6_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */
+#define DMA_DMA6_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */
+/* ===================================================== DMA6_IDX_REG ====================================================== */
+#define DMA_DMA6_IDX_REG_DMA6_IDX_Pos (0UL) /*!< DMA6_IDX (Bit 0) */
+#define DMA_DMA6_IDX_REG_DMA6_IDX_Msk (0xffffUL) /*!< DMA6_IDX (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA6_INT_REG ====================================================== */
+#define DMA_DMA6_INT_REG_DMA6_INT_Pos (0UL) /*!< DMA6_INT (Bit 0) */
+#define DMA_DMA6_INT_REG_DMA6_INT_Msk (0xffffUL) /*!< DMA6_INT (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA6_LEN_REG ====================================================== */
+#define DMA_DMA6_LEN_REG_DMA6_LEN_Pos (0UL) /*!< DMA6_LEN (Bit 0) */
+#define DMA_DMA6_LEN_REG_DMA6_LEN_Msk (0xffffUL) /*!< DMA6_LEN (Bitfield-Mask: 0xffff) */
+/* =================================================== DMA7_A_START_REG ==================================================== */
+#define DMA_DMA7_A_START_REG_DMA7_A_START_Pos (0UL) /*!< DMA7_A_START (Bit 0) */
+#define DMA_DMA7_A_START_REG_DMA7_A_START_Msk (0xffffffffUL) /*!< DMA7_A_START (Bitfield-Mask: 0xffffffff) */
+/* =================================================== DMA7_B_START_REG ==================================================== */
+#define DMA_DMA7_B_START_REG_DMA7_B_START_Pos (0UL) /*!< DMA7_B_START (Bit 0) */
+#define DMA_DMA7_B_START_REG_DMA7_B_START_Msk (0xffffffffUL) /*!< DMA7_B_START (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== DMA7_CTRL_REG ===================================================== */
+#define DMA_DMA7_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL) /*!< BUS_ERROR_DETECT (Bit 15) */
+#define DMA_DMA7_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL) /*!< BUS_ERROR_DETECT (Bitfield-Mask: 0x01) */
+#define DMA_DMA7_CTRL_REG_BURST_MODE_Pos (13UL) /*!< BURST_MODE (Bit 13) */
+#define DMA_DMA7_CTRL_REG_BURST_MODE_Msk (0x6000UL) /*!< BURST_MODE (Bitfield-Mask: 0x03) */
+#define DMA_DMA7_CTRL_REG_REQ_SENSE_Pos (12UL) /*!< REQ_SENSE (Bit 12) */
+#define DMA_DMA7_CTRL_REG_REQ_SENSE_Msk (0x1000UL) /*!< REQ_SENSE (Bitfield-Mask: 0x01) */
+#define DMA_DMA7_CTRL_REG_DMA_INIT_Pos (11UL) /*!< DMA_INIT (Bit 11) */
+#define DMA_DMA7_CTRL_REG_DMA_INIT_Msk (0x800UL) /*!< DMA_INIT (Bitfield-Mask: 0x01) */
+#define DMA_DMA7_CTRL_REG_DMA_IDLE_Pos (10UL) /*!< DMA_IDLE (Bit 10) */
+#define DMA_DMA7_CTRL_REG_DMA_IDLE_Msk (0x400UL) /*!< DMA_IDLE (Bitfield-Mask: 0x01) */
+#define DMA_DMA7_CTRL_REG_DMA_PRIO_Pos (7UL) /*!< DMA_PRIO (Bit 7) */
+#define DMA_DMA7_CTRL_REG_DMA_PRIO_Msk (0x380UL) /*!< DMA_PRIO (Bitfield-Mask: 0x07) */
+#define DMA_DMA7_CTRL_REG_CIRCULAR_Pos (6UL) /*!< CIRCULAR (Bit 6) */
+#define DMA_DMA7_CTRL_REG_CIRCULAR_Msk (0x40UL) /*!< CIRCULAR (Bitfield-Mask: 0x01) */
+#define DMA_DMA7_CTRL_REG_AINC_Pos (5UL) /*!< AINC (Bit 5) */
+#define DMA_DMA7_CTRL_REG_AINC_Msk (0x20UL) /*!< AINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA7_CTRL_REG_BINC_Pos (4UL) /*!< BINC (Bit 4) */
+#define DMA_DMA7_CTRL_REG_BINC_Msk (0x10UL) /*!< BINC (Bitfield-Mask: 0x01) */
+#define DMA_DMA7_CTRL_REG_DREQ_MODE_Pos (3UL) /*!< DREQ_MODE (Bit 3) */
+#define DMA_DMA7_CTRL_REG_DREQ_MODE_Msk (0x8UL) /*!< DREQ_MODE (Bitfield-Mask: 0x01) */
+#define DMA_DMA7_CTRL_REG_BW_Pos (1UL) /*!< BW (Bit 1) */
+#define DMA_DMA7_CTRL_REG_BW_Msk (0x6UL) /*!< BW (Bitfield-Mask: 0x03) */
+#define DMA_DMA7_CTRL_REG_DMA_ON_Pos (0UL) /*!< DMA_ON (Bit 0) */
+#define DMA_DMA7_CTRL_REG_DMA_ON_Msk (0x1UL) /*!< DMA_ON (Bitfield-Mask: 0x01) */
+/* ===================================================== DMA7_IDX_REG ====================================================== */
+#define DMA_DMA7_IDX_REG_DMA7_IDX_Pos (0UL) /*!< DMA7_IDX (Bit 0) */
+#define DMA_DMA7_IDX_REG_DMA7_IDX_Msk (0xffffUL) /*!< DMA7_IDX (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA7_INT_REG ====================================================== */
+#define DMA_DMA7_INT_REG_DMA7_INT_Pos (0UL) /*!< DMA7_INT (Bit 0) */
+#define DMA_DMA7_INT_REG_DMA7_INT_Msk (0xffffUL) /*!< DMA7_INT (Bitfield-Mask: 0xffff) */
+/* ===================================================== DMA7_LEN_REG ====================================================== */
+#define DMA_DMA7_LEN_REG_DMA7_LEN_Pos (0UL) /*!< DMA7_LEN (Bit 0) */
+#define DMA_DMA7_LEN_REG_DMA7_LEN_Msk (0xffffUL) /*!< DMA7_LEN (Bitfield-Mask: 0xffff) */
+/* =================================================== DMA_CLEAR_INT_REG =================================================== */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Pos (7UL) /*!< DMA_RST_IRQ_CH7 (Bit 7) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Msk (0x80UL) /*!< DMA_RST_IRQ_CH7 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Pos (6UL) /*!< DMA_RST_IRQ_CH6 (Bit 6) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Msk (0x40UL) /*!< DMA_RST_IRQ_CH6 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Pos (5UL) /*!< DMA_RST_IRQ_CH5 (Bit 5) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Msk (0x20UL) /*!< DMA_RST_IRQ_CH5 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Pos (4UL) /*!< DMA_RST_IRQ_CH4 (Bit 4) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Msk (0x10UL) /*!< DMA_RST_IRQ_CH4 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Pos (3UL) /*!< DMA_RST_IRQ_CH3 (Bit 3) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Msk (0x8UL) /*!< DMA_RST_IRQ_CH3 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Pos (2UL) /*!< DMA_RST_IRQ_CH2 (Bit 2) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Msk (0x4UL) /*!< DMA_RST_IRQ_CH2 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Pos (1UL) /*!< DMA_RST_IRQ_CH1 (Bit 1) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Msk (0x2UL) /*!< DMA_RST_IRQ_CH1 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Pos (0UL) /*!< DMA_RST_IRQ_CH0 (Bit 0) */
+#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Msk (0x1UL) /*!< DMA_RST_IRQ_CH0 (Bitfield-Mask: 0x01) */
+/* =================================================== DMA_INT_MASK_REG ==================================================== */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE7_Pos (7UL) /*!< DMA_IRQ_ENABLE7 (Bit 7) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE7_Msk (0x80UL) /*!< DMA_IRQ_ENABLE7 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE6_Pos (6UL) /*!< DMA_IRQ_ENABLE6 (Bit 6) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE6_Msk (0x40UL) /*!< DMA_IRQ_ENABLE6 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Pos (5UL) /*!< DMA_IRQ_ENABLE5 (Bit 5) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Msk (0x20UL) /*!< DMA_IRQ_ENABLE5 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Pos (4UL) /*!< DMA_IRQ_ENABLE4 (Bit 4) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Msk (0x10UL) /*!< DMA_IRQ_ENABLE4 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Pos (3UL) /*!< DMA_IRQ_ENABLE3 (Bit 3) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Msk (0x8UL) /*!< DMA_IRQ_ENABLE3 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Pos (2UL) /*!< DMA_IRQ_ENABLE2 (Bit 2) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Msk (0x4UL) /*!< DMA_IRQ_ENABLE2 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Pos (1UL) /*!< DMA_IRQ_ENABLE1 (Bit 1) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Msk (0x2UL) /*!< DMA_IRQ_ENABLE1 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Pos (0UL) /*!< DMA_IRQ_ENABLE0 (Bit 0) */
+#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Msk (0x1UL) /*!< DMA_IRQ_ENABLE0 (Bitfield-Mask: 0x01) */
+/* ================================================== DMA_INT_STATUS_REG =================================================== */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR7_Pos (15UL) /*!< DMA_BUS_ERR7 (Bit 15) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR7_Msk (0x8000UL) /*!< DMA_BUS_ERR7 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR6_Pos (14UL) /*!< DMA_BUS_ERR6 (Bit 14) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR6_Msk (0x4000UL) /*!< DMA_BUS_ERR6 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Pos (13UL) /*!< DMA_BUS_ERR5 (Bit 13) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Msk (0x2000UL) /*!< DMA_BUS_ERR5 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Pos (12UL) /*!< DMA_BUS_ERR4 (Bit 12) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Msk (0x1000UL) /*!< DMA_BUS_ERR4 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Pos (11UL) /*!< DMA_BUS_ERR3 (Bit 11) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Msk (0x800UL) /*!< DMA_BUS_ERR3 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Pos (10UL) /*!< DMA_BUS_ERR2 (Bit 10) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Msk (0x400UL) /*!< DMA_BUS_ERR2 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Pos (9UL) /*!< DMA_BUS_ERR1 (Bit 9) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Msk (0x200UL) /*!< DMA_BUS_ERR1 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Pos (8UL) /*!< DMA_BUS_ERR0 (Bit 8) */
+#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Msk (0x100UL) /*!< DMA_BUS_ERR0 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Pos (7UL) /*!< DMA_IRQ_CH7 (Bit 7) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Msk (0x80UL) /*!< DMA_IRQ_CH7 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Pos (6UL) /*!< DMA_IRQ_CH6 (Bit 6) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Msk (0x40UL) /*!< DMA_IRQ_CH6 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Pos (5UL) /*!< DMA_IRQ_CH5 (Bit 5) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Msk (0x20UL) /*!< DMA_IRQ_CH5 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Pos (4UL) /*!< DMA_IRQ_CH4 (Bit 4) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Msk (0x10UL) /*!< DMA_IRQ_CH4 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Pos (3UL) /*!< DMA_IRQ_CH3 (Bit 3) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Msk (0x8UL) /*!< DMA_IRQ_CH3 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Pos (2UL) /*!< DMA_IRQ_CH2 (Bit 2) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Msk (0x4UL) /*!< DMA_IRQ_CH2 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Pos (1UL) /*!< DMA_IRQ_CH1 (Bit 1) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Msk (0x2UL) /*!< DMA_IRQ_CH1 (Bitfield-Mask: 0x01) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Pos (0UL) /*!< DMA_IRQ_CH0 (Bit 0) */
+#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Msk (0x1UL) /*!< DMA_IRQ_CH0 (Bitfield-Mask: 0x01) */
+/* ==================================================== DMA_REQ_MUX_REG ==================================================== */
+#define DMA_DMA_REQ_MUX_REG_DMA67_SEL_Pos (12UL) /*!< DMA67_SEL (Bit 12) */
+#define DMA_DMA_REQ_MUX_REG_DMA67_SEL_Msk (0xf000UL) /*!< DMA67_SEL (Bitfield-Mask: 0x0f) */
+#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Pos (8UL) /*!< DMA45_SEL (Bit 8) */
+#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Msk (0xf00UL) /*!< DMA45_SEL (Bitfield-Mask: 0x0f) */
+#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Pos (4UL) /*!< DMA23_SEL (Bit 4) */
+#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Msk (0xf0UL) /*!< DMA23_SEL (Bitfield-Mask: 0x0f) */
+#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Pos (0UL) /*!< DMA01_SEL (Bit 0) */
+#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Msk (0xfUL) /*!< DMA01_SEL (Bitfield-Mask: 0x0f) */
+
+
+/* =========================================================================================================================== */
+/* ================ DW ================ */
+/* =========================================================================================================================== */
+
+/* =================================================== AHB_DMA_CCLM1_REG =================================================== */
+#define DW_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */
+#define DW_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */
+/* =================================================== AHB_DMA_CCLM2_REG =================================================== */
+#define DW_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */
+#define DW_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */
+/* =================================================== AHB_DMA_CCLM3_REG =================================================== */
+#define DW_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */
+#define DW_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */
+/* =================================================== AHB_DMA_CCLM4_REG =================================================== */
+#define DW_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Pos (0UL) /*!< AHB_DMA_CCLM (Bit 0) */
+#define DW_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Msk (0xffffUL) /*!< AHB_DMA_CCLM (Bitfield-Mask: 0xffff) */
+/* ================================================ AHB_DMA_DFLT_MASTER_REG ================================================ */
+#define DW_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Pos (0UL) /*!< AHB_DMA_DFLT_MASTER (Bit 0) */
+#define DW_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Msk (0xfUL) /*!< AHB_DMA_DFLT_MASTER (Bitfield-Mask: 0x0f) */
+/* ==================================================== AHB_DMA_PL1_REG ==================================================== */
+#define DW_AHB_DMA_PL1_REG_AHB_DMA_PL1_Pos (0UL) /*!< AHB_DMA_PL1 (Bit 0) */
+#define DW_AHB_DMA_PL1_REG_AHB_DMA_PL1_Msk (0xfUL) /*!< AHB_DMA_PL1 (Bitfield-Mask: 0x0f) */
+/* ==================================================== AHB_DMA_PL2_REG ==================================================== */
+#define DW_AHB_DMA_PL2_REG_AHB_DMA_PL2_Pos (0UL) /*!< AHB_DMA_PL2 (Bit 0) */
+#define DW_AHB_DMA_PL2_REG_AHB_DMA_PL2_Msk (0xfUL) /*!< AHB_DMA_PL2 (Bitfield-Mask: 0x0f) */
+/* ==================================================== AHB_DMA_PL3_REG ==================================================== */
+#define DW_AHB_DMA_PL3_REG_AHB_DMA_PL3_Pos (0UL) /*!< AHB_DMA_PL3 (Bit 0) */
+#define DW_AHB_DMA_PL3_REG_AHB_DMA_PL3_Msk (0xfUL) /*!< AHB_DMA_PL3 (Bitfield-Mask: 0x0f) */
+/* ==================================================== AHB_DMA_PL4_REG ==================================================== */
+#define DW_AHB_DMA_PL4_REG_AHB_DMA_PL4_Pos (0UL) /*!< AHB_DMA_PL4 (Bit 0) */
+#define DW_AHB_DMA_PL4_REG_AHB_DMA_PL4_Msk (0xfUL) /*!< AHB_DMA_PL4 (Bitfield-Mask: 0x0f) */
+/* ==================================================== AHB_DMA_TCL_REG ==================================================== */
+#define DW_AHB_DMA_TCL_REG_AHB_DMA_TCL_Pos (0UL) /*!< AHB_DMA_TCL (Bit 0) */
+#define DW_AHB_DMA_TCL_REG_AHB_DMA_TCL_Msk (0xffffUL) /*!< AHB_DMA_TCL (Bitfield-Mask: 0xffff) */
+/* ================================================== AHB_DMA_VERSION_REG ================================================== */
+#define DW_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Pos (0UL) /*!< AHB_DMA_VERSION (Bit 0) */
+#define DW_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Msk (0xffffffffUL) /*!< AHB_DMA_VERSION (Bitfield-Mask: 0xffffffff) */
+/* =================================================== AHB_DMA_WTEN_REG ==================================================== */
+#define DW_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Pos (0UL) /*!< AHB_DMA_WTEN (Bit 0) */
+#define DW_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Msk (0x1UL) /*!< AHB_DMA_WTEN (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPADC ================ */
+/* =========================================================================================================================== */
+
+/* ================================================= GP_ADC_CLEAR_INT_REG ================================================== */
+#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Pos (0UL) /*!< GP_ADC_CLR_INT (Bit 0) */
+#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Msk (0xffffUL) /*!< GP_ADC_CLR_INT (Bitfield-Mask: 0xffff) */
+/* =================================================== GP_ADC_CTRL2_REG ==================================================== */
+#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Pos (12UL) /*!< GP_ADC_STORE_DEL (Bit 12) */
+#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Msk (0xf000UL) /*!< GP_ADC_STORE_DEL (Bitfield-Mask: 0x0f) */
+#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Pos (8UL) /*!< GP_ADC_SMPL_TIME (Bit 8) */
+#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Msk (0xf00UL) /*!< GP_ADC_SMPL_TIME (Bitfield-Mask: 0x0f) */
+#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Pos (5UL) /*!< GP_ADC_CONV_NRS (Bit 5) */
+#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Msk (0xe0UL) /*!< GP_ADC_CONV_NRS (Bitfield-Mask: 0x07) */
+#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Pos (3UL) /*!< GP_ADC_DMA_EN (Bit 3) */
+#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Msk (0x8UL) /*!< GP_ADC_DMA_EN (Bitfield-Mask: 0x01) */
+#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Pos (2UL) /*!< GP_ADC_I20U (Bit 2) */
+#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Msk (0x4UL) /*!< GP_ADC_I20U (Bitfield-Mask: 0x01) */
+#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Pos (1UL) /*!< GP_ADC_IDYN (Bit 1) */
+#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Msk (0x2UL) /*!< GP_ADC_IDYN (Bitfield-Mask: 0x01) */
+#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Pos (0UL) /*!< GP_ADC_ATTN3X (Bit 0) */
+#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Msk (0x1UL) /*!< GP_ADC_ATTN3X (Bitfield-Mask: 0x01) */
+/* =================================================== GP_ADC_CTRL3_REG ==================================================== */
+#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Pos (8UL) /*!< GP_ADC_INTERVAL (Bit 8) */
+#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Msk (0xff00UL) /*!< GP_ADC_INTERVAL (Bitfield-Mask: 0xff) */
+#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Pos (0UL) /*!< GP_ADC_EN_DEL (Bit 0) */
+#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Msk (0xffUL) /*!< GP_ADC_EN_DEL (Bitfield-Mask: 0xff) */
+/* ==================================================== GP_ADC_CTRL_REG ==================================================== */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_DIFF_TEMP_EN_Pos (18UL) /*!< GP_ADC_DIFF_TEMP_EN (Bit 18) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_DIFF_TEMP_EN_Msk (0x40000UL) /*!< GP_ADC_DIFF_TEMP_EN (Bitfield-Mask: 0x01) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_DIFF_TEMP_SEL_Pos (16UL) /*!< GP_ADC_DIFF_TEMP_SEL (Bit 16) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_DIFF_TEMP_SEL_Msk (0x30000UL) /*!< GP_ADC_DIFF_TEMP_SEL (Bitfield-Mask: 0x03) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Pos (15UL) /*!< GP_ADC_LDO_ZERO (Bit 15) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Msk (0x8000UL) /*!< GP_ADC_LDO_ZERO (Bitfield-Mask: 0x01) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Pos (14UL) /*!< GP_ADC_CHOP (Bit 14) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Msk (0x4000UL) /*!< GP_ADC_CHOP (Bitfield-Mask: 0x01) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Pos (13UL) /*!< GP_ADC_SIGN (Bit 13) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Msk (0x2000UL) /*!< GP_ADC_SIGN (Bitfield-Mask: 0x01) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Pos (8UL) /*!< GP_ADC_SEL (Bit 8) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Msk (0x1f00UL) /*!< GP_ADC_SEL (Bitfield-Mask: 0x1f) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Pos (7UL) /*!< GP_ADC_MUTE (Bit 7) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Msk (0x80UL) /*!< GP_ADC_MUTE (Bitfield-Mask: 0x01) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Pos (6UL) /*!< GP_ADC_SE (Bit 6) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Msk (0x40UL) /*!< GP_ADC_SE (Bitfield-Mask: 0x01) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Pos (5UL) /*!< GP_ADC_MINT (Bit 5) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Msk (0x20UL) /*!< GP_ADC_MINT (Bitfield-Mask: 0x01) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Pos (4UL) /*!< GP_ADC_INT (Bit 4) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Msk (0x10UL) /*!< GP_ADC_INT (Bitfield-Mask: 0x01) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Pos (3UL) /*!< GP_ADC_CLK_SEL (Bit 3) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Msk (0x8UL) /*!< GP_ADC_CLK_SEL (Bitfield-Mask: 0x01) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Pos (2UL) /*!< GP_ADC_CONT (Bit 2) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Msk (0x4UL) /*!< GP_ADC_CONT (Bitfield-Mask: 0x01) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Pos (1UL) /*!< GP_ADC_START (Bit 1) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Msk (0x2UL) /*!< GP_ADC_START (Bitfield-Mask: 0x01) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Pos (0UL) /*!< GP_ADC_EN (Bit 0) */
+#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Msk (0x1UL) /*!< GP_ADC_EN (Bitfield-Mask: 0x01) */
+/* ==================================================== GP_ADC_OFFN_REG ==================================================== */
+#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Pos (0UL) /*!< GP_ADC_OFFN (Bit 0) */
+#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Msk (0x3ffUL) /*!< GP_ADC_OFFN (Bitfield-Mask: 0x3ff) */
+/* ==================================================== GP_ADC_OFFP_REG ==================================================== */
+#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Pos (0UL) /*!< GP_ADC_OFFP (Bit 0) */
+#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Msk (0x3ffUL) /*!< GP_ADC_OFFP (Bitfield-Mask: 0x3ff) */
+/* =================================================== GP_ADC_RESULT_REG =================================================== */
+#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Pos (0UL) /*!< GP_ADC_VAL (Bit 0) */
+#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Msk (0xffffUL) /*!< GP_ADC_VAL (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPIO ================ */
+/* =========================================================================================================================== */
+
+/* =================================================== GPIO_CLK_SEL_REG ==================================================== */
+#define GPIO_GPIO_CLK_SEL_REG_DIVN_OUTPUT_EN_Pos (9UL) /*!< DIVN_OUTPUT_EN (Bit 9) */
+#define GPIO_GPIO_CLK_SEL_REG_DIVN_OUTPUT_EN_Msk (0x200UL) /*!< DIVN_OUTPUT_EN (Bitfield-Mask: 0x01) */
+#define GPIO_GPIO_CLK_SEL_REG_RC32M_OUTPUT_EN_Pos (8UL) /*!< RC32M_OUTPUT_EN (Bit 8) */
+#define GPIO_GPIO_CLK_SEL_REG_RC32M_OUTPUT_EN_Msk (0x100UL) /*!< RC32M_OUTPUT_EN (Bitfield-Mask: 0x01) */
+#define GPIO_GPIO_CLK_SEL_REG_XTAL32M_OUTPUT_EN_Pos (7UL) /*!< XTAL32M_OUTPUT_EN (Bit 7) */
+#define GPIO_GPIO_CLK_SEL_REG_XTAL32M_OUTPUT_EN_Msk (0x80UL) /*!< XTAL32M_OUTPUT_EN (Bitfield-Mask: 0x01) */
+#define GPIO_GPIO_CLK_SEL_REG_RCX_OUTPUT_EN_Pos (6UL) /*!< RCX_OUTPUT_EN (Bit 6) */
+#define GPIO_GPIO_CLK_SEL_REG_RCX_OUTPUT_EN_Msk (0x40UL) /*!< RCX_OUTPUT_EN (Bitfield-Mask: 0x01) */
+#define GPIO_GPIO_CLK_SEL_REG_RC32K_OUTPUT_EN_Pos (5UL) /*!< RC32K_OUTPUT_EN (Bit 5) */
+#define GPIO_GPIO_CLK_SEL_REG_RC32K_OUTPUT_EN_Msk (0x20UL) /*!< RC32K_OUTPUT_EN (Bitfield-Mask: 0x01) */
+#define GPIO_GPIO_CLK_SEL_REG_XTAL32K_OUTPUT_EN_Pos (4UL) /*!< XTAL32K_OUTPUT_EN (Bit 4) */
+#define GPIO_GPIO_CLK_SEL_REG_XTAL32K_OUTPUT_EN_Msk (0x10UL) /*!< XTAL32K_OUTPUT_EN (Bitfield-Mask: 0x01) */
+#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Pos (3UL) /*!< FUNC_CLOCK_EN (Bit 3) */
+#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Msk (0x8UL) /*!< FUNC_CLOCK_EN (Bitfield-Mask: 0x01) */
+#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Pos (0UL) /*!< FUNC_CLOCK_SEL (Bit 0) */
+#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Msk (0x7UL) /*!< FUNC_CLOCK_SEL (Bitfield-Mask: 0x07) */
+/* ==================================================== P0_00_MODE_REG ===================================================== */
+#define GPIO_P0_00_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_00_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_00_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_00_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_00_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_00_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_01_MODE_REG ===================================================== */
+#define GPIO_P0_01_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_01_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_01_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_01_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_01_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_01_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_02_MODE_REG ===================================================== */
+#define GPIO_P0_02_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_02_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_02_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_02_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_02_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_02_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_03_MODE_REG ===================================================== */
+#define GPIO_P0_03_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_03_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_03_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_03_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_03_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_03_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_04_MODE_REG ===================================================== */
+#define GPIO_P0_04_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_04_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_04_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_04_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_04_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_04_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_05_MODE_REG ===================================================== */
+#define GPIO_P0_05_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_05_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_05_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_05_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_05_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_05_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_06_MODE_REG ===================================================== */
+#define GPIO_P0_06_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_06_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_06_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_06_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_06_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_06_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_07_MODE_REG ===================================================== */
+#define GPIO_P0_07_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_07_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_07_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_07_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_07_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_07_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_08_MODE_REG ===================================================== */
+#define GPIO_P0_08_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_08_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_08_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_08_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_08_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_08_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_09_MODE_REG ===================================================== */
+#define GPIO_P0_09_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_09_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_09_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_09_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_09_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_09_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_10_MODE_REG ===================================================== */
+#define GPIO_P0_10_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_10_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_10_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_10_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_10_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_10_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_11_MODE_REG ===================================================== */
+#define GPIO_P0_11_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_11_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_11_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_11_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_11_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_11_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_12_MODE_REG ===================================================== */
+#define GPIO_P0_12_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_12_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_12_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_12_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_12_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_12_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_13_MODE_REG ===================================================== */
+#define GPIO_P0_13_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_13_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_13_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_13_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_13_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_13_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_14_MODE_REG ===================================================== */
+#define GPIO_P0_14_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_14_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_14_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_14_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_14_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_14_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_15_MODE_REG ===================================================== */
+#define GPIO_P0_15_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_15_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_15_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_15_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_15_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_15_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_16_MODE_REG ===================================================== */
+#define GPIO_P0_16_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_16_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_16_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_16_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_16_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_16_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_17_MODE_REG ===================================================== */
+#define GPIO_P0_17_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_17_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_17_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_17_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_17_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_17_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_18_MODE_REG ===================================================== */
+#define GPIO_P0_18_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_18_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_18_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_18_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_18_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_18_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_19_MODE_REG ===================================================== */
+#define GPIO_P0_19_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_19_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_19_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_19_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_19_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_19_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_20_MODE_REG ===================================================== */
+#define GPIO_P0_20_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_20_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_20_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_20_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_20_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_20_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_21_MODE_REG ===================================================== */
+#define GPIO_P0_21_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_21_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_21_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_21_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_21_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_21_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_22_MODE_REG ===================================================== */
+#define GPIO_P0_22_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_22_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_22_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_22_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_22_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_22_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_23_MODE_REG ===================================================== */
+#define GPIO_P0_23_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_23_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_23_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_23_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_23_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_23_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_24_MODE_REG ===================================================== */
+#define GPIO_P0_24_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_24_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_24_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_24_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_24_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_24_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_25_MODE_REG ===================================================== */
+#define GPIO_P0_25_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_25_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_25_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_25_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_25_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_25_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_26_MODE_REG ===================================================== */
+#define GPIO_P0_26_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_26_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_26_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_26_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_26_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_26_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_27_MODE_REG ===================================================== */
+#define GPIO_P0_27_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_27_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_27_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_27_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_27_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_27_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_28_MODE_REG ===================================================== */
+#define GPIO_P0_28_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_28_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_28_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_28_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_28_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_28_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_29_MODE_REG ===================================================== */
+#define GPIO_P0_29_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_29_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_29_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_29_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_29_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_29_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_30_MODE_REG ===================================================== */
+#define GPIO_P0_30_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_30_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_30_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_30_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_30_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_30_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P0_31_MODE_REG ===================================================== */
+#define GPIO_P0_31_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P0_31_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P0_31_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P0_31_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P0_31_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P0_31_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ====================================================== P0_DATA_REG ====================================================== */
+#define GPIO_P0_DATA_REG_P0_DATA_Pos (0UL) /*!< P0_DATA (Bit 0) */
+#define GPIO_P0_DATA_REG_P0_DATA_Msk (0xffffffffUL) /*!< P0_DATA (Bitfield-Mask: 0xffffffff) */
+/* ================================================== P0_PADPWR_CTRL_REG =================================================== */
+#define GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Pos (6UL) /*!< P0_OUT_CTRL (Bit 6) */
+#define GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Msk (0xffffffc0UL) /*!< P0_OUT_CTRL (Bitfield-Mask: 0x3ffffff) */
+/* =================================================== P0_RESET_DATA_REG =================================================== */
+#define GPIO_P0_RESET_DATA_REG_P0_RESET_Pos (0UL) /*!< P0_RESET (Bit 0) */
+#define GPIO_P0_RESET_DATA_REG_P0_RESET_Msk (0xffffffffUL) /*!< P0_RESET (Bitfield-Mask: 0xffffffff) */
+/* ==================================================== P0_SET_DATA_REG ==================================================== */
+#define GPIO_P0_SET_DATA_REG_P0_SET_Pos (0UL) /*!< P0_SET (Bit 0) */
+#define GPIO_P0_SET_DATA_REG_P0_SET_Msk (0xffffffffUL) /*!< P0_SET (Bitfield-Mask: 0xffffffff) */
+/* ==================================================== P1_00_MODE_REG ===================================================== */
+#define GPIO_P1_00_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_00_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_00_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_00_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_00_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_00_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_01_MODE_REG ===================================================== */
+#define GPIO_P1_01_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_01_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_01_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_01_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_01_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_01_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_02_MODE_REG ===================================================== */
+#define GPIO_P1_02_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_02_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_02_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_02_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_02_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_02_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_03_MODE_REG ===================================================== */
+#define GPIO_P1_03_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_03_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_03_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_03_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_03_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_03_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_04_MODE_REG ===================================================== */
+#define GPIO_P1_04_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_04_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_04_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_04_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_04_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_04_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_05_MODE_REG ===================================================== */
+#define GPIO_P1_05_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_05_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_05_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_05_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_05_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_05_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_06_MODE_REG ===================================================== */
+#define GPIO_P1_06_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_06_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_06_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_06_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_06_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_06_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_07_MODE_REG ===================================================== */
+#define GPIO_P1_07_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_07_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_07_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_07_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_07_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_07_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_08_MODE_REG ===================================================== */
+#define GPIO_P1_08_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_08_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_08_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_08_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_08_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_08_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_09_MODE_REG ===================================================== */
+#define GPIO_P1_09_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_09_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_09_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_09_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_09_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_09_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_10_MODE_REG ===================================================== */
+#define GPIO_P1_10_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_10_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_10_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_10_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_10_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_10_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_11_MODE_REG ===================================================== */
+#define GPIO_P1_11_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_11_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_11_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_11_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_11_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_11_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_12_MODE_REG ===================================================== */
+#define GPIO_P1_12_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_12_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_12_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_12_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_12_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_12_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_13_MODE_REG ===================================================== */
+#define GPIO_P1_13_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_13_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_13_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_13_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_13_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_13_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_14_MODE_REG ===================================================== */
+#define GPIO_P1_14_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_14_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_14_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_14_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_14_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_14_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_15_MODE_REG ===================================================== */
+#define GPIO_P1_15_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_15_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_15_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_15_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_15_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_15_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_16_MODE_REG ===================================================== */
+#define GPIO_P1_16_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_16_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_16_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_16_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_16_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_16_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_17_MODE_REG ===================================================== */
+#define GPIO_P1_17_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_17_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_17_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_17_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_17_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_17_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_18_MODE_REG ===================================================== */
+#define GPIO_P1_18_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_18_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_18_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_18_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_18_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_18_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_19_MODE_REG ===================================================== */
+#define GPIO_P1_19_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_19_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_19_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_19_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_19_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_19_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_20_MODE_REG ===================================================== */
+#define GPIO_P1_20_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_20_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_20_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_20_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_20_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_20_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_21_MODE_REG ===================================================== */
+#define GPIO_P1_21_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_21_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_21_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_21_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_21_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_21_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ==================================================== P1_22_MODE_REG ===================================================== */
+#define GPIO_P1_22_MODE_REG_PPOD_Pos (10UL) /*!< PPOD (Bit 10) */
+#define GPIO_P1_22_MODE_REG_PPOD_Msk (0x400UL) /*!< PPOD (Bitfield-Mask: 0x01) */
+#define GPIO_P1_22_MODE_REG_PUPD_Pos (8UL) /*!< PUPD (Bit 8) */
+#define GPIO_P1_22_MODE_REG_PUPD_Msk (0x300UL) /*!< PUPD (Bitfield-Mask: 0x03) */
+#define GPIO_P1_22_MODE_REG_PID_Pos (0UL) /*!< PID (Bit 0) */
+#define GPIO_P1_22_MODE_REG_PID_Msk (0x3fUL) /*!< PID (Bitfield-Mask: 0x3f) */
+/* ====================================================== P1_DATA_REG ====================================================== */
+#define GPIO_P1_DATA_REG_P1_DATA_Pos (0UL) /*!< P1_DATA (Bit 0) */
+#define GPIO_P1_DATA_REG_P1_DATA_Msk (0x7fffffUL) /*!< P1_DATA (Bitfield-Mask: 0x7fffff) */
+/* ================================================== P1_PADPWR_CTRL_REG =================================================== */
+#define GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Pos (0UL) /*!< P1_OUT_CTRL (Bit 0) */
+#define GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Msk (0x7fffffUL) /*!< P1_OUT_CTRL (Bitfield-Mask: 0x7fffff) */
+/* =================================================== P1_RESET_DATA_REG =================================================== */
+#define GPIO_P1_RESET_DATA_REG_P1_RESET_Pos (0UL) /*!< P1_RESET (Bit 0) */
+#define GPIO_P1_RESET_DATA_REG_P1_RESET_Msk (0x7fffffUL) /*!< P1_RESET (Bitfield-Mask: 0x7fffff) */
+/* ==================================================== P1_SET_DATA_REG ==================================================== */
+#define GPIO_P1_SET_DATA_REG_P1_SET_Pos (0UL) /*!< P1_SET (Bit 0) */
+#define GPIO_P1_SET_DATA_REG_P1_SET_Msk (0x7fffffUL) /*!< P1_SET (Bitfield-Mask: 0x7fffff) */
+/* =================================================== PAD_WEAK_CTRL_REG =================================================== */
+#define GPIO_PAD_WEAK_CTRL_REG_P1_09_LOWDRV_Pos (12UL) /*!< P1_09_LOWDRV (Bit 12) */
+#define GPIO_PAD_WEAK_CTRL_REG_P1_09_LOWDRV_Msk (0x1000UL) /*!< P1_09_LOWDRV (Bitfield-Mask: 0x01) */
+#define GPIO_PAD_WEAK_CTRL_REG_P1_06_LOWDRV_Pos (11UL) /*!< P1_06_LOWDRV (Bit 11) */
+#define GPIO_PAD_WEAK_CTRL_REG_P1_06_LOWDRV_Msk (0x800UL) /*!< P1_06_LOWDRV (Bitfield-Mask: 0x01) */
+#define GPIO_PAD_WEAK_CTRL_REG_P1_02_LOWDRV_Pos (10UL) /*!< P1_02_LOWDRV (Bit 10) */
+#define GPIO_PAD_WEAK_CTRL_REG_P1_02_LOWDRV_Msk (0x400UL) /*!< P1_02_LOWDRV (Bitfield-Mask: 0x01) */
+#define GPIO_PAD_WEAK_CTRL_REG_P1_01_LOWDRV_Pos (9UL) /*!< P1_01_LOWDRV (Bit 9) */
+#define GPIO_PAD_WEAK_CTRL_REG_P1_01_LOWDRV_Msk (0x200UL) /*!< P1_01_LOWDRV (Bitfield-Mask: 0x01) */
+#define GPIO_PAD_WEAK_CTRL_REG_P1_00_LOWDRV_Pos (8UL) /*!< P1_00_LOWDRV (Bit 8) */
+#define GPIO_PAD_WEAK_CTRL_REG_P1_00_LOWDRV_Msk (0x100UL) /*!< P1_00_LOWDRV (Bitfield-Mask: 0x01) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_27_LOWDRV_Pos (7UL) /*!< P0_27_LOWDRV (Bit 7) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_27_LOWDRV_Msk (0x80UL) /*!< P0_27_LOWDRV (Bitfield-Mask: 0x01) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_26_LOWDRV_Pos (6UL) /*!< P0_26_LOWDRV (Bit 6) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_26_LOWDRV_Msk (0x40UL) /*!< P0_26_LOWDRV (Bitfield-Mask: 0x01) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_25_LOWDRV_Pos (5UL) /*!< P0_25_LOWDRV (Bit 5) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_25_LOWDRV_Msk (0x20UL) /*!< P0_25_LOWDRV (Bitfield-Mask: 0x01) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_18_LOWDRV_Pos (4UL) /*!< P0_18_LOWDRV (Bit 4) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_18_LOWDRV_Msk (0x10UL) /*!< P0_18_LOWDRV (Bitfield-Mask: 0x01) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_17_LOWDRV_Pos (3UL) /*!< P0_17_LOWDRV (Bit 3) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_17_LOWDRV_Msk (0x8UL) /*!< P0_17_LOWDRV (Bitfield-Mask: 0x01) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_16_LOWDRV_Pos (2UL) /*!< P0_16_LOWDRV (Bit 2) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_16_LOWDRV_Msk (0x4UL) /*!< P0_16_LOWDRV (Bitfield-Mask: 0x01) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_07_LOWDRV_Pos (1UL) /*!< P0_07_LOWDRV (Bit 1) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_07_LOWDRV_Msk (0x2UL) /*!< P0_07_LOWDRV (Bitfield-Mask: 0x01) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_06_LOWDRV_Pos (0UL) /*!< P0_06_LOWDRV (Bit 0) */
+#define GPIO_PAD_WEAK_CTRL_REG_P0_06_LOWDRV_Msk (0x1UL) /*!< P0_06_LOWDRV (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPREG ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================= DEBUG_REG ======================================================= */
+#define GPREG_DEBUG_REG_CROSS_CPU_HALT_SENSITIVITY_Pos (8UL) /*!< CROSS_CPU_HALT_SENSITIVITY (Bit 8) */
+#define GPREG_DEBUG_REG_CROSS_CPU_HALT_SENSITIVITY_Msk (0x100UL) /*!< CROSS_CPU_HALT_SENSITIVITY (Bitfield-Mask: 0x01) */
+#define GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Pos (7UL) /*!< SYS_CPUWAIT_ON_JTAG (Bit 7) */
+#define GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Msk (0x80UL) /*!< SYS_CPUWAIT_ON_JTAG (Bitfield-Mask: 0x01) */
+#define GPREG_DEBUG_REG_SYS_CPUWAIT_Pos (6UL) /*!< SYS_CPUWAIT (Bit 6) */
+#define GPREG_DEBUG_REG_SYS_CPUWAIT_Msk (0x40UL) /*!< SYS_CPUWAIT (Bitfield-Mask: 0x01) */
+#define GPREG_DEBUG_REG_CMAC_CPU_IS_HALTED_Pos (5UL) /*!< CMAC_CPU_IS_HALTED (Bit 5) */
+#define GPREG_DEBUG_REG_CMAC_CPU_IS_HALTED_Msk (0x20UL) /*!< CMAC_CPU_IS_HALTED (Bitfield-Mask: 0x01) */
+#define GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Pos (4UL) /*!< SYS_CPU_IS_HALTED (Bit 4) */
+#define GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Msk (0x10UL) /*!< SYS_CPU_IS_HALTED (Bitfield-Mask: 0x01) */
+#define GPREG_DEBUG_REG_HALT_CMAC_SYS_CPU_EN_Pos (3UL) /*!< HALT_CMAC_SYS_CPU_EN (Bit 3) */
+#define GPREG_DEBUG_REG_HALT_CMAC_SYS_CPU_EN_Msk (0x8UL) /*!< HALT_CMAC_SYS_CPU_EN (Bitfield-Mask: 0x01) */
+#define GPREG_DEBUG_REG_HALT_SYS_CMAC_CPU_EN_Pos (2UL) /*!< HALT_SYS_CMAC_CPU_EN (Bit 2) */
+#define GPREG_DEBUG_REG_HALT_SYS_CMAC_CPU_EN_Msk (0x4UL) /*!< HALT_SYS_CMAC_CPU_EN (Bitfield-Mask: 0x01) */
+#define GPREG_DEBUG_REG_CMAC_CPU_FREEZE_EN_Pos (1UL) /*!< CMAC_CPU_FREEZE_EN (Bit 1) */
+#define GPREG_DEBUG_REG_CMAC_CPU_FREEZE_EN_Msk (0x2UL) /*!< CMAC_CPU_FREEZE_EN (Bitfield-Mask: 0x01) */
+#define GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Pos (0UL) /*!< SYS_CPU_FREEZE_EN (Bit 0) */
+#define GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Msk (0x1UL) /*!< SYS_CPU_FREEZE_EN (Bitfield-Mask: 0x01) */
+/* ==================================================== GP_CONTROL_REG ===================================================== */
+#define GPREG_GP_CONTROL_REG_CMAC_H2H_BRIDGE_BYPASS_Pos (1UL) /*!< CMAC_H2H_BRIDGE_BYPASS (Bit 1) */
+#define GPREG_GP_CONTROL_REG_CMAC_H2H_BRIDGE_BYPASS_Msk (0x2UL) /*!< CMAC_H2H_BRIDGE_BYPASS (Bitfield-Mask: 0x01) */
+/* ===================================================== GP_STATUS_REG ===================================================== */
+#define GPREG_GP_STATUS_REG_CAL_PHASE_Pos (0UL) /*!< CAL_PHASE (Bit 0) */
+#define GPREG_GP_STATUS_REG_CAL_PHASE_Msk (0x1UL) /*!< CAL_PHASE (Bitfield-Mask: 0x01) */
+/* =================================================== RESET_FREEZE_REG ==================================================== */
+#define GPREG_RESET_FREEZE_REG_FRZ_CMAC_WDOG_Pos (10UL) /*!< FRZ_CMAC_WDOG (Bit 10) */
+#define GPREG_RESET_FREEZE_REG_FRZ_CMAC_WDOG_Msk (0x400UL) /*!< FRZ_CMAC_WDOG (Bitfield-Mask: 0x01) */
+#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Pos (9UL) /*!< FRZ_SWTIM4 (Bit 9) */
+#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Msk (0x200UL) /*!< FRZ_SWTIM4 (Bitfield-Mask: 0x01) */
+#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Pos (8UL) /*!< FRZ_SWTIM3 (Bit 8) */
+#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Msk (0x100UL) /*!< FRZ_SWTIM3 (Bitfield-Mask: 0x01) */
+#define GPREG_RESET_FREEZE_REG_FRZ_PWMLED_Pos (7UL) /*!< FRZ_PWMLED (Bit 7) */
+#define GPREG_RESET_FREEZE_REG_FRZ_PWMLED_Msk (0x80UL) /*!< FRZ_PWMLED (Bitfield-Mask: 0x01) */
+#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Pos (6UL) /*!< FRZ_SWTIM2 (Bit 6) */
+#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Msk (0x40UL) /*!< FRZ_SWTIM2 (Bitfield-Mask: 0x01) */
+#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Pos (5UL) /*!< FRZ_DMA (Bit 5) */
+#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Msk (0x20UL) /*!< FRZ_DMA (Bitfield-Mask: 0x01) */
+#define GPREG_RESET_FREEZE_REG_FRZ_USB_Pos (4UL) /*!< FRZ_USB (Bit 4) */
+#define GPREG_RESET_FREEZE_REG_FRZ_USB_Msk (0x10UL) /*!< FRZ_USB (Bitfield-Mask: 0x01) */
+#define GPREG_RESET_FREEZE_REG_FRZ_SYS_WDOG_Pos (3UL) /*!< FRZ_SYS_WDOG (Bit 3) */
+#define GPREG_RESET_FREEZE_REG_FRZ_SYS_WDOG_Msk (0x8UL) /*!< FRZ_SYS_WDOG (Bitfield-Mask: 0x01) */
+#define GPREG_RESET_FREEZE_REG_FRZ_RESERVED_Pos (2UL) /*!< FRZ_RESERVED (Bit 2) */
+#define GPREG_RESET_FREEZE_REG_FRZ_RESERVED_Msk (0x4UL) /*!< FRZ_RESERVED (Bitfield-Mask: 0x01) */
+#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Pos (1UL) /*!< FRZ_SWTIM (Bit 1) */
+#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Msk (0x2UL) /*!< FRZ_SWTIM (Bitfield-Mask: 0x01) */
+#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL) /*!< FRZ_WKUPTIM (Bit 0) */
+#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL) /*!< FRZ_WKUPTIM (Bitfield-Mask: 0x01) */
+/* ==================================================== SET_FREEZE_REG ===================================================== */
+#define GPREG_SET_FREEZE_REG_FRZ_CMAC_WDOG_Pos (10UL) /*!< FRZ_CMAC_WDOG (Bit 10) */
+#define GPREG_SET_FREEZE_REG_FRZ_CMAC_WDOG_Msk (0x400UL) /*!< FRZ_CMAC_WDOG (Bitfield-Mask: 0x01) */
+#define GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Pos (9UL) /*!< FRZ_SWTIM4 (Bit 9) */
+#define GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Msk (0x200UL) /*!< FRZ_SWTIM4 (Bitfield-Mask: 0x01) */
+#define GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Pos (8UL) /*!< FRZ_SWTIM3 (Bit 8) */
+#define GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Msk (0x100UL) /*!< FRZ_SWTIM3 (Bitfield-Mask: 0x01) */
+#define GPREG_SET_FREEZE_REG_FRZ_PWMLED_Pos (7UL) /*!< FRZ_PWMLED (Bit 7) */
+#define GPREG_SET_FREEZE_REG_FRZ_PWMLED_Msk (0x80UL) /*!< FRZ_PWMLED (Bitfield-Mask: 0x01) */
+#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Pos (6UL) /*!< FRZ_SWTIM2 (Bit 6) */
+#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Msk (0x40UL) /*!< FRZ_SWTIM2 (Bitfield-Mask: 0x01) */
+#define GPREG_SET_FREEZE_REG_FRZ_DMA_Pos (5UL) /*!< FRZ_DMA (Bit 5) */
+#define GPREG_SET_FREEZE_REG_FRZ_DMA_Msk (0x20UL) /*!< FRZ_DMA (Bitfield-Mask: 0x01) */
+#define GPREG_SET_FREEZE_REG_FRZ_USB_Pos (4UL) /*!< FRZ_USB (Bit 4) */
+#define GPREG_SET_FREEZE_REG_FRZ_USB_Msk (0x10UL) /*!< FRZ_USB (Bitfield-Mask: 0x01) */
+#define GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Pos (3UL) /*!< FRZ_SYS_WDOG (Bit 3) */
+#define GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk (0x8UL) /*!< FRZ_SYS_WDOG (Bitfield-Mask: 0x01) */
+#define GPREG_SET_FREEZE_REG_FRZ_RESERVED_Pos (2UL) /*!< FRZ_RESERVED (Bit 2) */
+#define GPREG_SET_FREEZE_REG_FRZ_RESERVED_Msk (0x4UL) /*!< FRZ_RESERVED (Bitfield-Mask: 0x01) */
+#define GPREG_SET_FREEZE_REG_FRZ_SWTIM_Pos (1UL) /*!< FRZ_SWTIM (Bit 1) */
+#define GPREG_SET_FREEZE_REG_FRZ_SWTIM_Msk (0x2UL) /*!< FRZ_SWTIM (Bitfield-Mask: 0x01) */
+#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL) /*!< FRZ_WKUPTIM (Bit 0) */
+#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL) /*!< FRZ_WKUPTIM (Bitfield-Mask: 0x01) */
+/* ====================================================== USBPAD_REG ======================================================= */
+#define GPREG_USBPAD_REG_USBPHY_FORCE_SW2_ON_Pos (2UL) /*!< USBPHY_FORCE_SW2_ON (Bit 2) */
+#define GPREG_USBPAD_REG_USBPHY_FORCE_SW2_ON_Msk (0x4UL) /*!< USBPHY_FORCE_SW2_ON (Bitfield-Mask: 0x01) */
+#define GPREG_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Pos (1UL) /*!< USBPHY_FORCE_SW1_OFF (Bit 1) */
+#define GPREG_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Msk (0x2UL) /*!< USBPHY_FORCE_SW1_OFF (Bitfield-Mask: 0x01) */
+#define GPREG_USBPAD_REG_USBPAD_EN_Pos (0UL) /*!< USBPAD_EN (Bit 0) */
+#define GPREG_USBPAD_REG_USBPAD_EN_Msk (0x1UL) /*!< USBPAD_EN (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ I2C ================ */
+/* =========================================================================================================================== */
+
+/* =============================================== I2C_ACK_GENERAL_CALL_REG ================================================ */
+#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL) /*!< ACK_GEN_CALL (Bit 0) */
+#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL) /*!< ACK_GEN_CALL (Bitfield-Mask: 0x01) */
+/* ================================================= I2C_CLR_ACTIVITY_REG ================================================== */
+#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL) /*!< CLR_ACTIVITY (Bit 0) */
+#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL) /*!< CLR_ACTIVITY (Bitfield-Mask: 0x01) */
+/* ================================================= I2C_CLR_GEN_CALL_REG ================================================== */
+#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL) /*!< CLR_GEN_CALL (Bit 0) */
+#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL) /*!< CLR_GEN_CALL (Bitfield-Mask: 0x01) */
+/* =================================================== I2C_CLR_INTR_REG ==================================================== */
+#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Pos (0UL) /*!< CLR_INTR (Bit 0) */
+#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Msk (0x1UL) /*!< CLR_INTR (Bitfield-Mask: 0x01) */
+/* ================================================== I2C_CLR_RD_REQ_REG =================================================== */
+#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL) /*!< CLR_RD_REQ (Bit 0) */
+#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL) /*!< CLR_RD_REQ (Bitfield-Mask: 0x01) */
+/* ================================================== I2C_CLR_RX_DONE_REG ================================================== */
+#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL) /*!< CLR_RX_DONE (Bit 0) */
+#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL) /*!< CLR_RX_DONE (Bitfield-Mask: 0x01) */
+/* ================================================== I2C_CLR_RX_OVER_REG ================================================== */
+#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL) /*!< CLR_RX_OVER (Bit 0) */
+#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL) /*!< CLR_RX_OVER (Bitfield-Mask: 0x01) */
+/* ================================================= I2C_CLR_RX_UNDER_REG ================================================== */
+#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL) /*!< CLR_RX_UNDER (Bit 0) */
+#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL) /*!< CLR_RX_UNDER (Bitfield-Mask: 0x01) */
+/* ================================================= I2C_CLR_START_DET_REG ================================================= */
+#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Pos (0UL) /*!< CLR_START_DET (Bit 0) */
+#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL) /*!< CLR_START_DET (Bitfield-Mask: 0x01) */
+/* ================================================= I2C_CLR_STOP_DET_REG ================================================== */
+#define I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Pos (0UL) /*!< CLR_STOP_DET (Bit 0) */
+#define I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Msk (0x1UL) /*!< CLR_STOP_DET (Bitfield-Mask: 0x01) */
+/* ================================================== I2C_CLR_TX_ABRT_REG ================================================== */
+#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL) /*!< CLR_TX_ABRT (Bit 0) */
+#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL) /*!< CLR_TX_ABRT (Bitfield-Mask: 0x01) */
+/* ================================================== I2C_CLR_TX_OVER_REG ================================================== */
+#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL) /*!< CLR_TX_OVER (Bit 0) */
+#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL) /*!< CLR_TX_OVER (Bitfield-Mask: 0x01) */
+/* ====================================================== I2C_CON_REG ====================================================== */
+#define I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Pos (10UL) /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bit 10) */
+#define I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Msk (0x400UL) /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bitfield-Mask: 0x01) */
+#define I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Pos (9UL) /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bit 9) */
+#define I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Msk (0x200UL) /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bitfield-Mask: 0x01) */
+#define I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Pos (8UL) /*!< I2C_TX_EMPTY_CTRL (Bit 8) */
+#define I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Msk (0x100UL) /*!< I2C_TX_EMPTY_CTRL (Bitfield-Mask: 0x01) */
+#define I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Pos (7UL) /*!< I2C_STOP_DET_IFADDRESSED (Bit 7) */
+#define I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Msk (0x80UL) /*!< I2C_STOP_DET_IFADDRESSED (Bitfield-Mask: 0x01) */
+#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL) /*!< I2C_SLAVE_DISABLE (Bit 6) */
+#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL) /*!< I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01) */
+#define I2C_I2C_CON_REG_I2C_RESTART_EN_Pos (5UL) /*!< I2C_RESTART_EN (Bit 5) */
+#define I2C_I2C_CON_REG_I2C_RESTART_EN_Msk (0x20UL) /*!< I2C_RESTART_EN (Bitfield-Mask: 0x01) */
+#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL) /*!< I2C_10BITADDR_MASTER (Bit 4) */
+#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL) /*!< I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01) */
+#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL) /*!< I2C_10BITADDR_SLAVE (Bit 3) */
+#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL) /*!< I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01) */
+#define I2C_I2C_CON_REG_I2C_SPEED_Pos (1UL) /*!< I2C_SPEED (Bit 1) */
+#define I2C_I2C_CON_REG_I2C_SPEED_Msk (0x6UL) /*!< I2C_SPEED (Bitfield-Mask: 0x03) */
+#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Pos (0UL) /*!< I2C_MASTER_MODE (Bit 0) */
+#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk (0x1UL) /*!< I2C_MASTER_MODE (Bitfield-Mask: 0x01) */
+/* =================================================== I2C_DATA_CMD_REG ==================================================== */
+#define I2C_I2C_DATA_CMD_REG_I2C_RESTART_Pos (10UL) /*!< I2C_RESTART (Bit 10) */
+#define I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk (0x400UL) /*!< I2C_RESTART (Bitfield-Mask: 0x01) */
+#define I2C_I2C_DATA_CMD_REG_I2C_STOP_Pos (9UL) /*!< I2C_STOP (Bit 9) */
+#define I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk (0x200UL) /*!< I2C_STOP (Bitfield-Mask: 0x01) */
+#define I2C_I2C_DATA_CMD_REG_I2C_CMD_Pos (8UL) /*!< I2C_CMD (Bit 8) */
+#define I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk (0x100UL) /*!< I2C_CMD (Bitfield-Mask: 0x01) */
+#define I2C_I2C_DATA_CMD_REG_I2C_DAT_Pos (0UL) /*!< I2C_DAT (Bit 0) */
+#define I2C_I2C_DATA_CMD_REG_I2C_DAT_Msk (0xffUL) /*!< I2C_DAT (Bitfield-Mask: 0xff) */
+/* ==================================================== I2C_DMA_CR_REG ===================================================== */
+#define I2C_I2C_DMA_CR_REG_TDMAE_Pos (1UL) /*!< TDMAE (Bit 1) */
+#define I2C_I2C_DMA_CR_REG_TDMAE_Msk (0x2UL) /*!< TDMAE (Bitfield-Mask: 0x01) */
+#define I2C_I2C_DMA_CR_REG_RDMAE_Pos (0UL) /*!< RDMAE (Bit 0) */
+#define I2C_I2C_DMA_CR_REG_RDMAE_Msk (0x1UL) /*!< RDMAE (Bitfield-Mask: 0x01) */
+/* =================================================== I2C_DMA_RDLR_REG ==================================================== */
+#define I2C_I2C_DMA_RDLR_REG_DMARDL_Pos (0UL) /*!< DMARDL (Bit 0) */
+#define I2C_I2C_DMA_RDLR_REG_DMARDL_Msk (0x1fUL) /*!< DMARDL (Bitfield-Mask: 0x1f) */
+/* =================================================== I2C_DMA_TDLR_REG ==================================================== */
+#define I2C_I2C_DMA_TDLR_REG_DMATDL_Pos (0UL) /*!< DMATDL (Bit 0) */
+#define I2C_I2C_DMA_TDLR_REG_DMATDL_Msk (0x1fUL) /*!< DMATDL (Bitfield-Mask: 0x1f) */
+/* ==================================================== I2C_ENABLE_REG ===================================================== */
+#define I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Pos (2UL) /*!< I2C_TX_CMD_BLOCK (Bit 2) */
+#define I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Msk (0x4UL) /*!< I2C_TX_CMD_BLOCK (Bitfield-Mask: 0x01) */
+#define I2C_I2C_ENABLE_REG_I2C_ABORT_Pos (1UL) /*!< I2C_ABORT (Bit 1) */
+#define I2C_I2C_ENABLE_REG_I2C_ABORT_Msk (0x2UL) /*!< I2C_ABORT (Bitfield-Mask: 0x01) */
+#define I2C_I2C_ENABLE_REG_I2C_EN_Pos (0UL) /*!< I2C_EN (Bit 0) */
+#define I2C_I2C_ENABLE_REG_I2C_EN_Msk (0x1UL) /*!< I2C_EN (Bitfield-Mask: 0x01) */
+/* ================================================= I2C_ENABLE_STATUS_REG ================================================= */
+#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL) /*!< SLV_RX_DATA_LOST (Bit 2) */
+#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL) /*!< SLV_RX_DATA_LOST (Bitfield-Mask: 0x01) */
+#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL) /*!< SLV_DISABLED_WHILE_BUSY (Bit 1) */
+#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL) /*!< SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01) */
+#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Pos (0UL) /*!< IC_EN (Bit 0) */
+#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Msk (0x1UL) /*!< IC_EN (Bitfield-Mask: 0x01) */
+/* ================================================== I2C_FS_SCL_HCNT_REG ================================================== */
+#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL) /*!< IC_FS_SCL_HCNT (Bit 0) */
+#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL) /*!< IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff) */
+/* ================================================== I2C_FS_SCL_LCNT_REG ================================================== */
+#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL) /*!< IC_FS_SCL_LCNT (Bit 0) */
+#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL) /*!< IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff) */
+/* =================================================== I2C_HS_MADDR_REG ==================================================== */
+#define I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Pos (0UL) /*!< I2C_IC_HS_MAR (Bit 0) */
+#define I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Msk (0x7UL) /*!< I2C_IC_HS_MAR (Bitfield-Mask: 0x07) */
+/* ================================================== I2C_HS_SCL_HCNT_REG ================================================== */
+#define I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Pos (0UL) /*!< IC_HS_SCL_HCNT (Bit 0) */
+#define I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Msk (0xffffUL) /*!< IC_HS_SCL_HCNT (Bitfield-Mask: 0xffff) */
+/* ================================================== I2C_HS_SCL_LCNT_REG ================================================== */
+#define I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Pos (0UL) /*!< IC_HS_SCL_LCNT (Bit 0) */
+#define I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Msk (0xffffUL) /*!< IC_HS_SCL_LCNT (Bitfield-Mask: 0xffff) */
+/* ================================================= I2C_IC_FS_SPKLEN_REG ================================================== */
+#define I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Pos (0UL) /*!< I2C_FS_SPKLEN (Bit 0) */
+#define I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Msk (0xffUL) /*!< I2C_FS_SPKLEN (Bitfield-Mask: 0xff) */
+/* ================================================= I2C_IC_HS_SPKLEN_REG ================================================== */
+#define I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Pos (0UL) /*!< I2C_HS_SPKLEN (Bit 0) */
+#define I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Msk (0xffUL) /*!< I2C_HS_SPKLEN (Bitfield-Mask: 0xff) */
+/* =================================================== I2C_INTR_MASK_REG =================================================== */
+#define I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Pos (14UL) /*!< M_SCL_STUCK_AT_LOW (Bit 14) */
+#define I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< M_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Pos (13UL) /*!< M_MASTER_ON_HOLD (Bit 13) */
+#define I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Msk (0x2000UL) /*!< M_MASTER_ON_HOLD (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Pos (12UL) /*!< M_RESTART_DET (Bit 12) */
+#define I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Msk (0x1000UL) /*!< M_RESTART_DET (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Pos (11UL) /*!< M_GEN_CALL (Bit 11) */
+#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Msk (0x800UL) /*!< M_GEN_CALL (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_MASK_REG_M_START_DET_Pos (10UL) /*!< M_START_DET (Bit 10) */
+#define I2C_I2C_INTR_MASK_REG_M_START_DET_Msk (0x400UL) /*!< M_START_DET (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Pos (9UL) /*!< M_STOP_DET (Bit 9) */
+#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Msk (0x200UL) /*!< M_STOP_DET (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Pos (8UL) /*!< M_ACTIVITY (Bit 8) */
+#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Msk (0x100UL) /*!< M_ACTIVITY (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Pos (7UL) /*!< M_RX_DONE (Bit 7) */
+#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Msk (0x80UL) /*!< M_RX_DONE (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Pos (6UL) /*!< M_TX_ABRT (Bit 6) */
+#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Msk (0x40UL) /*!< M_TX_ABRT (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Pos (5UL) /*!< M_RD_REQ (Bit 5) */
+#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Msk (0x20UL) /*!< M_RD_REQ (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Pos (4UL) /*!< M_TX_EMPTY (Bit 4) */
+#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk (0x10UL) /*!< M_TX_EMPTY (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Pos (3UL) /*!< M_TX_OVER (Bit 3) */
+#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Msk (0x8UL) /*!< M_TX_OVER (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Pos (2UL) /*!< M_RX_FULL (Bit 2) */
+#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk (0x4UL) /*!< M_RX_FULL (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Pos (1UL) /*!< M_RX_OVER (Bit 1) */
+#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Msk (0x2UL) /*!< M_RX_OVER (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Pos (0UL) /*!< M_RX_UNDER (Bit 0) */
+#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Msk (0x1UL) /*!< M_RX_UNDER (Bitfield-Mask: 0x01) */
+/* =================================================== I2C_INTR_STAT_REG =================================================== */
+#define I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Pos (14UL) /*!< R_SCL_STUCK_AT_LOW (Bit 14) */
+#define I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< R_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Pos (13UL) /*!< R_MASTER_ON_HOLD (Bit 13) */
+#define I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Msk (0x2000UL) /*!< R_MASTER_ON_HOLD (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Pos (12UL) /*!< R_RESTART_DET (Bit 12) */
+#define I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Msk (0x1000UL) /*!< R_RESTART_DET (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Pos (11UL) /*!< R_GEN_CALL (Bit 11) */
+#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk (0x800UL) /*!< R_GEN_CALL (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_STAT_REG_R_START_DET_Pos (10UL) /*!< R_START_DET (Bit 10) */
+#define I2C_I2C_INTR_STAT_REG_R_START_DET_Msk (0x400UL) /*!< R_START_DET (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Pos (9UL) /*!< R_STOP_DET (Bit 9) */
+#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk (0x200UL) /*!< R_STOP_DET (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Pos (8UL) /*!< R_ACTIVITY (Bit 8) */
+#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk (0x100UL) /*!< R_ACTIVITY (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Pos (7UL) /*!< R_RX_DONE (Bit 7) */
+#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk (0x80UL) /*!< R_RX_DONE (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Pos (6UL) /*!< R_TX_ABRT (Bit 6) */
+#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk (0x40UL) /*!< R_TX_ABRT (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Pos (5UL) /*!< R_RD_REQ (Bit 5) */
+#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk (0x20UL) /*!< R_RD_REQ (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Pos (4UL) /*!< R_TX_EMPTY (Bit 4) */
+#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk (0x10UL) /*!< R_TX_EMPTY (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Pos (3UL) /*!< R_TX_OVER (Bit 3) */
+#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk (0x8UL) /*!< R_TX_OVER (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Pos (2UL) /*!< R_RX_FULL (Bit 2) */
+#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk (0x4UL) /*!< R_RX_FULL (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Pos (1UL) /*!< R_RX_OVER (Bit 1) */
+#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk (0x2UL) /*!< R_RX_OVER (Bitfield-Mask: 0x01) */
+#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Pos (0UL) /*!< R_RX_UNDER (Bit 0) */
+#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk (0x1UL) /*!< R_RX_UNDER (Bitfield-Mask: 0x01) */
+/* ================================================= I2C_RAW_INTR_STAT_REG ================================================= */
+#define I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Pos (14UL) /*!< SCL_STUCK_AT_LOW (Bit 14) */
+#define I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */
+#define I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Pos (13UL) /*!< MASTER_ON_HOLD (Bit 13) */
+#define I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Msk (0x2000UL) /*!< MASTER_ON_HOLD (Bitfield-Mask: 0x01) */
+#define I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Pos (12UL) /*!< RESTART_DET (Bit 12) */
+#define I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Msk (0x1000UL) /*!< RESTART_DET (Bitfield-Mask: 0x01) */
+#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL) /*!< GEN_CALL (Bit 11) */
+#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL) /*!< GEN_CALL (Bitfield-Mask: 0x01) */
+#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Pos (10UL) /*!< START_DET (Bit 10) */
+#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL) /*!< START_DET (Bitfield-Mask: 0x01) */
+#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL) /*!< STOP_DET (Bit 9) */
+#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL) /*!< STOP_DET (Bitfield-Mask: 0x01) */
+#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL) /*!< ACTIVITY (Bit 8) */
+#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL) /*!< ACTIVITY (Bitfield-Mask: 0x01) */
+#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL) /*!< RX_DONE (Bit 7) */
+#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL) /*!< RX_DONE (Bitfield-Mask: 0x01) */
+#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL) /*!< TX_ABRT (Bit 6) */
+#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL) /*!< TX_ABRT (Bitfield-Mask: 0x01) */
+#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Pos (5UL) /*!< RD_REQ (Bit 5) */
+#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Msk (0x20UL) /*!< RD_REQ (Bitfield-Mask: 0x01) */
+#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL) /*!< TX_EMPTY (Bit 4) */
+#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL) /*!< TX_EMPTY (Bitfield-Mask: 0x01) */
+#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL) /*!< TX_OVER (Bit 3) */
+#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL) /*!< TX_OVER (Bitfield-Mask: 0x01) */
+#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL) /*!< RX_FULL (Bit 2) */
+#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL) /*!< RX_FULL (Bitfield-Mask: 0x01) */
+#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL) /*!< RX_OVER (Bit 1) */
+#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL) /*!< RX_OVER (Bitfield-Mask: 0x01) */
+#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL) /*!< RX_UNDER (Bit 0) */
+#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL) /*!< RX_UNDER (Bitfield-Mask: 0x01) */
+/* ===================================================== I2C_RXFLR_REG ===================================================== */
+#define I2C_I2C_RXFLR_REG_RXFLR_Pos (0UL) /*!< RXFLR (Bit 0) */
+#define I2C_I2C_RXFLR_REG_RXFLR_Msk (0x3fUL) /*!< RXFLR (Bitfield-Mask: 0x3f) */
+/* ===================================================== I2C_RX_TL_REG ===================================================== */
+#define I2C_I2C_RX_TL_REG_RX_TL_Pos (0UL) /*!< RX_TL (Bit 0) */
+#define I2C_I2C_RX_TL_REG_RX_TL_Msk (0x1fUL) /*!< RX_TL (Bitfield-Mask: 0x1f) */
+/* ====================================================== I2C_SAR_REG ====================================================== */
+#define I2C_I2C_SAR_REG_IC_SAR_Pos (0UL) /*!< IC_SAR (Bit 0) */
+#define I2C_I2C_SAR_REG_IC_SAR_Msk (0x3ffUL) /*!< IC_SAR (Bitfield-Mask: 0x3ff) */
+/* =================================================== I2C_SDA_HOLD_REG ==================================================== */
+#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Pos (16UL) /*!< I2C_SDA_RX_HOLD (Bit 16) */
+#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Msk (0xff0000UL) /*!< I2C_SDA_RX_HOLD (Bitfield-Mask: 0xff) */
+#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Pos (0UL) /*!< I2C_SDA_TX_HOLD (Bit 0) */
+#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Msk (0xffffUL) /*!< I2C_SDA_TX_HOLD (Bitfield-Mask: 0xffff) */
+/* =================================================== I2C_SDA_SETUP_REG =================================================== */
+#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Pos (0UL) /*!< SDA_SETUP (Bit 0) */
+#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Msk (0xffUL) /*!< SDA_SETUP (Bitfield-Mask: 0xff) */
+/* ================================================== I2C_SS_SCL_HCNT_REG ================================================== */
+#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL) /*!< IC_SS_SCL_HCNT (Bit 0) */
+#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL) /*!< IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff) */
+/* ================================================== I2C_SS_SCL_LCNT_REG ================================================== */
+#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL) /*!< IC_SS_SCL_LCNT (Bit 0) */
+#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL) /*!< IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff) */
+/* ==================================================== I2C_STATUS_REG ===================================================== */
+#define I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Pos (10UL) /*!< LV_HOLD_RX_FIFO_FULL (Bit 10) */
+#define I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Msk (0x400UL) /*!< LV_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01) */
+#define I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Pos (9UL) /*!< SLV_HOLD_TX_FIFO_EMPTY (Bit 9) */
+#define I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Msk (0x200UL) /*!< SLV_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */
+#define I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Pos (8UL) /*!< MST_HOLD_RX_FIFO_FULL (Bit 8) */
+#define I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Msk (0x100UL) /*!< MST_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01) */
+#define I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Pos (7UL) /*!< MST_HOLD_TX_FIFO_EMPTY (Bit 7) */
+#define I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Msk (0x80UL) /*!< MST_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */
+#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Pos (6UL) /*!< SLV_ACTIVITY (Bit 6) */
+#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Msk (0x40UL) /*!< SLV_ACTIVITY (Bitfield-Mask: 0x01) */
+#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Pos (5UL) /*!< MST_ACTIVITY (Bit 5) */
+#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Msk (0x20UL) /*!< MST_ACTIVITY (Bitfield-Mask: 0x01) */
+#define I2C_I2C_STATUS_REG_RFF_Pos (4UL) /*!< RFF (Bit 4) */
+#define I2C_I2C_STATUS_REG_RFF_Msk (0x10UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define I2C_I2C_STATUS_REG_RFNE_Pos (3UL) /*!< RFNE (Bit 3) */
+#define I2C_I2C_STATUS_REG_RFNE_Msk (0x8UL) /*!< RFNE (Bitfield-Mask: 0x01) */
+#define I2C_I2C_STATUS_REG_TFE_Pos (2UL) /*!< TFE (Bit 2) */
+#define I2C_I2C_STATUS_REG_TFE_Msk (0x4UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define I2C_I2C_STATUS_REG_TFNF_Pos (1UL) /*!< TFNF (Bit 1) */
+#define I2C_I2C_STATUS_REG_TFNF_Msk (0x2UL) /*!< TFNF (Bitfield-Mask: 0x01) */
+#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Pos (0UL) /*!< I2C_ACTIVITY (Bit 0) */
+#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Msk (0x1UL) /*!< I2C_ACTIVITY (Bitfield-Mask: 0x01) */
+/* ====================================================== I2C_TAR_REG ====================================================== */
+#define I2C_I2C_TAR_REG_SPECIAL_Pos (11UL) /*!< SPECIAL (Bit 11) */
+#define I2C_I2C_TAR_REG_SPECIAL_Msk (0x800UL) /*!< SPECIAL (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TAR_REG_GC_OR_START_Pos (10UL) /*!< GC_OR_START (Bit 10) */
+#define I2C_I2C_TAR_REG_GC_OR_START_Msk (0x400UL) /*!< GC_OR_START (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TAR_REG_IC_TAR_Pos (0UL) /*!< IC_TAR (Bit 0) */
+#define I2C_I2C_TAR_REG_IC_TAR_Msk (0x3ffUL) /*!< IC_TAR (Bitfield-Mask: 0x3ff) */
+/* ===================================================== I2C_TXFLR_REG ===================================================== */
+#define I2C_I2C_TXFLR_REG_TXFLR_Pos (0UL) /*!< TXFLR (Bit 0) */
+#define I2C_I2C_TXFLR_REG_TXFLR_Msk (0x3fUL) /*!< TXFLR (Bitfield-Mask: 0x3f) */
+/* ================================================ I2C_TX_ABRT_SOURCE_REG ================================================= */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Pos (16UL) /*!< ABRT_USER_ABRT (Bit 16) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Msk (0x10000UL) /*!< ABRT_USER_ABRT (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL) /*!< ABRT_SLVRD_INTX (Bit 15) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL) /*!< ABRT_SLVRD_INTX (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL) /*!< ABRT_SLV_ARBLOST (Bit 14) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL) /*!< ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bit 13) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL) /*!< ARB_LOST (Bit 12) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL) /*!< ARB_LOST (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL) /*!< ABRT_MASTER_DIS (Bit 11) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL) /*!< ABRT_MASTER_DIS (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL) /*!< ABRT_10B_RD_NORSTRT (Bit 10) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL) /*!< ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL) /*!< ABRT_SBYTE_NORSTRT (Bit 9) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL) /*!< ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL) /*!< ABRT_HS_NORSTRT (Bit 8) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL) /*!< ABRT_HS_NORSTRT (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL) /*!< ABRT_SBYTE_ACKDET (Bit 7) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL) /*!< ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL) /*!< ABRT_HS_ACKDET (Bit 6) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL) /*!< ABRT_HS_ACKDET (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL) /*!< ABRT_GCALL_READ (Bit 5) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL) /*!< ABRT_GCALL_READ (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL) /*!< ABRT_GCALL_NOACK (Bit 4) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL) /*!< ABRT_GCALL_NOACK (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL) /*!< ABRT_TXDATA_NOACK (Bit 3) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL) /*!< ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL) /*!< ABRT_10ADDR2_NOACK (Bit 2) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL) /*!< ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL) /*!< ABRT_10ADDR1_NOACK (Bit 1) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL) /*!< ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL) /*!< ABRT_7B_ADDR_NOACK (Bit 0) */
+#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL) /*!< ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01) */
+/* ===================================================== I2C_TX_TL_REG ===================================================== */
+#define I2C_I2C_TX_TL_REG_TX_TL_Pos (0UL) /*!< TX_TL (Bit 0) */
+#define I2C_I2C_TX_TL_REG_TX_TL_Msk (0x1fUL) /*!< TX_TL (Bitfield-Mask: 0x1f) */
+
+
+/* =========================================================================================================================== */
+/* ================ I2C2 ================ */
+/* =========================================================================================================================== */
+
+/* =============================================== I2C2_ACK_GENERAL_CALL_REG =============================================== */
+#define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL) /*!< ACK_GEN_CALL (Bit 0) */
+#define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL) /*!< ACK_GEN_CALL (Bitfield-Mask: 0x01) */
+/* ================================================= I2C2_CLR_ACTIVITY_REG ================================================= */
+#define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL) /*!< CLR_ACTIVITY (Bit 0) */
+#define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL) /*!< CLR_ACTIVITY (Bitfield-Mask: 0x01) */
+/* ================================================= I2C2_CLR_GEN_CALL_REG ================================================= */
+#define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL) /*!< CLR_GEN_CALL (Bit 0) */
+#define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL) /*!< CLR_GEN_CALL (Bitfield-Mask: 0x01) */
+/* =================================================== I2C2_CLR_INTR_REG =================================================== */
+#define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Pos (0UL) /*!< CLR_INTR (Bit 0) */
+#define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Msk (0x1UL) /*!< CLR_INTR (Bitfield-Mask: 0x01) */
+/* ================================================== I2C2_CLR_RD_REQ_REG ================================================== */
+#define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL) /*!< CLR_RD_REQ (Bit 0) */
+#define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL) /*!< CLR_RD_REQ (Bitfield-Mask: 0x01) */
+/* ================================================= I2C2_CLR_RX_DONE_REG ================================================== */
+#define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL) /*!< CLR_RX_DONE (Bit 0) */
+#define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL) /*!< CLR_RX_DONE (Bitfield-Mask: 0x01) */
+/* ================================================= I2C2_CLR_RX_OVER_REG ================================================== */
+#define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL) /*!< CLR_RX_OVER (Bit 0) */
+#define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL) /*!< CLR_RX_OVER (Bitfield-Mask: 0x01) */
+/* ================================================= I2C2_CLR_RX_UNDER_REG ================================================= */
+#define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL) /*!< CLR_RX_UNDER (Bit 0) */
+#define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL) /*!< CLR_RX_UNDER (Bitfield-Mask: 0x01) */
+/* ================================================ I2C2_CLR_START_DET_REG ================================================= */
+#define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Pos (0UL) /*!< CLR_START_DET (Bit 0) */
+#define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL) /*!< CLR_START_DET (Bitfield-Mask: 0x01) */
+/* ================================================= I2C2_CLR_STOP_DET_REG ================================================= */
+#define I2C2_I2C2_CLR_STOP_DET_REG_CLR_STOP_DET_Pos (0UL) /*!< CLR_STOP_DET (Bit 0) */
+#define I2C2_I2C2_CLR_STOP_DET_REG_CLR_STOP_DET_Msk (0x1UL) /*!< CLR_STOP_DET (Bitfield-Mask: 0x01) */
+/* ================================================= I2C2_CLR_TX_ABRT_REG ================================================== */
+#define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL) /*!< CLR_TX_ABRT (Bit 0) */
+#define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL) /*!< CLR_TX_ABRT (Bitfield-Mask: 0x01) */
+/* ================================================= I2C2_CLR_TX_OVER_REG ================================================== */
+#define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL) /*!< CLR_TX_OVER (Bit 0) */
+#define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL) /*!< CLR_TX_OVER (Bitfield-Mask: 0x01) */
+/* ===================================================== I2C2_CON_REG ====================================================== */
+#define I2C2_I2C2_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Pos (10UL) /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bit 10) */
+#define I2C2_I2C2_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Msk (0x400UL) /*!< I2C_STOP_DET_IF_MASTER_ACTIVE (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Pos (9UL) /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bit 9) */
+#define I2C2_I2C2_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Msk (0x200UL) /*!< I2C_RX_FIFO_FULL_HLD_CTRL (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_CON_REG_I2C_TX_EMPTY_CTRL_Pos (8UL) /*!< I2C_TX_EMPTY_CTRL (Bit 8) */
+#define I2C2_I2C2_CON_REG_I2C_TX_EMPTY_CTRL_Msk (0x100UL) /*!< I2C_TX_EMPTY_CTRL (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_CON_REG_I2C_STOP_DET_IFADDRESSED_Pos (7UL) /*!< I2C_STOP_DET_IFADDRESSED (Bit 7) */
+#define I2C2_I2C2_CON_REG_I2C_STOP_DET_IFADDRESSED_Msk (0x80UL) /*!< I2C_STOP_DET_IFADDRESSED (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL) /*!< I2C_SLAVE_DISABLE (Bit 6) */
+#define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL) /*!< I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Pos (5UL) /*!< I2C_RESTART_EN (Bit 5) */
+#define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Msk (0x20UL) /*!< I2C_RESTART_EN (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL) /*!< I2C_10BITADDR_MASTER (Bit 4) */
+#define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL) /*!< I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL) /*!< I2C_10BITADDR_SLAVE (Bit 3) */
+#define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL) /*!< I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_CON_REG_I2C_SPEED_Pos (1UL) /*!< I2C_SPEED (Bit 1) */
+#define I2C2_I2C2_CON_REG_I2C_SPEED_Msk (0x6UL) /*!< I2C_SPEED (Bitfield-Mask: 0x03) */
+#define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Pos (0UL) /*!< I2C_MASTER_MODE (Bit 0) */
+#define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Msk (0x1UL) /*!< I2C_MASTER_MODE (Bitfield-Mask: 0x01) */
+/* =================================================== I2C2_DATA_CMD_REG =================================================== */
+#define I2C2_I2C2_DATA_CMD_REG_I2C_RESTART_Pos (10UL) /*!< I2C_RESTART (Bit 10) */
+#define I2C2_I2C2_DATA_CMD_REG_I2C_RESTART_Msk (0x400UL) /*!< I2C_RESTART (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_DATA_CMD_REG_I2C_STOP_Pos (9UL) /*!< I2C_STOP (Bit 9) */
+#define I2C2_I2C2_DATA_CMD_REG_I2C_STOP_Msk (0x200UL) /*!< I2C_STOP (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_DATA_CMD_REG_I2C_CMD_Pos (8UL) /*!< I2C_CMD (Bit 8) */
+#define I2C2_I2C2_DATA_CMD_REG_I2C_CMD_Msk (0x100UL) /*!< I2C_CMD (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_DATA_CMD_REG_I2C_DAT_Pos (0UL) /*!< I2C_DAT (Bit 0) */
+#define I2C2_I2C2_DATA_CMD_REG_I2C_DAT_Msk (0xffUL) /*!< I2C_DAT (Bitfield-Mask: 0xff) */
+/* ==================================================== I2C2_DMA_CR_REG ==================================================== */
+#define I2C2_I2C2_DMA_CR_REG_TDMAE_Pos (1UL) /*!< TDMAE (Bit 1) */
+#define I2C2_I2C2_DMA_CR_REG_TDMAE_Msk (0x2UL) /*!< TDMAE (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_DMA_CR_REG_RDMAE_Pos (0UL) /*!< RDMAE (Bit 0) */
+#define I2C2_I2C2_DMA_CR_REG_RDMAE_Msk (0x1UL) /*!< RDMAE (Bitfield-Mask: 0x01) */
+/* =================================================== I2C2_DMA_RDLR_REG =================================================== */
+#define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Pos (0UL) /*!< DMARDL (Bit 0) */
+#define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Msk (0x1fUL) /*!< DMARDL (Bitfield-Mask: 0x1f) */
+/* =================================================== I2C2_DMA_TDLR_REG =================================================== */
+#define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Pos (0UL) /*!< DMATDL (Bit 0) */
+#define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Msk (0x1fUL) /*!< DMATDL (Bitfield-Mask: 0x1f) */
+/* ==================================================== I2C2_ENABLE_REG ==================================================== */
+#define I2C2_I2C2_ENABLE_REG_I2C_TX_CMD_BLOCK_Pos (2UL) /*!< I2C_TX_CMD_BLOCK (Bit 2) */
+#define I2C2_I2C2_ENABLE_REG_I2C_TX_CMD_BLOCK_Msk (0x4UL) /*!< I2C_TX_CMD_BLOCK (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_ENABLE_REG_I2C_ABORT_Pos (1UL) /*!< I2C_ABORT (Bit 1) */
+#define I2C2_I2C2_ENABLE_REG_I2C_ABORT_Msk (0x2UL) /*!< I2C_ABORT (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_ENABLE_REG_I2C_EN_Pos (0UL) /*!< I2C_EN (Bit 0) */
+#define I2C2_I2C2_ENABLE_REG_I2C_EN_Msk (0x1UL) /*!< I2C_EN (Bitfield-Mask: 0x01) */
+/* ================================================ I2C2_ENABLE_STATUS_REG ================================================= */
+#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL) /*!< SLV_RX_DATA_LOST (Bit 2) */
+#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL) /*!< SLV_RX_DATA_LOST (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL) /*!< SLV_DISABLED_WHILE_BUSY (Bit 1) */
+#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL) /*!< SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Pos (0UL) /*!< IC_EN (Bit 0) */
+#define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Msk (0x1UL) /*!< IC_EN (Bitfield-Mask: 0x01) */
+/* ================================================= I2C2_FS_SCL_HCNT_REG ================================================== */
+#define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL) /*!< IC_FS_SCL_HCNT (Bit 0) */
+#define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL) /*!< IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff) */
+/* ================================================= I2C2_FS_SCL_LCNT_REG ================================================== */
+#define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL) /*!< IC_FS_SCL_LCNT (Bit 0) */
+#define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL) /*!< IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff) */
+/* =================================================== I2C2_HS_MADDR_REG =================================================== */
+#define I2C2_I2C2_HS_MADDR_REG_I2C_IC_HS_MAR_Pos (0UL) /*!< I2C_IC_HS_MAR (Bit 0) */
+#define I2C2_I2C2_HS_MADDR_REG_I2C_IC_HS_MAR_Msk (0x7UL) /*!< I2C_IC_HS_MAR (Bitfield-Mask: 0x07) */
+/* ================================================= I2C2_HS_SCL_HCNT_REG ================================================== */
+#define I2C2_I2C2_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Pos (0UL) /*!< IC_HS_SCL_HCNT (Bit 0) */
+#define I2C2_I2C2_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Msk (0xffffUL) /*!< IC_HS_SCL_HCNT (Bitfield-Mask: 0xffff) */
+/* ================================================= I2C2_HS_SCL_LCNT_REG ================================================== */
+#define I2C2_I2C2_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Pos (0UL) /*!< IC_HS_SCL_LCNT (Bit 0) */
+#define I2C2_I2C2_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Msk (0xffffUL) /*!< IC_HS_SCL_LCNT (Bitfield-Mask: 0xffff) */
+/* ================================================= I2C2_IC_FS_SPKLEN_REG ================================================= */
+#define I2C2_I2C2_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Pos (0UL) /*!< I2C_FS_SPKLEN (Bit 0) */
+#define I2C2_I2C2_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Msk (0xffUL) /*!< I2C_FS_SPKLEN (Bitfield-Mask: 0xff) */
+/* ================================================= I2C2_IC_HS_SPKLEN_REG ================================================= */
+#define I2C2_I2C2_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Pos (0UL) /*!< I2C_HS_SPKLEN (Bit 0) */
+#define I2C2_I2C2_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Msk (0xffUL) /*!< I2C_HS_SPKLEN (Bitfield-Mask: 0xff) */
+/* ================================================== I2C2_INTR_MASK_REG =================================================== */
+#define I2C2_I2C2_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Pos (14UL) /*!< M_SCL_STUCK_AT_LOW (Bit 14) */
+#define I2C2_I2C2_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< M_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_MASK_REG_M_MASTER_ON_HOLD_Pos (13UL) /*!< M_MASTER_ON_HOLD (Bit 13) */
+#define I2C2_I2C2_INTR_MASK_REG_M_MASTER_ON_HOLD_Msk (0x2000UL) /*!< M_MASTER_ON_HOLD (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_MASK_REG_M_RESTART_DET_Pos (12UL) /*!< M_RESTART_DET (Bit 12) */
+#define I2C2_I2C2_INTR_MASK_REG_M_RESTART_DET_Msk (0x1000UL) /*!< M_RESTART_DET (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Pos (11UL) /*!< M_GEN_CALL (Bit 11) */
+#define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Msk (0x800UL) /*!< M_GEN_CALL (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Pos (10UL) /*!< M_START_DET (Bit 10) */
+#define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Msk (0x400UL) /*!< M_START_DET (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Pos (9UL) /*!< M_STOP_DET (Bit 9) */
+#define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Msk (0x200UL) /*!< M_STOP_DET (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Pos (8UL) /*!< M_ACTIVITY (Bit 8) */
+#define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Msk (0x100UL) /*!< M_ACTIVITY (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Pos (7UL) /*!< M_RX_DONE (Bit 7) */
+#define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Msk (0x80UL) /*!< M_RX_DONE (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Pos (6UL) /*!< M_TX_ABRT (Bit 6) */
+#define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Msk (0x40UL) /*!< M_TX_ABRT (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Pos (5UL) /*!< M_RD_REQ (Bit 5) */
+#define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Msk (0x20UL) /*!< M_RD_REQ (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Pos (4UL) /*!< M_TX_EMPTY (Bit 4) */
+#define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Msk (0x10UL) /*!< M_TX_EMPTY (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Pos (3UL) /*!< M_TX_OVER (Bit 3) */
+#define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Msk (0x8UL) /*!< M_TX_OVER (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Pos (2UL) /*!< M_RX_FULL (Bit 2) */
+#define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Msk (0x4UL) /*!< M_RX_FULL (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Pos (1UL) /*!< M_RX_OVER (Bit 1) */
+#define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Msk (0x2UL) /*!< M_RX_OVER (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Pos (0UL) /*!< M_RX_UNDER (Bit 0) */
+#define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Msk (0x1UL) /*!< M_RX_UNDER (Bitfield-Mask: 0x01) */
+/* ================================================== I2C2_INTR_STAT_REG =================================================== */
+#define I2C2_I2C2_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Pos (14UL) /*!< R_SCL_STUCK_AT_LOW (Bit 14) */
+#define I2C2_I2C2_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< R_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_STAT_REG_R_MASTER_ON_HOLD_Pos (13UL) /*!< R_MASTER_ON_HOLD (Bit 13) */
+#define I2C2_I2C2_INTR_STAT_REG_R_MASTER_ON_HOLD_Msk (0x2000UL) /*!< R_MASTER_ON_HOLD (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_STAT_REG_R_RESTART_DET_Pos (12UL) /*!< R_RESTART_DET (Bit 12) */
+#define I2C2_I2C2_INTR_STAT_REG_R_RESTART_DET_Msk (0x1000UL) /*!< R_RESTART_DET (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Pos (11UL) /*!< R_GEN_CALL (Bit 11) */
+#define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Msk (0x800UL) /*!< R_GEN_CALL (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Pos (10UL) /*!< R_START_DET (Bit 10) */
+#define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Msk (0x400UL) /*!< R_START_DET (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Pos (9UL) /*!< R_STOP_DET (Bit 9) */
+#define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Msk (0x200UL) /*!< R_STOP_DET (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Pos (8UL) /*!< R_ACTIVITY (Bit 8) */
+#define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Msk (0x100UL) /*!< R_ACTIVITY (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Pos (7UL) /*!< R_RX_DONE (Bit 7) */
+#define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Msk (0x80UL) /*!< R_RX_DONE (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Pos (6UL) /*!< R_TX_ABRT (Bit 6) */
+#define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Msk (0x40UL) /*!< R_TX_ABRT (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Pos (5UL) /*!< R_RD_REQ (Bit 5) */
+#define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Msk (0x20UL) /*!< R_RD_REQ (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Pos (4UL) /*!< R_TX_EMPTY (Bit 4) */
+#define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Msk (0x10UL) /*!< R_TX_EMPTY (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Pos (3UL) /*!< R_TX_OVER (Bit 3) */
+#define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Msk (0x8UL) /*!< R_TX_OVER (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Pos (2UL) /*!< R_RX_FULL (Bit 2) */
+#define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Msk (0x4UL) /*!< R_RX_FULL (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Pos (1UL) /*!< R_RX_OVER (Bit 1) */
+#define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Msk (0x2UL) /*!< R_RX_OVER (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Pos (0UL) /*!< R_RX_UNDER (Bit 0) */
+#define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Msk (0x1UL) /*!< R_RX_UNDER (Bitfield-Mask: 0x01) */
+/* ================================================ I2C2_RAW_INTR_STAT_REG ================================================= */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Pos (14UL) /*!< SCL_STUCK_AT_LOW (Bit 14) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Msk (0x4000UL) /*!< SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Pos (13UL) /*!< MASTER_ON_HOLD (Bit 13) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Msk (0x2000UL) /*!< MASTER_ON_HOLD (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_RESTART_DET_Pos (12UL) /*!< RESTART_DET (Bit 12) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_RESTART_DET_Msk (0x1000UL) /*!< RESTART_DET (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL) /*!< GEN_CALL (Bit 11) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL) /*!< GEN_CALL (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Pos (10UL) /*!< START_DET (Bit 10) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL) /*!< START_DET (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL) /*!< STOP_DET (Bit 9) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL) /*!< STOP_DET (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL) /*!< ACTIVITY (Bit 8) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL) /*!< ACTIVITY (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL) /*!< RX_DONE (Bit 7) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL) /*!< RX_DONE (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL) /*!< TX_ABRT (Bit 6) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL) /*!< TX_ABRT (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Pos (5UL) /*!< RD_REQ (Bit 5) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Msk (0x20UL) /*!< RD_REQ (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL) /*!< TX_EMPTY (Bit 4) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL) /*!< TX_EMPTY (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL) /*!< TX_OVER (Bit 3) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL) /*!< TX_OVER (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL) /*!< RX_FULL (Bit 2) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL) /*!< RX_FULL (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL) /*!< RX_OVER (Bit 1) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL) /*!< RX_OVER (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL) /*!< RX_UNDER (Bit 0) */
+#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL) /*!< RX_UNDER (Bitfield-Mask: 0x01) */
+/* ==================================================== I2C2_RXFLR_REG ===================================================== */
+#define I2C2_I2C2_RXFLR_REG_RXFLR_Pos (0UL) /*!< RXFLR (Bit 0) */
+#define I2C2_I2C2_RXFLR_REG_RXFLR_Msk (0x3fUL) /*!< RXFLR (Bitfield-Mask: 0x3f) */
+/* ==================================================== I2C2_RX_TL_REG ===================================================== */
+#define I2C2_I2C2_RX_TL_REG_RX_TL_Pos (0UL) /*!< RX_TL (Bit 0) */
+#define I2C2_I2C2_RX_TL_REG_RX_TL_Msk (0x1fUL) /*!< RX_TL (Bitfield-Mask: 0x1f) */
+/* ===================================================== I2C2_SAR_REG ====================================================== */
+#define I2C2_I2C2_SAR_REG_IC_SAR_Pos (0UL) /*!< IC_SAR (Bit 0) */
+#define I2C2_I2C2_SAR_REG_IC_SAR_Msk (0x3ffUL) /*!< IC_SAR (Bitfield-Mask: 0x3ff) */
+/* =================================================== I2C2_SDA_HOLD_REG =================================================== */
+#define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Pos (16UL) /*!< I2C_SDA_RX_HOLD (Bit 16) */
+#define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Msk (0xff0000UL) /*!< I2C_SDA_RX_HOLD (Bitfield-Mask: 0xff) */
+#define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Pos (0UL) /*!< I2C_SDA_TX_HOLD (Bit 0) */
+#define I2C2_I2C2_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Msk (0xffffUL) /*!< I2C_SDA_TX_HOLD (Bitfield-Mask: 0xffff) */
+/* ================================================== I2C2_SDA_SETUP_REG =================================================== */
+#define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Pos (0UL) /*!< SDA_SETUP (Bit 0) */
+#define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Msk (0xffUL) /*!< SDA_SETUP (Bitfield-Mask: 0xff) */
+/* ================================================= I2C2_SS_SCL_HCNT_REG ================================================== */
+#define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL) /*!< IC_SS_SCL_HCNT (Bit 0) */
+#define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL) /*!< IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff) */
+/* ================================================= I2C2_SS_SCL_LCNT_REG ================================================== */
+#define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL) /*!< IC_SS_SCL_LCNT (Bit 0) */
+#define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL) /*!< IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff) */
+/* ==================================================== I2C2_STATUS_REG ==================================================== */
+#define I2C2_I2C2_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Pos (10UL) /*!< LV_HOLD_RX_FIFO_FULL (Bit 10) */
+#define I2C2_I2C2_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Msk (0x400UL) /*!< LV_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Pos (9UL) /*!< SLV_HOLD_TX_FIFO_EMPTY (Bit 9) */
+#define I2C2_I2C2_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Msk (0x200UL) /*!< SLV_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Pos (8UL) /*!< MST_HOLD_RX_FIFO_FULL (Bit 8) */
+#define I2C2_I2C2_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Msk (0x100UL) /*!< MST_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Pos (7UL) /*!< MST_HOLD_TX_FIFO_EMPTY (Bit 7) */
+#define I2C2_I2C2_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Msk (0x80UL) /*!< MST_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Pos (6UL) /*!< SLV_ACTIVITY (Bit 6) */
+#define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Msk (0x40UL) /*!< SLV_ACTIVITY (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Pos (5UL) /*!< MST_ACTIVITY (Bit 5) */
+#define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Msk (0x20UL) /*!< MST_ACTIVITY (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_STATUS_REG_RFF_Pos (4UL) /*!< RFF (Bit 4) */
+#define I2C2_I2C2_STATUS_REG_RFF_Msk (0x10UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_STATUS_REG_RFNE_Pos (3UL) /*!< RFNE (Bit 3) */
+#define I2C2_I2C2_STATUS_REG_RFNE_Msk (0x8UL) /*!< RFNE (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_STATUS_REG_TFE_Pos (2UL) /*!< TFE (Bit 2) */
+#define I2C2_I2C2_STATUS_REG_TFE_Msk (0x4UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_STATUS_REG_TFNF_Pos (1UL) /*!< TFNF (Bit 1) */
+#define I2C2_I2C2_STATUS_REG_TFNF_Msk (0x2UL) /*!< TFNF (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Pos (0UL) /*!< I2C_ACTIVITY (Bit 0) */
+#define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Msk (0x1UL) /*!< I2C_ACTIVITY (Bitfield-Mask: 0x01) */
+/* ===================================================== I2C2_TAR_REG ====================================================== */
+#define I2C2_I2C2_TAR_REG_SPECIAL_Pos (11UL) /*!< SPECIAL (Bit 11) */
+#define I2C2_I2C2_TAR_REG_SPECIAL_Msk (0x800UL) /*!< SPECIAL (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TAR_REG_GC_OR_START_Pos (10UL) /*!< GC_OR_START (Bit 10) */
+#define I2C2_I2C2_TAR_REG_GC_OR_START_Msk (0x400UL) /*!< GC_OR_START (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TAR_REG_IC_TAR_Pos (0UL) /*!< IC_TAR (Bit 0) */
+#define I2C2_I2C2_TAR_REG_IC_TAR_Msk (0x3ffUL) /*!< IC_TAR (Bitfield-Mask: 0x3ff) */
+/* ==================================================== I2C2_TXFLR_REG ===================================================== */
+#define I2C2_I2C2_TXFLR_REG_TXFLR_Pos (0UL) /*!< TXFLR (Bit 0) */
+#define I2C2_I2C2_TXFLR_REG_TXFLR_Msk (0x3fUL) /*!< TXFLR (Bitfield-Mask: 0x3f) */
+/* ================================================ I2C2_TX_ABRT_SOURCE_REG ================================================ */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Pos (16UL) /*!< ABRT_USER_ABRT (Bit 16) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Msk (0x10000UL) /*!< ABRT_USER_ABRT (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL) /*!< ABRT_SLVRD_INTX (Bit 15) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL) /*!< ABRT_SLVRD_INTX (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL) /*!< ABRT_SLV_ARBLOST (Bit 14) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL) /*!< ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bit 13) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL) /*!< ARB_LOST (Bit 12) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL) /*!< ARB_LOST (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL) /*!< ABRT_MASTER_DIS (Bit 11) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL) /*!< ABRT_MASTER_DIS (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL) /*!< ABRT_10B_RD_NORSTRT (Bit 10) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL) /*!< ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL) /*!< ABRT_SBYTE_NORSTRT (Bit 9) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL) /*!< ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL) /*!< ABRT_HS_NORSTRT (Bit 8) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL) /*!< ABRT_HS_NORSTRT (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL) /*!< ABRT_SBYTE_ACKDET (Bit 7) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL) /*!< ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL) /*!< ABRT_HS_ACKDET (Bit 6) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL) /*!< ABRT_HS_ACKDET (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL) /*!< ABRT_GCALL_READ (Bit 5) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL) /*!< ABRT_GCALL_READ (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL) /*!< ABRT_GCALL_NOACK (Bit 4) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL) /*!< ABRT_GCALL_NOACK (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL) /*!< ABRT_TXDATA_NOACK (Bit 3) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL) /*!< ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL) /*!< ABRT_10ADDR2_NOACK (Bit 2) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL) /*!< ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL) /*!< ABRT_10ADDR1_NOACK (Bit 1) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL) /*!< ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL) /*!< ABRT_7B_ADDR_NOACK (Bit 0) */
+#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL) /*!< ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01) */
+/* ==================================================== I2C2_TX_TL_REG ===================================================== */
+#define I2C2_I2C2_TX_TL_REG_TX_TL_Pos (0UL) /*!< TX_TL (Bit 0) */
+#define I2C2_I2C2_TX_TL_REG_TX_TL_Msk (0x1fUL) /*!< TX_TL (Bitfield-Mask: 0x1f) */
+
+
+/* =========================================================================================================================== */
+/* ================ LCDC ================ */
+/* =========================================================================================================================== */
+
+/* ================================================= LCDC_BACKPORCHXY_REG ================================================== */
+#define LCDC_LCDC_BACKPORCHXY_REG_LCDC_BPORCH_X_Pos (16UL) /*!< LCDC_BPORCH_X (Bit 16) */
+#define LCDC_LCDC_BACKPORCHXY_REG_LCDC_BPORCH_X_Msk (0xffff0000UL) /*!< LCDC_BPORCH_X (Bitfield-Mask: 0xffff) */
+#define LCDC_LCDC_BACKPORCHXY_REG_LCDC_BPORCH_Y_Pos (0UL) /*!< LCDC_BPORCH_Y (Bit 0) */
+#define LCDC_LCDC_BACKPORCHXY_REG_LCDC_BPORCH_Y_Msk (0xffffUL) /*!< LCDC_BPORCH_Y (Bitfield-Mask: 0xffff) */
+/* =================================================== LCDC_BGCOLOR_REG ==================================================== */
+#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_RED_Pos (24UL) /*!< LCDC_BG_RED (Bit 24) */
+#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_RED_Msk (0xff000000UL) /*!< LCDC_BG_RED (Bitfield-Mask: 0xff) */
+#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_GREEN_Pos (16UL) /*!< LCDC_BG_GREEN (Bit 16) */
+#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_GREEN_Msk (0xff0000UL) /*!< LCDC_BG_GREEN (Bitfield-Mask: 0xff) */
+#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_BLUE_Pos (8UL) /*!< LCDC_BG_BLUE (Bit 8) */
+#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_BLUE_Msk (0xff00UL) /*!< LCDC_BG_BLUE (Bitfield-Mask: 0xff) */
+#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_ALPHA_Pos (0UL) /*!< LCDC_BG_ALPHA (Bit 0) */
+#define LCDC_LCDC_BGCOLOR_REG_LCDC_BG_ALPHA_Msk (0xffUL) /*!< LCDC_BG_ALPHA (Bitfield-Mask: 0xff) */
+/* ================================================== LCDC_BLANKINGXY_REG ================================================== */
+#define LCDC_LCDC_BLANKINGXY_REG_LCDC_BLANKING_X_Pos (16UL) /*!< LCDC_BLANKING_X (Bit 16) */
+#define LCDC_LCDC_BLANKINGXY_REG_LCDC_BLANKING_X_Msk (0xffff0000UL) /*!< LCDC_BLANKING_X (Bitfield-Mask: 0xffff) */
+#define LCDC_LCDC_BLANKINGXY_REG_LCDC_BLANKING_Y_Pos (0UL) /*!< LCDC_BLANKING_Y (Bit 0) */
+#define LCDC_LCDC_BLANKINGXY_REG_LCDC_BLANKING_Y_Msk (0xffffUL) /*!< LCDC_BLANKING_Y (Bitfield-Mask: 0xffff) */
+/* =================================================== LCDC_CLKCTRL_REG ==================================================== */
+#define LCDC_LCDC_CLKCTRL_REG_LCDC_SEC_CLK_DIV_Pos (27UL) /*!< LCDC_SEC_CLK_DIV (Bit 27) */
+#define LCDC_LCDC_CLKCTRL_REG_LCDC_SEC_CLK_DIV_Msk (0xf8000000UL) /*!< LCDC_SEC_CLK_DIV (Bitfield-Mask: 0x1f) */
+#define LCDC_LCDC_CLKCTRL_REG_LCDC_DMA_HOLD_Pos (8UL) /*!< LCDC_DMA_HOLD (Bit 8) */
+#define LCDC_LCDC_CLKCTRL_REG_LCDC_DMA_HOLD_Msk (0x3f00UL) /*!< LCDC_DMA_HOLD (Bitfield-Mask: 0x3f) */
+#define LCDC_LCDC_CLKCTRL_REG_LCDC_CLK_DIV_Pos (0UL) /*!< LCDC_CLK_DIV (Bit 0) */
+#define LCDC_LCDC_CLKCTRL_REG_LCDC_CLK_DIV_Msk (0x3fUL) /*!< LCDC_CLK_DIV (Bitfield-Mask: 0x3f) */
+/* ===================================================== LCDC_CRC_REG ====================================================== */
+#define LCDC_LCDC_CRC_REG_LCDC_CRC_Pos (0UL) /*!< LCDC_CRC (Bit 0) */
+#define LCDC_LCDC_CRC_REG_LCDC_CRC_Msk (0xffffffffUL) /*!< LCDC_CRC (Bitfield-Mask: 0xffffffff) */
+/* =================================================== LCDC_DBIB_CFG_REG =================================================== */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_TE_DIS_Pos (31UL) /*!< LCDC_DBIB_TE_DIS (Bit 31) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_TE_DIS_Msk (0x80000000UL) /*!< LCDC_DBIB_TE_DIS (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_CSX_FORCE_Pos (30UL) /*!< LCDC_DBIB_CSX_FORCE (Bit 30) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_CSX_FORCE_Msk (0x40000000UL) /*!< LCDC_DBIB_CSX_FORCE (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_CSX_FORCE_VAL_Pos (29UL) /*!< LCDC_DBIB_CSX_FORCE_VAL (Bit 29) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_CSX_FORCE_VAL_Msk (0x20000000UL) /*!< LCDC_DBIB_CSX_FORCE_VAL (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_PAD_Pos (28UL) /*!< LCDC_DBIB_SPI_PAD (Bit 28) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_PAD_Msk (0x10000000UL) /*!< LCDC_DBIB_SPI_PAD (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_RESX_Pos (25UL) /*!< LCDC_DBIB_RESX (Bit 25) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_RESX_Msk (0x2000000UL) /*!< LCDC_DBIB_RESX (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_DMA_EN_Pos (24UL) /*!< LCDC_DBIB_DMA_EN (Bit 24) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_DMA_EN_Msk (0x1000000UL) /*!< LCDC_DBIB_DMA_EN (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI3_EN_Pos (23UL) /*!< LCDC_DBIB_SPI3_EN (Bit 23) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI3_EN_Msk (0x800000UL) /*!< LCDC_DBIB_SPI3_EN (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI4_EN_Pos (22UL) /*!< LCDC_DBIB_SPI4_EN (Bit 22) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI4_EN_Msk (0x400000UL) /*!< LCDC_DBIB_SPI4_EN (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_CPHA_Pos (20UL) /*!< LCDC_DBIB_SPI_CPHA (Bit 20) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_CPHA_Msk (0x100000UL) /*!< LCDC_DBIB_SPI_CPHA (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_CPOL_Pos (19UL) /*!< LCDC_DBIB_SPI_CPOL (Bit 19) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_CPOL_Msk (0x80000UL) /*!< LCDC_DBIB_SPI_CPOL (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_JDI_Pos (18UL) /*!< LCDC_DBIB_SPI_JDI (Bit 18) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_JDI_Msk (0x40000UL) /*!< LCDC_DBIB_SPI_JDI (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_HOLD_Pos (17UL) /*!< LCDC_DBIB_SPI_HOLD (Bit 17) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_HOLD_Msk (0x20000UL) /*!< LCDC_DBIB_SPI_HOLD (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_INV_ADDR_Pos (16UL) /*!< LCDC_DBIB_SPI_INV_ADDR (Bit 16) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_SPI_INV_ADDR_Msk (0x10000UL) /*!< LCDC_DBIB_SPI_INV_ADDR (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_INV_DATA_Pos (15UL) /*!< LCDC_DBIB_INV_DATA (Bit 15) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_INV_DATA_Msk (0x8000UL) /*!< LCDC_DBIB_INV_DATA (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_JDI_INV_PIX_Pos (14UL) /*!< LCDC_DBIB_JDI_INV_PIX (Bit 14) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_JDI_INV_PIX_Msk (0x4000UL) /*!< LCDC_DBIB_JDI_INV_PIX (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_JDI_SOFT_RST_Pos (13UL) /*!< LCDC_DBIB_JDI_SOFT_RST (Bit 13) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_JDI_SOFT_RST_Msk (0x2000UL) /*!< LCDC_DBIB_JDI_SOFT_RST (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_FMT_Pos (0UL) /*!< LCDC_DBIB_FMT (Bit 0) */
+#define LCDC_LCDC_DBIB_CFG_REG_LCDC_DBIB_FMT_Msk (0x1fUL) /*!< LCDC_DBIB_FMT (Bitfield-Mask: 0x1f) */
+/* =================================================== LCDC_DBIB_CMD_REG =================================================== */
+#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_SEND_Pos (30UL) /*!< LCDC_DBIB_CMD_SEND (Bit 30) */
+#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_SEND_Msk (0x40000000UL) /*!< LCDC_DBIB_CMD_SEND (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_STORE_Pos (27UL) /*!< LCDC_DBIB_CMD_STORE (Bit 27) */
+#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_STORE_Msk (0x8000000UL) /*!< LCDC_DBIB_CMD_STORE (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_VAL_Pos (0UL) /*!< LCDC_DBIB_CMD_VAL (Bit 0) */
+#define LCDC_LCDC_DBIB_CMD_REG_LCDC_DBIB_CMD_VAL_Msk (0xffffUL) /*!< LCDC_DBIB_CMD_VAL (Bitfield-Mask: 0xffff) */
+/* ================================================= LCDC_FRONTPORCHXY_REG ================================================= */
+#define LCDC_LCDC_FRONTPORCHXY_REG_LCDC_FPORCH_X_Pos (16UL) /*!< LCDC_FPORCH_X (Bit 16) */
+#define LCDC_LCDC_FRONTPORCHXY_REG_LCDC_FPORCH_X_Msk (0xffff0000UL) /*!< LCDC_FPORCH_X (Bitfield-Mask: 0xffff) */
+#define LCDC_LCDC_FRONTPORCHXY_REG_LCDC_FPORCH_Y_Pos (0UL) /*!< LCDC_FPORCH_Y (Bit 0) */
+#define LCDC_LCDC_FRONTPORCHXY_REG_LCDC_FPORCH_Y_Msk (0xffffUL) /*!< LCDC_FPORCH_Y (Bitfield-Mask: 0xffff) */
+/* ===================================================== LCDC_GPIO_REG ===================================================== */
+#define LCDC_LCDC_GPIO_REG_LCDC_TE_INV_Pos (1UL) /*!< LCDC_TE_INV (Bit 1) */
+#define LCDC_LCDC_GPIO_REG_LCDC_TE_INV_Msk (0x2UL) /*!< LCDC_TE_INV (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_GPIO_REG_LCDC_PARIF_SEL_Pos (0UL) /*!< LCDC_PARIF_SEL (Bit 0) */
+#define LCDC_LCDC_GPIO_REG_LCDC_PARIF_SEL_Msk (0x1UL) /*!< LCDC_PARIF_SEL (Bitfield-Mask: 0x01) */
+/* ==================================================== LCDC_IDREG_REG ===================================================== */
+#define LCDC_LCDC_IDREG_REG_LCDC_ID_Pos (0UL) /*!< LCDC_ID (Bit 0) */
+#define LCDC_LCDC_IDREG_REG_LCDC_ID_Msk (0xffffffffUL) /*!< LCDC_ID (Bitfield-Mask: 0xffffffff) */
+/* ================================================== LCDC_INTERRUPT_REG =================================================== */
+#define LCDC_LCDC_INTERRUPT_REG_LCDC_IRQ_TRIGGER_SEL_Pos (31UL) /*!< LCDC_IRQ_TRIGGER_SEL (Bit 31) */
+#define LCDC_LCDC_INTERRUPT_REG_LCDC_IRQ_TRIGGER_SEL_Msk (0x80000000UL) /*!< LCDC_IRQ_TRIGGER_SEL (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_INTERRUPT_REG_LCDC_FRAME_END_IRQ_EN_Pos (5UL) /*!< LCDC_FRAME_END_IRQ_EN (Bit 5) */
+#define LCDC_LCDC_INTERRUPT_REG_LCDC_FRAME_END_IRQ_EN_Msk (0x20UL) /*!< LCDC_FRAME_END_IRQ_EN (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_INTERRUPT_REG_LCDC_TE_IRQ_EN_Pos (3UL) /*!< LCDC_TE_IRQ_EN (Bit 3) */
+#define LCDC_LCDC_INTERRUPT_REG_LCDC_TE_IRQ_EN_Msk (0x8UL) /*!< LCDC_TE_IRQ_EN (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_INTERRUPT_REG_LCDC_HSYNC_IRQ_EN_Pos (1UL) /*!< LCDC_HSYNC_IRQ_EN (Bit 1) */
+#define LCDC_LCDC_INTERRUPT_REG_LCDC_HSYNC_IRQ_EN_Msk (0x2UL) /*!< LCDC_HSYNC_IRQ_EN (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Pos (0UL) /*!< LCDC_VSYNC_IRQ_EN (Bit 0) */
+#define LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Msk (0x1UL) /*!< LCDC_VSYNC_IRQ_EN (Bitfield-Mask: 0x01) */
+/* ============================================== LCDC_JDI_ENB_END_HLINE_REG =============================================== */
+#define LCDC_LCDC_JDI_ENB_END_HLINE_REG_LCDC_JDI_ENB_END_HLINE_Pos (0UL) /*!< LCDC_JDI_ENB_END_HLINE (Bit 0) */
+#define LCDC_LCDC_JDI_ENB_END_HLINE_REG_LCDC_JDI_ENB_END_HLINE_Msk (0xffffffffUL) /*!< LCDC_JDI_ENB_END_HLINE (Bitfield-Mask: 0xffffffff) */
+/* ============================================== LCDC_JDI_ENB_START_CLK_REG =============================================== */
+#define LCDC_LCDC_JDI_ENB_START_CLK_REG_LCDC_JDI_ENB_START_CLK_Pos (0UL) /*!< LCDC_JDI_ENB_START_CLK (Bit 0) */
+#define LCDC_LCDC_JDI_ENB_START_CLK_REG_LCDC_JDI_ENB_START_CLK_Msk (0xffffffffUL) /*!< LCDC_JDI_ENB_START_CLK (Bitfield-Mask: 0xffffffff) */
+/* ============================================= LCDC_JDI_ENB_START_HLINE_REG ============================================== */
+#define LCDC_LCDC_JDI_ENB_START_HLINE_REG_LCDC_JDI_ENB_START_HLINE_Pos (0UL) /*!< LCDC_JDI_ENB_START_HLINE (Bit 0) */
+#define LCDC_LCDC_JDI_ENB_START_HLINE_REG_LCDC_JDI_ENB_START_HLINE_Msk (0xffffffffUL) /*!< LCDC_JDI_ENB_START_HLINE (Bitfield-Mask: 0xffffffff) */
+/* ============================================== LCDC_JDI_ENB_WIDTH_CLK_REG =============================================== */
+#define LCDC_LCDC_JDI_ENB_WIDTH_CLK_REG_LCDC_JDI_ENB_WIDTH_CLK_Pos (0UL) /*!< LCDC_JDI_ENB_WIDTH_CLK (Bit 0) */
+#define LCDC_LCDC_JDI_ENB_WIDTH_CLK_REG_LCDC_JDI_ENB_WIDTH_CLK_Msk (0xffffffffUL) /*!< LCDC_JDI_ENB_WIDTH_CLK (Bitfield-Mask: 0xffffffff) */
+/* =============================================== LCDC_JDI_FBX_BLANKING_REG =============================================== */
+#define LCDC_LCDC_JDI_FBX_BLANKING_REG_LCDC_JDI_FXBLANKING_Pos (16UL) /*!< LCDC_JDI_FXBLANKING (Bit 16) */
+#define LCDC_LCDC_JDI_FBX_BLANKING_REG_LCDC_JDI_FXBLANKING_Msk (0xffff0000UL) /*!< LCDC_JDI_FXBLANKING (Bitfield-Mask: 0xffff) */
+#define LCDC_LCDC_JDI_FBX_BLANKING_REG_LCDC_JDI_BXBLANKING_Pos (0UL) /*!< LCDC_JDI_BXBLANKING (Bit 0) */
+#define LCDC_LCDC_JDI_FBX_BLANKING_REG_LCDC_JDI_BXBLANKING_Msk (0xffffUL) /*!< LCDC_JDI_BXBLANKING (Bitfield-Mask: 0xffff) */
+/* =============================================== LCDC_JDI_FBY_BLANKING_REG =============================================== */
+#define LCDC_LCDC_JDI_FBY_BLANKING_REG_LCDC_JDI_FYBLANKING_Pos (16UL) /*!< LCDC_JDI_FYBLANKING (Bit 16) */
+#define LCDC_LCDC_JDI_FBY_BLANKING_REG_LCDC_JDI_FYBLANKING_Msk (0xffff0000UL) /*!< LCDC_JDI_FYBLANKING (Bitfield-Mask: 0xffff) */
+#define LCDC_LCDC_JDI_FBY_BLANKING_REG_LCDC_JDI_BYBLANKING_Pos (0UL) /*!< LCDC_JDI_BYBLANKING (Bit 0) */
+#define LCDC_LCDC_JDI_FBY_BLANKING_REG_LCDC_JDI_BYBLANKING_Msk (0xffffUL) /*!< LCDC_JDI_BYBLANKING (Bitfield-Mask: 0xffff) */
+/* ================================================ LCDC_JDI_HCK_WIDTH_REG ================================================= */
+#define LCDC_LCDC_JDI_HCK_WIDTH_REG_LCDC_JDI_HCK_WIDTH_Pos (0UL) /*!< LCDC_JDI_HCK_WIDTH (Bit 0) */
+#define LCDC_LCDC_JDI_HCK_WIDTH_REG_LCDC_JDI_HCK_WIDTH_Msk (0xffffffffUL) /*!< LCDC_JDI_HCK_WIDTH (Bitfield-Mask: 0xffffffff) */
+/* ================================================ LCDC_JDI_HST_DELAY_REG ================================================= */
+#define LCDC_LCDC_JDI_HST_DELAY_REG_LCDC_JDI_HST_DELAY_Pos (0UL) /*!< LCDC_JDI_HST_DELAY (Bit 0) */
+#define LCDC_LCDC_JDI_HST_DELAY_REG_LCDC_JDI_HST_DELAY_Msk (0xffffffffUL) /*!< LCDC_JDI_HST_DELAY (Bitfield-Mask: 0xffffffff) */
+/* ================================================ LCDC_JDI_HST_WIDTH_REG ================================================= */
+#define LCDC_LCDC_JDI_HST_WIDTH_REG_LCDC_JDI_HST_WIDTH_Pos (0UL) /*!< LCDC_JDI_HST_WIDTH (Bit 0) */
+#define LCDC_LCDC_JDI_HST_WIDTH_REG_LCDC_JDI_HST_WIDTH_Msk (0xffffffffUL) /*!< LCDC_JDI_HST_WIDTH (Bitfield-Mask: 0xffffffff) */
+/* ================================================== LCDC_JDI_RESXY_REG =================================================== */
+#define LCDC_LCDC_JDI_RESXY_REG_LCDC_JDI_RES_X_Pos (16UL) /*!< LCDC_JDI_RES_X (Bit 16) */
+#define LCDC_LCDC_JDI_RESXY_REG_LCDC_JDI_RES_X_Msk (0xffff0000UL) /*!< LCDC_JDI_RES_X (Bitfield-Mask: 0xffff) */
+#define LCDC_LCDC_JDI_RESXY_REG_LCDC_JDI_RES_Y_Pos (0UL) /*!< LCDC_JDI_RES_Y (Bit 0) */
+#define LCDC_LCDC_JDI_RESXY_REG_LCDC_JDI_RES_Y_Msk (0xffffUL) /*!< LCDC_JDI_RES_Y (Bitfield-Mask: 0xffff) */
+/* ================================================ LCDC_JDI_VCK_DELAY_REG ================================================= */
+#define LCDC_LCDC_JDI_VCK_DELAY_REG_LCDC_JDI_VCK_DELAY_Pos (0UL) /*!< LCDC_JDI_VCK_DELAY (Bit 0) */
+#define LCDC_LCDC_JDI_VCK_DELAY_REG_LCDC_JDI_VCK_DELAY_Msk (0xffffffffUL) /*!< LCDC_JDI_VCK_DELAY (Bitfield-Mask: 0xffffffff) */
+/* ================================================ LCDC_JDI_VST_DELAY_REG ================================================= */
+#define LCDC_LCDC_JDI_VST_DELAY_REG_LCDC_JDI_VST_DELAY_Pos (0UL) /*!< LCDC_JDI_VST_DELAY (Bit 0) */
+#define LCDC_LCDC_JDI_VST_DELAY_REG_LCDC_JDI_VST_DELAY_Msk (0xffffffffUL) /*!< LCDC_JDI_VST_DELAY (Bitfield-Mask: 0xffffffff) */
+/* ================================================ LCDC_JDI_VST_WIDTH_REG ================================================= */
+#define LCDC_LCDC_JDI_VST_WIDTH_REG_LCDC_JDI_VST_WIDTH_Pos (0UL) /*!< LCDC_JDI_VST_WIDTH (Bit 0) */
+#define LCDC_LCDC_JDI_VST_WIDTH_REG_LCDC_JDI_VST_WIDTH_Msk (0xffffffffUL) /*!< LCDC_JDI_VST_WIDTH (Bitfield-Mask: 0xffffffff) */
+/* ================================================ LCDC_JDI_XRST_WIDTH_REG ================================================ */
+#define LCDC_LCDC_JDI_XRST_WIDTH_REG_LCDC_JDI_XRST_WIDTH_Pos (0UL) /*!< LCDC_JDI_XRST_WIDTH (Bit 0) */
+#define LCDC_LCDC_JDI_XRST_WIDTH_REG_LCDC_JDI_XRST_WIDTH_Msk (0xffffffffUL) /*!< LCDC_JDI_XRST_WIDTH (Bitfield-Mask: 0xffffffff) */
+/* =============================================== LCDC_LAYER0_BASEADDR_REG ================================================ */
+#define LCDC_LCDC_LAYER0_BASEADDR_REG_LCDC_L0_FB_ADDR_Pos (0UL) /*!< LCDC_L0_FB_ADDR (Bit 0) */
+#define LCDC_LCDC_LAYER0_BASEADDR_REG_LCDC_L0_FB_ADDR_Msk (0xffffffffUL) /*!< LCDC_L0_FB_ADDR (Bitfield-Mask: 0xffffffff) */
+/* ================================================= LCDC_LAYER0_MODE_REG ================================================== */
+#define LCDC_LCDC_LAYER0_MODE_REG_LCDC_L0_EN_Pos (31UL) /*!< LCDC_L0_EN (Bit 31) */
+#define LCDC_LCDC_LAYER0_MODE_REG_LCDC_L0_EN_Msk (0x80000000UL) /*!< LCDC_L0_EN (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_LAYER0_MODE_REG_LCDC_L0_COLOUR_MODE_Pos (0UL) /*!< LCDC_L0_COLOUR_MODE (Bit 0) */
+#define LCDC_LCDC_LAYER0_MODE_REG_LCDC_L0_COLOUR_MODE_Msk (0x1fUL) /*!< LCDC_L0_COLOUR_MODE (Bitfield-Mask: 0x1f) */
+/* ================================================ LCDC_LAYER0_OFFSETX_REG ================================================ */
+#define LCDC_LCDC_LAYER0_OFFSETX_REG_LCDC_L0_DMA_PREFETCH_Pos (16UL) /*!< LCDC_L0_DMA_PREFETCH (Bit 16) */
+#define LCDC_LCDC_LAYER0_OFFSETX_REG_LCDC_L0_DMA_PREFETCH_Msk (0xffff0000UL) /*!< LCDC_L0_DMA_PREFETCH (Bitfield-Mask: 0xffff) */
+#define LCDC_LCDC_LAYER0_OFFSETX_REG_LCDC_L0_OFFSETX_Pos (0UL) /*!< LCDC_L0_OFFSETX (Bit 0) */
+#define LCDC_LCDC_LAYER0_OFFSETX_REG_LCDC_L0_OFFSETX_Msk (0xffffUL) /*!< LCDC_L0_OFFSETX (Bitfield-Mask: 0xffff) */
+/* ================================================= LCDC_LAYER0_RESXY_REG ================================================= */
+#define LCDC_LCDC_LAYER0_RESXY_REG_LCDC_L0_RES_X_Pos (16UL) /*!< LCDC_L0_RES_X (Bit 16) */
+#define LCDC_LCDC_LAYER0_RESXY_REG_LCDC_L0_RES_X_Msk (0xffff0000UL) /*!< LCDC_L0_RES_X (Bitfield-Mask: 0xffff) */
+#define LCDC_LCDC_LAYER0_RESXY_REG_LCDC_L0_RES_Y_Pos (0UL) /*!< LCDC_L0_RES_Y (Bit 0) */
+#define LCDC_LCDC_LAYER0_RESXY_REG_LCDC_L0_RES_Y_Msk (0xffffUL) /*!< LCDC_L0_RES_Y (Bitfield-Mask: 0xffff) */
+/* ================================================ LCDC_LAYER0_SIZEXY_REG ================================================= */
+#define LCDC_LCDC_LAYER0_SIZEXY_REG_LCDC_L0_SIZE_X_Pos (16UL) /*!< LCDC_L0_SIZE_X (Bit 16) */
+#define LCDC_LCDC_LAYER0_SIZEXY_REG_LCDC_L0_SIZE_X_Msk (0xffff0000UL) /*!< LCDC_L0_SIZE_X (Bitfield-Mask: 0xffff) */
+#define LCDC_LCDC_LAYER0_SIZEXY_REG_LCDC_L0_SIZE_Y_Pos (0UL) /*!< LCDC_L0_SIZE_Y (Bit 0) */
+#define LCDC_LCDC_LAYER0_SIZEXY_REG_LCDC_L0_SIZE_Y_Msk (0xffffUL) /*!< LCDC_L0_SIZE_Y (Bitfield-Mask: 0xffff) */
+/* ================================================ LCDC_LAYER0_STARTXY_REG ================================================ */
+#define LCDC_LCDC_LAYER0_STARTXY_REG_LCDC_L0_START_X_Pos (16UL) /*!< LCDC_L0_START_X (Bit 16) */
+#define LCDC_LCDC_LAYER0_STARTXY_REG_LCDC_L0_START_X_Msk (0xffff0000UL) /*!< LCDC_L0_START_X (Bitfield-Mask: 0xffff) */
+#define LCDC_LCDC_LAYER0_STARTXY_REG_LCDC_L0_START_Y_Pos (0UL) /*!< LCDC_L0_START_Y (Bit 0) */
+#define LCDC_LCDC_LAYER0_STARTXY_REG_LCDC_L0_START_Y_Msk (0xffffUL) /*!< LCDC_L0_START_Y (Bitfield-Mask: 0xffff) */
+/* ================================================ LCDC_LAYER0_STRIDE_REG ================================================= */
+#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_FIFO_THR_Pos (19UL) /*!< LCDC_L0_FIFO_THR (Bit 19) */
+#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_FIFO_THR_Msk (0x180000UL) /*!< LCDC_L0_FIFO_THR (Bitfield-Mask: 0x03) */
+#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_BURST_LEN_Pos (16UL) /*!< LCDC_L0_BURST_LEN (Bit 16) */
+#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_BURST_LEN_Msk (0x70000UL) /*!< LCDC_L0_BURST_LEN (Bitfield-Mask: 0x07) */
+#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_STRIDE_Pos (0UL) /*!< LCDC_L0_STRIDE (Bit 0) */
+#define LCDC_LCDC_LAYER0_STRIDE_REG_LCDC_L0_STRIDE_Msk (0xffffUL) /*!< LCDC_L0_STRIDE (Bitfield-Mask: 0xffff) */
+/* ===================================================== LCDC_MODE_REG ===================================================== */
+#define LCDC_LCDC_MODE_REG_LCDC_MODE_EN_Pos (31UL) /*!< LCDC_MODE_EN (Bit 31) */
+#define LCDC_LCDC_MODE_REG_LCDC_MODE_EN_Msk (0x80000000UL) /*!< LCDC_MODE_EN (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_MODE_REG_LCDC_VSYNC_POL_Pos (28UL) /*!< LCDC_VSYNC_POL (Bit 28) */
+#define LCDC_LCDC_MODE_REG_LCDC_VSYNC_POL_Msk (0x10000000UL) /*!< LCDC_VSYNC_POL (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_MODE_REG_LCDC_HSYNC_POL_Pos (27UL) /*!< LCDC_HSYNC_POL (Bit 27) */
+#define LCDC_LCDC_MODE_REG_LCDC_HSYNC_POL_Msk (0x8000000UL) /*!< LCDC_HSYNC_POL (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_MODE_REG_LCDC_DE_POL_Pos (26UL) /*!< LCDC_DE_POL (Bit 26) */
+#define LCDC_LCDC_MODE_REG_LCDC_DE_POL_Msk (0x4000000UL) /*!< LCDC_DE_POL (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_MODE_REG_LCDC_VSYNC_SCPL_Pos (23UL) /*!< LCDC_VSYNC_SCPL (Bit 23) */
+#define LCDC_LCDC_MODE_REG_LCDC_VSYNC_SCPL_Msk (0x800000UL) /*!< LCDC_VSYNC_SCPL (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_MODE_REG_LCDC_PIXCLKOUT_POL_Pos (22UL) /*!< LCDC_PIXCLKOUT_POL (Bit 22) */
+#define LCDC_LCDC_MODE_REG_LCDC_PIXCLKOUT_POL_Msk (0x400000UL) /*!< LCDC_PIXCLKOUT_POL (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_MODE_REG_LCDC_FORCE_BLANK_Pos (19UL) /*!< LCDC_FORCE_BLANK (Bit 19) */
+#define LCDC_LCDC_MODE_REG_LCDC_FORCE_BLANK_Msk (0x80000UL) /*!< LCDC_FORCE_BLANK (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_MODE_REG_LCDC_SFRAME_UPD_Pos (17UL) /*!< LCDC_SFRAME_UPD (Bit 17) */
+#define LCDC_LCDC_MODE_REG_LCDC_SFRAME_UPD_Msk (0x20000UL) /*!< LCDC_SFRAME_UPD (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_MODE_REG_LCDC_PIXCLKOUT_SEL_Pos (11UL) /*!< LCDC_PIXCLKOUT_SEL (Bit 11) */
+#define LCDC_LCDC_MODE_REG_LCDC_PIXCLKOUT_SEL_Msk (0x800UL) /*!< LCDC_PIXCLKOUT_SEL (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_MODE_REG_LCDC_OUT_MODE_Pos (5UL) /*!< LCDC_OUT_MODE (Bit 5) */
+#define LCDC_LCDC_MODE_REG_LCDC_OUT_MODE_Msk (0x1e0UL) /*!< LCDC_OUT_MODE (Bitfield-Mask: 0x0f) */
+#define LCDC_LCDC_MODE_REG_LCDC_MIPI_OFF_Pos (4UL) /*!< LCDC_MIPI_OFF (Bit 4) */
+#define LCDC_LCDC_MODE_REG_LCDC_MIPI_OFF_Msk (0x10UL) /*!< LCDC_MIPI_OFF (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_MODE_REG_LCDC_FORM_OFF_Pos (3UL) /*!< LCDC_FORM_OFF (Bit 3) */
+#define LCDC_LCDC_MODE_REG_LCDC_FORM_OFF_Msk (0x8UL) /*!< LCDC_FORM_OFF (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_MODE_REG_LCDC_DSCAN_Pos (1UL) /*!< LCDC_DSCAN (Bit 1) */
+#define LCDC_LCDC_MODE_REG_LCDC_DSCAN_Msk (0x2UL) /*!< LCDC_DSCAN (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_MODE_REG_LCDC_TMODE_Pos (0UL) /*!< LCDC_TMODE (Bit 0) */
+#define LCDC_LCDC_MODE_REG_LCDC_TMODE_Msk (0x1UL) /*!< LCDC_TMODE (Bitfield-Mask: 0x01) */
+/* ==================================================== LCDC_RESXY_REG ===================================================== */
+#define LCDC_LCDC_RESXY_REG_LCDC_RES_X_Pos (16UL) /*!< LCDC_RES_X (Bit 16) */
+#define LCDC_LCDC_RESXY_REG_LCDC_RES_X_Msk (0xffff0000UL) /*!< LCDC_RES_X (Bitfield-Mask: 0xffff) */
+#define LCDC_LCDC_RESXY_REG_LCDC_RES_Y_Pos (0UL) /*!< LCDC_RES_Y (Bit 0) */
+#define LCDC_LCDC_RESXY_REG_LCDC_RES_Y_Msk (0xffffUL) /*!< LCDC_RES_Y (Bitfield-Mask: 0xffff) */
+/* ==================================================== LCDC_STATUS_REG ==================================================== */
+#define LCDC_LCDC_STATUS_REG_LCDC_JDI_TIM_SW_RST_Pos (15UL) /*!< LCDC_JDI_TIM_SW_RST (Bit 15) */
+#define LCDC_LCDC_STATUS_REG_LCDC_JDI_TIM_SW_RST_Msk (0x8000UL) /*!< LCDC_JDI_TIM_SW_RST (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_STATUS_REG_LCDC_FRAME_START_Pos (14UL) /*!< LCDC_FRAME_START (Bit 14) */
+#define LCDC_LCDC_STATUS_REG_LCDC_FRAME_START_Msk (0x4000UL) /*!< LCDC_FRAME_START (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_STATUS_REG_LCDC_FRAME_END_Pos (13UL) /*!< LCDC_FRAME_END (Bit 13) */
+#define LCDC_LCDC_STATUS_REG_LCDC_FRAME_END_Msk (0x2000UL) /*!< LCDC_FRAME_END (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_PENDING_Pos (12UL) /*!< LCDC_DBIB_CMD_PENDING (Bit 12) */
+#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_PENDING_Msk (0x1000UL) /*!< LCDC_DBIB_CMD_PENDING (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_FIFO_FULL_Pos (11UL) /*!< LCDC_DBIB_CMD_FIFO_FULL (Bit 11) */
+#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_FIFO_FULL_Msk (0x800UL) /*!< LCDC_DBIB_CMD_FIFO_FULL (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_FIFO_EMPTY_N_Pos (10UL) /*!< LCDC_DBIB_CMD_FIFO_EMPTY_N (Bit 10) */
+#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_CMD_FIFO_EMPTY_N_Msk (0x400UL) /*!< LCDC_DBIB_CMD_FIFO_EMPTY_N (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_TE_Pos (8UL) /*!< LCDC_DBIB_TE (Bit 8) */
+#define LCDC_LCDC_STATUS_REG_LCDC_DBIB_TE_Msk (0x100UL) /*!< LCDC_DBIB_TE (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_STATUS_REG_LCDC_STICKY_UNDERFLOW_Pos (7UL) /*!< LCDC_STICKY_UNDERFLOW (Bit 7) */
+#define LCDC_LCDC_STATUS_REG_LCDC_STICKY_UNDERFLOW_Msk (0x80UL) /*!< LCDC_STICKY_UNDERFLOW (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_STATUS_REG_LCDC_UNDERFLOW_Pos (6UL) /*!< LCDC_UNDERFLOW (Bit 6) */
+#define LCDC_LCDC_STATUS_REG_LCDC_UNDERFLOW_Msk (0x40UL) /*!< LCDC_UNDERFLOW (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_STATUS_REG_LCDC_LAST_ROW_Pos (5UL) /*!< LCDC_LAST_ROW (Bit 5) */
+#define LCDC_LCDC_STATUS_REG_LCDC_LAST_ROW_Msk (0x20UL) /*!< LCDC_LAST_ROW (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_STATUS_REG_LCDC_STAT_CSYNC_Pos (4UL) /*!< LCDC_STAT_CSYNC (Bit 4) */
+#define LCDC_LCDC_STATUS_REG_LCDC_STAT_CSYNC_Msk (0x10UL) /*!< LCDC_STAT_CSYNC (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_STATUS_REG_LCDC_STAT_VSYNC_Pos (3UL) /*!< LCDC_STAT_VSYNC (Bit 3) */
+#define LCDC_LCDC_STATUS_REG_LCDC_STAT_VSYNC_Msk (0x8UL) /*!< LCDC_STAT_VSYNC (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_STATUS_REG_LCDC_STAT_HSYNC_Pos (2UL) /*!< LCDC_STAT_HSYNC (Bit 2) */
+#define LCDC_LCDC_STATUS_REG_LCDC_STAT_HSYNC_Msk (0x4UL) /*!< LCDC_STAT_HSYNC (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_STATUS_REG_LCDC_FRAMEGEN_BUSY_Pos (1UL) /*!< LCDC_FRAMEGEN_BUSY (Bit 1) */
+#define LCDC_LCDC_STATUS_REG_LCDC_FRAMEGEN_BUSY_Msk (0x2UL) /*!< LCDC_FRAMEGEN_BUSY (Bitfield-Mask: 0x01) */
+#define LCDC_LCDC_STATUS_REG_LCDC_STAT_ACTIVE_Pos (0UL) /*!< LCDC_STAT_ACTIVE (Bit 0) */
+#define LCDC_LCDC_STATUS_REG_LCDC_STAT_ACTIVE_Msk (0x1UL) /*!< LCDC_STAT_ACTIVE (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ LRA ================ */
+/* =========================================================================================================================== */
+
+/* =================================================== LRA_ADC_CTRL1_REG =================================================== */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_BUSY_Pos (31UL) /*!< LRA_ADC_BUSY (Bit 31) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_BUSY_Msk (0x80000000UL) /*!< LRA_ADC_BUSY (Bitfield-Mask: 0x01) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_OFFSET_Pos (9UL) /*!< LRA_ADC_OFFSET (Bit 9) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_OFFSET_Msk (0x1fe00UL) /*!< LRA_ADC_OFFSET (Bitfield-Mask: 0xff) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_TEST_PARAM_Pos (8UL) /*!< LRA_ADC_TEST_PARAM (Bit 8) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_TEST_PARAM_Msk (0x100UL) /*!< LRA_ADC_TEST_PARAM (Bitfield-Mask: 0x01) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_TEST_IN_SEL_Pos (7UL) /*!< LRA_ADC_TEST_IN_SEL (Bit 7) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_TEST_IN_SEL_Msk (0x80UL) /*!< LRA_ADC_TEST_IN_SEL (Bitfield-Mask: 0x01) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_FREQ_Pos (3UL) /*!< LRA_ADC_FREQ (Bit 3) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_FREQ_Msk (0x78UL) /*!< LRA_ADC_FREQ (Bitfield-Mask: 0x0f) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_SIGN_Pos (2UL) /*!< LRA_ADC_SIGN (Bit 2) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_SIGN_Msk (0x4UL) /*!< LRA_ADC_SIGN (Bitfield-Mask: 0x01) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_MUTE_Pos (1UL) /*!< LRA_ADC_MUTE (Bit 1) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_MUTE_Msk (0x2UL) /*!< LRA_ADC_MUTE (Bitfield-Mask: 0x01) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_START_Pos (0UL) /*!< LRA_ADC_START (Bit 0) */
+#define LRA_LRA_ADC_CTRL1_REG_LRA_ADC_START_Msk (0x1UL) /*!< LRA_ADC_START (Bitfield-Mask: 0x01) */
+/* ================================================== LRA_ADC_RESULT_REG =================================================== */
+#define LRA_LRA_ADC_RESULT_REG_MAN_FLT_IN_Pos (16UL) /*!< MAN_FLT_IN (Bit 16) */
+#define LRA_LRA_ADC_RESULT_REG_MAN_FLT_IN_Msk (0xffff0000UL) /*!< MAN_FLT_IN (Bitfield-Mask: 0xffff) */
+#define LRA_LRA_ADC_RESULT_REG_GP_ADC_VAL_Pos (0UL) /*!< GP_ADC_VAL (Bit 0) */
+#define LRA_LRA_ADC_RESULT_REG_GP_ADC_VAL_Msk (0xffffUL) /*!< GP_ADC_VAL (Bitfield-Mask: 0xffff) */
+/* ==================================================== LRA_BRD_HS_REG ===================================================== */
+#define LRA_LRA_BRD_HS_REG_TRIM_GAIN_Pos (11UL) /*!< TRIM_GAIN (Bit 11) */
+#define LRA_LRA_BRD_HS_REG_TRIM_GAIN_Msk (0x7800UL) /*!< TRIM_GAIN (Bitfield-Mask: 0x0f) */
+#define LRA_LRA_BRD_HS_REG_HSGND_TRIM_Pos (8UL) /*!< HSGND_TRIM (Bit 8) */
+#define LRA_LRA_BRD_HS_REG_HSGND_TRIM_Msk (0x700UL) /*!< HSGND_TRIM (Bitfield-Mask: 0x07) */
+#define LRA_LRA_BRD_HS_REG_SCP_HS_TRIM_Pos (4UL) /*!< SCP_HS_TRIM (Bit 4) */
+#define LRA_LRA_BRD_HS_REG_SCP_HS_TRIM_Msk (0xf0UL) /*!< SCP_HS_TRIM (Bitfield-Mask: 0x0f) */
+#define LRA_LRA_BRD_HS_REG_SCP_HS_EN_Pos (3UL) /*!< SCP_HS_EN (Bit 3) */
+#define LRA_LRA_BRD_HS_REG_SCP_HS_EN_Msk (0x8UL) /*!< SCP_HS_EN (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_HS_REG_ERC_HS_TRIM_Pos (1UL) /*!< ERC_HS_TRIM (Bit 1) */
+#define LRA_LRA_BRD_HS_REG_ERC_HS_TRIM_Msk (0x6UL) /*!< ERC_HS_TRIM (Bitfield-Mask: 0x03) */
+#define LRA_LRA_BRD_HS_REG_ERC_HS_EN_Pos (0UL) /*!< ERC_HS_EN (Bit 0) */
+#define LRA_LRA_BRD_HS_REG_ERC_HS_EN_Msk (0x1UL) /*!< ERC_HS_EN (Bitfield-Mask: 0x01) */
+/* ==================================================== LRA_BRD_LS_REG ===================================================== */
+#define LRA_LRA_BRD_LS_REG_SCP_LS_TRIM_N_Pos (8UL) /*!< SCP_LS_TRIM_N (Bit 8) */
+#define LRA_LRA_BRD_LS_REG_SCP_LS_TRIM_N_Msk (0xf00UL) /*!< SCP_LS_TRIM_N (Bitfield-Mask: 0x0f) */
+#define LRA_LRA_BRD_LS_REG_SCP_LS_TRIM_P_Pos (4UL) /*!< SCP_LS_TRIM_P (Bit 4) */
+#define LRA_LRA_BRD_LS_REG_SCP_LS_TRIM_P_Msk (0xf0UL) /*!< SCP_LS_TRIM_P (Bitfield-Mask: 0x0f) */
+#define LRA_LRA_BRD_LS_REG_SCP_LS_EN_Pos (3UL) /*!< SCP_LS_EN (Bit 3) */
+#define LRA_LRA_BRD_LS_REG_SCP_LS_EN_Msk (0x8UL) /*!< SCP_LS_EN (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_LS_REG_ERC_LS_TRIM_Pos (1UL) /*!< ERC_LS_TRIM (Bit 1) */
+#define LRA_LRA_BRD_LS_REG_ERC_LS_TRIM_Msk (0x6UL) /*!< ERC_LS_TRIM (Bitfield-Mask: 0x03) */
+#define LRA_LRA_BRD_LS_REG_ERC_LS_EN_Pos (0UL) /*!< ERC_LS_EN (Bit 0) */
+#define LRA_LRA_BRD_LS_REG_ERC_LS_EN_Msk (0x1UL) /*!< ERC_LS_EN (Bitfield-Mask: 0x01) */
+/* =================================================== LRA_BRD_STAT_REG ==================================================== */
+#define LRA_LRA_BRD_STAT_REG_SCP_HS_OUT_Pos (13UL) /*!< SCP_HS_OUT (Bit 13) */
+#define LRA_LRA_BRD_STAT_REG_SCP_HS_OUT_Msk (0x2000UL) /*!< SCP_HS_OUT (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_STAT_REG_SCP_LS_COMP_OUT_N_Pos (12UL) /*!< SCP_LS_COMP_OUT_N (Bit 12) */
+#define LRA_LRA_BRD_STAT_REG_SCP_LS_COMP_OUT_N_Msk (0x1000UL) /*!< SCP_LS_COMP_OUT_N (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_STAT_REG_SCP_LS_COMP_OUT_P_Pos (11UL) /*!< SCP_LS_COMP_OUT_P (Bit 11) */
+#define LRA_LRA_BRD_STAT_REG_SCP_LS_COMP_OUT_P_Msk (0x800UL) /*!< SCP_LS_COMP_OUT_P (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_STAT_REG_SC_EVENT_LS_Pos (10UL) /*!< SC_EVENT_LS (Bit 10) */
+#define LRA_LRA_BRD_STAT_REG_SC_EVENT_LS_Msk (0x400UL) /*!< SC_EVENT_LS (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_STAT_REG_SC_EVENT_HS_Pos (9UL) /*!< SC_EVENT_HS (Bit 9) */
+#define LRA_LRA_BRD_STAT_REG_SC_EVENT_HS_Msk (0x200UL) /*!< SC_EVENT_HS (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_STAT_REG_LOOP_STAT_Pos (8UL) /*!< LOOP_STAT (Bit 8) */
+#define LRA_LRA_BRD_STAT_REG_LOOP_STAT_Msk (0x100UL) /*!< LOOP_STAT (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_STAT_REG_LSN_ON_Pos (7UL) /*!< LSN_ON (Bit 7) */
+#define LRA_LRA_BRD_STAT_REG_LSN_ON_Msk (0x80UL) /*!< LSN_ON (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_STAT_REG_LSP_ON_Pos (6UL) /*!< LSP_ON (Bit 6) */
+#define LRA_LRA_BRD_STAT_REG_LSP_ON_Msk (0x40UL) /*!< LSP_ON (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_STAT_REG_HSN_ON_Pos (5UL) /*!< HSN_ON (Bit 5) */
+#define LRA_LRA_BRD_STAT_REG_HSN_ON_Msk (0x20UL) /*!< HSN_ON (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_STAT_REG_HSP_ON_Pos (4UL) /*!< HSP_ON (Bit 4) */
+#define LRA_LRA_BRD_STAT_REG_HSP_ON_Msk (0x10UL) /*!< HSP_ON (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_STAT_REG_LSN_STAT_Pos (3UL) /*!< LSN_STAT (Bit 3) */
+#define LRA_LRA_BRD_STAT_REG_LSN_STAT_Msk (0x8UL) /*!< LSN_STAT (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_STAT_REG_LSP_STAT_Pos (2UL) /*!< LSP_STAT (Bit 2) */
+#define LRA_LRA_BRD_STAT_REG_LSP_STAT_Msk (0x4UL) /*!< LSP_STAT (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_STAT_REG_HSN_STAT_Pos (1UL) /*!< HSN_STAT (Bit 1) */
+#define LRA_LRA_BRD_STAT_REG_HSN_STAT_Msk (0x2UL) /*!< HSN_STAT (Bitfield-Mask: 0x01) */
+#define LRA_LRA_BRD_STAT_REG_HSP_STAT_Pos (0UL) /*!< HSP_STAT (Bit 0) */
+#define LRA_LRA_BRD_STAT_REG_HSP_STAT_Msk (0x1UL) /*!< HSP_STAT (Bitfield-Mask: 0x01) */
+/* ===================================================== LRA_CTRL1_REG ===================================================== */
+#define LRA_LRA_CTRL1_REG_SMP_IDX_Pos (24UL) /*!< SMP_IDX (Bit 24) */
+#define LRA_LRA_CTRL1_REG_SMP_IDX_Msk (0xf000000UL) /*!< SMP_IDX (Bitfield-Mask: 0x0f) */
+#define LRA_LRA_CTRL1_REG_IRQ_SCP_EVENT_EN_Pos (18UL) /*!< IRQ_SCP_EVENT_EN (Bit 18) */
+#define LRA_LRA_CTRL1_REG_IRQ_SCP_EVENT_EN_Msk (0x40000UL) /*!< IRQ_SCP_EVENT_EN (Bitfield-Mask: 0x01) */
+#define LRA_LRA_CTRL1_REG_IRQ_ADC_EN_Pos (17UL) /*!< IRQ_ADC_EN (Bit 17) */
+#define LRA_LRA_CTRL1_REG_IRQ_ADC_EN_Msk (0x20000UL) /*!< IRQ_ADC_EN (Bitfield-Mask: 0x01) */
+#define LRA_LRA_CTRL1_REG_IRQ_CTRL_EN_Pos (16UL) /*!< IRQ_CTRL_EN (Bit 16) */
+#define LRA_LRA_CTRL1_REG_IRQ_CTRL_EN_Msk (0x10000UL) /*!< IRQ_CTRL_EN (Bitfield-Mask: 0x01) */
+#define LRA_LRA_CTRL1_REG_IRQ_IDX_Pos (12UL) /*!< IRQ_IDX (Bit 12) */
+#define LRA_LRA_CTRL1_REG_IRQ_IDX_Msk (0xf000UL) /*!< IRQ_IDX (Bitfield-Mask: 0x0f) */
+#define LRA_LRA_CTRL1_REG_IRQ_DIV_Pos (8UL) /*!< IRQ_DIV (Bit 8) */
+#define LRA_LRA_CTRL1_REG_IRQ_DIV_Msk (0xf00UL) /*!< IRQ_DIV (Bitfield-Mask: 0x0f) */
+#define LRA_LRA_CTRL1_REG_SMP_SEL_Pos (6UL) /*!< SMP_SEL (Bit 6) */
+#define LRA_LRA_CTRL1_REG_SMP_SEL_Msk (0xc0UL) /*!< SMP_SEL (Bitfield-Mask: 0x03) */
+#define LRA_LRA_CTRL1_REG_PULLDOWN_EN_Pos (5UL) /*!< PULLDOWN_EN (Bit 5) */
+#define LRA_LRA_CTRL1_REG_PULLDOWN_EN_Msk (0x20UL) /*!< PULLDOWN_EN (Bitfield-Mask: 0x01) */
+#define LRA_LRA_CTRL1_REG_LOOP_EN_Pos (4UL) /*!< LOOP_EN (Bit 4) */
+#define LRA_LRA_CTRL1_REG_LOOP_EN_Msk (0x10UL) /*!< LOOP_EN (Bitfield-Mask: 0x01) */
+#define LRA_LRA_CTRL1_REG_LDO_EN_Pos (3UL) /*!< LDO_EN (Bit 3) */
+#define LRA_LRA_CTRL1_REG_LDO_EN_Msk (0x8UL) /*!< LDO_EN (Bitfield-Mask: 0x01) */
+#define LRA_LRA_CTRL1_REG_ADC_EN_Pos (2UL) /*!< ADC_EN (Bit 2) */
+#define LRA_LRA_CTRL1_REG_ADC_EN_Msk (0x4UL) /*!< ADC_EN (Bitfield-Mask: 0x01) */
+#define LRA_LRA_CTRL1_REG_HBRIDGE_EN_Pos (1UL) /*!< HBRIDGE_EN (Bit 1) */
+#define LRA_LRA_CTRL1_REG_HBRIDGE_EN_Msk (0x2UL) /*!< HBRIDGE_EN (Bitfield-Mask: 0x01) */
+#define LRA_LRA_CTRL1_REG_LRA_EN_Pos (0UL) /*!< LRA_EN (Bit 0) */
+#define LRA_LRA_CTRL1_REG_LRA_EN_Msk (0x1UL) /*!< LRA_EN (Bitfield-Mask: 0x01) */
+/* ===================================================== LRA_CTRL2_REG ===================================================== */
+#define LRA_LRA_CTRL2_REG_HALF_PERIOD_Pos (16UL) /*!< HALF_PERIOD (Bit 16) */
+#define LRA_LRA_CTRL2_REG_HALF_PERIOD_Msk (0xffff0000UL) /*!< HALF_PERIOD (Bitfield-Mask: 0xffff) */
+#define LRA_LRA_CTRL2_REG_AUTO_MODE_Pos (5UL) /*!< AUTO_MODE (Bit 5) */
+#define LRA_LRA_CTRL2_REG_AUTO_MODE_Msk (0x20UL) /*!< AUTO_MODE (Bitfield-Mask: 0x01) */
+#define LRA_LRA_CTRL2_REG_SMP_MODE_Pos (4UL) /*!< SMP_MODE (Bit 4) */
+#define LRA_LRA_CTRL2_REG_SMP_MODE_Msk (0x10UL) /*!< SMP_MODE (Bitfield-Mask: 0x01) */
+#define LRA_LRA_CTRL2_REG_POLARITY_Pos (3UL) /*!< POLARITY (Bit 3) */
+#define LRA_LRA_CTRL2_REG_POLARITY_Msk (0x8UL) /*!< POLARITY (Bitfield-Mask: 0x01) */
+#define LRA_LRA_CTRL2_REG_FLT_IN_SEL_Pos (2UL) /*!< FLT_IN_SEL (Bit 2) */
+#define LRA_LRA_CTRL2_REG_FLT_IN_SEL_Msk (0x4UL) /*!< FLT_IN_SEL (Bitfield-Mask: 0x01) */
+#define LRA_LRA_CTRL2_REG_PWM_MODE_Pos (0UL) /*!< PWM_MODE (Bit 0) */
+#define LRA_LRA_CTRL2_REG_PWM_MODE_Msk (0x3UL) /*!< PWM_MODE (Bitfield-Mask: 0x03) */
+/* ===================================================== LRA_CTRL3_REG ===================================================== */
+#define LRA_LRA_CTRL3_REG_VREF_Pos (16UL) /*!< VREF (Bit 16) */
+#define LRA_LRA_CTRL3_REG_VREF_Msk (0xffff0000UL) /*!< VREF (Bitfield-Mask: 0xffff) */
+#define LRA_LRA_CTRL3_REG_DREF_Pos (0UL) /*!< DREF (Bit 0) */
+#define LRA_LRA_CTRL3_REG_DREF_Msk (0xffffUL) /*!< DREF (Bitfield-Mask: 0xffff) */
+/* ====================================================== LRA_DFT_REG ====================================================== */
+#define LRA_LRA_DFT_REG_SPARE_Pos (29UL) /*!< SPARE (Bit 29) */
+#define LRA_LRA_DFT_REG_SPARE_Msk (0xe0000000UL) /*!< SPARE (Bitfield-Mask: 0x07) */
+#define LRA_LRA_DFT_REG_SWM_SEL_Pos (28UL) /*!< SWM_SEL (Bit 28) */
+#define LRA_LRA_DFT_REG_SWM_SEL_Msk (0x10000000UL) /*!< SWM_SEL (Bitfield-Mask: 0x01) */
+#define LRA_LRA_DFT_REG_SWM_MAN_Pos (27UL) /*!< SWM_MAN (Bit 27) */
+#define LRA_LRA_DFT_REG_SWM_MAN_Msk (0x8000000UL) /*!< SWM_MAN (Bitfield-Mask: 0x01) */
+#define LRA_LRA_DFT_REG_PWM_SEL_Pos (26UL) /*!< PWM_SEL (Bit 26) */
+#define LRA_LRA_DFT_REG_PWM_SEL_Msk (0x4000000UL) /*!< PWM_SEL (Bitfield-Mask: 0x01) */
+#define LRA_LRA_DFT_REG_PWM_MAN_Pos (25UL) /*!< PWM_MAN (Bit 25) */
+#define LRA_LRA_DFT_REG_PWM_MAN_Msk (0x2000000UL) /*!< PWM_MAN (Bitfield-Mask: 0x01) */
+#define LRA_LRA_DFT_REG_TIMER_TRIM_Pos (23UL) /*!< TIMER_TRIM (Bit 23) */
+#define LRA_LRA_DFT_REG_TIMER_TRIM_Msk (0x1800000UL) /*!< TIMER_TRIM (Bitfield-Mask: 0x03) */
+#define LRA_LRA_DFT_REG_TIMER_SCALE_TRIM_Pos (21UL) /*!< TIMER_SCALE_TRIM (Bit 21) */
+#define LRA_LRA_DFT_REG_TIMER_SCALE_TRIM_Msk (0x600000UL) /*!< TIMER_SCALE_TRIM (Bitfield-Mask: 0x03) */
+#define LRA_LRA_DFT_REG_DFT_SEL_Pos (20UL) /*!< DFT_SEL (Bit 20) */
+#define LRA_LRA_DFT_REG_DFT_SEL_Msk (0x100000UL) /*!< DFT_SEL (Bitfield-Mask: 0x01) */
+#define LRA_LRA_DFT_REG_DFT_FORCE_HSPN_Pos (19UL) /*!< DFT_FORCE_HSPN (Bit 19) */
+#define LRA_LRA_DFT_REG_DFT_FORCE_HSPN_Msk (0x80000UL) /*!< DFT_FORCE_HSPN (Bitfield-Mask: 0x01) */
+#define LRA_LRA_DFT_REG_DFT_EN_TIMER_Pos (18UL) /*!< DFT_EN_TIMER (Bit 18) */
+#define LRA_LRA_DFT_REG_DFT_EN_TIMER_Msk (0x40000UL) /*!< DFT_EN_TIMER (Bitfield-Mask: 0x01) */
+#define LRA_LRA_DFT_REG_DFT_STALL_Pos (16UL) /*!< DFT_STALL (Bit 16) */
+#define LRA_LRA_DFT_REG_DFT_STALL_Msk (0x30000UL) /*!< DFT_STALL (Bitfield-Mask: 0x03) */
+#define LRA_LRA_DFT_REG_DFT_CTRL_Pos (0UL) /*!< DFT_CTRL (Bit 0) */
+#define LRA_LRA_DFT_REG_DFT_CTRL_Msk (0xffffUL) /*!< DFT_CTRL (Bitfield-Mask: 0xffff) */
+/* =================================================== LRA_FLT_COEF1_REG =================================================== */
+#define LRA_LRA_FLT_COEF1_REG_FLT_COEF_01_Pos (16UL) /*!< FLT_COEF_01 (Bit 16) */
+#define LRA_LRA_FLT_COEF1_REG_FLT_COEF_01_Msk (0xffff0000UL) /*!< FLT_COEF_01 (Bitfield-Mask: 0xffff) */
+#define LRA_LRA_FLT_COEF1_REG_FLT_COEF_00_Pos (0UL) /*!< FLT_COEF_00 (Bit 0) */
+#define LRA_LRA_FLT_COEF1_REG_FLT_COEF_00_Msk (0xffffUL) /*!< FLT_COEF_00 (Bitfield-Mask: 0xffff) */
+/* =================================================== LRA_FLT_COEF2_REG =================================================== */
+#define LRA_LRA_FLT_COEF2_REG_FLT_COEF_10_Pos (16UL) /*!< FLT_COEF_10 (Bit 16) */
+#define LRA_LRA_FLT_COEF2_REG_FLT_COEF_10_Msk (0xffff0000UL) /*!< FLT_COEF_10 (Bitfield-Mask: 0xffff) */
+#define LRA_LRA_FLT_COEF2_REG_FLT_COEF_02_Pos (0UL) /*!< FLT_COEF_02 (Bit 0) */
+#define LRA_LRA_FLT_COEF2_REG_FLT_COEF_02_Msk (0xffffUL) /*!< FLT_COEF_02 (Bitfield-Mask: 0xffff) */
+/* =================================================== LRA_FLT_COEF3_REG =================================================== */
+#define LRA_LRA_FLT_COEF3_REG_FLT_COEF_12_Pos (16UL) /*!< FLT_COEF_12 (Bit 16) */
+#define LRA_LRA_FLT_COEF3_REG_FLT_COEF_12_Msk (0xffff0000UL) /*!< FLT_COEF_12 (Bitfield-Mask: 0xffff) */
+#define LRA_LRA_FLT_COEF3_REG_FLT_COEF_11_Pos (0UL) /*!< FLT_COEF_11 (Bit 0) */
+#define LRA_LRA_FLT_COEF3_REG_FLT_COEF_11_Msk (0xffffUL) /*!< FLT_COEF_11 (Bitfield-Mask: 0xffff) */
+/* =================================================== LRA_FLT_SMP1_REG ==================================================== */
+#define LRA_LRA_FLT_SMP1_REG_LRA_SMP_2_Pos (16UL) /*!< LRA_SMP_2 (Bit 16) */
+#define LRA_LRA_FLT_SMP1_REG_LRA_SMP_2_Msk (0xffff0000UL) /*!< LRA_SMP_2 (Bitfield-Mask: 0xffff) */
+#define LRA_LRA_FLT_SMP1_REG_LRA_SMP_1_Pos (0UL) /*!< LRA_SMP_1 (Bit 0) */
+#define LRA_LRA_FLT_SMP1_REG_LRA_SMP_1_Msk (0xffffUL) /*!< LRA_SMP_1 (Bitfield-Mask: 0xffff) */
+/* =================================================== LRA_FLT_SMP2_REG ==================================================== */
+#define LRA_LRA_FLT_SMP2_REG_LRA_SMP_4_Pos (16UL) /*!< LRA_SMP_4 (Bit 16) */
+#define LRA_LRA_FLT_SMP2_REG_LRA_SMP_4_Msk (0xffff0000UL) /*!< LRA_SMP_4 (Bitfield-Mask: 0xffff) */
+#define LRA_LRA_FLT_SMP2_REG_LRA_SMP_3_Pos (0UL) /*!< LRA_SMP_3 (Bit 0) */
+#define LRA_LRA_FLT_SMP2_REG_LRA_SMP_3_Msk (0xffffUL) /*!< LRA_SMP_3 (Bitfield-Mask: 0xffff) */
+/* =================================================== LRA_FLT_SMP3_REG ==================================================== */
+#define LRA_LRA_FLT_SMP3_REG_LRA_SMP_6_Pos (16UL) /*!< LRA_SMP_6 (Bit 16) */
+#define LRA_LRA_FLT_SMP3_REG_LRA_SMP_6_Msk (0xffff0000UL) /*!< LRA_SMP_6 (Bitfield-Mask: 0xffff) */
+#define LRA_LRA_FLT_SMP3_REG_LRA_SMP_5_Pos (0UL) /*!< LRA_SMP_5 (Bit 0) */
+#define LRA_LRA_FLT_SMP3_REG_LRA_SMP_5_Msk (0xffffUL) /*!< LRA_SMP_5 (Bitfield-Mask: 0xffff) */
+/* =================================================== LRA_FLT_SMP4_REG ==================================================== */
+#define LRA_LRA_FLT_SMP4_REG_LRA_SMP_8_Pos (16UL) /*!< LRA_SMP_8 (Bit 16) */
+#define LRA_LRA_FLT_SMP4_REG_LRA_SMP_8_Msk (0xffff0000UL) /*!< LRA_SMP_8 (Bitfield-Mask: 0xffff) */
+#define LRA_LRA_FLT_SMP4_REG_LRA_SMP_7_Pos (0UL) /*!< LRA_SMP_7 (Bit 0) */
+#define LRA_LRA_FLT_SMP4_REG_LRA_SMP_7_Msk (0xffffUL) /*!< LRA_SMP_7 (Bitfield-Mask: 0xffff) */
+/* =================================================== LRA_FLT_SMP5_REG ==================================================== */
+#define LRA_LRA_FLT_SMP5_REG_LRA_SMP_10_Pos (16UL) /*!< LRA_SMP_10 (Bit 16) */
+#define LRA_LRA_FLT_SMP5_REG_LRA_SMP_10_Msk (0xffff0000UL) /*!< LRA_SMP_10 (Bitfield-Mask: 0xffff) */
+#define LRA_LRA_FLT_SMP5_REG_LRA_SMP_9_Pos (0UL) /*!< LRA_SMP_9 (Bit 0) */
+#define LRA_LRA_FLT_SMP5_REG_LRA_SMP_9_Msk (0xffffUL) /*!< LRA_SMP_9 (Bitfield-Mask: 0xffff) */
+/* =================================================== LRA_FLT_SMP6_REG ==================================================== */
+#define LRA_LRA_FLT_SMP6_REG_LRA_SMP_12_Pos (16UL) /*!< LRA_SMP_12 (Bit 16) */
+#define LRA_LRA_FLT_SMP6_REG_LRA_SMP_12_Msk (0xffff0000UL) /*!< LRA_SMP_12 (Bitfield-Mask: 0xffff) */
+#define LRA_LRA_FLT_SMP6_REG_LRA_SMP_11_Pos (0UL) /*!< LRA_SMP_11 (Bit 0) */
+#define LRA_LRA_FLT_SMP6_REG_LRA_SMP_11_Msk (0xffffUL) /*!< LRA_SMP_11 (Bitfield-Mask: 0xffff) */
+/* =================================================== LRA_FLT_SMP7_REG ==================================================== */
+#define LRA_LRA_FLT_SMP7_REG_LRA_SMP_14_Pos (16UL) /*!< LRA_SMP_14 (Bit 16) */
+#define LRA_LRA_FLT_SMP7_REG_LRA_SMP_14_Msk (0xffff0000UL) /*!< LRA_SMP_14 (Bitfield-Mask: 0xffff) */
+#define LRA_LRA_FLT_SMP7_REG_LRA_SMP_13_Pos (0UL) /*!< LRA_SMP_13 (Bit 0) */
+#define LRA_LRA_FLT_SMP7_REG_LRA_SMP_13_Msk (0xffffUL) /*!< LRA_SMP_13 (Bitfield-Mask: 0xffff) */
+/* =================================================== LRA_FLT_SMP8_REG ==================================================== */
+#define LRA_LRA_FLT_SMP8_REG_LRA_SMP_16_Pos (16UL) /*!< LRA_SMP_16 (Bit 16) */
+#define LRA_LRA_FLT_SMP8_REG_LRA_SMP_16_Msk (0xffff0000UL) /*!< LRA_SMP_16 (Bitfield-Mask: 0xffff) */
+#define LRA_LRA_FLT_SMP8_REG_LRA_SMP_15_Pos (0UL) /*!< LRA_SMP_15 (Bit 0) */
+#define LRA_LRA_FLT_SMP8_REG_LRA_SMP_15_Msk (0xffffUL) /*!< LRA_SMP_15 (Bitfield-Mask: 0xffff) */
+/* ====================================================== LRA_LDO_REG ====================================================== */
+#define LRA_LRA_LDO_REG_LDO_OK_Pos (31UL) /*!< LDO_OK (Bit 31) */
+#define LRA_LRA_LDO_REG_LDO_OK_Msk (0x80000000UL) /*!< LDO_OK (Bitfield-Mask: 0x01) */
+#define LRA_LRA_LDO_REG_LDO_TST_Pos (1UL) /*!< LDO_TST (Bit 1) */
+#define LRA_LRA_LDO_REG_LDO_TST_Msk (0x2UL) /*!< LDO_TST (Bitfield-Mask: 0x01) */
+#define LRA_LRA_LDO_REG_LDO_VREF_HOLD_Pos (0UL) /*!< LDO_VREF_HOLD (Bit 0) */
+#define LRA_LRA_LDO_REG_LDO_VREF_HOLD_Msk (0x1UL) /*!< LDO_VREF_HOLD (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ MEMCTRL ================ */
+/* =========================================================================================================================== */
+
+/* ==================================================== BUSY_RESET_REG ===================================================== */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Pos (30UL) /*!< BUSY_SPARE (Bit 30) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Msk (0xc0000000UL) /*!< BUSY_SPARE (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_MOTOR_Pos (28UL) /*!< BUSY_MOTOR (Bit 28) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_MOTOR_Msk (0x30000000UL) /*!< BUSY_MOTOR (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER2_Pos (26UL) /*!< BUSY_TIMER2 (Bit 26) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER2_Msk (0xc000000UL) /*!< BUSY_TIMER2 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER_Pos (24UL) /*!< BUSY_TIMER (Bit 24) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER_Msk (0x3000000UL) /*!< BUSY_TIMER (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_UART3_Pos (22UL) /*!< BUSY_UART3 (Bit 22) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_UART3_Msk (0xc00000UL) /*!< BUSY_UART3 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_GPADC_Pos (20UL) /*!< BUSY_GPADC (Bit 20) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_GPADC_Msk (0x300000UL) /*!< BUSY_GPADC (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_PDM_Pos (18UL) /*!< BUSY_PDM (Bit 18) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_PDM_Msk (0xc0000UL) /*!< BUSY_PDM (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_SRC_Pos (16UL) /*!< BUSY_SRC (Bit 16) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_SRC_Msk (0x30000UL) /*!< BUSY_SRC (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_PCM_Pos (14UL) /*!< BUSY_PCM (Bit 14) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_PCM_Msk (0xc000UL) /*!< BUSY_PCM (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_SDADC_Pos (12UL) /*!< BUSY_SDADC (Bit 12) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_SDADC_Msk (0x3000UL) /*!< BUSY_SDADC (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_I2C2_Pos (10UL) /*!< BUSY_I2C2 (Bit 10) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_I2C2_Msk (0xc00UL) /*!< BUSY_I2C2 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_I2C_Pos (8UL) /*!< BUSY_I2C (Bit 8) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_I2C_Msk (0x300UL) /*!< BUSY_I2C (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_SPI2_Pos (6UL) /*!< BUSY_SPI2 (Bit 6) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_SPI2_Msk (0xc0UL) /*!< BUSY_SPI2 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_SPI_Pos (4UL) /*!< BUSY_SPI (Bit 4) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_SPI_Msk (0x30UL) /*!< BUSY_SPI (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_UART2_Pos (2UL) /*!< BUSY_UART2 (Bit 2) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_UART2_Msk (0xcUL) /*!< BUSY_UART2 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_UART_Pos (0UL) /*!< BUSY_UART (Bit 0) */
+#define MEMCTRL_BUSY_RESET_REG_BUSY_UART_Msk (0x3UL) /*!< BUSY_UART (Bitfield-Mask: 0x03) */
+/* ===================================================== BUSY_SET_REG ====================================================== */
+#define MEMCTRL_BUSY_SET_REG_BUSY_SPARE_Pos (30UL) /*!< BUSY_SPARE (Bit 30) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_SPARE_Msk (0xc0000000UL) /*!< BUSY_SPARE (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_MOTOR_Pos (28UL) /*!< BUSY_MOTOR (Bit 28) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_MOTOR_Msk (0x30000000UL) /*!< BUSY_MOTOR (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER2_Pos (26UL) /*!< BUSY_TIMER2 (Bit 26) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER2_Msk (0xc000000UL) /*!< BUSY_TIMER2 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER_Pos (24UL) /*!< BUSY_TIMER (Bit 24) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER_Msk (0x3000000UL) /*!< BUSY_TIMER (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_UART3_Pos (22UL) /*!< BUSY_UART3 (Bit 22) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_UART3_Msk (0xc00000UL) /*!< BUSY_UART3 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_GPADC_Pos (20UL) /*!< BUSY_GPADC (Bit 20) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_GPADC_Msk (0x300000UL) /*!< BUSY_GPADC (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_PDM_Pos (18UL) /*!< BUSY_PDM (Bit 18) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_PDM_Msk (0xc0000UL) /*!< BUSY_PDM (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_SRC_Pos (16UL) /*!< BUSY_SRC (Bit 16) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_SRC_Msk (0x30000UL) /*!< BUSY_SRC (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_PCM_Pos (14UL) /*!< BUSY_PCM (Bit 14) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_PCM_Msk (0xc000UL) /*!< BUSY_PCM (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_SDADC_Pos (12UL) /*!< BUSY_SDADC (Bit 12) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_SDADC_Msk (0x3000UL) /*!< BUSY_SDADC (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_I2C2_Pos (10UL) /*!< BUSY_I2C2 (Bit 10) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_I2C2_Msk (0xc00UL) /*!< BUSY_I2C2 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_I2C_Pos (8UL) /*!< BUSY_I2C (Bit 8) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_I2C_Msk (0x300UL) /*!< BUSY_I2C (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_SPI2_Pos (6UL) /*!< BUSY_SPI2 (Bit 6) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_SPI2_Msk (0xc0UL) /*!< BUSY_SPI2 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_SPI_Pos (4UL) /*!< BUSY_SPI (Bit 4) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_SPI_Msk (0x30UL) /*!< BUSY_SPI (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_UART2_Pos (2UL) /*!< BUSY_UART2 (Bit 2) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_UART2_Msk (0xcUL) /*!< BUSY_UART2 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_UART_Pos (0UL) /*!< BUSY_UART (Bit 0) */
+#define MEMCTRL_BUSY_SET_REG_BUSY_UART_Msk (0x3UL) /*!< BUSY_UART (Bitfield-Mask: 0x03) */
+/* ===================================================== BUSY_STAT_REG ===================================================== */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_SPARE_Pos (30UL) /*!< BUSY_SPARE (Bit 30) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_SPARE_Msk (0xc0000000UL) /*!< BUSY_SPARE (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_MOTOR_Pos (28UL) /*!< BUSY_MOTOR (Bit 28) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_MOTOR_Msk (0x30000000UL) /*!< BUSY_MOTOR (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER2_Pos (26UL) /*!< BUSY_TIMER2 (Bit 26) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER2_Msk (0xc000000UL) /*!< BUSY_TIMER2 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER_Pos (24UL) /*!< BUSY_TIMER (Bit 24) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER_Msk (0x3000000UL) /*!< BUSY_TIMER (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_UART3_Pos (22UL) /*!< BUSY_UART3 (Bit 22) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_UART3_Msk (0xc00000UL) /*!< BUSY_UART3 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_GPADC_Pos (20UL) /*!< BUSY_GPADC (Bit 20) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_GPADC_Msk (0x300000UL) /*!< BUSY_GPADC (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_PDM_Pos (18UL) /*!< BUSY_PDM (Bit 18) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_PDM_Msk (0xc0000UL) /*!< BUSY_PDM (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_SRC_Pos (16UL) /*!< BUSY_SRC (Bit 16) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_SRC_Msk (0x30000UL) /*!< BUSY_SRC (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_PCM_Pos (14UL) /*!< BUSY_PCM (Bit 14) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_PCM_Msk (0xc000UL) /*!< BUSY_PCM (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_SDADC_Pos (12UL) /*!< BUSY_SDADC (Bit 12) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_SDADC_Msk (0x3000UL) /*!< BUSY_SDADC (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_I2C2_Pos (10UL) /*!< BUSY_I2C2 (Bit 10) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_I2C2_Msk (0xc00UL) /*!< BUSY_I2C2 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_I2C_Pos (8UL) /*!< BUSY_I2C (Bit 8) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_I2C_Msk (0x300UL) /*!< BUSY_I2C (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_SPI2_Pos (6UL) /*!< BUSY_SPI2 (Bit 6) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_SPI2_Msk (0xc0UL) /*!< BUSY_SPI2 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_SPI_Pos (4UL) /*!< BUSY_SPI (Bit 4) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_SPI_Msk (0x30UL) /*!< BUSY_SPI (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_UART2_Pos (2UL) /*!< BUSY_UART2 (Bit 2) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_UART2_Msk (0xcUL) /*!< BUSY_UART2 (Bitfield-Mask: 0x03) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_UART_Pos (0UL) /*!< BUSY_UART (Bit 0) */
+#define MEMCTRL_BUSY_STAT_REG_BUSY_UART_Msk (0x3UL) /*!< BUSY_UART (Bitfield-Mask: 0x03) */
+/* =================================================== CMI_CODE_BASE_REG =================================================== */
+#define MEMCTRL_CMI_CODE_BASE_REG_CMI_CODE_BASE_ADDR_Pos (10UL) /*!< CMI_CODE_BASE_ADDR (Bit 10) */
+#define MEMCTRL_CMI_CODE_BASE_REG_CMI_CODE_BASE_ADDR_Msk (0x7fc00UL) /*!< CMI_CODE_BASE_ADDR (Bitfield-Mask: 0x1ff) */
+/* =================================================== CMI_DATA_BASE_REG =================================================== */
+#define MEMCTRL_CMI_DATA_BASE_REG_CMI_DATA_BASE_ADDR_Pos (2UL) /*!< CMI_DATA_BASE_ADDR (Bit 2) */
+#define MEMCTRL_CMI_DATA_BASE_REG_CMI_DATA_BASE_ADDR_Msk (0x7fffcUL) /*!< CMI_DATA_BASE_ADDR (Bitfield-Mask: 0x1ffff) */
+/* ====================================================== CMI_END_REG ====================================================== */
+#define MEMCTRL_CMI_END_REG_CMI_END_ADDR_Pos (10UL) /*!< CMI_END_ADDR (Bit 10) */
+#define MEMCTRL_CMI_END_REG_CMI_END_ADDR_Msk (0x7fc00UL) /*!< CMI_END_ADDR (Bitfield-Mask: 0x1ff) */
+/* ================================================== CMI_SHARED_BASE_REG ================================================== */
+#define MEMCTRL_CMI_SHARED_BASE_REG_CMI_SHARED_BASE_ADDR_Pos (10UL) /*!< CMI_SHARED_BASE_ADDR (Bit 10) */
+#define MEMCTRL_CMI_SHARED_BASE_REG_CMI_SHARED_BASE_ADDR_Msk (0x7fc00UL) /*!< CMI_SHARED_BASE_ADDR (Bitfield-Mask: 0x1ff) */
+/* ===================================================== MEM_PRIO_REG ====================================================== */
+#define MEMCTRL_MEM_PRIO_REG_AHB_PRIO_Pos (4UL) /*!< AHB_PRIO (Bit 4) */
+#define MEMCTRL_MEM_PRIO_REG_AHB_PRIO_Msk (0x30UL) /*!< AHB_PRIO (Bitfield-Mask: 0x03) */
+#define MEMCTRL_MEM_PRIO_REG_AHB2_PRIO_Pos (2UL) /*!< AHB2_PRIO (Bit 2) */
+#define MEMCTRL_MEM_PRIO_REG_AHB2_PRIO_Msk (0xcUL) /*!< AHB2_PRIO (Bitfield-Mask: 0x03) */
+#define MEMCTRL_MEM_PRIO_REG_SNC_PRIO_Pos (0UL) /*!< SNC_PRIO (Bit 0) */
+#define MEMCTRL_MEM_PRIO_REG_SNC_PRIO_Msk (0x3UL) /*!< SNC_PRIO (Bitfield-Mask: 0x03) */
+/* ===================================================== MEM_STALL_REG ===================================================== */
+#define MEMCTRL_MEM_STALL_REG_AHB_MAX_STALL_Pos (8UL) /*!< AHB_MAX_STALL (Bit 8) */
+#define MEMCTRL_MEM_STALL_REG_AHB_MAX_STALL_Msk (0xf00UL) /*!< AHB_MAX_STALL (Bitfield-Mask: 0x0f) */
+#define MEMCTRL_MEM_STALL_REG_AHB2_MAX_STALL_Pos (4UL) /*!< AHB2_MAX_STALL (Bit 4) */
+#define MEMCTRL_MEM_STALL_REG_AHB2_MAX_STALL_Msk (0xf0UL) /*!< AHB2_MAX_STALL (Bitfield-Mask: 0x0f) */
+#define MEMCTRL_MEM_STALL_REG_SNC_MAX_STALL_Pos (0UL) /*!< SNC_MAX_STALL (Bit 0) */
+#define MEMCTRL_MEM_STALL_REG_SNC_MAX_STALL_Msk (0xfUL) /*!< SNC_MAX_STALL (Bitfield-Mask: 0x0f) */
+/* ==================================================== MEM_STATUS2_REG ==================================================== */
+#define MEMCTRL_MEM_STATUS2_REG_RAM8_OFF_BUT_ACCESS_Pos (7UL) /*!< RAM8_OFF_BUT_ACCESS (Bit 7) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM8_OFF_BUT_ACCESS_Msk (0x80UL) /*!< RAM8_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM7_OFF_BUT_ACCESS_Pos (6UL) /*!< RAM7_OFF_BUT_ACCESS (Bit 6) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM7_OFF_BUT_ACCESS_Msk (0x40UL) /*!< RAM7_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM6_OFF_BUT_ACCESS_Pos (5UL) /*!< RAM6_OFF_BUT_ACCESS (Bit 5) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM6_OFF_BUT_ACCESS_Msk (0x20UL) /*!< RAM6_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM5_OFF_BUT_ACCESS_Pos (4UL) /*!< RAM5_OFF_BUT_ACCESS (Bit 4) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM5_OFF_BUT_ACCESS_Msk (0x10UL) /*!< RAM5_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM4_OFF_BUT_ACCESS_Pos (3UL) /*!< RAM4_OFF_BUT_ACCESS (Bit 3) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM4_OFF_BUT_ACCESS_Msk (0x8UL) /*!< RAM4_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM3_OFF_BUT_ACCESS_Pos (2UL) /*!< RAM3_OFF_BUT_ACCESS (Bit 2) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM3_OFF_BUT_ACCESS_Msk (0x4UL) /*!< RAM3_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM2_OFF_BUT_ACCESS_Pos (1UL) /*!< RAM2_OFF_BUT_ACCESS (Bit 1) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM2_OFF_BUT_ACCESS_Msk (0x2UL) /*!< RAM2_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM1_OFF_BUT_ACCESS_Pos (0UL) /*!< RAM1_OFF_BUT_ACCESS (Bit 0) */
+#define MEMCTRL_MEM_STATUS2_REG_RAM1_OFF_BUT_ACCESS_Msk (0x1UL) /*!< RAM1_OFF_BUT_ACCESS (Bitfield-Mask: 0x01) */
+/* ==================================================== MEM_STATUS_REG ===================================================== */
+#define MEMCTRL_MEM_STATUS_REG_CMI_CLEAR_READY_Pos (13UL) /*!< CMI_CLEAR_READY (Bit 13) */
+#define MEMCTRL_MEM_STATUS_REG_CMI_CLEAR_READY_Msk (0x2000UL) /*!< CMI_CLEAR_READY (Bitfield-Mask: 0x01) */
+#define MEMCTRL_MEM_STATUS_REG_CMI_NOT_READY_Pos (12UL) /*!< CMI_NOT_READY (Bit 12) */
+#define MEMCTRL_MEM_STATUS_REG_CMI_NOT_READY_Msk (0x1000UL) /*!< CMI_NOT_READY (Bitfield-Mask: 0x01) */
+#define MEMCTRL_MEM_STATUS_REG_AHB2_WR_BUFF_CNT_Pos (8UL) /*!< AHB2_WR_BUFF_CNT (Bit 8) */
+#define MEMCTRL_MEM_STATUS_REG_AHB2_WR_BUFF_CNT_Msk (0xf00UL) /*!< AHB2_WR_BUFF_CNT (Bitfield-Mask: 0x0f) */
+#define MEMCTRL_MEM_STATUS_REG_AHB_WR_BUFF_CNT_Pos (4UL) /*!< AHB_WR_BUFF_CNT (Bit 4) */
+#define MEMCTRL_MEM_STATUS_REG_AHB_WR_BUFF_CNT_Msk (0xf0UL) /*!< AHB_WR_BUFF_CNT (Bitfield-Mask: 0x0f) */
+#define MEMCTRL_MEM_STATUS_REG_AHB2_CLR_WR_BUFF_Pos (3UL) /*!< AHB2_CLR_WR_BUFF (Bit 3) */
+#define MEMCTRL_MEM_STATUS_REG_AHB2_CLR_WR_BUFF_Msk (0x8UL) /*!< AHB2_CLR_WR_BUFF (Bitfield-Mask: 0x01) */
+#define MEMCTRL_MEM_STATUS_REG_AHB_CLR_WR_BUFF_Pos (2UL) /*!< AHB_CLR_WR_BUFF (Bit 2) */
+#define MEMCTRL_MEM_STATUS_REG_AHB_CLR_WR_BUFF_Msk (0x4UL) /*!< AHB_CLR_WR_BUFF (Bitfield-Mask: 0x01) */
+#define MEMCTRL_MEM_STATUS_REG_AHB2_WRITE_BUFF_Pos (1UL) /*!< AHB2_WRITE_BUFF (Bit 1) */
+#define MEMCTRL_MEM_STATUS_REG_AHB2_WRITE_BUFF_Msk (0x2UL) /*!< AHB2_WRITE_BUFF (Bitfield-Mask: 0x01) */
+#define MEMCTRL_MEM_STATUS_REG_AHB_WRITE_BUFF_Pos (0UL) /*!< AHB_WRITE_BUFF (Bit 0) */
+#define MEMCTRL_MEM_STATUS_REG_AHB_WRITE_BUFF_Msk (0x1UL) /*!< AHB_WRITE_BUFF (Bitfield-Mask: 0x01) */
+/* ===================================================== SNC_BASE_REG ====================================================== */
+#define MEMCTRL_SNC_BASE_REG_SNC_BASE_ADDRESS_Pos (2UL) /*!< SNC_BASE_ADDRESS (Bit 2) */
+#define MEMCTRL_SNC_BASE_REG_SNC_BASE_ADDRESS_Msk (0x7fffcUL) /*!< SNC_BASE_ADDRESS (Bitfield-Mask: 0x1ffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ OTPC ================ */
+/* =========================================================================================================================== */
+
+/* ===================================================== OTPC_MODE_REG ===================================================== */
+#define OTPC_OTPC_MODE_REG_OTPC_MODE_PRG_SEL_Pos (6UL) /*!< OTPC_MODE_PRG_SEL (Bit 6) */
+#define OTPC_OTPC_MODE_REG_OTPC_MODE_PRG_SEL_Msk (0xc0UL) /*!< OTPC_MODE_PRG_SEL (Bitfield-Mask: 0x03) */
+#define OTPC_OTPC_MODE_REG_OTPC_MODE_HT_MARG_EN_Pos (5UL) /*!< OTPC_MODE_HT_MARG_EN (Bit 5) */
+#define OTPC_OTPC_MODE_REG_OTPC_MODE_HT_MARG_EN_Msk (0x20UL) /*!< OTPC_MODE_HT_MARG_EN (Bitfield-Mask: 0x01) */
+#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_TST_ROW_Pos (4UL) /*!< OTPC_MODE_USE_TST_ROW (Bit 4) */
+#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_TST_ROW_Msk (0x10UL) /*!< OTPC_MODE_USE_TST_ROW (Bitfield-Mask: 0x01) */
+#define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Pos (0UL) /*!< OTPC_MODE_MODE (Bit 0) */
+#define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Msk (0x7UL) /*!< OTPC_MODE_MODE (Bitfield-Mask: 0x07) */
+/* ==================================================== OTPC_PADDR_REG ===================================================== */
+#define OTPC_OTPC_PADDR_REG_OTPC_PADDR_Pos (0UL) /*!< OTPC_PADDR (Bit 0) */
+#define OTPC_OTPC_PADDR_REG_OTPC_PADDR_Msk (0x3ffUL) /*!< OTPC_PADDR (Bitfield-Mask: 0x3ff) */
+/* ==================================================== OTPC_PWORD_REG ===================================================== */
+#define OTPC_OTPC_PWORD_REG_OTPC_PWORD_Pos (0UL) /*!< OTPC_PWORD (Bit 0) */
+#define OTPC_OTPC_PWORD_REG_OTPC_PWORD_Msk (0xffffffffUL) /*!< OTPC_PWORD (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== OTPC_STAT_REG ===================================================== */
+#define OTPC_OTPC_STAT_REG_OTPC_STAT_MRDY_Pos (2UL) /*!< OTPC_STAT_MRDY (Bit 2) */
+#define OTPC_OTPC_STAT_REG_OTPC_STAT_MRDY_Msk (0x4UL) /*!< OTPC_STAT_MRDY (Bitfield-Mask: 0x01) */
+#define OTPC_OTPC_STAT_REG_OTPC_STAT_PBUF_EMPTY_Pos (1UL) /*!< OTPC_STAT_PBUF_EMPTY (Bit 1) */
+#define OTPC_OTPC_STAT_REG_OTPC_STAT_PBUF_EMPTY_Msk (0x2UL) /*!< OTPC_STAT_PBUF_EMPTY (Bitfield-Mask: 0x01) */
+#define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Pos (0UL) /*!< OTPC_STAT_PRDY (Bit 0) */
+#define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Msk (0x1UL) /*!< OTPC_STAT_PRDY (Bitfield-Mask: 0x01) */
+/* ===================================================== OTPC_TIM1_REG ===================================================== */
+#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CSP_Pos (24UL) /*!< OTPC_TIM1_US_T_CSP (Bit 24) */
+#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CSP_Msk (0x7f000000UL) /*!< OTPC_TIM1_US_T_CSP (Bitfield-Mask: 0x7f) */
+#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CS_Pos (20UL) /*!< OTPC_TIM1_US_T_CS (Bit 20) */
+#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_CS_Msk (0xf00000UL) /*!< OTPC_TIM1_US_T_CS (Bitfield-Mask: 0x0f) */
+#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_PL_Pos (16UL) /*!< OTPC_TIM1_US_T_PL (Bit 16) */
+#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_US_T_PL_Msk (0xf0000UL) /*!< OTPC_TIM1_US_T_PL (Bitfield-Mask: 0x0f) */
+#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_RD_Pos (12UL) /*!< OTPC_TIM1_CC_T_RD (Bit 12) */
+#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_RD_Msk (0x7000UL) /*!< OTPC_TIM1_CC_T_RD (Bitfield-Mask: 0x07) */
+#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_20NS_Pos (8UL) /*!< OTPC_TIM1_CC_T_20NS (Bit 8) */
+#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_20NS_Msk (0x300UL) /*!< OTPC_TIM1_CC_T_20NS (Bitfield-Mask: 0x03) */
+#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos (0UL) /*!< OTPC_TIM1_CC_T_1US (Bit 0) */
+#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Msk (0x7fUL) /*!< OTPC_TIM1_CC_T_1US (Bitfield-Mask: 0x7f) */
+/* ===================================================== OTPC_TIM2_REG ===================================================== */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_ADD_CC_EN_Pos (31UL) /*!< OTPC_TIM2_US_ADD_CC_EN (Bit 31) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_ADD_CC_EN_Msk (0x80000000UL) /*!< OTPC_TIM2_US_ADD_CC_EN (Bitfield-Mask: 0x01) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_SAS_Pos (29UL) /*!< OTPC_TIM2_US_T_SAS (Bit 29) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_SAS_Msk (0x60000000UL) /*!< OTPC_TIM2_US_T_SAS (Bitfield-Mask: 0x03) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPH_Pos (24UL) /*!< OTPC_TIM2_US_T_PPH (Bit 24) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPH_Msk (0x1f000000UL) /*!< OTPC_TIM2_US_T_PPH (Bitfield-Mask: 0x1f) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_VDS_Pos (21UL) /*!< OTPC_TIM2_US_T_VDS (Bit 21) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_VDS_Msk (0xe00000UL) /*!< OTPC_TIM2_US_T_VDS (Bitfield-Mask: 0x07) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPS_Pos (16UL) /*!< OTPC_TIM2_US_T_PPS (Bit 16) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPS_Msk (0x1f0000UL) /*!< OTPC_TIM2_US_T_PPS (Bitfield-Mask: 0x1f) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPR_Pos (8UL) /*!< OTPC_TIM2_US_T_PPR (Bit 8) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PPR_Msk (0x7f00UL) /*!< OTPC_TIM2_US_T_PPR (Bitfield-Mask: 0x7f) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PWI_Pos (5UL) /*!< OTPC_TIM2_US_T_PWI (Bit 5) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PWI_Msk (0xe0UL) /*!< OTPC_TIM2_US_T_PWI (Bitfield-Mask: 0x07) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PW_Pos (0UL) /*!< OTPC_TIM2_US_T_PW (Bit 0) */
+#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_US_T_PW_Msk (0x1fUL) /*!< OTPC_TIM2_US_T_PW (Bitfield-Mask: 0x1f) */
+
+
+/* =========================================================================================================================== */
+/* ================ PDC ================ */
+/* =========================================================================================================================== */
+
+/* ================================================== PDC_ACKNOWLEDGE_REG ================================================== */
+#define PDC_PDC_ACKNOWLEDGE_REG_PDC_ACKNOWLEDGE_Pos (0UL) /*!< PDC_ACKNOWLEDGE (Bit 0) */
+#define PDC_PDC_ACKNOWLEDGE_REG_PDC_ACKNOWLEDGE_Msk (0x1fUL) /*!< PDC_ACKNOWLEDGE (Bitfield-Mask: 0x1f) */
+/* ===================================================== PDC_CTRL0_REG ===================================================== */
+#define PDC_PDC_CTRL0_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL0_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL0_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL0_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL0_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL0_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL0_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL0_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL0_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL0_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL0_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL0_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL0_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL0_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ==================================================== PDC_CTRL10_REG ===================================================== */
+#define PDC_PDC_CTRL10_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL10_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL10_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL10_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL10_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL10_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL10_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL10_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL10_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL10_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL10_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL10_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL10_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL10_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ==================================================== PDC_CTRL11_REG ===================================================== */
+#define PDC_PDC_CTRL11_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL11_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL11_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL11_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL11_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL11_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL11_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL11_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL11_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL11_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL11_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL11_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL11_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL11_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ==================================================== PDC_CTRL12_REG ===================================================== */
+#define PDC_PDC_CTRL12_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL12_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL12_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL12_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL12_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL12_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL12_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL12_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL12_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL12_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL12_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL12_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL12_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL12_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ==================================================== PDC_CTRL13_REG ===================================================== */
+#define PDC_PDC_CTRL13_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL13_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL13_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL13_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL13_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL13_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL13_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL13_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL13_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL13_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL13_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL13_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL13_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL13_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ==================================================== PDC_CTRL14_REG ===================================================== */
+#define PDC_PDC_CTRL14_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL14_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL14_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL14_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL14_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL14_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL14_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL14_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL14_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL14_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL14_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL14_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL14_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL14_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ==================================================== PDC_CTRL15_REG ===================================================== */
+#define PDC_PDC_CTRL15_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL15_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL15_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL15_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL15_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL15_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL15_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL15_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL15_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL15_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL15_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL15_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL15_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL15_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ===================================================== PDC_CTRL1_REG ===================================================== */
+#define PDC_PDC_CTRL1_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL1_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL1_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL1_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL1_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL1_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL1_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL1_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL1_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL1_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL1_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL1_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL1_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL1_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ===================================================== PDC_CTRL2_REG ===================================================== */
+#define PDC_PDC_CTRL2_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL2_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL2_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL2_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL2_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL2_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL2_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL2_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL2_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL2_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL2_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL2_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL2_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL2_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ===================================================== PDC_CTRL3_REG ===================================================== */
+#define PDC_PDC_CTRL3_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL3_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL3_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL3_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL3_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL3_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL3_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL3_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL3_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL3_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL3_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL3_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL3_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL3_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ===================================================== PDC_CTRL4_REG ===================================================== */
+#define PDC_PDC_CTRL4_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL4_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL4_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL4_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL4_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL4_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL4_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL4_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL4_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL4_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL4_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL4_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL4_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL4_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ===================================================== PDC_CTRL5_REG ===================================================== */
+#define PDC_PDC_CTRL5_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL5_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL5_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL5_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL5_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL5_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL5_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL5_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL5_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL5_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL5_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL5_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL5_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL5_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ===================================================== PDC_CTRL6_REG ===================================================== */
+#define PDC_PDC_CTRL6_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL6_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL6_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL6_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL6_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL6_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL6_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL6_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL6_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL6_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL6_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL6_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL6_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL6_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ===================================================== PDC_CTRL7_REG ===================================================== */
+#define PDC_PDC_CTRL7_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL7_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL7_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL7_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL7_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL7_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL7_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL7_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL7_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL7_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL7_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL7_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL7_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL7_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ===================================================== PDC_CTRL8_REG ===================================================== */
+#define PDC_PDC_CTRL8_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL8_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL8_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL8_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL8_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL8_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL8_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL8_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL8_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL8_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL8_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL8_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL8_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL8_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ===================================================== PDC_CTRL9_REG ===================================================== */
+#define PDC_PDC_CTRL9_REG_PDC_MASTER_Pos (11UL) /*!< PDC_MASTER (Bit 11) */
+#define PDC_PDC_CTRL9_REG_PDC_MASTER_Msk (0x1800UL) /*!< PDC_MASTER (Bitfield-Mask: 0x03) */
+#define PDC_PDC_CTRL9_REG_EN_COM_Pos (10UL) /*!< EN_COM (Bit 10) */
+#define PDC_PDC_CTRL9_REG_EN_COM_Msk (0x400UL) /*!< EN_COM (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL9_REG_EN_PER_Pos (9UL) /*!< EN_PER (Bit 9) */
+#define PDC_PDC_CTRL9_REG_EN_PER_Msk (0x200UL) /*!< EN_PER (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL9_REG_EN_TMR_Pos (8UL) /*!< EN_TMR (Bit 8) */
+#define PDC_PDC_CTRL9_REG_EN_TMR_Msk (0x100UL) /*!< EN_TMR (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL9_REG_EN_XTAL_Pos (7UL) /*!< EN_XTAL (Bit 7) */
+#define PDC_PDC_CTRL9_REG_EN_XTAL_Msk (0x80UL) /*!< EN_XTAL (Bitfield-Mask: 0x01) */
+#define PDC_PDC_CTRL9_REG_TRIG_ID_Pos (2UL) /*!< TRIG_ID (Bit 2) */
+#define PDC_PDC_CTRL9_REG_TRIG_ID_Msk (0x7cUL) /*!< TRIG_ID (Bitfield-Mask: 0x1f) */
+#define PDC_PDC_CTRL9_REG_TRIG_SELECT_Pos (0UL) /*!< TRIG_SELECT (Bit 0) */
+#define PDC_PDC_CTRL9_REG_TRIG_SELECT_Msk (0x3UL) /*!< TRIG_SELECT (Bitfield-Mask: 0x03) */
+/* ================================================= PDC_PENDING_CM33_REG ================================================== */
+#define PDC_PDC_PENDING_CM33_REG_PDC_PENDING_Pos (0UL) /*!< PDC_PENDING (Bit 0) */
+#define PDC_PDC_PENDING_CM33_REG_PDC_PENDING_Msk (0xffffUL) /*!< PDC_PENDING (Bitfield-Mask: 0xffff) */
+/* ================================================= PDC_PENDING_CMAC_REG ================================================== */
+#define PDC_PDC_PENDING_CMAC_REG_PDC_PENDING_Pos (0UL) /*!< PDC_PENDING (Bit 0) */
+#define PDC_PDC_PENDING_CMAC_REG_PDC_PENDING_Msk (0xffffUL) /*!< PDC_PENDING (Bitfield-Mask: 0xffff) */
+/* ==================================================== PDC_PENDING_REG ==================================================== */
+#define PDC_PDC_PENDING_REG_PDC_PENDING_Pos (0UL) /*!< PDC_PENDING (Bit 0) */
+#define PDC_PDC_PENDING_REG_PDC_PENDING_Msk (0xffffUL) /*!< PDC_PENDING (Bitfield-Mask: 0xffff) */
+/* ================================================== PDC_PENDING_SNC_REG ================================================== */
+#define PDC_PDC_PENDING_SNC_REG_PDC_PENDING_Pos (0UL) /*!< PDC_PENDING (Bit 0) */
+#define PDC_PDC_PENDING_SNC_REG_PDC_PENDING_Msk (0xffffUL) /*!< PDC_PENDING (Bitfield-Mask: 0xffff) */
+/* ================================================== PDC_SET_PENDING_REG ================================================== */
+#define PDC_PDC_SET_PENDING_REG_PDC_SET_PENDING_Pos (0UL) /*!< PDC_SET_PENDING (Bit 0) */
+#define PDC_PDC_SET_PENDING_REG_PDC_SET_PENDING_Msk (0x1fUL) /*!< PDC_SET_PENDING (Bitfield-Mask: 0x1f) */
+
+
+/* =========================================================================================================================== */
+/* ================ PWMLED ================ */
+/* =========================================================================================================================== */
+
+/* ==================================================== PWMLED_CTRL_REG ==================================================== */
+#define PWMLED_PWMLED_CTRL_REG_LED2_LOAD_SEL_Pos (11UL) /*!< LED2_LOAD_SEL (Bit 11) */
+#define PWMLED_PWMLED_CTRL_REG_LED2_LOAD_SEL_Msk (0x3800UL) /*!< LED2_LOAD_SEL (Bitfield-Mask: 0x07) */
+#define PWMLED_PWMLED_CTRL_REG_LED1_LOAD_SEL_Pos (8UL) /*!< LED1_LOAD_SEL (Bit 8) */
+#define PWMLED_PWMLED_CTRL_REG_LED1_LOAD_SEL_Msk (0x700UL) /*!< LED1_LOAD_SEL (Bitfield-Mask: 0x07) */
+#define PWMLED_PWMLED_CTRL_REG_LED2_EN_Pos (7UL) /*!< LED2_EN (Bit 7) */
+#define PWMLED_PWMLED_CTRL_REG_LED2_EN_Msk (0x80UL) /*!< LED2_EN (Bitfield-Mask: 0x01) */
+#define PWMLED_PWMLED_CTRL_REG_LED1_EN_Pos (6UL) /*!< LED1_EN (Bit 6) */
+#define PWMLED_PWMLED_CTRL_REG_LED1_EN_Msk (0x40UL) /*!< LED1_EN (Bitfield-Mask: 0x01) */
+#define PWMLED_PWMLED_CTRL_REG_LED_TRIM_Pos (2UL) /*!< LED_TRIM (Bit 2) */
+#define PWMLED_PWMLED_CTRL_REG_LED_TRIM_Msk (0x3cUL) /*!< LED_TRIM (Bitfield-Mask: 0x0f) */
+#define PWMLED_PWMLED_CTRL_REG_SW_PAUSE_EN_Pos (1UL) /*!< SW_PAUSE_EN (Bit 1) */
+#define PWMLED_PWMLED_CTRL_REG_SW_PAUSE_EN_Msk (0x2UL) /*!< SW_PAUSE_EN (Bitfield-Mask: 0x01) */
+#define PWMLED_PWMLED_CTRL_REG_PWM_ENABLE_Pos (0UL) /*!< PWM_ENABLE (Bit 0) */
+#define PWMLED_PWMLED_CTRL_REG_PWM_ENABLE_Msk (0x1UL) /*!< PWM_ENABLE (Bitfield-Mask: 0x01) */
+/* ============================================== PWMLED_DUTY_CYCLE_LED1_REG =============================================== */
+#define PWMLED_PWMLED_DUTY_CYCLE_LED1_REG_LED1_PWM_START_CYCLE_Pos (8UL) /*!< LED1_PWM_START_CYCLE (Bit 8) */
+#define PWMLED_PWMLED_DUTY_CYCLE_LED1_REG_LED1_PWM_START_CYCLE_Msk (0xff00UL) /*!< LED1_PWM_START_CYCLE (Bitfield-Mask: 0xff) */
+#define PWMLED_PWMLED_DUTY_CYCLE_LED1_REG_LED1_PWM_END_CYCLE_Pos (0UL) /*!< LED1_PWM_END_CYCLE (Bit 0) */
+#define PWMLED_PWMLED_DUTY_CYCLE_LED1_REG_LED1_PWM_END_CYCLE_Msk (0xffUL) /*!< LED1_PWM_END_CYCLE (Bitfield-Mask: 0xff) */
+/* ============================================== PWMLED_DUTY_CYCLE_LED2_REG =============================================== */
+#define PWMLED_PWMLED_DUTY_CYCLE_LED2_REG_LED2_PWM_START_CYCLE_Pos (8UL) /*!< LED2_PWM_START_CYCLE (Bit 8) */
+#define PWMLED_PWMLED_DUTY_CYCLE_LED2_REG_LED2_PWM_START_CYCLE_Msk (0xff00UL) /*!< LED2_PWM_START_CYCLE (Bitfield-Mask: 0xff) */
+#define PWMLED_PWMLED_DUTY_CYCLE_LED2_REG_LED2_PWM_END_CYCLE_Pos (0UL) /*!< LED2_PWM_END_CYCLE (Bit 0) */
+#define PWMLED_PWMLED_DUTY_CYCLE_LED2_REG_LED2_PWM_END_CYCLE_Msk (0xffUL) /*!< LED2_PWM_END_CYCLE (Bitfield-Mask: 0xff) */
+/* ================================================= PWMLED_FREQUENCY_REG ================================================== */
+#define PWMLED_PWMLED_FREQUENCY_REG_LED_PWM_FREQUENCY_Pos (0UL) /*!< LED_PWM_FREQUENCY (Bit 0) */
+#define PWMLED_PWMLED_FREQUENCY_REG_LED_PWM_FREQUENCY_Msk (0xffUL) /*!< LED_PWM_FREQUENCY (Bitfield-Mask: 0xff) */
+
+
+/* =========================================================================================================================== */
+/* ================ QSPIC ================ */
+/* =========================================================================================================================== */
+
+/* ================================================== QSPIC_BURSTBRK_REG =================================================== */
+#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos (20UL) /*!< QSPIC_SEC_HF_DS (Bit 20) */
+#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk (0x100000UL) /*!< QSPIC_SEC_HF_DS (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos (18UL) /*!< QSPIC_BRK_TX_MD (Bit 18) */
+#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk (0xc0000UL) /*!< QSPIC_BRK_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Pos (17UL) /*!< QSPIC_BRK_SZ (Bit 17) */
+#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Msk (0x20000UL) /*!< QSPIC_BRK_SZ (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Pos (16UL) /*!< QSPIC_BRK_EN (Bit 16) */
+#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Msk (0x10000UL) /*!< QSPIC_BRK_EN (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Pos (0UL) /*!< QSPIC_BRK_WRD (Bit 0) */
+#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Msk (0xffffUL) /*!< QSPIC_BRK_WRD (Bitfield-Mask: 0xffff) */
+/* ================================================== QSPIC_BURSTCMDA_REG ================================================== */
+#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos (30UL) /*!< QSPIC_DMY_TX_MD (Bit 30) */
+#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk (0xc0000000UL) /*!< QSPIC_DMY_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos (28UL) /*!< QSPIC_EXT_TX_MD (Bit 28) */
+#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk (0x30000000UL) /*!< QSPIC_EXT_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos (26UL) /*!< QSPIC_ADR_TX_MD (Bit 26) */
+#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk (0xc000000UL) /*!< QSPIC_ADR_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos (24UL) /*!< QSPIC_INST_TX_MD (Bit 24) */
+#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk (0x3000000UL) /*!< QSPIC_INST_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos (16UL) /*!< QSPIC_EXT_BYTE (Bit 16) */
+#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk (0xff0000UL) /*!< QSPIC_EXT_BYTE (Bitfield-Mask: 0xff) */
+#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Pos (8UL) /*!< QSPIC_INST_WB (Bit 8) */
+#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Msk (0xff00UL) /*!< QSPIC_INST_WB (Bitfield-Mask: 0xff) */
+#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Pos (0UL) /*!< QSPIC_INST (Bit 0) */
+#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Msk (0xffUL) /*!< QSPIC_INST (Bitfield-Mask: 0xff) */
+/* ================================================== QSPIC_BURSTCMDB_REG ================================================== */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos (15UL) /*!< QSPIC_DMY_FORCE (Bit 15) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk (0x8000UL) /*!< QSPIC_DMY_FORCE (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos (12UL) /*!< QSPIC_CS_HIGH_MIN (Bit 12) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk (0x7000UL) /*!< QSPIC_CS_HIGH_MIN (Bitfield-Mask: 0x07) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos (10UL) /*!< QSPIC_WRAP_SIZE (Bit 10) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk (0xc00UL) /*!< QSPIC_WRAP_SIZE (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos (8UL) /*!< QSPIC_WRAP_LEN (Bit 8) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk (0x300UL) /*!< QSPIC_WRAP_LEN (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos (7UL) /*!< QSPIC_WRAP_MD (Bit 7) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk (0x80UL) /*!< QSPIC_WRAP_MD (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Pos (6UL) /*!< QSPIC_INST_MD (Bit 6) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Msk (0x40UL) /*!< QSPIC_INST_MD (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos (4UL) /*!< QSPIC_DMY_NUM (Bit 4) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk (0x30UL) /*!< QSPIC_DMY_NUM (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos (3UL) /*!< QSPIC_EXT_HF_DS (Bit 3) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk (0x8UL) /*!< QSPIC_EXT_HF_DS (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos (2UL) /*!< QSPIC_EXT_BYTE_EN (Bit 2) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk (0x4UL) /*!< QSPIC_EXT_BYTE_EN (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos (0UL) /*!< QSPIC_DAT_RX_MD (Bit 0) */
+#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk (0x3UL) /*!< QSPIC_DAT_RX_MD (Bitfield-Mask: 0x03) */
+/* ================================================== QSPIC_CHCKERASE_REG ================================================== */
+#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Pos (0UL) /*!< QSPIC_CHCKERASE (Bit 0) */
+#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Msk (0xffffffffUL) /*!< QSPIC_CHCKERASE (Bitfield-Mask: 0xffffffff) */
+/* =================================================== QSPIC_CTRLBUS_REG =================================================== */
+#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Pos (4UL) /*!< QSPIC_DIS_CS (Bit 4) */
+#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk (0x10UL) /*!< QSPIC_DIS_CS (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Pos (3UL) /*!< QSPIC_EN_CS (Bit 3) */
+#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk (0x8UL) /*!< QSPIC_EN_CS (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Pos (2UL) /*!< QSPIC_SET_QUAD (Bit 2) */
+#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Msk (0x4UL) /*!< QSPIC_SET_QUAD (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Pos (1UL) /*!< QSPIC_SET_DUAL (Bit 1) */
+#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Msk (0x2UL) /*!< QSPIC_SET_DUAL (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos (0UL) /*!< QSPIC_SET_SINGLE (Bit 0) */
+#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk (0x1UL) /*!< QSPIC_SET_SINGLE (Bitfield-Mask: 0x01) */
+/* ================================================== QSPIC_CTRLMODE_REG =================================================== */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Pos (13UL) /*!< QSPIC_USE_32BA (Bit 13) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Msk (0x2000UL) /*!< QSPIC_USE_32BA (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_BUF_LIM_EN_Pos (12UL) /*!< QSPIC_BUF_LIM_EN (Bit 12) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_BUF_LIM_EN_Msk (0x1000UL) /*!< QSPIC_BUF_LIM_EN (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Pos (9UL) /*!< QSPIC_PCLK_MD (Bit 9) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Msk (0xe00UL) /*!< QSPIC_PCLK_MD (Bitfield-Mask: 0x07) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos (8UL) /*!< QSPIC_RPIPE_EN (Bit 8) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk (0x100UL) /*!< QSPIC_RPIPE_EN (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Pos (7UL) /*!< QSPIC_RXD_NEG (Bit 7) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Msk (0x80UL) /*!< QSPIC_RXD_NEG (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Pos (6UL) /*!< QSPIC_HRDY_MD (Bit 6) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Msk (0x40UL) /*!< QSPIC_HRDY_MD (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Pos (5UL) /*!< QSPIC_IO3_DAT (Bit 5) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Msk (0x20UL) /*!< QSPIC_IO3_DAT (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Pos (4UL) /*!< QSPIC_IO2_DAT (Bit 4) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Msk (0x10UL) /*!< QSPIC_IO2_DAT (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Pos (3UL) /*!< QSPIC_IO3_OEN (Bit 3) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Msk (0x8UL) /*!< QSPIC_IO3_OEN (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Pos (2UL) /*!< QSPIC_IO2_OEN (Bit 2) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk (0x4UL) /*!< QSPIC_IO2_OEN (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Pos (1UL) /*!< QSPIC_CLK_MD (Bit 1) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Msk (0x2UL) /*!< QSPIC_CLK_MD (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Pos (0UL) /*!< QSPIC_AUTO_MD (Bit 0) */
+#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk (0x1UL) /*!< QSPIC_AUTO_MD (Bitfield-Mask: 0x01) */
+/* ================================================== QSPIC_CTR_CTRL_REG =================================================== */
+#define QSPIC_QSPIC_CTR_CTRL_REG_QSPIC_CTR_EN_Pos (0UL) /*!< QSPIC_CTR_EN (Bit 0) */
+#define QSPIC_QSPIC_CTR_CTRL_REG_QSPIC_CTR_EN_Msk (0x1UL) /*!< QSPIC_CTR_EN (Bitfield-Mask: 0x01) */
+/* ================================================== QSPIC_CTR_EADDR_REG ================================================== */
+#define QSPIC_QSPIC_CTR_EADDR_REG_QSPIC_CTR_EADDR_Pos (10UL) /*!< QSPIC_CTR_EADDR (Bit 10) */
+#define QSPIC_QSPIC_CTR_EADDR_REG_QSPIC_CTR_EADDR_Msk (0xfffffc00UL) /*!< QSPIC_CTR_EADDR (Bitfield-Mask: 0x3fffff) */
+/* ================================================= QSPIC_CTR_KEY_0_3_REG ================================================= */
+#define QSPIC_QSPIC_CTR_KEY_0_3_REG_QSPIC_CTR_KEY_0_3_Pos (0UL) /*!< QSPIC_CTR_KEY_0_3 (Bit 0) */
+#define QSPIC_QSPIC_CTR_KEY_0_3_REG_QSPIC_CTR_KEY_0_3_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_0_3 (Bitfield-Mask: 0xffffffff) */
+/* ================================================ QSPIC_CTR_KEY_12_15_REG ================================================ */
+#define QSPIC_QSPIC_CTR_KEY_12_15_REG_QSPIC_CTR_KEY_12_15_Pos (0UL) /*!< QSPIC_CTR_KEY_12_15 (Bit 0) */
+#define QSPIC_QSPIC_CTR_KEY_12_15_REG_QSPIC_CTR_KEY_12_15_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_12_15 (Bitfield-Mask: 0xffffffff) */
+/* ================================================ QSPIC_CTR_KEY_16_19_REG ================================================ */
+#define QSPIC_QSPIC_CTR_KEY_16_19_REG_QSPIC_CTR_KEY_16_19_Pos (0UL) /*!< QSPIC_CTR_KEY_16_19 (Bit 0) */
+#define QSPIC_QSPIC_CTR_KEY_16_19_REG_QSPIC_CTR_KEY_16_19_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_16_19 (Bitfield-Mask: 0xffffffff) */
+/* ================================================ QSPIC_CTR_KEY_20_23_REG ================================================ */
+#define QSPIC_QSPIC_CTR_KEY_20_23_REG_QSPIC_CTR_KEY_20_23_Pos (0UL) /*!< QSPIC_CTR_KEY_20_23 (Bit 0) */
+#define QSPIC_QSPIC_CTR_KEY_20_23_REG_QSPIC_CTR_KEY_20_23_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_20_23 (Bitfield-Mask: 0xffffffff) */
+/* ================================================ QSPIC_CTR_KEY_24_27_REG ================================================ */
+#define QSPIC_QSPIC_CTR_KEY_24_27_REG_QSPIC_CTR_KEY_24_27_Pos (0UL) /*!< QSPIC_CTR_KEY_24_27 (Bit 0) */
+#define QSPIC_QSPIC_CTR_KEY_24_27_REG_QSPIC_CTR_KEY_24_27_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_24_27 (Bitfield-Mask: 0xffffffff) */
+/* ================================================ QSPIC_CTR_KEY_28_31_REG ================================================ */
+#define QSPIC_QSPIC_CTR_KEY_28_31_REG_QSPIC_CTR_KEY_28_31_Pos (0UL) /*!< QSPIC_CTR_KEY_28_31 (Bit 0) */
+#define QSPIC_QSPIC_CTR_KEY_28_31_REG_QSPIC_CTR_KEY_28_31_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_28_31 (Bitfield-Mask: 0xffffffff) */
+/* ================================================= QSPIC_CTR_KEY_4_7_REG ================================================= */
+#define QSPIC_QSPIC_CTR_KEY_4_7_REG_QSPIC_CTR_KEY_4_7_Pos (0UL) /*!< QSPIC_CTR_KEY_4_7 (Bit 0) */
+#define QSPIC_QSPIC_CTR_KEY_4_7_REG_QSPIC_CTR_KEY_4_7_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_4_7 (Bitfield-Mask: 0xffffffff) */
+/* ================================================ QSPIC_CTR_KEY_8_11_REG ================================================= */
+#define QSPIC_QSPIC_CTR_KEY_8_11_REG_QSPIC_CTR_KEY_8_11_Pos (0UL) /*!< QSPIC_CTR_KEY_8_11 (Bit 0) */
+#define QSPIC_QSPIC_CTR_KEY_8_11_REG_QSPIC_CTR_KEY_8_11_Msk (0xffffffffUL) /*!< QSPIC_CTR_KEY_8_11 (Bitfield-Mask: 0xffffffff) */
+/* ================================================ QSPIC_CTR_NONCE_0_3_REG ================================================ */
+#define QSPIC_QSPIC_CTR_NONCE_0_3_REG_QSPIC_CTR_NONCE_0_3_Pos (0UL) /*!< QSPIC_CTR_NONCE_0_3 (Bit 0) */
+#define QSPIC_QSPIC_CTR_NONCE_0_3_REG_QSPIC_CTR_NONCE_0_3_Msk (0xffffffffUL) /*!< QSPIC_CTR_NONCE_0_3 (Bitfield-Mask: 0xffffffff) */
+/* ================================================ QSPIC_CTR_NONCE_4_7_REG ================================================ */
+#define QSPIC_QSPIC_CTR_NONCE_4_7_REG_QSPIC_CTR_NONCE_4_7_Pos (0UL) /*!< QSPIC_CTR_NONCE_4_7 (Bit 0) */
+#define QSPIC_QSPIC_CTR_NONCE_4_7_REG_QSPIC_CTR_NONCE_4_7_Msk (0xffffffffUL) /*!< QSPIC_CTR_NONCE_4_7 (Bitfield-Mask: 0xffffffff) */
+/* ================================================== QSPIC_CTR_SADDR_REG ================================================== */
+#define QSPIC_QSPIC_CTR_SADDR_REG_QSPIC_CTR_SADDR_Pos (10UL) /*!< QSPIC_CTR_SADDR (Bit 10) */
+#define QSPIC_QSPIC_CTR_SADDR_REG_QSPIC_CTR_SADDR_Msk (0xfffffc00UL) /*!< QSPIC_CTR_SADDR (Bitfield-Mask: 0x3fffff) */
+/* ================================================== QSPIC_DUMMYDATA_REG ================================================== */
+#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos (0UL) /*!< QSPIC_DUMMYDATA (Bit 0) */
+#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk (0xffffffffUL) /*!< QSPIC_DUMMYDATA (Bitfield-Mask: 0xffffffff) */
+/* ================================================== QSPIC_ERASECMDA_REG ================================================== */
+#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Pos (24UL) /*!< QSPIC_RES_INST (Bit 24) */
+#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Msk (0xff000000UL) /*!< QSPIC_RES_INST (Bitfield-Mask: 0xff) */
+#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Pos (16UL) /*!< QSPIC_SUS_INST (Bit 16) */
+#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Msk (0xff0000UL) /*!< QSPIC_SUS_INST (Bitfield-Mask: 0xff) */
+#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Pos (8UL) /*!< QSPIC_WEN_INST (Bit 8) */
+#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Msk (0xff00UL) /*!< QSPIC_WEN_INST (Bitfield-Mask: 0xff) */
+#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Pos (0UL) /*!< QSPIC_ERS_INST (Bit 0) */
+#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Msk (0xffUL) /*!< QSPIC_ERS_INST (Bitfield-Mask: 0xff) */
+/* ================================================== QSPIC_ERASECMDB_REG ================================================== */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos (24UL) /*!< QSPIC_RESSUS_DLY (Bit 24) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk (0x3f000000UL) /*!< QSPIC_RESSUS_DLY (Bitfield-Mask: 0x3f) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos (16UL) /*!< QSPIC_ERSRES_HLD (Bit 16) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk (0xf0000UL) /*!< QSPIC_ERSRES_HLD (Bitfield-Mask: 0x0f) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos (10UL) /*!< QSPIC_ERS_CS_HI (Bit 10) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk (0x7c00UL) /*!< QSPIC_ERS_CS_HI (Bitfield-Mask: 0x1f) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos (8UL) /*!< QSPIC_EAD_TX_MD (Bit 8) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk (0x300UL) /*!< QSPIC_EAD_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos (6UL) /*!< QSPIC_RES_TX_MD (Bit 6) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk (0xc0UL) /*!< QSPIC_RES_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos (4UL) /*!< QSPIC_SUS_TX_MD (Bit 4) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk (0x30UL) /*!< QSPIC_SUS_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos (2UL) /*!< QSPIC_WEN_TX_MD (Bit 2) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk (0xcUL) /*!< QSPIC_WEN_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos (0UL) /*!< QSPIC_ERS_TX_MD (Bit 0) */
+#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk (0x3UL) /*!< QSPIC_ERS_TX_MD (Bitfield-Mask: 0x03) */
+/* ================================================== QSPIC_ERASECTRL_REG ================================================== */
+#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Pos (25UL) /*!< QSPIC_ERS_STATE (Bit 25) */
+#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Msk (0xe000000UL) /*!< QSPIC_ERS_STATE (Bitfield-Mask: 0x07) */
+#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Pos (24UL) /*!< QSPIC_ERASE_EN (Bit 24) */
+#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Msk (0x1000000UL) /*!< QSPIC_ERASE_EN (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos (4UL) /*!< QSPIC_ERS_ADDR (Bit 4) */
+#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk (0xfffff0UL) /*!< QSPIC_ERS_ADDR (Bitfield-Mask: 0xfffff) */
+/* ===================================================== QSPIC_GP_REG ====================================================== */
+#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Pos (3UL) /*!< QSPIC_PADS_SLEW (Bit 3) */
+#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Msk (0x18UL) /*!< QSPIC_PADS_SLEW (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Pos (1UL) /*!< QSPIC_PADS_DRV (Bit 1) */
+#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Msk (0x6UL) /*!< QSPIC_PADS_DRV (Bitfield-Mask: 0x03) */
+/* ================================================== QSPIC_READDATA_REG =================================================== */
+#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Pos (0UL) /*!< QSPIC_READDATA (Bit 0) */
+#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Msk (0xffffffffUL) /*!< QSPIC_READDATA (Bitfield-Mask: 0xffffffff) */
+/* ================================================== QSPIC_RECVDATA_REG =================================================== */
+#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Pos (0UL) /*!< QSPIC_RECVDATA (Bit 0) */
+#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Msk (0xffffffffUL) /*!< QSPIC_RECVDATA (Bitfield-Mask: 0xffffffff) */
+/* ================================================== QSPIC_STATUSCMD_REG ================================================== */
+#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos (22UL) /*!< QSPIC_STSDLY_SEL (Bit 22) */
+#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk (0x400000UL) /*!< QSPIC_STSDLY_SEL (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos (16UL) /*!< QSPIC_RESSTS_DLY (Bit 16) */
+#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk (0x3f0000UL) /*!< QSPIC_RESSTS_DLY (Bitfield-Mask: 0x3f) */
+#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos (15UL) /*!< QSPIC_BUSY_VAL (Bit 15) */
+#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk (0x8000UL) /*!< QSPIC_BUSY_VAL (Bitfield-Mask: 0x01) */
+#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Pos (12UL) /*!< QSPIC_BUSY_POS (Bit 12) */
+#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Msk (0x7000UL) /*!< QSPIC_BUSY_POS (Bitfield-Mask: 0x07) */
+#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos (10UL) /*!< QSPIC_RSTAT_RX_MD (Bit 10) */
+#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk (0xc00UL) /*!< QSPIC_RSTAT_RX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos (8UL) /*!< QSPIC_RSTAT_TX_MD (Bit 8) */
+#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk (0x300UL) /*!< QSPIC_RSTAT_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos (0UL) /*!< QSPIC_RSTAT_INST (Bit 0) */
+#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk (0xffUL) /*!< QSPIC_RSTAT_INST (Bitfield-Mask: 0xff) */
+/* =================================================== QSPIC_STATUS_REG ==================================================== */
+#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Pos (0UL) /*!< QSPIC_BUSY (Bit 0) */
+#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Msk (0x1UL) /*!< QSPIC_BUSY (Bitfield-Mask: 0x01) */
+/* =================================================== QSPIC_UCODE_START =================================================== */
+#define QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Pos (0UL) /*!< QSPIC_UCODE_X (Bit 0) */
+#define QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Msk (0xffffffffUL) /*!< QSPIC_UCODE_X (Bitfield-Mask: 0xffffffff) */
+/* ================================================== QSPIC_WRITEDATA_REG ================================================== */
+#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Pos (0UL) /*!< QSPIC_WRITEDATA (Bit 0) */
+#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Msk (0xffffffffUL) /*!< QSPIC_WRITEDATA (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ QSPIC2 ================ */
+/* =========================================================================================================================== */
+
+/* ================================================= QSPIC2_AWRITECMD_REG ================================================== */
+#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Pos (14UL) /*!< QSPIC_WR_CS_HIGH_MIN (Bit 14) */
+#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Msk (0x7c000UL) /*!< QSPIC_WR_CS_HIGH_MIN (Bitfield-Mask: 0x1f) */
+#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Pos (12UL) /*!< QSPIC_WR_DAT_TX_MD (Bit 12) */
+#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Msk (0x3000UL) /*!< QSPIC_WR_DAT_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Pos (10UL) /*!< QSPIC_WR_ADR_TX_MD (Bit 10) */
+#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Msk (0xc00UL) /*!< QSPIC_WR_ADR_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Pos (8UL) /*!< QSPIC_WR_INST_TX_MD (Bit 8) */
+#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Msk (0x300UL) /*!< QSPIC_WR_INST_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_INST_Pos (0UL) /*!< QSPIC_WR_INST (Bit 0) */
+#define QSPIC2_QSPIC2_AWRITECMD_REG_QSPIC_WR_INST_Msk (0xffUL) /*!< QSPIC_WR_INST (Bitfield-Mask: 0xff) */
+/* ================================================== QSPIC2_BURSTBRK_REG ================================================== */
+#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos (20UL) /*!< QSPIC_SEC_HF_DS (Bit 20) */
+#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk (0x100000UL) /*!< QSPIC_SEC_HF_DS (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos (18UL) /*!< QSPIC_BRK_TX_MD (Bit 18) */
+#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk (0xc0000UL) /*!< QSPIC_BRK_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_SZ_Pos (17UL) /*!< QSPIC_BRK_SZ (Bit 17) */
+#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_SZ_Msk (0x20000UL) /*!< QSPIC_BRK_SZ (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_EN_Pos (16UL) /*!< QSPIC_BRK_EN (Bit 16) */
+#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_EN_Msk (0x10000UL) /*!< QSPIC_BRK_EN (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_WRD_Pos (0UL) /*!< QSPIC_BRK_WRD (Bit 0) */
+#define QSPIC2_QSPIC2_BURSTBRK_REG_QSPIC_BRK_WRD_Msk (0xffffUL) /*!< QSPIC_BRK_WRD (Bitfield-Mask: 0xffff) */
+/* ================================================= QSPIC2_BURSTCMDA_REG ================================================== */
+#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos (30UL) /*!< QSPIC_DMY_TX_MD (Bit 30) */
+#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk (0xc0000000UL) /*!< QSPIC_DMY_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos (28UL) /*!< QSPIC_EXT_TX_MD (Bit 28) */
+#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk (0x30000000UL) /*!< QSPIC_EXT_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos (26UL) /*!< QSPIC_ADR_TX_MD (Bit 26) */
+#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk (0xc000000UL) /*!< QSPIC_ADR_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos (24UL) /*!< QSPIC_INST_TX_MD (Bit 24) */
+#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk (0x3000000UL) /*!< QSPIC_INST_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos (16UL) /*!< QSPIC_EXT_BYTE (Bit 16) */
+#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk (0xff0000UL) /*!< QSPIC_EXT_BYTE (Bitfield-Mask: 0xff) */
+#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_WB_Pos (8UL) /*!< QSPIC_INST_WB (Bit 8) */
+#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_WB_Msk (0xff00UL) /*!< QSPIC_INST_WB (Bitfield-Mask: 0xff) */
+#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_Pos (0UL) /*!< QSPIC_INST (Bit 0) */
+#define QSPIC2_QSPIC2_BURSTCMDA_REG_QSPIC_INST_Msk (0xffUL) /*!< QSPIC_INST (Bitfield-Mask: 0xff) */
+/* ================================================= QSPIC2_BURSTCMDB_REG ================================================== */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos (15UL) /*!< QSPIC_DMY_FORCE (Bit 15) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk (0x8000UL) /*!< QSPIC_DMY_FORCE (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos (12UL) /*!< QSPIC_CS_HIGH_MIN (Bit 12) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk (0x7000UL) /*!< QSPIC_CS_HIGH_MIN (Bitfield-Mask: 0x07) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos (10UL) /*!< QSPIC_WRAP_SIZE (Bit 10) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk (0xc00UL) /*!< QSPIC_WRAP_SIZE (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos (8UL) /*!< QSPIC_WRAP_LEN (Bit 8) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk (0x300UL) /*!< QSPIC_WRAP_LEN (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos (7UL) /*!< QSPIC_WRAP_MD (Bit 7) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk (0x80UL) /*!< QSPIC_WRAP_MD (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_INST_MD_Pos (6UL) /*!< QSPIC_INST_MD (Bit 6) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_INST_MD_Msk (0x40UL) /*!< QSPIC_INST_MD (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos (4UL) /*!< QSPIC_DMY_NUM (Bit 4) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk (0x30UL) /*!< QSPIC_DMY_NUM (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos (3UL) /*!< QSPIC_EXT_HF_DS (Bit 3) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk (0x8UL) /*!< QSPIC_EXT_HF_DS (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos (2UL) /*!< QSPIC_EXT_BYTE_EN (Bit 2) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk (0x4UL) /*!< QSPIC_EXT_BYTE_EN (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos (0UL) /*!< QSPIC_DAT_RX_MD (Bit 0) */
+#define QSPIC2_QSPIC2_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk (0x3UL) /*!< QSPIC_DAT_RX_MD (Bitfield-Mask: 0x03) */
+/* ================================================= QSPIC2_CHCKERASE_REG ================================================== */
+#define QSPIC2_QSPIC2_CHCKERASE_REG_QSPIC_CHCKERASE_Pos (0UL) /*!< QSPIC_CHCKERASE (Bit 0) */
+#define QSPIC2_QSPIC2_CHCKERASE_REG_QSPIC_CHCKERASE_Msk (0xffffffffUL) /*!< QSPIC_CHCKERASE (Bitfield-Mask: 0xffffffff) */
+/* ================================================== QSPIC2_CTRLBUS_REG =================================================== */
+#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_DIS_CS_Pos (4UL) /*!< QSPIC_DIS_CS (Bit 4) */
+#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_DIS_CS_Msk (0x10UL) /*!< QSPIC_DIS_CS (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_EN_CS_Pos (3UL) /*!< QSPIC_EN_CS (Bit 3) */
+#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_EN_CS_Msk (0x8UL) /*!< QSPIC_EN_CS (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_QUAD_Pos (2UL) /*!< QSPIC_SET_QUAD (Bit 2) */
+#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_QUAD_Msk (0x4UL) /*!< QSPIC_SET_QUAD (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_DUAL_Pos (1UL) /*!< QSPIC_SET_DUAL (Bit 1) */
+#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_DUAL_Msk (0x2UL) /*!< QSPIC_SET_DUAL (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos (0UL) /*!< QSPIC_SET_SINGLE (Bit 0) */
+#define QSPIC2_QSPIC2_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk (0x1UL) /*!< QSPIC_SET_SINGLE (Bitfield-Mask: 0x01) */
+/* ================================================== QSPIC2_CTRLMODE_REG ================================================== */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Pos (16UL) /*!< QSPIC_CLK_FREE_EN (Bit 16) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Msk (0x10000UL) /*!< QSPIC_CLK_FREE_EN (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CS_MD_Pos (15UL) /*!< QSPIC_CS_MD (Bit 15) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CS_MD_Msk (0x8000UL) /*!< QSPIC_CS_MD (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_SRAM_EN_Pos (14UL) /*!< QSPIC_SRAM_EN (Bit 14) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_SRAM_EN_Msk (0x4000UL) /*!< QSPIC_SRAM_EN (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_USE_32BA_Pos (13UL) /*!< QSPIC_USE_32BA (Bit 13) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_USE_32BA_Msk (0x2000UL) /*!< QSPIC_USE_32BA (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Pos (12UL) /*!< QSPIC_FORCENSEQ_EN (Bit 12) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Msk (0x1000UL) /*!< QSPIC_FORCENSEQ_EN (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_PCLK_MD_Pos (9UL) /*!< QSPIC_PCLK_MD (Bit 9) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_PCLK_MD_Msk (0xe00UL) /*!< QSPIC_PCLK_MD (Bitfield-Mask: 0x07) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos (8UL) /*!< QSPIC_RPIPE_EN (Bit 8) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk (0x100UL) /*!< QSPIC_RPIPE_EN (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_RXD_NEG_Pos (7UL) /*!< QSPIC_RXD_NEG (Bit 7) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_RXD_NEG_Msk (0x80UL) /*!< QSPIC_RXD_NEG (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_HRDY_MD_Pos (6UL) /*!< QSPIC_HRDY_MD (Bit 6) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_HRDY_MD_Msk (0x40UL) /*!< QSPIC_HRDY_MD (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO3_DAT_Pos (5UL) /*!< QSPIC_IO3_DAT (Bit 5) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO3_DAT_Msk (0x20UL) /*!< QSPIC_IO3_DAT (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO2_DAT_Pos (4UL) /*!< QSPIC_IO2_DAT (Bit 4) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO2_DAT_Msk (0x10UL) /*!< QSPIC_IO2_DAT (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO3_OEN_Pos (3UL) /*!< QSPIC_IO3_OEN (Bit 3) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO3_OEN_Msk (0x8UL) /*!< QSPIC_IO3_OEN (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO2_OEN_Pos (2UL) /*!< QSPIC_IO2_OEN (Bit 2) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_IO2_OEN_Msk (0x4UL) /*!< QSPIC_IO2_OEN (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CLK_MD_Pos (1UL) /*!< QSPIC_CLK_MD (Bit 1) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_CLK_MD_Msk (0x2UL) /*!< QSPIC_CLK_MD (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_AUTO_MD_Pos (0UL) /*!< QSPIC_AUTO_MD (Bit 0) */
+#define QSPIC2_QSPIC2_CTRLMODE_REG_QSPIC_AUTO_MD_Msk (0x1UL) /*!< QSPIC_AUTO_MD (Bitfield-Mask: 0x01) */
+/* ================================================= QSPIC2_DUMMYDATA_REG ================================================== */
+#define QSPIC2_QSPIC2_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos (0UL) /*!< QSPIC_DUMMYDATA (Bit 0) */
+#define QSPIC2_QSPIC2_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk (0xffffffffUL) /*!< QSPIC_DUMMYDATA (Bitfield-Mask: 0xffffffff) */
+/* ================================================= QSPIC2_ERASECMDA_REG ================================================== */
+#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_RES_INST_Pos (24UL) /*!< QSPIC_RES_INST (Bit 24) */
+#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_RES_INST_Msk (0xff000000UL) /*!< QSPIC_RES_INST (Bitfield-Mask: 0xff) */
+#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_SUS_INST_Pos (16UL) /*!< QSPIC_SUS_INST (Bit 16) */
+#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_SUS_INST_Msk (0xff0000UL) /*!< QSPIC_SUS_INST (Bitfield-Mask: 0xff) */
+#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_WEN_INST_Pos (8UL) /*!< QSPIC_WEN_INST (Bit 8) */
+#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_WEN_INST_Msk (0xff00UL) /*!< QSPIC_WEN_INST (Bitfield-Mask: 0xff) */
+#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_ERS_INST_Pos (0UL) /*!< QSPIC_ERS_INST (Bit 0) */
+#define QSPIC2_QSPIC2_ERASECMDA_REG_QSPIC_ERS_INST_Msk (0xffUL) /*!< QSPIC_ERS_INST (Bitfield-Mask: 0xff) */
+/* ================================================= QSPIC2_ERASECMDB_REG ================================================== */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos (24UL) /*!< QSPIC_RESSUS_DLY (Bit 24) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk (0x3f000000UL) /*!< QSPIC_RESSUS_DLY (Bitfield-Mask: 0x3f) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos (16UL) /*!< QSPIC_ERSRES_HLD (Bit 16) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk (0xf0000UL) /*!< QSPIC_ERSRES_HLD (Bitfield-Mask: 0x0f) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos (10UL) /*!< QSPIC_ERS_CS_HI (Bit 10) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk (0x7c00UL) /*!< QSPIC_ERS_CS_HI (Bitfield-Mask: 0x1f) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos (8UL) /*!< QSPIC_EAD_TX_MD (Bit 8) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk (0x300UL) /*!< QSPIC_EAD_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos (6UL) /*!< QSPIC_RES_TX_MD (Bit 6) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk (0xc0UL) /*!< QSPIC_RES_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos (4UL) /*!< QSPIC_SUS_TX_MD (Bit 4) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk (0x30UL) /*!< QSPIC_SUS_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos (2UL) /*!< QSPIC_WEN_TX_MD (Bit 2) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk (0xcUL) /*!< QSPIC_WEN_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos (0UL) /*!< QSPIC_ERS_TX_MD (Bit 0) */
+#define QSPIC2_QSPIC2_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk (0x3UL) /*!< QSPIC_ERS_TX_MD (Bitfield-Mask: 0x03) */
+/* ================================================= QSPIC2_ERASECTRL_REG ================================================== */
+#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERS_STATE_Pos (25UL) /*!< QSPIC_ERS_STATE (Bit 25) */
+#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERS_STATE_Msk (0xe000000UL) /*!< QSPIC_ERS_STATE (Bitfield-Mask: 0x07) */
+#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERASE_EN_Pos (24UL) /*!< QSPIC_ERASE_EN (Bit 24) */
+#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERASE_EN_Msk (0x1000000UL) /*!< QSPIC_ERASE_EN (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos (4UL) /*!< QSPIC_ERS_ADDR (Bit 4) */
+#define QSPIC2_QSPIC2_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk (0xfffff0UL) /*!< QSPIC_ERS_ADDR (Bitfield-Mask: 0xfffff) */
+/* ===================================================== QSPIC2_GP_REG ===================================================== */
+#define QSPIC2_QSPIC2_GP_REG_QSPIC_PADS_SLEW_Pos (3UL) /*!< QSPIC_PADS_SLEW (Bit 3) */
+#define QSPIC2_QSPIC2_GP_REG_QSPIC_PADS_SLEW_Msk (0x18UL) /*!< QSPIC_PADS_SLEW (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_GP_REG_QSPIC_PADS_DRV_Pos (1UL) /*!< QSPIC_PADS_DRV (Bit 1) */
+#define QSPIC2_QSPIC2_GP_REG_QSPIC_PADS_DRV_Msk (0x6UL) /*!< QSPIC_PADS_DRV (Bitfield-Mask: 0x03) */
+/* ================================================== QSPIC2_MEMBLEN_REG =================================================== */
+#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_T_CEM_CC_Pos (4UL) /*!< QSPIC_T_CEM_CC (Bit 4) */
+#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_T_CEM_CC_Msk (0x3ff0UL) /*!< QSPIC_T_CEM_CC (Bitfield-Mask: 0x3ff) */
+#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_T_CEM_EN_Pos (3UL) /*!< QSPIC_T_CEM_EN (Bit 3) */
+#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_T_CEM_EN_Msk (0x8UL) /*!< QSPIC_T_CEM_EN (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_MEMBLEN_Pos (0UL) /*!< QSPIC_MEMBLEN (Bit 0) */
+#define QSPIC2_QSPIC2_MEMBLEN_REG_QSPIC_MEMBLEN_Msk (0x7UL) /*!< QSPIC_MEMBLEN (Bitfield-Mask: 0x07) */
+/* ================================================== QSPIC2_READDATA_REG ================================================== */
+#define QSPIC2_QSPIC2_READDATA_REG_QSPIC_READDATA_Pos (0UL) /*!< QSPIC_READDATA (Bit 0) */
+#define QSPIC2_QSPIC2_READDATA_REG_QSPIC_READDATA_Msk (0xffffffffUL) /*!< QSPIC_READDATA (Bitfield-Mask: 0xffffffff) */
+/* ================================================== QSPIC2_RECVDATA_REG ================================================== */
+#define QSPIC2_QSPIC2_RECVDATA_REG_QSPIC_RECVDATA_Pos (0UL) /*!< QSPIC_RECVDATA (Bit 0) */
+#define QSPIC2_QSPIC2_RECVDATA_REG_QSPIC_RECVDATA_Msk (0xffffffffUL) /*!< QSPIC_RECVDATA (Bitfield-Mask: 0xffffffff) */
+/* ================================================= QSPIC2_STATUSCMD_REG ================================================== */
+#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos (22UL) /*!< QSPIC_STSDLY_SEL (Bit 22) */
+#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk (0x400000UL) /*!< QSPIC_STSDLY_SEL (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos (16UL) /*!< QSPIC_RESSTS_DLY (Bit 16) */
+#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk (0x3f0000UL) /*!< QSPIC_RESSTS_DLY (Bitfield-Mask: 0x3f) */
+#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos (15UL) /*!< QSPIC_BUSY_VAL (Bit 15) */
+#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk (0x8000UL) /*!< QSPIC_BUSY_VAL (Bitfield-Mask: 0x01) */
+#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_BUSY_POS_Pos (12UL) /*!< QSPIC_BUSY_POS (Bit 12) */
+#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_BUSY_POS_Msk (0x7000UL) /*!< QSPIC_BUSY_POS (Bitfield-Mask: 0x07) */
+#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos (10UL) /*!< QSPIC_RSTAT_RX_MD (Bit 10) */
+#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk (0xc00UL) /*!< QSPIC_RSTAT_RX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos (8UL) /*!< QSPIC_RSTAT_TX_MD (Bit 8) */
+#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk (0x300UL) /*!< QSPIC_RSTAT_TX_MD (Bitfield-Mask: 0x03) */
+#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos (0UL) /*!< QSPIC_RSTAT_INST (Bit 0) */
+#define QSPIC2_QSPIC2_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk (0xffUL) /*!< QSPIC_RSTAT_INST (Bitfield-Mask: 0xff) */
+/* =================================================== QSPIC2_STATUS_REG =================================================== */
+#define QSPIC2_QSPIC2_STATUS_REG_QSPIC_BUSY_Pos (0UL) /*!< QSPIC_BUSY (Bit 0) */
+#define QSPIC2_QSPIC2_STATUS_REG_QSPIC_BUSY_Msk (0x1UL) /*!< QSPIC_BUSY (Bitfield-Mask: 0x01) */
+/* ================================================= QSPIC2_WRITEDATA_REG ================================================== */
+#define QSPIC2_QSPIC2_WRITEDATA_REG_QSPIC_WRITEDATA_Pos (0UL) /*!< QSPIC_WRITEDATA (Bit 0) */
+#define QSPIC2_QSPIC2_WRITEDATA_REG_QSPIC_WRITEDATA_Msk (0xffffffffUL) /*!< QSPIC_WRITEDATA (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ RFMON ================ */
+/* =========================================================================================================================== */
+
+/* ==================================================== RFMON_ADDR_REG ===================================================== */
+#define RFMON_RFMON_ADDR_REG_RFMON_ADDR_Pos (2UL) /*!< RFMON_ADDR (Bit 2) */
+#define RFMON_RFMON_ADDR_REG_RFMON_ADDR_Msk (0xfffffffcUL) /*!< RFMON_ADDR (Bitfield-Mask: 0x3fffffff) */
+/* ================================================== RFMON_CRV_ADDR_REG =================================================== */
+#define RFMON_RFMON_CRV_ADDR_REG_RFMON_CRV_ADDR_Pos (2UL) /*!< RFMON_CRV_ADDR (Bit 2) */
+#define RFMON_RFMON_CRV_ADDR_REG_RFMON_CRV_ADDR_Msk (0xfffffffcUL) /*!< RFMON_CRV_ADDR (Bitfield-Mask: 0x3fffffff) */
+/* =================================================== RFMON_CRV_LEN_REG =================================================== */
+#define RFMON_RFMON_CRV_LEN_REG_RFMON_CRV_LEN_Pos (0UL) /*!< RFMON_CRV_LEN (Bit 0) */
+#define RFMON_RFMON_CRV_LEN_REG_RFMON_CRV_LEN_Msk (0x1ffffUL) /*!< RFMON_CRV_LEN (Bitfield-Mask: 0x1ffff) */
+/* ==================================================== RFMON_CTRL_REG ===================================================== */
+#define RFMON_RFMON_CTRL_REG_RFMON_BREQ_FORCE_Pos (2UL) /*!< RFMON_BREQ_FORCE (Bit 2) */
+#define RFMON_RFMON_CTRL_REG_RFMON_BREQ_FORCE_Msk (0x4UL) /*!< RFMON_BREQ_FORCE (Bitfield-Mask: 0x01) */
+#define RFMON_RFMON_CTRL_REG_RFMON_CIRC_EN_Pos (1UL) /*!< RFMON_CIRC_EN (Bit 1) */
+#define RFMON_RFMON_CTRL_REG_RFMON_CIRC_EN_Msk (0x2UL) /*!< RFMON_CIRC_EN (Bitfield-Mask: 0x01) */
+#define RFMON_RFMON_CTRL_REG_RFMON_PACK_EN_Pos (0UL) /*!< RFMON_PACK_EN (Bit 0) */
+#define RFMON_RFMON_CTRL_REG_RFMON_PACK_EN_Msk (0x1UL) /*!< RFMON_PACK_EN (Bitfield-Mask: 0x01) */
+/* ===================================================== RFMON_LEN_REG ===================================================== */
+#define RFMON_RFMON_LEN_REG_RFMON_LEN_Pos (0UL) /*!< RFMON_LEN (Bit 0) */
+#define RFMON_RFMON_LEN_REG_RFMON_LEN_Msk (0x1ffffUL) /*!< RFMON_LEN (Bitfield-Mask: 0x1ffff) */
+/* ==================================================== RFMON_STAT_REG ===================================================== */
+#define RFMON_RFMON_STAT_REG_RFMON_OFLOW_STK_Pos (1UL) /*!< RFMON_OFLOW_STK (Bit 1) */
+#define RFMON_RFMON_STAT_REG_RFMON_OFLOW_STK_Msk (0x2UL) /*!< RFMON_OFLOW_STK (Bitfield-Mask: 0x01) */
+#define RFMON_RFMON_STAT_REG_RFMON_ACTIVE_Pos (0UL) /*!< RFMON_ACTIVE (Bit 0) */
+#define RFMON_RFMON_STAT_REG_RFMON_ACTIVE_Msk (0x1UL) /*!< RFMON_ACTIVE (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ RTC ================ */
+/* =========================================================================================================================== */
+
+/* ================================================= RTC_ALARM_ENABLE_REG ================================================== */
+#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Pos (5UL) /*!< RTC_ALARM_MNTH_EN (Bit 5) */
+#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Msk (0x20UL) /*!< RTC_ALARM_MNTH_EN (Bitfield-Mask: 0x01) */
+#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Pos (4UL) /*!< RTC_ALARM_DATE_EN (Bit 4) */
+#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Msk (0x10UL) /*!< RTC_ALARM_DATE_EN (Bitfield-Mask: 0x01) */
+#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Pos (3UL) /*!< RTC_ALARM_HOUR_EN (Bit 3) */
+#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Msk (0x8UL) /*!< RTC_ALARM_HOUR_EN (Bitfield-Mask: 0x01) */
+#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Pos (2UL) /*!< RTC_ALARM_MIN_EN (Bit 2) */
+#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Msk (0x4UL) /*!< RTC_ALARM_MIN_EN (Bitfield-Mask: 0x01) */
+#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Pos (1UL) /*!< RTC_ALARM_SEC_EN (Bit 1) */
+#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Msk (0x2UL) /*!< RTC_ALARM_SEC_EN (Bitfield-Mask: 0x01) */
+#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOS_EN_Pos (0UL) /*!< RTC_ALARM_HOS_EN (Bit 0) */
+#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOS_EN_Msk (0x1UL) /*!< RTC_ALARM_HOS_EN (Bitfield-Mask: 0x01) */
+/* ================================================ RTC_CALENDAR_ALARM_REG ================================================= */
+#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_T_Pos (12UL) /*!< RTC_CAL_D_T (Bit 12) */
+#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_T_Msk (0x3000UL) /*!< RTC_CAL_D_T (Bitfield-Mask: 0x03) */
+#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_U_Pos (8UL) /*!< RTC_CAL_D_U (Bit 8) */
+#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_U_Msk (0xf00UL) /*!< RTC_CAL_D_U (Bitfield-Mask: 0x0f) */
+#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_T_Pos (7UL) /*!< RTC_CAL_M_T (Bit 7) */
+#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_T_Msk (0x80UL) /*!< RTC_CAL_M_T (Bitfield-Mask: 0x01) */
+#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_U_Pos (3UL) /*!< RTC_CAL_M_U (Bit 3) */
+#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_U_Msk (0x78UL) /*!< RTC_CAL_M_U (Bitfield-Mask: 0x0f) */
+/* =================================================== RTC_CALENDAR_REG ==================================================== */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_CH_Pos (31UL) /*!< RTC_CAL_CH (Bit 31) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_CH_Msk (0x80000000UL) /*!< RTC_CAL_CH (Bitfield-Mask: 0x01) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_T_Pos (28UL) /*!< RTC_CAL_C_T (Bit 28) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_T_Msk (0x30000000UL) /*!< RTC_CAL_C_T (Bitfield-Mask: 0x03) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_U_Pos (24UL) /*!< RTC_CAL_C_U (Bit 24) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_U_Msk (0xf000000UL) /*!< RTC_CAL_C_U (Bitfield-Mask: 0x0f) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_T_Pos (20UL) /*!< RTC_CAL_Y_T (Bit 20) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_T_Msk (0xf00000UL) /*!< RTC_CAL_Y_T (Bitfield-Mask: 0x0f) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_U_Pos (16UL) /*!< RTC_CAL_Y_U (Bit 16) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_U_Msk (0xf0000UL) /*!< RTC_CAL_Y_U (Bitfield-Mask: 0x0f) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_T_Pos (12UL) /*!< RTC_CAL_D_T (Bit 12) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_T_Msk (0x3000UL) /*!< RTC_CAL_D_T (Bitfield-Mask: 0x03) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_U_Pos (8UL) /*!< RTC_CAL_D_U (Bit 8) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_U_Msk (0xf00UL) /*!< RTC_CAL_D_U (Bitfield-Mask: 0x0f) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_T_Pos (7UL) /*!< RTC_CAL_M_T (Bit 7) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_T_Msk (0x80UL) /*!< RTC_CAL_M_T (Bitfield-Mask: 0x01) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_U_Pos (3UL) /*!< RTC_CAL_M_U (Bit 3) */
+#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_U_Msk (0x78UL) /*!< RTC_CAL_M_U (Bitfield-Mask: 0x0f) */
+#define RTC_RTC_CALENDAR_REG_RTC_DAY_Pos (0UL) /*!< RTC_DAY (Bit 0) */
+#define RTC_RTC_CALENDAR_REG_RTC_DAY_Msk (0x7UL) /*!< RTC_DAY (Bitfield-Mask: 0x07) */
+/* ==================================================== RTC_CONTROL_REG ==================================================== */
+#define RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Pos (1UL) /*!< RTC_CAL_DISABLE (Bit 1) */
+#define RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Msk (0x2UL) /*!< RTC_CAL_DISABLE (Bitfield-Mask: 0x01) */
+#define RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Pos (0UL) /*!< RTC_TIME_DISABLE (Bit 0) */
+#define RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Msk (0x1UL) /*!< RTC_TIME_DISABLE (Bitfield-Mask: 0x01) */
+/* ================================================== RTC_EVENT_CTRL_REG =================================================== */
+#define RTC_RTC_EVENT_CTRL_REG_RTC_PDC_EVENT_EN_Pos (1UL) /*!< RTC_PDC_EVENT_EN (Bit 1) */
+#define RTC_RTC_EVENT_CTRL_REG_RTC_PDC_EVENT_EN_Msk (0x2UL) /*!< RTC_PDC_EVENT_EN (Bitfield-Mask: 0x01) */
+#define RTC_RTC_EVENT_CTRL_REG_RTC_MOTOR_EVENT_EN_Pos (0UL) /*!< RTC_MOTOR_EVENT_EN (Bit 0) */
+#define RTC_RTC_EVENT_CTRL_REG_RTC_MOTOR_EVENT_EN_Msk (0x1UL) /*!< RTC_MOTOR_EVENT_EN (Bitfield-Mask: 0x01) */
+/* ================================================== RTC_EVENT_FLAGS_REG ================================================== */
+#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Pos (6UL) /*!< RTC_EVENT_ALRM (Bit 6) */
+#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Msk (0x40UL) /*!< RTC_EVENT_ALRM (Bitfield-Mask: 0x01) */
+#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MNTH_Pos (5UL) /*!< RTC_EVENT_MNTH (Bit 5) */
+#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MNTH_Msk (0x20UL) /*!< RTC_EVENT_MNTH (Bitfield-Mask: 0x01) */
+#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_DATE_Pos (4UL) /*!< RTC_EVENT_DATE (Bit 4) */
+#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_DATE_Msk (0x10UL) /*!< RTC_EVENT_DATE (Bitfield-Mask: 0x01) */
+#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOUR_Pos (3UL) /*!< RTC_EVENT_HOUR (Bit 3) */
+#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOUR_Msk (0x8UL) /*!< RTC_EVENT_HOUR (Bitfield-Mask: 0x01) */
+#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MIN_Pos (2UL) /*!< RTC_EVENT_MIN (Bit 2) */
+#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MIN_Msk (0x4UL) /*!< RTC_EVENT_MIN (Bitfield-Mask: 0x01) */
+#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Pos (1UL) /*!< RTC_EVENT_SEC (Bit 1) */
+#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Msk (0x2UL) /*!< RTC_EVENT_SEC (Bitfield-Mask: 0x01) */
+#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOS_Pos (0UL) /*!< RTC_EVENT_HOS (Bit 0) */
+#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOS_Msk (0x1UL) /*!< RTC_EVENT_HOS (Bitfield-Mask: 0x01) */
+/* =================================================== RTC_HOUR_MODE_REG =================================================== */
+#define RTC_RTC_HOUR_MODE_REG_RTC_HMS_Pos (0UL) /*!< RTC_HMS (Bit 0) */
+#define RTC_RTC_HOUR_MODE_REG_RTC_HMS_Msk (0x1UL) /*!< RTC_HMS (Bitfield-Mask: 0x01) */
+/* =============================================== RTC_INTERRUPT_DISABLE_REG =============================================== */
+#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Pos (6UL) /*!< RTC_ALRM_INT_DIS (Bit 6) */
+#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Msk (0x40UL) /*!< RTC_ALRM_INT_DIS (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MNTH_INT_DIS_Pos (5UL) /*!< RTC_MNTH_INT_DIS (Bit 5) */
+#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MNTH_INT_DIS_Msk (0x20UL) /*!< RTC_MNTH_INT_DIS (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_DATE_INT_DIS_Pos (4UL) /*!< RTC_DATE_INT_DIS (Bit 4) */
+#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_DATE_INT_DIS_Msk (0x10UL) /*!< RTC_DATE_INT_DIS (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOUR_INT_DIS_Pos (3UL) /*!< RTC_HOUR_INT_DIS (Bit 3) */
+#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOUR_INT_DIS_Msk (0x8UL) /*!< RTC_HOUR_INT_DIS (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MIN_INT_DIS_Pos (2UL) /*!< RTC_MIN_INT_DIS (Bit 2) */
+#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MIN_INT_DIS_Msk (0x4UL) /*!< RTC_MIN_INT_DIS (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Pos (1UL) /*!< RTC_SEC_INT_DIS (Bit 1) */
+#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Msk (0x2UL) /*!< RTC_SEC_INT_DIS (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOS_INT_DIS_Pos (0UL) /*!< RTC_HOS_INT_DIS (Bit 0) */
+#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOS_INT_DIS_Msk (0x1UL) /*!< RTC_HOS_INT_DIS (Bitfield-Mask: 0x01) */
+/* =============================================== RTC_INTERRUPT_ENABLE_REG ================================================ */
+#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Pos (6UL) /*!< RTC_ALRM_INT_EN (Bit 6) */
+#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Msk (0x40UL) /*!< RTC_ALRM_INT_EN (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MNTH_INT_EN_Pos (5UL) /*!< RTC_MNTH_INT_EN (Bit 5) */
+#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MNTH_INT_EN_Msk (0x20UL) /*!< RTC_MNTH_INT_EN (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_DATE_INT_EN_Pos (4UL) /*!< RTC_DATE_INT_EN (Bit 4) */
+#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_DATE_INT_EN_Msk (0x10UL) /*!< RTC_DATE_INT_EN (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOUR_INT_EN_Pos (3UL) /*!< RTC_HOUR_INT_EN (Bit 3) */
+#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOUR_INT_EN_Msk (0x8UL) /*!< RTC_HOUR_INT_EN (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MIN_INT_EN_Pos (2UL) /*!< RTC_MIN_INT_EN (Bit 2) */
+#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MIN_INT_EN_Msk (0x4UL) /*!< RTC_MIN_INT_EN (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Pos (1UL) /*!< RTC_SEC_INT_EN (Bit 1) */
+#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Msk (0x2UL) /*!< RTC_SEC_INT_EN (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOS_INT_EN_Pos (0UL) /*!< RTC_HOS_INT_EN (Bit 0) */
+#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOS_INT_EN_Msk (0x1UL) /*!< RTC_HOS_INT_EN (Bitfield-Mask: 0x01) */
+/* ================================================ RTC_INTERRUPT_MASK_REG ================================================= */
+#define RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Pos (6UL) /*!< RTC_ALRM_INT_MSK (Bit 6) */
+#define RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Msk (0x40UL) /*!< RTC_ALRM_INT_MSK (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MNTH_INT_MSK_Pos (5UL) /*!< RTC_MNTH_INT_MSK (Bit 5) */
+#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MNTH_INT_MSK_Msk (0x20UL) /*!< RTC_MNTH_INT_MSK (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_MASK_REG_RTC_DATE_INT_MSK_Pos (4UL) /*!< RTC_DATE_INT_MSK (Bit 4) */
+#define RTC_RTC_INTERRUPT_MASK_REG_RTC_DATE_INT_MSK_Msk (0x10UL) /*!< RTC_DATE_INT_MSK (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOUR_INT_MSK_Pos (3UL) /*!< RTC_HOUR_INT_MSK (Bit 3) */
+#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOUR_INT_MSK_Msk (0x8UL) /*!< RTC_HOUR_INT_MSK (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MIN_INT_MSK_Pos (2UL) /*!< RTC_MIN_INT_MSK (Bit 2) */
+#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MIN_INT_MSK_Msk (0x4UL) /*!< RTC_MIN_INT_MSK (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Pos (1UL) /*!< RTC_SEC_INT_MSK (Bit 1) */
+#define RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Msk (0x2UL) /*!< RTC_SEC_INT_MSK (Bitfield-Mask: 0x01) */
+#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOS_INT_MSK_Pos (0UL) /*!< RTC_HOS_INT_MSK (Bit 0) */
+#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOS_INT_MSK_Msk (0x1UL) /*!< RTC_HOS_INT_MSK (Bitfield-Mask: 0x01) */
+/* =================================================== RTC_KEEP_RTC_REG ==================================================== */
+#define RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Pos (0UL) /*!< RTC_KEEP (Bit 0) */
+#define RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Msk (0x1UL) /*!< RTC_KEEP (Bitfield-Mask: 0x01) */
+/* ================================================ RTC_MOTOR_EVENT_CNT_REG ================================================ */
+#define RTC_RTC_MOTOR_EVENT_CNT_REG_RTC_MOTOR_EVENT_CNT_Pos (0UL) /*!< RTC_MOTOR_EVENT_CNT (Bit 0) */
+#define RTC_RTC_MOTOR_EVENT_CNT_REG_RTC_MOTOR_EVENT_CNT_Msk (0xfffUL) /*!< RTC_MOTOR_EVENT_CNT (Bitfield-Mask: 0xfff) */
+/* ============================================== RTC_MOTOR_EVENT_PERIOD_REG =============================================== */
+#define RTC_RTC_MOTOR_EVENT_PERIOD_REG_RTC_MOTOR_EVENT_PERIOD_Pos (0UL) /*!< RTC_MOTOR_EVENT_PERIOD (Bit 0) */
+#define RTC_RTC_MOTOR_EVENT_PERIOD_REG_RTC_MOTOR_EVENT_PERIOD_Msk (0xfffUL) /*!< RTC_MOTOR_EVENT_PERIOD (Bitfield-Mask: 0xfff) */
+/* ================================================ RTC_PDC_EVENT_CLEAR_REG ================================================ */
+#define RTC_RTC_PDC_EVENT_CLEAR_REG_PDC_EVENT_CLEAR_Pos (0UL) /*!< PDC_EVENT_CLEAR (Bit 0) */
+#define RTC_RTC_PDC_EVENT_CLEAR_REG_PDC_EVENT_CLEAR_Msk (0x1UL) /*!< PDC_EVENT_CLEAR (Bitfield-Mask: 0x01) */
+/* ================================================= RTC_PDC_EVENT_CNT_REG ================================================= */
+#define RTC_RTC_PDC_EVENT_CNT_REG_RTC_PDC_EVENT_CNT_Pos (0UL) /*!< RTC_PDC_EVENT_CNT (Bit 0) */
+#define RTC_RTC_PDC_EVENT_CNT_REG_RTC_PDC_EVENT_CNT_Msk (0x1fffUL) /*!< RTC_PDC_EVENT_CNT (Bitfield-Mask: 0x1fff) */
+/* =============================================== RTC_PDC_EVENT_PERIOD_REG ================================================ */
+#define RTC_RTC_PDC_EVENT_PERIOD_REG_RTC_PDC_EVENT_PERIOD_Pos (0UL) /*!< RTC_PDC_EVENT_PERIOD (Bit 0) */
+#define RTC_RTC_PDC_EVENT_PERIOD_REG_RTC_PDC_EVENT_PERIOD_Msk (0x1fffUL) /*!< RTC_PDC_EVENT_PERIOD (Bitfield-Mask: 0x1fff) */
+/* ==================================================== RTC_STATUS_REG ===================================================== */
+#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Pos (3UL) /*!< RTC_VALID_CAL_ALM (Bit 3) */
+#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Msk (0x8UL) /*!< RTC_VALID_CAL_ALM (Bitfield-Mask: 0x01) */
+#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Pos (2UL) /*!< RTC_VALID_TIME_ALM (Bit 2) */
+#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Msk (0x4UL) /*!< RTC_VALID_TIME_ALM (Bitfield-Mask: 0x01) */
+#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_Pos (1UL) /*!< RTC_VALID_CAL (Bit 1) */
+#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_Msk (0x2UL) /*!< RTC_VALID_CAL (Bitfield-Mask: 0x01) */
+#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_Pos (0UL) /*!< RTC_VALID_TIME (Bit 0) */
+#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_Msk (0x1UL) /*!< RTC_VALID_TIME (Bitfield-Mask: 0x01) */
+/* ================================================== RTC_TIME_ALARM_REG =================================================== */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_PM_Pos (30UL) /*!< RTC_TIME_PM (Bit 30) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_PM_Msk (0x40000000UL) /*!< RTC_TIME_PM (Bitfield-Mask: 0x01) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_T_Pos (28UL) /*!< RTC_TIME_HR_T (Bit 28) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_T_Msk (0x30000000UL) /*!< RTC_TIME_HR_T (Bitfield-Mask: 0x03) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_U_Pos (24UL) /*!< RTC_TIME_HR_U (Bit 24) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_U_Msk (0xf000000UL) /*!< RTC_TIME_HR_U (Bitfield-Mask: 0x0f) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_T_Pos (20UL) /*!< RTC_TIME_M_T (Bit 20) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_T_Msk (0x700000UL) /*!< RTC_TIME_M_T (Bitfield-Mask: 0x07) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_U_Pos (16UL) /*!< RTC_TIME_M_U (Bit 16) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_U_Msk (0xf0000UL) /*!< RTC_TIME_M_U (Bitfield-Mask: 0x0f) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_T_Pos (12UL) /*!< RTC_TIME_S_T (Bit 12) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_T_Msk (0x7000UL) /*!< RTC_TIME_S_T (Bitfield-Mask: 0x07) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_U_Pos (8UL) /*!< RTC_TIME_S_U (Bit 8) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_U_Msk (0xf00UL) /*!< RTC_TIME_S_U (Bitfield-Mask: 0x0f) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_T_Pos (4UL) /*!< RTC_TIME_H_T (Bit 4) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_T_Msk (0xf0UL) /*!< RTC_TIME_H_T (Bitfield-Mask: 0x0f) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_U_Pos (0UL) /*!< RTC_TIME_H_U (Bit 0) */
+#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_U_Msk (0xfUL) /*!< RTC_TIME_H_U (Bitfield-Mask: 0x0f) */
+/* ===================================================== RTC_TIME_REG ====================================================== */
+#define RTC_RTC_TIME_REG_RTC_TIME_CH_Pos (31UL) /*!< RTC_TIME_CH (Bit 31) */
+#define RTC_RTC_TIME_REG_RTC_TIME_CH_Msk (0x80000000UL) /*!< RTC_TIME_CH (Bitfield-Mask: 0x01) */
+#define RTC_RTC_TIME_REG_RTC_TIME_PM_Pos (30UL) /*!< RTC_TIME_PM (Bit 30) */
+#define RTC_RTC_TIME_REG_RTC_TIME_PM_Msk (0x40000000UL) /*!< RTC_TIME_PM (Bitfield-Mask: 0x01) */
+#define RTC_RTC_TIME_REG_RTC_TIME_HR_T_Pos (28UL) /*!< RTC_TIME_HR_T (Bit 28) */
+#define RTC_RTC_TIME_REG_RTC_TIME_HR_T_Msk (0x30000000UL) /*!< RTC_TIME_HR_T (Bitfield-Mask: 0x03) */
+#define RTC_RTC_TIME_REG_RTC_TIME_HR_U_Pos (24UL) /*!< RTC_TIME_HR_U (Bit 24) */
+#define RTC_RTC_TIME_REG_RTC_TIME_HR_U_Msk (0xf000000UL) /*!< RTC_TIME_HR_U (Bitfield-Mask: 0x0f) */
+#define RTC_RTC_TIME_REG_RTC_TIME_M_T_Pos (20UL) /*!< RTC_TIME_M_T (Bit 20) */
+#define RTC_RTC_TIME_REG_RTC_TIME_M_T_Msk (0x700000UL) /*!< RTC_TIME_M_T (Bitfield-Mask: 0x07) */
+#define RTC_RTC_TIME_REG_RTC_TIME_M_U_Pos (16UL) /*!< RTC_TIME_M_U (Bit 16) */
+#define RTC_RTC_TIME_REG_RTC_TIME_M_U_Msk (0xf0000UL) /*!< RTC_TIME_M_U (Bitfield-Mask: 0x0f) */
+#define RTC_RTC_TIME_REG_RTC_TIME_S_T_Pos (12UL) /*!< RTC_TIME_S_T (Bit 12) */
+#define RTC_RTC_TIME_REG_RTC_TIME_S_T_Msk (0x7000UL) /*!< RTC_TIME_S_T (Bitfield-Mask: 0x07) */
+#define RTC_RTC_TIME_REG_RTC_TIME_S_U_Pos (8UL) /*!< RTC_TIME_S_U (Bit 8) */
+#define RTC_RTC_TIME_REG_RTC_TIME_S_U_Msk (0xf00UL) /*!< RTC_TIME_S_U (Bitfield-Mask: 0x0f) */
+#define RTC_RTC_TIME_REG_RTC_TIME_H_T_Pos (4UL) /*!< RTC_TIME_H_T (Bit 4) */
+#define RTC_RTC_TIME_REG_RTC_TIME_H_T_Msk (0xf0UL) /*!< RTC_TIME_H_T (Bitfield-Mask: 0x0f) */
+#define RTC_RTC_TIME_REG_RTC_TIME_H_U_Pos (0UL) /*!< RTC_TIME_H_U (Bit 0) */
+#define RTC_RTC_TIME_REG_RTC_TIME_H_U_Msk (0xfUL) /*!< RTC_TIME_H_U (Bitfield-Mask: 0x0f) */
+
+
+/* =========================================================================================================================== */
+/* ================ SDADC ================ */
+/* =========================================================================================================================== */
+
+/* ================================================== SDADC_CLEAR_INT_REG ================================================== */
+#define SDADC_SDADC_CLEAR_INT_REG_SDADC_CLR_INT_Pos (0UL) /*!< SDADC_CLR_INT (Bit 0) */
+#define SDADC_SDADC_CLEAR_INT_REG_SDADC_CLR_INT_Msk (0xffffUL) /*!< SDADC_CLR_INT (Bitfield-Mask: 0xffff) */
+/* ==================================================== SDADC_CTRL_REG ===================================================== */
+#define SDADC_SDADC_CTRL_REG_SDADC_DMA_EN_Pos (17UL) /*!< SDADC_DMA_EN (Bit 17) */
+#define SDADC_SDADC_CTRL_REG_SDADC_DMA_EN_Msk (0x20000UL) /*!< SDADC_DMA_EN (Bitfield-Mask: 0x01) */
+#define SDADC_SDADC_CTRL_REG_SDADC_MINT_Pos (16UL) /*!< SDADC_MINT (Bit 16) */
+#define SDADC_SDADC_CTRL_REG_SDADC_MINT_Msk (0x10000UL) /*!< SDADC_MINT (Bitfield-Mask: 0x01) */
+#define SDADC_SDADC_CTRL_REG_SDADC_INT_Pos (15UL) /*!< SDADC_INT (Bit 15) */
+#define SDADC_SDADC_CTRL_REG_SDADC_INT_Msk (0x8000UL) /*!< SDADC_INT (Bitfield-Mask: 0x01) */
+#define SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Pos (14UL) /*!< SDADC_LDO_OK (Bit 14) */
+#define SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Msk (0x4000UL) /*!< SDADC_LDO_OK (Bitfield-Mask: 0x01) */
+#define SDADC_SDADC_CTRL_REG_SDADC_VREF_SEL_Pos (13UL) /*!< SDADC_VREF_SEL (Bit 13) */
+#define SDADC_SDADC_CTRL_REG_SDADC_VREF_SEL_Msk (0x2000UL) /*!< SDADC_VREF_SEL (Bitfield-Mask: 0x01) */
+#define SDADC_SDADC_CTRL_REG_SDADC_CONT_Pos (12UL) /*!< SDADC_CONT (Bit 12) */
+#define SDADC_SDADC_CTRL_REG_SDADC_CONT_Msk (0x1000UL) /*!< SDADC_CONT (Bitfield-Mask: 0x01) */
+#define SDADC_SDADC_CTRL_REG_SDADC_OSR_Pos (10UL) /*!< SDADC_OSR (Bit 10) */
+#define SDADC_SDADC_CTRL_REG_SDADC_OSR_Msk (0xc00UL) /*!< SDADC_OSR (Bitfield-Mask: 0x03) */
+#define SDADC_SDADC_CTRL_REG_SDADC_SE_Pos (9UL) /*!< SDADC_SE (Bit 9) */
+#define SDADC_SDADC_CTRL_REG_SDADC_SE_Msk (0x200UL) /*!< SDADC_SE (Bitfield-Mask: 0x01) */
+#define SDADC_SDADC_CTRL_REG_SDADC_INN_SEL_Pos (6UL) /*!< SDADC_INN_SEL (Bit 6) */
+#define SDADC_SDADC_CTRL_REG_SDADC_INN_SEL_Msk (0x1c0UL) /*!< SDADC_INN_SEL (Bitfield-Mask: 0x07) */
+#define SDADC_SDADC_CTRL_REG_SDADC_INP_SEL_Pos (2UL) /*!< SDADC_INP_SEL (Bit 2) */
+#define SDADC_SDADC_CTRL_REG_SDADC_INP_SEL_Msk (0x3cUL) /*!< SDADC_INP_SEL (Bitfield-Mask: 0x0f) */
+#define SDADC_SDADC_CTRL_REG_SDADC_START_Pos (1UL) /*!< SDADC_START (Bit 1) */
+#define SDADC_SDADC_CTRL_REG_SDADC_START_Msk (0x2UL) /*!< SDADC_START (Bitfield-Mask: 0x01) */
+#define SDADC_SDADC_CTRL_REG_SDADC_EN_Pos (0UL) /*!< SDADC_EN (Bit 0) */
+#define SDADC_SDADC_CTRL_REG_SDADC_EN_Msk (0x1UL) /*!< SDADC_EN (Bitfield-Mask: 0x01) */
+/* ================================================== SDADC_GAIN_CORR_REG ================================================== */
+#define SDADC_SDADC_GAIN_CORR_REG_SDADC_GAIN_CORR_Pos (0UL) /*!< SDADC_GAIN_CORR (Bit 0) */
+#define SDADC_SDADC_GAIN_CORR_REG_SDADC_GAIN_CORR_Msk (0x3ffUL) /*!< SDADC_GAIN_CORR (Bitfield-Mask: 0x3ff) */
+/* ================================================== SDADC_OFFS_CORR_REG ================================================== */
+#define SDADC_SDADC_OFFS_CORR_REG_SDADC_OFFS_CORR_Pos (0UL) /*!< SDADC_OFFS_CORR (Bit 0) */
+#define SDADC_SDADC_OFFS_CORR_REG_SDADC_OFFS_CORR_Msk (0x3ffUL) /*!< SDADC_OFFS_CORR (Bitfield-Mask: 0x3ff) */
+/* =================================================== SDADC_RESULT_REG ==================================================== */
+#define SDADC_SDADC_RESULT_REG_SDADC_VAL_Pos (0UL) /*!< SDADC_VAL (Bit 0) */
+#define SDADC_SDADC_RESULT_REG_SDADC_VAL_Msk (0xffffUL) /*!< SDADC_VAL (Bitfield-Mask: 0xffff) */
+/* ==================================================== SDADC_TEST_REG ===================================================== */
+#define SDADC_SDADC_TEST_REG_SDADC_CLK_FREQ_Pos (6UL) /*!< SDADC_CLK_FREQ (Bit 6) */
+#define SDADC_SDADC_TEST_REG_SDADC_CLK_FREQ_Msk (0xc0UL) /*!< SDADC_CLK_FREQ (Bitfield-Mask: 0x03) */
+
+
+/* =========================================================================================================================== */
+/* ================ SMOTOR ================ */
+/* =========================================================================================================================== */
+
+/* ==================================================== CMD_TABLE_BASE ===================================================== */
+/* ===================================================== PG0_CTRL_REG ====================================================== */
+#define SMOTOR_PG0_CTRL_REG_GENEND_IRQ_EN_Pos (15UL) /*!< GENEND_IRQ_EN (Bit 15) */
+#define SMOTOR_PG0_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL) /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG0_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL) /*!< GENSTART_IRQ_EN (Bit 14) */
+#define SMOTOR_PG0_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL) /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG0_CTRL_REG_PG_START_MODE_Pos (13UL) /*!< PG_START_MODE (Bit 13) */
+#define SMOTOR_PG0_CTRL_REG_PG_START_MODE_Msk (0x2000UL) /*!< PG_START_MODE (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG0_CTRL_REG_PG_MODE_Pos (12UL) /*!< PG_MODE (Bit 12) */
+#define SMOTOR_PG0_CTRL_REG_PG_MODE_Msk (0x1000UL) /*!< PG_MODE (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG0_CTRL_REG_SIG3_EN_Pos (11UL) /*!< SIG3_EN (Bit 11) */
+#define SMOTOR_PG0_CTRL_REG_SIG3_EN_Msk (0x800UL) /*!< SIG3_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG0_CTRL_REG_SIG2_EN_Pos (10UL) /*!< SIG2_EN (Bit 10) */
+#define SMOTOR_PG0_CTRL_REG_SIG2_EN_Msk (0x400UL) /*!< SIG2_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG0_CTRL_REG_SIG1_EN_Pos (9UL) /*!< SIG1_EN (Bit 9) */
+#define SMOTOR_PG0_CTRL_REG_SIG1_EN_Msk (0x200UL) /*!< SIG1_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG0_CTRL_REG_SIG0_EN_Pos (8UL) /*!< SIG0_EN (Bit 8) */
+#define SMOTOR_PG0_CTRL_REG_SIG0_EN_Msk (0x100UL) /*!< SIG0_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG0_CTRL_REG_OUT3_SIG_Pos (6UL) /*!< OUT3_SIG (Bit 6) */
+#define SMOTOR_PG0_CTRL_REG_OUT3_SIG_Msk (0xc0UL) /*!< OUT3_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG0_CTRL_REG_OUT2_SIG_Pos (4UL) /*!< OUT2_SIG (Bit 4) */
+#define SMOTOR_PG0_CTRL_REG_OUT2_SIG_Msk (0x30UL) /*!< OUT2_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG0_CTRL_REG_OUT1_SIG_Pos (2UL) /*!< OUT1_SIG (Bit 2) */
+#define SMOTOR_PG0_CTRL_REG_OUT1_SIG_Msk (0xcUL) /*!< OUT1_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG0_CTRL_REG_OUT0_SIG_Pos (0UL) /*!< OUT0_SIG (Bit 0) */
+#define SMOTOR_PG0_CTRL_REG_OUT0_SIG_Msk (0x3UL) /*!< OUT0_SIG (Bitfield-Mask: 0x03) */
+/* ===================================================== PG1_CTRL_REG ====================================================== */
+#define SMOTOR_PG1_CTRL_REG_GENEND_IRQ_EN_Pos (15UL) /*!< GENEND_IRQ_EN (Bit 15) */
+#define SMOTOR_PG1_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL) /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG1_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL) /*!< GENSTART_IRQ_EN (Bit 14) */
+#define SMOTOR_PG1_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL) /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG1_CTRL_REG_PG_START_MODE_Pos (13UL) /*!< PG_START_MODE (Bit 13) */
+#define SMOTOR_PG1_CTRL_REG_PG_START_MODE_Msk (0x2000UL) /*!< PG_START_MODE (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG1_CTRL_REG_PG_MODE_Pos (12UL) /*!< PG_MODE (Bit 12) */
+#define SMOTOR_PG1_CTRL_REG_PG_MODE_Msk (0x1000UL) /*!< PG_MODE (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG1_CTRL_REG_SIG3_EN_Pos (11UL) /*!< SIG3_EN (Bit 11) */
+#define SMOTOR_PG1_CTRL_REG_SIG3_EN_Msk (0x800UL) /*!< SIG3_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG1_CTRL_REG_SIG2_EN_Pos (10UL) /*!< SIG2_EN (Bit 10) */
+#define SMOTOR_PG1_CTRL_REG_SIG2_EN_Msk (0x400UL) /*!< SIG2_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG1_CTRL_REG_SIG1_EN_Pos (9UL) /*!< SIG1_EN (Bit 9) */
+#define SMOTOR_PG1_CTRL_REG_SIG1_EN_Msk (0x200UL) /*!< SIG1_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG1_CTRL_REG_SIG0_EN_Pos (8UL) /*!< SIG0_EN (Bit 8) */
+#define SMOTOR_PG1_CTRL_REG_SIG0_EN_Msk (0x100UL) /*!< SIG0_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG1_CTRL_REG_OUT3_SIG_Pos (6UL) /*!< OUT3_SIG (Bit 6) */
+#define SMOTOR_PG1_CTRL_REG_OUT3_SIG_Msk (0xc0UL) /*!< OUT3_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG1_CTRL_REG_OUT2_SIG_Pos (4UL) /*!< OUT2_SIG (Bit 4) */
+#define SMOTOR_PG1_CTRL_REG_OUT2_SIG_Msk (0x30UL) /*!< OUT2_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG1_CTRL_REG_OUT1_SIG_Pos (2UL) /*!< OUT1_SIG (Bit 2) */
+#define SMOTOR_PG1_CTRL_REG_OUT1_SIG_Msk (0xcUL) /*!< OUT1_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG1_CTRL_REG_OUT0_SIG_Pos (0UL) /*!< OUT0_SIG (Bit 0) */
+#define SMOTOR_PG1_CTRL_REG_OUT0_SIG_Msk (0x3UL) /*!< OUT0_SIG (Bitfield-Mask: 0x03) */
+/* ===================================================== PG2_CTRL_REG ====================================================== */
+#define SMOTOR_PG2_CTRL_REG_GENEND_IRQ_EN_Pos (15UL) /*!< GENEND_IRQ_EN (Bit 15) */
+#define SMOTOR_PG2_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL) /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG2_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL) /*!< GENSTART_IRQ_EN (Bit 14) */
+#define SMOTOR_PG2_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL) /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG2_CTRL_REG_PG_START_MODE_Pos (13UL) /*!< PG_START_MODE (Bit 13) */
+#define SMOTOR_PG2_CTRL_REG_PG_START_MODE_Msk (0x2000UL) /*!< PG_START_MODE (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG2_CTRL_REG_PG_MODE_Pos (12UL) /*!< PG_MODE (Bit 12) */
+#define SMOTOR_PG2_CTRL_REG_PG_MODE_Msk (0x1000UL) /*!< PG_MODE (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG2_CTRL_REG_SIG3_EN_Pos (11UL) /*!< SIG3_EN (Bit 11) */
+#define SMOTOR_PG2_CTRL_REG_SIG3_EN_Msk (0x800UL) /*!< SIG3_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG2_CTRL_REG_SIG2_EN_Pos (10UL) /*!< SIG2_EN (Bit 10) */
+#define SMOTOR_PG2_CTRL_REG_SIG2_EN_Msk (0x400UL) /*!< SIG2_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG2_CTRL_REG_SIG1_EN_Pos (9UL) /*!< SIG1_EN (Bit 9) */
+#define SMOTOR_PG2_CTRL_REG_SIG1_EN_Msk (0x200UL) /*!< SIG1_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG2_CTRL_REG_SIG0_EN_Pos (8UL) /*!< SIG0_EN (Bit 8) */
+#define SMOTOR_PG2_CTRL_REG_SIG0_EN_Msk (0x100UL) /*!< SIG0_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG2_CTRL_REG_OUT3_SIG_Pos (6UL) /*!< OUT3_SIG (Bit 6) */
+#define SMOTOR_PG2_CTRL_REG_OUT3_SIG_Msk (0xc0UL) /*!< OUT3_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG2_CTRL_REG_OUT2_SIG_Pos (4UL) /*!< OUT2_SIG (Bit 4) */
+#define SMOTOR_PG2_CTRL_REG_OUT2_SIG_Msk (0x30UL) /*!< OUT2_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG2_CTRL_REG_OUT1_SIG_Pos (2UL) /*!< OUT1_SIG (Bit 2) */
+#define SMOTOR_PG2_CTRL_REG_OUT1_SIG_Msk (0xcUL) /*!< OUT1_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG2_CTRL_REG_OUT0_SIG_Pos (0UL) /*!< OUT0_SIG (Bit 0) */
+#define SMOTOR_PG2_CTRL_REG_OUT0_SIG_Msk (0x3UL) /*!< OUT0_SIG (Bitfield-Mask: 0x03) */
+/* ===================================================== PG3_CTRL_REG ====================================================== */
+#define SMOTOR_PG3_CTRL_REG_GENEND_IRQ_EN_Pos (15UL) /*!< GENEND_IRQ_EN (Bit 15) */
+#define SMOTOR_PG3_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL) /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG3_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL) /*!< GENSTART_IRQ_EN (Bit 14) */
+#define SMOTOR_PG3_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL) /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG3_CTRL_REG_PG_START_MODE_Pos (13UL) /*!< PG_START_MODE (Bit 13) */
+#define SMOTOR_PG3_CTRL_REG_PG_START_MODE_Msk (0x2000UL) /*!< PG_START_MODE (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG3_CTRL_REG_PG_MODE_Pos (12UL) /*!< PG_MODE (Bit 12) */
+#define SMOTOR_PG3_CTRL_REG_PG_MODE_Msk (0x1000UL) /*!< PG_MODE (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG3_CTRL_REG_SIG3_EN_Pos (11UL) /*!< SIG3_EN (Bit 11) */
+#define SMOTOR_PG3_CTRL_REG_SIG3_EN_Msk (0x800UL) /*!< SIG3_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG3_CTRL_REG_SIG2_EN_Pos (10UL) /*!< SIG2_EN (Bit 10) */
+#define SMOTOR_PG3_CTRL_REG_SIG2_EN_Msk (0x400UL) /*!< SIG2_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG3_CTRL_REG_SIG1_EN_Pos (9UL) /*!< SIG1_EN (Bit 9) */
+#define SMOTOR_PG3_CTRL_REG_SIG1_EN_Msk (0x200UL) /*!< SIG1_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG3_CTRL_REG_SIG0_EN_Pos (8UL) /*!< SIG0_EN (Bit 8) */
+#define SMOTOR_PG3_CTRL_REG_SIG0_EN_Msk (0x100UL) /*!< SIG0_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG3_CTRL_REG_OUT3_SIG_Pos (6UL) /*!< OUT3_SIG (Bit 6) */
+#define SMOTOR_PG3_CTRL_REG_OUT3_SIG_Msk (0xc0UL) /*!< OUT3_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG3_CTRL_REG_OUT2_SIG_Pos (4UL) /*!< OUT2_SIG (Bit 4) */
+#define SMOTOR_PG3_CTRL_REG_OUT2_SIG_Msk (0x30UL) /*!< OUT2_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG3_CTRL_REG_OUT1_SIG_Pos (2UL) /*!< OUT1_SIG (Bit 2) */
+#define SMOTOR_PG3_CTRL_REG_OUT1_SIG_Msk (0xcUL) /*!< OUT1_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG3_CTRL_REG_OUT0_SIG_Pos (0UL) /*!< OUT0_SIG (Bit 0) */
+#define SMOTOR_PG3_CTRL_REG_OUT0_SIG_Msk (0x3UL) /*!< OUT0_SIG (Bitfield-Mask: 0x03) */
+/* ===================================================== PG4_CTRL_REG ====================================================== */
+#define SMOTOR_PG4_CTRL_REG_GENEND_IRQ_EN_Pos (15UL) /*!< GENEND_IRQ_EN (Bit 15) */
+#define SMOTOR_PG4_CTRL_REG_GENEND_IRQ_EN_Msk (0x8000UL) /*!< GENEND_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG4_CTRL_REG_GENSTART_IRQ_EN_Pos (14UL) /*!< GENSTART_IRQ_EN (Bit 14) */
+#define SMOTOR_PG4_CTRL_REG_GENSTART_IRQ_EN_Msk (0x4000UL) /*!< GENSTART_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG4_CTRL_REG_PG_START_MODE_Pos (13UL) /*!< PG_START_MODE (Bit 13) */
+#define SMOTOR_PG4_CTRL_REG_PG_START_MODE_Msk (0x2000UL) /*!< PG_START_MODE (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG4_CTRL_REG_PG_MODE_Pos (12UL) /*!< PG_MODE (Bit 12) */
+#define SMOTOR_PG4_CTRL_REG_PG_MODE_Msk (0x1000UL) /*!< PG_MODE (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG4_CTRL_REG_SIG3_EN_Pos (11UL) /*!< SIG3_EN (Bit 11) */
+#define SMOTOR_PG4_CTRL_REG_SIG3_EN_Msk (0x800UL) /*!< SIG3_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG4_CTRL_REG_SIG2_EN_Pos (10UL) /*!< SIG2_EN (Bit 10) */
+#define SMOTOR_PG4_CTRL_REG_SIG2_EN_Msk (0x400UL) /*!< SIG2_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG4_CTRL_REG_SIG1_EN_Pos (9UL) /*!< SIG1_EN (Bit 9) */
+#define SMOTOR_PG4_CTRL_REG_SIG1_EN_Msk (0x200UL) /*!< SIG1_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG4_CTRL_REG_SIG0_EN_Pos (8UL) /*!< SIG0_EN (Bit 8) */
+#define SMOTOR_PG4_CTRL_REG_SIG0_EN_Msk (0x100UL) /*!< SIG0_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_PG4_CTRL_REG_OUT3_SIG_Pos (6UL) /*!< OUT3_SIG (Bit 6) */
+#define SMOTOR_PG4_CTRL_REG_OUT3_SIG_Msk (0xc0UL) /*!< OUT3_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG4_CTRL_REG_OUT2_SIG_Pos (4UL) /*!< OUT2_SIG (Bit 4) */
+#define SMOTOR_PG4_CTRL_REG_OUT2_SIG_Msk (0x30UL) /*!< OUT2_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG4_CTRL_REG_OUT1_SIG_Pos (2UL) /*!< OUT1_SIG (Bit 2) */
+#define SMOTOR_PG4_CTRL_REG_OUT1_SIG_Msk (0xcUL) /*!< OUT1_SIG (Bitfield-Mask: 0x03) */
+#define SMOTOR_PG4_CTRL_REG_OUT0_SIG_Pos (0UL) /*!< OUT0_SIG (Bit 0) */
+#define SMOTOR_PG4_CTRL_REG_OUT0_SIG_Msk (0x3UL) /*!< OUT0_SIG (Bitfield-Mask: 0x03) */
+/* ================================================== SMOTOR_CMD_FIFO_REG ================================================== */
+#define SMOTOR_SMOTOR_CMD_FIFO_REG_SMOTOR_CMD_FIFO_Pos (0UL) /*!< SMOTOR_CMD_FIFO (Bit 0) */
+#define SMOTOR_SMOTOR_CMD_FIFO_REG_SMOTOR_CMD_FIFO_Msk (0xffffUL) /*!< SMOTOR_CMD_FIFO (Bitfield-Mask: 0xffff) */
+/* ================================================ SMOTOR_CMD_READ_PTR_REG ================================================ */
+#define SMOTOR_SMOTOR_CMD_READ_PTR_REG_SMOTOR_CMD_READ_PTR_Pos (0UL) /*!< SMOTOR_CMD_READ_PTR (Bit 0) */
+#define SMOTOR_SMOTOR_CMD_READ_PTR_REG_SMOTOR_CMD_READ_PTR_Msk (0x3fUL) /*!< SMOTOR_CMD_READ_PTR (Bitfield-Mask: 0x3f) */
+/* =============================================== SMOTOR_CMD_WRITE_PTR_REG ================================================ */
+#define SMOTOR_SMOTOR_CMD_WRITE_PTR_REG_SMOTOR_CMD_WRITE_PTR_Pos (0UL) /*!< SMOTOR_CMD_WRITE_PTR (Bit 0) */
+#define SMOTOR_SMOTOR_CMD_WRITE_PTR_REG_SMOTOR_CMD_WRITE_PTR_Msk (0x3fUL) /*!< SMOTOR_CMD_WRITE_PTR (Bitfield-Mask: 0x3f) */
+/* ==================================================== SMOTOR_CTRL_REG ==================================================== */
+#define SMOTOR_SMOTOR_CTRL_REG_TRIG_RTC_EVENT_EN_Pos (28UL) /*!< TRIG_RTC_EVENT_EN (Bit 28) */
+#define SMOTOR_SMOTOR_CTRL_REG_TRIG_RTC_EVENT_EN_Msk (0x10000000UL) /*!< TRIG_RTC_EVENT_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_CTRL_REG_MC_LP_CLK_TRIG_EN_Pos (27UL) /*!< MC_LP_CLK_TRIG_EN (Bit 27) */
+#define SMOTOR_SMOTOR_CTRL_REG_MC_LP_CLK_TRIG_EN_Msk (0x8000000UL) /*!< MC_LP_CLK_TRIG_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_THRESHOLD_IRQ_EN_Pos (26UL) /*!< SMOTOR_THRESHOLD_IRQ_EN (Bit 26) */
+#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_THRESHOLD_IRQ_EN_Msk (0x4000000UL) /*!< SMOTOR_THRESHOLD_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_THRESHOLD_Pos (21UL) /*!< SMOTOR_THRESHOLD (Bit 21) */
+#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_THRESHOLD_Msk (0x3e00000UL) /*!< SMOTOR_THRESHOLD (Bitfield-Mask: 0x1f) */
+#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_FIFO_UNR_IRQ_EN_Pos (20UL) /*!< SMOTOR_FIFO_UNR_IRQ_EN (Bit 20) */
+#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_FIFO_UNR_IRQ_EN_Msk (0x100000UL) /*!< SMOTOR_FIFO_UNR_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_FIFO_OVF_IRQ_EN_Pos (19UL) /*!< SMOTOR_FIFO_OVF_IRQ_EN (Bit 19) */
+#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_FIFO_OVF_IRQ_EN_Msk (0x80000UL) /*!< SMOTOR_FIFO_OVF_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_GENEND_IRQ_EN_Pos (18UL) /*!< SMOTOR_GENEND_IRQ_EN (Bit 18) */
+#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_GENEND_IRQ_EN_Msk (0x40000UL) /*!< SMOTOR_GENEND_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_GENSTART_IRQ_EN_Pos (17UL) /*!< SMOTOR_GENSTART_IRQ_EN (Bit 17) */
+#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_GENSTART_IRQ_EN_Msk (0x20000UL) /*!< SMOTOR_GENSTART_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_MOI_Pos (7UL) /*!< SMOTOR_MOI (Bit 7) */
+#define SMOTOR_SMOTOR_CTRL_REG_SMOTOR_MOI_Msk (0x1ff80UL) /*!< SMOTOR_MOI (Bitfield-Mask: 0x3ff) */
+#define SMOTOR_SMOTOR_CTRL_REG_CYCLIC_SIZE_Pos (1UL) /*!< CYCLIC_SIZE (Bit 1) */
+#define SMOTOR_SMOTOR_CTRL_REG_CYCLIC_SIZE_Msk (0x7eUL) /*!< CYCLIC_SIZE (Bitfield-Mask: 0x3f) */
+#define SMOTOR_SMOTOR_CTRL_REG_CYCLIC_MODE_Pos (0UL) /*!< CYCLIC_MODE (Bit 0) */
+#define SMOTOR_SMOTOR_CTRL_REG_CYCLIC_MODE_Msk (0x1UL) /*!< CYCLIC_MODE (Bitfield-Mask: 0x01) */
+/* ================================================= SMOTOR_IRQ_CLEAR_REG ================================================== */
+#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_THRESHOLD_IRQ_CLEAR_Pos (4UL) /*!< THRESHOLD_IRQ_CLEAR (Bit 4) */
+#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_THRESHOLD_IRQ_CLEAR_Msk (0x10UL) /*!< THRESHOLD_IRQ_CLEAR (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_FIFO_UNR_IRQ_CLEAR_Pos (3UL) /*!< FIFO_UNR_IRQ_CLEAR (Bit 3) */
+#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_FIFO_UNR_IRQ_CLEAR_Msk (0x8UL) /*!< FIFO_UNR_IRQ_CLEAR (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_FIFO_OVF_IRQ_CLEAR_Pos (2UL) /*!< FIFO_OVF_IRQ_CLEAR (Bit 2) */
+#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_FIFO_OVF_IRQ_CLEAR_Msk (0x4UL) /*!< FIFO_OVF_IRQ_CLEAR (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_GENEND_IRQ_CLEAR_Pos (1UL) /*!< GENEND_IRQ_CLEAR (Bit 1) */
+#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_GENEND_IRQ_CLEAR_Msk (0x2UL) /*!< GENEND_IRQ_CLEAR (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_GENSTART_IRQ_CLEAR_Pos (0UL) /*!< GENSTART_IRQ_CLEAR (Bit 0) */
+#define SMOTOR_SMOTOR_IRQ_CLEAR_REG_GENSTART_IRQ_CLEAR_Msk (0x1UL) /*!< GENSTART_IRQ_CLEAR (Bitfield-Mask: 0x01) */
+/* =================================================== SMOTOR_STATUS_REG =================================================== */
+#define SMOTOR_SMOTOR_STATUS_REG_PG4_BUSY_Pos (9UL) /*!< PG4_BUSY (Bit 9) */
+#define SMOTOR_SMOTOR_STATUS_REG_PG4_BUSY_Msk (0x200UL) /*!< PG4_BUSY (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_STATUS_REG_PG3_BUSY_Pos (8UL) /*!< PG3_BUSY (Bit 8) */
+#define SMOTOR_SMOTOR_STATUS_REG_PG3_BUSY_Msk (0x100UL) /*!< PG3_BUSY (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_STATUS_REG_PG2_BUSY_Pos (7UL) /*!< PG2_BUSY (Bit 7) */
+#define SMOTOR_SMOTOR_STATUS_REG_PG2_BUSY_Msk (0x80UL) /*!< PG2_BUSY (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_STATUS_REG_PG1_BUSY_Pos (6UL) /*!< PG1_BUSY (Bit 6) */
+#define SMOTOR_SMOTOR_STATUS_REG_PG1_BUSY_Msk (0x40UL) /*!< PG1_BUSY (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_STATUS_REG_PG0_BUSY_Pos (5UL) /*!< PG0_BUSY (Bit 5) */
+#define SMOTOR_SMOTOR_STATUS_REG_PG0_BUSY_Msk (0x20UL) /*!< PG0_BUSY (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_STATUS_REG_THRESHOLD_IRQ_STATUS_Pos (4UL) /*!< THRESHOLD_IRQ_STATUS (Bit 4) */
+#define SMOTOR_SMOTOR_STATUS_REG_THRESHOLD_IRQ_STATUS_Msk (0x10UL) /*!< THRESHOLD_IRQ_STATUS (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_STATUS_REG_FIFO_UNR_IRQ_STATUS_Pos (3UL) /*!< FIFO_UNR_IRQ_STATUS (Bit 3) */
+#define SMOTOR_SMOTOR_STATUS_REG_FIFO_UNR_IRQ_STATUS_Msk (0x8UL) /*!< FIFO_UNR_IRQ_STATUS (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_STATUS_REG_FIFO_OVF_IRQ_STATUS_Pos (2UL) /*!< FIFO_OVF_IRQ_STATUS (Bit 2) */
+#define SMOTOR_SMOTOR_STATUS_REG_FIFO_OVF_IRQ_STATUS_Msk (0x4UL) /*!< FIFO_OVF_IRQ_STATUS (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_STATUS_REG_GENEND_IRQ_STATUS_Pos (1UL) /*!< GENEND_IRQ_STATUS (Bit 1) */
+#define SMOTOR_SMOTOR_STATUS_REG_GENEND_IRQ_STATUS_Msk (0x2UL) /*!< GENEND_IRQ_STATUS (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_STATUS_REG_GENSTART_IRQ_STATUS_Pos (0UL) /*!< GENSTART_IRQ_STATUS (Bit 0) */
+#define SMOTOR_SMOTOR_STATUS_REG_GENSTART_IRQ_STATUS_Msk (0x1UL) /*!< GENSTART_IRQ_STATUS (Bitfield-Mask: 0x01) */
+/* ================================================== SMOTOR_TRIGGER_REG =================================================== */
+#define SMOTOR_SMOTOR_TRIGGER_REG_PG4_START_Pos (5UL) /*!< PG4_START (Bit 5) */
+#define SMOTOR_SMOTOR_TRIGGER_REG_PG4_START_Msk (0x20UL) /*!< PG4_START (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_TRIGGER_REG_PG3_START_Pos (4UL) /*!< PG3_START (Bit 4) */
+#define SMOTOR_SMOTOR_TRIGGER_REG_PG3_START_Msk (0x10UL) /*!< PG3_START (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_TRIGGER_REG_PG2_START_Pos (3UL) /*!< PG2_START (Bit 3) */
+#define SMOTOR_SMOTOR_TRIGGER_REG_PG2_START_Msk (0x8UL) /*!< PG2_START (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_TRIGGER_REG_PG1_START_Pos (2UL) /*!< PG1_START (Bit 2) */
+#define SMOTOR_SMOTOR_TRIGGER_REG_PG1_START_Msk (0x4UL) /*!< PG1_START (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_TRIGGER_REG_PG0_START_Pos (1UL) /*!< PG0_START (Bit 1) */
+#define SMOTOR_SMOTOR_TRIGGER_REG_PG0_START_Msk (0x2UL) /*!< PG0_START (Bitfield-Mask: 0x01) */
+#define SMOTOR_SMOTOR_TRIGGER_REG_POP_CMD_Pos (0UL) /*!< POP_CMD (Bit 0) */
+#define SMOTOR_SMOTOR_TRIGGER_REG_POP_CMD_Msk (0x1UL) /*!< POP_CMD (Bitfield-Mask: 0x01) */
+/* ==================================================== WAVETABLE_BASE ===================================================== */
+
+
+/* =========================================================================================================================== */
+/* ================ SNC ================ */
+/* =========================================================================================================================== */
+
+/* ===================================================== SNC_CTRL_REG ====================================================== */
+#define SNC_SNC_CTRL_REG_SNC_IRQ_ACK_Pos (8UL) /*!< SNC_IRQ_ACK (Bit 8) */
+#define SNC_SNC_CTRL_REG_SNC_IRQ_ACK_Msk (0x100UL) /*!< SNC_IRQ_ACK (Bitfield-Mask: 0x01) */
+#define SNC_SNC_CTRL_REG_SNC_IRQ_CONFIG_Pos (6UL) /*!< SNC_IRQ_CONFIG (Bit 6) */
+#define SNC_SNC_CTRL_REG_SNC_IRQ_CONFIG_Msk (0xc0UL) /*!< SNC_IRQ_CONFIG (Bitfield-Mask: 0x03) */
+#define SNC_SNC_CTRL_REG_SNC_IRQ_EN_Pos (5UL) /*!< SNC_IRQ_EN (Bit 5) */
+#define SNC_SNC_CTRL_REG_SNC_IRQ_EN_Msk (0x20UL) /*!< SNC_IRQ_EN (Bitfield-Mask: 0x01) */
+#define SNC_SNC_CTRL_REG_SNC_BRANCH_LOOP_INIT_Pos (4UL) /*!< SNC_BRANCH_LOOP_INIT (Bit 4) */
+#define SNC_SNC_CTRL_REG_SNC_BRANCH_LOOP_INIT_Msk (0x10UL) /*!< SNC_BRANCH_LOOP_INIT (Bitfield-Mask: 0x01) */
+#define SNC_SNC_CTRL_REG_SNC_RESET_Pos (3UL) /*!< SNC_RESET (Bit 3) */
+#define SNC_SNC_CTRL_REG_SNC_RESET_Msk (0x8UL) /*!< SNC_RESET (Bitfield-Mask: 0x01) */
+#define SNC_SNC_CTRL_REG_BUS_ERROR_DETECT_EN_Pos (2UL) /*!< BUS_ERROR_DETECT_EN (Bit 2) */
+#define SNC_SNC_CTRL_REG_BUS_ERROR_DETECT_EN_Msk (0x4UL) /*!< BUS_ERROR_DETECT_EN (Bitfield-Mask: 0x01) */
+#define SNC_SNC_CTRL_REG_SNC_SW_CTRL_Pos (1UL) /*!< SNC_SW_CTRL (Bit 1) */
+#define SNC_SNC_CTRL_REG_SNC_SW_CTRL_Msk (0x2UL) /*!< SNC_SW_CTRL (Bitfield-Mask: 0x01) */
+#define SNC_SNC_CTRL_REG_SNC_EN_Pos (0UL) /*!< SNC_EN (Bit 0) */
+#define SNC_SNC_CTRL_REG_SNC_EN_Msk (0x1UL) /*!< SNC_EN (Bitfield-Mask: 0x01) */
+/* =================================================== SNC_LP_TIMER_REG ==================================================== */
+#define SNC_SNC_LP_TIMER_REG_LP_TIMER_Pos (0UL) /*!< LP_TIMER (Bit 0) */
+#define SNC_SNC_LP_TIMER_REG_LP_TIMER_Msk (0xffUL) /*!< LP_TIMER (Bitfield-Mask: 0xff) */
+/* ====================================================== SNC_PC_REG ======================================================= */
+#define SNC_SNC_PC_REG_PC_REG_Pos (2UL) /*!< PC_REG (Bit 2) */
+#define SNC_SNC_PC_REG_PC_REG_Msk (0x7fffcUL) /*!< PC_REG (Bitfield-Mask: 0x1ffff) */
+/* ====================================================== SNC_R1_REG ======================================================= */
+#define SNC_SNC_R1_REG_R1_REG_Pos (0UL) /*!< R1_REG (Bit 0) */
+#define SNC_SNC_R1_REG_R1_REG_Msk (0xffffffffUL) /*!< R1_REG (Bitfield-Mask: 0xffffffff) */
+/* ====================================================== SNC_R2_REG ======================================================= */
+#define SNC_SNC_R2_REG_R2_REG_Pos (0UL) /*!< R2_REG (Bit 0) */
+#define SNC_SNC_R2_REG_R2_REG_Msk (0xffffffffUL) /*!< R2_REG (Bitfield-Mask: 0xffffffff) */
+/* ==================================================== SNC_STATUS_REG ===================================================== */
+#define SNC_SNC_STATUS_REG_SNC_PC_LOADED_Pos (6UL) /*!< SNC_PC_LOADED (Bit 6) */
+#define SNC_SNC_STATUS_REG_SNC_PC_LOADED_Msk (0x40UL) /*!< SNC_PC_LOADED (Bitfield-Mask: 0x01) */
+#define SNC_SNC_STATUS_REG_SNC_IS_STOPPED_Pos (5UL) /*!< SNC_IS_STOPPED (Bit 5) */
+#define SNC_SNC_STATUS_REG_SNC_IS_STOPPED_Msk (0x20UL) /*!< SNC_IS_STOPPED (Bitfield-Mask: 0x01) */
+#define SNC_SNC_STATUS_REG_HARD_FAULT_STATUS_Pos (4UL) /*!< HARD_FAULT_STATUS (Bit 4) */
+#define SNC_SNC_STATUS_REG_HARD_FAULT_STATUS_Msk (0x10UL) /*!< HARD_FAULT_STATUS (Bitfield-Mask: 0x01) */
+#define SNC_SNC_STATUS_REG_BUS_ERROR_STATUS_Pos (3UL) /*!< BUS_ERROR_STATUS (Bit 3) */
+#define SNC_SNC_STATUS_REG_BUS_ERROR_STATUS_Msk (0x8UL) /*!< BUS_ERROR_STATUS (Bitfield-Mask: 0x01) */
+#define SNC_SNC_STATUS_REG_SNC_DONE_STATUS_Pos (2UL) /*!< SNC_DONE_STATUS (Bit 2) */
+#define SNC_SNC_STATUS_REG_SNC_DONE_STATUS_Msk (0x4UL) /*!< SNC_DONE_STATUS (Bitfield-Mask: 0x01) */
+#define SNC_SNC_STATUS_REG_GR_FLAG_Pos (1UL) /*!< GR_FLAG (Bit 1) */
+#define SNC_SNC_STATUS_REG_GR_FLAG_Msk (0x2UL) /*!< GR_FLAG (Bitfield-Mask: 0x01) */
+#define SNC_SNC_STATUS_REG_EQ_FLAG_Pos (0UL) /*!< EQ_FLAG (Bit 0) */
+#define SNC_SNC_STATUS_REG_EQ_FLAG_Msk (0x1UL) /*!< EQ_FLAG (Bitfield-Mask: 0x01) */
+/* ===================================================== SNC_TMP1_REG ====================================================== */
+#define SNC_SNC_TMP1_REG_TMP1_REG_Pos (0UL) /*!< TMP1_REG (Bit 0) */
+#define SNC_SNC_TMP1_REG_TMP1_REG_Msk (0xffffffffUL) /*!< TMP1_REG (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== SNC_TMP2_REG ====================================================== */
+#define SNC_SNC_TMP2_REG_TMP2_REG_Pos (0UL) /*!< TMP2_REG (Bit 0) */
+#define SNC_SNC_TMP2_REG_TMP2_REG_Msk (0xffffffffUL) /*!< TMP2_REG (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ SPI ================ */
+/* =========================================================================================================================== */
+
+/* =================================================== SPI_CLEAR_INT_REG =================================================== */
+#define SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Pos (0UL) /*!< SPI_CLEAR_INT (Bit 0) */
+#define SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Msk (0xffffffffUL) /*!< SPI_CLEAR_INT (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== SPI_CTRL_REG ====================================================== */
+#define SPI_SPI_CTRL_REG_SPI_TX_FIFO_NOTFULL_MASK_Pos (25UL) /*!< SPI_TX_FIFO_NOTFULL_MASK (Bit 25) */
+#define SPI_SPI_CTRL_REG_SPI_TX_FIFO_NOTFULL_MASK_Msk (0x2000000UL) /*!< SPI_TX_FIFO_NOTFULL_MASK (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_DMA_TXREQ_MODE_Pos (24UL) /*!< SPI_DMA_TXREQ_MODE (Bit 24) */
+#define SPI_SPI_CTRL_REG_SPI_DMA_TXREQ_MODE_Msk (0x1000000UL) /*!< SPI_DMA_TXREQ_MODE (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_TX_FIFO_EMPTY_Pos (23UL) /*!< SPI_TX_FIFO_EMPTY (Bit 23) */
+#define SPI_SPI_CTRL_REG_SPI_TX_FIFO_EMPTY_Msk (0x800000UL) /*!< SPI_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_RX_FIFO_FULL_Pos (22UL) /*!< SPI_RX_FIFO_FULL (Bit 22) */
+#define SPI_SPI_CTRL_REG_SPI_RX_FIFO_FULL_Msk (0x400000UL) /*!< SPI_RX_FIFO_FULL (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_RX_FIFO_EMPTY_Pos (21UL) /*!< SPI_RX_FIFO_EMPTY (Bit 21) */
+#define SPI_SPI_CTRL_REG_SPI_RX_FIFO_EMPTY_Msk (0x200000UL) /*!< SPI_RX_FIFO_EMPTY (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_9BIT_VAL_Pos (20UL) /*!< SPI_9BIT_VAL (Bit 20) */
+#define SPI_SPI_CTRL_REG_SPI_9BIT_VAL_Msk (0x100000UL) /*!< SPI_9BIT_VAL (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_BUSY_Pos (19UL) /*!< SPI_BUSY (Bit 19) */
+#define SPI_SPI_CTRL_REG_SPI_BUSY_Msk (0x80000UL) /*!< SPI_BUSY (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_PRIORITY_Pos (18UL) /*!< SPI_PRIORITY (Bit 18) */
+#define SPI_SPI_CTRL_REG_SPI_PRIORITY_Msk (0x40000UL) /*!< SPI_PRIORITY (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_FIFO_MODE_Pos (16UL) /*!< SPI_FIFO_MODE (Bit 16) */
+#define SPI_SPI_CTRL_REG_SPI_FIFO_MODE_Msk (0x30000UL) /*!< SPI_FIFO_MODE (Bitfield-Mask: 0x03) */
+#define SPI_SPI_CTRL_REG_SPI_EN_CTRL_Pos (15UL) /*!< SPI_EN_CTRL (Bit 15) */
+#define SPI_SPI_CTRL_REG_SPI_EN_CTRL_Msk (0x8000UL) /*!< SPI_EN_CTRL (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_MINT_Pos (14UL) /*!< SPI_MINT (Bit 14) */
+#define SPI_SPI_CTRL_REG_SPI_MINT_Msk (0x4000UL) /*!< SPI_MINT (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_INT_BIT_Pos (13UL) /*!< SPI_INT_BIT (Bit 13) */
+#define SPI_SPI_CTRL_REG_SPI_INT_BIT_Msk (0x2000UL) /*!< SPI_INT_BIT (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_DI_Pos (12UL) /*!< SPI_DI (Bit 12) */
+#define SPI_SPI_CTRL_REG_SPI_DI_Msk (0x1000UL) /*!< SPI_DI (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_TXH_Pos (11UL) /*!< SPI_TXH (Bit 11) */
+#define SPI_SPI_CTRL_REG_SPI_TXH_Msk (0x800UL) /*!< SPI_TXH (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_FORCE_DO_Pos (10UL) /*!< SPI_FORCE_DO (Bit 10) */
+#define SPI_SPI_CTRL_REG_SPI_FORCE_DO_Msk (0x400UL) /*!< SPI_FORCE_DO (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_WORD_Pos (8UL) /*!< SPI_WORD (Bit 8) */
+#define SPI_SPI_CTRL_REG_SPI_WORD_Msk (0x300UL) /*!< SPI_WORD (Bitfield-Mask: 0x03) */
+#define SPI_SPI_CTRL_REG_SPI_RST_Pos (7UL) /*!< SPI_RST (Bit 7) */
+#define SPI_SPI_CTRL_REG_SPI_RST_Msk (0x80UL) /*!< SPI_RST (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_SMN_Pos (6UL) /*!< SPI_SMN (Bit 6) */
+#define SPI_SPI_CTRL_REG_SPI_SMN_Msk (0x40UL) /*!< SPI_SMN (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_DO_Pos (5UL) /*!< SPI_DO (Bit 5) */
+#define SPI_SPI_CTRL_REG_SPI_DO_Msk (0x20UL) /*!< SPI_DO (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_CLK_Pos (3UL) /*!< SPI_CLK (Bit 3) */
+#define SPI_SPI_CTRL_REG_SPI_CLK_Msk (0x18UL) /*!< SPI_CLK (Bitfield-Mask: 0x03) */
+#define SPI_SPI_CTRL_REG_SPI_POL_Pos (2UL) /*!< SPI_POL (Bit 2) */
+#define SPI_SPI_CTRL_REG_SPI_POL_Msk (0x4UL) /*!< SPI_POL (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_PHA_Pos (1UL) /*!< SPI_PHA (Bit 1) */
+#define SPI_SPI_CTRL_REG_SPI_PHA_Msk (0x2UL) /*!< SPI_PHA (Bitfield-Mask: 0x01) */
+#define SPI_SPI_CTRL_REG_SPI_ON_Pos (0UL) /*!< SPI_ON (Bit 0) */
+#define SPI_SPI_CTRL_REG_SPI_ON_Msk (0x1UL) /*!< SPI_ON (Bitfield-Mask: 0x01) */
+/* ===================================================== SPI_RX_TX_REG ===================================================== */
+#define SPI_SPI_RX_TX_REG_SPI_DATA_Pos (0UL) /*!< SPI_DATA (Bit 0) */
+#define SPI_SPI_RX_TX_REG_SPI_DATA_Msk (0xffffffffUL) /*!< SPI_DATA (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ SPI2 ================ */
+/* =========================================================================================================================== */
+
+/* ================================================== SPI2_CLEAR_INT_REG =================================================== */
+#define SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Pos (0UL) /*!< SPI_CLEAR_INT (Bit 0) */
+#define SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Msk (0xffffffffUL) /*!< SPI_CLEAR_INT (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== SPI2_CTRL_REG ===================================================== */
+#define SPI2_SPI2_CTRL_REG_SPI_TX_FIFO_NOTFULL_MASK_Pos (25UL) /*!< SPI_TX_FIFO_NOTFULL_MASK (Bit 25) */
+#define SPI2_SPI2_CTRL_REG_SPI_TX_FIFO_NOTFULL_MASK_Msk (0x2000000UL) /*!< SPI_TX_FIFO_NOTFULL_MASK (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_DMA_TXREQ_MODE_Pos (24UL) /*!< SPI_DMA_TXREQ_MODE (Bit 24) */
+#define SPI2_SPI2_CTRL_REG_SPI_DMA_TXREQ_MODE_Msk (0x1000000UL) /*!< SPI_DMA_TXREQ_MODE (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_TX_FIFO_EMPTY_Pos (23UL) /*!< SPI_TX_FIFO_EMPTY (Bit 23) */
+#define SPI2_SPI2_CTRL_REG_SPI_TX_FIFO_EMPTY_Msk (0x800000UL) /*!< SPI_TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_RX_FIFO_FULL_Pos (22UL) /*!< SPI_RX_FIFO_FULL (Bit 22) */
+#define SPI2_SPI2_CTRL_REG_SPI_RX_FIFO_FULL_Msk (0x400000UL) /*!< SPI_RX_FIFO_FULL (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_RX_FIFO_EMPTY_Pos (21UL) /*!< SPI_RX_FIFO_EMPTY (Bit 21) */
+#define SPI2_SPI2_CTRL_REG_SPI_RX_FIFO_EMPTY_Msk (0x200000UL) /*!< SPI_RX_FIFO_EMPTY (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_9BIT_VAL_Pos (20UL) /*!< SPI_9BIT_VAL (Bit 20) */
+#define SPI2_SPI2_CTRL_REG_SPI_9BIT_VAL_Msk (0x100000UL) /*!< SPI_9BIT_VAL (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_BUSY_Pos (19UL) /*!< SPI_BUSY (Bit 19) */
+#define SPI2_SPI2_CTRL_REG_SPI_BUSY_Msk (0x80000UL) /*!< SPI_BUSY (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_PRIORITY_Pos (18UL) /*!< SPI_PRIORITY (Bit 18) */
+#define SPI2_SPI2_CTRL_REG_SPI_PRIORITY_Msk (0x40000UL) /*!< SPI_PRIORITY (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_FIFO_MODE_Pos (16UL) /*!< SPI_FIFO_MODE (Bit 16) */
+#define SPI2_SPI2_CTRL_REG_SPI_FIFO_MODE_Msk (0x30000UL) /*!< SPI_FIFO_MODE (Bitfield-Mask: 0x03) */
+#define SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Pos (15UL) /*!< SPI_EN_CTRL (Bit 15) */
+#define SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Msk (0x8000UL) /*!< SPI_EN_CTRL (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_MINT_Pos (14UL) /*!< SPI_MINT (Bit 14) */
+#define SPI2_SPI2_CTRL_REG_SPI_MINT_Msk (0x4000UL) /*!< SPI_MINT (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Pos (13UL) /*!< SPI_INT_BIT (Bit 13) */
+#define SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Msk (0x2000UL) /*!< SPI_INT_BIT (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_DI_Pos (12UL) /*!< SPI_DI (Bit 12) */
+#define SPI2_SPI2_CTRL_REG_SPI_DI_Msk (0x1000UL) /*!< SPI_DI (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_TXH_Pos (11UL) /*!< SPI_TXH (Bit 11) */
+#define SPI2_SPI2_CTRL_REG_SPI_TXH_Msk (0x800UL) /*!< SPI_TXH (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Pos (10UL) /*!< SPI_FORCE_DO (Bit 10) */
+#define SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Msk (0x400UL) /*!< SPI_FORCE_DO (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_WORD_Pos (8UL) /*!< SPI_WORD (Bit 8) */
+#define SPI2_SPI2_CTRL_REG_SPI_WORD_Msk (0x300UL) /*!< SPI_WORD (Bitfield-Mask: 0x03) */
+#define SPI2_SPI2_CTRL_REG_SPI_RST_Pos (7UL) /*!< SPI_RST (Bit 7) */
+#define SPI2_SPI2_CTRL_REG_SPI_RST_Msk (0x80UL) /*!< SPI_RST (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_SMN_Pos (6UL) /*!< SPI_SMN (Bit 6) */
+#define SPI2_SPI2_CTRL_REG_SPI_SMN_Msk (0x40UL) /*!< SPI_SMN (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_DO_Pos (5UL) /*!< SPI_DO (Bit 5) */
+#define SPI2_SPI2_CTRL_REG_SPI_DO_Msk (0x20UL) /*!< SPI_DO (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_CLK_Pos (3UL) /*!< SPI_CLK (Bit 3) */
+#define SPI2_SPI2_CTRL_REG_SPI_CLK_Msk (0x18UL) /*!< SPI_CLK (Bitfield-Mask: 0x03) */
+#define SPI2_SPI2_CTRL_REG_SPI_POL_Pos (2UL) /*!< SPI_POL (Bit 2) */
+#define SPI2_SPI2_CTRL_REG_SPI_POL_Msk (0x4UL) /*!< SPI_POL (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_PHA_Pos (1UL) /*!< SPI_PHA (Bit 1) */
+#define SPI2_SPI2_CTRL_REG_SPI_PHA_Msk (0x2UL) /*!< SPI_PHA (Bitfield-Mask: 0x01) */
+#define SPI2_SPI2_CTRL_REG_SPI_ON_Pos (0UL) /*!< SPI_ON (Bit 0) */
+#define SPI2_SPI2_CTRL_REG_SPI_ON_Msk (0x1UL) /*!< SPI_ON (Bitfield-Mask: 0x01) */
+/* ==================================================== SPI2_RX_TX_REG ===================================================== */
+#define SPI2_SPI2_RX_TX_REG_SPI_DATA_Pos (0UL) /*!< SPI_DATA (Bit 0) */
+#define SPI2_SPI2_RX_TX_REG_SPI_DATA_Msk (0xffffffffUL) /*!< SPI_DATA (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ SYS_WDOG ================ */
+/* =========================================================================================================================== */
+
+/* =================================================== WATCHDOG_CTRL_REG =================================================== */
+#define SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Pos (3UL) /*!< WRITE_BUSY (Bit 3) */
+#define SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Msk (0x8UL) /*!< WRITE_BUSY (Bitfield-Mask: 0x01) */
+#define SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Pos (2UL) /*!< WDOG_FREEZE_EN (Bit 2) */
+#define SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Msk (0x4UL) /*!< WDOG_FREEZE_EN (Bitfield-Mask: 0x01) */
+#define SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Pos (0UL) /*!< NMI_RST (Bit 0) */
+#define SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk (0x1UL) /*!< NMI_RST (Bitfield-Mask: 0x01) */
+/* ===================================================== WATCHDOG_REG ====================================================== */
+#define SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Pos (14UL) /*!< WDOG_WEN (Bit 14) */
+#define SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Msk (0xffffc000UL) /*!< WDOG_WEN (Bitfield-Mask: 0x3ffff) */
+#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Pos (13UL) /*!< WDOG_VAL_NEG (Bit 13) */
+#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Msk (0x2000UL) /*!< WDOG_VAL_NEG (Bitfield-Mask: 0x01) */
+#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Pos (0UL) /*!< WDOG_VAL (Bit 0) */
+#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Msk (0x1fffUL) /*!< WDOG_VAL (Bitfield-Mask: 0x1fff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TIMER ================ */
+/* =========================================================================================================================== */
+
+/* ================================================ TIMER_CAPTURE_GPIO1_REG ================================================ */
+#define TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL) /*!< TIM_CAPTURE_GPIO1 (Bit 0) */
+#define TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff) */
+/* ================================================ TIMER_CAPTURE_GPIO2_REG ================================================ */
+#define TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL) /*!< TIM_CAPTURE_GPIO2 (Bit 0) */
+#define TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff) */
+/* ================================================ TIMER_CAPTURE_GPIO3_REG ================================================ */
+#define TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO3_Pos (0UL) /*!< TIM_CAPTURE_GPIO3 (Bit 0) */
+#define TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO3_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO3 (Bitfield-Mask: 0xffffff) */
+/* ================================================ TIMER_CAPTURE_GPIO4_REG ================================================ */
+#define TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO4_Pos (0UL) /*!< TIM_CAPTURE_GPIO4 (Bit 0) */
+#define TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO4_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO4 (Bitfield-Mask: 0xffffff) */
+/* ============================================== TIMER_CLEAR_GPIO_EVENT_REG =============================================== */
+#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Pos (3UL) /*!< TIM_CLEAR_GPIO4_EVENT (Bit 3) */
+#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Msk (0x8UL) /*!< TIM_CLEAR_GPIO4_EVENT (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Pos (2UL) /*!< TIM_CLEAR_GPIO3_EVENT (Bit 2) */
+#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Msk (0x4UL) /*!< TIM_CLEAR_GPIO3_EVENT (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Pos (1UL) /*!< TIM_CLEAR_GPIO2_EVENT (Bit 1) */
+#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Msk (0x2UL) /*!< TIM_CLEAR_GPIO2_EVENT (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Pos (0UL) /*!< TIM_CLEAR_GPIO1_EVENT (Bit 0) */
+#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Msk (0x1UL) /*!< TIM_CLEAR_GPIO1_EVENT (Bitfield-Mask: 0x01) */
+/* ================================================== TIMER_CLEAR_IRQ_REG ================================================== */
+#define TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */
+#define TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */
+/* ==================================================== TIMER_CTRL_REG ===================================================== */
+#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Pos (14UL) /*!< TIM_CAP_GPIO4_IRQ_EN (Bit 14) */
+#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Msk (0x4000UL) /*!< TIM_CAP_GPIO4_IRQ_EN (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Pos (13UL) /*!< TIM_CAP_GPIO3_IRQ_EN (Bit 13) */
+#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Msk (0x2000UL) /*!< TIM_CAP_GPIO3_IRQ_EN (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Pos (12UL) /*!< TIM_CAP_GPIO2_IRQ_EN (Bit 12) */
+#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Msk (0x1000UL) /*!< TIM_CAP_GPIO2_IRQ_EN (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Pos (11UL) /*!< TIM_CAP_GPIO1_IRQ_EN (Bit 11) */
+#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Msk (0x800UL) /*!< TIM_CAP_GPIO1_IRQ_EN (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Pos (10UL) /*!< TIM_IN4_EVENT_FALL_EN (Bit 10) */
+#define TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Msk (0x400UL) /*!< TIM_IN4_EVENT_FALL_EN (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Pos (9UL) /*!< TIM_IN3_EVENT_FALL_EN (Bit 9) */
+#define TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Msk (0x200UL) /*!< TIM_IN3_EVENT_FALL_EN (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */
+#define TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */
+#define TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */
+#define TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */
+#define TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */
+#define TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */
+#define TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */
+#define TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL) /*!< TIM_ONESHOT_MODE_EN (Bit 1) */
+#define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL) /*!< TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */
+#define TIMER_TIMER_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */
+/* ================================================= TIMER_GPIO1_CONF_REG ================================================== */
+#define TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */
+#define TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */
+/* ================================================= TIMER_GPIO2_CONF_REG ================================================== */
+#define TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */
+#define TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */
+/* ================================================= TIMER_GPIO3_CONF_REG ================================================== */
+#define TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Pos (0UL) /*!< TIM_GPIO3_CONF (Bit 0) */
+#define TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Msk (0x3fUL) /*!< TIM_GPIO3_CONF (Bitfield-Mask: 0x3f) */
+/* ================================================= TIMER_GPIO4_CONF_REG ================================================== */
+#define TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Pos (0UL) /*!< TIM_GPIO4_CONF (Bit 0) */
+#define TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Msk (0x3fUL) /*!< TIM_GPIO4_CONF (Bitfield-Mask: 0x3f) */
+/* ================================================== TIMER_PRESCALER_REG ================================================== */
+#define TIMER_TIMER_PRESCALER_REG_TIM_PRESCALER_Pos (0UL) /*!< TIM_PRESCALER (Bit 0) */
+#define TIMER_TIMER_PRESCALER_REG_TIM_PRESCALER_Msk (0x1fUL) /*!< TIM_PRESCALER (Bitfield-Mask: 0x1f) */
+/* ================================================ TIMER_PRESCALER_VAL_REG ================================================ */
+#define TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */
+#define TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */
+/* =================================================== TIMER_PWM_DC_REG ==================================================== */
+#define TIMER_TIMER_PWM_DC_REG_TIM_PWM_DC_Pos (0UL) /*!< TIM_PWM_DC (Bit 0) */
+#define TIMER_TIMER_PWM_DC_REG_TIM_PWM_DC_Msk (0xffffUL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */
+/* ================================================== TIMER_PWM_FREQ_REG =================================================== */
+#define TIMER_TIMER_PWM_FREQ_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */
+#define TIMER_TIMER_PWM_FREQ_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */
+/* =================================================== TIMER_RELOAD_REG ==================================================== */
+#define TIMER_TIMER_RELOAD_REG_TIM_RELOAD_Pos (0UL) /*!< TIM_RELOAD (Bit 0) */
+#define TIMER_TIMER_RELOAD_REG_TIM_RELOAD_Msk (0xffffffUL) /*!< TIM_RELOAD (Bitfield-Mask: 0xffffff) */
+/* ================================================== TIMER_SHOTWIDTH_REG ================================================== */
+#define TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Pos (0UL) /*!< TIM_SHOTWIDTH (Bit 0) */
+#define TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk (0xffffffUL) /*!< TIM_SHOTWIDTH (Bitfield-Mask: 0xffffff) */
+/* =================================================== TIMER_STATUS_REG ==================================================== */
+#define TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Pos (7UL) /*!< TIM_GPIO4_EVENT_PENDING (Bit 7) */
+#define TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Msk (0x80UL) /*!< TIM_GPIO4_EVENT_PENDING (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Pos (6UL) /*!< TIM_GPIO3_EVENT_PENDING (Bit 6) */
+#define TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Msk (0x40UL) /*!< TIM_GPIO3_EVENT_PENDING (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Pos (5UL) /*!< TIM_GPIO2_EVENT_PENDING (Bit 5) */
+#define TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Msk (0x20UL) /*!< TIM_GPIO2_EVENT_PENDING (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Pos (4UL) /*!< TIM_GPIO1_EVENT_PENDING (Bit 4) */
+#define TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Msk (0x10UL) /*!< TIM_GPIO1_EVENT_PENDING (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */
+#define TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */
+#define TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */
+#define TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */
+#define TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */
+#define TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */
+/* ================================================== TIMER_TIMER_VAL_REG ================================================== */
+#define TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL) /*!< TIM_TIMER_VALUE (Bit 0) */
+#define TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL) /*!< TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TIMER2 ================ */
+/* =========================================================================================================================== */
+
+/* =============================================== TIMER2_CAPTURE_GPIO1_REG ================================================ */
+#define TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL) /*!< TIM_CAPTURE_GPIO1 (Bit 0) */
+#define TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff) */
+/* =============================================== TIMER2_CAPTURE_GPIO2_REG ================================================ */
+#define TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL) /*!< TIM_CAPTURE_GPIO2 (Bit 0) */
+#define TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff) */
+/* ================================================= TIMER2_CLEAR_IRQ_REG ================================================== */
+#define TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */
+#define TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */
+/* ==================================================== TIMER2_CTRL_REG ==================================================== */
+#define TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL) /*!< TIM_ONESHOT_MODE_EN (Bit 1) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL) /*!< TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */
+#define TIMER2_TIMER2_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */
+/* ================================================= TIMER2_GPIO1_CONF_REG ================================================= */
+#define TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */
+#define TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */
+/* ================================================= TIMER2_GPIO2_CONF_REG ================================================= */
+#define TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */
+#define TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */
+/* ================================================= TIMER2_PRESCALER_REG ================================================== */
+#define TIMER2_TIMER2_PRESCALER_REG_TIM_PRESCALER_Pos (0UL) /*!< TIM_PRESCALER (Bit 0) */
+#define TIMER2_TIMER2_PRESCALER_REG_TIM_PRESCALER_Msk (0x1fUL) /*!< TIM_PRESCALER (Bitfield-Mask: 0x1f) */
+/* =============================================== TIMER2_PRESCALER_VAL_REG ================================================ */
+#define TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */
+#define TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */
+/* =================================================== TIMER2_PWM_DC_REG =================================================== */
+#define TIMER2_TIMER2_PWM_DC_REG_TIM_PWM_DC_Pos (0UL) /*!< TIM_PWM_DC (Bit 0) */
+#define TIMER2_TIMER2_PWM_DC_REG_TIM_PWM_DC_Msk (0xffffUL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */
+/* ================================================== TIMER2_PWM_FREQ_REG ================================================== */
+#define TIMER2_TIMER2_PWM_FREQ_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */
+#define TIMER2_TIMER2_PWM_FREQ_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */
+/* =================================================== TIMER2_RELOAD_REG =================================================== */
+#define TIMER2_TIMER2_RELOAD_REG_TIM_RELOAD_Pos (0UL) /*!< TIM_RELOAD (Bit 0) */
+#define TIMER2_TIMER2_RELOAD_REG_TIM_RELOAD_Msk (0xffffffUL) /*!< TIM_RELOAD (Bitfield-Mask: 0xffffff) */
+/* ================================================= TIMER2_SHOTWIDTH_REG ================================================== */
+#define TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH_Pos (0UL) /*!< TIM_SHOTWIDTH (Bit 0) */
+#define TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk (0xffffffUL) /*!< TIM_SHOTWIDTH (Bitfield-Mask: 0xffffff) */
+/* =================================================== TIMER2_STATUS_REG =================================================== */
+#define TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */
+#define TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */
+#define TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */
+#define TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */
+#define TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */
+#define TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */
+/* ================================================= TIMER2_TIMER_VAL_REG ================================================== */
+#define TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL) /*!< TIM_TIMER_VALUE (Bit 0) */
+#define TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL) /*!< TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TIMER3 ================ */
+/* =========================================================================================================================== */
+
+/* =============================================== TIMER3_CAPTURE_GPIO1_REG ================================================ */
+#define TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL) /*!< TIM_CAPTURE_GPIO1 (Bit 0) */
+#define TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff) */
+/* =============================================== TIMER3_CAPTURE_GPIO2_REG ================================================ */
+#define TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL) /*!< TIM_CAPTURE_GPIO2 (Bit 0) */
+#define TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff) */
+/* ================================================= TIMER3_CLEAR_IRQ_REG ================================================== */
+#define TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */
+#define TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */
+/* ==================================================== TIMER3_CTRL_REG ==================================================== */
+#define TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */
+#define TIMER3_TIMER3_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */
+/* ================================================= TIMER3_GPIO1_CONF_REG ================================================= */
+#define TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */
+#define TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */
+/* ================================================= TIMER3_GPIO2_CONF_REG ================================================= */
+#define TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */
+#define TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */
+/* ================================================= TIMER3_PRESCALER_REG ================================================== */
+#define TIMER3_TIMER3_PRESCALER_REG_TIM_PRESCALER_Pos (0UL) /*!< TIM_PRESCALER (Bit 0) */
+#define TIMER3_TIMER3_PRESCALER_REG_TIM_PRESCALER_Msk (0x1fUL) /*!< TIM_PRESCALER (Bitfield-Mask: 0x1f) */
+/* =============================================== TIMER3_PRESCALER_VAL_REG ================================================ */
+#define TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */
+#define TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */
+/* =================================================== TIMER3_PWM_DC_REG =================================================== */
+#define TIMER3_TIMER3_PWM_DC_REG_TIM_PWM_DC_Pos (0UL) /*!< TIM_PWM_DC (Bit 0) */
+#define TIMER3_TIMER3_PWM_DC_REG_TIM_PWM_DC_Msk (0xffffUL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */
+/* ================================================== TIMER3_PWM_FREQ_REG ================================================== */
+#define TIMER3_TIMER3_PWM_FREQ_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */
+#define TIMER3_TIMER3_PWM_FREQ_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */
+/* =================================================== TIMER3_RELOAD_REG =================================================== */
+#define TIMER3_TIMER3_RELOAD_REG_TIM_RELOAD_Pos (0UL) /*!< TIM_RELOAD (Bit 0) */
+#define TIMER3_TIMER3_RELOAD_REG_TIM_RELOAD_Msk (0xffffffUL) /*!< TIM_RELOAD (Bitfield-Mask: 0xffffff) */
+/* =================================================== TIMER3_STATUS_REG =================================================== */
+#define TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */
+#define TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */
+#define TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */
+#define TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */
+#define TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */
+#define TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */
+/* ================================================= TIMER3_TIMER_VAL_REG ================================================== */
+#define TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL) /*!< TIM_TIMER_VALUE (Bit 0) */
+#define TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL) /*!< TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TIMER4 ================ */
+/* =========================================================================================================================== */
+
+/* =============================================== TIMER4_CAPTURE_GPIO1_REG ================================================ */
+#define TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL) /*!< TIM_CAPTURE_GPIO1 (Bit 0) */
+#define TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff) */
+/* =============================================== TIMER4_CAPTURE_GPIO2_REG ================================================ */
+#define TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL) /*!< TIM_CAPTURE_GPIO2 (Bit 0) */
+#define TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL) /*!< TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff) */
+/* ================================================= TIMER4_CLEAR_IRQ_REG ================================================== */
+#define TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL) /*!< TIM_CLEAR_IRQ (Bit 0) */
+#define TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL) /*!< TIM_CLEAR_IRQ (Bitfield-Mask: 0x01) */
+/* ==================================================== TIMER4_CTRL_REG ==================================================== */
+#define TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Pos (8UL) /*!< TIM_CLK_EN (Bit 8) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Msk (0x100UL) /*!< TIM_CLK_EN (Bitfield-Mask: 0x01) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL) /*!< TIM_SYS_CLK_EN (Bit 7) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL) /*!< TIM_SYS_CLK_EN (Bitfield-Mask: 0x01) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL) /*!< TIM_FREE_RUN_MODE_EN (Bit 6) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL) /*!< TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Pos (5UL) /*!< TIM_IRQ_EN (Bit 5) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL) /*!< TIM_IRQ_EN (Bitfield-Mask: 0x01) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL) /*!< TIM_IN2_EVENT_FALL_EN (Bit 4) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL) /*!< TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL) /*!< TIM_IN1_EVENT_FALL_EN (Bit 3) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL) /*!< TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL) /*!< TIM_COUNT_DOWN_EN (Bit 2) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL) /*!< TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_EN_Pos (0UL) /*!< TIM_EN (Bit 0) */
+#define TIMER4_TIMER4_CTRL_REG_TIM_EN_Msk (0x1UL) /*!< TIM_EN (Bitfield-Mask: 0x01) */
+/* ================================================= TIMER4_GPIO1_CONF_REG ================================================= */
+#define TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL) /*!< TIM_GPIO1_CONF (Bit 0) */
+#define TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL) /*!< TIM_GPIO1_CONF (Bitfield-Mask: 0x3f) */
+/* ================================================= TIMER4_GPIO2_CONF_REG ================================================= */
+#define TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL) /*!< TIM_GPIO2_CONF (Bit 0) */
+#define TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL) /*!< TIM_GPIO2_CONF (Bitfield-Mask: 0x3f) */
+/* ================================================= TIMER4_PRESCALER_REG ================================================== */
+#define TIMER4_TIMER4_PRESCALER_REG_TIM_PRESCALER_Pos (0UL) /*!< TIM_PRESCALER (Bit 0) */
+#define TIMER4_TIMER4_PRESCALER_REG_TIM_PRESCALER_Msk (0x1fUL) /*!< TIM_PRESCALER (Bitfield-Mask: 0x1f) */
+/* =============================================== TIMER4_PRESCALER_VAL_REG ================================================ */
+#define TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL) /*!< TIM_PRESCALER_VAL (Bit 0) */
+#define TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL) /*!< TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f) */
+/* =================================================== TIMER4_PWM_DC_REG =================================================== */
+#define TIMER4_TIMER4_PWM_DC_REG_TIM_PWM_DC_Pos (0UL) /*!< TIM_PWM_DC (Bit 0) */
+#define TIMER4_TIMER4_PWM_DC_REG_TIM_PWM_DC_Msk (0xffffUL) /*!< TIM_PWM_DC (Bitfield-Mask: 0xffff) */
+/* ================================================== TIMER4_PWM_FREQ_REG ================================================== */
+#define TIMER4_TIMER4_PWM_FREQ_REG_TIM_PWM_FREQ_Pos (0UL) /*!< TIM_PWM_FREQ (Bit 0) */
+#define TIMER4_TIMER4_PWM_FREQ_REG_TIM_PWM_FREQ_Msk (0xffffUL) /*!< TIM_PWM_FREQ (Bitfield-Mask: 0xffff) */
+/* =================================================== TIMER4_RELOAD_REG =================================================== */
+#define TIMER4_TIMER4_RELOAD_REG_TIM_RELOAD_Pos (0UL) /*!< TIM_RELOAD (Bit 0) */
+#define TIMER4_TIMER4_RELOAD_REG_TIM_RELOAD_Msk (0xffffffUL) /*!< TIM_RELOAD (Bitfield-Mask: 0xffffff) */
+/* =================================================== TIMER4_STATUS_REG =================================================== */
+#define TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL) /*!< TIM_ONESHOT_PHASE (Bit 2) */
+#define TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL) /*!< TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03) */
+#define TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Pos (1UL) /*!< TIM_IN2_STATE (Bit 1) */
+#define TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL) /*!< TIM_IN2_STATE (Bitfield-Mask: 0x01) */
+#define TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Pos (0UL) /*!< TIM_IN1_STATE (Bit 0) */
+#define TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL) /*!< TIM_IN1_STATE (Bitfield-Mask: 0x01) */
+/* ================================================= TIMER4_TIMER_VAL_REG ================================================== */
+#define TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL) /*!< TIM_TIMER_VALUE (Bit 0) */
+#define TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL) /*!< TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TRNG ================ */
+/* =========================================================================================================================== */
+
+/* ===================================================== TRNG_CTRL_REG ===================================================== */
+#define TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Pos (0UL) /*!< TRNG_ENABLE (Bit 0) */
+#define TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Msk (0x1UL) /*!< TRNG_ENABLE (Bitfield-Mask: 0x01) */
+/* =================================================== TRNG_FIFOLVL_REG ==================================================== */
+#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Pos (5UL) /*!< TRNG_FIFOFULL (Bit 5) */
+#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Msk (0x20UL) /*!< TRNG_FIFOFULL (Bitfield-Mask: 0x01) */
+#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Pos (0UL) /*!< TRNG_FIFOLVL (Bit 0) */
+#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Msk (0x1fUL) /*!< TRNG_FIFOLVL (Bitfield-Mask: 0x1f) */
+/* ===================================================== TRNG_VER_REG ====================================================== */
+#define TRNG_TRNG_VER_REG_TRNG_MAJ_Pos (24UL) /*!< TRNG_MAJ (Bit 24) */
+#define TRNG_TRNG_VER_REG_TRNG_MAJ_Msk (0xff000000UL) /*!< TRNG_MAJ (Bitfield-Mask: 0xff) */
+#define TRNG_TRNG_VER_REG_TRNG_MIN_Pos (16UL) /*!< TRNG_MIN (Bit 16) */
+#define TRNG_TRNG_VER_REG_TRNG_MIN_Msk (0xff0000UL) /*!< TRNG_MIN (Bitfield-Mask: 0xff) */
+#define TRNG_TRNG_VER_REG_TRNG_SVN_Pos (0UL) /*!< TRNG_SVN (Bit 0) */
+#define TRNG_TRNG_VER_REG_TRNG_SVN_Msk (0xffffUL) /*!< TRNG_SVN (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ UART ================ */
+/* =========================================================================================================================== */
+
+/* ===================================================== UART_CTR_REG ====================================================== */
+#define UART_UART_CTR_REG_UART_CTR_Pos (0UL) /*!< UART_CTR (Bit 0) */
+#define UART_UART_CTR_REG_UART_CTR_Msk (0xffffffffUL) /*!< UART_CTR (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== UART_DLF_REG ====================================================== */
+#define UART_UART_DLF_REG_UART_DLF_Pos (0UL) /*!< UART_DLF (Bit 0) */
+#define UART_UART_DLF_REG_UART_DLF_Msk (0xfUL) /*!< UART_DLF (Bitfield-Mask: 0x0f) */
+/* ==================================================== UART_DMASA_REG ===================================================== */
+#define UART_UART_DMASA_REG_UART_DMASA_Pos (0UL) /*!< UART_DMASA (Bit 0) */
+#define UART_UART_DMASA_REG_UART_DMASA_Msk (0x1UL) /*!< UART_DMASA (Bitfield-Mask: 0x01) */
+/* ===================================================== UART_HTX_REG ====================================================== */
+#define UART_UART_HTX_REG_UART_HALT_TX_Pos (0UL) /*!< UART_HALT_TX (Bit 0) */
+#define UART_UART_HTX_REG_UART_HALT_TX_Msk (0x1UL) /*!< UART_HALT_TX (Bitfield-Mask: 0x01) */
+/* =================================================== UART_IER_DLH_REG ==================================================== */
+#define UART_UART_IER_DLH_REG_PTIME_DLH7_Pos (7UL) /*!< PTIME_DLH7 (Bit 7) */
+#define UART_UART_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL) /*!< PTIME_DLH7 (Bitfield-Mask: 0x01) */
+#define UART_UART_IER_DLH_REG_DLH6_5_Pos (5UL) /*!< DLH6_5 (Bit 5) */
+#define UART_UART_IER_DLH_REG_DLH6_5_Msk (0x60UL) /*!< DLH6_5 (Bitfield-Mask: 0x03) */
+#define UART_UART_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL) /*!< ELCOLR_DLH4 (Bit 4) */
+#define UART_UART_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL) /*!< ELCOLR_DLH4 (Bitfield-Mask: 0x01) */
+#define UART_UART_IER_DLH_REG_EDSSI_DLH3_Pos (3UL) /*!< EDSSI_DLH3 (Bit 3) */
+#define UART_UART_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL) /*!< EDSSI_DLH3 (Bitfield-Mask: 0x01) */
+#define UART_UART_IER_DLH_REG_ELSI_DLH2_Pos (2UL) /*!< ELSI_DLH2 (Bit 2) */
+#define UART_UART_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL) /*!< ELSI_DLH2 (Bitfield-Mask: 0x01) */
+#define UART_UART_IER_DLH_REG_ETBEI_DLH1_Pos (1UL) /*!< ETBEI_DLH1 (Bit 1) */
+#define UART_UART_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL) /*!< ETBEI_DLH1 (Bitfield-Mask: 0x01) */
+#define UART_UART_IER_DLH_REG_ERBFI_DLH0_Pos (0UL) /*!< ERBFI_DLH0 (Bit 0) */
+#define UART_UART_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL) /*!< ERBFI_DLH0 (Bitfield-Mask: 0x01) */
+/* =================================================== UART_IIR_FCR_REG ==================================================== */
+#define UART_UART_IIR_FCR_REG_IIR_FCR_Pos (0UL) /*!< IIR_FCR (Bit 0) */
+#define UART_UART_IIR_FCR_REG_IIR_FCR_Msk (0xffUL) /*!< IIR_FCR (Bitfield-Mask: 0xff) */
+/* ===================================================== UART_LCR_REG ====================================================== */
+#define UART_UART_LCR_REG_UART_DLAB_Pos (7UL) /*!< UART_DLAB (Bit 7) */
+#define UART_UART_LCR_REG_UART_DLAB_Msk (0x80UL) /*!< UART_DLAB (Bitfield-Mask: 0x01) */
+#define UART_UART_LCR_REG_UART_BC_Pos (6UL) /*!< UART_BC (Bit 6) */
+#define UART_UART_LCR_REG_UART_BC_Msk (0x40UL) /*!< UART_BC (Bitfield-Mask: 0x01) */
+#define UART_UART_LCR_REG_UART_EPS_Pos (4UL) /*!< UART_EPS (Bit 4) */
+#define UART_UART_LCR_REG_UART_EPS_Msk (0x10UL) /*!< UART_EPS (Bitfield-Mask: 0x01) */
+#define UART_UART_LCR_REG_UART_PEN_Pos (3UL) /*!< UART_PEN (Bit 3) */
+#define UART_UART_LCR_REG_UART_PEN_Msk (0x8UL) /*!< UART_PEN (Bitfield-Mask: 0x01) */
+#define UART_UART_LCR_REG_UART_STOP_Pos (2UL) /*!< UART_STOP (Bit 2) */
+#define UART_UART_LCR_REG_UART_STOP_Msk (0x4UL) /*!< UART_STOP (Bitfield-Mask: 0x01) */
+#define UART_UART_LCR_REG_UART_DLS_Pos (0UL) /*!< UART_DLS (Bit 0) */
+#define UART_UART_LCR_REG_UART_DLS_Msk (0x3UL) /*!< UART_DLS (Bitfield-Mask: 0x03) */
+/* ===================================================== UART_LSR_REG ====================================================== */
+#define UART_UART_LSR_REG_UART_RFE_Pos (7UL) /*!< UART_RFE (Bit 7) */
+#define UART_UART_LSR_REG_UART_RFE_Msk (0x80UL) /*!< UART_RFE (Bitfield-Mask: 0x01) */
+#define UART_UART_LSR_REG_UART_TEMT_Pos (6UL) /*!< UART_TEMT (Bit 6) */
+#define UART_UART_LSR_REG_UART_TEMT_Msk (0x40UL) /*!< UART_TEMT (Bitfield-Mask: 0x01) */
+#define UART_UART_LSR_REG_UART_THRE_Pos (5UL) /*!< UART_THRE (Bit 5) */
+#define UART_UART_LSR_REG_UART_THRE_Msk (0x20UL) /*!< UART_THRE (Bitfield-Mask: 0x01) */
+#define UART_UART_LSR_REG_UART_BI_Pos (4UL) /*!< UART_BI (Bit 4) */
+#define UART_UART_LSR_REG_UART_BI_Msk (0x10UL) /*!< UART_BI (Bitfield-Mask: 0x01) */
+#define UART_UART_LSR_REG_UART_FE_Pos (3UL) /*!< UART_FE (Bit 3) */
+#define UART_UART_LSR_REG_UART_FE_Msk (0x8UL) /*!< UART_FE (Bitfield-Mask: 0x01) */
+#define UART_UART_LSR_REG_UART_PE_Pos (2UL) /*!< UART_PE (Bit 2) */
+#define UART_UART_LSR_REG_UART_PE_Msk (0x4UL) /*!< UART_PE (Bitfield-Mask: 0x01) */
+#define UART_UART_LSR_REG_UART_OE_Pos (1UL) /*!< UART_OE (Bit 1) */
+#define UART_UART_LSR_REG_UART_OE_Msk (0x2UL) /*!< UART_OE (Bitfield-Mask: 0x01) */
+#define UART_UART_LSR_REG_UART_DR_Pos (0UL) /*!< UART_DR (Bit 0) */
+#define UART_UART_LSR_REG_UART_DR_Msk (0x1UL) /*!< UART_DR (Bitfield-Mask: 0x01) */
+/* ===================================================== UART_MCR_REG ====================================================== */
+#define UART_UART_MCR_REG_UART_LB_Pos (4UL) /*!< UART_LB (Bit 4) */
+#define UART_UART_MCR_REG_UART_LB_Msk (0x10UL) /*!< UART_LB (Bitfield-Mask: 0x01) */
+/* ================================================= UART_RBR_THR_DLL_REG ================================================== */
+#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL) /*!< RBR_THR_DLL (Bit 0) */
+#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL) /*!< RBR_THR_DLL (Bitfield-Mask: 0xff) */
+/* ===================================================== UART_RFL_REG ====================================================== */
+#define UART_UART_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL) /*!< UART_RECEIVE_FIFO_LEVEL (Bit 0) */
+#define UART_UART_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL) /*!< UART_RECEIVE_FIFO_LEVEL (Bitfield-Mask: 0x1f) */
+/* ===================================================== UART_SBCR_REG ===================================================== */
+#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL) /*!< UART_SHADOW_BREAK_CONTROL (Bit 0) */
+#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL) /*!< UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01) */
+/* ===================================================== UART_SCR_REG ====================================================== */
+#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Pos (0UL) /*!< UART_SCRATCH_PAD (Bit 0) */
+#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Msk (0xffUL) /*!< UART_SCRATCH_PAD (Bitfield-Mask: 0xff) */
+/* ==================================================== UART_SDMAM_REG ===================================================== */
+#define UART_UART_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL) /*!< UART_SHADOW_DMA_MODE (Bit 0) */
+#define UART_UART_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL) /*!< UART_SHADOW_DMA_MODE (Bitfield-Mask: 0x01) */
+/* ===================================================== UART_SFE_REG ====================================================== */
+#define UART_UART_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL) /*!< UART_SHADOW_FIFO_ENABLE (Bit 0) */
+#define UART_UART_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL) /*!< UART_SHADOW_FIFO_ENABLE (Bitfield-Mask: 0x01) */
+/* ================================================== UART_SRBR_STHR0_REG ================================================== */
+#define UART_UART_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART_SRBR_STHR10_REG ================================================== */
+#define UART_UART_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART_SRBR_STHR11_REG ================================================== */
+#define UART_UART_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART_SRBR_STHR12_REG ================================================== */
+#define UART_UART_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART_SRBR_STHR13_REG ================================================== */
+#define UART_UART_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART_SRBR_STHR14_REG ================================================== */
+#define UART_UART_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART_SRBR_STHR15_REG ================================================== */
+#define UART_UART_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================== UART_SRBR_STHR1_REG ================================================== */
+#define UART_UART_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================== UART_SRBR_STHR2_REG ================================================== */
+#define UART_UART_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================== UART_SRBR_STHR3_REG ================================================== */
+#define UART_UART_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================== UART_SRBR_STHR4_REG ================================================== */
+#define UART_UART_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================== UART_SRBR_STHR5_REG ================================================== */
+#define UART_UART_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================== UART_SRBR_STHR6_REG ================================================== */
+#define UART_UART_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================== UART_SRBR_STHR7_REG ================================================== */
+#define UART_UART_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================== UART_SRBR_STHR8_REG ================================================== */
+#define UART_UART_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================== UART_SRBR_STHR9_REG ================================================== */
+#define UART_UART_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART_UART_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ===================================================== UART_SRR_REG ====================================================== */
+#define UART_UART_SRR_REG_UART_XFR_Pos (2UL) /*!< UART_XFR (Bit 2) */
+#define UART_UART_SRR_REG_UART_XFR_Msk (0x4UL) /*!< UART_XFR (Bitfield-Mask: 0x01) */
+#define UART_UART_SRR_REG_UART_RFR_Pos (1UL) /*!< UART_RFR (Bit 1) */
+#define UART_UART_SRR_REG_UART_RFR_Msk (0x2UL) /*!< UART_RFR (Bitfield-Mask: 0x01) */
+#define UART_UART_SRR_REG_UART_UR_Pos (0UL) /*!< UART_UR (Bit 0) */
+#define UART_UART_SRR_REG_UART_UR_Msk (0x1UL) /*!< UART_UR (Bitfield-Mask: 0x01) */
+/* ===================================================== UART_SRT_REG ====================================================== */
+#define UART_UART_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL) /*!< UART_SHADOW_RCVR_TRIGGER (Bit 0) */
+#define UART_UART_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_RCVR_TRIGGER (Bitfield-Mask: 0x03) */
+/* ===================================================== UART_STET_REG ===================================================== */
+#define UART_UART_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bit 0) */
+#define UART_UART_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bitfield-Mask: 0x03) */
+/* ===================================================== UART_TFL_REG ====================================================== */
+#define UART_UART_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL) /*!< UART_TRANSMIT_FIFO_LEVEL (Bit 0) */
+#define UART_UART_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL) /*!< UART_TRANSMIT_FIFO_LEVEL (Bitfield-Mask: 0x1f) */
+/* ===================================================== UART_UCV_REG ====================================================== */
+#define UART_UART_UCV_REG_UART_UCV_Pos (0UL) /*!< UART_UCV (Bit 0) */
+#define UART_UART_UCV_REG_UART_UCV_Msk (0xffffffffUL) /*!< UART_UCV (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== UART_USR_REG ====================================================== */
+#define UART_UART_USR_REG_UART_RFF_Pos (4UL) /*!< UART_RFF (Bit 4) */
+#define UART_UART_USR_REG_UART_RFF_Msk (0x10UL) /*!< UART_RFF (Bitfield-Mask: 0x01) */
+#define UART_UART_USR_REG_UART_RFNE_Pos (3UL) /*!< UART_RFNE (Bit 3) */
+#define UART_UART_USR_REG_UART_RFNE_Msk (0x8UL) /*!< UART_RFNE (Bitfield-Mask: 0x01) */
+#define UART_UART_USR_REG_UART_TFE_Pos (2UL) /*!< UART_TFE (Bit 2) */
+#define UART_UART_USR_REG_UART_TFE_Msk (0x4UL) /*!< UART_TFE (Bitfield-Mask: 0x01) */
+#define UART_UART_USR_REG_UART_TFNF_Pos (1UL) /*!< UART_TFNF (Bit 1) */
+#define UART_UART_USR_REG_UART_TFNF_Msk (0x2UL) /*!< UART_TFNF (Bitfield-Mask: 0x01) */
+#define UART_UART_USR_REG_UART_BUSY_Pos (0UL) /*!< UART_BUSY (Bit 0) */
+#define UART_UART_USR_REG_UART_BUSY_Msk (0x1UL) /*!< UART_BUSY (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ UART2 ================ */
+/* =========================================================================================================================== */
+
+/* ===================================================== UART2_CTR_REG ===================================================== */
+#define UART2_UART2_CTR_REG_UART_CTR_Pos (0UL) /*!< UART_CTR (Bit 0) */
+#define UART2_UART2_CTR_REG_UART_CTR_Msk (0xffffffffUL) /*!< UART_CTR (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== UART2_DLF_REG ===================================================== */
+#define UART2_UART2_DLF_REG_UART_DLF_Pos (0UL) /*!< UART_DLF (Bit 0) */
+#define UART2_UART2_DLF_REG_UART_DLF_Msk (0xfUL) /*!< UART_DLF (Bitfield-Mask: 0x0f) */
+/* ==================================================== UART2_DMASA_REG ==================================================== */
+#define UART2_UART2_DMASA_REG_UART_DMASA_Pos (0UL) /*!< UART_DMASA (Bit 0) */
+#define UART2_UART2_DMASA_REG_UART_DMASA_Msk (0x1UL) /*!< UART_DMASA (Bitfield-Mask: 0x01) */
+/* ===================================================== UART2_HTX_REG ===================================================== */
+#define UART2_UART2_HTX_REG_UART_HALT_TX_Pos (0UL) /*!< UART_HALT_TX (Bit 0) */
+#define UART2_UART2_HTX_REG_UART_HALT_TX_Msk (0x1UL) /*!< UART_HALT_TX (Bitfield-Mask: 0x01) */
+/* =================================================== UART2_IER_DLH_REG =================================================== */
+#define UART2_UART2_IER_DLH_REG_PTIME_DLH7_Pos (7UL) /*!< PTIME_DLH7 (Bit 7) */
+#define UART2_UART2_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL) /*!< PTIME_DLH7 (Bitfield-Mask: 0x01) */
+#define UART2_UART2_IER_DLH_REG_DLH6_5_Pos (5UL) /*!< DLH6_5 (Bit 5) */
+#define UART2_UART2_IER_DLH_REG_DLH6_5_Msk (0x60UL) /*!< DLH6_5 (Bitfield-Mask: 0x03) */
+#define UART2_UART2_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL) /*!< ELCOLR_DLH4 (Bit 4) */
+#define UART2_UART2_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL) /*!< ELCOLR_DLH4 (Bitfield-Mask: 0x01) */
+#define UART2_UART2_IER_DLH_REG_EDSSI_DLH3_Pos (3UL) /*!< EDSSI_DLH3 (Bit 3) */
+#define UART2_UART2_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL) /*!< EDSSI_DLH3 (Bitfield-Mask: 0x01) */
+#define UART2_UART2_IER_DLH_REG_ELSI_DLH2_Pos (2UL) /*!< ELSI_DLH2 (Bit 2) */
+#define UART2_UART2_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL) /*!< ELSI_DLH2 (Bitfield-Mask: 0x01) */
+#define UART2_UART2_IER_DLH_REG_ETBEI_DLH1_Pos (1UL) /*!< ETBEI_DLH1 (Bit 1) */
+#define UART2_UART2_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL) /*!< ETBEI_DLH1 (Bitfield-Mask: 0x01) */
+#define UART2_UART2_IER_DLH_REG_ERBFI_DLH0_Pos (0UL) /*!< ERBFI_DLH0 (Bit 0) */
+#define UART2_UART2_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL) /*!< ERBFI_DLH0 (Bitfield-Mask: 0x01) */
+/* =================================================== UART2_IIR_FCR_REG =================================================== */
+#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Pos (0UL) /*!< IIR_FCR (Bit 0) */
+#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Msk (0xffUL) /*!< IIR_FCR (Bitfield-Mask: 0xff) */
+/* ===================================================== UART2_LCR_EXT ===================================================== */
+#define UART2_UART2_LCR_EXT_UART_TRANSMIT_MODE_Pos (3UL) /*!< UART_TRANSMIT_MODE (Bit 3) */
+#define UART2_UART2_LCR_EXT_UART_TRANSMIT_MODE_Msk (0x8UL) /*!< UART_TRANSMIT_MODE (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LCR_EXT_UART_SEND_ADDR_Pos (2UL) /*!< UART_SEND_ADDR (Bit 2) */
+#define UART2_UART2_LCR_EXT_UART_SEND_ADDR_Msk (0x4UL) /*!< UART_SEND_ADDR (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LCR_EXT_UART_ADDR_MATCH_Pos (1UL) /*!< UART_ADDR_MATCH (Bit 1) */
+#define UART2_UART2_LCR_EXT_UART_ADDR_MATCH_Msk (0x2UL) /*!< UART_ADDR_MATCH (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LCR_EXT_UART_DLS_E_Pos (0UL) /*!< UART_DLS_E (Bit 0) */
+#define UART2_UART2_LCR_EXT_UART_DLS_E_Msk (0x1UL) /*!< UART_DLS_E (Bitfield-Mask: 0x01) */
+/* ===================================================== UART2_LCR_REG ===================================================== */
+#define UART2_UART2_LCR_REG_UART_DLAB_Pos (7UL) /*!< UART_DLAB (Bit 7) */
+#define UART2_UART2_LCR_REG_UART_DLAB_Msk (0x80UL) /*!< UART_DLAB (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LCR_REG_UART_BC_Pos (6UL) /*!< UART_BC (Bit 6) */
+#define UART2_UART2_LCR_REG_UART_BC_Msk (0x40UL) /*!< UART_BC (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LCR_REG_UART_SP_Pos (5UL) /*!< UART_SP (Bit 5) */
+#define UART2_UART2_LCR_REG_UART_SP_Msk (0x20UL) /*!< UART_SP (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LCR_REG_UART_EPS_Pos (4UL) /*!< UART_EPS (Bit 4) */
+#define UART2_UART2_LCR_REG_UART_EPS_Msk (0x10UL) /*!< UART_EPS (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LCR_REG_UART_PEN_Pos (3UL) /*!< UART_PEN (Bit 3) */
+#define UART2_UART2_LCR_REG_UART_PEN_Msk (0x8UL) /*!< UART_PEN (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LCR_REG_UART_STOP_Pos (2UL) /*!< UART_STOP (Bit 2) */
+#define UART2_UART2_LCR_REG_UART_STOP_Msk (0x4UL) /*!< UART_STOP (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LCR_REG_UART_DLS_Pos (0UL) /*!< UART_DLS (Bit 0) */
+#define UART2_UART2_LCR_REG_UART_DLS_Msk (0x3UL) /*!< UART_DLS (Bitfield-Mask: 0x03) */
+/* ===================================================== UART2_LSR_REG ===================================================== */
+#define UART2_UART2_LSR_REG_UART_ADDR_RCVD_Pos (8UL) /*!< UART_ADDR_RCVD (Bit 8) */
+#define UART2_UART2_LSR_REG_UART_ADDR_RCVD_Msk (0x100UL) /*!< UART_ADDR_RCVD (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LSR_REG_UART_RFE_Pos (7UL) /*!< UART_RFE (Bit 7) */
+#define UART2_UART2_LSR_REG_UART_RFE_Msk (0x80UL) /*!< UART_RFE (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LSR_REG_UART_TEMT_Pos (6UL) /*!< UART_TEMT (Bit 6) */
+#define UART2_UART2_LSR_REG_UART_TEMT_Msk (0x40UL) /*!< UART_TEMT (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LSR_REG_UART_THRE_Pos (5UL) /*!< UART_THRE (Bit 5) */
+#define UART2_UART2_LSR_REG_UART_THRE_Msk (0x20UL) /*!< UART_THRE (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LSR_REG_UART_BI_Pos (4UL) /*!< UART_BI (Bit 4) */
+#define UART2_UART2_LSR_REG_UART_BI_Msk (0x10UL) /*!< UART_BI (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LSR_REG_UART_FE_Pos (3UL) /*!< UART_FE (Bit 3) */
+#define UART2_UART2_LSR_REG_UART_FE_Msk (0x8UL) /*!< UART_FE (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LSR_REG_UART_PE_Pos (2UL) /*!< UART_PE (Bit 2) */
+#define UART2_UART2_LSR_REG_UART_PE_Msk (0x4UL) /*!< UART_PE (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LSR_REG_UART_OE_Pos (1UL) /*!< UART_OE (Bit 1) */
+#define UART2_UART2_LSR_REG_UART_OE_Msk (0x2UL) /*!< UART_OE (Bitfield-Mask: 0x01) */
+#define UART2_UART2_LSR_REG_UART_DR_Pos (0UL) /*!< UART_DR (Bit 0) */
+#define UART2_UART2_LSR_REG_UART_DR_Msk (0x1UL) /*!< UART_DR (Bitfield-Mask: 0x01) */
+/* ===================================================== UART2_MCR_REG ===================================================== */
+#define UART2_UART2_MCR_REG_UART_AFCE_Pos (5UL) /*!< UART_AFCE (Bit 5) */
+#define UART2_UART2_MCR_REG_UART_AFCE_Msk (0x20UL) /*!< UART_AFCE (Bitfield-Mask: 0x01) */
+#define UART2_UART2_MCR_REG_UART_LB_Pos (4UL) /*!< UART_LB (Bit 4) */
+#define UART2_UART2_MCR_REG_UART_LB_Msk (0x10UL) /*!< UART_LB (Bitfield-Mask: 0x01) */
+#define UART2_UART2_MCR_REG_UART_RTS_Pos (1UL) /*!< UART_RTS (Bit 1) */
+#define UART2_UART2_MCR_REG_UART_RTS_Msk (0x2UL) /*!< UART_RTS (Bitfield-Mask: 0x01) */
+/* ===================================================== UART2_MSR_REG ===================================================== */
+#define UART2_UART2_MSR_REG_UART_CTS_Pos (4UL) /*!< UART_CTS (Bit 4) */
+#define UART2_UART2_MSR_REG_UART_CTS_Msk (0x10UL) /*!< UART_CTS (Bitfield-Mask: 0x01) */
+#define UART2_UART2_MSR_REG_UART_DCTS_Pos (0UL) /*!< UART_DCTS (Bit 0) */
+#define UART2_UART2_MSR_REG_UART_DCTS_Msk (0x1UL) /*!< UART_DCTS (Bitfield-Mask: 0x01) */
+/* ===================================================== UART2_RAR_REG ===================================================== */
+#define UART2_UART2_RAR_REG_UART_RAR_Pos (0UL) /*!< UART_RAR (Bit 0) */
+#define UART2_UART2_RAR_REG_UART_RAR_Msk (0xffUL) /*!< UART_RAR (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_RBR_THR_DLL_REG ================================================= */
+#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_9BIT_Pos (8UL) /*!< RBR_THR_9BIT (Bit 8) */
+#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_9BIT_Msk (0x100UL) /*!< RBR_THR_9BIT (Bitfield-Mask: 0x01) */
+#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL) /*!< RBR_THR_DLL (Bit 0) */
+#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL) /*!< RBR_THR_DLL (Bitfield-Mask: 0xff) */
+/* ===================================================== UART2_RFL_REG ===================================================== */
+#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL) /*!< UART_RECEIVE_FIFO_LEVEL (Bit 0) */
+#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL) /*!< UART_RECEIVE_FIFO_LEVEL (Bitfield-Mask: 0x1f) */
+/* ==================================================== UART2_SBCR_REG ===================================================== */
+#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL) /*!< UART_SHADOW_BREAK_CONTROL (Bit 0) */
+#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL) /*!< UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01) */
+/* ===================================================== UART2_SCR_REG ===================================================== */
+#define UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Pos (0UL) /*!< UART_SCRATCH_PAD (Bit 0) */
+#define UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Msk (0xffUL) /*!< UART_SCRATCH_PAD (Bitfield-Mask: 0xff) */
+/* ==================================================== UART2_SDMAM_REG ==================================================== */
+#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL) /*!< UART_SHADOW_DMA_MODE (Bit 0) */
+#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL) /*!< UART_SHADOW_DMA_MODE (Bitfield-Mask: 0x01) */
+/* ===================================================== UART2_SFE_REG ===================================================== */
+#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL) /*!< UART_SHADOW_FIFO_ENABLE (Bit 0) */
+#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL) /*!< UART_SHADOW_FIFO_ENABLE (Bitfield-Mask: 0x01) */
+/* ================================================= UART2_SRBR_STHR0_REG ================================================== */
+#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR10_REG ================================================= */
+#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR11_REG ================================================= */
+#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR12_REG ================================================= */
+#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR13_REG ================================================= */
+#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR14_REG ================================================= */
+#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR15_REG ================================================= */
+#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR1_REG ================================================== */
+#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR2_REG ================================================== */
+#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR3_REG ================================================== */
+#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR4_REG ================================================== */
+#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR5_REG ================================================== */
+#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR6_REG ================================================== */
+#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR7_REG ================================================== */
+#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR8_REG ================================================== */
+#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART2_SRBR_STHR9_REG ================================================== */
+#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ===================================================== UART2_SRR_REG ===================================================== */
+#define UART2_UART2_SRR_REG_UART_XFR_Pos (2UL) /*!< UART_XFR (Bit 2) */
+#define UART2_UART2_SRR_REG_UART_XFR_Msk (0x4UL) /*!< UART_XFR (Bitfield-Mask: 0x01) */
+#define UART2_UART2_SRR_REG_UART_RFR_Pos (1UL) /*!< UART_RFR (Bit 1) */
+#define UART2_UART2_SRR_REG_UART_RFR_Msk (0x2UL) /*!< UART_RFR (Bitfield-Mask: 0x01) */
+#define UART2_UART2_SRR_REG_UART_UR_Pos (0UL) /*!< UART_UR (Bit 0) */
+#define UART2_UART2_SRR_REG_UART_UR_Msk (0x1UL) /*!< UART_UR (Bitfield-Mask: 0x01) */
+/* ==================================================== UART2_SRTS_REG ===================================================== */
+#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos (0UL) /*!< UART_SHADOW_REQUEST_TO_SEND (Bit 0) */
+#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk (0x1UL) /*!< UART_SHADOW_REQUEST_TO_SEND (Bitfield-Mask: 0x01) */
+/* ===================================================== UART2_SRT_REG ===================================================== */
+#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL) /*!< UART_SHADOW_RCVR_TRIGGER (Bit 0) */
+#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_RCVR_TRIGGER (Bitfield-Mask: 0x03) */
+/* ==================================================== UART2_STET_REG ===================================================== */
+#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bit 0) */
+#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bitfield-Mask: 0x03) */
+/* ===================================================== UART2_TAR_REG ===================================================== */
+#define UART2_UART2_TAR_REG_UART_TAR_Pos (0UL) /*!< UART_TAR (Bit 0) */
+#define UART2_UART2_TAR_REG_UART_TAR_Msk (0xffUL) /*!< UART_TAR (Bitfield-Mask: 0xff) */
+/* ===================================================== UART2_TFL_REG ===================================================== */
+#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL) /*!< UART_TRANSMIT_FIFO_LEVEL (Bit 0) */
+#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL) /*!< UART_TRANSMIT_FIFO_LEVEL (Bitfield-Mask: 0x1f) */
+/* ===================================================== UART2_UCV_REG ===================================================== */
+#define UART2_UART2_UCV_REG_UART_UCV_Pos (0UL) /*!< UART_UCV (Bit 0) */
+#define UART2_UART2_UCV_REG_UART_UCV_Msk (0xffffffffUL) /*!< UART_UCV (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== UART2_USR_REG ===================================================== */
+#define UART2_UART2_USR_REG_UART_RFF_Pos (4UL) /*!< UART_RFF (Bit 4) */
+#define UART2_UART2_USR_REG_UART_RFF_Msk (0x10UL) /*!< UART_RFF (Bitfield-Mask: 0x01) */
+#define UART2_UART2_USR_REG_UART_RFNE_Pos (3UL) /*!< UART_RFNE (Bit 3) */
+#define UART2_UART2_USR_REG_UART_RFNE_Msk (0x8UL) /*!< UART_RFNE (Bitfield-Mask: 0x01) */
+#define UART2_UART2_USR_REG_UART_TFE_Pos (2UL) /*!< UART_TFE (Bit 2) */
+#define UART2_UART2_USR_REG_UART_TFE_Msk (0x4UL) /*!< UART_TFE (Bitfield-Mask: 0x01) */
+#define UART2_UART2_USR_REG_UART_TFNF_Pos (1UL) /*!< UART_TFNF (Bit 1) */
+#define UART2_UART2_USR_REG_UART_TFNF_Msk (0x2UL) /*!< UART_TFNF (Bitfield-Mask: 0x01) */
+#define UART2_UART2_USR_REG_UART_BUSY_Pos (0UL) /*!< UART_BUSY (Bit 0) */
+#define UART2_UART2_USR_REG_UART_BUSY_Msk (0x1UL) /*!< UART_BUSY (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ UART3 ================ */
+/* =========================================================================================================================== */
+
+/* =================================================== UART3_CONFIG_REG ==================================================== */
+#define UART3_UART3_CONFIG_REG_ISO7816_SCRATCH_PAD_Pos (3UL) /*!< ISO7816_SCRATCH_PAD (Bit 3) */
+#define UART3_UART3_CONFIG_REG_ISO7816_SCRATCH_PAD_Msk (0xf8UL) /*!< ISO7816_SCRATCH_PAD (Bitfield-Mask: 0x1f) */
+#define UART3_UART3_CONFIG_REG_ISO7816_ENABLE_Pos (2UL) /*!< ISO7816_ENABLE (Bit 2) */
+#define UART3_UART3_CONFIG_REG_ISO7816_ENABLE_Msk (0x4UL) /*!< ISO7816_ENABLE (Bitfield-Mask: 0x01) */
+#define UART3_UART3_CONFIG_REG_ISO7816_ERR_SIG_EN_Pos (1UL) /*!< ISO7816_ERR_SIG_EN (Bit 1) */
+#define UART3_UART3_CONFIG_REG_ISO7816_ERR_SIG_EN_Msk (0x2UL) /*!< ISO7816_ERR_SIG_EN (Bitfield-Mask: 0x01) */
+#define UART3_UART3_CONFIG_REG_ISO7816_CONVENTION_Pos (0UL) /*!< ISO7816_CONVENTION (Bit 0) */
+#define UART3_UART3_CONFIG_REG_ISO7816_CONVENTION_Msk (0x1UL) /*!< ISO7816_CONVENTION (Bitfield-Mask: 0x01) */
+/* ==================================================== UART3_CTRL_REG ===================================================== */
+#define UART3_UART3_CTRL_REG_ISO7816_AUTO_GT_Pos (11UL) /*!< ISO7816_AUTO_GT (Bit 11) */
+#define UART3_UART3_CTRL_REG_ISO7816_AUTO_GT_Msk (0x800UL) /*!< ISO7816_AUTO_GT (Bitfield-Mask: 0x01) */
+#define UART3_UART3_CTRL_REG_ISO7816_ERR_TX_VALUE_IRQMASK_Pos (10UL) /*!< ISO7816_ERR_TX_VALUE_IRQMASK (Bit 10) */
+#define UART3_UART3_CTRL_REG_ISO7816_ERR_TX_VALUE_IRQMASK_Msk (0x400UL) /*!< ISO7816_ERR_TX_VALUE_IRQMASK (Bitfield-Mask: 0x01) */
+#define UART3_UART3_CTRL_REG_ISO7816_ERR_TX_TIME_IRQMASK_Pos (9UL) /*!< ISO7816_ERR_TX_TIME_IRQMASK (Bit 9) */
+#define UART3_UART3_CTRL_REG_ISO7816_ERR_TX_TIME_IRQMASK_Msk (0x200UL) /*!< ISO7816_ERR_TX_TIME_IRQMASK (Bitfield-Mask: 0x01) */
+#define UART3_UART3_CTRL_REG_ISO7816_TIM_EXPIRED_IRQMASK_Pos (8UL) /*!< ISO7816_TIM_EXPIRED_IRQMASK (Bit 8) */
+#define UART3_UART3_CTRL_REG_ISO7816_TIM_EXPIRED_IRQMASK_Msk (0x100UL) /*!< ISO7816_TIM_EXPIRED_IRQMASK (Bitfield-Mask: 0x01) */
+#define UART3_UART3_CTRL_REG_ISO7816_CLK_STATUS_Pos (7UL) /*!< ISO7816_CLK_STATUS (Bit 7) */
+#define UART3_UART3_CTRL_REG_ISO7816_CLK_STATUS_Msk (0x80UL) /*!< ISO7816_CLK_STATUS (Bitfield-Mask: 0x01) */
+#define UART3_UART3_CTRL_REG_ISO7816_CLK_LEVEL_Pos (6UL) /*!< ISO7816_CLK_LEVEL (Bit 6) */
+#define UART3_UART3_CTRL_REG_ISO7816_CLK_LEVEL_Msk (0x40UL) /*!< ISO7816_CLK_LEVEL (Bitfield-Mask: 0x01) */
+#define UART3_UART3_CTRL_REG_ISO7816_CLK_EN_Pos (5UL) /*!< ISO7816_CLK_EN (Bit 5) */
+#define UART3_UART3_CTRL_REG_ISO7816_CLK_EN_Msk (0x20UL) /*!< ISO7816_CLK_EN (Bitfield-Mask: 0x01) */
+#define UART3_UART3_CTRL_REG_ISO7816_CLK_DIV_Pos (0UL) /*!< ISO7816_CLK_DIV (Bit 0) */
+#define UART3_UART3_CTRL_REG_ISO7816_CLK_DIV_Msk (0x1fUL) /*!< ISO7816_CLK_DIV (Bitfield-Mask: 0x1f) */
+/* ===================================================== UART3_CTR_REG ===================================================== */
+#define UART3_UART3_CTR_REG_UART_CTR_Pos (0UL) /*!< UART_CTR (Bit 0) */
+#define UART3_UART3_CTR_REG_UART_CTR_Msk (0xffffffffUL) /*!< UART_CTR (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== UART3_DLF_REG ===================================================== */
+#define UART3_UART3_DLF_REG_UART_DLF_Pos (0UL) /*!< UART_DLF (Bit 0) */
+#define UART3_UART3_DLF_REG_UART_DLF_Msk (0xfUL) /*!< UART_DLF (Bitfield-Mask: 0x0f) */
+/* ==================================================== UART3_DMASA_REG ==================================================== */
+#define UART3_UART3_DMASA_REG_UART_DMASA_Pos (0UL) /*!< UART_DMASA (Bit 0) */
+#define UART3_UART3_DMASA_REG_UART_DMASA_Msk (0x1UL) /*!< UART_DMASA (Bitfield-Mask: 0x01) */
+/* ================================================== UART3_ERR_CTRL_REG =================================================== */
+#define UART3_UART3_ERR_CTRL_REG_ISO7816_ERR_PULSE_WIDTH_Pos (4UL) /*!< ISO7816_ERR_PULSE_WIDTH (Bit 4) */
+#define UART3_UART3_ERR_CTRL_REG_ISO7816_ERR_PULSE_WIDTH_Msk (0x1f0UL) /*!< ISO7816_ERR_PULSE_WIDTH (Bitfield-Mask: 0x1f) */
+#define UART3_UART3_ERR_CTRL_REG_ISO7816_ERR_PULSE_OFFSET_Pos (0UL) /*!< ISO7816_ERR_PULSE_OFFSET (Bit 0) */
+#define UART3_UART3_ERR_CTRL_REG_ISO7816_ERR_PULSE_OFFSET_Msk (0xfUL) /*!< ISO7816_ERR_PULSE_OFFSET (Bitfield-Mask: 0x0f) */
+/* ===================================================== UART3_HTX_REG ===================================================== */
+#define UART3_UART3_HTX_REG_UART_HALT_TX_Pos (0UL) /*!< UART_HALT_TX (Bit 0) */
+#define UART3_UART3_HTX_REG_UART_HALT_TX_Msk (0x1UL) /*!< UART_HALT_TX (Bitfield-Mask: 0x01) */
+/* =================================================== UART3_IER_DLH_REG =================================================== */
+#define UART3_UART3_IER_DLH_REG_PTIME_DLH7_Pos (7UL) /*!< PTIME_DLH7 (Bit 7) */
+#define UART3_UART3_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL) /*!< PTIME_DLH7 (Bitfield-Mask: 0x01) */
+#define UART3_UART3_IER_DLH_REG_DLH6_5_Pos (5UL) /*!< DLH6_5 (Bit 5) */
+#define UART3_UART3_IER_DLH_REG_DLH6_5_Msk (0x60UL) /*!< DLH6_5 (Bitfield-Mask: 0x03) */
+#define UART3_UART3_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL) /*!< ELCOLR_DLH4 (Bit 4) */
+#define UART3_UART3_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL) /*!< ELCOLR_DLH4 (Bitfield-Mask: 0x01) */
+#define UART3_UART3_IER_DLH_REG_EDSSI_DLH3_Pos (3UL) /*!< EDSSI_DLH3 (Bit 3) */
+#define UART3_UART3_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL) /*!< EDSSI_DLH3 (Bitfield-Mask: 0x01) */
+#define UART3_UART3_IER_DLH_REG_ELSI_DLH2_Pos (2UL) /*!< ELSI_DLH2 (Bit 2) */
+#define UART3_UART3_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL) /*!< ELSI_DLH2 (Bitfield-Mask: 0x01) */
+#define UART3_UART3_IER_DLH_REG_ETBEI_DLH1_Pos (1UL) /*!< ETBEI_DLH1 (Bit 1) */
+#define UART3_UART3_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL) /*!< ETBEI_DLH1 (Bitfield-Mask: 0x01) */
+#define UART3_UART3_IER_DLH_REG_ERBFI_DLH0_Pos (0UL) /*!< ERBFI_DLH0 (Bit 0) */
+#define UART3_UART3_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL) /*!< ERBFI_DLH0 (Bitfield-Mask: 0x01) */
+/* =================================================== UART3_IIR_FCR_REG =================================================== */
+#define UART3_UART3_IIR_FCR_REG_IIR_FCR_Pos (0UL) /*!< IIR_FCR (Bit 0) */
+#define UART3_UART3_IIR_FCR_REG_IIR_FCR_Msk (0xffUL) /*!< IIR_FCR (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_IRQ_STATUS_REG ================================================== */
+#define UART3_UART3_IRQ_STATUS_REG_ISO7816_ERR_TX_VALUE_IRQ_Pos (2UL) /*!< ISO7816_ERR_TX_VALUE_IRQ (Bit 2) */
+#define UART3_UART3_IRQ_STATUS_REG_ISO7816_ERR_TX_VALUE_IRQ_Msk (0x4UL) /*!< ISO7816_ERR_TX_VALUE_IRQ (Bitfield-Mask: 0x01) */
+#define UART3_UART3_IRQ_STATUS_REG_ISO7816_ERR_TX_TIME_IRQ_Pos (1UL) /*!< ISO7816_ERR_TX_TIME_IRQ (Bit 1) */
+#define UART3_UART3_IRQ_STATUS_REG_ISO7816_ERR_TX_TIME_IRQ_Msk (0x2UL) /*!< ISO7816_ERR_TX_TIME_IRQ (Bitfield-Mask: 0x01) */
+#define UART3_UART3_IRQ_STATUS_REG_ISO7816_TIM_EXPIRED_IRQ_Pos (0UL) /*!< ISO7816_TIM_EXPIRED_IRQ (Bit 0) */
+#define UART3_UART3_IRQ_STATUS_REG_ISO7816_TIM_EXPIRED_IRQ_Msk (0x1UL) /*!< ISO7816_TIM_EXPIRED_IRQ (Bitfield-Mask: 0x01) */
+/* ===================================================== UART3_LCR_EXT ===================================================== */
+#define UART3_UART3_LCR_EXT_UART_TRANSMIT_MODE_Pos (3UL) /*!< UART_TRANSMIT_MODE (Bit 3) */
+#define UART3_UART3_LCR_EXT_UART_TRANSMIT_MODE_Msk (0x8UL) /*!< UART_TRANSMIT_MODE (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LCR_EXT_UART_SEND_ADDR_Pos (2UL) /*!< UART_SEND_ADDR (Bit 2) */
+#define UART3_UART3_LCR_EXT_UART_SEND_ADDR_Msk (0x4UL) /*!< UART_SEND_ADDR (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LCR_EXT_UART_ADDR_MATCH_Pos (1UL) /*!< UART_ADDR_MATCH (Bit 1) */
+#define UART3_UART3_LCR_EXT_UART_ADDR_MATCH_Msk (0x2UL) /*!< UART_ADDR_MATCH (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LCR_EXT_UART_DLS_E_Pos (0UL) /*!< UART_DLS_E (Bit 0) */
+#define UART3_UART3_LCR_EXT_UART_DLS_E_Msk (0x1UL) /*!< UART_DLS_E (Bitfield-Mask: 0x01) */
+/* ===================================================== UART3_LCR_REG ===================================================== */
+#define UART3_UART3_LCR_REG_UART_DLAB_Pos (7UL) /*!< UART_DLAB (Bit 7) */
+#define UART3_UART3_LCR_REG_UART_DLAB_Msk (0x80UL) /*!< UART_DLAB (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LCR_REG_UART_BC_Pos (6UL) /*!< UART_BC (Bit 6) */
+#define UART3_UART3_LCR_REG_UART_BC_Msk (0x40UL) /*!< UART_BC (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LCR_REG_UART_SP_Pos (5UL) /*!< UART_SP (Bit 5) */
+#define UART3_UART3_LCR_REG_UART_SP_Msk (0x20UL) /*!< UART_SP (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LCR_REG_UART_EPS_Pos (4UL) /*!< UART_EPS (Bit 4) */
+#define UART3_UART3_LCR_REG_UART_EPS_Msk (0x10UL) /*!< UART_EPS (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LCR_REG_UART_PEN_Pos (3UL) /*!< UART_PEN (Bit 3) */
+#define UART3_UART3_LCR_REG_UART_PEN_Msk (0x8UL) /*!< UART_PEN (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LCR_REG_UART_STOP_Pos (2UL) /*!< UART_STOP (Bit 2) */
+#define UART3_UART3_LCR_REG_UART_STOP_Msk (0x4UL) /*!< UART_STOP (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LCR_REG_UART_DLS_Pos (0UL) /*!< UART_DLS (Bit 0) */
+#define UART3_UART3_LCR_REG_UART_DLS_Msk (0x3UL) /*!< UART_DLS (Bitfield-Mask: 0x03) */
+/* ===================================================== UART3_LSR_REG ===================================================== */
+#define UART3_UART3_LSR_REG_UART_ADDR_RCVD_Pos (8UL) /*!< UART_ADDR_RCVD (Bit 8) */
+#define UART3_UART3_LSR_REG_UART_ADDR_RCVD_Msk (0x100UL) /*!< UART_ADDR_RCVD (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LSR_REG_UART_RFE_Pos (7UL) /*!< UART_RFE (Bit 7) */
+#define UART3_UART3_LSR_REG_UART_RFE_Msk (0x80UL) /*!< UART_RFE (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LSR_REG_UART_TEMT_Pos (6UL) /*!< UART_TEMT (Bit 6) */
+#define UART3_UART3_LSR_REG_UART_TEMT_Msk (0x40UL) /*!< UART_TEMT (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LSR_REG_UART_THRE_Pos (5UL) /*!< UART_THRE (Bit 5) */
+#define UART3_UART3_LSR_REG_UART_THRE_Msk (0x20UL) /*!< UART_THRE (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LSR_REG_UART_BI_Pos (4UL) /*!< UART_BI (Bit 4) */
+#define UART3_UART3_LSR_REG_UART_BI_Msk (0x10UL) /*!< UART_BI (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LSR_REG_UART_FE_Pos (3UL) /*!< UART_FE (Bit 3) */
+#define UART3_UART3_LSR_REG_UART_FE_Msk (0x8UL) /*!< UART_FE (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LSR_REG_UART_PE_Pos (2UL) /*!< UART_PE (Bit 2) */
+#define UART3_UART3_LSR_REG_UART_PE_Msk (0x4UL) /*!< UART_PE (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LSR_REG_UART_OE_Pos (1UL) /*!< UART_OE (Bit 1) */
+#define UART3_UART3_LSR_REG_UART_OE_Msk (0x2UL) /*!< UART_OE (Bitfield-Mask: 0x01) */
+#define UART3_UART3_LSR_REG_UART_DR_Pos (0UL) /*!< UART_DR (Bit 0) */
+#define UART3_UART3_LSR_REG_UART_DR_Msk (0x1UL) /*!< UART_DR (Bitfield-Mask: 0x01) */
+/* ===================================================== UART3_MCR_REG ===================================================== */
+#define UART3_UART3_MCR_REG_UART_AFCE_Pos (5UL) /*!< UART_AFCE (Bit 5) */
+#define UART3_UART3_MCR_REG_UART_AFCE_Msk (0x20UL) /*!< UART_AFCE (Bitfield-Mask: 0x01) */
+#define UART3_UART3_MCR_REG_UART_LB_Pos (4UL) /*!< UART_LB (Bit 4) */
+#define UART3_UART3_MCR_REG_UART_LB_Msk (0x10UL) /*!< UART_LB (Bitfield-Mask: 0x01) */
+#define UART3_UART3_MCR_REG_UART_RTS_Pos (1UL) /*!< UART_RTS (Bit 1) */
+#define UART3_UART3_MCR_REG_UART_RTS_Msk (0x2UL) /*!< UART_RTS (Bitfield-Mask: 0x01) */
+/* ===================================================== UART3_MSR_REG ===================================================== */
+#define UART3_UART3_MSR_REG_UART_CTS_Pos (4UL) /*!< UART_CTS (Bit 4) */
+#define UART3_UART3_MSR_REG_UART_CTS_Msk (0x10UL) /*!< UART_CTS (Bitfield-Mask: 0x01) */
+#define UART3_UART3_MSR_REG_UART_DCTS_Pos (0UL) /*!< UART_DCTS (Bit 0) */
+#define UART3_UART3_MSR_REG_UART_DCTS_Msk (0x1UL) /*!< UART_DCTS (Bitfield-Mask: 0x01) */
+/* ===================================================== UART3_RAR_REG ===================================================== */
+#define UART3_UART3_RAR_REG_UART_RAR_Pos (0UL) /*!< UART_RAR (Bit 0) */
+#define UART3_UART3_RAR_REG_UART_RAR_Msk (0xffUL) /*!< UART_RAR (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_RBR_THR_DLL_REG ================================================= */
+#define UART3_UART3_RBR_THR_DLL_REG_RBR_THR_9BIT_Pos (8UL) /*!< RBR_THR_9BIT (Bit 8) */
+#define UART3_UART3_RBR_THR_DLL_REG_RBR_THR_9BIT_Msk (0x100UL) /*!< RBR_THR_9BIT (Bitfield-Mask: 0x01) */
+#define UART3_UART3_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL) /*!< RBR_THR_DLL (Bit 0) */
+#define UART3_UART3_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL) /*!< RBR_THR_DLL (Bitfield-Mask: 0xff) */
+/* ===================================================== UART3_RFL_REG ===================================================== */
+#define UART3_UART3_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL) /*!< UART_RECEIVE_FIFO_LEVEL (Bit 0) */
+#define UART3_UART3_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL) /*!< UART_RECEIVE_FIFO_LEVEL (Bitfield-Mask: 0x1f) */
+/* ==================================================== UART3_SBCR_REG ===================================================== */
+#define UART3_UART3_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL) /*!< UART_SHADOW_BREAK_CONTROL (Bit 0) */
+#define UART3_UART3_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL) /*!< UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01) */
+/* ==================================================== UART3_SDMAM_REG ==================================================== */
+#define UART3_UART3_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL) /*!< UART_SHADOW_DMA_MODE (Bit 0) */
+#define UART3_UART3_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL) /*!< UART_SHADOW_DMA_MODE (Bitfield-Mask: 0x01) */
+/* ===================================================== UART3_SFE_REG ===================================================== */
+#define UART3_UART3_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL) /*!< UART_SHADOW_FIFO_ENABLE (Bit 0) */
+#define UART3_UART3_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL) /*!< UART_SHADOW_FIFO_ENABLE (Bitfield-Mask: 0x01) */
+/* ================================================= UART3_SRBR_STHR0_REG ================================================== */
+#define UART3_UART3_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR10_REG ================================================= */
+#define UART3_UART3_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR11_REG ================================================= */
+#define UART3_UART3_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR12_REG ================================================= */
+#define UART3_UART3_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR13_REG ================================================= */
+#define UART3_UART3_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR14_REG ================================================= */
+#define UART3_UART3_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR15_REG ================================================= */
+#define UART3_UART3_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR1_REG ================================================== */
+#define UART3_UART3_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR2_REG ================================================== */
+#define UART3_UART3_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR3_REG ================================================== */
+#define UART3_UART3_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR4_REG ================================================== */
+#define UART3_UART3_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR5_REG ================================================== */
+#define UART3_UART3_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR6_REG ================================================== */
+#define UART3_UART3_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR7_REG ================================================== */
+#define UART3_UART3_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR8_REG ================================================== */
+#define UART3_UART3_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ================================================= UART3_SRBR_STHR9_REG ================================================== */
+#define UART3_UART3_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL) /*!< SRBR_STHRx (Bit 0) */
+#define UART3_UART3_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL) /*!< SRBR_STHRx (Bitfield-Mask: 0xff) */
+/* ===================================================== UART3_SRR_REG ===================================================== */
+#define UART3_UART3_SRR_REG_UART_XFR_Pos (2UL) /*!< UART_XFR (Bit 2) */
+#define UART3_UART3_SRR_REG_UART_XFR_Msk (0x4UL) /*!< UART_XFR (Bitfield-Mask: 0x01) */
+#define UART3_UART3_SRR_REG_UART_RFR_Pos (1UL) /*!< UART_RFR (Bit 1) */
+#define UART3_UART3_SRR_REG_UART_RFR_Msk (0x2UL) /*!< UART_RFR (Bitfield-Mask: 0x01) */
+#define UART3_UART3_SRR_REG_UART_UR_Pos (0UL) /*!< UART_UR (Bit 0) */
+#define UART3_UART3_SRR_REG_UART_UR_Msk (0x1UL) /*!< UART_UR (Bitfield-Mask: 0x01) */
+/* ==================================================== UART3_SRTS_REG ===================================================== */
+#define UART3_UART3_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos (0UL) /*!< UART_SHADOW_REQUEST_TO_SEND (Bit 0) */
+#define UART3_UART3_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk (0x1UL) /*!< UART_SHADOW_REQUEST_TO_SEND (Bitfield-Mask: 0x01) */
+/* ===================================================== UART3_SRT_REG ===================================================== */
+#define UART3_UART3_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL) /*!< UART_SHADOW_RCVR_TRIGGER (Bit 0) */
+#define UART3_UART3_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_RCVR_TRIGGER (Bitfield-Mask: 0x03) */
+/* ==================================================== UART3_STET_REG ===================================================== */
+#define UART3_UART3_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bit 0) */
+#define UART3_UART3_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL) /*!< UART_SHADOW_TX_EMPTY_TRIGGER (Bitfield-Mask: 0x03) */
+/* ===================================================== UART3_TAR_REG ===================================================== */
+#define UART3_UART3_TAR_REG_UART_TAR_Pos (0UL) /*!< UART_TAR (Bit 0) */
+#define UART3_UART3_TAR_REG_UART_TAR_Msk (0xffUL) /*!< UART_TAR (Bitfield-Mask: 0xff) */
+/* ===================================================== UART3_TFL_REG ===================================================== */
+#define UART3_UART3_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL) /*!< UART_TRANSMIT_FIFO_LEVEL (Bit 0) */
+#define UART3_UART3_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL) /*!< UART_TRANSMIT_FIFO_LEVEL (Bitfield-Mask: 0x1f) */
+/* ==================================================== UART3_TIMER_REG ==================================================== */
+#define UART3_UART3_TIMER_REG_ISO7816_TIM_MODE_Pos (17UL) /*!< ISO7816_TIM_MODE (Bit 17) */
+#define UART3_UART3_TIMER_REG_ISO7816_TIM_MODE_Msk (0x20000UL) /*!< ISO7816_TIM_MODE (Bitfield-Mask: 0x01) */
+#define UART3_UART3_TIMER_REG_ISO7816_TIM_EN_Pos (16UL) /*!< ISO7816_TIM_EN (Bit 16) */
+#define UART3_UART3_TIMER_REG_ISO7816_TIM_EN_Msk (0x10000UL) /*!< ISO7816_TIM_EN (Bitfield-Mask: 0x01) */
+#define UART3_UART3_TIMER_REG_ISO7816_TIM_MAX_Pos (0UL) /*!< ISO7816_TIM_MAX (Bit 0) */
+#define UART3_UART3_TIMER_REG_ISO7816_TIM_MAX_Msk (0xffffUL) /*!< ISO7816_TIM_MAX (Bitfield-Mask: 0xffff) */
+/* ===================================================== UART3_UCV_REG ===================================================== */
+#define UART3_UART3_UCV_REG_UART_UCV_Pos (0UL) /*!< UART_UCV (Bit 0) */
+#define UART3_UART3_UCV_REG_UART_UCV_Msk (0xffffffffUL) /*!< UART_UCV (Bitfield-Mask: 0xffffffff) */
+/* ===================================================== UART3_USR_REG ===================================================== */
+#define UART3_UART3_USR_REG_UART_RFF_Pos (4UL) /*!< UART_RFF (Bit 4) */
+#define UART3_UART3_USR_REG_UART_RFF_Msk (0x10UL) /*!< UART_RFF (Bitfield-Mask: 0x01) */
+#define UART3_UART3_USR_REG_UART_RFNE_Pos (3UL) /*!< UART_RFNE (Bit 3) */
+#define UART3_UART3_USR_REG_UART_RFNE_Msk (0x8UL) /*!< UART_RFNE (Bitfield-Mask: 0x01) */
+#define UART3_UART3_USR_REG_UART_TFE_Pos (2UL) /*!< UART_TFE (Bit 2) */
+#define UART3_UART3_USR_REG_UART_TFE_Msk (0x4UL) /*!< UART_TFE (Bitfield-Mask: 0x01) */
+#define UART3_UART3_USR_REG_UART_TFNF_Pos (1UL) /*!< UART_TFNF (Bit 1) */
+#define UART3_UART3_USR_REG_UART_TFNF_Msk (0x2UL) /*!< UART_TFNF (Bitfield-Mask: 0x01) */
+#define UART3_UART3_USR_REG_UART_BUSY_Pos (0UL) /*!< UART_BUSY (Bit 0) */
+#define UART3_UART3_USR_REG_UART_BUSY_Msk (0x1UL) /*!< UART_BUSY (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ USB ================ */
+/* =========================================================================================================================== */
+
+/* ===================================================== USB_ALTEV_REG ===================================================== */
+#define USB_USB_ALTEV_REG_USB_RESUME_Pos (7UL) /*!< USB_RESUME (Bit 7) */
+#define USB_USB_ALTEV_REG_USB_RESUME_Msk (0x80UL) /*!< USB_RESUME (Bitfield-Mask: 0x01) */
+#define USB_USB_ALTEV_REG_USB_RESET_Pos (6UL) /*!< USB_RESET (Bit 6) */
+#define USB_USB_ALTEV_REG_USB_RESET_Msk (0x40UL) /*!< USB_RESET (Bitfield-Mask: 0x01) */
+#define USB_USB_ALTEV_REG_USB_SD5_Pos (5UL) /*!< USB_SD5 (Bit 5) */
+#define USB_USB_ALTEV_REG_USB_SD5_Msk (0x20UL) /*!< USB_SD5 (Bitfield-Mask: 0x01) */
+#define USB_USB_ALTEV_REG_USB_SD3_Pos (4UL) /*!< USB_SD3 (Bit 4) */
+#define USB_USB_ALTEV_REG_USB_SD3_Msk (0x10UL) /*!< USB_SD3 (Bitfield-Mask: 0x01) */
+#define USB_USB_ALTEV_REG_USB_EOP_Pos (3UL) /*!< USB_EOP (Bit 3) */
+#define USB_USB_ALTEV_REG_USB_EOP_Msk (0x8UL) /*!< USB_EOP (Bitfield-Mask: 0x01) */
+/* ==================================================== USB_ALTMSK_REG ===================================================== */
+#define USB_USB_ALTMSK_REG_USB_M_RESUME_Pos (7UL) /*!< USB_M_RESUME (Bit 7) */
+#define USB_USB_ALTMSK_REG_USB_M_RESUME_Msk (0x80UL) /*!< USB_M_RESUME (Bitfield-Mask: 0x01) */
+#define USB_USB_ALTMSK_REG_USB_M_RESET_Pos (6UL) /*!< USB_M_RESET (Bit 6) */
+#define USB_USB_ALTMSK_REG_USB_M_RESET_Msk (0x40UL) /*!< USB_M_RESET (Bitfield-Mask: 0x01) */
+#define USB_USB_ALTMSK_REG_USB_M_SD5_Pos (5UL) /*!< USB_M_SD5 (Bit 5) */
+#define USB_USB_ALTMSK_REG_USB_M_SD5_Msk (0x20UL) /*!< USB_M_SD5 (Bitfield-Mask: 0x01) */
+#define USB_USB_ALTMSK_REG_USB_M_SD3_Pos (4UL) /*!< USB_M_SD3 (Bit 4) */
+#define USB_USB_ALTMSK_REG_USB_M_SD3_Msk (0x10UL) /*!< USB_M_SD3 (Bitfield-Mask: 0x01) */
+#define USB_USB_ALTMSK_REG_USB_M_EOP_Pos (3UL) /*!< USB_M_EOP (Bit 3) */
+#define USB_USB_ALTMSK_REG_USB_M_EOP_Msk (0x8UL) /*!< USB_M_EOP (Bitfield-Mask: 0x01) */
+/* ================================================= USB_CHARGER_CTRL_REG ================================================== */
+#define USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Pos (5UL) /*!< IDM_SINK_ON (Bit 5) */
+#define USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Msk (0x20UL) /*!< IDM_SINK_ON (Bitfield-Mask: 0x01) */
+#define USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Pos (4UL) /*!< IDP_SINK_ON (Bit 4) */
+#define USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Msk (0x10UL) /*!< IDP_SINK_ON (Bitfield-Mask: 0x01) */
+#define USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Pos (3UL) /*!< VDM_SRC_ON (Bit 3) */
+#define USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Msk (0x8UL) /*!< VDM_SRC_ON (Bitfield-Mask: 0x01) */
+#define USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Pos (2UL) /*!< VDP_SRC_ON (Bit 2) */
+#define USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Msk (0x4UL) /*!< VDP_SRC_ON (Bitfield-Mask: 0x01) */
+#define USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Pos (1UL) /*!< IDP_SRC_ON (Bit 1) */
+#define USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Msk (0x2UL) /*!< IDP_SRC_ON (Bitfield-Mask: 0x01) */
+#define USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Pos (0UL) /*!< USB_CHARGE_ON (Bit 0) */
+#define USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Msk (0x1UL) /*!< USB_CHARGE_ON (Bitfield-Mask: 0x01) */
+/* ================================================= USB_CHARGER_STAT_REG ================================================== */
+#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Pos (5UL) /*!< USB_DM_VAL2 (Bit 5) */
+#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Msk (0x20UL) /*!< USB_DM_VAL2 (Bitfield-Mask: 0x01) */
+#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Pos (4UL) /*!< USB_DP_VAL2 (Bit 4) */
+#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Msk (0x10UL) /*!< USB_DP_VAL2 (Bitfield-Mask: 0x01) */
+#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Pos (3UL) /*!< USB_DM_VAL (Bit 3) */
+#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Msk (0x8UL) /*!< USB_DM_VAL (Bitfield-Mask: 0x01) */
+#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Pos (2UL) /*!< USB_DP_VAL (Bit 2) */
+#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Msk (0x4UL) /*!< USB_DP_VAL (Bitfield-Mask: 0x01) */
+#define USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Pos (1UL) /*!< USB_CHG_DET (Bit 1) */
+#define USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Msk (0x2UL) /*!< USB_CHG_DET (Bitfield-Mask: 0x01) */
+#define USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Pos (0UL) /*!< USB_DCP_DET (Bit 0) */
+#define USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Msk (0x1UL) /*!< USB_DCP_DET (Bitfield-Mask: 0x01) */
+/* =================================================== USB_DMA_CTRL_REG ==================================================== */
+#define USB_USB_DMA_CTRL_REG_USB_DMA_EN_Pos (6UL) /*!< USB_DMA_EN (Bit 6) */
+#define USB_USB_DMA_CTRL_REG_USB_DMA_EN_Msk (0x40UL) /*!< USB_DMA_EN (Bitfield-Mask: 0x01) */
+#define USB_USB_DMA_CTRL_REG_USB_DMA_TX_Pos (3UL) /*!< USB_DMA_TX (Bit 3) */
+#define USB_USB_DMA_CTRL_REG_USB_DMA_TX_Msk (0x38UL) /*!< USB_DMA_TX (Bitfield-Mask: 0x07) */
+#define USB_USB_DMA_CTRL_REG_USB_DMA_RX_Pos (0UL) /*!< USB_DMA_RX (Bit 0) */
+#define USB_USB_DMA_CTRL_REG_USB_DMA_RX_Msk (0x7UL) /*!< USB_DMA_RX (Bitfield-Mask: 0x07) */
+/* ==================================================== USB_EP0_NAK_REG ==================================================== */
+#define USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Pos (1UL) /*!< USB_EP0_OUTNAK (Bit 1) */
+#define USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Msk (0x2UL) /*!< USB_EP0_OUTNAK (Bitfield-Mask: 0x01) */
+#define USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Pos (0UL) /*!< USB_EP0_INNAK (Bit 0) */
+#define USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Msk (0x1UL) /*!< USB_EP0_INNAK (Bitfield-Mask: 0x01) */
+/* ===================================================== USB_EPC0_REG ====================================================== */
+#define USB_USB_EPC0_REG_USB_STALL_Pos (7UL) /*!< USB_STALL (Bit 7) */
+#define USB_USB_EPC0_REG_USB_STALL_Msk (0x80UL) /*!< USB_STALL (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC0_REG_USB_DEF_Pos (6UL) /*!< USB_DEF (Bit 6) */
+#define USB_USB_EPC0_REG_USB_DEF_Msk (0x40UL) /*!< USB_DEF (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC0_REG_USB_EP_Pos (0UL) /*!< USB_EP (Bit 0) */
+#define USB_USB_EPC0_REG_USB_EP_Msk (0xfUL) /*!< USB_EP (Bitfield-Mask: 0x0f) */
+/* ===================================================== USB_EPC1_REG ====================================================== */
+#define USB_USB_EPC1_REG_USB_STALL_Pos (7UL) /*!< USB_STALL (Bit 7) */
+#define USB_USB_EPC1_REG_USB_STALL_Msk (0x80UL) /*!< USB_STALL (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC1_REG_USB_ISO_Pos (5UL) /*!< USB_ISO (Bit 5) */
+#define USB_USB_EPC1_REG_USB_ISO_Msk (0x20UL) /*!< USB_ISO (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC1_REG_USB_EP_EN_Pos (4UL) /*!< USB_EP_EN (Bit 4) */
+#define USB_USB_EPC1_REG_USB_EP_EN_Msk (0x10UL) /*!< USB_EP_EN (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC1_REG_USB_EP_Pos (0UL) /*!< USB_EP (Bit 0) */
+#define USB_USB_EPC1_REG_USB_EP_Msk (0xfUL) /*!< USB_EP (Bitfield-Mask: 0x0f) */
+/* ===================================================== USB_EPC2_REG ====================================================== */
+#define USB_USB_EPC2_REG_USB_STALL_Pos (7UL) /*!< USB_STALL (Bit 7) */
+#define USB_USB_EPC2_REG_USB_STALL_Msk (0x80UL) /*!< USB_STALL (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC2_REG_USB_ISO_Pos (5UL) /*!< USB_ISO (Bit 5) */
+#define USB_USB_EPC2_REG_USB_ISO_Msk (0x20UL) /*!< USB_ISO (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC2_REG_USB_EP_EN_Pos (4UL) /*!< USB_EP_EN (Bit 4) */
+#define USB_USB_EPC2_REG_USB_EP_EN_Msk (0x10UL) /*!< USB_EP_EN (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC2_REG_USB_EP_Pos (0UL) /*!< USB_EP (Bit 0) */
+#define USB_USB_EPC2_REG_USB_EP_Msk (0xfUL) /*!< USB_EP (Bitfield-Mask: 0x0f) */
+/* ===================================================== USB_EPC3_REG ====================================================== */
+#define USB_USB_EPC3_REG_USB_STALL_Pos (7UL) /*!< USB_STALL (Bit 7) */
+#define USB_USB_EPC3_REG_USB_STALL_Msk (0x80UL) /*!< USB_STALL (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC3_REG_USB_ISO_Pos (5UL) /*!< USB_ISO (Bit 5) */
+#define USB_USB_EPC3_REG_USB_ISO_Msk (0x20UL) /*!< USB_ISO (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC3_REG_USB_EP_EN_Pos (4UL) /*!< USB_EP_EN (Bit 4) */
+#define USB_USB_EPC3_REG_USB_EP_EN_Msk (0x10UL) /*!< USB_EP_EN (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC3_REG_USB_EP_Pos (0UL) /*!< USB_EP (Bit 0) */
+#define USB_USB_EPC3_REG_USB_EP_Msk (0xfUL) /*!< USB_EP (Bitfield-Mask: 0x0f) */
+/* ===================================================== USB_EPC4_REG ====================================================== */
+#define USB_USB_EPC4_REG_USB_STALL_Pos (7UL) /*!< USB_STALL (Bit 7) */
+#define USB_USB_EPC4_REG_USB_STALL_Msk (0x80UL) /*!< USB_STALL (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC4_REG_USB_ISO_Pos (5UL) /*!< USB_ISO (Bit 5) */
+#define USB_USB_EPC4_REG_USB_ISO_Msk (0x20UL) /*!< USB_ISO (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC4_REG_USB_EP_EN_Pos (4UL) /*!< USB_EP_EN (Bit 4) */
+#define USB_USB_EPC4_REG_USB_EP_EN_Msk (0x10UL) /*!< USB_EP_EN (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC4_REG_USB_EP_Pos (0UL) /*!< USB_EP (Bit 0) */
+#define USB_USB_EPC4_REG_USB_EP_Msk (0xfUL) /*!< USB_EP (Bitfield-Mask: 0x0f) */
+/* ===================================================== USB_EPC5_REG ====================================================== */
+#define USB_USB_EPC5_REG_USB_STALL_Pos (7UL) /*!< USB_STALL (Bit 7) */
+#define USB_USB_EPC5_REG_USB_STALL_Msk (0x80UL) /*!< USB_STALL (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC5_REG_USB_ISO_Pos (5UL) /*!< USB_ISO (Bit 5) */
+#define USB_USB_EPC5_REG_USB_ISO_Msk (0x20UL) /*!< USB_ISO (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC5_REG_USB_EP_EN_Pos (4UL) /*!< USB_EP_EN (Bit 4) */
+#define USB_USB_EPC5_REG_USB_EP_EN_Msk (0x10UL) /*!< USB_EP_EN (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC5_REG_USB_EP_Pos (0UL) /*!< USB_EP (Bit 0) */
+#define USB_USB_EPC5_REG_USB_EP_Msk (0xfUL) /*!< USB_EP (Bitfield-Mask: 0x0f) */
+/* ===================================================== USB_EPC6_REG ====================================================== */
+#define USB_USB_EPC6_REG_USB_STALL_Pos (7UL) /*!< USB_STALL (Bit 7) */
+#define USB_USB_EPC6_REG_USB_STALL_Msk (0x80UL) /*!< USB_STALL (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC6_REG_USB_ISO_Pos (5UL) /*!< USB_ISO (Bit 5) */
+#define USB_USB_EPC6_REG_USB_ISO_Msk (0x20UL) /*!< USB_ISO (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC6_REG_USB_EP_EN_Pos (4UL) /*!< USB_EP_EN (Bit 4) */
+#define USB_USB_EPC6_REG_USB_EP_EN_Msk (0x10UL) /*!< USB_EP_EN (Bitfield-Mask: 0x01) */
+#define USB_USB_EPC6_REG_USB_EP_Pos (0UL) /*!< USB_EP (Bit 0) */
+#define USB_USB_EPC6_REG_USB_EP_Msk (0xfUL) /*!< USB_EP (Bitfield-Mask: 0x0f) */
+/* ====================================================== USB_FAR_REG ====================================================== */
+#define USB_USB_FAR_REG_USB_AD_EN_Pos (7UL) /*!< USB_AD_EN (Bit 7) */
+#define USB_USB_FAR_REG_USB_AD_EN_Msk (0x80UL) /*!< USB_AD_EN (Bitfield-Mask: 0x01) */
+#define USB_USB_FAR_REG_USB_AD_Pos (0UL) /*!< USB_AD (Bit 0) */
+#define USB_USB_FAR_REG_USB_AD_Msk (0x7fUL) /*!< USB_AD (Bitfield-Mask: 0x7f) */
+/* ====================================================== USB_FNH_REG ====================================================== */
+#define USB_USB_FNH_REG_USB_MF_Pos (7UL) /*!< USB_MF (Bit 7) */
+#define USB_USB_FNH_REG_USB_MF_Msk (0x80UL) /*!< USB_MF (Bitfield-Mask: 0x01) */
+#define USB_USB_FNH_REG_USB_UL_Pos (6UL) /*!< USB_UL (Bit 6) */
+#define USB_USB_FNH_REG_USB_UL_Msk (0x40UL) /*!< USB_UL (Bitfield-Mask: 0x01) */
+#define USB_USB_FNH_REG_USB_RFC_Pos (5UL) /*!< USB_RFC (Bit 5) */
+#define USB_USB_FNH_REG_USB_RFC_Msk (0x20UL) /*!< USB_RFC (Bitfield-Mask: 0x01) */
+#define USB_USB_FNH_REG_USB_FN_10_8_Pos (0UL) /*!< USB_FN_10_8 (Bit 0) */
+#define USB_USB_FNH_REG_USB_FN_10_8_Msk (0x7UL) /*!< USB_FN_10_8 (Bitfield-Mask: 0x07) */
+/* ====================================================== USB_FNL_REG ====================================================== */
+#define USB_USB_FNL_REG_USB_FN_Pos (0UL) /*!< USB_FN (Bit 0) */
+#define USB_USB_FNL_REG_USB_FN_Msk (0xffUL) /*!< USB_FN (Bitfield-Mask: 0xff) */
+/* ===================================================== USB_FWEV_REG ====================================================== */
+#define USB_USB_FWEV_REG_USB_RXWARN31_Pos (4UL) /*!< USB_RXWARN31 (Bit 4) */
+#define USB_USB_FWEV_REG_USB_RXWARN31_Msk (0x70UL) /*!< USB_RXWARN31 (Bitfield-Mask: 0x07) */
+#define USB_USB_FWEV_REG_USB_TXWARN31_Pos (0UL) /*!< USB_TXWARN31 (Bit 0) */
+#define USB_USB_FWEV_REG_USB_TXWARN31_Msk (0x7UL) /*!< USB_TXWARN31 (Bitfield-Mask: 0x07) */
+/* ===================================================== USB_FWMSK_REG ===================================================== */
+#define USB_USB_FWMSK_REG_USB_M_RXWARN31_Pos (4UL) /*!< USB_M_RXWARN31 (Bit 4) */
+#define USB_USB_FWMSK_REG_USB_M_RXWARN31_Msk (0x70UL) /*!< USB_M_RXWARN31 (Bitfield-Mask: 0x07) */
+#define USB_USB_FWMSK_REG_USB_M_TXWARN31_Pos (0UL) /*!< USB_M_TXWARN31 (Bit 0) */
+#define USB_USB_FWMSK_REG_USB_M_TXWARN31_Msk (0x7UL) /*!< USB_M_TXWARN31 (Bitfield-Mask: 0x07) */
+/* ===================================================== USB_MAEV_REG ====================================================== */
+#define USB_USB_MAEV_REG_USB_CH_EV_Pos (11UL) /*!< USB_CH_EV (Bit 11) */
+#define USB_USB_MAEV_REG_USB_CH_EV_Msk (0x800UL) /*!< USB_CH_EV (Bitfield-Mask: 0x01) */
+#define USB_USB_MAEV_REG_USB_EP0_NAK_Pos (10UL) /*!< USB_EP0_NAK (Bit 10) */
+#define USB_USB_MAEV_REG_USB_EP0_NAK_Msk (0x400UL) /*!< USB_EP0_NAK (Bitfield-Mask: 0x01) */
+#define USB_USB_MAEV_REG_USB_EP0_RX_Pos (9UL) /*!< USB_EP0_RX (Bit 9) */
+#define USB_USB_MAEV_REG_USB_EP0_RX_Msk (0x200UL) /*!< USB_EP0_RX (Bitfield-Mask: 0x01) */
+#define USB_USB_MAEV_REG_USB_EP0_TX_Pos (8UL) /*!< USB_EP0_TX (Bit 8) */
+#define USB_USB_MAEV_REG_USB_EP0_TX_Msk (0x100UL) /*!< USB_EP0_TX (Bitfield-Mask: 0x01) */
+#define USB_USB_MAEV_REG_USB_INTR_Pos (7UL) /*!< USB_INTR (Bit 7) */
+#define USB_USB_MAEV_REG_USB_INTR_Msk (0x80UL) /*!< USB_INTR (Bitfield-Mask: 0x01) */
+#define USB_USB_MAEV_REG_USB_RX_EV_Pos (6UL) /*!< USB_RX_EV (Bit 6) */
+#define USB_USB_MAEV_REG_USB_RX_EV_Msk (0x40UL) /*!< USB_RX_EV (Bitfield-Mask: 0x01) */
+#define USB_USB_MAEV_REG_USB_ULD_Pos (5UL) /*!< USB_ULD (Bit 5) */
+#define USB_USB_MAEV_REG_USB_ULD_Msk (0x20UL) /*!< USB_ULD (Bitfield-Mask: 0x01) */
+#define USB_USB_MAEV_REG_USB_NAK_Pos (4UL) /*!< USB_NAK (Bit 4) */
+#define USB_USB_MAEV_REG_USB_NAK_Msk (0x10UL) /*!< USB_NAK (Bitfield-Mask: 0x01) */
+#define USB_USB_MAEV_REG_USB_FRAME_Pos (3UL) /*!< USB_FRAME (Bit 3) */
+#define USB_USB_MAEV_REG_USB_FRAME_Msk (0x8UL) /*!< USB_FRAME (Bitfield-Mask: 0x01) */
+#define USB_USB_MAEV_REG_USB_TX_EV_Pos (2UL) /*!< USB_TX_EV (Bit 2) */
+#define USB_USB_MAEV_REG_USB_TX_EV_Msk (0x4UL) /*!< USB_TX_EV (Bitfield-Mask: 0x01) */
+#define USB_USB_MAEV_REG_USB_ALT_Pos (1UL) /*!< USB_ALT (Bit 1) */
+#define USB_USB_MAEV_REG_USB_ALT_Msk (0x2UL) /*!< USB_ALT (Bitfield-Mask: 0x01) */
+#define USB_USB_MAEV_REG_USB_WARN_Pos (0UL) /*!< USB_WARN (Bit 0) */
+#define USB_USB_MAEV_REG_USB_WARN_Msk (0x1UL) /*!< USB_WARN (Bitfield-Mask: 0x01) */
+/* ===================================================== USB_MAMSK_REG ===================================================== */
+#define USB_USB_MAMSK_REG_USB_M_CH_EV_Pos (11UL) /*!< USB_M_CH_EV (Bit 11) */
+#define USB_USB_MAMSK_REG_USB_M_CH_EV_Msk (0x800UL) /*!< USB_M_CH_EV (Bitfield-Mask: 0x01) */
+#define USB_USB_MAMSK_REG_USB_M_EP0_NAK_Pos (10UL) /*!< USB_M_EP0_NAK (Bit 10) */
+#define USB_USB_MAMSK_REG_USB_M_EP0_NAK_Msk (0x400UL) /*!< USB_M_EP0_NAK (Bitfield-Mask: 0x01) */
+#define USB_USB_MAMSK_REG_USB_M_EP0_RX_Pos (9UL) /*!< USB_M_EP0_RX (Bit 9) */
+#define USB_USB_MAMSK_REG_USB_M_EP0_RX_Msk (0x200UL) /*!< USB_M_EP0_RX (Bitfield-Mask: 0x01) */
+#define USB_USB_MAMSK_REG_USB_M_EP0_TX_Pos (8UL) /*!< USB_M_EP0_TX (Bit 8) */
+#define USB_USB_MAMSK_REG_USB_M_EP0_TX_Msk (0x100UL) /*!< USB_M_EP0_TX (Bitfield-Mask: 0x01) */
+#define USB_USB_MAMSK_REG_USB_M_INTR_Pos (7UL) /*!< USB_M_INTR (Bit 7) */
+#define USB_USB_MAMSK_REG_USB_M_INTR_Msk (0x80UL) /*!< USB_M_INTR (Bitfield-Mask: 0x01) */
+#define USB_USB_MAMSK_REG_USB_M_RX_EV_Pos (6UL) /*!< USB_M_RX_EV (Bit 6) */
+#define USB_USB_MAMSK_REG_USB_M_RX_EV_Msk (0x40UL) /*!< USB_M_RX_EV (Bitfield-Mask: 0x01) */
+#define USB_USB_MAMSK_REG_USB_M_ULD_Pos (5UL) /*!< USB_M_ULD (Bit 5) */
+#define USB_USB_MAMSK_REG_USB_M_ULD_Msk (0x20UL) /*!< USB_M_ULD (Bitfield-Mask: 0x01) */
+#define USB_USB_MAMSK_REG_USB_M_NAK_Pos (4UL) /*!< USB_M_NAK (Bit 4) */
+#define USB_USB_MAMSK_REG_USB_M_NAK_Msk (0x10UL) /*!< USB_M_NAK (Bitfield-Mask: 0x01) */
+#define USB_USB_MAMSK_REG_USB_M_FRAME_Pos (3UL) /*!< USB_M_FRAME (Bit 3) */
+#define USB_USB_MAMSK_REG_USB_M_FRAME_Msk (0x8UL) /*!< USB_M_FRAME (Bitfield-Mask: 0x01) */
+#define USB_USB_MAMSK_REG_USB_M_TX_EV_Pos (2UL) /*!< USB_M_TX_EV (Bit 2) */
+#define USB_USB_MAMSK_REG_USB_M_TX_EV_Msk (0x4UL) /*!< USB_M_TX_EV (Bitfield-Mask: 0x01) */
+#define USB_USB_MAMSK_REG_USB_M_ALT_Pos (1UL) /*!< USB_M_ALT (Bit 1) */
+#define USB_USB_MAMSK_REG_USB_M_ALT_Msk (0x2UL) /*!< USB_M_ALT (Bitfield-Mask: 0x01) */
+#define USB_USB_MAMSK_REG_USB_M_WARN_Pos (0UL) /*!< USB_M_WARN (Bit 0) */
+#define USB_USB_MAMSK_REG_USB_M_WARN_Msk (0x1UL) /*!< USB_M_WARN (Bitfield-Mask: 0x01) */
+/* ===================================================== USB_MCTRL_REG ===================================================== */
+#define USB_USB_MCTRL_REG_LSMODE_Pos (4UL) /*!< LSMODE (Bit 4) */
+#define USB_USB_MCTRL_REG_LSMODE_Msk (0x10UL) /*!< LSMODE (Bitfield-Mask: 0x01) */
+#define USB_USB_MCTRL_REG_USB_NAT_Pos (3UL) /*!< USB_NAT (Bit 3) */
+#define USB_USB_MCTRL_REG_USB_NAT_Msk (0x8UL) /*!< USB_NAT (Bitfield-Mask: 0x01) */
+#define USB_USB_MCTRL_REG_USB_DBG_Pos (1UL) /*!< USB_DBG (Bit 1) */
+#define USB_USB_MCTRL_REG_USB_DBG_Msk (0x2UL) /*!< USB_DBG (Bitfield-Mask: 0x01) */
+#define USB_USB_MCTRL_REG_USBEN_Pos (0UL) /*!< USBEN (Bit 0) */
+#define USB_USB_MCTRL_REG_USBEN_Msk (0x1UL) /*!< USBEN (Bitfield-Mask: 0x01) */
+/* ===================================================== USB_NAKEV_REG ===================================================== */
+#define USB_USB_NAKEV_REG_USB_OUT31_Pos (4UL) /*!< USB_OUT31 (Bit 4) */
+#define USB_USB_NAKEV_REG_USB_OUT31_Msk (0x70UL) /*!< USB_OUT31 (Bitfield-Mask: 0x07) */
+#define USB_USB_NAKEV_REG_USB_IN31_Pos (0UL) /*!< USB_IN31 (Bit 0) */
+#define USB_USB_NAKEV_REG_USB_IN31_Msk (0x7UL) /*!< USB_IN31 (Bitfield-Mask: 0x07) */
+/* ==================================================== USB_NAKMSK_REG ===================================================== */
+#define USB_USB_NAKMSK_REG_USB_M_OUT31_Pos (4UL) /*!< USB_M_OUT31 (Bit 4) */
+#define USB_USB_NAKMSK_REG_USB_M_OUT31_Msk (0x70UL) /*!< USB_M_OUT31 (Bitfield-Mask: 0x07) */
+#define USB_USB_NAKMSK_REG_USB_M_IN31_Pos (0UL) /*!< USB_M_IN31 (Bit 0) */
+#define USB_USB_NAKMSK_REG_USB_M_IN31_Msk (0x7UL) /*!< USB_M_IN31 (Bitfield-Mask: 0x07) */
+/* ===================================================== USB_NFSR_REG ====================================================== */
+#define USB_USB_NFSR_REG_USB_NFS_Pos (0UL) /*!< USB_NFS (Bit 0) */
+#define USB_USB_NFSR_REG_USB_NFS_Msk (0x3UL) /*!< USB_NFS (Bitfield-Mask: 0x03) */
+/* ===================================================== USB_RXC0_REG ====================================================== */
+#define USB_USB_RXC0_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */
+#define USB_USB_RXC0_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */
+#define USB_USB_RXC0_REG_USB_IGN_SETUP_Pos (2UL) /*!< USB_IGN_SETUP (Bit 2) */
+#define USB_USB_RXC0_REG_USB_IGN_SETUP_Msk (0x4UL) /*!< USB_IGN_SETUP (Bitfield-Mask: 0x01) */
+#define USB_USB_RXC0_REG_USB_IGN_OUT_Pos (1UL) /*!< USB_IGN_OUT (Bit 1) */
+#define USB_USB_RXC0_REG_USB_IGN_OUT_Msk (0x2UL) /*!< USB_IGN_OUT (Bitfield-Mask: 0x01) */
+#define USB_USB_RXC0_REG_USB_RX_EN_Pos (0UL) /*!< USB_RX_EN (Bit 0) */
+#define USB_USB_RXC0_REG_USB_RX_EN_Msk (0x1UL) /*!< USB_RX_EN (Bitfield-Mask: 0x01) */
+/* ===================================================== USB_RXC1_REG ====================================================== */
+#define USB_USB_RXC1_REG_USB_RFWL_Pos (5UL) /*!< USB_RFWL (Bit 5) */
+#define USB_USB_RXC1_REG_USB_RFWL_Msk (0x60UL) /*!< USB_RFWL (Bitfield-Mask: 0x03) */
+#define USB_USB_RXC1_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */
+#define USB_USB_RXC1_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */
+#define USB_USB_RXC1_REG_USB_IGN_SETUP_Pos (2UL) /*!< USB_IGN_SETUP (Bit 2) */
+#define USB_USB_RXC1_REG_USB_IGN_SETUP_Msk (0x4UL) /*!< USB_IGN_SETUP (Bitfield-Mask: 0x01) */
+#define USB_USB_RXC1_REG_USB_RX_EN_Pos (0UL) /*!< USB_RX_EN (Bit 0) */
+#define USB_USB_RXC1_REG_USB_RX_EN_Msk (0x1UL) /*!< USB_RX_EN (Bitfield-Mask: 0x01) */
+/* ===================================================== USB_RXC2_REG ====================================================== */
+#define USB_USB_RXC2_REG_USB_RFWL_Pos (5UL) /*!< USB_RFWL (Bit 5) */
+#define USB_USB_RXC2_REG_USB_RFWL_Msk (0x60UL) /*!< USB_RFWL (Bitfield-Mask: 0x03) */
+#define USB_USB_RXC2_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */
+#define USB_USB_RXC2_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */
+#define USB_USB_RXC2_REG_USB_IGN_SETUP_Pos (2UL) /*!< USB_IGN_SETUP (Bit 2) */
+#define USB_USB_RXC2_REG_USB_IGN_SETUP_Msk (0x4UL) /*!< USB_IGN_SETUP (Bitfield-Mask: 0x01) */
+#define USB_USB_RXC2_REG_USB_RX_EN_Pos (0UL) /*!< USB_RX_EN (Bit 0) */
+#define USB_USB_RXC2_REG_USB_RX_EN_Msk (0x1UL) /*!< USB_RX_EN (Bitfield-Mask: 0x01) */
+/* ===================================================== USB_RXC3_REG ====================================================== */
+#define USB_USB_RXC3_REG_USB_RFWL_Pos (5UL) /*!< USB_RFWL (Bit 5) */
+#define USB_USB_RXC3_REG_USB_RFWL_Msk (0x60UL) /*!< USB_RFWL (Bitfield-Mask: 0x03) */
+#define USB_USB_RXC3_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */
+#define USB_USB_RXC3_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */
+#define USB_USB_RXC3_REG_USB_IGN_SETUP_Pos (2UL) /*!< USB_IGN_SETUP (Bit 2) */
+#define USB_USB_RXC3_REG_USB_IGN_SETUP_Msk (0x4UL) /*!< USB_IGN_SETUP (Bitfield-Mask: 0x01) */
+#define USB_USB_RXC3_REG_USB_RX_EN_Pos (0UL) /*!< USB_RX_EN (Bit 0) */
+#define USB_USB_RXC3_REG_USB_RX_EN_Msk (0x1UL) /*!< USB_RX_EN (Bitfield-Mask: 0x01) */
+/* ===================================================== USB_RXD0_REG ====================================================== */
+#define USB_USB_RXD0_REG_USB_RXFD_Pos (0UL) /*!< USB_RXFD (Bit 0) */
+#define USB_USB_RXD0_REG_USB_RXFD_Msk (0xffUL) /*!< USB_RXFD (Bitfield-Mask: 0xff) */
+/* ===================================================== USB_RXD1_REG ====================================================== */
+#define USB_USB_RXD1_REG_USB_RXFD_Pos (0UL) /*!< USB_RXFD (Bit 0) */
+#define USB_USB_RXD1_REG_USB_RXFD_Msk (0xffUL) /*!< USB_RXFD (Bitfield-Mask: 0xff) */
+/* ===================================================== USB_RXD2_REG ====================================================== */
+#define USB_USB_RXD2_REG_USB_RXFD_Pos (0UL) /*!< USB_RXFD (Bit 0) */
+#define USB_USB_RXD2_REG_USB_RXFD_Msk (0xffUL) /*!< USB_RXFD (Bitfield-Mask: 0xff) */
+/* ===================================================== USB_RXD3_REG ====================================================== */
+#define USB_USB_RXD3_REG_USB_RXFD_Pos (0UL) /*!< USB_RXFD (Bit 0) */
+#define USB_USB_RXD3_REG_USB_RXFD_Msk (0xffUL) /*!< USB_RXFD (Bitfield-Mask: 0xff) */
+/* ===================================================== USB_RXEV_REG ====================================================== */
+#define USB_USB_RXEV_REG_USB_RXOVRRN31_Pos (4UL) /*!< USB_RXOVRRN31 (Bit 4) */
+#define USB_USB_RXEV_REG_USB_RXOVRRN31_Msk (0x70UL) /*!< USB_RXOVRRN31 (Bitfield-Mask: 0x07) */
+#define USB_USB_RXEV_REG_USB_RXFIFO31_Pos (0UL) /*!< USB_RXFIFO31 (Bit 0) */
+#define USB_USB_RXEV_REG_USB_RXFIFO31_Msk (0x7UL) /*!< USB_RXFIFO31 (Bitfield-Mask: 0x07) */
+/* ===================================================== USB_RXMSK_REG ===================================================== */
+#define USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Pos (4UL) /*!< USB_M_RXOVRRN31 (Bit 4) */
+#define USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Msk (0x70UL) /*!< USB_M_RXOVRRN31 (Bitfield-Mask: 0x07) */
+#define USB_USB_RXMSK_REG_USB_M_RXFIFO31_Pos (0UL) /*!< USB_M_RXFIFO31 (Bit 0) */
+#define USB_USB_RXMSK_REG_USB_M_RXFIFO31_Msk (0x7UL) /*!< USB_M_RXFIFO31 (Bitfield-Mask: 0x07) */
+/* ===================================================== USB_RXS0_REG ====================================================== */
+#define USB_USB_RXS0_REG_USB_SETUP_Pos (6UL) /*!< USB_SETUP (Bit 6) */
+#define USB_USB_RXS0_REG_USB_SETUP_Msk (0x40UL) /*!< USB_SETUP (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS0_REG_USB_TOGGLE_RX0_Pos (5UL) /*!< USB_TOGGLE_RX0 (Bit 5) */
+#define USB_USB_RXS0_REG_USB_TOGGLE_RX0_Msk (0x20UL) /*!< USB_TOGGLE_RX0 (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS0_REG_USB_RX_LAST_Pos (4UL) /*!< USB_RX_LAST (Bit 4) */
+#define USB_USB_RXS0_REG_USB_RX_LAST_Msk (0x10UL) /*!< USB_RX_LAST (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS0_REG_USB_RCOUNT_Pos (0UL) /*!< USB_RCOUNT (Bit 0) */
+#define USB_USB_RXS0_REG_USB_RCOUNT_Msk (0xfUL) /*!< USB_RCOUNT (Bitfield-Mask: 0x0f) */
+/* ===================================================== USB_RXS1_REG ====================================================== */
+#define USB_USB_RXS1_REG_USB_RXCOUNT_Pos (8UL) /*!< USB_RXCOUNT (Bit 8) */
+#define USB_USB_RXS1_REG_USB_RXCOUNT_Msk (0x7f00UL) /*!< USB_RXCOUNT (Bitfield-Mask: 0x7f) */
+#define USB_USB_RXS1_REG_USB_RX_ERR_Pos (7UL) /*!< USB_RX_ERR (Bit 7) */
+#define USB_USB_RXS1_REG_USB_RX_ERR_Msk (0x80UL) /*!< USB_RX_ERR (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS1_REG_USB_SETUP_Pos (6UL) /*!< USB_SETUP (Bit 6) */
+#define USB_USB_RXS1_REG_USB_SETUP_Msk (0x40UL) /*!< USB_SETUP (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS1_REG_USB_TOGGLE_RX_Pos (5UL) /*!< USB_TOGGLE_RX (Bit 5) */
+#define USB_USB_RXS1_REG_USB_TOGGLE_RX_Msk (0x20UL) /*!< USB_TOGGLE_RX (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS1_REG_USB_RX_LAST_Pos (4UL) /*!< USB_RX_LAST (Bit 4) */
+#define USB_USB_RXS1_REG_USB_RX_LAST_Msk (0x10UL) /*!< USB_RX_LAST (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS1_REG_USB_RCOUNT_Pos (0UL) /*!< USB_RCOUNT (Bit 0) */
+#define USB_USB_RXS1_REG_USB_RCOUNT_Msk (0xfUL) /*!< USB_RCOUNT (Bitfield-Mask: 0x0f) */
+/* ===================================================== USB_RXS2_REG ====================================================== */
+#define USB_USB_RXS2_REG_USB_RXCOUNT_Pos (8UL) /*!< USB_RXCOUNT (Bit 8) */
+#define USB_USB_RXS2_REG_USB_RXCOUNT_Msk (0x7f00UL) /*!< USB_RXCOUNT (Bitfield-Mask: 0x7f) */
+#define USB_USB_RXS2_REG_USB_RX_ERR_Pos (7UL) /*!< USB_RX_ERR (Bit 7) */
+#define USB_USB_RXS2_REG_USB_RX_ERR_Msk (0x80UL) /*!< USB_RX_ERR (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS2_REG_USB_SETUP_Pos (6UL) /*!< USB_SETUP (Bit 6) */
+#define USB_USB_RXS2_REG_USB_SETUP_Msk (0x40UL) /*!< USB_SETUP (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS2_REG_USB_TOGGLE_RX_Pos (5UL) /*!< USB_TOGGLE_RX (Bit 5) */
+#define USB_USB_RXS2_REG_USB_TOGGLE_RX_Msk (0x20UL) /*!< USB_TOGGLE_RX (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS2_REG_USB_RX_LAST_Pos (4UL) /*!< USB_RX_LAST (Bit 4) */
+#define USB_USB_RXS2_REG_USB_RX_LAST_Msk (0x10UL) /*!< USB_RX_LAST (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS2_REG_USB_RCOUNT_Pos (0UL) /*!< USB_RCOUNT (Bit 0) */
+#define USB_USB_RXS2_REG_USB_RCOUNT_Msk (0xfUL) /*!< USB_RCOUNT (Bitfield-Mask: 0x0f) */
+/* ===================================================== USB_RXS3_REG ====================================================== */
+#define USB_USB_RXS3_REG_USB_RXCOUNT_Pos (8UL) /*!< USB_RXCOUNT (Bit 8) */
+#define USB_USB_RXS3_REG_USB_RXCOUNT_Msk (0x7f00UL) /*!< USB_RXCOUNT (Bitfield-Mask: 0x7f) */
+#define USB_USB_RXS3_REG_USB_RX_ERR_Pos (7UL) /*!< USB_RX_ERR (Bit 7) */
+#define USB_USB_RXS3_REG_USB_RX_ERR_Msk (0x80UL) /*!< USB_RX_ERR (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS3_REG_USB_SETUP_Pos (6UL) /*!< USB_SETUP (Bit 6) */
+#define USB_USB_RXS3_REG_USB_SETUP_Msk (0x40UL) /*!< USB_SETUP (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS3_REG_USB_TOGGLE_RX_Pos (5UL) /*!< USB_TOGGLE_RX (Bit 5) */
+#define USB_USB_RXS3_REG_USB_TOGGLE_RX_Msk (0x20UL) /*!< USB_TOGGLE_RX (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS3_REG_USB_RX_LAST_Pos (4UL) /*!< USB_RX_LAST (Bit 4) */
+#define USB_USB_RXS3_REG_USB_RX_LAST_Msk (0x10UL) /*!< USB_RX_LAST (Bitfield-Mask: 0x01) */
+#define USB_USB_RXS3_REG_USB_RCOUNT_Pos (0UL) /*!< USB_RCOUNT (Bit 0) */
+#define USB_USB_RXS3_REG_USB_RCOUNT_Msk (0xfUL) /*!< USB_RCOUNT (Bitfield-Mask: 0x0f) */
+/* ====================================================== USB_TCR_REG ====================================================== */
+#define USB_USB_TCR_REG_USB_VADJ_Pos (5UL) /*!< USB_VADJ (Bit 5) */
+#define USB_USB_TCR_REG_USB_VADJ_Msk (0xe0UL) /*!< USB_VADJ (Bitfield-Mask: 0x07) */
+#define USB_USB_TCR_REG_USB_CADJ_Pos (0UL) /*!< USB_CADJ (Bit 0) */
+#define USB_USB_TCR_REG_USB_CADJ_Msk (0x1fUL) /*!< USB_CADJ (Bitfield-Mask: 0x1f) */
+/* ===================================================== USB_TXC0_REG ====================================================== */
+#define USB_USB_TXC0_REG_USB_IGN_IN_Pos (4UL) /*!< USB_IGN_IN (Bit 4) */
+#define USB_USB_TXC0_REG_USB_IGN_IN_Msk (0x10UL) /*!< USB_IGN_IN (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC0_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */
+#define USB_USB_TXC0_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC0_REG_USB_TOGGLE_TX0_Pos (2UL) /*!< USB_TOGGLE_TX0 (Bit 2) */
+#define USB_USB_TXC0_REG_USB_TOGGLE_TX0_Msk (0x4UL) /*!< USB_TOGGLE_TX0 (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC0_REG_USB_TX_EN_Pos (0UL) /*!< USB_TX_EN (Bit 0) */
+#define USB_USB_TXC0_REG_USB_TX_EN_Msk (0x1UL) /*!< USB_TX_EN (Bitfield-Mask: 0x01) */
+/* ===================================================== USB_TXC1_REG ====================================================== */
+#define USB_USB_TXC1_REG_USB_IGN_ISOMSK_Pos (7UL) /*!< USB_IGN_ISOMSK (Bit 7) */
+#define USB_USB_TXC1_REG_USB_IGN_ISOMSK_Msk (0x80UL) /*!< USB_IGN_ISOMSK (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC1_REG_USB_TFWL_Pos (5UL) /*!< USB_TFWL (Bit 5) */
+#define USB_USB_TXC1_REG_USB_TFWL_Msk (0x60UL) /*!< USB_TFWL (Bitfield-Mask: 0x03) */
+#define USB_USB_TXC1_REG_USB_RFF_Pos (4UL) /*!< USB_RFF (Bit 4) */
+#define USB_USB_TXC1_REG_USB_RFF_Msk (0x10UL) /*!< USB_RFF (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC1_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */
+#define USB_USB_TXC1_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC1_REG_USB_TOGGLE_TX_Pos (2UL) /*!< USB_TOGGLE_TX (Bit 2) */
+#define USB_USB_TXC1_REG_USB_TOGGLE_TX_Msk (0x4UL) /*!< USB_TOGGLE_TX (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC1_REG_USB_LAST_Pos (1UL) /*!< USB_LAST (Bit 1) */
+#define USB_USB_TXC1_REG_USB_LAST_Msk (0x2UL) /*!< USB_LAST (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC1_REG_USB_TX_EN_Pos (0UL) /*!< USB_TX_EN (Bit 0) */
+#define USB_USB_TXC1_REG_USB_TX_EN_Msk (0x1UL) /*!< USB_TX_EN (Bitfield-Mask: 0x01) */
+/* ===================================================== USB_TXC2_REG ====================================================== */
+#define USB_USB_TXC2_REG_USB_IGN_ISOMSK_Pos (7UL) /*!< USB_IGN_ISOMSK (Bit 7) */
+#define USB_USB_TXC2_REG_USB_IGN_ISOMSK_Msk (0x80UL) /*!< USB_IGN_ISOMSK (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC2_REG_USB_TFWL_Pos (5UL) /*!< USB_TFWL (Bit 5) */
+#define USB_USB_TXC2_REG_USB_TFWL_Msk (0x60UL) /*!< USB_TFWL (Bitfield-Mask: 0x03) */
+#define USB_USB_TXC2_REG_USB_RFF_Pos (4UL) /*!< USB_RFF (Bit 4) */
+#define USB_USB_TXC2_REG_USB_RFF_Msk (0x10UL) /*!< USB_RFF (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC2_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */
+#define USB_USB_TXC2_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC2_REG_USB_TOGGLE_TX_Pos (2UL) /*!< USB_TOGGLE_TX (Bit 2) */
+#define USB_USB_TXC2_REG_USB_TOGGLE_TX_Msk (0x4UL) /*!< USB_TOGGLE_TX (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC2_REG_USB_LAST_Pos (1UL) /*!< USB_LAST (Bit 1) */
+#define USB_USB_TXC2_REG_USB_LAST_Msk (0x2UL) /*!< USB_LAST (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC2_REG_USB_TX_EN_Pos (0UL) /*!< USB_TX_EN (Bit 0) */
+#define USB_USB_TXC2_REG_USB_TX_EN_Msk (0x1UL) /*!< USB_TX_EN (Bitfield-Mask: 0x01) */
+/* ===================================================== USB_TXC3_REG ====================================================== */
+#define USB_USB_TXC3_REG_USB_IGN_ISOMSK_Pos (7UL) /*!< USB_IGN_ISOMSK (Bit 7) */
+#define USB_USB_TXC3_REG_USB_IGN_ISOMSK_Msk (0x80UL) /*!< USB_IGN_ISOMSK (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC3_REG_USB_TFWL_Pos (5UL) /*!< USB_TFWL (Bit 5) */
+#define USB_USB_TXC3_REG_USB_TFWL_Msk (0x60UL) /*!< USB_TFWL (Bitfield-Mask: 0x03) */
+#define USB_USB_TXC3_REG_USB_RFF_Pos (4UL) /*!< USB_RFF (Bit 4) */
+#define USB_USB_TXC3_REG_USB_RFF_Msk (0x10UL) /*!< USB_RFF (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC3_REG_USB_FLUSH_Pos (3UL) /*!< USB_FLUSH (Bit 3) */
+#define USB_USB_TXC3_REG_USB_FLUSH_Msk (0x8UL) /*!< USB_FLUSH (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC3_REG_USB_TOGGLE_TX_Pos (2UL) /*!< USB_TOGGLE_TX (Bit 2) */
+#define USB_USB_TXC3_REG_USB_TOGGLE_TX_Msk (0x4UL) /*!< USB_TOGGLE_TX (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC3_REG_USB_LAST_Pos (1UL) /*!< USB_LAST (Bit 1) */
+#define USB_USB_TXC3_REG_USB_LAST_Msk (0x2UL) /*!< USB_LAST (Bitfield-Mask: 0x01) */
+#define USB_USB_TXC3_REG_USB_TX_EN_Pos (0UL) /*!< USB_TX_EN (Bit 0) */
+#define USB_USB_TXC3_REG_USB_TX_EN_Msk (0x1UL) /*!< USB_TX_EN (Bitfield-Mask: 0x01) */
+/* ===================================================== USB_TXD0_REG ====================================================== */
+#define USB_USB_TXD0_REG_USB_TXFD_Pos (0UL) /*!< USB_TXFD (Bit 0) */
+#define USB_USB_TXD0_REG_USB_TXFD_Msk (0xffUL) /*!< USB_TXFD (Bitfield-Mask: 0xff) */
+/* ===================================================== USB_TXD1_REG ====================================================== */
+#define USB_USB_TXD1_REG_USB_TXFD_Pos (0UL) /*!< USB_TXFD (Bit 0) */
+#define USB_USB_TXD1_REG_USB_TXFD_Msk (0xffUL) /*!< USB_TXFD (Bitfield-Mask: 0xff) */
+/* ===================================================== USB_TXD2_REG ====================================================== */
+#define USB_USB_TXD2_REG_USB_TXFD_Pos (0UL) /*!< USB_TXFD (Bit 0) */
+#define USB_USB_TXD2_REG_USB_TXFD_Msk (0xffUL) /*!< USB_TXFD (Bitfield-Mask: 0xff) */
+/* ===================================================== USB_TXD3_REG ====================================================== */
+#define USB_USB_TXD3_REG_USB_TXFD_Pos (0UL) /*!< USB_TXFD (Bit 0) */
+#define USB_USB_TXD3_REG_USB_TXFD_Msk (0xffUL) /*!< USB_TXFD (Bitfield-Mask: 0xff) */
+/* ===================================================== USB_TXEV_REG ====================================================== */
+#define USB_USB_TXEV_REG_USB_TXUDRRN31_Pos (4UL) /*!< USB_TXUDRRN31 (Bit 4) */
+#define USB_USB_TXEV_REG_USB_TXUDRRN31_Msk (0x70UL) /*!< USB_TXUDRRN31 (Bitfield-Mask: 0x07) */
+#define USB_USB_TXEV_REG_USB_TXFIFO31_Pos (0UL) /*!< USB_TXFIFO31 (Bit 0) */
+#define USB_USB_TXEV_REG_USB_TXFIFO31_Msk (0x7UL) /*!< USB_TXFIFO31 (Bitfield-Mask: 0x07) */
+/* ===================================================== USB_TXMSK_REG ===================================================== */
+#define USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Pos (4UL) /*!< USB_M_TXUDRRN31 (Bit 4) */
+#define USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Msk (0x70UL) /*!< USB_M_TXUDRRN31 (Bitfield-Mask: 0x07) */
+#define USB_USB_TXMSK_REG_USB_M_TXFIFO31_Pos (0UL) /*!< USB_M_TXFIFO31 (Bit 0) */
+#define USB_USB_TXMSK_REG_USB_M_TXFIFO31_Msk (0x7UL) /*!< USB_M_TXFIFO31 (Bitfield-Mask: 0x07) */
+/* ===================================================== USB_TXS0_REG ====================================================== */
+#define USB_USB_TXS0_REG_USB_ACK_STAT_Pos (6UL) /*!< USB_ACK_STAT (Bit 6) */
+#define USB_USB_TXS0_REG_USB_ACK_STAT_Msk (0x40UL) /*!< USB_ACK_STAT (Bitfield-Mask: 0x01) */
+#define USB_USB_TXS0_REG_USB_TX_DONE_Pos (5UL) /*!< USB_TX_DONE (Bit 5) */
+#define USB_USB_TXS0_REG_USB_TX_DONE_Msk (0x20UL) /*!< USB_TX_DONE (Bitfield-Mask: 0x01) */
+#define USB_USB_TXS0_REG_USB_TCOUNT_Pos (0UL) /*!< USB_TCOUNT (Bit 0) */
+#define USB_USB_TXS0_REG_USB_TCOUNT_Msk (0x1fUL) /*!< USB_TCOUNT (Bitfield-Mask: 0x1f) */
+/* ===================================================== USB_TXS1_REG ====================================================== */
+#define USB_USB_TXS1_REG_USB_TX_URUN_Pos (7UL) /*!< USB_TX_URUN (Bit 7) */
+#define USB_USB_TXS1_REG_USB_TX_URUN_Msk (0x80UL) /*!< USB_TX_URUN (Bitfield-Mask: 0x01) */
+#define USB_USB_TXS1_REG_USB_ACK_STAT_Pos (6UL) /*!< USB_ACK_STAT (Bit 6) */
+#define USB_USB_TXS1_REG_USB_ACK_STAT_Msk (0x40UL) /*!< USB_ACK_STAT (Bitfield-Mask: 0x01) */
+#define USB_USB_TXS1_REG_USB_TX_DONE_Pos (5UL) /*!< USB_TX_DONE (Bit 5) */
+#define USB_USB_TXS1_REG_USB_TX_DONE_Msk (0x20UL) /*!< USB_TX_DONE (Bitfield-Mask: 0x01) */
+#define USB_USB_TXS1_REG_USB_TCOUNT_Pos (0UL) /*!< USB_TCOUNT (Bit 0) */
+#define USB_USB_TXS1_REG_USB_TCOUNT_Msk (0x1fUL) /*!< USB_TCOUNT (Bitfield-Mask: 0x1f) */
+/* ===================================================== USB_TXS2_REG ====================================================== */
+#define USB_USB_TXS2_REG_USB_TX_URUN_Pos (7UL) /*!< USB_TX_URUN (Bit 7) */
+#define USB_USB_TXS2_REG_USB_TX_URUN_Msk (0x80UL) /*!< USB_TX_URUN (Bitfield-Mask: 0x01) */
+#define USB_USB_TXS2_REG_USB_ACK_STAT_Pos (6UL) /*!< USB_ACK_STAT (Bit 6) */
+#define USB_USB_TXS2_REG_USB_ACK_STAT_Msk (0x40UL) /*!< USB_ACK_STAT (Bitfield-Mask: 0x01) */
+#define USB_USB_TXS2_REG_USB_TX_DONE_Pos (5UL) /*!< USB_TX_DONE (Bit 5) */
+#define USB_USB_TXS2_REG_USB_TX_DONE_Msk (0x20UL) /*!< USB_TX_DONE (Bitfield-Mask: 0x01) */
+#define USB_USB_TXS2_REG_USB_TCOUNT_Pos (0UL) /*!< USB_TCOUNT (Bit 0) */
+#define USB_USB_TXS2_REG_USB_TCOUNT_Msk (0x1fUL) /*!< USB_TCOUNT (Bitfield-Mask: 0x1f) */
+/* ===================================================== USB_TXS3_REG ====================================================== */
+#define USB_USB_TXS3_REG_USB_TX_URUN_Pos (7UL) /*!< USB_TX_URUN (Bit 7) */
+#define USB_USB_TXS3_REG_USB_TX_URUN_Msk (0x80UL) /*!< USB_TX_URUN (Bitfield-Mask: 0x01) */
+#define USB_USB_TXS3_REG_USB_ACK_STAT_Pos (6UL) /*!< USB_ACK_STAT (Bit 6) */
+#define USB_USB_TXS3_REG_USB_ACK_STAT_Msk (0x40UL) /*!< USB_ACK_STAT (Bitfield-Mask: 0x01) */
+#define USB_USB_TXS3_REG_USB_TX_DONE_Pos (5UL) /*!< USB_TX_DONE (Bit 5) */
+#define USB_USB_TXS3_REG_USB_TX_DONE_Msk (0x20UL) /*!< USB_TX_DONE (Bitfield-Mask: 0x01) */
+#define USB_USB_TXS3_REG_USB_TCOUNT_Pos (0UL) /*!< USB_TCOUNT (Bit 0) */
+#define USB_USB_TXS3_REG_USB_TCOUNT_Msk (0x1fUL) /*!< USB_TCOUNT (Bitfield-Mask: 0x1f) */
+/* ====================================================== USB_UTR_REG ====================================================== */
+#define USB_USB_UTR_REG_USB_DIAG_Pos (7UL) /*!< USB_DIAG (Bit 7) */
+#define USB_USB_UTR_REG_USB_DIAG_Msk (0x80UL) /*!< USB_DIAG (Bitfield-Mask: 0x01) */
+#define USB_USB_UTR_REG_USB_NCRC_Pos (6UL) /*!< USB_NCRC (Bit 6) */
+#define USB_USB_UTR_REG_USB_NCRC_Msk (0x40UL) /*!< USB_NCRC (Bitfield-Mask: 0x01) */
+#define USB_USB_UTR_REG_USB_SF_Pos (5UL) /*!< USB_SF (Bit 5) */
+#define USB_USB_UTR_REG_USB_SF_Msk (0x20UL) /*!< USB_SF (Bitfield-Mask: 0x01) */
+#define USB_USB_UTR_REG_USB_UTR_RES_Pos (0UL) /*!< USB_UTR_RES (Bit 0) */
+#define USB_USB_UTR_REG_USB_UTR_RES_Msk (0x1fUL) /*!< USB_UTR_RES (Bitfield-Mask: 0x1f) */
+/* ==================================================== USB_UX20CDR_REG ==================================================== */
+#define USB_USB_UX20CDR_REG_RPU_TEST7_Pos (7UL) /*!< RPU_TEST7 (Bit 7) */
+#define USB_USB_UX20CDR_REG_RPU_TEST7_Msk (0x80UL) /*!< RPU_TEST7 (Bitfield-Mask: 0x01) */
+#define USB_USB_UX20CDR_REG_RPU_TEST_SW2_Pos (6UL) /*!< RPU_TEST_SW2 (Bit 6) */
+#define USB_USB_UX20CDR_REG_RPU_TEST_SW2_Msk (0x40UL) /*!< RPU_TEST_SW2 (Bitfield-Mask: 0x01) */
+#define USB_USB_UX20CDR_REG_RPU_TEST_SW1_Pos (5UL) /*!< RPU_TEST_SW1 (Bit 5) */
+#define USB_USB_UX20CDR_REG_RPU_TEST_SW1_Msk (0x20UL) /*!< RPU_TEST_SW1 (Bitfield-Mask: 0x01) */
+#define USB_USB_UX20CDR_REG_RPU_TEST_EN_Pos (4UL) /*!< RPU_TEST_EN (Bit 4) */
+#define USB_USB_UX20CDR_REG_RPU_TEST_EN_Msk (0x10UL) /*!< RPU_TEST_EN (Bitfield-Mask: 0x01) */
+#define USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Pos (2UL) /*!< RPU_TEST_SW1DM (Bit 2) */
+#define USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Msk (0x4UL) /*!< RPU_TEST_SW1DM (Bitfield-Mask: 0x01) */
+#define USB_USB_UX20CDR_REG_RPU_RCDELAY_Pos (1UL) /*!< RPU_RCDELAY (Bit 1) */
+#define USB_USB_UX20CDR_REG_RPU_RCDELAY_Msk (0x2UL) /*!< RPU_RCDELAY (Bitfield-Mask: 0x01) */
+#define USB_USB_UX20CDR_REG_RPU_SSPROTEN_Pos (0UL) /*!< RPU_SSPROTEN (Bit 0) */
+#define USB_USB_UX20CDR_REG_RPU_SSPROTEN_Msk (0x1UL) /*!< RPU_SSPROTEN (Bitfield-Mask: 0x01) */
+/* ==================================================== USB_XCVDIAG_REG ==================================================== */
+#define USB_USB_XCVDIAG_REG_USB_VPIN_Pos (7UL) /*!< USB_VPIN (Bit 7) */
+#define USB_USB_XCVDIAG_REG_USB_VPIN_Msk (0x80UL) /*!< USB_VPIN (Bitfield-Mask: 0x01) */
+#define USB_USB_XCVDIAG_REG_USB_VMIN_Pos (6UL) /*!< USB_VMIN (Bit 6) */
+#define USB_USB_XCVDIAG_REG_USB_VMIN_Msk (0x40UL) /*!< USB_VMIN (Bitfield-Mask: 0x01) */
+#define USB_USB_XCVDIAG_REG_USB_RCV_Pos (5UL) /*!< USB_RCV (Bit 5) */
+#define USB_USB_XCVDIAG_REG_USB_RCV_Msk (0x20UL) /*!< USB_RCV (Bitfield-Mask: 0x01) */
+#define USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Pos (3UL) /*!< USB_XCV_TXEN (Bit 3) */
+#define USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Msk (0x8UL) /*!< USB_XCV_TXEN (Bitfield-Mask: 0x01) */
+#define USB_USB_XCVDIAG_REG_USB_XCV_TXn_Pos (2UL) /*!< USB_XCV_TXn (Bit 2) */
+#define USB_USB_XCVDIAG_REG_USB_XCV_TXn_Msk (0x4UL) /*!< USB_XCV_TXn (Bitfield-Mask: 0x01) */
+#define USB_USB_XCVDIAG_REG_USB_XCV_TXp_Pos (1UL) /*!< USB_XCV_TXp (Bit 1) */
+#define USB_USB_XCVDIAG_REG_USB_XCV_TXp_Msk (0x2UL) /*!< USB_XCV_TXp (Bitfield-Mask: 0x01) */
+#define USB_USB_XCVDIAG_REG_USB_XCV_TEST_Pos (0UL) /*!< USB_XCV_TEST (Bit 0) */
+#define USB_USB_XCVDIAG_REG_USB_XCV_TEST_Msk (0x1UL) /*!< USB_XCV_TEST (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ WAKEUP ================ */
+/* =========================================================================================================================== */
+
+/* =================================================== WKUP_CLEAR_P0_REG =================================================== */
+#define WAKEUP_WKUP_CLEAR_P0_REG_WKUP_CLEAR_P0_Pos (0UL) /*!< WKUP_CLEAR_P0 (Bit 0) */
+#define WAKEUP_WKUP_CLEAR_P0_REG_WKUP_CLEAR_P0_Msk (0xffffffffUL) /*!< WKUP_CLEAR_P0 (Bitfield-Mask: 0xffffffff) */
+/* =================================================== WKUP_CLEAR_P1_REG =================================================== */
+#define WAKEUP_WKUP_CLEAR_P1_REG_WKUP_CLEAR_P1_Pos (0UL) /*!< WKUP_CLEAR_P1 (Bit 0) */
+#define WAKEUP_WKUP_CLEAR_P1_REG_WKUP_CLEAR_P1_Msk (0x7fffffUL) /*!< WKUP_CLEAR_P1 (Bitfield-Mask: 0x7fffff) */
+/* ===================================================== WKUP_CTRL_REG ===================================================== */
+#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Pos (7UL) /*!< WKUP_ENABLE_IRQ (Bit 7) */
+#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk (0x80UL) /*!< WKUP_ENABLE_IRQ (Bitfield-Mask: 0x01) */
+#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Pos (6UL) /*!< WKUP_SFT_KEYHIT (Bit 6) */
+#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Msk (0x40UL) /*!< WKUP_SFT_KEYHIT (Bitfield-Mask: 0x01) */
+#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Pos (0UL) /*!< WKUP_DEB_VALUE (Bit 0) */
+#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Msk (0x3fUL) /*!< WKUP_DEB_VALUE (Bitfield-Mask: 0x3f) */
+/* ==================================================== WKUP_POL_P0_REG ==================================================== */
+#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Pos (0UL) /*!< WKUP_POL_P0 (Bit 0) */
+#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Msk (0xffffffffUL) /*!< WKUP_POL_P0 (Bitfield-Mask: 0xffffffff) */
+/* ==================================================== WKUP_POL_P1_REG ==================================================== */
+#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Pos (0UL) /*!< WKUP_POL_P1 (Bit 0) */
+#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Msk (0x7fffffUL) /*!< WKUP_POL_P1 (Bitfield-Mask: 0x7fffff) */
+/* ================================================== WKUP_RESET_IRQ_REG =================================================== */
+#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Pos (0UL) /*!< WKUP_IRQ_RST (Bit 0) */
+#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk (0xffffUL) /*!< WKUP_IRQ_RST (Bitfield-Mask: 0xffff) */
+/* ================================================== WKUP_SELECT_P0_REG =================================================== */
+#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Pos (0UL) /*!< WKUP_SELECT_P0 (Bit 0) */
+#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Msk (0xffffffffUL) /*!< WKUP_SELECT_P0 (Bitfield-Mask: 0xffffffff) */
+/* ================================================== WKUP_SELECT_P1_REG =================================================== */
+#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Pos (0UL) /*!< WKUP_SELECT_P1 (Bit 0) */
+#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Msk (0x7fffffUL) /*!< WKUP_SELECT_P1 (Bitfield-Mask: 0x7fffff) */
+/* ================================================= WKUP_SEL_GPIO_P0_REG ================================================== */
+#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Pos (0UL) /*!< WKUP_SEL_GPIO_P0 (Bit 0) */
+#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Msk (0xffffffffUL) /*!< WKUP_SEL_GPIO_P0 (Bitfield-Mask: 0xffffffff) */
+/* ================================================= WKUP_SEL_GPIO_P1_REG ================================================== */
+#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Pos (0UL) /*!< WKUP_SEL_GPIO_P1 (Bit 0) */
+#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Msk (0x7fffffUL) /*!< WKUP_SEL_GPIO_P1 (Bitfield-Mask: 0x7fffff) */
+/* ================================================== WKUP_STATUS_P0_REG =================================================== */
+#define WAKEUP_WKUP_STATUS_P0_REG_WKUP_STAT_P0_Pos (0UL) /*!< WKUP_STAT_P0 (Bit 0) */
+#define WAKEUP_WKUP_STATUS_P0_REG_WKUP_STAT_P0_Msk (0xffffffffUL) /*!< WKUP_STAT_P0 (Bitfield-Mask: 0xffffffff) */
+/* ================================================== WKUP_STATUS_P1_REG =================================================== */
+#define WAKEUP_WKUP_STATUS_P1_REG_WKUP_STAT_P1_Pos (0UL) /*!< WKUP_STAT_P1 (Bit 0) */
+#define WAKEUP_WKUP_STATUS_P1_REG_WKUP_STAT_P1_Msk (0x7fffffUL) /*!< WKUP_STAT_P1 (Bitfield-Mask: 0x7fffff) */
+
+/** @} */ /* End of group PosMask_peripherals */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DA1469X_H */
+
+
+/** @} */ /* End of group DA1469x */
+
+/** @} */ /* End of group PLA_BSP_REGISTERS */
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h
new file mode 100644
index 0000000..fdb1a97
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h
@@ -0,0 +1,271 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.1.0
+ * @date 09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+ #include "cmsis_armclang_ltm.h"
+
+ /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include <cmsis_ccs.h>
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #define __RESTRICT __restrict
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h
new file mode 100644
index 0000000..47a4b59
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h
@@ -0,0 +1,2102 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.1.0
+ * @date 20. December 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ /* Copyright (c) 2019 Modified by Dialog Semiconductor */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] val Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] val Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_version.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_version.h
new file mode 100644
index 0000000..660f612
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.2
+ * @date 19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h
new file mode 100644
index 0000000..e2cf6b9
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h
@@ -0,0 +1,950 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V5.0.6
+ * @date 13. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ /* Copyright (c) 2019 Modified by Dialog Semiconductor */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M0
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000U
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref __NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref __NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t vectors = 0x0U;
+ (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t vectors = 0x0U;
+ return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h
new file mode 100644
index 0000000..7249e13
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h
@@ -0,0 +1,2908 @@
+/**************************************************************************//**
+ * @file core_cm33.h
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version V5.1.0
+ * @date 12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ /* Copyright (c) 2019 Modified by Dialog Semiconductor */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M33
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (33U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined (__TARGET_FPU_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined (__ARM_FP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined (__ARMVFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined (__TI_VFP_SUPPORT__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined (__FPU_VFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM33_REV
+ #define __CM33_REV 0x0000U
+ #warning "__CM33_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref __NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with \ref __NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h
new file mode 100644
index 0000000..bc3b051
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h
@@ -0,0 +1,347 @@
+/******************************************************************************
+ * @file mpu_armv8.h
+ * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version V5.1.0
+ * @date 08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ /* Copyright (c) 2019 Modified by Dialog Semiconductor */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+ (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable */
+#define ARM_MPU_SH_NON (0U)
+
+/** \brief Normal memory outer shareable */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \param XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+ ((BASE & MPU_RBAR_BASE_Msk) | \
+ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+ ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; /*!< Region Base Address Register value */
+ uint32_t RLAR; /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+ const uint8_t reg = idx / 4U;
+ const uint32_t pos = ((idx % 4U) * 8U);
+ const uint32_t mask = 0xFFU << pos;
+
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+ return; // invalid index
+ }
+
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+ mpu->RNR = rnr;
+ mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ mpu->RNR = rnr;
+ mpu->RBAR = rbar;
+ mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ if (cnt == 1U) {
+ mpu->RNR = rnr;
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+ } else {
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+
+ mpu->RNR = rnrBase;
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+ table += c;
+ cnt -= c;
+ rnrOffset = 0U;
+ rnrBase += MPU_TYPE_RALIASES;
+ mpu->RNR = rnrBase;
+ }
+
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_ARMCM0.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_ARMCM0.h
new file mode 100644
index 0000000..7fe7e91
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_ARMCM0.h
@@ -0,0 +1,55 @@
+/**************************************************************************//**
+ * @file system_ARMCM0.h
+ * @brief CMSIS Device System Header File for
+ * ARMCM0 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef SYSTEM_ARMCM0_H
+#define SYSTEM_ARMCM0_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ARMCM0_H */
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_DA1469x.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_DA1469x.h
new file mode 100644
index 0000000..6c53ee9
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/system_DA1469x.h
@@ -0,0 +1,72 @@
+/**************************************************************************//**
+ * @file system_DA1469x.h
+ * @brief CMSIS Device System Header File for DA1469x Device
+ * @version V5.3.1
+ * @date 17. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/* Copyright (c) 2017 Modified by Dialog Semiconductor */
+
+
+#ifndef SYSTEM_DA1469x_H
+#define SYSTEM_DA1469x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ * \brief Convert a CPU address to a physical address
+ *
+ * To calculate the physical address, the current remapping (SYS_CTRL_REG.REMAP_ADR0)
+ * is used.
+ *
+ * \param [in] addr address seen by CPU
+ *
+ * \return physical address (for DMA, AES/HASH etc.) -- can be same or different as addr
+ *
+ */
+extern uint32_t black_orca_phy_addr(uint32_t addr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_DA1469x_H */
diff --git a/hw/mcu/dialog/da1469x/da1469x.ld b/hw/mcu/dialog/da1469x/da1469x.ld
new file mode 100644
index 0000000..c91dea8
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/da1469x.ld
@@ -0,0 +1,228 @@
+/* Linker script for Dialog DA1469x devices
+ *
+ * Version: Sourcery G++ 4.5-1
+ * Support: https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __bssnz_start__
+ * __bssnz_end__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .imghdr (NOLOAD):
+ {
+ . = . + _imghdr_size;
+ } > FLASH
+
+ __text = .;
+
+ .text :
+ {
+ __isr_vector_start = .;
+ KEEP(*(.isr_vector))
+ /* ISR vector shall have exactly 512 bytes */
+ . = __isr_vector_start + 0x200;
+ __isr_vector_end = .;
+
+ *(.text)
+ *(.text.*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ *(.eh_frame*)
+ . = ALIGN(4);
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ . = ALIGN(4);
+ } > FLASH
+ __exidx_end = .;
+
+ .intvect :
+ {
+ . = ALIGN(4);
+ __intvect_start__ = .;
+ . = . + (__isr_vector_end - __isr_vector_start);
+ . = ALIGN(4);
+ } > RAM
+
+ .sleep_state (NOLOAD) :
+ {
+ . = ALIGN(4);
+ *(sleep_state)
+ } > RAM
+
+ /* This section will be zeroed by RTT package init */
+ .rtt (NOLOAD):
+ {
+ . = ALIGN(4);
+ *(.rtt)
+ . = ALIGN(4);
+ } > RAM
+
+ __text_ram_addr = LOADADDR(.text_ram);
+
+ .text_ram :
+ {
+ . = ALIGN(4);
+ __text_ram_start__ = .;
+ *(.text_ram*)
+ . = ALIGN(4);
+ __text_ram_end__ = .;
+ } > RAM AT > FLASH
+
+ __etext = LOADADDR(.data);
+
+ .data :
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ *(.preinit_array)
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ *(SORT(.init_array.*))
+ *(.init_array)
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ *(SORT(.fini_array.*))
+ *(.fini_array)
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.jcr)
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ } > RAM AT > FLASH
+
+ .bssnz :
+ {
+ . = ALIGN(4);
+ __bssnz_start__ = .;
+ *(.bss.core.nz*)
+ . = ALIGN(4);
+ __bssnz_end__ = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .cmac (NOLOAD) :
+ {
+ . = ALIGN(0x400);
+ *(.libcmac.ram)
+ } > RAM
+
+ /* Heap starts after BSS */
+ . = ALIGN(8);
+ __HeapBase = .;
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ _ram_start = ORIGIN(RAM);
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Top of head is the bottom of the stack */
+ __HeapLimit = __StackLimit;
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
+
+ /* Check that intvect is at the beginning of RAM */
+ ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM")
+}
+
diff --git a/hw/mcu/dialog/da1469x/include/hal/hal_gpio.h b/hw/mcu/dialog/da1469x/include/hal/hal_gpio.h
new file mode 100644
index 0000000..67fc3c1
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/include/hal/hal_gpio.h
@@ -0,0 +1,184 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+
+/**
+ * @addtogroup HAL
+ * @{
+ * @defgroup HALGpio HAL GPIO
+ * @{
+ */
+
+#ifndef H_HAL_GPIO_
+#define H_HAL_GPIO_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * The "mode" of the gpio. The gpio is either an input, output, or it is
+ * "not connected" (the pin specified is not functioning as a gpio)
+ */
+enum hal_gpio_mode_e {
+ /** Not connected */
+ HAL_GPIO_MODE_NC = -1,
+ /** Input */
+ HAL_GPIO_MODE_IN = 0,
+ /** Output */
+ HAL_GPIO_MODE_OUT = 1
+};
+typedef enum hal_gpio_mode_e hal_gpio_mode_t;
+
+/*
+ * The "pull" of the gpio. This is either an input or an output.
+ */
+enum hal_gpio_pull {
+ /** Pull-up/down not enabled */
+ HAL_GPIO_PULL_NONE = 0,
+ /** Pull-up enabled */
+ HAL_GPIO_PULL_UP = 1,
+ /** Pull-down enabled */
+ HAL_GPIO_PULL_DOWN = 2
+};
+typedef enum hal_gpio_pull hal_gpio_pull_t;
+
+/*
+ * IRQ trigger type.
+ */
+enum hal_gpio_irq_trigger {
+ HAL_GPIO_TRIG_NONE = 0,
+ /** IRQ occurs on rising edge */
+ HAL_GPIO_TRIG_RISING = 1,
+ /** IRQ occurs on falling edge */
+ HAL_GPIO_TRIG_FALLING = 2,
+ /** IRQ occurs on either edge */
+ HAL_GPIO_TRIG_BOTH = 3,
+ /** IRQ occurs when line is low */
+ HAL_GPIO_TRIG_LOW = 4,
+ /** IRQ occurs when line is high */
+ HAL_GPIO_TRIG_HIGH = 5
+};
+typedef enum hal_gpio_irq_trigger hal_gpio_irq_trig_t;
+
+/* Function proto for GPIO irq handler functions */
+typedef void (*hal_gpio_irq_handler_t)(void *arg);
+
+/**
+ * Initializes the specified pin as an input
+ *
+ * @param pin Pin number to set as input
+ * @param pull pull type
+ *
+ * @return int 0: no error; -1 otherwise.
+ */
+int hal_gpio_init_in(int pin, hal_gpio_pull_t pull);
+
+/**
+ * Initialize the specified pin as an output, setting the pin to the specified
+ * value.
+ *
+ * @param pin Pin number to set as output
+ * @param val Value to set pin
+ *
+ * @return int 0: no error; -1 otherwise.
+ */
+int hal_gpio_init_out(int pin, int val);
+
+/**
+ * Deinitialize the specified pin to revert the previous initialization
+ *
+ * @param pin Pin number to unset
+ *
+ * @return int 0: no error; -1 otherwise.
+ */
+int hal_gpio_deinit(int pin);
+
+/**
+ * Write a value (either high or low) to the specified pin.
+ *
+ * @param pin Pin to set
+ * @param val Value to set pin (0:low 1:high)
+ */
+void hal_gpio_write(int pin, int val);
+
+/**
+ * Reads the specified pin.
+ *
+ * @param pin Pin number to read
+ *
+ * @return int 0: low, 1: high
+ */
+int hal_gpio_read(int pin);
+
+/**
+ * Toggles the specified pin
+ *
+ * @param pin Pin number to toggle
+ *
+ * @return current gpio state int 0: low, 1: high
+ */
+int hal_gpio_toggle(int pin);
+
+/**
+ * Initialize a given pin to trigger a GPIO IRQ callback.
+ *
+ * @param pin The pin to trigger GPIO interrupt on
+ * @param handler The handler function to call
+ * @param arg The argument to provide to the IRQ handler
+ * @param trig The trigger mode (e.g. rising, falling)
+ * @param pull The mode of the pin (e.g. pullup, pulldown)
+ *
+ * @return 0 on success, non-zero error code on failure.
+ */
+int hal_gpio_irq_init(int pin, hal_gpio_irq_handler_t handler, void *arg,
+ hal_gpio_irq_trig_t trig, hal_gpio_pull_t pull);
+
+/**
+ * Release a pin from being configured to trigger IRQ on state change.
+ *
+ * @param pin The pin to release
+ */
+void hal_gpio_irq_release(int pin);
+
+/**
+ * Enable IRQs on the passed pin
+ *
+ * @param pin The pin to enable IRQs on
+ */
+void hal_gpio_irq_enable(int pin);
+
+/**
+ * Disable IRQs on the passed pin
+ *
+ * @param pin The pin to disable IRQs on
+ */
+void hal_gpio_irq_disable(int pin);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_HAL_GPIO_ */
+
+/**
+ * @} HALGpio
+ * @} HAL
+ */
diff --git a/hw/mcu/dialog/da1469x/include/mcu/da1469x_clock.h b/hw/mcu/dialog/da1469x/include/mcu/da1469x_clock.h
new file mode 100644
index 0000000..3c69774
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/include/mcu/da1469x_clock.h
@@ -0,0 +1,138 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_DA1469X_CLOCK_H_
+#define __MCU_DA1469X_CLOCK_H_
+
+#include <stdint.h>
+#include "mcu/da1469x_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Initialize XTAL32M
+ */
+void da1469x_clock_sys_xtal32m_init(void);
+
+/**
+ * Enable XTAL32M
+ */
+void da1469x_clock_sys_xtal32m_enable(void);
+
+/**
+ * Wait for XTAL32M to settle
+ */
+void da1469x_clock_sys_xtal32m_wait_to_settle(void);
+
+/**
+ * Switch sys_clk to XTAL32M
+ *
+ * Caller shall ensure that XTAL32M is already settled.
+ */
+void da1469x_clock_sys_xtal32m_switch(void);
+
+/**
+ * Switch sys_clk to XTAL32M
+ *
+ * Waits for XTAL32M to settle before switching.
+ */
+void da1469x_clock_sys_xtal32m_switch_safe(void);
+
+/**
+ * Disable RC32M
+ */
+void da1469x_clock_sys_rc32m_disable(void);
+
+/**
+ * Enable AMBA clock(s)
+ *
+ * @param mask
+ */
+static inline void
+da1469x_clock_amba_enable(uint32_t mask)
+{
+ uint32_t primask;
+
+ __HAL_DISABLE_INTERRUPTS(primask);
+ CRG_TOP->CLK_AMBA_REG |= mask;
+ __HAL_ENABLE_INTERRUPTS(primask);
+}
+
+/**
+ * Disable AMBA clock(s)
+ *
+ * @param uint32_t mask
+ */
+static inline void
+da1469x_clock_amba_disable(uint32_t mask)
+{
+ uint32_t primask;
+
+ __HAL_DISABLE_INTERRUPTS(primask);
+ CRG_TOP->CLK_AMBA_REG &= ~mask;
+ __HAL_ENABLE_INTERRUPTS(primask);
+}
+
+/**
+ * Enable PLL96
+ */
+static inline void
+da1469x_clock_sys_pll_enable(void)
+{
+ CRG_XTAL->PLL_SYS_CTRL1_REG |= CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_EN_Msk |
+ CRG_XTAL_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Msk;
+}
+
+/**
+ * Disable PLL96
+ *
+ * If PLL was used as SYS_CLOCK switches to XTAL32M.
+ */
+void da1469x_clock_sys_pll_disable(void);
+
+/**
+ * Checks whether PLL96 is locked and can be use as system clock or USB clock
+ *
+ * @return 0 if PLL is off, non-0 it its running
+ */
+static inline int
+da1469x_clock_is_pll_locked(void)
+{
+ return 0 != (CRG_XTAL->PLL_SYS_STATUS_REG & CRG_XTAL_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Msk);
+}
+
+/**
+ * Waits for PLL96 to lock.
+ */
+void da1469x_clock_pll_wait_to_lock(void);
+
+/**
+ * Switches system clock to PLL96
+ *
+ * Caller shall ensure that PLL is already locked.
+ */
+void da1469x_clock_sys_pll_switch(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_DA1469X_CLOCK_H_ */
diff --git a/hw/mcu/dialog/da1469x/include/mcu/da1469x_hal.h b/hw/mcu/dialog/da1469x/include/mcu/da1469x_hal.h
new file mode 100644
index 0000000..28fa1aa
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/include/mcu/da1469x_hal.h
@@ -0,0 +1,53 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_DA1469X_HAL_H_
+#define __MCU_DA1469X_HAL_H_
+
+#include <assert.h>
+#include "mcu/mcu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Helper functions to enable/disable interrupts. */
+#define __HAL_DISABLE_INTERRUPTS(x) \
+ do { \
+ x = __get_PRIMASK(); \
+ __disable_irq(); \
+ } while (0)
+
+#define __HAL_ENABLE_INTERRUPTS(x) \
+ do { \
+ if (!x) { \
+ __enable_irq(); \
+ } \
+ } while (0)
+
+#define __HAL_ASSERT_CRITICAL() \
+ do { \
+ assert(__get_PRIMASK() & 1); \
+ } while (0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_DA1469X_HAL_H_ */
diff --git a/hw/mcu/dialog/da1469x/include/mcu/mcu.h b/hw/mcu/dialog/da1469x/include/mcu/mcu.h
new file mode 100644
index 0000000..1e67367
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/include/mcu/mcu.h
@@ -0,0 +1,165 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_MCU_H_
+#define __MCU_MCU_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "DA1469xAB.h"
+
+#define sec_text_ram_core __attribute__((section(".text_ram"))) __attribute__((noinline))
+
+#define MCU_SYSVIEW_INTERRUPTS \
+ "I#1=Reset,I#2=MNI,I#3=HardFault,I#4=MemoryMgmt,I#5=BusFault,I#6=UsageFault," \
+ "I#7=SecureFault,I#11=SVCall,I#12=DebugMonitor,I#14=PendSV,I#15=SysTick," \
+ "I#16=SENSOR_NODE,I#17=DMA,I#18=CHARGER_STATE,I#19=CHARGER_ERROR," \
+ "I#20=CMAC2SYS,I#21=UART,I#22=UART2,I#23=UART3,I#24=I2C,I#25=I2C2,I#26=SPI," \
+ "I#27=SPI2,I#28=PCM,I#29=SRC_IN,I#30=SRC_OUT,I#31=USB,I#32=TIMER," \
+ "I#33=TIMER2,I#34=RTC,I#35=KEY_WKUP_GPIO,I#36=PDC,I#37=VBUS,I#38=MRM," \
+ "I#39=MOTOR_CONTROLLER,I#40=TRNG,I#41=DCDC,I#42=XTAL32M_RDY,I#43=ADC," \
+ "I#44=ADC2,I#45=CRYPTO,I#46=CAPTIMER1,I#47=RFDIAG,I#48=LCD_CONTROLLER," \
+ "I#49=PLL_LOCK,I#50=TIMER3,I#51=TIMER4,I#52=LRA,I#53=RTC_EVENT," \
+ "I#54=GPIO_P0,I#55=GPIO_P1"
+
+/**
+* \brief GPIO function
+*
+*/
+typedef enum {
+ MCU_GPIO_FUNC_GPIO = 0, /**< GPIO */
+ MCU_GPIO_FUNC_UART_RX = 1, /**< GPIO as UART RX */
+ MCU_GPIO_FUNC_UART_TX = 2, /**< GPIO as UART TX */
+ MCU_GPIO_FUNC_UART2_RX = 3, /**< GPIO as UART2 RX */
+ MCU_GPIO_FUNC_UART2_TX = 4, /**< GPIO as UART2 TX */
+ MCU_GPIO_FUNC_UART2_CTSN = 5, /**< GPIO as UART2 CTSN */
+ MCU_GPIO_FUNC_UART2_RTSN = 6, /**< GPIO as UART2 RTSN */
+ MCU_GPIO_FUNC_UART3_RX = 7, /**< GPIO as UART3 RX */
+ MCU_GPIO_FUNC_UART3_TX = 8, /**< GPIO as UART3 TX */
+ MCU_GPIO_FUNC_UART3_CTSN = 9, /**< GPIO as UART3 CTSN */
+ MCU_GPIO_FUNC_UART3_RTSN = 10, /**< GPIO as UART3 RTSN */
+ MCU_GPIO_FUNC_ISO_CLK = 11, /**< GPIO as ISO CLK */
+ MCU_GPIO_FUNC_ISO_DATA = 12, /**< GPIO as ISO DATA */
+ MCU_GPIO_FUNC_SPI_DI = 13, /**< GPIO as SPI DI */
+ MCU_GPIO_FUNC_SPI_DO = 14, /**< GPIO as SPI DO */
+ MCU_GPIO_FUNC_SPI_CLK = 15, /**< GPIO as SPI CLK */
+ MCU_GPIO_FUNC_SPI_EN = 16, /**< GPIO as SPI EN */
+ MCU_GPIO_FUNC_SPI2_DI = 17, /**< GPIO as SPI2 DI */
+ MCU_GPIO_FUNC_SPI2_DO = 18, /**< GPIO as SPI2 DO */
+ MCU_GPIO_FUNC_SPI2_CLK = 19, /**< GPIO as SPI2 CLK */
+ MCU_GPIO_FUNC_SPI2_EN = 20, /**< GPIO as SPI2 EN */
+ MCU_GPIO_FUNC_I2C_SCL = 21, /**< GPIO as I2C SCL */
+ MCU_GPIO_FUNC_I2C_SDA = 22, /**< GPIO as I2C SDA */
+ MCU_GPIO_FUNC_I2C2_SCL = 23, /**< GPIO as I2C2 SCL */
+ MCU_GPIO_FUNC_I2C2_SDA = 24, /**< GPIO as I2C2 SDA */
+ MCU_GPIO_FUNC_USB_SOF = 25, /**< GPIO as USB SOF */
+ MCU_GPIO_FUNC_ADC = 26, /**< GPIO as ADC (dedicated pin) */
+ MCU_GPIO_FUNC_USB = 27, /**< GPIO as USB */
+ MCU_GPIO_FUNC_PCM_DI = 28, /**< GPIO as PCM DI */
+ MCU_GPIO_FUNC_PCM_DO = 29, /**< GPIO as PCM DO */
+ MCU_GPIO_FUNC_PCM_FSC = 30, /**< GPIO as PCM FSC */
+ MCU_GPIO_FUNC_PCM_CLK = 31, /**< GPIO as PCM CLK */
+ MCU_GPIO_FUNC_PDM_DATA = 32, /**< GPIO as PDM DATA */
+ MCU_GPIO_FUNC_PDM_CLK = 33, /**< GPIO as PDM CLK */
+ MCU_GPIO_FUNC_COEX_EXT_ACT = 34, /**< GPIO as COEX EXT ACT0 */
+ MCU_GPIO_FUNC_COEX_SMART_ACT = 35, /**< GPIO as COEX SMART ACT */
+ MCU_GPIO_FUNC_COEX_SMART_PRI = 36, /**< GPIO as COEX SMART PRI */
+ MCU_GPIO_FUNC_PORT0_DCF = 37, /**< GPIO as PORT0 DCF */
+ MCU_GPIO_FUNC_PORT1_DCF = 38, /**< GPIO as PORT1 DCF */
+ MCU_GPIO_FUNC_PORT2_DCF = 39, /**< GPIO as PORT2 DCF */
+ MCU_GPIO_FUNC_PORT3_DCF = 40, /**< GPIO as PORT3 DCF */
+ MCU_GPIO_FUNC_PORT4_DCF = 41, /**< GPIO as PORT4 DCF */
+ MCU_GPIO_FUNC_CLOCK = 42, /**< GPIO as CLOCK */
+ MCU_GPIO_FUNC_PG = 43, /**< GPIO as PG */
+ MCU_GPIO_FUNC_LCD = 44, /**< GPIO as LCD */
+ MCU_GPIO_FUNC_LCD_SPI_DC = 45, /**< GPIO as LCD SPI DC */
+ MCU_GPIO_FUNC_LCD_SPI_DO = 46, /**< GPIO as LCD SPI DO */
+ MCU_GPIO_FUNC_LCD_SPI_CLK = 47, /**< GPIO as LCD SPI CLK */
+ MCU_GPIO_FUNC_LCD_SPI_EN = 48, /**< GPIO as LCD SPI EN */
+ MCU_GPIO_FUNC_TIM_PWM = 49, /**< GPIO as TIM PWM */
+ MCU_GPIO_FUNC_TIM2_PWM = 50, /**< GPIO as TIM2 PWM */
+ MCU_GPIO_FUNC_TIM_1SHOT = 51, /**< GPIO as TIM 1SHOT */
+ MCU_GPIO_FUNC_TIM2_1SHOT = 52, /**< GPIO as TIM2 1SHOT */
+ MCU_GPIO_FUNC_TIM3_PWM = 53, /**< GPIO as TIM3 PWM */
+ MCU_GPIO_FUNC_TIM4_PWM = 54, /**< GPIO as TIM4 PWM */
+ MCU_GPIO_FUNC_AGC_EXT = 55, /**< GPIO as AGC EXT */
+ MCU_GPIO_FUNC_CMAC_DIAG0 = 56, /**< GPIO as CMAC DIAG0 */
+ MCU_GPIO_FUNC_CMAC_DIAG1 = 57, /**< GPIO as CMAC DIAG1 */
+ MCU_GPIO_FUNC_CMAC_DIAG2 = 58, /**< GPIO as CMAC DIAG2 */
+ MCU_GPIO_FUNC_CMAC_DIAGX = 59, /**< GPIO as CMAC DIAGX */
+ MCU_GPIO_FUNC_LAST,
+} mcu_gpio_func;
+
+#define MCU_GPIO_MODE_INPUT 0x000 /**< GPIO as an input */
+#define MCU_GPIO_MODE_INPUT_PULLUP 0x100 /**< GPIO as an input with pull-up */
+#define MCU_GPIO_MODE_INPUT_PULLDOWN 0x200 /**< GPIO as an input with pull-down */
+#define MCU_GPIO_MODE_OUTPUT 0x300 /**< GPIO as an output */
+#define MCU_GPIO_MODE_OUTPUT_OPEN_DRAIN 0x700 /**< GPIO as an open-drain output */
+
+#define MCU_GPIO_PORT0_PIN_COUNT 32
+#define MCU_GPIO_PORT0(pin) ((0 * 32) + (pin))
+#define MCU_GPIO_PORT1(pin) ((1 * 32) + (pin))
+#define MCU_DMA_CHAN_MAX 8
+
+#define MCU_PIN_GPADC_SEL0 MCU_GPIO_PORT1(9)
+#define MCU_PIN_GPADC_SEL1 MCU_GPIO_PORT0(25)
+#define MCU_PIN_GPADC_SEL2 MCU_GPIO_PORT0(8)
+#define MCU_PIN_GPADC_SEL3 MCU_GPIO_PORT0(9)
+#define MCU_PIN_GPADC_SEL16 MCU_GPIO_PORT1(13)
+#define MCU_PIN_GPADC_SEL17 MCU_GPIO_PORT1(12)
+#define MCU_PIN_GPADC_SEL18 MCU_GPIO_PORT1(18)
+#define MCU_PIN_GPADC_SEL19 MCU_GPIO_PORT1(19)
+#define MCU_PIN_GPADC_DIFF0_P0 MCU_GPIO_PORT1(9)
+#define MCU_PIN_GPADC_DIFF0_P1 MCU_GPIO_PORT0(25)
+#define MCU_PIN_GPADC_DIFF1_P0 MCU_GPIO_PORT0(8)
+#define MCU_PIN_GPADC_DIFF1_P1 MCU_GPIO_PORT0(9)
+
+#define MCU_PIN_SDADC0 MCU_GPIO_PORT1(9)
+#define MCU_PIN_SDADC1 MCU_GPIO_PORT0(25)
+#define MCU_PIN_SDADC2 MCU_GPIO_PORT0(8)
+#define MCU_PIN_SDADC3 MCU_GPIO_PORT0(9)
+#define MCU_PIN_SDADC4 MCU_GPIO_PORT1(14)
+#define MCU_PIN_SDADC5 MCU_GPIO_PORT1(20)
+#define MCU_PIN_SDADC6 MCU_GPIO_PORT1(21)
+#define MCU_PIN_SDADC7 MCU_GPIO_PORT1(22)
+
+void mcu_gpio_set_pin_function(int pin, int mode, mcu_gpio_func func);
+void mcu_gpio_enter_sleep(void);
+void mcu_gpio_exit_sleep(void);
+
+#define MCU_MEM_QSPIF_M_END_REMAP_ADDRESS (0x800000)
+#define MCU_MEM_QSPIF_M_START_ADDRESS (0x16000000)
+#define MCU_MEM_QSPIF_M_END_ADDRESS (0x18000000)
+#define MCU_MEM_SYSRAM_START_ADDRESS (0x20000000)
+#define MCU_MEM_SYSRAM_END_ADDRESS (0x20080000)
+
+#define MCU_OTPM_BASE 0x30080000UL
+#define MCU_OTPM_SIZE 4096
+
+/* Largest group id seen on a DA14699 was 18 so far */
+#define MCU_TRIMV_GROUP_ID_MAX (18)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_MCU_H_ */
+
diff --git a/hw/mcu/dialog/da1469x/src/da1469x_clock.c b/hw/mcu/dialog/da1469x/src/da1469x_clock.c
new file mode 100644
index 0000000..6b4f0e6
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/src/da1469x_clock.c
@@ -0,0 +1,159 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include "syscfg/syscfg.h"
+#include "mcu/da1469x_hal.h"
+#include "mcu/da1469x_clock.h"
+
+static inline bool
+da1469x_clock_is_xtal32m_settled(void)
+{
+ return ((*(uint32_t *)0x5001001c & 0xff00) == 0) &&
+ ((*(uint32_t *)0x50010054 & 0x000f) != 0xb);
+}
+
+void
+da1469x_clock_sys_xtal32m_init(void)
+{
+ uint32_t reg;
+ int xtalrdy_cnt;
+
+ /* Number of lp_clk cycles (~30.5us) */
+ xtalrdy_cnt = MYNEWT_VAL(MCU_CLOCK_XTAL32M_SETTLE_TIME_US) * 10 / 305;
+
+ reg = CRG_XTAL->XTALRDY_CTRL_REG;
+ reg &= ~(CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CLK_SEL_Msk |
+ CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CNT_Msk);
+ reg |= xtalrdy_cnt;
+ CRG_XTAL->XTALRDY_CTRL_REG = reg;
+}
+
+void
+da1469x_clock_sys_xtal32m_enable(void)
+{
+ PDC->PDC_CTRL0_REG = (2 << PDC_PDC_CTRL0_REG_TRIG_SELECT_Pos) |
+ (15 << PDC_PDC_CTRL0_REG_TRIG_ID_Pos) |
+ (1 << PDC_PDC_CTRL0_REG_PDC_MASTER_Pos) |
+ (1 << PDC_PDC_CTRL0_REG_EN_XTAL_Pos);
+
+ PDC->PDC_SET_PENDING_REG = 0;
+ PDC->PDC_ACKNOWLEDGE_REG = 0;
+}
+
+void
+da1469x_clock_sys_xtal32m_switch(void)
+{
+ if (CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk) {
+ CRG_TOP->CLK_SWITCH2XTAL_REG = CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk;
+ } else {
+ CRG_TOP->CLK_CTRL_REG &= ~CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk;
+ }
+
+ while (!(CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk));
+}
+
+void
+da1469x_clock_sys_xtal32m_wait_to_settle(void)
+{
+ uint32_t primask;
+
+ __HAL_DISABLE_INTERRUPTS(primask);
+
+ NVIC_ClearPendingIRQ(XTAL32M_RDY_IRQn);
+
+ if (!da1469x_clock_is_xtal32m_settled()) {
+ NVIC_EnableIRQ(XTAL32M_RDY_IRQn);
+ while (!NVIC_GetPendingIRQ(XTAL32M_RDY_IRQn)) {
+ __WFI();
+ }
+ NVIC_DisableIRQ(XTAL32M_RDY_IRQn);
+ }
+
+ __HAL_ENABLE_INTERRUPTS(primask);
+}
+
+void
+da1469x_clock_sys_xtal32m_switch_safe(void)
+{
+ da1469x_clock_sys_xtal32m_wait_to_settle();
+
+ da1469x_clock_sys_xtal32m_switch();
+}
+
+void
+da1469x_clock_sys_rc32m_disable(void)
+{
+ CRG_TOP->CLK_RC32M_REG &= ~CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk;
+}
+
+void
+da1469x_clock_lp_xtal32k_enable(void)
+{
+ CRG_TOP->CLK_XTAL32K_REG |= CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Msk;
+}
+
+void
+da1469x_clock_lp_xtal32k_switch(void)
+{
+ CRG_TOP->CLK_CTRL_REG = (CRG_TOP->CLK_CTRL_REG &
+ ~CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) |
+ (2 << CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos);
+}
+
+void
+da1469x_clock_pll_disable(void)
+{
+ while (CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk) {
+ CRG_TOP->CLK_SWITCH2XTAL_REG = CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk;
+ }
+
+ CRG_XTAL->PLL_SYS_CTRL1_REG &= ~CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_EN_Msk;
+}
+
+void
+da1469x_clock_pll_wait_to_lock(void)
+{
+ uint32_t primask;
+
+ __HAL_DISABLE_INTERRUPTS(primask);
+
+ NVIC_ClearPendingIRQ(PLL_LOCK_IRQn);
+
+ if (!da1469x_clock_is_pll_locked()) {
+ NVIC_EnableIRQ(PLL_LOCK_IRQn);
+ while (!NVIC_GetPendingIRQ(PLL_LOCK_IRQn)) {
+ __WFI();
+ }
+ NVIC_DisableIRQ(PLL_LOCK_IRQn);
+ }
+
+ __HAL_ENABLE_INTERRUPTS(primask);
+}
+
+void
+da1469x_clock_sys_pll_switch(void)
+{
+ /* CLK_SEL_Msk == 3 means PLL */
+ CRG_TOP->CLK_CTRL_REG |= CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk;
+
+ while (!(CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk));
+}
diff --git a/hw/mcu/dialog/da1469x/src/hal_gpio.c b/hw/mcu/dialog/da1469x/src/hal_gpio.c
new file mode 100644
index 0000000..e105cf2
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/src/hal_gpio.c
@@ -0,0 +1,478 @@
+
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include "syscfg/syscfg.h"
+#include "mcu/da1469x_hal.h"
+#include <mcu/mcu.h>
+#include "hal/hal_gpio.h"
+
+/* GPIO interrupts */
+#define HAL_GPIO_MAX_IRQ MYNEWT_VAL(MCU_GPIO_MAX_IRQ)
+
+#define GPIO_REG(name) ((__IO uint32_t *)(GPIO_BASE + offsetof(GPIO_Type, name)))
+#define WAKEUP_REG(name) ((__IO uint32_t *)(WAKEUP_BASE + offsetof(WAKEUP_Type, name)))
+#define CRG_TOP_REG(name) ((__IO uint32_t *)(CRG_TOP_BASE + offsetof(CRG_TOP_Type, name)))
+
+#ifndef MCU_GPIO_PORT0_PIN_COUNT
+#define MCU_GPIO_PORT0_PIN_COUNT 32
+#endif
+
+#if (MCU_GPIO_PORT0_PIN_COUNT) == 32
+#define GPIO_PORT(pin) (((unsigned)(pin)) >> 5U)
+#define GPIO_PORT_PIN(pin) (((unsigned)(pin)) & 31U)
+#else
+#define GPIO_PORT(pin) (((unsigned)(pin)) < MCU_GPIO_PORT0_PIN_COUNT ? 0 : 1)
+#define GPIO_PORT_PIN(pin) ((unsigned)(pin) < MCU_GPIO_PORT0_PIN_COUNT ? \
+ (pin) : (pin) - MCU_GPIO_PORT0_PIN_COUNT)
+#endif
+
+#define GPIO_PIN_BIT(pin) (1 << GPIO_PORT_PIN(pin))
+
+#define GPIO_PIN_DATA_REG_ADDR(pin) (GPIO_REG(P0_DATA_REG) + GPIO_PORT(pin))
+#define GPIO_PIN_DATA_REG(pin) *GPIO_PIN_DATA_REG_ADDR(pin)
+#define GPIO_PIN_SET_DATA_REG_ADDR(pin) (GPIO_REG(P0_SET_DATA_REG) + GPIO_PORT(pin))
+#define GPIO_PIN_SET_DATA_REG(pin) *GPIO_PIN_SET_DATA_REG_ADDR(pin)
+#define GPIO_PIN_RESET_DATA_REG_ADDR(pin) (GPIO_REG(P0_RESET_DATA_REG) + GPIO_PORT(pin))
+#define GPIO_PIN_RESET_DATA_REG(pin) *GPIO_PIN_RESET_DATA_REG_ADDR(pin)
+#define GPIO_PIN_MODE_REG_ADDR(pin) (GPIO_REG(P0_00_MODE_REG) + (pin))
+#define GPIO_PIN_MODE_REG(pin) *GPIO_PIN_MODE_REG_ADDR(pin)
+#define GPIO_PIN_PADPWR_CTRL_REG_ADDR(pin) (GPIO_REG(P0_PADPWR_CTRL_REG) + GPIO_PORT(pin))
+#define GPIO_PIN_PADPWR_CTRL_REG(pin) *GPIO_PIN_PADPWR_CTRL_REG_ADDR(pin)
+#define GPIO_PIN_UNLATCH_ADDR(pin) (CRG_TOP_REG(P0_SET_PAD_LATCH_REG) + GPIO_PORT(pin) * 3)
+#define GPIO_PIN_LATCH_ADDR(pin) (CRG_TOP_REG(P0_RESET_PAD_LATCH_REG) + GPIO_PORT(pin) * 3)
+
+#define WKUP_CTRL_REG_ADDR (WAKEUP_REG(WKUP_CTRL_REG))
+#define WKUP_RESET_IRQ_REG_ADDR (WAKEUP_REG(WKUP_RESET_IRQ_REG))
+#define WKUP_SELECT_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_SELECT_P0_REG) + GPIO_PORT(pin))
+#define WKUP_SELECT_PX_REG(pin) *(WKUP_SELECT_PX_REG_ADDR(pin))
+#define WKUP_POL_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_POL_P0_REG) + GPIO_PORT(pin))
+#define WKUP_POL_PX_SET_FALLING(pin) do { *(WKUP_POL_PX_REG_ADDR(pin)) |= GPIO_PIN_BIT(pin); } while (0)
+#define WKUP_POL_PX_SET_RISING(pin) do { *(WKUP_POL_PX_REG_ADDR(pin)) &= ~GPIO_PIN_BIT(pin); } while (0)
+#define WKUP_STAT_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_STATUS_P0_REG) + GPIO_PORT(pin))
+#define WKUP_STAT(pin) ((*(WKUP_STAT_PX_REG_ADDR(pin)) >> GPIO_PORT_PIN(pin)) & 1)
+#define WKUP_CLEAR_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_CLEAR_P0_REG) + GPIO_PORT(pin))
+#define WKUP_CLEAR_PX(pin) do { (*(WKUP_CLEAR_PX_REG_ADDR(pin)) = GPIO_PIN_BIT(pin)); } while (0)
+#define WKUP_SEL_GPIO_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_SEL_GPIO_P0_REG) + GPIO_PORT(pin))
+#define WKUP_SEL_GPIO_PX_REG(pin) *(WKUP_SEL_GPIO_PX_REG_ADDR(pin))
+
+/* Storage for GPIO callbacks. */
+struct hal_gpio_irq {
+ int pin;
+ hal_gpio_irq_handler_t func;
+ void *arg;
+};
+
+static struct hal_gpio_irq hal_gpio_irqs[HAL_GPIO_MAX_IRQ];
+
+#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
+static uint32_t g_mcu_gpio_latch_state[2];
+static uint8_t g_mcu_gpio_retained_num;
+static struct da1469x_retreg g_mcu_gpio_retained[MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM)];
+#endif
+
+/*
+ * We assume that any latched pin has default configuration, i.e. was either
+ * not configured or was deinited. Any unlatched pin is considered to be used
+ * by someone.
+ *
+ * By default, all pins are assumed to have default configuration and are
+ * latched. This allows PD_COM to be disabled (if no other peripheral needs
+ * it) since we do not need GPIO mux to be active.
+ *
+ * Configuration of any pin shall be done as follows, with interrupts disabled:
+ * 1. call mcu_gpio_unlatch_prepare() to enable PD_COM if needed
+ * 2. configure pin
+ * 3. call mcu_gpio_unlatch() to actually unlatch pin
+ *
+ * Once pin is restored to default configuration it shall be latched again by
+ * calling mcu_gpio_latch().
+ */
+
+#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
+static void
+mcu_gpio_retained_add_port(uint32_t latch_val, volatile uint32_t *base_reg)
+{
+ struct da1469x_retreg *retreg;
+ int pin;
+
+ retreg = &g_mcu_gpio_retained[g_mcu_gpio_retained_num];
+
+ while (latch_val) {
+ assert(g_mcu_gpio_retained_num < MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM));
+
+ pin = __builtin_ctz(latch_val);
+ latch_val &= ~(1 << pin);
+
+ da1469x_retreg_assign(retreg, &base_reg[pin]);
+
+ g_mcu_gpio_retained_num++;
+ retreg++;
+ }
+}
+#endif
+
+static void
+mcu_gpio_retained_refresh(void)
+{
+#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
+ g_mcu_gpio_retained_num = 0;
+
+ mcu_gpio_retained_add_port(CRG_TOP->P0_PAD_LATCH_REG, &GPIO->P0_00_MODE_REG);
+ mcu_gpio_retained_add_port(CRG_TOP->P1_PAD_LATCH_REG, &GPIO->P1_00_MODE_REG);
+#endif
+}
+
+static inline void
+mcu_gpio_unlatch_prepare(int pin)
+{
+ __HAL_ASSERT_CRITICAL();
+ (void)pin;
+
+ /* Acquire PD_COM if first pin will be unlatched */
+// if ((CRG_TOP->P0_PAD_LATCH_REG | CRG_TOP->P1_PAD_LATCH_REG) == 0) {
+// da1469x_pd_acquire(MCU_PD_DOMAIN_COM);
+// }
+}
+
+static inline void
+mcu_gpio_unlatch(int pin)
+{
+ __HAL_ASSERT_CRITICAL();
+
+ *GPIO_PIN_UNLATCH_ADDR(pin) = GPIO_PIN_BIT(pin);
+ mcu_gpio_retained_refresh();
+}
+
+static inline void
+mcu_gpio_latch(int pin)
+{
+ (void)pin;
+// uint32_t primask;
+// uint32_t latch_pre;
+// uint32_t latch_post;
+//
+// __HAL_DISABLE_INTERRUPTS(primask);
+//
+// latch_pre = CRG_TOP->P0_PAD_LATCH_REG | CRG_TOP->P1_PAD_LATCH_REG;
+//
+// *GPIO_PIN_LATCH_ADDR(pin) = GPIO_PIN_BIT(pin);
+// mcu_gpio_retained_refresh();
+//
+// latch_post = CRG_TOP->P0_PAD_LATCH_REG | CRG_TOP->P1_PAD_LATCH_REG;
+//
+// /* Release PD_COM if last pin was latched */
+// if (latch_pre && !latch_post) {
+// da1469x_pd_release(MCU_PD_DOMAIN_COM);
+// }
+//
+// __HAL_ENABLE_INTERRUPTS(primask);
+}
+
+int
+hal_gpio_init_in(int pin, hal_gpio_pull_t pull)
+{
+ volatile uint32_t *px_xx_mod_reg = GPIO_PIN_MODE_REG_ADDR(pin);
+ uint32_t regval;
+ uint32_t primask;
+
+ switch (pull) {
+ case HAL_GPIO_PULL_UP:
+ regval = MCU_GPIO_FUNC_GPIO | MCU_GPIO_MODE_INPUT_PULLUP;
+ break;
+ case HAL_GPIO_PULL_DOWN:
+ regval = MCU_GPIO_FUNC_GPIO | MCU_GPIO_MODE_INPUT_PULLDOWN;
+ break;
+ case HAL_GPIO_PULL_NONE:
+ regval = MCU_GPIO_FUNC_GPIO | MCU_GPIO_MODE_INPUT;
+ break;
+ default:
+ return -1;
+ }
+
+ __HAL_DISABLE_INTERRUPTS(primask);
+
+ mcu_gpio_unlatch_prepare(pin);
+
+ *px_xx_mod_reg = regval;
+
+ mcu_gpio_unlatch(pin);
+
+ __HAL_ENABLE_INTERRUPTS(primask);
+
+ return 0;
+}
+
+int
+hal_gpio_init_out(int pin, int val)
+{
+ uint32_t primask;
+
+ __HAL_DISABLE_INTERRUPTS(primask);
+
+ mcu_gpio_unlatch_prepare(pin);
+
+ GPIO_PIN_MODE_REG(pin) = MCU_GPIO_MODE_OUTPUT;
+
+ if (val) {
+ GPIO_PIN_SET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
+ } else {
+ GPIO_PIN_RESET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
+ }
+
+ mcu_gpio_unlatch(pin);
+
+ __HAL_ENABLE_INTERRUPTS(primask);
+
+ return 0;
+}
+
+int
+hal_gpio_deinit(int pin)
+{
+ /* Reset mode to default value and latch pin */
+ GPIO_PIN_MODE_REG(pin) = 0x200;
+ GPIO_PIN_RESET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
+
+ mcu_gpio_latch(pin);
+
+ return 0;
+}
+
+void
+hal_gpio_write(int pin, int val)
+{
+ if (val) {
+ GPIO_PIN_SET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
+ } else {
+ GPIO_PIN_RESET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
+ }
+}
+
+int
+hal_gpio_read(int pin)
+{
+ return (GPIO_PIN_DATA_REG(pin) >> GPIO_PORT_PIN(pin)) & 1;
+}
+
+int
+hal_gpio_toggle(int pin)
+{
+ int new_value = hal_gpio_read(pin) == 0;
+
+ hal_gpio_write(pin, new_value);
+
+ return new_value;
+}
+
+static void
+hal_gpio_irq_handler(void)
+{
+ struct hal_gpio_irq *irq;
+ uint32_t stat;
+ int i;
+
+ *WKUP_RESET_IRQ_REG_ADDR = 1;
+ NVIC_ClearPendingIRQ(KEY_WKUP_GPIO_IRQn);
+
+ for (i = 0; i < HAL_GPIO_MAX_IRQ; i++) {
+ irq = &hal_gpio_irqs[i];
+
+ /* Read latched status value from relevant GPIO port */
+ stat = WKUP_STAT(irq->pin);
+
+ if (irq->func && stat) {
+ irq->func(irq->arg);
+ }
+
+ WKUP_CLEAR_PX(irq->pin);
+ }
+}
+
+static void
+hal_gpio_irq_setup(void)
+{
+ static uint8_t irq_setup;
+ int sr;
+
+ if (!irq_setup) {
+ __HAL_DISABLE_INTERRUPTS(sr);
+
+ irq_setup = 1;
+
+ NVIC_ClearPendingIRQ(GPIO_P0_IRQn);
+ NVIC_ClearPendingIRQ(GPIO_P1_IRQn);
+ NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)hal_gpio_irq_handler);
+ NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)hal_gpio_irq_handler);
+ WAKEUP->WKUP_CTRL_REG = 0;
+ WAKEUP->WKUP_CLEAR_P0_REG = 0xFFFFFFFF;
+ WAKEUP->WKUP_CLEAR_P1_REG = 0x007FFFFF;
+ WAKEUP->WKUP_SELECT_P0_REG = 0;
+ WAKEUP->WKUP_SELECT_P1_REG = 0;
+ WAKEUP->WKUP_SEL_GPIO_P0_REG = 0;
+ WAKEUP->WKUP_SEL_GPIO_P1_REG = 0;
+ WAKEUP->WKUP_RESET_IRQ_REG = 0;
+
+ CRG_TOP->CLK_TMR_REG |= CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk;
+
+ __HAL_ENABLE_INTERRUPTS(sr);
+ NVIC_EnableIRQ(GPIO_P0_IRQn);
+ NVIC_EnableIRQ(GPIO_P1_IRQn);
+ }
+}
+
+static int
+hal_gpio_find_empty_slot(void)
+{
+ int i;
+
+ for (i = 0; i < HAL_GPIO_MAX_IRQ; i++) {
+ if (hal_gpio_irqs[i].func == NULL) {
+ return i;
+ }
+ }
+
+ return -1;
+}
+
+int
+hal_gpio_irq_init(int pin, hal_gpio_irq_handler_t handler, void *arg,
+ hal_gpio_irq_trig_t trig, hal_gpio_pull_t pull)
+{
+ int i;
+
+ hal_gpio_irq_setup();
+
+ i = hal_gpio_find_empty_slot();
+ /* If assert failed increase syscfg value MCU_GPIO_MAX_IRQ */
+ assert(i >= 0);
+ if (i < 0) {
+ return -1;
+ }
+
+ hal_gpio_init_in(pin, pull);
+
+ switch (trig) {
+ case HAL_GPIO_TRIG_RISING:
+ WKUP_POL_PX_SET_RISING(pin);
+ break;
+ case HAL_GPIO_TRIG_FALLING:
+ WKUP_POL_PX_SET_FALLING(pin);
+ break;
+ case HAL_GPIO_TRIG_BOTH:
+ /* Not supported */
+ default:
+ return -1;
+ }
+
+ hal_gpio_irqs[i].pin = pin;
+ hal_gpio_irqs[i].func = handler;
+ hal_gpio_irqs[i].arg = arg;
+
+ return 0;
+}
+
+void
+hal_gpio_irq_release(int pin)
+{
+ int i;
+
+ hal_gpio_irq_disable(pin);
+
+ for (i = 0; i < HAL_GPIO_MAX_IRQ; i++) {
+ if (hal_gpio_irqs[i].pin == pin && hal_gpio_irqs[i].func) {
+ hal_gpio_irqs[i].pin = -1;
+ hal_gpio_irqs[i].arg = NULL;
+ hal_gpio_irqs[i].func = NULL;
+ }
+ }
+}
+
+void
+hal_gpio_irq_enable(int pin)
+{
+ WKUP_SEL_GPIO_PX_REG(pin) |= GPIO_PIN_BIT(pin);
+}
+
+void
+hal_gpio_irq_disable(int pin)
+{
+ WKUP_SEL_GPIO_PX_REG(pin) &= ~GPIO_PIN_BIT(pin);
+ WKUP_CLEAR_PX(pin);
+}
+
+void
+mcu_gpio_set_pin_function(int pin, int mode, mcu_gpio_func func)
+{
+ uint32_t primask;
+
+ __HAL_DISABLE_INTERRUPTS(primask);
+
+ mcu_gpio_unlatch_prepare(pin);
+
+ GPIO_PIN_MODE_REG(pin) = (func & GPIO_P0_00_MODE_REG_PID_Msk) |
+ (mode & (GPIO_P0_00_MODE_REG_PUPD_Msk | GPIO_P0_00_MODE_REG_PPOD_Msk));
+
+ mcu_gpio_unlatch(pin);
+
+ __HAL_ENABLE_INTERRUPTS(primask);
+}
+
+void
+mcu_gpio_enter_sleep(void)
+{
+#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
+ if (g_mcu_gpio_retained_num == 0) {
+ return;
+ }
+
+ g_mcu_gpio_latch_state[0] = CRG_TOP->P0_PAD_LATCH_REG;
+ g_mcu_gpio_latch_state[1] = CRG_TOP->P1_PAD_LATCH_REG;
+
+ da1469x_retreg_update(g_mcu_gpio_retained, g_mcu_gpio_retained_num);
+
+ CRG_TOP->P0_RESET_PAD_LATCH_REG = CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk;
+ CRG_TOP->P1_RESET_PAD_LATCH_REG = CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk;
+
+ da1469x_pd_release(MCU_PD_DOMAIN_COM);
+#endif
+}
+
+void
+mcu_gpio_exit_sleep(void)
+{
+#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
+ if (g_mcu_gpio_retained_num == 0) {
+ return;
+ }
+
+ da1469x_pd_acquire(MCU_PD_DOMAIN_COM);
+
+ da1469x_retreg_restore(g_mcu_gpio_retained, g_mcu_gpio_retained_num);
+
+ /* Set pins states to their latched values */
+ GPIO->P0_DATA_REG = GPIO->P0_DATA_REG;
+ GPIO->P1_DATA_REG = GPIO->P1_DATA_REG;
+
+ CRG_TOP->P0_PAD_LATCH_REG = g_mcu_gpio_latch_state[0];
+ CRG_TOP->P1_PAD_LATCH_REG = g_mcu_gpio_latch_state[1];
+#endif
+}
diff --git a/hw/mcu/dialog/da1469x/src/hal_system.c b/hw/mcu/dialog/da1469x/src/hal_system.c
new file mode 100644
index 0000000..2841979
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/src/hal_system.c
@@ -0,0 +1,136 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include "syscfg/syscfg.h"
+#include "mcu/da1469x_clock.h"
+#include "mcu/da1469x_lpclk.h"
+#include "mcu/da1469x_pd.h"
+#include "mcu/da1469x_pdc.h"
+#include "mcu/da1469x_prail.h"
+#include "hal/hal_system.h"
+#include "os/os_cputime.h"
+
+#if !MYNEWT_VAL(BOOT_LOADER)
+static enum hal_reset_reason g_hal_reset_reason;
+#endif
+
+void
+hal_system_init(void)
+{
+#if MYNEWT_VAL(MCU_DCDC_ENABLE)
+ da1469x_prail_dcdc_enable();
+#endif
+
+ /*
+ * RESET_STAT_REG has to be cleared to allow HW set bits during next reset
+ * so we should read it now and keep result for application to check at any
+ * time. This does not happen for bootloader since reading reset reason in
+ * bootloader would prevent application from reading it.
+ */
+
+#if !MYNEWT_VAL(BOOT_LOADER)
+ uint32_t reg;
+
+ reg = CRG_TOP->RESET_STAT_REG;
+ CRG_TOP->RESET_STAT_REG = 0;
+
+ if (reg & CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk) {
+ g_hal_reset_reason = HAL_RESET_POR;
+ } else if (reg & CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk) {
+ g_hal_reset_reason = HAL_RESET_WATCHDOG;
+ } else if (reg & CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk) {
+ g_hal_reset_reason = HAL_RESET_SOFT;
+ } else if (reg & CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk) {
+ g_hal_reset_reason = HAL_RESET_PIN;
+ } else {
+ g_hal_reset_reason = 0;
+ }
+#endif
+}
+
+void
+hal_system_reset(void)
+{
+
+#if MYNEWT_VAL(HAL_SYSTEM_RESET_CB)
+ hal_system_reset_cb();
+#endif
+
+ while (1) {
+ HAL_DEBUG_BREAK();
+ CRG_TOP->SYS_CTRL_REG = 0x20;
+ NVIC_SystemReset();
+ }
+}
+
+int
+hal_debugger_connected(void)
+{
+ return CRG_TOP->SYS_STAT_REG & CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk;
+}
+
+void
+hal_system_clock_start(void)
+{
+ /* Reset clock dividers to 0 */
+ CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk | CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk);
+
+ /* PD_TIM is already started in SystemInit */
+
+ da1469x_clock_sys_xtal32m_init();
+ da1469x_clock_sys_xtal32m_enable();
+#if MYNEWT_VAL(MCU_PLL_ENABLE)
+ da1469x_clock_sys_pll_enable();
+#endif
+#if MYNEWT_VAL_CHOICE(MCU_SYSCLK_SOURCE, PLL96)
+ da1469x_clock_pll_wait_to_lock();
+ da1469x_clock_sys_pll_switch();
+#endif
+#if MYNEWT_VAL_CHOICE(MCU_SYSCLK_SOURCE, XTAL32M)
+ /* Switch to XTAL32M and disable RC32M */
+ da1469x_clock_sys_xtal32m_switch_safe();
+#endif
+ da1469x_clock_sys_rc32m_disable();
+
+#if MYNEWT_VAL_CHOICE(MCU_LPCLK_SOURCE, RCX)
+ /* Switch to RCX and calibrate it */
+ da1469x_clock_lp_rcx_enable();
+ da1469x_clock_lp_rcx_switch();
+ da1469x_clock_lp_rcx_calibrate();
+ da1469x_lpclk_enabled();
+#else
+ /*
+ * We cannot switch lp_clk to XTAL32K here since it needs some time to
+ * settle, so we just disable RCX (we don't need it) and then we'll handle
+ * switch to XTAL32K from sysinit since we need os_cputime for this.
+ */
+ da1469x_clock_lp_rcx_disable();
+#endif
+}
+
+enum hal_reset_reason
+hal_reset_cause(void)
+{
+#if MYNEWT_VAL(BOOT_LOADER)
+ return 0;
+#else
+ return g_hal_reset_reason;
+#endif
+}
diff --git a/hw/mcu/dialog/da1469x/src/hal_system_start.c b/hw/mcu/dialog/da1469x/src/hal_system_start.c
new file mode 100644
index 0000000..bd24650
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/src/hal_system_start.c
@@ -0,0 +1,177 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdint.h>
+#include "mcu/mcu.h"
+#include "mcu/da1469x_hal.h"
+#include <flash_map/flash_map.h>
+#include <mcu/da1469x_clock.h>
+#if MCUBOOT_MYNEWT
+#include "bootutil/bootutil.h"
+#include "bootutil/image.h"
+#include "bootutil/bootutil_log.h"
+#include "mcu/da1469x_dma.h"
+#include "mcu/da1469x_otp.h"
+#endif
+
+#if MYNEWT_VAL(BOOT_CUSTOM_START) && MCUBOOT_MYNEWT
+sec_text_ram_core
+#endif
+void __attribute__((naked))
+hal_system_start(void *img_start)
+{
+ uint32_t img_data_addr;
+ uint32_t *img_data;
+
+ img_data_addr = MCU_MEM_QSPIF_M_START_ADDRESS + (uint32_t)img_start;
+
+ assert(img_data_addr < MCU_MEM_QSPIF_M_END_ADDRESS);
+
+ img_data = (uint32_t *)img_data_addr;
+
+ asm volatile (".syntax unified \n"
+ /* 1st word is stack pointer */
+ " msr msp, %0 \n"
+ /* 2nd word is a reset handler (image entry) */
+ " bx %1 \n"
+ : /* no output */
+ : "r" (img_data[0]), "r" (img_data[1]));
+}
+
+void
+hal_system_restart(void *img_start)
+{
+ uint32_t primask __attribute__((unused));
+ int i;
+
+ /*
+ * Disable interrupts, and leave them disabled.
+ * They get re-enabled when system starts coming back again.
+ */
+ __HAL_DISABLE_INTERRUPTS(primask);
+
+ for (i = 0; i < sizeof(NVIC->ICER) / sizeof(NVIC->ICER[0]); i++) {
+ NVIC->ICER[i] = 0xffffffff;
+ }
+
+ hal_system_start(img_start);
+}
+
+#if MYNEWT_VAL(BOOT_CUSTOM_START) && MCUBOOT_MYNEWT
+#define IMAGE_TLV_AES_NONCE 0x50
+#define IMAGE_TLV_SECRET_ID 0x60
+
+sec_text_ram_core void
+boot_custom_start(uintptr_t flash_base, struct boot_rsp *rsp)
+{
+ int rc;
+ struct image_tlv_iter it;
+ const struct flash_area *fap;
+ uint32_t off;
+ uint16_t len;
+ uint16_t type;
+ uint8_t buf[8];
+ uint8_t key;
+ uint32_t nonce[2];
+ bool has_aes_nonce;
+ bool has_secret_id;
+ DMA_Type *dma_regs = DMA;
+ uint32_t jump_offset = rsp->br_image_off + rsp->br_hdr->ih_hdr_size;
+
+ BOOT_LOG_INF("Custom initialization");
+
+ /* skip to booting if we are running nonsecure mode */
+ if (!(CRG_TOP->SECURE_BOOT_REG & 0x1)) {
+ hal_system_start((void *)(flash_base + jump_offset));
+ }
+
+ rc = flash_area_open(flash_area_id_from_image_slot(0), &fap);
+ assert(rc == 0);
+
+ rc = bootutil_tlv_iter_begin(&it, rsp->br_hdr, fap, IMAGE_TLV_ANY, true);
+ assert(rc == 0);
+
+ has_aes_nonce = has_secret_id = false;
+ while (true) {
+ rc = bootutil_tlv_iter_next(&it, &off, &len, &type);
+ assert(rc >= 0);
+
+ if (rc > 0) {
+ break;
+ }
+
+ if (type == IMAGE_TLV_AES_NONCE) {
+ assert(len == 8);
+
+ rc = flash_area_read(fap, off, buf, len);
+ assert(rc == 0);
+
+ nonce[0] = __builtin_bswap32(*(uint32_t *)buf);
+ nonce[1] = __builtin_bswap32(*(uint32_t *)(buf + 4));
+ has_aes_nonce = true;
+ } else if (type == IMAGE_TLV_SECRET_ID) {
+ assert(len == 4);
+
+ rc = flash_area_read(fap, off, buf, len);
+ assert(rc == 0);
+
+ key = buf[0];
+ has_secret_id = true;
+ }
+ }
+
+ assert(has_aes_nonce && has_secret_id && key <= 7);
+
+ /* enable OTP clock and set in read mode */
+ da1469x_clock_amba_enable(CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk);
+ da1469x_otp_set_mode(OTPC_MODE_READ);
+
+ /* disable decrypt on the fly and program start and end addresses */
+ QSPIC->QSPIC_CTR_CTRL_REG = 0;
+ QSPIC->QSPIC_CTR_SADDR_REG = jump_offset;
+ QSPIC->QSPIC_CTR_EADDR_REG = QSPIC->QSPIC_CTR_SADDR_REG +
+ rsp->br_hdr->ih_img_size - 1;
+
+ /* securely DMA hardware key from secret storage to QSPI decrypt engine */
+ dma_regs->DMA_REQ_MUX_REG |= 0xf000;
+ dma_regs->DMA7_LEN_REG = 8;
+ dma_regs->DMA7_A_START_REG = MCU_OTPM_BASE + OTP_SEGMENT_QSPI_FW_KEYS +
+ (32 * key);
+ dma_regs->DMA7_B_START_REG = (uint32_t)&QSPIC->QSPIC_CTR_KEY_0_3_REG;
+ dma_regs->DMA7_CTRL_REG = DMA_DMA7_CTRL_REG_AINC_Msk |
+ DMA_DMA7_CTRL_REG_BINC_Msk |
+ (MCU_DMA_BUS_WIDTH_4B << DMA_DMA7_CTRL_REG_BW_Pos) |
+ DMA_DMA7_CTRL_REG_DMA_ON_Msk;
+ while (dma_regs->DMA7_IDX_REG != 8);
+
+ /* program NONCE */
+ QSPIC->QSPIC_CTR_NONCE_0_3_REG = nonce[0];
+ QSPIC->QSPIC_CTR_NONCE_4_7_REG = nonce[1];
+
+ /* turn back on decrypt on the fly */
+ QSPIC->QSPIC_CTR_CTRL_REG = 1;
+
+ /* set OTP to standby and turn off clock */
+ da1469x_otp_set_mode(OTPC_MODE_STBY);
+ da1469x_clock_amba_disable(CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk);
+
+ hal_system_start((void *)(flash_base + jump_offset));
+}
+#endif
diff --git a/hw/mcu/dialog/da1469x/src/system_da1469x.c b/hw/mcu/dialog/da1469x/src/system_da1469x.c
new file mode 100644
index 0000000..538bac7
--- /dev/null
+++ b/hw/mcu/dialog/da1469x/src/system_da1469x.c
@@ -0,0 +1,61 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "mcu/mcu.h"
+#include <mcu/da1469x_clock.h>
+
+extern uint8_t __StackLimit;
+
+uint32_t SystemCoreClock = 32000000;
+
+void
+SystemInit(void)
+{
+ /* Enable FPU when using hard-float */
+#if (__FPU_USED == 1)
+ SCB->CPACR |= (3UL << 20) | (3UL << 22);
+ __DSB();
+ __ISB();
+#endif
+
+ /* Freez watchdog */
+ GPREG->SET_FREEZE_REG |= GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk;
+ /* Initialize power domains (disable radio only) */
+ CRG_TOP->PMU_CTRL_REG = CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk;
+
+ CRG_TOP->P0_SET_PAD_LATCH_REG = CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk;
+ CRG_TOP->P1_SET_PAD_LATCH_REG = CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk;
+
+ /* Reset clock dividers to 0 */
+ CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk | CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk);
+
+ /* PD_TIM is already started in SystemInit */
+
+ da1469x_clock_sys_xtal32m_init();
+ da1469x_clock_sys_xtal32m_enable();
+ da1469x_clock_sys_pll_enable();
+ da1469x_clock_pll_wait_to_lock();
+ /* Switch to XTAL32M and disable RC32M */
+ da1469x_clock_sys_xtal32m_switch_safe();
+ da1469x_clock_sys_rc32m_disable();
+}
+
+void _init(void)
+{
+}