more new symbols
diff --git a/bbb_cape/schematic/packages/beaglebone.fp b/bbb_cape/schematic/packages/beaglebone.fp
new file mode 100644
index 0000000..9616f9d
--- /dev/null
+++ b/bbb_cape/schematic/packages/beaglebone.fp
@@ -0,0 +1,110 @@
+Element[0x0 "footprint.built" "" "" 0 0 -112500 -118000 0 100 0x0]
+(
+ ElementArc[155000 -60000 50000 50000 180 90 1000]
+ ElementArc[155000 55000 50000 50000 90 90 1000]
+ ElementArc[-110000 80000 25000 25000 0 90 1000]
+ ElementLine[-112500 -110000 155000 -110000 1000]
+ ElementLine[205000 55000 205000 -60000 1000]
+ ElementLine[-110000 105000 155000 105000 1000]
+ ElementLine[-135000 80000 -135000 22500 1000]
+ ElementLine[-135000 22500 -55000 22500 1000]
+ ElementLine[-55000 22500 -55000 -47500 1000]
+ ElementLine[-55000 -47500 -112500 -47500 1000]
+ ElementLine[-112500 -47500 -112500 -110000 1000]
+ Pin[-77500 92500 14500 1800 16500 12500 "bogus_442" "442" 0x01]
+ Pin[-77500 -97500 14500 1800 16500 12500 "bogus_542" "542" 0x01]
+ Pin[182500 80000 14500 1800 16500 12500 "bogus_642" "642" 0x01]
+ Pin[182500 -85000 14500 1800 16500 12500 "bogus_742" "742" 0x01]
+ Pin[-57500 87500 6600 2000 8600 4600 "" "48" 0x01]
+ Pin[-57500 97500 6600 2000 8600 4600 "" "47" 0x0101]
+ Pin[-47500 87500 6600 2000 8600 4600 "" "50" 0x01]
+ Pin[-47500 97500 6600 2000 8600 4600 "" "49" 0x01]
+ Pin[-37500 87500 6600 2000 8600 4600 "" "52" 0x01]
+ Pin[-37500 97500 6600 2000 8600 4600 "" "51" 0x01]
+ Pin[-27500 87500 6600 2000 8600 4600 "" "54" 0x01]
+ Pin[-27500 97500 6600 2000 8600 4600 "" "53" 0x01]
+ Pin[-17500 87500 6600 2000 8600 4600 "" "56" 0x01]
+ Pin[-17500 97500 6600 2000 8600 4600 "" "55" 0x01]
+ Pin[-7500 87500 6600 2000 8600 4600 "" "58" 0x01]
+ Pin[-7500 97500 6600 2000 8600 4600 "" "57" 0x01]
+ Pin[2500 87500 6600 2000 8600 4600 "" "60" 0x01]
+ Pin[2500 97500 6600 2000 8600 4600 "" "59" 0x01]
+ Pin[12500 87500 6600 2000 8600 4600 "" "62" 0x01]
+ Pin[12500 97500 6600 2000 8600 4600 "" "61" 0x01]
+ Pin[22500 87500 6600 2000 8600 4600 "" "64" 0x01]
+ Pin[22500 97500 6600 2000 8600 4600 "" "63" 0x01]
+ Pin[32500 87500 6600 2000 8600 4600 "" "66" 0x01]
+ Pin[32500 97500 6600 2000 8600 4600 "" "65" 0x01]
+ Pin[42500 87500 6600 2000 8600 4600 "" "68" 0x01]
+ Pin[42500 97500 6600 2000 8600 4600 "" "67" 0x01]
+ Pin[52500 87500 6600 2000 8600 4600 "" "70" 0x01]
+ Pin[52500 97500 6600 2000 8600 4600 "" "69" 0x01]
+ Pin[62500 87500 6600 2000 8600 4600 "" "72" 0x01]
+ Pin[62500 97500 6600 2000 8600 4600 "" "71" 0x01]
+ Pin[72500 87500 6600 2000 8600 4600 "" "74" 0x01]
+ Pin[72500 97500 6600 2000 8600 4600 "" "73" 0x01]
+ Pin[82500 87500 6600 2000 8600 4600 "" "76" 0x01]
+ Pin[82500 97500 6600 2000 8600 4600 "" "75" 0x01]
+ Pin[92500 87500 6600 2000 8600 4600 "" "78" 0x01]
+ Pin[92500 97500 6600 2000 8600 4600 "" "77" 0x01]
+ Pin[102500 87500 6600 2000 8600 4600 "" "80" 0x01]
+ Pin[102500 97500 6600 2000 8600 4600 "" "79" 0x01]
+ Pin[112500 87500 6600 2000 8600 4600 "" "82" 0x01]
+ Pin[112500 97500 6600 2000 8600 4600 "" "81" 0x01]
+ Pin[122500 87500 6600 2000 8600 4600 "" "84" 0x01]
+ Pin[122500 97500 6600 2000 8600 4600 "" "83" 0x01]
+ Pin[132500 87500 6600 2000 8600 4600 "" "86" 0x01]
+ Pin[132500 97500 6600 2000 8600 4600 "" "85" 0x01]
+ Pin[142500 87500 6600 2000 8600 4600 "" "88" 0x01]
+ Pin[142500 97500 6600 2000 8600 4600 "" "87" 0x01]
+ Pin[152500 87500 6600 2000 8600 4600 "" "90" 0x01]
+ Pin[152500 97500 6600 2000 8600 4600 "" "89" 0x01]
+ Pin[162500 87500 6600 2000 8600 4600 "" "92" 0x01]
+ Pin[162500 97500 6600 2000 8600 4600 "" "91" 0x01]
+ Pin[-57500 -102500 6600 2000 8600 4600 "" "2" 0x01]
+ Pin[-57500 -92500 6600 2000 8600 4600 "" "1" 0x0101]
+ Pin[-47500 -102500 6600 2000 8600 4600 "" "4" 0x01]
+ Pin[-47500 -92500 6600 2000 8600 4600 "" "3" 0x01]
+ Pin[-37500 -102500 6600 2000 8600 4600 "" "6" 0x01]
+ Pin[-37500 -92500 6600 2000 8600 4600 "" "5" 0x01]
+ Pin[-27500 -102500 6600 2000 8600 4600 "" "8" 0x01]
+ Pin[-27500 -92500 6600 2000 8600 4600 "" "7" 0x01]
+ Pin[-17500 -102500 6600 2000 8600 4600 "" "10" 0x01]
+ Pin[-17500 -92500 6600 2000 8600 4600 "" "9" 0x01]
+ Pin[-7500 -102500 6600 2000 8600 4600 "" "12" 0x01]
+ Pin[-7500 -92500 6600 2000 8600 4600 "" "11" 0x01]
+ Pin[2500 -102500 6600 2000 8600 4600 "" "14" 0x01]
+ Pin[2500 -92500 6600 2000 8600 4600 "" "13" 0x01]
+ Pin[12500 -102500 6600 2000 8600 4600 "" "16" 0x01]
+ Pin[12500 -92500 6600 2000 8600 4600 "" "15" 0x01]
+ Pin[22500 -102500 6600 2000 8600 4600 "" "18" 0x01]
+ Pin[22500 -92500 6600 2000 8600 4600 "" "17" 0x01]
+ Pin[32500 -102500 6600 2000 8600 4600 "" "20" 0x01]
+ Pin[32500 -92500 6600 2000 8600 4600 "" "19" 0x01]
+ Pin[42500 -102500 6600 2000 8600 4600 "" "22" 0x01]
+ Pin[42500 -92500 6600 2000 8600 4600 "" "21" 0x01]
+ Pin[52500 -102500 6600 2000 8600 4600 "" "24" 0x01]
+ Pin[52500 -92500 6600 2000 8600 4600 "" "23" 0x01]
+ Pin[62500 -102500 6600 2000 8600 4600 "" "26" 0x01]
+ Pin[62500 -92500 6600 2000 8600 4600 "" "25" 0x01]
+ Pin[72500 -102500 6600 2000 8600 4600 "" "28" 0x01]
+ Pin[72500 -92500 6600 2000 8600 4600 "" "27" 0x01]
+ Pin[82500 -102500 6600 2000 8600 4600 "" "30" 0x01]
+ Pin[82500 -92500 6600 2000 8600 4600 "" "29" 0x01]
+ Pin[92500 -102500 6600 2000 8600 4600 "" "32" 0x01]
+ Pin[92500 -92500 6600 2000 8600 4600 "" "31" 0x01]
+ Pin[102500 -102500 6600 2000 8600 4600 "" "34" 0x01]
+ Pin[102500 -92500 6600 2000 8600 4600 "" "33" 0x01]
+ Pin[112500 -102500 6600 2000 8600 4600 "" "36" 0x01]
+ Pin[112500 -92500 6600 2000 8600 4600 "" "35" 0x01]
+ Pin[122500 -102500 6600 2000 8600 4600 "" "38" 0x01]
+ Pin[122500 -92500 6600 2000 8600 4600 "" "37" 0x01]
+ Pin[132500 -102500 6600 2000 8600 4600 "" "40" 0x01]
+ Pin[132500 -92500 6600 2000 8600 4600 "" "39" 0x01]
+ Pin[142500 -102500 6600 2000 8600 4600 "" "42" 0x01]
+ Pin[142500 -92500 6600 2000 8600 4600 "" "41" 0x01]
+ Pin[152500 -102500 6600 2000 8600 4600 "" "44" 0x01]
+ Pin[152500 -92500 6600 2000 8600 4600 "" "43" 0x01]
+ Pin[162500 -102500 6600 2000 8600 4600 "" "46" 0x01]
+ Pin[162500 -92500 6600 2000 8600 4600 "" "45" 0x01]
+)
diff --git a/bbb_cape/schematic/symbols/MCP3008-ISL-1.sym b/bbb_cape/schematic/symbols/MCP3008-ISL-1.sym
new file mode 100644
index 0000000..2627b4e
--- /dev/null
+++ b/bbb_cape/schematic/symbols/MCP3008-ISL-1.sym
@@ -0,0 +1,190 @@
+v 20110115 2
+B 300 0 1900 2400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 2500 1600 2200 1600 1 0 0
+{
+T 2500 1600 5 10 0 0 0 0 1
+pintype=pwr
+T 2145 1595 5 10 1 1 0 6 1
+pinlabel=DVDD
+T 2295 1645 5 10 1 1 0 0 1
+pinnumber=16
+T 2500 1600 5 10 0 0 0 0 1
+pinseq=0
+}
+P 2500 1300 2200 1300 1 0 0
+{
+T 2500 1300 5 10 0 0 0 0 1
+pintype=pwr
+T 2145 1295 5 10 1 1 0 6 1
+pinlabel=DGND
+T 2295 1345 5 10 1 1 0 0 1
+pinnumber=9
+T 2500 1300 5 10 0 0 0 0 1
+pinseq=0
+}
+P 2500 2200 2200 2200 1 0 0
+{
+T 2500 2200 5 10 0 0 0 0 1
+pintype=pwr
+T 2145 2195 5 10 1 1 0 6 1
+pinlabel=AVDD
+T 2295 2245 5 10 1 1 0 0 1
+pinnumber=15
+T 2500 2200 5 10 0 0 0 0 1
+pinseq=0
+}
+P 2500 1900 2200 1900 1 0 0
+{
+T 2500 1900 5 10 0 0 0 0 1
+pintype=pwr
+T 2145 1895 5 10 1 1 0 6 1
+pinlabel=AGND
+T 2295 1945 5 10 1 1 0 0 1
+pinnumber=14
+T 2500 1900 5 10 0 0 0 0 1
+pinseq=0
+}
+P 2500 1000 2200 1000 1 0 0
+{
+T 2500 1000 5 10 0 0 0 0 1
+pintype=clk
+T 2145 995 5 10 1 1 0 6 1
+pinlabel=CLK
+T 2295 1045 5 10 1 1 0 0 1
+pinnumber=13
+T 2500 1000 5 10 0 0 0 0 1
+pinseq=0
+}
+P 2500 700 2200 700 1 0 0
+{
+T 2500 700 5 10 0 0 0 0 1
+pintype=in
+T 2145 695 5 10 1 1 0 6 1
+pinlabel=\_CS\_
+T 2295 745 5 10 1 1 0 0 1
+pinnumber=10
+T 2500 700 5 10 0 0 0 0 1
+pinseq=0
+}
+P 2500 400 2200 400 1 0 0
+{
+T 2500 400 5 10 0 0 0 0 1
+pintype=in
+T 2145 395 5 10 1 1 0 6 1
+pinlabel=MOSI
+T 2295 445 5 10 1 1 0 0 1
+pinnumber=11
+T 2500 400 5 10 0 0 0 0 1
+pinseq=0
+}
+P 2500 100 2200 100 1 0 0
+{
+T 2500 100 5 10 0 0 0 0 1
+pintype=out
+T 2145 95 5 10 1 1 0 6 1
+pinlabel=MISO
+T 2295 145 5 10 1 1 0 0 1
+pinnumber=12
+T 2500 100 5 10 0 0 0 0 1
+pinseq=0
+}
+P 0 2200 300 2200 1 0 0
+{
+T 0 2200 5 10 0 0 0 0 1
+pintype=in
+T 355 2195 5 10 1 1 0 0 1
+pinlabel=CH0
+T 205 2245 5 10 1 1 0 6 1
+pinnumber=1
+T 0 2200 5 10 0 0 0 0 1
+pinseq=0
+}
+P 0 1900 300 1900 1 0 0
+{
+T 0 1900 5 10 0 0 0 0 1
+pintype=in
+T 355 1895 5 10 1 1 0 0 1
+pinlabel=CH1
+T 205 1945 5 10 1 1 0 6 1
+pinnumber=2
+T 0 1900 5 10 0 0 0 0 1
+pinseq=0
+}
+P 0 1600 300 1600 1 0 0
+{
+T 0 1600 5 10 0 0 0 0 1
+pintype=in
+T 355 1595 5 10 1 1 0 0 1
+pinlabel=CH2
+T 205 1645 5 10 1 1 0 6 1
+pinnumber=3
+T 0 1600 5 10 0 0 0 0 1
+pinseq=0
+}
+P 0 1300 300 1300 1 0 0
+{
+T 0 1300 5 10 0 0 0 0 1
+pintype=in
+T 355 1295 5 10 1 1 0 0 1
+pinlabel=CH3
+T 205 1345 5 10 1 1 0 6 1
+pinnumber=4
+T 0 1300 5 10 0 0 0 0 1
+pinseq=0
+}
+P 0 1000 300 1000 1 0 0
+{
+T 0 1000 5 10 0 0 0 0 1
+pintype=in
+T 355 995 5 10 1 1 0 0 1
+pinlabel=CH4
+T 205 1045 5 10 1 1 0 6 1
+pinnumber=5
+T 0 1000 5 10 0 0 0 0 1
+pinseq=0
+}
+P 0 700 300 700 1 0 0
+{
+T 0 700 5 10 0 0 0 0 1
+pintype=in
+T 355 695 5 10 1 1 0 0 1
+pinlabel=CH5
+T 205 745 5 10 1 1 0 6 1
+pinnumber=6
+T 0 700 5 10 0 0 0 0 1
+pinseq=0
+}
+P 0 400 300 400 1 0 0
+{
+T 0 400 5 10 0 0 0 0 1
+pintype=in
+T 355 395 5 10 1 1 0 0 1
+pinlabel=CH6
+T 205 445 5 10 1 1 0 6 1
+pinnumber=7
+T 0 400 5 10 0 0 0 0 1
+pinseq=0
+}
+P 0 100 300 100 1 0 0
+{
+T 0 100 5 10 0 0 0 0 1
+pintype=in
+T 355 95 5 10 1 1 0 0 1
+pinlabel=CH7
+T 205 145 5 10 1 1 0 6 1
+pinnumber=8
+T 0 100 5 10 0 0 0 0 1
+pinseq=0
+}
+T 3100 800 8 10 0 1 0 0 1
+footprint=SO16
+T 3000 900 8 10 0 1 0 0 1
+device=MCP3008-ISL
+T 3000 600 8 10 0 1 0 0 1
+description=microchip SPI ADC
+T 1100 2200 8 10 1 1 0 0 1
+refdes=U?
+T 1400 2700 8 10 0 1 0 0 1
+numslots=1
+T 700 2500 9 10 1 0 0 0 1
+MCP3008-ISL
diff --git a/bbb_cape/schematic/symbols/beaglebone-1.sym b/bbb_cape/schematic/symbols/beaglebone-1.sym
new file mode 100644
index 0000000..c2f9a56
--- /dev/null
+++ b/bbb_cape/schematic/symbols/beaglebone-1.sym
@@ -0,0 +1,1030 @@
+v 20110115 2
+P 8700 18500 8400 18500 1 0 0
+{
+T 8500 18550 5 8 1 1 0 0 1
+pinnumber=1
+T 8500 18450 5 8 0 1 0 2 1
+pinseq=1
+T 8350 18500 9 8 1 1 0 6 1
+pinlabel=GND
+T 8350 18500 5 8 0 1 0 8 1
+pintype=pwr
+}
+P 8700 18100 8400 18100 1 0 0
+{
+T 8500 18150 5 8 1 1 0 0 1
+pinnumber=2
+T 8500 18050 5 8 0 1 0 2 1
+pinseq=2
+T 8350 18100 9 8 1 1 0 6 1
+pinlabel=GND
+T 8350 18100 5 8 0 1 0 8 1
+pintype=pwr
+}
+P 8700 17700 8400 17700 1 0 0
+{
+T 8500 17750 5 8 1 1 0 0 1
+pinnumber=3
+T 8500 17650 5 8 0 1 0 2 1
+pinseq=3
+T 8350 17700 9 8 1 1 0 6 1
+pinlabel=(R9) GPIO1_6
+T 8350 17700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 17300 8400 17300 1 0 0
+{
+T 8500 17350 5 8 1 1 0 0 1
+pinnumber=4
+T 8500 17250 5 8 0 1 0 2 1
+pinseq=4
+T 8350 17300 9 8 1 1 0 6 1
+pinlabel=(T9) GPIO1_7
+T 8350 17300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 16900 8400 16900 1 0 0
+{
+T 8500 16950 5 8 1 1 0 0 1
+pinnumber=5
+T 8500 16850 5 8 0 1 0 2 1
+pinseq=5
+T 8350 16900 9 8 1 1 0 6 1
+pinlabel=(R8) GPIO1_2
+T 8350 16900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 16500 8400 16500 1 0 0
+{
+T 8500 16550 5 8 1 1 0 0 1
+pinnumber=6
+T 8500 16450 5 8 0 1 0 2 1
+pinseq=6
+T 8350 16500 9 8 1 1 0 6 1
+pinlabel=(T8) GPIO1_3
+T 8350 16500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 16100 8400 16100 1 0 0
+{
+T 8500 16150 5 8 1 1 0 0 1
+pinnumber=7
+T 8500 16050 5 8 0 1 0 2 1
+pinseq=7
+T 8350 16100 9 8 1 1 0 6 1
+pinlabel=(R7) TIMER4
+T 8350 16100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 15700 8400 15700 1 0 0
+{
+T 8500 15750 5 8 1 1 0 0 1
+pinnumber=8
+T 8500 15650 5 8 0 1 0 2 1
+pinseq=8
+T 8350 15700 9 8 1 1 0 6 1
+pinlabel=(T7) TIMER7
+T 8350 15700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 15300 8400 15300 1 0 0
+{
+T 8500 15350 5 8 1 1 0 0 1
+pinnumber=9
+T 8500 15250 5 8 0 1 0 2 1
+pinseq=9
+T 8350 15300 9 8 1 1 0 6 1
+pinlabel=(T6) TIMER5
+T 8350 15300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 14900 8400 14900 1 0 0
+{
+T 8500 14950 5 8 1 1 0 0 1
+pinnumber=10
+T 8500 14850 5 8 0 1 0 2 1
+pinseq=10
+T 8350 14900 9 8 1 1 0 6 1
+pinlabel=(U6) TIMER6
+T 8350 14900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 14500 8400 14500 1 0 0
+{
+T 8500 14550 5 8 1 1 0 0 1
+pinnumber=11
+T 8500 14450 5 8 0 1 0 2 1
+pinseq=11
+T 8350 14500 9 8 1 1 0 6 1
+pinlabel=(R12) GPIO1_13
+T 8350 14500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 14100 8400 14100 1 0 0
+{
+T 8500 14150 5 8 1 1 0 0 1
+pinnumber=12
+T 8500 14050 5 8 0 1 0 2 1
+pinseq=12
+T 8350 14100 9 8 1 1 0 6 1
+pinlabel=(T12) GPIO1_12
+T 8350 14100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 13700 8400 13700 1 0 0
+{
+T 8500 13750 5 8 1 1 0 0 1
+pinnumber=13
+T 8500 13650 5 8 0 1 0 2 1
+pinseq=13
+T 8350 13700 9 8 1 1 0 6 1
+pinlabel=(T10) EHRPWM2B
+T 8350 13700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 13300 8400 13300 1 0 0
+{
+T 8500 13350 5 8 1 1 0 0 1
+pinnumber=14
+T 8500 13250 5 8 0 1 0 2 1
+pinseq=14
+T 8350 13300 9 8 1 1 0 6 1
+pinlabel=(T11) GPIO0_26
+T 8350 13300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 12900 8400 12900 1 0 0
+{
+T 8500 12950 5 8 1 1 0 0 1
+pinnumber=15
+T 8500 12850 5 8 0 1 0 2 1
+pinseq=15
+T 8350 12900 9 8 1 1 0 6 1
+pinlabel=(U13) GPIO1_15
+T 8350 12900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 12500 8400 12500 1 0 0
+{
+T 8500 12550 5 8 1 1 0 0 1
+pinnumber=16
+T 8500 12450 5 8 0 1 0 2 1
+pinseq=16
+T 8350 12500 9 8 1 1 0 6 1
+pinlabel=(V13) GPIO1_14
+T 8350 12500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 12100 8400 12100 1 0 0
+{
+T 8500 12150 5 8 1 1 0 0 1
+pinnumber=17
+T 8500 12050 5 8 0 1 0 2 1
+pinseq=17
+T 8350 12100 9 8 1 1 0 6 1
+pinlabel=(U12) GPIO0_27
+T 8350 12100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 11700 8400 11700 1 0 0
+{
+T 8500 11750 5 8 1 1 0 0 1
+pinnumber=18
+T 8500 11650 5 8 0 1 0 2 1
+pinseq=18
+T 8350 11700 9 8 1 1 0 6 1
+pinlabel=(V12) GPIO2_1
+T 8350 11700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 11300 8400 11300 1 0 0
+{
+T 8500 11350 5 8 1 1 0 0 1
+pinnumber=19
+T 8500 11250 5 8 0 1 0 2 1
+pinseq=19
+T 8350 11300 9 8 1 1 0 6 1
+pinlabel=(U10) EHRPWM2A
+T 8350 11300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 10900 8400 10900 1 0 0
+{
+T 8500 10950 5 8 1 1 0 0 1
+pinnumber=20
+T 8500 10850 5 8 0 1 0 2 1
+pinseq=20
+T 8350 10900 9 8 1 1 0 6 1
+pinlabel=(V9) GPIO1_31
+T 8350 10900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 10500 8400 10500 1 0 0
+{
+T 8500 10550 5 8 1 1 0 0 1
+pinnumber=21
+T 8500 10450 5 8 0 1 0 2 1
+pinseq=21
+T 8350 10500 9 8 1 1 0 6 1
+pinlabel=(U9) GPIO1_30
+T 8350 10500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 10100 8400 10100 1 0 0
+{
+T 8500 10150 5 8 1 1 0 0 1
+pinnumber=22
+T 8500 10050 5 8 0 1 0 2 1
+pinseq=22
+T 8350 10100 9 8 1 1 0 6 1
+pinlabel=(V8) GPIO1_5
+T 8350 10100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 9700 8400 9700 1 0 0
+{
+T 8500 9750 5 8 1 1 0 0 1
+pinnumber=23
+T 8500 9650 5 8 0 1 0 2 1
+pinseq=23
+T 8350 9700 9 8 1 1 0 6 1
+pinlabel=(U8) GPIO1_4
+T 8350 9700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 9300 8400 9300 1 0 0
+{
+T 8500 9350 5 8 1 1 0 0 1
+pinnumber=24
+T 8500 9250 5 8 0 1 0 2 1
+pinseq=24
+T 8350 9300 9 8 1 1 0 6 1
+pinlabel=(V7) GPIO1_1
+T 8350 9300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 8900 8400 8900 1 0 0
+{
+T 8500 8950 5 8 1 1 0 0 1
+pinnumber=25
+T 8500 8850 5 8 0 1 0 2 1
+pinseq=25
+T 8350 8900 9 8 1 1 0 6 1
+pinlabel=(U7) GPIO1_0
+T 8350 8900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 8500 8400 8500 1 0 0
+{
+T 8500 8550 5 8 1 1 0 0 1
+pinnumber=26
+T 8500 8450 5 8 0 1 0 2 1
+pinseq=26
+T 8350 8500 9 8 1 1 0 6 1
+pinlabel=(V6) GPIO1_29
+T 8350 8500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 8100 8400 8100 1 0 0
+{
+T 8500 8150 5 8 1 1 0 0 1
+pinnumber=27
+T 8500 8050 5 8 0 1 0 2 1
+pinseq=27
+T 8350 8100 9 8 1 1 0 6 1
+pinlabel=(U5) GPIO2_22
+T 8350 8100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 7700 8400 7700 1 0 0
+{
+T 8500 7750 5 8 1 1 0 0 1
+pinnumber=28
+T 8500 7650 5 8 0 1 0 2 1
+pinseq=28
+T 8350 7700 9 8 1 1 0 6 1
+pinlabel=(V5) GPIO2_24
+T 8350 7700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 7300 8400 7300 1 0 0
+{
+T 8500 7350 5 8 1 1 0 0 1
+pinnumber=29
+T 8500 7250 5 8 0 1 0 2 1
+pinseq=29
+T 8350 7300 9 8 1 1 0 6 1
+pinlabel=(R5) GPIO2_23
+T 8350 7300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 6900 8400 6900 1 0 0
+{
+T 8500 6950 5 8 1 1 0 0 1
+pinnumber=30
+T 8500 6850 5 8 0 1 0 2 1
+pinseq=30
+T 8350 6900 9 8 1 1 0 6 1
+pinlabel=(R6) GPIO2_25
+T 8350 6900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 6500 8400 6500 1 0 0
+{
+T 8500 6550 5 8 1 1 0 0 1
+pinnumber=31
+T 8500 6450 5 8 0 1 0 2 1
+pinseq=31
+T 8350 6500 9 8 1 1 0 6 1
+pinlabel=(V4) UART5_CTSN
+T 8350 6500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 6100 8400 6100 1 0 0
+{
+T 8500 6150 5 8 1 1 0 0 1
+pinnumber=32
+T 8500 6050 5 8 0 1 0 2 1
+pinseq=32
+T 8350 6100 9 8 1 1 0 6 1
+pinlabel=(T5) UART5_RTSN
+T 8350 6100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 5700 8400 5700 1 0 0
+{
+T 8500 5750 5 8 1 1 0 0 1
+pinnumber=33
+T 8500 5650 5 8 0 1 0 2 1
+pinseq=33
+T 8350 5700 9 8 1 1 0 6 1
+pinlabel=(V3) UART4_RTSN
+T 8350 5700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 5300 8400 5300 1 0 0
+{
+T 8500 5350 5 8 1 1 0 0 1
+pinnumber=34
+T 8500 5250 5 8 0 1 0 2 1
+pinseq=34
+T 8350 5300 9 8 1 1 0 6 1
+pinlabel=(U4) UART3_RTSN
+T 8350 5300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 4900 8400 4900 1 0 0
+{
+T 8500 4950 5 8 1 1 0 0 1
+pinnumber=35
+T 8500 4850 5 8 0 1 0 2 1
+pinseq=35
+T 8350 4900 9 8 1 1 0 6 1
+pinlabel=(V2) UART4_CTSN
+T 8350 4900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 4500 8400 4500 1 0 0
+{
+T 8500 4550 5 8 1 1 0 0 1
+pinnumber=36
+T 8500 4450 5 8 0 1 0 2 1
+pinseq=36
+T 8350 4500 9 8 1 1 0 6 1
+pinlabel=(U3) UART3_CTSN
+T 8350 4500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 4100 8400 4100 1 0 0
+{
+T 8500 4150 5 8 1 1 0 0 1
+pinnumber=37
+T 8500 4050 5 8 0 1 0 2 1
+pinseq=37
+T 8350 4100 9 8 1 1 0 6 1
+pinlabel=(U1) UART5_TXD
+T 8350 4100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 3700 8400 3700 1 0 0
+{
+T 8500 3750 5 8 1 1 0 0 1
+pinnumber=38
+T 8500 3650 5 8 0 1 0 2 1
+pinseq=38
+T 8350 3700 9 8 1 1 0 6 1
+pinlabel=(U2) UART5_RXD
+T 8350 3700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 3300 8400 3300 1 0 0
+{
+T 8500 3350 5 8 1 1 0 0 1
+pinnumber=39
+T 8500 3250 5 8 0 1 0 2 1
+pinseq=39
+T 8350 3300 9 8 1 1 0 6 1
+pinlabel=(T3) GPIO2_12
+T 8350 3300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 2900 8400 2900 1 0 0
+{
+T 8500 2950 5 8 1 1 0 0 1
+pinnumber=40
+T 8500 2850 5 8 0 1 0 2 1
+pinseq=40
+T 8350 2900 9 8 1 1 0 6 1
+pinlabel=(T4) GPIO2_13
+T 8350 2900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 2500 8400 2500 1 0 0
+{
+T 8500 2550 5 8 1 1 0 0 1
+pinnumber=41
+T 8500 2450 5 8 0 1 0 2 1
+pinseq=41
+T 8350 2500 9 8 1 1 0 6 1
+pinlabel=(T1) GPIO2_10
+T 8350 2500 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 2100 8400 2100 1 0 0
+{
+T 8500 2150 5 8 1 1 0 0 1
+pinnumber=42
+T 8500 2050 5 8 0 1 0 2 1
+pinseq=42
+T 8350 2100 9 8 1 1 0 6 1
+pinlabel=(T2) GPIO2_11
+T 8350 2100 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 1700 8400 1700 1 0 0
+{
+T 8500 1750 5 8 1 1 0 0 1
+pinnumber=43
+T 8500 1650 5 8 0 1 0 2 1
+pinseq=43
+T 8350 1700 9 8 1 1 0 6 1
+pinlabel=(R3) GPIO2_8
+T 8350 1700 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 1300 8400 1300 1 0 0
+{
+T 8500 1350 5 8 1 1 0 0 1
+pinnumber=44
+T 8500 1250 5 8 0 1 0 2 1
+pinseq=44
+T 8350 1300 9 8 1 1 0 6 1
+pinlabel=(R4) GPIO2_9
+T 8350 1300 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 900 8400 900 1 0 0
+{
+T 8500 950 5 8 1 1 0 0 1
+pinnumber=45
+T 8500 850 5 8 0 1 0 2 1
+pinseq=45
+T 8350 900 9 8 1 1 0 6 1
+pinlabel=(R1) GPIO2_6
+T 8350 900 5 8 0 1 0 8 1
+pintype=io
+}
+P 8700 500 8400 500 1 0 0
+{
+T 8500 550 5 8 1 1 0 0 1
+pinnumber=46
+T 8500 450 5 8 0 1 0 2 1
+pinseq=46
+T 8350 500 9 8 1 1 0 6 1
+pinlabel=(R2) GPIO2_7
+T 8350 500 5 8 0 1 0 8 1
+pintype=io
+}
+P 100 18500 400 18500 1 0 0
+{
+T 300 18550 5 8 1 1 0 6 1
+pinnumber=47
+T 300 18450 5 8 0 1 0 8 1
+pinseq=1
+T 450 18500 9 8 1 1 0 0 1
+pinlabel=(1) GND
+T 450 18500 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 18100 400 18100 1 0 0
+{
+T 300 18150 5 8 1 1 0 6 1
+pinnumber=48
+T 300 18050 5 8 0 1 0 8 1
+pinseq=2
+T 450 18100 9 8 1 1 0 0 1
+pinlabel=(2) GND
+T 450 18100 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 17700 400 17700 1 0 0
+{
+T 300 17750 5 8 1 1 0 6 1
+pinnumber=49
+T 300 17650 5 8 0 1 0 8 1
+pinseq=3
+T 450 17700 9 8 1 1 0 0 1
+pinlabel=(3) DC_3.3V
+T 450 17700 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 17300 400 17300 1 0 0
+{
+T 300 17350 5 8 1 1 0 6 1
+pinnumber=50
+T 300 17250 5 8 0 1 0 8 1
+pinseq=4
+T 450 17300 9 8 1 1 0 0 1
+pinlabel=(4) DC_3.3V
+T 450 17300 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 16900 400 16900 1 0 0
+{
+T 300 16950 5 8 1 1 0 6 1
+pinnumber=51
+T 300 16850 5 8 0 1 0 8 1
+pinseq=5
+T 450 16900 9 8 1 1 0 0 1
+pinlabel=(5) VDD_5V
+T 450 16900 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 16500 400 16500 1 0 0
+{
+T 300 16550 5 8 1 1 0 6 1
+pinnumber=52
+T 300 16450 5 8 0 1 0 8 1
+pinseq=6
+T 450 16500 9 8 1 1 0 0 1
+pinlabel=(6) VDD_5V
+T 450 16500 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 16100 400 16100 1 0 0
+{
+T 300 16150 5 8 1 1 0 6 1
+pinnumber=53
+T 300 16050 5 8 0 1 0 8 1
+pinseq=7
+T 450 16100 9 8 1 1 0 0 1
+pinlabel=(7) SYS_5V
+T 450 16100 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 15700 400 15700 1 0 0
+{
+T 300 15750 5 8 1 1 0 6 1
+pinnumber=54
+T 300 15650 5 8 0 1 0 8 1
+pinseq=8
+T 450 15700 9 8 1 1 0 0 1
+pinlabel=(8) SYS_5V
+T 450 15700 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 15300 400 15300 1 0 0
+{
+T 300 15350 5 8 1 1 0 6 1
+pinnumber=55
+T 300 15250 5 8 0 1 0 8 1
+pinseq=9
+T 450 15300 9 8 1 1 0 0 1
+pinlabel=(9) PWR_BUT
+T 450 15300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 14900 400 14900 1 0 0
+{
+T 300 14950 5 8 1 1 0 6 1
+pinnumber=56
+T 300 14850 5 8 0 1 0 8 1
+pinseq=10
+T 450 14900 9 8 1 1 0 0 1
+pinlabel=(10) SYS_RESETn (A10)
+T 450 14900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 14500 400 14500 1 0 0
+{
+T 300 14550 5 8 1 1 0 6 1
+pinnumber=57
+T 300 14450 5 8 0 1 0 8 1
+pinseq=57
+T 450 14500 9 8 1 1 0 0 1
+pinlabel=(11) UART4_RXD (T17)
+T 450 14500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 14100 400 14100 1 0 0
+{
+T 300 14150 5 8 1 1 0 6 1
+pinnumber=58
+T 300 14050 5 8 0 1 0 8 1
+pinseq=58
+T 450 14100 9 8 1 1 0 0 1
+pinlabel=(12) GPIO1_28 (U18)
+T 450 14100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 13700 400 13700 1 0 0
+{
+T 300 13750 5 8 1 1 0 6 1
+pinnumber=59
+T 300 13650 5 8 0 1 0 8 1
+pinseq=59
+T 450 13700 9 8 1 1 0 0 1
+pinlabel=(13) UART4_TXD (U17)
+T 450 13700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 13300 400 13300 1 0 0
+{
+T 300 13350 5 8 1 1 0 6 1
+pinnumber=60
+T 300 13250 5 8 0 1 0 8 1
+pinseq=60
+T 450 13300 9 8 1 1 0 0 1
+pinlabel=(14) EHRPWM1A (U14)
+T 450 13300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 12900 400 12900 1 0 0
+{
+T 300 12950 5 8 1 1 0 6 1
+pinnumber=61
+T 300 12850 5 8 0 1 0 8 1
+pinseq=61
+T 450 12900 9 8 1 1 0 0 1
+pinlabel=(15) GPIO1_16 (R13)
+T 450 12900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 12500 400 12500 1 0 0
+{
+T 300 12550 5 8 1 1 0 6 1
+pinnumber=62
+T 300 12450 5 8 0 1 0 8 1
+pinseq=62
+T 450 12500 9 8 1 1 0 0 1
+pinlabel=(16) EHRPWM1B (T14)
+T 450 12500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 12100 400 12100 1 0 0
+{
+T 300 12150 5 8 1 1 0 6 1
+pinnumber=63
+T 300 12050 5 8 0 1 0 8 1
+pinseq=63
+T 450 12100 9 8 1 1 0 0 1
+pinlabel=(17) I2C1_SCL (A16)
+T 450 12100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 11700 400 11700 1 0 0
+{
+T 300 11750 5 8 1 1 0 6 1
+pinnumber=64
+T 300 11650 5 8 0 1 0 8 1
+pinseq=64
+T 450 11700 9 8 1 1 0 0 1
+pinlabel=(18) I2C1_SDA (B16)
+T 450 11700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 11300 400 11300 1 0 0
+{
+T 300 11350 5 8 1 1 0 6 1
+pinnumber=65
+T 300 11250 5 8 0 1 0 8 1
+pinseq=65
+T 450 11300 9 8 1 1 0 0 1
+pinlabel=(19) I2C2_SCL (D17)
+T 450 11300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 10900 400 10900 1 0 0
+{
+T 300 10950 5 8 1 1 0 6 1
+pinnumber=66
+T 300 10850 5 8 0 1 0 8 1
+pinseq=66
+T 450 10900 9 8 1 1 0 0 1
+pinlabel=(20) I2C2_SDA (D18)
+T 450 10900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 10500 400 10500 1 0 0
+{
+T 300 10550 5 8 1 1 0 6 1
+pinnumber=67
+T 300 10450 5 8 0 1 0 8 1
+pinseq=67
+T 450 10500 9 8 1 1 0 0 1
+pinlabel=(21) UART2_TXD (B17)
+T 450 10500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 10100 400 10100 1 0 0
+{
+T 300 10150 5 8 1 1 0 6 1
+pinnumber=68
+T 300 10050 5 8 0 1 0 8 1
+pinseq=68
+T 450 10100 9 8 1 1 0 0 1
+pinlabel=(22) UART2_RXD (A17)
+T 450 10100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 9700 400 9700 1 0 0
+{
+T 300 9750 5 8 1 1 0 6 1
+pinnumber=69
+T 300 9650 5 8 0 1 0 8 1
+pinseq=69
+T 450 9700 9 8 1 1 0 0 1
+pinlabel=(23) GPIO1_17 (V14)
+T 450 9700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 9300 400 9300 1 0 0
+{
+T 300 9350 5 8 1 1 0 6 1
+pinnumber=70
+T 300 9250 5 8 0 1 0 8 1
+pinseq=70
+T 450 9300 9 8 1 1 0 0 1
+pinlabel=(24) UART1_TXD (D15)
+T 450 9300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 8900 400 8900 1 0 0
+{
+T 300 8950 5 8 1 1 0 6 1
+pinnumber=71
+T 300 8850 5 8 0 1 0 8 1
+pinseq=71
+T 450 8900 9 8 1 1 0 0 1
+pinlabel=(25) GPIO3_21 (A14)
+T 450 8900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 8500 400 8500 1 0 0
+{
+T 300 8550 5 8 1 1 0 6 1
+pinnumber=72
+T 300 8450 5 8 0 1 0 8 1
+pinseq=72
+T 450 8500 9 8 1 1 0 0 1
+pinlabel=(26) UART1_RXD (D16)
+T 450 8500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 8100 400 8100 1 0 0
+{
+T 300 8150 5 8 1 1 0 6 1
+pinnumber=73
+T 300 8050 5 8 0 1 0 8 1
+pinseq=73
+T 450 8100 9 8 1 1 0 0 1
+pinlabel=(27) GPIO3_19 (C13)
+T 450 8100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 7700 400 7700 1 0 0
+{
+T 300 7750 5 8 1 1 0 6 1
+pinnumber=74
+T 300 7650 5 8 0 1 0 8 1
+pinseq=74
+T 450 7700 9 8 1 1 0 0 1
+pinlabel=(28) SPI1_CS0 (C12)
+T 450 7700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 7300 400 7300 1 0 0
+{
+T 300 7350 5 8 1 1 0 6 1
+pinnumber=75
+T 300 7250 5 8 0 1 0 8 1
+pinseq=75
+T 450 7300 9 8 1 1 0 0 1
+pinlabel=(29) SPI1_D0 (B13)
+T 450 7300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 6900 400 6900 1 0 0
+{
+T 300 6950 5 8 1 1 0 6 1
+pinnumber=76
+T 300 6850 5 8 0 1 0 8 1
+pinseq=76
+T 450 6900 9 8 1 1 0 0 1
+pinlabel=(30) SPI1_D1 (D12)
+T 450 6900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 6500 400 6500 1 0 0
+{
+T 300 6550 5 8 1 1 0 6 1
+pinnumber=77
+T 300 6450 5 8 0 1 0 8 1
+pinseq=77
+T 450 6500 9 8 1 1 0 0 1
+pinlabel=(31) SPI1_SCLK (A13)
+T 450 6500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 6100 400 6100 1 0 0
+{
+T 300 6150 5 8 1 1 0 6 1
+pinnumber=78
+T 300 6050 5 8 0 1 0 8 1
+pinseq=78
+T 450 6100 9 8 1 1 0 0 1
+pinlabel=(32) VADC
+T 450 6100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 5700 400 5700 1 0 0
+{
+T 300 5750 5 8 1 1 0 6 1
+pinnumber=79
+T 300 5650 5 8 0 1 0 8 1
+pinseq=79
+T 450 5700 9 8 1 1 0 0 1
+pinlabel=(33) AIN4 (C8)
+T 450 5700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 5300 400 5300 1 0 0
+{
+T 300 5350 5 8 1 1 0 6 1
+pinnumber=80
+T 300 5250 5 8 0 1 0 8 1
+pinseq=80
+T 450 5300 9 8 1 1 0 0 1
+pinlabel=(34) AGND
+T 450 5300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 4900 400 4900 1 0 0
+{
+T 300 4950 5 8 1 1 0 6 1
+pinnumber=81
+T 300 4850 5 8 0 1 0 8 1
+pinseq=81
+T 450 4900 9 8 1 1 0 0 1
+pinlabel=(35) AIN6 (A8)
+T 450 4900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 4500 400 4500 1 0 0
+{
+T 300 4550 5 8 1 1 0 6 1
+pinnumber=82
+T 300 4450 5 8 0 1 0 8 1
+pinseq=82
+T 450 4500 9 8 1 1 0 0 1
+pinlabel=(36) AIN5 (B8)
+T 450 4500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 4100 400 4100 1 0 0
+{
+T 300 4150 5 8 1 1 0 6 1
+pinnumber=83
+T 300 4050 5 8 0 1 0 8 1
+pinseq=83
+T 450 4100 9 8 1 1 0 0 1
+pinlabel=(37) AIN2 (B7)
+T 450 4100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 3700 400 3700 1 0 0
+{
+T 300 3750 5 8 1 1 0 6 1
+pinnumber=84
+T 300 3650 5 8 0 1 0 8 1
+pinseq=84
+T 450 3700 9 8 1 1 0 0 1
+pinlabel=(38) AIN3 (A7)
+T 450 3700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 3300 400 3300 1 0 0
+{
+T 300 3350 5 8 1 1 0 6 1
+pinnumber=85
+T 300 3250 5 8 0 1 0 8 1
+pinseq=85
+T 450 3300 9 8 1 1 0 0 1
+pinlabel=(39) AIN0 (B6)
+T 450 3300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2900 400 2900 1 0 0
+{
+T 300 2950 5 8 1 1 0 6 1
+pinnumber=86
+T 300 2850 5 8 0 1 0 8 1
+pinseq=86
+T 450 2900 9 8 1 1 0 0 1
+pinlabel=(40) AIN1 (C7)
+T 450 2900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2500 400 2500 1 0 0
+{
+T 300 2550 5 8 1 1 0 6 1
+pinnumber=87
+T 300 2450 5 8 0 1 0 8 1
+pinseq=87
+T 450 2500 9 8 1 1 0 0 1
+pinlabel=(41) CLKOUT2 (D14)
+T 450 2500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2100 400 2100 1 0 0
+{
+T 300 2150 5 8 1 1 0 6 1
+pinnumber=88
+T 300 2050 5 8 0 1 0 8 1
+pinseq=88
+T 450 2100 9 8 1 1 0 0 1
+pinlabel=(42) GPIO0_7 (C18)
+T 450 2100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 1700 400 1700 1 0 0
+{
+T 300 1750 5 8 1 1 0 6 1
+pinnumber=89
+T 300 1650 5 8 0 1 0 8 1
+pinseq=89
+T 450 1700 9 8 1 1 0 0 1
+pinlabel=(43) GND
+T 450 1700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 1300 400 1300 1 0 0
+{
+T 300 1350 5 8 1 1 0 6 1
+pinnumber=90
+T 300 1250 5 8 0 1 0 8 1
+pinseq=90
+T 450 1300 9 8 1 1 0 0 1
+pinlabel=(44) GND
+T 450 1300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 900 400 900 1 0 0
+{
+T 300 950 5 8 1 1 0 6 1
+pinnumber=91
+T 300 850 5 8 0 1 0 8 1
+pinseq=91
+T 450 900 9 8 1 1 0 0 1
+pinlabel=(45) GND
+T 450 900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 500 400 500 1 0 0
+{
+T 300 550 5 8 1 1 0 6 1
+pinnumber=92
+T 300 450 5 8 0 1 0 8 1
+pinseq=92
+T 450 500 9 8 1 1 0 0 1
+pinlabel=(46) GND
+T 450 500 5 8 0 1 0 2 1
+pintype=io
+}
+B 400 100 8000 18800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 8400 19000 8 10 1 1 0 6 1
+refdes=U?
+T 3400 18550 9 10 1 0 0 0 1
+BEAGLEBONE BLACK CAPE
+T 4200 9850 5 10 0 0 0 0 1
+device=BEAGLEBOND BLACK CAPE
+T 4200 10050 5 10 0 0 0 0 1
+footprint=beaglebone
+T 4200 10650 5 10 0 0 0 0 1
+description=TI Sitara AM335x powered development board
+T 4200 10850 5 10 0 0 0 0 1
+numslots=0
+T 1300 18500 3 10 1 0 0 0 1
+P9
+T 7500 18500 3 10 1 0 0 0 1
+P8
diff --git a/bbb_cape/schematic/symbols/regulator-1.sym b/bbb_cape/schematic/symbols/regulator-1.sym
index 6506122..b08f11c 100644
--- a/bbb_cape/schematic/symbols/regulator-1.sym
+++ b/bbb_cape/schematic/symbols/regulator-1.sym
@@ -29,7 +29,7 @@
T -700 1300 8 10 0 1 0 0 1
description=voltage regulator
T 800 1300 8 10 1 1 0 0 1
-refdes=U?
+refdes=X?
P 1500 200 1500 500 1 0 0
{
T 1500 200 5 10 0 0 0 0 1