diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
new file mode 100644
index 0000000..f800c2f
--- /dev/null
+++ b/src/CMakeLists.txt
@@ -0,0 +1,121 @@
+cmake_policy(SET CMP0079 NEW) # allow inserting of dependencies into our INTERFACE libraries
+set(PICO_PLATFORM_CMAKE_FILE "" CACHE INTERNAL "")
+set(PICO_DOXYGEN_PATHS "" CACHE INTERNAL "") # generated each time
+
+if (NOT PICO_PLATFORM_CMAKE_FILE)
+    set(PICO_PLATFORM_CMAKE_FILE ${CMAKE_CURRENT_LIST_DIR}/${PICO_PLATFORM}.cmake CACHE INTERNAL "")
+endif ()
+
+if (NOT EXISTS "${PICO_PLATFORM_CMAKE_FILE}")
+    message(FATAL_ERROR "${PICO_PLATFORM_CMAKE_FILE} does not exist. \
+    Either specify a valid PICO_PLATFORM (or PICO_PLATFORM_CMAKE_FILE).")
+endif ()
+
+# Initialize board related build/compile settings
+include(${CMAKE_CURRENT_LIST_DIR}/board_setup.cmake)
+
+# call add_subdirectory(subdir) unless SKIP_SUBDIR evaluates to true
+function(pico_add_subdirectory subdir)
+    # todo add option to disable skip flag
+    string(TOUPPER ${subdir} subdir_upper)
+    set(replace_flag SKIP_${subdir_upper})
+    if (NOT ${replace_flag})
+        add_subdirectory(${subdir})
+    else ()
+        message("Not including ${subdir} because ${replace_flag} defined.")
+    endif ()
+    pico_promote_common_scope_vars()
+endfunction()
+
+# add a link option to wrap the given function name; i.e. -Wl:wrap=FUNCNAME for gcc
+function(pico_wrap_function TARGET FUNCNAME)
+    target_link_options(${TARGET} INTERFACE "LINKER:--wrap=${FUNCNAME}")
+endfunction()
+
+# add map file generation for the given target
+function(pico_add_map_output TARGET)
+    get_target_property(target_type ${TARGET} TYPE)
+    if ("EXECUTABLE" STREQUAL "${target_type}")
+        target_link_options(${TARGET} PRIVATE "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map")
+    else ()
+        target_link_options(${TARGET} INTERFACE "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map")
+    endif ()
+endfunction()
+
+# create a hardware_NAME_headers target (see pico_pico_simple_hardware_headers_target)
+# create a hardware_NAME target (see pico_pico_simple_hardware_target)
+macro(pico_simple_hardware_target NAME)
+    pico_simple_hardware_headers_target(${NAME})
+    pico_simple_hardware_impl_target(${NAME})
+endmacro()
+
+# create an INTERFACE library named target, and define LIB_TARGET=1 (upper case) as a compile option
+function(pico_add_impl_library target)
+    add_library(${target} INTERFACE)
+    string(TOUPPER ${target} TARGET_UPPER)
+    target_compile_definitions(${target} INTERFACE LIB_${TARGET_UPPER}=1)
+endfunction()
+
+# create an INTERFACE library named hardware_NAME_headers INTERFACE library if it doesn't already exist,
+#        and add include/ relative to the calling directory to the includes.
+#        and hardware_structs and hardware_claim as dependencies of the library
+macro(pico_simple_hardware_headers_target NAME)
+    if (NOT TARGET hardware_${NAME}_headers)
+        add_library(hardware_${NAME}_headers INTERFACE)
+
+        target_include_directories(hardware_${NAME}_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+        target_link_libraries(hardware_${NAME}_headers INTERFACE pico_base_headers)
+        if (NOT PICO_NO_HARDWARE)
+            target_link_libraries(hardware_${NAME}_headers INTERFACE hardware_structs hardware_claim)
+        endif()
+    endif()
+endmacro()
+
+# create an INTERFACE library named hardware_NAME if it doesn't exist, along with a hardware_NAME_headers
+#        INTERFACE library that it depends on. The hardware_NAME_headers library add include/ relative to
+#        and pico_base_headers, and harddware_structs as a dependency of the library
+macro(pico_simple_hardware_headers_only_target NAME)
+    if (NOT TARGET hardware_${NAME})
+        # Choosing not to add LIB_HARDWARE_ defines to avoid command line bloat pending a need (they aren't
+        #   super interesting except to determine functionality as they are mostly passive accessors, however
+        #   they could be useful to determine if the header is available.
+        # pico_add_sdk_impl_library(hardware_${NAME})
+        add_library(hardware_${NAME} INTERFACE)
+
+        target_include_directories(hardware_${NAME} INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+        target_link_libraries(hardware_${NAME} INTERFACE pico_base_headers)
+        if (NOT PICO_NO_HARDWARE)
+            target_link_libraries(hardware_${NAME} INTERFACE hardware_structs)
+        endif()
+    endif()
+endmacro()
+
+# create an INTERFACE library named hardware_NAME if it doesn't exist, dependent on a pre-existing  hardware_NAME_headers
+#        INTERFACE library and pico_platform. The file NAME.c relative to the caller is added to the C sources for the hardware_NAME
+macro(pico_simple_hardware_impl_target NAME)
+    if (NOT TARGET hardware_${NAME})
+        # Choosing not to add LIB_HARDWARE_ defines to avoid command line bloat pending a need (they aren't
+        #   super interesting except to determine functionality as they are mostly passive accessors, however
+        #   they could be useful to determine if the header is available.
+        # pico_add_sdk_impl_library(hardware_${NAME})
+        add_library(hardware_${NAME} INTERFACE)
+
+        target_sources(hardware_${NAME} INTERFACE
+                ${CMAKE_CURRENT_LIST_DIR}/${NAME}.c
+                )
+
+        target_link_libraries(hardware_${NAME} INTERFACE hardware_${NAME}_headers pico_platform)
+    endif()
+endmacro()
+
+function(pico_add_doxygen SOURCE_DIR)
+    set(PICO_DOXYGEN_PATHS "${PICO_DOXYGEN_PATHS} ${SOURCE_DIR}" CACHE INTERNAL "")
+endfunction()
+
+function(pico_add_doxygen_exclude SOURCE_DIR)
+    set(PICO_DOXYGEN_EXCLUDE_PATHS "${PICO_DOXYGEN_EXCLUDE_PATHS} ${SOURCE_DIR}" CACHE INTERNAL "")
+endfunction()
+
+include(${PICO_PLATFORM_CMAKE_FILE})
+
+pico_promote_common_scope_vars()
\ No newline at end of file
diff --git a/src/board_setup.cmake b/src/board_setup.cmake
new file mode 100644
index 0000000..405d784
--- /dev/null
+++ b/src/board_setup.cmake
@@ -0,0 +1,31 @@
+# PICO_CMAKE_CONFIG: PICO_BOARD, The board name being built for. This is overridable from the user environment, type=string, default=pico, group=build
+if (DEFINED ENV{PICO_BOARD})
+    set(PICO_BOARD $ENV{PICO_BOARD})
+    message("Using PICO_BOARD from environment ('${PICO_BOARD}')")
+else()
+    if (NOT PICO_BOARD)
+        set(PICO_BOARD "pico")
+        pico_message("Defaulting PICO target board to ${PICO_BOARD} since not specified.")
+    else()
+        message("PICO target board is ${PICO_BOARD}.")
+    endif()
+endif()
+set(PICO_BOARD ${PICO_BOARD} CACHE STRING "PICO target board (e.g. pico)")
+
+# PICO_CMAKE_CONFIG: PICO_BOARD_CMAKE_DIRS, Directories to look for <PICO_BOARD>.cmake in. This is overridable from the user environment, type=list, default="", group=build
+if (DEFINED ENV{PICO_BOARD_CMAKE_DIRS})
+    set(PICO_BOARD_CMAKE_DIRS $ENV{PICO_BOARD_CMAKE_DIRS})
+    message("Using PICO_BOARD_CMAKE_DIRS from environment ('${PICO_BOARD_CMAKE_DIRS}')")
+endif()
+
+list(APPEND PICO_BOARD_CMAKE_DIRS ${CMAKE_CURRENT_LIST_DIR}/boards)
+
+pico_find_in_paths(PICO_BOARD_CMAKE_FILE PICO_BOARD_CMAKE_DIRS ${PICO_BOARD}.cmake)
+if (EXISTS "${PICO_BOARD_CMAKE_FILE}")
+    message("Using CMake board configuration from ${PICO_BOARD_CMAKE_FILE}")
+    include(${PICO_BOARD_CMAKE_FILE} board_config)
+else()
+    include(boards/generic_board.cmake)
+endif()
+
+list(APPEND PICO_INCLUDE_DIRS ${CMAKE_CURRENT_LIST_DIR}/boards/include) # so boards/foo.h can be explicitly included
diff --git a/src/boards/generic_board.cmake b/src/boards/generic_board.cmake
new file mode 100644
index 0000000..54b43d1
--- /dev/null
+++ b/src/boards/generic_board.cmake
@@ -0,0 +1,23 @@
+# For boards without their own cmake file, simply include a header
+
+# PICO_CMAKE_CONFIG: PICO_BOARD_HEADER_DIRS, Directories to look for <PICO_BOARD>.h in. This is overridable from the user environment, type=list, default="", group=build
+if (DEFINED ENV{PICO_BOARD_HEADER_DIRS})
+    set(PICO_BOARD_HEADER_DIRS $ENV{PICO_BOARD_HEADER_DIRS})
+    message("Using PICO_BOARD_HEADER_DIRS from environment ('${PICO_BOARD_HEADER_DIRS}')")
+endif()
+set(PICO_BOARD_HEADER_DIRS ${PICO_BOARD_HEADER_DIRS} CACHE STRING "PICO board header directories")
+
+list(APPEND PICO_BOARD_HEADER_DIRS ${CMAKE_CURRENT_LIST_DIR}/include/boards)
+pico_find_in_paths(PICO_BOARD_HEADER_FILE PICO_BOARD_HEADER_DIRS ${PICO_BOARD}.h)
+
+if (EXISTS ${PICO_BOARD_HEADER_FILE})
+    message("Using board configuration from ${PICO_BOARD_HEADER_FILE}")
+    list(APPEND PICO_CONFIG_HEADER_FILES ${PICO_BOARD_HEADER_FILE})
+else()
+    set(msg "Unable to find definition of board '${PICO_BOARD}' (specified by PICO_BOARD):\n")
+    list(JOIN PICO_BOARD_HEADER_DIRS ", " DIRS)
+    string(CONCAT msg ${msg} "   Looked for ${PICO_BOARD}.h in ${DIRS} (additional paths specified by PICO_BOARD_HEADER_DIRS)\n")
+    list(JOIN PICO_BOARD_CMAKE_DIRS ", " DIRS)
+    string(CONCAT msg ${msg} "   Looked for ${PICO_BOARD}.cmake in ${DIRS} (additional paths specified by PICO_BOARD_CMAKE_DIRS)")
+    message(FATAL_ERROR ${msg})
+endif()
diff --git a/src/boards/include/boards/adafruit_feather_rp2040.h b/src/boards/include/boards/adafruit_feather_rp2040.h
new file mode 100644
index 0000000..2da8e70
--- /dev/null
+++ b/src/boards/include/boards/adafruit_feather_rp2040.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_ADAFRUIT_FEATHER_RP2040_H
+#define _BOARDS_ADAFRUIT_FEATHER_RP2040_H
+
+// For board detection
+#define ADAFRUIT_FEATHER_RP2040
+
+// On some samples, the xosc can take longer to stabilize than is usual
+#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER
+#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64
+#endif
+
+//------------- UART -------------//
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+//------------- LED -------------//
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 13
+#endif
+
+#ifndef PICO_DEFAULT_WS2812_PIN
+#define PICO_DEFAULT_WS2812_PIN 16
+#endif
+
+//------------- I2C -------------//
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 2
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 3
+#endif
+
+//------------- SPI -------------//
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 20
+#endif
+
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+
+//------------- FLASH -------------//
+
+// Use slower generic flash access
+#define PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 4
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/adafruit_itsybitsy_rp2040.h b/src/boards/include/boards/adafruit_itsybitsy_rp2040.h
new file mode 100644
index 0000000..f9d27e9
--- /dev/null
+++ b/src/boards/include/boards/adafruit_itsybitsy_rp2040.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_ADAFRUIT_ITSYBITSY_RP2040_H
+#define _BOARDS_ADAFRUIT_ITSYBITSY_RP2040_H
+
+// For board detection
+#define ADAFRUIT_ITSYBITSY_RP2040
+
+// On some samples, the xosc can take longer to stabilize than is usual
+#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER
+#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64
+#endif
+
+//------------- UART -------------//
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+//------------- LED -------------//
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 11
+#endif
+
+#ifndef PICO_DEFAULT_WS2812_PIN
+#define PICO_DEFAULT_WS2812_PIN 17
+#endif
+
+#ifndef PICO_DEFAULT_WS2812_POWER_PIN
+#define PICO_DEFAULT_WS2812_POWER_PIN 16
+#endif
+
+//------------- I2C -------------//
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 2
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 3
+#endif
+
+//------------- SPI -------------//
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 20
+#endif
+
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+
+//------------- FLASH -------------//
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/adafruit_qtpy_rp2040.h b/src/boards/include/boards/adafruit_qtpy_rp2040.h
new file mode 100644
index 0000000..24184c2
--- /dev/null
+++ b/src/boards/include/boards/adafruit_qtpy_rp2040.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_ADAFRUIT_QTPY_RP2040_H
+#define _BOARDS_ADAFRUIT_QTPY_RP2040_H
+
+// For board detection
+#define ADAFRUIT_QTPY_RP2040
+
+// On some samples, the xosc can take longer to stabilize than is usual
+#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER
+#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64
+#endif
+
+//------------- UART -------------//
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 1
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 20
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 5
+#endif
+
+//------------- LED -------------//
+// No normal LED
+// #define PICO_DEFAULT_LED_PIN 13
+
+#ifndef PICO_DEFAULT_WS2812_PIN
+#define PICO_DEFAULT_WS2812_PIN 12
+#endif
+
+#ifndef PICO_DEFAULT_WS2812_POWER_PIN
+#define PICO_DEFAULT_WS2812_POWER_PIN 11
+#endif
+
+//------------- I2C -------------//
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 24
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 25
+#endif
+
+//------------- SPI -------------//
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 3
+#endif
+
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 4
+#endif
+
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 6
+#endif
+
+//------------- FLASH -------------//
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/adafruit_trinkey_qt2040.h b/src/boards/include/boards/adafruit_trinkey_qt2040.h
new file mode 100644
index 0000000..f9b49df
--- /dev/null
+++ b/src/boards/include/boards/adafruit_trinkey_qt2040.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_ADAFRUIT_TRINKEY_QT2040_H
+#define _BOARDS_ADAFRUIT_TRINKEY_QT2040_H
+
+// For board detection
+#define ADAFRUIT_TRINKEY_QT2040
+
+// On some samples, the xosc can take longer to stabilize than is usual
+#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER
+#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64
+#endif
+
+//------------- UART -------------//
+// no PICO_DEFAULT_UART
+// no PICO_DEFAULT_UART_TX_PIN
+// no PICO_DEFAULT_UART_RX_PIN
+
+//------------- LED -------------//
+// No normal LED
+// #define PICO_DEFAULT_LED_PIN 13
+
+#ifndef PICO_DEFAULT_WS2812_PIN
+#define PICO_DEFAULT_WS2812_PIN 27
+#endif
+
+//------------- I2C -------------//
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 16
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 17
+#endif
+
+//------------- SPI -------------//
+// no PICO_DEFAULT_SPI
+// no PICO_DEFAULT_SPI_SCK_PIN
+// no PICO_DEFAULT_SPI_TX_PIN
+// no PICO_DEFAULT_SPI_RX_PIN
+// no PICO_DEFAULT_SPI_CSN_PIN
+
+//------------- FLASH -------------//
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/arduino_nano_rp2040_connect.h b/src/boards/include/boards/arduino_nano_rp2040_connect.h
new file mode 100644
index 0000000..39c6564
--- /dev/null
+++ b/src/boards/include/boards/arduino_nano_rp2040_connect.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_ARDUINO_NANO_RP2040_CONNECT_H
+#define _BOARDS_ARDUINO_NANO_RP2040_CONNECT_H
+
+// For board detection
+#define ARDUINO_NANO_RP2040_CONNECT
+
+//------------- UART -------------//
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+//------------- LED -------------//
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 6
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+//------------- I2C -------------//
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 12
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 13
+#endif
+
+//------------- SPI -------------//
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 7
+#endif
+
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 4
+#endif
+
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 6
+#endif
+
+//------------- FLASH -------------//
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/melopero_shake_rp2040.h b/src/boards/include/boards/melopero_shake_rp2040.h
new file mode 100644
index 0000000..d07ca61
--- /dev/null
+++ b/src/boards/include/boards/melopero_shake_rp2040.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_MELOPERO_SHAKE_RP2040_H
+#define _BOARDS_MELOPERO_SHAKE_RP2040_H
+
+// For board detection
+#define MELOPERO_SHAKE_RP2040
+
+//------------- UART -------------//
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 1
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 8
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 9
+#endif
+
+//------------- LED -------------//
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 13
+#endif
+
+#ifndef PICO_DEFAULT_WS2812_PIN
+#define PICO_DEFAULT_WS2812_PIN 16
+#endif
+
+//------------- I2C -------------//
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 2
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 3
+#endif
+
+//------------- SPI -------------//
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 20
+#endif
+
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 1
+#endif
+
+//------------- FLASH -------------//
+
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/none.h b/src/boards/include/boards/none.h
new file mode 100644
index 0000000..236c395
--- /dev/null
+++ b/src/boards/include/boards/none.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_NONE_H
+#define _BOARDS_NONE_H
+
+#endif
\ No newline at end of file
diff --git a/src/boards/include/boards/pico.h b/src/boards/include/boards/pico.h
new file mode 100644
index 0000000..9e7f537
--- /dev/null
+++ b/src/boards/include/boards/pico.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+// This header may be included by other board headers as "boards/pico.h"
+
+#ifndef _BOARDS_PICO_H
+#define _BOARDS_PICO_H
+
+// For board detection
+#define RASPBERRYPI_PICO
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 25
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 4
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 5
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
+#define PICO_SMPS_MODE_PIN 23
+
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 1
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pimoroni_interstate75.h b/src/boards/include/boards/pimoroni_interstate75.h
new file mode 100644
index 0000000..e2621b0
--- /dev/null
+++ b/src/boards/include/boards/pimoroni_interstate75.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_INTERSTATE75_H
+#define _BOARDS_PIMORONI_INTERSTATE75_H
+
+// For board detection
+#define PIMORONI_INTERSTATE75
+
+// --- BOARD SPECIFIC ---
+#ifndef INTERSTATE75_R0_PIN
+#define INTERSTATE75_R0_PIN 0
+#endif
+
+#ifndef INTERSTATE75_G0_PIN
+#define INTERSTATE75_G0_PIN 1
+#endif
+
+#ifndef INTERSTATE75_B0_PIN
+#define INTERSTATE75_B0_PIN 2
+#endif
+
+#ifndef INTERSTATE75_R1_PIN
+#define INTERSTATE75_R1_PIN 3
+#endif
+
+#ifndef INTERSTATE75_G1_PIN
+#define INTERSTATE75_G1_PIN 4
+#endif
+
+#ifndef INTERSTATE75_B1_PIN
+#define INTERSTATE75_B1_PIN 5
+#endif
+
+#ifndef INTERSTATE75_ROW_A_PIN
+#define INTERSTATE75_ROW_A_PIN 6
+#endif
+
+#ifndef INTERSTATE75_ROW_B_PIN
+#define INTERSTATE75_ROW_B_PIN 7
+#endif
+
+#ifndef INTERSTATE75_ROW_C_PIN
+#define INTERSTATE75_ROW_C_PIN 8
+#endif
+
+#ifndef INTERSTATE75_ROW_D_PIN
+#define INTERSTATE75_ROW_D_PIN 9
+#endif
+
+#ifndef INTERSTATE75_ROW_E_PIN
+#define INTERSTATE75_ROW_E_PIN 10
+#endif
+
+#ifndef INTERSTATE75_CLK_PIN
+#define INTERSTATE75_CLK_PIN 11
+#endif
+
+#ifndef INTERSTATE75_LAT_PIN
+#define INTERSTATE75_LAT_PIN 12
+#endif
+
+#ifndef INTERSTATE75_OE_PIN
+#define INTERSTATE75_OE_PIN 13
+#endif
+
+#ifndef INTERSTATE75_SW_A_PIN
+#define INTERSTATE75_SW_A_PIN 14
+#endif
+
+#ifndef INTERSTATE75_LED_R_PIN
+#define INTERSTATE75_LED_R_PIN 16
+#endif
+
+#ifndef INTERSTATE75_LED_G_PIN
+#define INTERSTATE75_LED_G_PIN 17
+#endif
+
+#ifndef INTERSTATE75_LED_B_PIN
+#define INTERSTATE75_LED_B_PIN 18
+#endif
+
+#ifndef INTERSTATE75_I2C
+#define INTERSTATE75_I2C 0
+#endif
+
+#ifndef INTERSTATE75_INT_PIN
+#define INTERSTATE75_INT_PIN 19
+#endif
+
+#ifndef INTERSTATE75_SDA_PIN
+#define INTERSTATE75_SDA_PIN 20
+#endif
+
+#ifndef INTERSTATE75_SCL_PIN
+#define INTERSTATE75_SCL_PIN 21
+#endif
+
+#ifndef INTERSTATE75_USER_SW_PIN
+#define INTERSTATE75_USER_SW_PIN 23
+#endif
+
+#ifndef INTERSTATE75_A0_PIN
+#define INTERSTATE75_A0_PIN 26
+#endif
+
+#ifndef INTERSTATE75_A1_PIN
+#define INTERSTATE75_A1_PIN 27
+#endif
+
+#ifndef INTERSTATE75_A2_PIN
+#define INTERSTATE75_A2_PIN 28
+#endif
+
+#ifndef INTERSTATE75_NUM_ADC_PINS
+#define INTERSTATE75_NUM_ADC_PINS 3
+#endif
+
+#ifndef INTERSTATE75_CURRENT_SENSE_PIN
+#define INTERSTATE75_CURRENT_SENSE_PIN 29
+#endif
+
+// --- UART ---
+// no PICO_DEFAULT_UART
+// no PICO_DEFAULT_UART_TX_PIN
+// no PICO_DEFAULT_UART_RX_PIN
+
+// --- LED ---
+// Included so basic examples will work, and set it to the green LED
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN INTERSTATE75_LED_G_PIN
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+#ifndef PICO_DEFAULT_LED_PIN_INVERTED
+#define PICO_DEFAULT_LED_PIN_INVERTED 1
+#endif
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C INTERSTATE75_I2C
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN INTERSTATE75_SDA_PIN
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN INTERSTATE75_SCL_PIN
+#endif
+
+// --- SPI ---
+// no PICO_DEFAULT_SPI
+// no PICO_DEFAULT_SPI_SCK_PIN
+// no PICO_DEFAULT_SPI_TX_PIN
+// no PICO_DEFAULT_SPI_RX_PIN
+// no PICO_DEFAULT_SPI_CSN_PIN
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pimoroni_keybow2040.h b/src/boards/include/boards/pimoroni_keybow2040.h
new file mode 100644
index 0000000..43772e8
--- /dev/null
+++ b/src/boards/include/boards/pimoroni_keybow2040.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_KEYBOW2040_H
+#define _BOARDS_PIMORONI_KEYBOW2040_H
+
+// For board detection
+#define PIMORONI_KEYBOW2040
+
+// --- BOARD SPECIFIC ---
+#ifndef KEYBOW2040_I2C_SDA_PIN
+#define KEYBOW2040_I2C_SDA_PIN 4
+#endif
+
+#ifndef KEYBOW2040_I2C_SCL_PIN
+#define KEYBOW2040_I2C_SCL_PIN 5
+#endif
+
+#ifndef KEYBOW2040_I2C_INT_PIN
+#define KEYBOW2040_I2C_INT_PIN 3
+#endif
+
+#ifndef KEYBOW2040_USER_SW_PIN
+#define KEYBOW2040_USER_SW_PIN 23
+#endif
+
+#ifndef KEYBOW2040_SW0_PIN
+#define KEYBOW2040_SW0_PIN 21
+#endif
+
+#ifndef KEYBOW2040_SW1_PIN
+#define KEYBOW2040_SW1_PIN 20
+#endif
+
+#ifndef KEYBOW2040_SW2_PIN
+#define KEYBOW2040_SW2_PIN 19
+#endif
+
+#ifndef KEYBOW2040_SW3_PIN
+#define KEYBOW2040_SW3_PIN 18
+#endif
+
+#ifndef KEYBOW2040_SW4_PIN
+#define KEYBOW2040_SW4_PIN 17
+#endif
+
+#ifndef KEYBOW2040_SW5_PIN
+#define KEYBOW2040_SW5_PIN 16
+#endif
+
+#ifndef KEYBOW2040_SW6_PIN
+#define KEYBOW2040_SW6_PIN 15
+#endif
+
+#ifndef KEYBOW2040_SW7_PIN
+#define KEYBOW2040_SW7_PIN 14
+#endif
+
+#ifndef KEYBOW2040_SW8_PIN
+#define KEYBOW2040_SW8_PIN 13
+#endif
+
+#ifndef KEYBOW2040_SW9_PIN
+#define KEYBOW2040_SW9_PIN 12
+#endif
+
+#ifndef KEYBOW2040_SW10_PIN
+#define KEYBOW2040_SW10_PIN 11
+#endif
+
+#ifndef KEYBOW2040_SW11_PIN
+#define KEYBOW2040_SW11_PIN 10
+#endif
+
+#ifndef KEYBOW2040_SW12_PIN
+#define KEYBOW2040_SW12_PIN 9
+#endif
+
+#ifndef KEYBOW2040_SW13_PIN
+#define KEYBOW2040_SW13_PIN 8
+#endif
+
+#ifndef KEYBOW2040_SW14_PIN
+#define KEYBOW2040_SW14_PIN 7
+#endif
+
+#ifndef KEYBOW2040_SW15_PIN
+#define KEYBOW2040_SW15_PIN 6
+#endif
+
+#ifndef KEYBOW2040_NUM_SWITCHES_PINS
+#define KEYBOW2040_NUM_SWITCHES_PINS 16
+#endif
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+// no PICO_DEFAULT_LED_PIN
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN KEYBOW2040_I2C_SDA_PIN
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN KEYBOW2040_I2C_SCL_PIN
+#endif
+
+// --- SPI ---
+// no PICO_DEFAULT_SPI
+// no PICO_DEFAULT_SPI_SCK_PIN
+// no PICO_DEFAULT_SPI_TX_PIN
+// no PICO_DEFAULT_SPI_RX_PIN
+// no PICO_DEFAULT_SPI_CSN_PIN
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pimoroni_pga2040.h b/src/boards/include/boards/pimoroni_pga2040.h
new file mode 100644
index 0000000..980f168
--- /dev/null
+++ b/src/boards/include/boards/pimoroni_pga2040.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_PGA2040_H
+#define _BOARDS_PIMORONI_PGA2040_H
+
+// For board detection
+#define PIMORONI_PGA2040
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+// no PICO_DEFAULT_LED_PIN
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 4
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 5
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pimoroni_picolipo_16mb.h b/src/boards/include/boards/pimoroni_picolipo_16mb.h
new file mode 100644
index 0000000..338977b
--- /dev/null
+++ b/src/boards/include/boards/pimoroni_picolipo_16mb.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_PICOLIPO_16MB_H
+#define _BOARDS_PIMORONI_PICOLIPO_16MB_H
+
+// For board detection
+#define PIMORONI_PICOLIPO_16MB
+
+// --- BOARD SPECIFIC ---
+#ifndef PICOLIPO_USER_SW_PIN
+#define PICOLIPO_USER_SW_PIN 23
+#endif
+
+#ifndef PICOLIPO_VBUS_DETECT_PIN
+#define PICOLIPO_VBUS_DETECT_PIN 24
+#endif
+
+#ifndef PICOLIPO_BAT_SENSE_PIN
+#define PICOLIPO_BAT_SENSE_PIN 29
+#endif
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 25
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 4
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 5
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pimoroni_picolipo_4mb.h b/src/boards/include/boards/pimoroni_picolipo_4mb.h
new file mode 100644
index 0000000..871ed83
--- /dev/null
+++ b/src/boards/include/boards/pimoroni_picolipo_4mb.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_PICOLIPO_4MB_H
+#define _BOARDS_PIMORONI_PICOLIPO_4MB_H
+
+// For board detection
+#define PIMORONI_PICOLIPO_4MB
+
+// --- BOARD SPECIFIC ---
+#ifndef PICOLIPO_USER_SW_PIN
+#define PICOLIPO_USER_SW_PIN 23
+#endif
+
+#ifndef PICOLIPO_VBUS_DETECT_PIN
+#define PICOLIPO_VBUS_DETECT_PIN 24
+#endif
+
+#ifndef PICOLIPO_BAT_SENSE_PIN
+#define PICOLIPO_BAT_SENSE_PIN 29
+#endif
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 25
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 4
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 5
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pimoroni_picosystem.h b/src/boards/include/boards/pimoroni_picosystem.h
new file mode 100644
index 0000000..1e7c80e
--- /dev/null
+++ b/src/boards/include/boards/pimoroni_picosystem.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_PICOSYSTEM_H
+#define _BOARDS_PIMORONI_PICOSYSTEM_H
+
+// For board detection
+#define PIMORONI_PICOSYSTEM
+
+// --- BOARD SPECIFIC ---
+#ifndef PICOSYSTEM_VBUS_DETECT_PIN
+#define PICOSYSTEM_VBUS_DETECT_PIN 2
+#endif
+
+#ifndef PICOSYSTEM_LCD_SPI
+#define PICOSYSTEM_LCD_SPI 0
+#endif
+
+#ifndef PICOSYSTEM_LCD_RESET_PIN
+#define PICOSYSTEM_LCD_RESET_PIN 4
+#endif
+
+#ifndef PICOSYSTEM_LCD_CSN_PIN
+#define PICOSYSTEM_LCD_CSN_PIN 5
+#endif
+
+#ifndef PICOSYSTEM_LCD_SCLK_PIN
+#define PICOSYSTEM_LCD_SCLK_PIN 6
+#endif
+
+#ifndef PICOSYSTEM_LCD_MOSI_PIN
+#define PICOSYSTEM_LCD_MOSI_PIN 7
+#endif
+
+#ifndef PICOSYSTEM_LCD_VSYNC_PIN
+#define PICOSYSTEM_LCD_VSYNC_PIN 8
+#endif
+
+#ifndef PICOSYSTEM_LCD_DC_PIN
+#define PICOSYSTEM_LCD_DC_PIN 9
+#endif
+
+#ifndef PICOSYSTEM_AUDIO_PIN
+#define PICOSYSTEM_AUDIO_PIN 11
+#endif
+
+#ifndef PICOSYSTEM_BACKLIGHT_PIN
+#define PICOSYSTEM_BACKLIGHT_PIN 12
+#endif
+
+#ifndef PICOSYSTEM_LED_G_PIN
+#define PICOSYSTEM_LED_G_PIN 13
+#endif
+
+#ifndef PICOSYSTEM_LED_R_PIN
+#define PICOSYSTEM_LED_R_PIN 14
+#endif
+
+#ifndef PICOSYSTEM_LED_B_PIN
+#define PICOSYSTEM_LED_B_PIN 15
+#endif
+
+#ifndef PICOSYSTEM_SW_Y_PIN
+#define PICOSYSTEM_SW_Y_PIN 16
+#endif
+
+#ifndef PICOSYSTEM_SW_X_PIN
+#define PICOSYSTEM_SW_X_PIN 17
+#endif
+
+#ifndef PICOSYSTEM_SW_A_PIN
+#define PICOSYSTEM_SW_A_PIN 18
+#endif
+
+#ifndef PICOSYSTEM_SW_B_PIN
+#define PICOSYSTEM_SW_B_PIN 19
+#endif
+
+#ifndef PICOSYSTEM_SW_DOWN_PIN
+#define PICOSYSTEM_SW_DOWN_PIN 20
+#endif
+
+#ifndef PICOSYSTEM_SW_RIGHT_PIN
+#define PICOSYSTEM_SW_RIGHT_PIN 21
+#endif
+
+#ifndef PICOSYSTEM_SW_LEFT_PIN
+#define PICOSYSTEM_SW_LEFT_PIN 22
+#endif
+
+#ifndef PICOSYSTEM_SW_UP_PIN
+#define PICOSYSTEM_SW_UP_PIN 23
+#endif
+
+#ifndef PICOSYSTEM_CHARGE_STAT_PIN
+#define PICOSYSTEM_CHARGE_STAT_PIN 24
+#endif
+
+#ifndef PICOSYSTEM_BAT_SENSE_PIN
+#define PICOSYSTEM_BAT_SENSE_PIN 26
+#endif
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+// Included so basic examples will work, and set it to the green LED
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN PICOSYSTEM_LED_G_PIN
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+#ifndef PICO_DEFAULT_LED_PIN_INVERTED
+#define PICO_DEFAULT_LED_PIN_INVERTED 1
+#endif
+
+// --- I2C ---
+//no PICO_DEFAULT_I2C
+//no PICO_DEFAULT_I2C_SDA_PIN
+//no PICO_DEFAULT_I2C_SCL_PIN
+
+// --- SPI ---
+// no PICO_DEFAULT_SPI
+// no PICO_DEFAULT_SPI_SCK_PIN
+// no PICO_DEFAULT_SPI_TX_PIN
+// no PICO_DEFAULT_SPI_RX_PIN
+// no PICO_DEFAULT_SPI_CSN_PIN
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pimoroni_plasma2040.h b/src/boards/include/boards/pimoroni_plasma2040.h
new file mode 100644
index 0000000..226aaf5
--- /dev/null
+++ b/src/boards/include/boards/pimoroni_plasma2040.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_PLASMA2040_H
+#define _BOARDS_PIMORONI_PLASMA2040_H
+
+// For board detection
+#define PIMORONI_PLASMA2040
+
+// --- BOARD SPECIFIC ---
+#ifndef PLASMA2040_SW_A_PIN
+#define PLASMA2040_SW_A_PIN 12
+#endif
+
+#ifndef PLASMA2040_SW_B_PIN
+#define PLASMA2040_SW_B_PIN 13
+#endif
+
+#ifndef PLASMA2040_CLK_PIN
+#define PLASMA2040_CLK_PIN 14
+#endif
+
+#ifndef PLASMA2040_DATA_PIN
+#define PLASMA2040_DATA_PIN 15
+#endif
+
+#ifndef PLASMA2040_LED_R_PIN
+#define PLASMA2040_LED_R_PIN 16
+#endif
+
+#ifndef PLASMA2040_LED_G_PIN
+#define PLASMA2040_LED_G_PIN 17
+#endif
+
+#ifndef PLASMA2040_LED_B_PIN
+#define PLASMA2040_LED_B_PIN 18
+#endif
+
+#ifndef PLASMA2040_I2C
+#define PLASMA2040_I2C 0
+#endif
+
+#ifndef PLASMA2040_INT_PIN
+#define PLASMA2040_INT_PIN 19
+#endif
+
+#ifndef PLASMA2040_SDA_PIN
+#define PLASMA2040_SDA_PIN 20
+#endif
+
+#ifndef PLASMA2040_SCL_PIN
+#define PLASMA2040_SCL_PIN 21
+#endif
+
+#ifndef PLASMA2040_USER_SW_PIN
+#define PLASMA2040_USER_SW_PIN 23
+#endif
+
+#ifndef PLASMA2040_A0_PIN
+#define PLASMA2040_A0_PIN 26
+#endif
+
+#ifndef PLASMA2040_A1_PIN
+#define PLASMA2040_A1_PIN 27
+#endif
+
+#ifndef PLASMA2040_A2_PIN
+#define PLASMA2040_A2_PIN 28
+#endif
+
+#ifndef PLASMA2040_NUM_ADC_PINS
+#define PLASMA2040_NUM_ADC_PINS 3
+#endif
+
+#ifndef PLASMA2040_CURRENT_SENSE_PIN
+#define PLASMA2040_CURRENT_SENSE_PIN 29
+#endif
+
+// --- UART ---
+// no PICO_DEFAULT_UART
+// no PICO_DEFAULT_UART_TX_PIN
+// no PICO_DEFAULT_UART_RX_PIN
+
+// --- LED ---
+// Included so basic examples will work, and set it to the green LED
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN PLASMA2040_LED_G_PIN
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+#ifndef PICO_DEFAULT_LED_PIN_INVERTED
+#define PICO_DEFAULT_LED_PIN_INVERTED 1
+#endif
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C PLASMA2040_I2C
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN PLASMA2040_SDA_PIN
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN PLASMA2040_SCL_PIN
+#endif
+
+// --- SPI ---
+// no PICO_DEFAULT_SPI
+// no PICO_DEFAULT_SPI_SCK_PIN
+// no PICO_DEFAULT_SPI_TX_PIN
+// no PICO_DEFAULT_SPI_RX_PIN
+// no PICO_DEFAULT_SPI_CSN_PIN
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pimoroni_tiny2040.h b/src/boards/include/boards/pimoroni_tiny2040.h
new file mode 100644
index 0000000..51d17f6
--- /dev/null
+++ b/src/boards/include/boards/pimoroni_tiny2040.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PIMORONI_TINY2040_H
+#define _BOARDS_PIMORONI_TINY2040_H
+
+// For board detection
+#define PIMORONI_TINY2040
+
+// --- BOARD SPECIFIC ---
+#ifndef TINY2040_LED_R_PIN
+#define TINY2040_LED_R_PIN 18
+#endif
+
+#ifndef TINY2040_LED_G_PIN
+#define TINY2040_LED_G_PIN 19
+#endif
+
+#ifndef TINY2040_LED_B_PIN
+#define TINY2040_LED_B_PIN 20
+#endif
+
+#ifndef TINY2040_USER_SW_PIN
+#define TINY2040_USER_SW_PIN 23
+#endif
+
+#ifndef TINY2040_A0_PIN
+#define TINY2040_A0_PIN 26
+#endif
+
+#ifndef TINY2040_A1_PIN
+#define TINY2040_A1_PIN 27
+#endif
+
+#ifndef TINY2040_A2_PIN
+#define TINY2040_A2_PIN 28
+#endif
+
+#ifndef TINY2040_A3_PIN
+#define TINY2040_A3_PIN 29
+#endif
+
+#ifndef TINY2040_NUM_IO_PINS
+#define TINY2040_NUM_IO_PINS 8
+#endif
+
+#ifndef TINY2040_NUM_ADC_PINS
+#define TINY2040_NUM_ADC_PINS 4
+#endif
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+// Included so basic examples will work, and set it to the green LED
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN TINY2040_LED_G_PIN
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+#ifndef PICO_DEFAULT_LED_PIN_INVERTED
+#define PICO_DEFAULT_LED_PIN_INVERTED 1
+#endif
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 2
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 3
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 6
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 7
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 4
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 5
+#endif
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/pybstick26_rp2040.h b/src/boards/include/boards/pybstick26_rp2040.h
new file mode 100644
index 0000000..8a9ca41
--- /dev/null
+++ b/src/boards/include/boards/pybstick26_rp2040.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_PYBSTICK26_RP2040_H
+#define _BOARDS_PYBSTICK26_RP2040_H
+
+// For board detection
+#define PYBSTICK26_RP2040
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 23
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1 
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 6
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 7 
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 1
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 10
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 11
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 8
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 9
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2 
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (1 * 1024 * 1024)
+#endif
+
+// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
+// Linear regulator on Pybstick26
+//#define PICO_SMPS_MODE_PIN 23
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif
+// of #define _BOARDS_PYBSTICK26_RP2040_H
diff --git a/src/boards/include/boards/sparkfun_micromod.h b/src/boards/include/boards/sparkfun_micromod.h
new file mode 100644
index 0000000..0c6e568
--- /dev/null
+++ b/src/boards/include/boards/sparkfun_micromod.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+//
+//------------------------------------------------------------------------------------------
+// Board definition for the SparkFun RP2040 MicroMod processor board
+//
+// This header may be included by other board headers as "boards/sparkfun_micromod.h"
+
+#ifndef _BOARDS_SPARKFUN_MICROMOD_H
+#define _BOARDS_SPARKFUN_MICROMOD_H
+
+// For board detection
+#define SPARKFUN_MICROMOD
+
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 25
+#endif
+
+// Default I2C - for qwiic connector
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C       0
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN   4
+#endif
+
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN   5
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 22
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 23
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 20
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 21
+#endif
+
+// spi flash
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/sparkfun_promicro.h b/src/boards/include/boards/sparkfun_promicro.h
new file mode 100644
index 0000000..45bb4a2
--- /dev/null
+++ b/src/boards/include/boards/sparkfun_promicro.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+//
+//------------------------------------------------------------------------------------------
+// Board definition for the SparkFun RP2040 ProMicro
+//
+// This header may be included by other board headers as "boards/sparkfun_promicro.h"
+
+#ifndef _BOARDS_SPARKFUN_PROMICRO_H
+#define _BOARDS_SPARKFUN_PROMICRO_H
+
+// For board detection
+#define SPARKFUN_PROMICRO
+
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// The PRO Micro doesnt have a plain LED, but a WS2812
+//#ifndef PICO_DEFAULT_LED_PIN
+//#define PICO_DEFAULT_LED_PIN   25
+//#endif
+#ifndef PICO_DEFAULT_WS2812_PIN
+#define PICO_DEFAULT_WS2812_PIN 25
+#endif
+
+// Default I2C - for the onboard qwiic connector
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C       0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN   16
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN   17
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 22
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 23
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 20
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 21
+#endif
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+// board has 16M onboard flash
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/sparkfun_thingplus.h b/src/boards/include/boards/sparkfun_thingplus.h
new file mode 100644
index 0000000..d1e69d5
--- /dev/null
+++ b/src/boards/include/boards/sparkfun_thingplus.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+//
+//------------------------------------------------------------------------------------------
+// Board definition for the SparkFun RP2040 Thing Plus
+//
+// This header may be included by other board headers as "boards/sparkfun_thingplus.h"
+
+#ifndef _BOARDS_SPARKFUN_THINGPLUS_H
+#define _BOARDS_SPARKFUN_THINGPLUS_H
+
+// For board detection
+#define SPARKFUN_THINGPLUS
+
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 25
+#endif
+
+// Default I2C - for qwiic connector
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C       1
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN   6
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN   7
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 2
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 3
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 4
+#endif
+
+
+// spi flash
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+// The thing plus has a SD Card.
+#define PICO_SD_CLK_PIN   14
+#define PICO_SD_CMD_PIN   15
+#define PICO_SD_DAT0_PIN  12
+// DAT pins count down
+#define PICO_SD_DAT_PIN_INCREMENT -1
+
+#ifndef PICO_SD_DAT_PIN_COUNT
+#define PICO_SD_DAT_PIN_COUNT 4
+#endif
+
+// All boards have B1 RP2040
+
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/vgaboard.h b/src/boards/include/boards/vgaboard.h
new file mode 100644
index 0000000..f0b6f0e
--- /dev/null
+++ b/src/boards/include/boards/vgaboard.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+#ifndef _BOARDS_VGABOARD_H
+#define _BOARDS_VGABOARD_H
+
+// For board detection
+#define RASPBERRYPI_VGABOARD
+
+// Audio pins. I2S BCK, LRCK are on the same pins as PWM L/R.
+// - When outputting I2S, PWM sees BCK and LRCK, which should sound silent as
+//   they are constant duty cycle, and above the filter cutoff
+// - When outputting PWM, I2S DIN should be low, so I2S should remain silent.
+#define VGABOARD_I2S_DIN_PIN 26
+#define VGABOARD_I2S_BCK_PIN 27
+#define VGABOARD_I2S_LRCK_PIN 28
+
+#define VGABOARD_PWM_L_PIN 28
+#define VGABOARD_PWM_R_PIN 27
+
+#define VGABOARD_VGA_COLOR_PIN_BASE 0
+#define VGABOARD_VGA_SYNC_PIN_BASE 16
+
+// Note DAT1/2 are shared with UART TX/RX (pull jumpers off header to access
+// UART pins and disconnect SD DAT1/2)
+#define VGABOARD_SD_CLK_PIN 5
+#define VGABOARD_SD_CMD_PIN 18
+#define VGABOARD_SD_DAT0_PIN 19
+
+// Note buttons are shared with VGA colour LSBs -- if using VGA, you can float
+// the pin on VSYNC assertion and sample on VSYNC deassertion
+#define VGABOARD_BUTTON_A_PIN 0
+#define VGABOARD_BUTTON_B_PIN 6
+#define VGABOARD_BUTTON_C_PIN 11
+
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 1
+#endif
+
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 20
+#endif
+
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 21
+#endif
+
+#define PICO_SCANVIDEO_COLOR_PIN_BASE VGABOARD_VGA_COLOR_PIN_BASE
+#define PICO_SCANVIDEO_SYNC_PIN_BASE VGABOARD_VGA_SYNC_PIN_BASE
+
+#define PICO_SD_CLK_PIN VGABOARD_SD_CLK_PIN
+#define PICO_SD_CMD_PIN VGABOARD_SD_CMD_PIN
+#define PICO_SD_DAT0_PIN VGABOARD_SD_DAT0_PIN
+
+// 1 or 4
+#ifndef PICO_SD_DAT_PIN_COUNT
+#define PICO_SD_DAT_PIN_COUNT 4
+#endif
+
+// 1 or -1
+#define PICO_SD_DAT_PIN_INCREMENT 1
+
+#define PICO_AUDIO_I2S_DATA_PIN VGABOARD_I2S_DIN_PIN
+#define PICO_AUDIO_I2S_CLOCK_PIN_BASE VGABOARD_I2S_BCK_PIN
+
+#define PICO_AUDIO_PWM_L_PIN VGABOARD_PWM_L_PIN
+#define PICO_AUDIO_PWM_R_PIN VGABOARD_PWM_R_PIN
+
+#define PICO_VGA_BOARD
+
+// vgaboard has a Pico on it, so default anything we haven't set above
+#include "boards/pico.h"
+
+#endif
diff --git a/src/boards/include/boards/waveshare_rp2040_lcd_0.96.h b/src/boards/include/boards/waveshare_rp2040_lcd_0.96.h
new file mode 100644
index 0000000..8c59c5c
--- /dev/null
+++ b/src/boards/include/boards/waveshare_rp2040_lcd_0.96.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+
+#ifndef _BOARDS_WAVESHARE_RP2040_LCD_0_96_H
+#define _BOARDS_WAVESHARE_RP2040_LCD_0_96_H
+
+// For board detection
+#define WAVESHARE_RP2040_LCD_0_96
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 4
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 5
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- LCD ---
+#ifndef WAVESHARE_RP2040_LCD_SPI
+#define WAVESHARE_RP2040_LCD_SPI 1
+#endif
+#ifndef WAVESHARE_RP2040_LCD_DC_PIN
+#define WAVESHARE_RP2040_LCD_DC_PIN 8
+#endif
+#ifndef WAVESHARE_RP2040_LCD_CS_PIN
+#define WAVESHARE_RP2040_LCD_CS_PIN 9
+#endif
+#ifndef WAVESHARE_RP2040_LCD_SCLK_PIN
+#define WAVESHARE_RP2040_LCD_SCLK_PIN 10
+#endif
+#ifndef WAVESHARE_RP2040_LCD_TX_PIN
+#define WAVESHARE_RP2040_LCD_TX_PIN 11
+#endif
+#ifndef WAVESHARE_RP2040_LCD_RST_PIN
+#define WAVESHARE_RP2040_LCD_RST_PIN 12
+#endif
+#ifndef WAVESHARE_RP2040_LCD_BL_PIN
+#define WAVESHARE_RP2040_LCD_BL_PIN 25
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
+#define PICO_SMPS_MODE_PIN 23
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif
+
diff --git a/src/boards/include/boards/waveshare_rp2040_plus_16mb.h b/src/boards/include/boards/waveshare_rp2040_plus_16mb.h
new file mode 100644
index 0000000..6f5e144
--- /dev/null
+++ b/src/boards/include/boards/waveshare_rp2040_plus_16mb.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+
+#ifndef _BOARDS_WAVESHARE_RP2040_PLUS_16MB_H
+#define _BOARDS_WAVESHARE_RP2040_PLUS_16MB_H
+
+// For board detection
+#define WAVESHARE_RP2040_PLUS_16MB
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 25
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 6
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 7
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
+#endif
+
+// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
+#define PICO_SMPS_MODE_PIN 23
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/waveshare_rp2040_plus_4mb.h b/src/boards/include/boards/waveshare_rp2040_plus_4mb.h
new file mode 100644
index 0000000..d8dd8f6
--- /dev/null
+++ b/src/boards/include/boards/waveshare_rp2040_plus_4mb.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+
+#ifndef _BOARDS_WAVESHARE_RP2040_PLUS_4MB_H
+#define _BOARDS_WAVESHARE_RP2040_PLUS_4MB_H
+
+// For board detection
+#define WAVESHARE_RP2040_PLUS_4MB
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 25
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 6
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 7
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024)
+#endif
+
+// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
+#define PICO_SMPS_MODE_PIN 23
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif
diff --git a/src/boards/include/boards/waveshare_rp2040_zero.h b/src/boards/include/boards/waveshare_rp2040_zero.h
new file mode 100644
index 0000000..281b4dc
--- /dev/null
+++ b/src/boards/include/boards/waveshare_rp2040_zero.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// -----------------------------------------------------
+
+
+#ifndef _BOARDS_WAVESHARE_RP2040_ZERO_H
+#define _BOARDS_WAVESHARE_RP2040_ZERO_H
+
+// For board detection
+#define WAVESHARE_RP2040_ZERO
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- WS2812 ---
+#ifndef PICO_DEFAULT_WS2812_PIN
+#define PICO_DEFAULT_WS2812_PIN 16
+#endif
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 1
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 6
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 7
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 1
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 10
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 11
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 12
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 13
+#endif
+
+// --- FLASH ---
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// All boards have B1 RP2040
+#ifndef PICO_RP2040_B0_SUPPORTED 
+#define PICO_RP2040_B0_SUPPORTED  0
+#endif
+
+#endif
diff --git a/src/common/CMakeLists.txt b/src/common/CMakeLists.txt
new file mode 100644
index 0000000..38cf238
--- /dev/null
+++ b/src/common/CMakeLists.txt
@@ -0,0 +1,19 @@
+pico_add_subdirectory(boot_picoboot)
+pico_add_subdirectory(boot_uf2)
+pico_add_subdirectory(pico_base)
+pico_add_subdirectory(pico_usb_reset_interface)
+
+# PICO_CMAKE_CONFIG: PICO_BARE_METAL, Flag to exclude anything except base headers from the build, type=bool, default=0, group=build
+if (NOT PICO_BARE_METAL)
+    pico_add_subdirectory(pico_bit_ops)
+    pico_add_subdirectory(pico_binary_info)
+    pico_add_subdirectory(pico_divider)
+    pico_add_subdirectory(pico_sync)
+    pico_add_subdirectory(pico_time)
+    pico_add_subdirectory(pico_util)
+    pico_add_subdirectory(pico_stdlib)
+endif()
+
+pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR})
+
+pico_promote_common_scope_vars()
\ No newline at end of file
diff --git a/src/common/README.md b/src/common/README.md
new file mode 100644
index 0000000..0f30a42
--- /dev/null
+++ b/src/common/README.md
@@ -0,0 +1,3 @@
+This directory code that is common to all builds regardless of `PICO_PLATFORM`. It is a mix
+of common header files, or high level functionality built entirely using `hardware_` or `pico_` libraries provided
+by the actual target `PICO_PLATFORM`` 
\ No newline at end of file
diff --git a/src/common/boot_picoboot/CMakeLists.txt b/src/common/boot_picoboot/CMakeLists.txt
new file mode 100644
index 0000000..463fde4
--- /dev/null
+++ b/src/common/boot_picoboot/CMakeLists.txt
@@ -0,0 +1,2 @@
+add_library(boot_picoboot_headers INTERFACE)
+target_include_directories(boot_picoboot_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
diff --git a/src/common/boot_picoboot/include/boot/picoboot.h b/src/common/boot_picoboot/include/boot/picoboot.h
new file mode 100644
index 0000000..ddfa0aa
--- /dev/null
+++ b/src/common/boot_picoboot/include/boot/picoboot.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOOT_PICOBOOT_H
+#define _BOOT_PICOBOOT_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+
+#ifndef NO_PICO_PLATFORM
+#include "pico/platform.h"
+#endif
+
+/** \file picoboot.h
+*  \defgroup boot_picoboot boot_picoboot
+*
+* Header file for the PICOBOOT USB interface exposed by an RP2040 in BOOTSEL mode.
+*/
+
+#define PICOBOOT_MAGIC 0x431fd10bu
+
+// --------------------------------------------
+// CONTROL REQUESTS FOR THE PICOBOOT INTERFACE
+// --------------------------------------------
+
+// size 0 OUT - unstall EPs and reset
+#define PICOBOOT_IF_RESET 0x41
+
+// size 16 IN - return the status of the last command
+#define PICOBOOT_IF_CMD_STATUS 0x42
+
+// --------------------------------------------------
+// COMMAND REQUESTS SENT TO THE PICOBOOT OUT ENDPOINT
+// --------------------------------------------------
+//
+// picoboot_cmd structure of size 32 is sent to OUT endpoint
+// transfer_length bytes are transferred via IN/OUT
+// device responds on success with 0 length ACK packet set via OUT/IN
+// device may stall the transferring endpoint in case of error
+
+enum picoboot_cmd_id {
+    PC_EXCLUSIVE_ACCESS = 0x1,
+    PC_REBOOT = 0x2,
+    PC_FLASH_ERASE = 0x3,
+    PC_READ = 0x84, // either RAM or FLASH
+    PC_WRITE = 5, // either RAM or FLASH (does no erase)
+    PC_EXIT_XIP = 0x6,
+    PC_ENTER_CMD_XIP = 0x7,
+    PC_EXEC = 0x8,
+    PC_VECTORIZE_FLASH = 0x9
+};
+
+enum picoboot_status {
+    PICOBOOT_OK = 0,
+    PICOBOOT_UNKNOWN_CMD = 1,
+    PICOBOOT_INVALID_CMD_LENGTH = 2,
+    PICOBOOT_INVALID_TRANSFER_LENGTH = 3,
+    PICOBOOT_INVALID_ADDRESS = 4,
+    PICOBOOT_BAD_ALIGNMENT = 5,
+    PICOBOOT_INTERLEAVED_WRITE = 6,
+    PICOBOOT_REBOOTING = 7,
+    PICOBOOT_UNKNOWN_ERROR = 8,
+};
+
+struct __packed picoboot_reboot_cmd {
+    uint32_t dPC; // 0 means reset into bootrom
+    uint32_t dSP;
+    uint32_t dDelayMS;
+};
+
+// used for EXEC, VECTORIZE_FLASH
+struct __packed picoboot_address_only_cmd {
+    uint32_t dAddr;
+};
+
+// used for READ, WRITE, FLASH_ERASE
+struct __packed picoboot_range_cmd {
+    uint32_t dAddr;
+    uint32_t dSize;
+};
+
+enum picoboot_exclusive_type {
+    NOT_EXCLUSIVE = 0,
+    EXCLUSIVE,
+    EXCLUSIVE_AND_EJECT
+};
+
+struct __packed picoboot_exclusive_cmd {
+    uint8_t bExclusive;
+};
+
+// little endian
+struct __packed __aligned(4) picoboot_cmd {
+    uint32_t dMagic;
+    uint32_t dToken; // an identifier for this token to correlate with a status response
+    uint8_t bCmdId; // top bit set for IN
+    uint8_t bCmdSize; // bytes of actual data in the arg part of this structure
+    uint16_t _unused;
+    uint32_t dTransferLength; // length of IN/OUT transfer (or 0) if none
+    union {
+        uint8_t args[16];
+        struct picoboot_reboot_cmd reboot_cmd;
+        struct picoboot_range_cmd range_cmd;
+        struct picoboot_address_only_cmd address_only_cmd;
+        struct picoboot_exclusive_cmd exclusive_cmd;
+    };
+};
+
+static_assert(32 == sizeof(struct picoboot_cmd), "picoboot_cmd must be 32 bytes big");
+
+struct __packed __aligned(4) picoboot_cmd_status {
+    uint32_t dToken;
+    uint32_t dStatusCode;
+    uint8_t bCmdId;
+    uint8_t bInProgress;
+    uint8_t _pad[6];
+};
+
+static_assert(16 == sizeof(struct picoboot_cmd_status), "picoboot_cmd_status must be 16 bytes big");
+#endif
diff --git a/src/common/boot_uf2/CMakeLists.txt b/src/common/boot_uf2/CMakeLists.txt
new file mode 100644
index 0000000..6ca5c20
--- /dev/null
+++ b/src/common/boot_uf2/CMakeLists.txt
@@ -0,0 +1,2 @@
+add_library(boot_uf2_headers INTERFACE)
+target_include_directories(boot_uf2_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
diff --git a/src/common/boot_uf2/include/boot/uf2.h b/src/common/boot_uf2/include/boot/uf2.h
new file mode 100644
index 0000000..a040242
--- /dev/null
+++ b/src/common/boot_uf2/include/boot/uf2.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOOT_UF2_H
+#define _BOOT_UF2_H
+
+#include <stdint.h>
+#include <assert.h>
+
+/** \file uf2.h
+*  \defgroup boot_uf2 boot_uf2
+*
+* Header file for the UF2 format supported by an RP2040 in BOOTSEL mode.
+*/
+
+#define UF2_MAGIC_START0 0x0A324655u
+#define UF2_MAGIC_START1 0x9E5D5157u
+#define UF2_MAGIC_END    0x0AB16F30u
+
+#define UF2_FLAG_NOT_MAIN_FLASH     0x00000001u
+#define UF2_FLAG_FILE_CONTAINER     0x00001000u
+#define UF2_FLAG_FAMILY_ID_PRESENT  0x00002000u
+#define UF2_FLAG_MD5_PRESENT        0x00004000u
+
+#define RP2040_FAMILY_ID 0xe48bff56
+
+struct uf2_block {
+    // 32 byte header
+    uint32_t magic_start0;
+    uint32_t magic_start1;
+    uint32_t flags;
+    uint32_t target_addr;
+    uint32_t payload_size;
+    uint32_t block_no;
+    uint32_t num_blocks;
+    uint32_t file_size; // or familyID;
+    uint8_t  data[476];
+    uint32_t magic_end;
+};
+
+static_assert(sizeof(struct uf2_block) == 512, "uf2_block not sector sized");
+
+#endif
diff --git a/src/common/pico_base/CMakeLists.txt b/src/common/pico_base/CMakeLists.txt
new file mode 100644
index 0000000..3555dc0
--- /dev/null
+++ b/src/common/pico_base/CMakeLists.txt
@@ -0,0 +1,13 @@
+if (NOT TARGET pico_base_headers)
+    add_library(pico_base_headers INTERFACE)
+    target_include_directories(pico_base_headers INTERFACE include ${CMAKE_BINARY_DIR}/generated/pico_base)
+
+    # PICO_BUILD_DEFINE: PICO_BOARD, Name of board, type=string, default=CMake PICO_BOARD variable, group=pico_base
+    target_compile_definitions(pico_base_headers INTERFACE
+            PICO_BOARD="${PICO_BOARD}")
+
+    target_link_libraries(pico_base_headers INTERFACE pico_platform_headers)
+
+    list(APPEND PICO_SDK_POST_LIST_FILES ${CMAKE_CURRENT_LIST_DIR}/generate_config_header.cmake)
+    pico_promote_common_scope_vars()
+endif()
\ No newline at end of file
diff --git a/src/common/pico_base/generate_config_header.cmake b/src/common/pico_base/generate_config_header.cmake
new file mode 100644
index 0000000..333dfa7
--- /dev/null
+++ b/src/common/pico_base/generate_config_header.cmake
@@ -0,0 +1,29 @@
+# build the auto gen config headers
+
+set(header_content "// AUTOGENERATED FROM PICO_CONFIG_HEADER_FILES and then PICO_<PLATFORM>_CONFIG_HEADER_FILES\n// DO NOT EDIT!\n")
+string(TOUPPER ${PICO_PLATFORM} PICO_PLATFORM_UPPER)
+
+macro(add_header_content_from_var VAR)
+    set(header_content "${header_content}\n\n// based on ${VAR}:\n")
+    foreach(var IN LISTS ${VAR})
+        set(header_content "${header_content}\n#include \"${var}\"")
+    endforeach()
+endmacro()
+
+# PICO_CMAKE_CONFIG: PICO_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for all platforms, type=list, default="", group=pico_base
+add_header_content_from_var(PICO_CONFIG_HEADER_FILES)
+
+# PICO_CMAKE_CONFIG: PICO_CONFIG_RP2040_HEADER_FILES, List of extra header files to include from pico/config.h for rp2040 platform, type=list, default="", group=pico_base
+# PICO_CMAKE_CONFIG: PICO_CONFIG_HOST_HEADER_FILES, List of extra header files to include from pico/config.h for host platform, type=list, default="", group=pico_base
+add_header_content_from_var(PICO_${PICO_PLATFORM_UPPER}_CONFIG_HEADER_FILES)
+
+file(GENERATE
+        OUTPUT  ${CMAKE_BINARY_DIR}/generated/pico_base/pico/config_autogen.h
+        CONTENT "${header_content}"
+        )
+
+configure_file( ${CMAKE_CURRENT_LIST_DIR}/include/pico/version.h.in ${CMAKE_BINARY_DIR}/generated/pico_base/pico/version.h)
+
+foreach(DIR IN LISTS PICO_INCLUDE_DIRS)
+    target_include_directories(pico_base_headers INTERFACE ${DIR})
+endforeach()
\ No newline at end of file
diff --git a/src/common/pico_base/include/pico.h b/src/common/pico_base/include/pico.h
new file mode 100644
index 0000000..1b73651
--- /dev/null
+++ b/src/common/pico_base/include/pico.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PICO_H_
+#define PICO_H_
+
+/** \file pico.h
+ *  \defgroup pico_base pico_base
+ *
+ * Core types and macros for the Raspberry Pi Pico SDK. This header is intended to be included by all source code
+ * as it includes configuration headers and overrides in the correct order
+ *
+ * This header may be included by assembly code
+*/
+
+#include "pico/types.h"
+#include "pico/version.h"
+#include "pico/config.h"
+#include "pico/platform.h"
+#include "pico/error.h"
+
+#endif
diff --git a/src/common/pico_base/include/pico/assert.h b/src/common/pico_base/include/pico/assert.h
new file mode 100644
index 0000000..8910ebd
--- /dev/null
+++ b/src/common/pico_base/include/pico/assert.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_ASSERT_H
+#define _PICO_ASSERT_H
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+
+#include <cassert>
+
+extern "C" {
+#else
+#include <assert.h>
+#endif
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLE_ALL, Global assert enable, type=bool, default=0, group=pico_base
+// PICO_CONFIG: PARAM_ASSERTIONS_DISABLE_ALL, Global assert disable, type=bool, default=0, group=pico_base
+
+#ifndef PARAM_ASSERTIONS_ENABLE_ALL
+#define PARAM_ASSERTIONS_ENABLE_ALL 0
+#endif
+
+#ifndef PARAM_ASSERTIONS_DISABLE_ALL
+#define PARAM_ASSERTIONS_DISABLE_ALL 0
+#endif
+
+#define PARAM_ASSERTIONS_ENABLED(x) ((PARAM_ASSERTIONS_ENABLED_ ## x || PARAM_ASSERTIONS_ENABLE_ALL) && !PARAM_ASSERTIONS_DISABLE_ALL)
+
+#define invalid_params_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) assert(!(test));})
+#define valid_params_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) assert(test);})
+#define hard_assert_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) hard_assert(!(test));})
+
+#ifdef NDEBUG
+extern void hard_assertion_failure(void);
+static inline void hard_assert(bool condition, ...) {
+    if (!condition)
+        hard_assertion_failure();
+}
+#else
+#define hard_assert assert
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/src/common/pico_base/include/pico/config.h b/src/common/pico_base/include/pico/config.h
new file mode 100644
index 0000000..8d69269
--- /dev/null
+++ b/src/common/pico_base/include/pico/config.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PICO_CONFIG_H_
+#define PICO_CONFIG_H_
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLY CODE SO
+//       SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+//       OR USE #ifndef __ASSEMBLER__ guards
+// -------------
+
+// PICO_CONFIG_HEADER_FILES and then PICO_SDK_<PLATFORM>_CONFIG_INCLUDE_FILES
+// entries are dumped in order at build time into this generated header
+
+#include "pico/config_autogen.h"
+
+#endif
\ No newline at end of file
diff --git a/src/common/pico_base/include/pico/error.h b/src/common/pico_base/include/pico/error.h
new file mode 100644
index 0000000..fadb45e
--- /dev/null
+++ b/src/common/pico_base/include/pico/error.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_ERROR_H
+#define _PICO_ERROR_H
+
+#ifndef __ASSEMBLER__
+
+/*!
+ * Common return codes from pico_sdk methods that return a status
+ */
+enum {
+    PICO_OK = 0,
+    PICO_ERROR_NONE = 0,
+    PICO_ERROR_TIMEOUT = -1,
+    PICO_ERROR_GENERIC = -2,
+    PICO_ERROR_NO_DATA = -3,
+};
+
+#endif // !__ASSEMBLER__
+
+#endif
\ No newline at end of file
diff --git a/src/common/pico_base/include/pico/types.h b/src/common/pico_base/include/pico/types.h
new file mode 100644
index 0000000..8e1627c
--- /dev/null
+++ b/src/common/pico_base/include/pico/types.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_TYPES_H
+#define _PICO_TYPES_H
+
+#ifndef __ASSEMBLER__
+
+#include "pico/assert.h"
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+typedef unsigned int uint;
+
+/*! \typedef absolute_time_t
+    \brief An opaque 64 bit timestamp in microseconds
+
+    The type is used instead of a raw uint64_t to prevent accidentally passing relative times or times in the wrong
+    time units where an absolute time is required. It is equivalent to uint64_t in release builds.
+
+    \see to_us_since_boot()
+    \see update_us_since_boot()
+    \ingroup timestamp
+*/
+#ifdef NDEBUG
+typedef uint64_t absolute_time_t;
+#else
+typedef struct {
+    uint64_t _private_us_since_boot;
+} absolute_time_t;
+#endif
+
+/*! fn to_us_since_boot
+ * \brief convert an absolute_time_t into a number of microseconds since boot.
+ * \param t the absolute time to convert
+ * \return a number of microseconds since boot, equivalent to t
+ * \ingroup timestamp
+ */
+static inline uint64_t to_us_since_boot(absolute_time_t t) {
+#ifdef NDEBUG
+    return t;
+#else
+    return t._private_us_since_boot;
+#endif
+}
+
+/*! fn update_us_since_boot
+ * \brief update an absolute_time_t value to represent a given number of microseconds since boot
+ * \param t the absolute time value to update
+ * \param us_since_boot the number of microseconds since boot to represent. Note this should be representable
+ *                      as a signed 64 bit integer
+ * \ingroup timestamp
+ */
+static inline void update_us_since_boot(absolute_time_t *t, uint64_t us_since_boot) {
+#ifdef NDEBUG
+    *t = us_since_boot;
+#else
+    assert(us_since_boot <= INT64_MAX);
+    t->_private_us_since_boot = us_since_boot;
+#endif
+}
+
+#ifdef NDEBUG
+#define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = value
+#else
+#define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = {value}
+#endif
+
+/** \struct datetime_t
+ *  \ingroup util_datetime
+ *  \brief Structure containing date and time information
+ *
+ *    When setting an RTC alarm, set a field to -1 tells
+ *    the RTC to not match on this field
+ */
+typedef struct {
+    int16_t year;    ///< 0..4095
+    int8_t month;    ///< 1..12, 1 is January
+    int8_t day;      ///< 1..28,29,30,31 depending on month
+    int8_t dotw;     ///< 0..6, 0 is Sunday
+    int8_t hour;     ///< 0..23
+    int8_t min;      ///< 0..59
+    int8_t sec;      ///< 0..59
+} datetime_t;
+
+#define bool_to_bit(x) ((uint)!!(x))
+
+#endif
+#endif
diff --git a/src/common/pico_base/include/pico/version.h.in b/src/common/pico_base/include/pico/version.h.in
new file mode 100644
index 0000000..08fbfb5
--- /dev/null
+++ b/src/common/pico_base/include/pico/version.h.in
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// ---------------------------------------
+// THIS FILE IS AUTOGENERATED; DO NOT EDIT
+// ---------------------------------------
+
+#ifndef _PICO_VERSION_H
+#define _PICO_VERSION_H
+
+#define PICO_SDK_VERSION_MAJOR    ${PICO_SDK_VERSION_MAJOR}
+#define PICO_SDK_VERSION_MINOR    ${PICO_SDK_VERSION_MINOR}
+#define PICO_SDK_VERSION_REVISION ${PICO_SDK_VERSION_REVISION}
+#define PICO_SDK_VERSION_STRING   "${PICO_SDK_VERSION_STRING}"
+
+#endif
diff --git a/src/common/pico_binary_info/CMakeLists.txt b/src/common/pico_binary_info/CMakeLists.txt
new file mode 100644
index 0000000..eb0c3f6
--- /dev/null
+++ b/src/common/pico_binary_info/CMakeLists.txt
@@ -0,0 +1,34 @@
+add_library(pico_binary_info_headers INTERFACE)
+
+target_include_directories(pico_binary_info_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+if (COMMAND pico_add_platform_library)
+    pico_add_platform_library(pico_binary_info)
+else()
+    add_library(pico_binary_info INTERFACE)
+endif()
+
+target_link_libraries(pico_binary_info INTERFACE pico_binary_info_headers)
+
+function(pico_set_program_name TARGET name)
+    # PICO_BUILD_DEFINE: PICO_PROGRAM_NAME, value passed to pico_set_program_name, type=string, default=none, group=pico_binary_info
+    target_compile_definitions(${TARGET} PRIVATE -DPICO_PROGRAM_NAME="${name}")
+endfunction()
+
+function(pico_set_program_description TARGET description)
+    # since this is the command line, we will remove newlines
+    string(REPLACE "\n" " " description ${description})
+    string(REPLACE "\"" "\\\"" description ${description})
+    # PICO_BUILD_DEFINE: PICO_PROGRAM_DESCRIPTION, value passed to pico_set_program_description, type=string, default=none, group=pico_binary_info
+    target_compile_definitions(${TARGET} PRIVATE -DPICO_PROGRAM_DESCRIPTION="${description}")
+endfunction()
+
+function(pico_set_program_url TARGET url)
+    # PICO_BUILD_DEFINE: PICO_PROGRAM_URL, value passed to pico_set_program_url, type=string, default=none, group=pico_binary_info
+    target_compile_definitions(${TARGET} PRIVATE -DPICO_PROGRAM_URL="${url}")
+endfunction()
+
+function(pico_set_program_version TARGET version)
+    # PICO_BUILD_DEFINE: PICO_PROGRAM_VERSION_STRING, value passed to pico_set_program_version, type=string, default=none, group=pico_binary_info
+    target_compile_definitions(${TARGET} PRIVATE -DPICO_PROGRAM_VERSION_STRING="${version}")
+endfunction()
diff --git a/src/common/pico_binary_info/include/pico/binary_info.h b/src/common/pico_binary_info/include/pico/binary_info.h
new file mode 100644
index 0000000..77b1c08
--- /dev/null
+++ b/src/common/pico_binary_info/include/pico/binary_info.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_BINARY_INFO_H
+#define _PICO_BINARY_INFO_H
+
+/** \file binary_info.h
+ *  \defgroup pico_binary_info pico_binary_info
+ *
+ * Binary info is intended for embedding machine readable information with the binary in FLASH.
+ *
+ * Example uses include:
+ *
+ * - Program identification / information
+ * - Pin layouts
+ * - Included features
+ * - Identifying flash regions used as block devices/storage
+ */
+
+#include "pico/binary_info/defs.h"
+#include "pico/binary_info/structure.h"
+#if !PICO_ON_DEVICE && !defined(PICO_NO_BINARY_INFO)
+#define PICO_NO_BINARY_INFO 1
+#endif
+#if !PICO_NO_BINARY_INFO
+#include "pico/binary_info/code.h"
+#endif
+#endif
diff --git a/src/common/pico_binary_info/include/pico/binary_info/code.h b/src/common/pico_binary_info/include/pico/binary_info/code.h
new file mode 100644
index 0000000..e87a2cd
--- /dev/null
+++ b/src/common/pico_binary_info/include/pico/binary_info/code.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_BINARY_INFO_CODE_H
+#define _PICO_BINARY_INFO_CODE_H
+
+#include "pico.h"
+#include "pico/binary_info/structure.h"
+
+#if !PICO_NO_BINARY_INFO
+#define __bi_decl(name, bi, section_prefix, attr) static const attr __attribute__((section(section_prefix __STRING(name)))) struct _binary_info_core *name = bi
+#define __bi_lineno_var_name __CONCAT(__bi_, __LINE__)
+#define __bi_ptr_lineno_var_name __CONCAT(__bi_ptr, __LINE__)
+#define __bi_enclosure_check_lineno_var_name __CONCAT(_error_bi_is_missing_enclosing_decl_,__LINE__)
+#define __bi_mark_enclosure static const __unused int __bi_enclosure_check_lineno_var_name=0;
+#if !defined(__GNUC__) || __cplusplus || __GNUC__ >= 8
+#define __bi_enclosure_check(x) (x + __bi_enclosure_check_lineno_var_name)
+#else
+// skip the version check on older GCC non C++, as it doesn't compile.. this is only here to catch the
+// user accidentally forgetting to enclose the binary item with bi_decl
+#define __bi_enclosure_check(x) (x)
+#endif
+/**
+ * Declare some binary information that will be included if the contain source file/line is compiled into the binary
+ * \ingroup pico_binary_info
+ */
+#define bi_decl(_decl) __bi_mark_enclosure _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.keep.", __used);
+/**
+ * Declare some binary information that will be included if the function containing the decl is linked into the binary.
+ * The SDK uses --gc-sections, so functions that are never called will be removed by the linker, and any associated
+ * binary information declared this way will also be stripped
+ * \ingroup pico_binary_info
+ */
+#define bi_decl_if_func_used(_decl) ({__bi_mark_enclosure _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.", ); *(volatile uint8_t *)&__bi_ptr_lineno_var_name;});
+
+#define bi_decl_with_attr(_decl, _attr) __bi_mark_enclosure _attr _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.keep.", __used);
+#define bi_decl_if_func_used_with_attr(_decl, _attr) ({__bi_mark_enclosure _attr _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.", ); *(volatile uint8_t *)&__bi_ptr_lineno_var_name;});
+#else
+#define __bi_decl(bi, name, attr)
+#define bi_decl_with_attr(_decl, _attr)
+#define bi_decl(_decl)
+#define bi_decl_if_func_used_with_attr(_decl, _attr) ((void)0);
+#define bi_decl_if_func_used(_decl) ((void)0);
+#endif
+
+#define bi_int(_tag, _id, _value) \
+     static const struct _binary_info_id_and_int __bi_lineno_var_name = { \
+        .core = { \
+            .type = __bi_enclosure_check(BINARY_INFO_TYPE_ID_AND_INT), \
+            .tag = _tag, \
+        },\
+        .id = _id, \
+        .value = _value \
+    };
+
+#define bi_string(_tag, _id, _value) \
+    static const struct _binary_info_id_and_string __bi_lineno_var_name = { \
+        .core = { \
+            .type = __bi_enclosure_check(BINARY_INFO_TYPE_ID_AND_STRING), \
+            .tag = _tag, \
+        },\
+        .id = _id, \
+        .value = _value, \
+    }
+
+#define bi_block_device(_tag, _name, _address, _size, _extra, _flags) \
+    static const struct _binary_info_block_device __bi_lineno_var_name = { \
+        .core = { \
+            .type = __bi_enclosure_check(BINARY_INFO_TYPE_BLOCK_DEVICE), \
+            .tag = _tag, \
+        },\
+        .name = _name, \
+        .address = _address, \
+        .size = _size, \
+        .extra = _extra, \
+        .flags = _flags, \
+    }
+
+#define __bi_encoded_pins_with_func(_encoding) \
+    static const struct _binary_info_pins_with_func __bi_lineno_var_name = { \
+        .core = { \
+            .type = __bi_enclosure_check(BINARY_INFO_TYPE_PINS_WITH_FUNC), \
+            .tag = BINARY_INFO_TAG_RASPBERRY_PI, \
+        },\
+        .pin_encoding = _encoding \
+    }
+
+#define __bi_pins_with_name(_mask, _label) \
+    static const struct _binary_info_pins_with_name __bi_lineno_var_name = { \
+        .core = { \
+            .type = __bi_enclosure_check(BINARY_INFO_TYPE_PINS_WITH_NAME), \
+            .tag = BINARY_INFO_TAG_RASPBERRY_PI, \
+        },\
+        .pin_mask = _mask, \
+        .label = _label \
+    }
+
+#define __bi_named_group(_parent_tag, _parent_id, _group_tag, _group_id, _label, _flags) \
+static const struct _binary_info_named_group __bi_lineno_var_name = { \
+        .core = { \
+            .type = __bi_enclosure_check(BINARY_INFO_TYPE_NAMED_GROUP), \
+            .tag = _parent_tag, \
+        },\
+        .parent_id = _parent_id, \
+        .group_tag = _group_tag, \
+        .flags = _flags, \
+        .group_id = _group_id, \
+        .label = _label \
+    }
+
+#define bi_binary_end(end) bi_int(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_BINARY_END, end)
+#define bi_program_name(name) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_NAME, name)
+#define bi_program_description(description) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_DESCRIPTION, description)
+#define bi_program_version_string(version_string) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_VERSION_STRING, version_string)
+#define bi_program_build_date_string(date_string) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_BUILD_DATE_STRING, date_string)
+#define bi_program_url(url) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_URL, url)
+// multiple of these may be added
+#define bi_program_feature(feature) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_FEATURE, feature)
+#define bi_program_build_attribute(attr) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_BUILD_ATTRIBUTE, attr)
+#define bi_program_feature_group(tag, id, name) __bi_named_group(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_FEATURE, tag, id, name, 0)
+#define bi_program_feature_group_with_flags(tag, id, name, flags) __bi_named_group(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_FEATURE, tag, id, name, flags)
+
+#define bi_1pin_with_func(p0, func)                  __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p0) << 12))
+#define bi_2pins_with_func(p0, p1, func)             __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p1) << 17))
+#define bi_3pins_with_func(p0, p1, p2, func)         __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p2) << 17) | ((p2) << 22))
+#define bi_4pins_with_func(p0, p1, p2, p3, func)     __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p2) << 17) | ((p3) << 22) | ((p3) << 27))
+#define bi_5pins_with_func(p0, p1, p2, p3, p4, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p2) << 17) | ((p3) << 22) | ((p4) << 27))
+#define bi_pin_range_with_func(plo, phi, func)       __bi_encoded_pins_with_func(BI_PINS_ENCODING_RANGE | ((func << 3)) | ((plo) << 7) | ((phi) << 12))
+
+#define bi_pin_mask_with_name(pmask, label)          __bi_pins_with_name((pmask), (label))
+// names are sperated by | ... i.e. "name1|name2|name3"
+#define bi_pin_mask_with_names(pmask, label)          __bi_pins_with_name((pmask), (label))
+#define bi_1pin_with_name(p0, name)                   bi_pin_mask_with_name(1u << (p0), name)
+#define bi_2pins_with_names(p0, name0, p1, name1)     bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)), name0 "|" name1)
+#define bi_3pins_with_names(p0, name0, p1, name1, p2, name2)  bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)) | (1u << (p2)), name0 "|" name1 "|" name2)
+#define bi_4pins_with_names(p0, name0, p1, name1, p2, name2, p3, name3)  bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)) | (1u << (p2)) | (1u << (p3)), name0 "|" name1 "|" name2 "|" name3)
+
+#endif
diff --git a/src/common/pico_binary_info/include/pico/binary_info/defs.h b/src/common/pico_binary_info/include/pico/binary_info/defs.h
new file mode 100644
index 0000000..407c0ac
--- /dev/null
+++ b/src/common/pico_binary_info/include/pico/binary_info/defs.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_BINARY_INFO_DEFS_H
+#define _PICO_BINARY_INFO_DEFS_H
+
+// this file is for pre-processor definitions only
+
+// should be found within the first 256 bytes of the real binary (i.e. after the flash second stage if a flash binary)
+//
+// Note the layout is:
+//
+// addr      : BINARY_INFO_MARKER_START
+// addr+0x04 : __binary_info_start
+// addr+0x08 : __binary_info_end
+// addr+0x0c : __address_mapping_table
+// addr+0x10 | BINARY_INFO_MARKER_END
+//
+// __binary_info_start to __binary_info_end are the start, end (non inclusive) of an array
+// of pointers to binary_info_t structures
+//
+// __address_mapping_table is an array of the following items:
+//
+// uint32_t source_addr_start
+// uint32_t dest_addr_start
+// uint32_t dest_addr_end
+//
+// representing a mapping from the stored address in the binary/flash to addresses at runtime.
+// The linker will store pointers within the binary using their runtime values, however because of
+// "AT" mapping in the link script these addresses actually correspond to a different address in the binary
+// image. This mapping (which in the case of crt0.S is simply the data copy table used at initialization
+// to copy data into it's runtime location) can be used by picotool or others to reverse the mapping to find data
+// within the binary.
+//
+// Note the above array is terminated with a NULL source_addr_start
+
+#define BINARY_INFO_MARKER_START 0x7188ebf2
+#define BINARY_INFO_MARKER_END 0xe71aa390
+
+#endif
\ No newline at end of file
diff --git a/src/common/pico_binary_info/include/pico/binary_info/structure.h b/src/common/pico_binary_info/include/pico/binary_info/structure.h
new file mode 100644
index 0000000..49d2fd6
--- /dev/null
+++ b/src/common/pico_binary_info/include/pico/binary_info/structure.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_BINARY_INFO_STRUCTURE_H
+#define _PICO_BINARY_INFO_STRUCTURE_H
+
+// NOTE: This file may be included by non SDK code, so does not use SDK includes
+
+// NOTE: ALL CHANGES MUST BE BACKWARDS COMPATIBLE
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif
+
+typedef struct _binary_info_core binary_info_t;
+
+#define BINARY_INFO_TYPE_RAW_DATA 1
+#define BINARY_INFO_TYPE_SIZED_DATA 2
+#define BINARY_INFO_TYPE_BINARY_INFO_LIST_ZERO_TERMINATED 3
+#define BINARY_INFO_TYPE_BSON 4
+#define BINARY_INFO_TYPE_ID_AND_INT 5
+#define BINARY_INFO_TYPE_ID_AND_STRING 6
+// traditional block device
+#define BINARY_INFO_TYPE_BLOCK_DEVICE 7
+#define BINARY_INFO_TYPE_PINS_WITH_FUNC 8
+#define BINARY_INFO_TYPE_PINS_WITH_NAME 9
+#define BINARY_INFO_TYPE_PINS_WITH_NAMES 9
+#define BINARY_INFO_TYPE_NAMED_GROUP 10
+
+// note plan is to reserve c1 = 0->31 for "collision tags"; i.e.
+// for which you should always use random IDs with the binary_info,
+// giving you 4 + 8 + 32 = 44 bits to avoid collisions
+#define BINARY_INFO_MAKE_TAG(c1, c2) ((((uint)c2&0xffu)<<8u)|((uint)c1&0xffu))
+
+// Raspberry Pi defined. do not use
+#define BINARY_INFO_TAG_RASPBERRY_PI BINARY_INFO_MAKE_TAG('R','P')
+
+#define BINARY_INFO_ID_RP_PROGRAM_NAME 0x02031c86
+#define BINARY_INFO_ID_RP_PROGRAM_VERSION_STRING 0x11a9bc3a
+#define BINARY_INFO_ID_RP_PROGRAM_BUILD_DATE_STRING 0x9da22254
+#define BINARY_INFO_ID_RP_BINARY_END 0x68f465de
+#define BINARY_INFO_ID_RP_PROGRAM_URL 0x1856239a
+#define BINARY_INFO_ID_RP_PROGRAM_DESCRIPTION 0xb6a07c19
+#define BINARY_INFO_ID_RP_PROGRAM_FEATURE 0xa1f4b453
+#define BINARY_INFO_ID_RP_PROGRAM_BUILD_ATTRIBUTE 0x4275f0d3
+#define BINARY_INFO_ID_RP_SDK_VERSION 0x5360b3ab
+#define BINARY_INFO_ID_RP_PICO_BOARD 0xb63cffbb
+#define BINARY_INFO_ID_RP_BOOT2_NAME 0x7f8882e1
+
+#if PICO_ON_DEVICE
+#define bi_ptr_of(x) x *
+#else
+#define bi_ptr_of(x) uint32_t
+#endif
+typedef struct __packed _binary_info_core {
+        uint16_t type;
+        uint16_t tag;
+} binary_info_core_t;
+
+typedef struct __packed _binary_info_raw_data {
+        struct _binary_info_core core;
+        uint8_t bytes[1];
+} binary_info_raw_data_t;
+
+typedef struct __packed _binary_info_sized_data {
+        struct _binary_info_core core;
+        uint32_t length;
+        uint8_t bytes[1];
+} binary_info_sized_data_t;
+
+typedef struct __packed _binary_info_list_zero_terminated {
+        struct _binary_info_core core;
+        bi_ptr_of(binary_info_t) list;
+} binary_info_list_zero_terminated_t;
+
+typedef struct __packed _binary_info_id_and_int {
+        struct _binary_info_core core;
+        uint32_t id;
+        int32_t value;
+} binary_info_id_and_int_t;
+
+typedef struct __packed _binary_info_id_and_string {
+        struct _binary_info_core core;
+        uint32_t id;
+        bi_ptr_of(const char) value;
+} binary_info_id_and_string_t;
+
+typedef struct __packed _binary_info_block_device {
+        struct _binary_info_core core;
+        bi_ptr_of(const char) name; // optional static name (independent of what is formatted)
+        uint32_t address;
+        uint32_t size;
+        bi_ptr_of(binary_info_t) extra; // additional info
+        uint16_t flags;
+} binary_info_block_device_t;
+
+#define BI_PINS_ENCODING_RANGE 1
+#define BI_PINS_ENCODING_MULTI 2
+
+typedef struct __packed _binary_info_pins_with_func {
+    struct _binary_info_core core;
+    // p4_5 : p3_5 : p2_5 : p1_5 : p0_5 : func_4 : 001_3 //individual pins p0,p1,p2,p3,p4 ... if fewer than 5 then duplicate p
+    //                    phi_5 : plo_5 : func_4 : 010_3 // pin range plo-phi inclusive
+    uint32_t pin_encoding;
+} binary_info_pins_with_func_t;
+
+typedef struct __packed _binary_info_pins_with_name {
+    struct _binary_info_core core;
+    uint32_t pin_mask;
+    bi_ptr_of(const char) label;
+} binary_info_pins_with_name_t;
+
+#define BI_NAMED_GROUP_SHOW_IF_EMPTY   0x0001  // default is to hide
+#define BI_NAMED_GROUP_SEPARATE_COMMAS 0x0002  // default is newlines
+#define BI_NAMED_GROUP_SORT_ALPHA      0x0004  // default is no sort
+#define BI_NAMED_GROUP_ADVANCED        0x0008  // if set, then only shown in say info -a
+
+typedef struct __packed _binary_info_named_group {
+    struct _binary_info_core core;
+    uint32_t parent_id;
+    uint16_t flags;
+    uint16_t group_tag;
+    uint32_t group_id;
+    bi_ptr_of(const char) label;
+} binary_info_named_group_t;
+
+enum {
+    BINARY_INFO_BLOCK_DEV_FLAG_READ =
+    1 << 0, // if not readable, then it is basically hidden, but tools may choose to avoid overwriting it
+    BINARY_INFO_BLOCK_DEV_FLAG_WRITE = 1 << 1,
+    BINARY_INFO_BLOCK_DEV_FLAG_REFORMAT = 1 << 2, // may be reformatted..
+
+    BINARY_INFO_BLOCK_DEV_FLAG_PT_UNKNOWN = 0 << 4, // unknown free to look
+    BINARY_INFO_BLOCK_DEV_FLAG_PT_MBR = 1 << 4, // expect MBR
+    BINARY_INFO_BLOCK_DEV_FLAG_PT_GPT = 2 << 4, // expect GPT
+    BINARY_INFO_BLOCK_DEV_FLAG_PT_NONE = 3 << 4, // no partition table
+};
+
+#ifdef __cplusplus
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/src/common/pico_bit_ops/CMakeLists.txt b/src/common/pico_bit_ops/CMakeLists.txt
new file mode 100644
index 0000000..603a520
--- /dev/null
+++ b/src/common/pico_bit_ops/CMakeLists.txt
@@ -0,0 +1,5 @@
+if (NOT TARGET pico_bit_ops_headers)
+    add_library(pico_bit_ops_headers INTERFACE)
+    target_include_directories(pico_bit_ops_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+    target_link_libraries(pico_bit_ops_headers INTERFACE pico_base_headers)
+endif()
\ No newline at end of file
diff --git a/src/common/pico_bit_ops/include/pico/bit_ops.h b/src/common/pico_bit_ops/include/pico/bit_ops.h
new file mode 100644
index 0000000..7b63c1d
--- /dev/null
+++ b/src/common/pico_bit_ops/include/pico/bit_ops.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_BIT_OPS_H
+#define _PICO_BIT_OPS_H
+
+#include "pico.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file bit_ops.h
+*  \defgroup pico_bit_ops pico_bit_ops
+*
+* Optimized bit manipulation functions.
+* Additionally provides  replacement implementations of the compiler built-ins __builtin_popcount, __builtin_clz
+* and __bulitin_ctz
+*/
+
+/*! \brief Reverse the bits in a 32 bit word
+ *  \ingroup pico_bit_ops
+ *
+ * \param bits 32 bit input
+ * \return the 32 input bits reversed
+ */
+uint32_t __rev(uint32_t bits);
+
+/*! \brief Reverse the bits in a 64 bit double word
+ *  \ingroup pico_bit_ops
+ *
+ * \param bits 64 bit input
+ * \return the 64 input bits reversed
+ */
+uint64_t __revll(uint64_t bits);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/common/pico_divider/CMakeLists.txt b/src/common/pico_divider/CMakeLists.txt
new file mode 100644
index 0000000..aed07d2
--- /dev/null
+++ b/src/common/pico_divider/CMakeLists.txt
@@ -0,0 +1,5 @@
+if (NOT TARGET pico_divider_headers)
+    add_library(pico_divider_headers INTERFACE)
+    target_include_directories(pico_divider_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+    target_link_libraries(pico_divider_headers INTERFACE pico_base_headers)
+endif()
\ No newline at end of file
diff --git a/src/common/pico_divider/include/pico/divider.h b/src/common/pico_divider/include/pico/divider.h
new file mode 100644
index 0000000..749f734
--- /dev/null
+++ b/src/common/pico_divider/include/pico/divider.h
@@ -0,0 +1,322 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_DIVIDER_H_
+#define _PICO_DIVIDER_H_
+
+#include "pico.h"
+#include "hardware/divider.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup pico_divider pico_divider
+ * Optimized 32 and 64 bit division functions accelerated by the RP2040 hardware divider.
+ * Additionally provides integration with the C `/` and `%` operators
+ */
+
+/** \file pico/divider.h
+* \brief High level APIs including combined quotient and remainder functions for 32 and 64 bit accelerated by the hardware divider
+* \ingroup pico_divider
+*
+* These functions all call __aeabi_idiv0 or __aebi_ldiv0 on division by zero
+* passing the largest applicably signed value
+*
+* Functions with unsafe in their name do not save/restore divider state, so are unsafe to call from interrupts. Unsafe functions are slightly faster.
+*/
+
+/**
+ * \brief Integer divide of two signed 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient
+ */
+int32_t div_s32s32(int32_t a, int32_t b);
+
+/**
+ * \brief Integer divide of two signed 32-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ */
+static inline int32_t divmod_s32s32_rem(int32_t a, int32_t b, int32_t *rem) {
+    divmod_result_t r = hw_divider_divmod_s32(a, b);
+    *rem = to_remainder_s32(r);
+    return to_quotient_s32(r);
+}
+
+/**
+ * \brief Integer divide of two signed 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in low word/r0, remainder in high word/r1
+ */
+divmod_result_t divmod_s32s32(int32_t a, int32_t b);
+
+/**
+ * \brief Integer divide of two unsigned 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return Quotient
+ */
+uint32_t div_u32u32(uint32_t a, uint32_t b);
+
+/**
+ * \brief Integer divide of two unsigned 32-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ */
+static inline uint32_t divmod_u32u32_rem(uint32_t a, uint32_t b, uint32_t *rem) {
+    divmod_result_t r = hw_divider_divmod_u32(a, b);
+    *rem = to_remainder_u32(r);
+    return to_quotient_u32(r);
+}
+
+/**
+ * \brief Integer divide of two unsigned 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in low word/r0, remainder in high word/r1
+ */
+divmod_result_t divmod_u32u32(uint32_t a, uint32_t b);
+
+/**
+ * \brief Integer divide of two signed 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return Quotient
+ */
+int64_t div_s64s64(int64_t a, int64_t b);
+
+/**
+ * \brief Integer divide of two signed 64-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ */
+int64_t divmod_s64s64_rem(int64_t a, int64_t b, int64_t *rem);
+
+/**
+ * \brief Integer divide of two signed 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in result (r0,r1), remainder in regs (r2, r3)
+ */
+int64_t divmod_s64s64(int64_t a, int64_t b);
+
+/**
+ * \brief Integer divide of two unsigned 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return Quotient
+ */
+uint64_t div_u64u64(uint64_t a, uint64_t b);
+
+/**
+ * \brief Integer divide of two unsigned 64-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ */
+uint64_t divmod_u64u64_rem(uint64_t a, uint64_t b, uint64_t *rem);
+
+
+/**
+ * \brief Integer divide of two signed 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in result (r0,r1), remainder in regs (r2, r3)
+ */
+uint64_t divmod_u64u64(uint64_t a, uint64_t b);
+
+// -----------------------------------------------------------------------
+// these "unsafe" functions are slightly faster, but do not save the divider state,
+// so are not generally safe to be called from interrupts
+// -----------------------------------------------------------------------
+
+/**
+ * \brief Unsafe integer divide of two signed 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient
+ *
+ * Do not use in interrupts
+ */
+int32_t div_s32s32_unsafe(int32_t a, int32_t b);
+
+/**
+ * \brief Unsafe integer divide of two signed 32-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ *
+ * Do not use in interrupts
+ */
+int32_t divmod_s32s32_rem_unsafe(int32_t a, int32_t b, int32_t *rem);
+
+/**
+ * \brief Unsafe integer divide of two unsigned 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in low word/r0, remainder in high word/r1
+ *
+ * Do not use in interrupts
+ */
+int64_t divmod_s32s32_unsafe(int32_t a, int32_t b);
+
+/**
+ * \brief Unsafe integer divide of two unsigned 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return Quotient
+ *
+ * Do not use in interrupts
+ */
+uint32_t div_u32u32_unsafe(uint32_t a, uint32_t b);
+
+/**
+ * \brief Unsafe integer divide of two unsigned 32-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ *
+ * Do not use in interrupts
+ */
+uint32_t divmod_u32u32_rem_unsafe(uint32_t a, uint32_t b, uint32_t *rem);
+
+/**
+ * \brief Unsafe integer divide of two unsigned 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in low word/r0, remainder in high word/r1
+ *
+ * Do not use in interrupts
+ */
+uint64_t divmod_u32u32_unsafe(uint32_t a, uint32_t b);
+
+/**
+ * \brief Unsafe integer divide of two signed 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return Quotient
+ *
+ * Do not use in interrupts
+ */
+int64_t div_s64s64_unsafe(int64_t a, int64_t b);
+
+/**
+ * \brief Unsafe integer divide of two signed 64-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ *
+ * Do not use in interrupts
+ */
+int64_t divmod_s64s64_rem_unsafe(int64_t a, int64_t b, int64_t *rem);
+
+/**
+ * \brief Unsafe integer divide of two signed 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in result (r0,r1), remainder in regs (r2, r3)
+ *
+ * Do not use in interrupts
+ */
+int64_t divmod_s64s64_unsafe(int64_t a, int64_t b);
+
+/**
+ * \brief Unsafe integer divide of two unsigned 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return Quotient
+ *
+ * Do not use in interrupts
+ */
+uint64_t div_u64u64_unsafe(uint64_t a, uint64_t b);
+
+/**
+ * \brief Unsafe integer divide of two unsigned 64-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ *
+ * Do not use in interrupts
+ */
+uint64_t divmod_u64u64_rem_unsafe(uint64_t a, uint64_t b, uint64_t *rem);
+
+/**
+ * \brief Unsafe integer divide of two signed 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in result (r0,r1), remainder in regs (r2, r3)
+ *
+ * Do not use in interrupts
+ */
+uint64_t divmod_u64u64_unsafe(uint64_t a, uint64_t b);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/src/common/pico_stdlib/CMakeLists.txt b/src/common/pico_stdlib/CMakeLists.txt
new file mode 100644
index 0000000..454ea57
--- /dev/null
+++ b/src/common/pico_stdlib/CMakeLists.txt
@@ -0,0 +1,11 @@
+if (NOT TARGET pico_stdlib_headers)
+    add_library(pico_stdlib_headers INTERFACE)
+    target_include_directories(pico_stdlib_headers INTERFACE include)
+    target_link_libraries(pico_stdlib_headers INTERFACE
+            hardware_gpio
+            hardware_uart
+            hardware_divider
+            pico_time
+            pico_util
+    )
+endif()
\ No newline at end of file
diff --git a/src/common/pico_stdlib/include/pico/stdlib.h b/src/common/pico_stdlib/include/pico/stdlib.h
new file mode 100644
index 0000000..da0eef5
--- /dev/null
+++ b/src/common/pico_stdlib/include/pico/stdlib.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_STDLIB_H
+#define _PICO_STDLIB_H
+
+#include "pico.h"
+#include "pico/stdio.h"
+#include "pico/time.h"
+#include "hardware/gpio.h"
+#include "hardware/uart.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file stdlib.h
+ *  \defgroup pico_stdlib pico_stdlib
+ *
+ * Aggregation of a core subset of Raspberry Pi Pico SDK libraries used by most executables along with some additional
+ * utility methods. Including pico_stdlib gives you everything you need to get a basic program running
+ * which prints to stdout or flashes a LED
+ *
+ * This library aggregates:
+ *   - @ref hardware_uart
+ *   - @ref hardware_gpio
+ *   - @ref pico_binary_info
+ *   - @ref pico_runtime
+ *   - @ref pico_platform
+ *   - @ref pico_printf
+ *   - @ref pico_stdio
+ *   - @ref pico_standard_link
+ *   - @ref pico_util
+ *
+ * There are some basic default values used by these functions that will default to
+ * usable values, however, they can be customised in a board definition header via
+ * config.h or similar
+ */
+
+// Note PICO_STDIO_UART, PICO_STDIO_USB, PICO_STDIO_SEMIHOSTING are set by the
+// respective INTERFACE libraries, so these defines are set if the library
+// is included for the target executable
+
+#if LIB_PICO_STDIO_UART
+#include "pico/stdio_uart.h"
+#endif
+
+#if LIB_PICO_STDIO_USB
+#include "pico/stdio_usb.h"
+#endif
+
+#if LIB_PICO_STDIO_SEMIHOSTING
+#include "pico/stdio_semihosting.h"
+#endif
+
+// PICO_CONFIG: PICO_DEFAULT_LED_PIN, Optionally define a pin that drives a regular LED on the board, group=pico_stdlib
+
+// PICO_CONFIG: PICO_DEFAULT_LED_PIN_INVERTED, 1 if LED is inverted or 0 if not, type=int, default=0, group=pico_stdlib
+#ifndef PICO_DEFAULT_LED_PIN_INVERTED
+#define PICO_DEFAULT_LED_PIN_INVERTED 0
+#endif
+
+// PICO_CONFIG: PICO_DEFAULT_WS2812_PIN, Optionally define a pin that controls data to a WS2812 compatible LED on the board, group=pico_stdlib
+// PICO_CONFIG: PICO_DEFAULT_WS2812_POWER_PIN, Optionally define a pin that controls power to a WS2812 compatible LED on the board, group=pico_stdlib
+
+/*! \brief Set up the default UART and assign it to the default GPIO's
+ *  \ingroup pico_stdlib
+ *
+ * By default this will use UART 0, with TX to pin GPIO 0,
+ * RX to pin GPIO 1, and the baudrate to 115200
+ *
+ * Calling this method also initializes stdin/stdout over UART if the
+ * @ref pico_stdio_uart library is linked.
+ *
+ * Defaults can be changed using configuration defines,
+ *  PICO_DEFAULT_UART_INSTANCE,
+ *  PICO_DEFAULT_UART_BAUD_RATE
+ *  PICO_DEFAULT_UART_TX_PIN
+ *  PICO_DEFAULT_UART_RX_PIN
+ */
+void setup_default_uart(void);
+
+/*! \brief Initialise the system clock to 48MHz
+ *  \ingroup pico_stdlib
+ *
+ *  Set the system clock to 48MHz, and set the peripheral clock to match.
+ */
+void set_sys_clock_48mhz(void);
+
+/*! \brief Initialise the system clock
+ *  \ingroup pico_stdlib
+ *
+ * \param vco_freq The voltage controller oscillator frequency to be used by the SYS PLL
+ * \param post_div1 The first post divider for the SYS PLL
+ * \param post_div2 The second post divider for the SYS PLL.
+ *
+ * See the PLL documentation in the datasheet for details of driving the PLLs.
+ */
+void set_sys_clock_pll(uint32_t vco_freq, uint post_div1, uint post_div2);
+
+/*! \brief Check if a given system clock frequency is valid/attainable
+ *  \ingroup pico_stdlib
+ *
+ * \param freq_khz Requested frequency
+ * \param vco_freq_out On success, the voltage controller oscillator frequeucny to be used by the SYS PLL
+ * \param post_div1_out On success, The first post divider for the SYS PLL
+ * \param post_div2_out On success, The second post divider for the SYS PLL.
+ * @return true if the frequency is possible and the output parameters have been written.
+ */
+bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_freq_out, uint *post_div1_out, uint *post_div2_out);
+
+/*! \brief Attempt to set a system clock frequency in khz
+ *  \ingroup pico_stdlib
+ *
+ * Note that not all clock frequencies are possible; it is preferred that you
+ * use src/rp2_common/hardware_clocks/scripts/vcocalc.py to calculate the parameters
+ * for use with set_sys_clock_pll
+ *
+ * \param freq_khz Requested frequency
+ * \param required if true then this function will assert if the frequency is not attainable.
+ * \return true if the clock was configured
+ */
+static inline bool set_sys_clock_khz(uint32_t freq_khz, bool required) {
+    uint vco, postdiv1, postdiv2;
+    if (check_sys_clock_khz(freq_khz, &vco, &postdiv1, &postdiv2)) {
+        set_sys_clock_pll(vco, postdiv1, postdiv2);
+        return true;
+    } else if (required) {
+        panic("System clock of %u kHz cannot be exactly achieved", freq_khz);
+    }
+    return false;
+}
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/src/common/pico_sync/CMakeLists.txt b/src/common/pico_sync/CMakeLists.txt
new file mode 100644
index 0000000..2f8bde2
--- /dev/null
+++ b/src/common/pico_sync/CMakeLists.txt
@@ -0,0 +1,44 @@
+if (NOT TARGET pico_sync_headers)
+    add_library(pico_sync_headers INTERFACE)
+    target_include_directories(pico_sync_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+    target_link_libraries(pico_sync_headers INTERFACE hardware_sync pico_time)
+endif()
+
+if (NOT TARGET pico_sync_core)
+    pico_add_impl_library(pico_sync_core)
+    target_sources(pico_sync_core INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/lock_core.c
+    )
+    target_link_libraries(pico_sync_core INTERFACE pico_sync_headers)
+endif()
+
+if (NOT TARGET pico_sync_sem)
+    pico_add_impl_library(pico_sync_sem)
+    target_sources(pico_sync_sem INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/sem.c
+    )
+    target_link_libraries(pico_sync_sem INTERFACE pico_sync_core pico_time)
+endif()
+
+if (NOT TARGET pico_sync_mutex)
+    pico_add_impl_library(pico_sync_mutex)
+    target_sources(pico_sync_mutex INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/mutex.c
+            )
+    target_link_libraries(pico_sync_mutex INTERFACE pico_sync_core pico_time)
+endif()
+
+if (NOT TARGET pico_sync_critical_section)
+    pico_add_impl_library(pico_sync_critical_section)
+    target_sources(pico_sync_critical_section INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/critical_section.c
+            )
+    target_link_libraries(pico_sync_critical_section INTERFACE pico_sync_core pico_time)
+endif()
+
+if (NOT TARGET pico_sync)
+    pico_add_impl_library(pico_sync)
+    target_link_libraries(pico_sync INTERFACE pico_sync_sem pico_sync_mutex pico_sync_critical_section pico_sync_core)
+endif()
+
+
diff --git a/src/common/pico_sync/critical_section.c b/src/common/pico_sync/critical_section.c
new file mode 100644
index 0000000..f28732b
--- /dev/null
+++ b/src/common/pico_sync/critical_section.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/critical_section.h"
+
+#if !PICO_NO_HARDWARE
+static_assert(sizeof(critical_section_t) == 8, "");
+#endif
+
+void critical_section_init(critical_section_t *crit_sec) {
+    critical_section_init_with_lock_num(crit_sec, (uint)spin_lock_claim_unused(true));
+}
+
+void critical_section_init_with_lock_num(critical_section_t *crit_sec, uint lock_num) {
+    crit_sec->spin_lock = spin_lock_instance(lock_num);
+    __mem_fence_release();
+}
+
+void critical_section_deinit(critical_section_t *crit_sec) {
+    spin_lock_unclaim(spin_lock_get_num(crit_sec->spin_lock));
+#ifndef NDEBUG
+    crit_sec->spin_lock = (spin_lock_t *)-1;
+#endif
+}
\ No newline at end of file
diff --git a/src/common/pico_sync/include/pico/critical_section.h b/src/common/pico_sync/include/pico/critical_section.h
new file mode 100644
index 0000000..2f94494
--- /dev/null
+++ b/src/common/pico_sync/include/pico/critical_section.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PLATFORM_CRITICAL_SECTION_H
+#define _PLATFORM_CRITICAL_SECTION_H
+
+#include "pico/lock_core.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file critical_section.h
+ *  \defgroup critical_section critical_section
+ *  \ingroup pico_sync
+ *  \brief Critical Section API for short-lived mutual exclusion safe for IRQ and multi-core
+ *
+ *  A critical section is non-reentrant, and provides mutual exclusion using a spin-lock to prevent access
+ *  from the other core, and from (higher priority) interrupts on the same core. It does the former
+ *  using a spin lock and the latter by disabling interrupts on the calling core.
+ *
+ *  Because interrupts are disabled when a critical_section is owned, uses of the critical_section
+ *  should be as short as possible.
+ */
+
+typedef struct __packed_aligned critical_section {
+    spin_lock_t *spin_lock;
+    uint32_t save;
+} critical_section_t;
+
+/*! \brief  Initialise a critical_section structure allowing the system to assign a spin lock number
+ *  \ingroup critical_section
+ *
+ * The critical section is initialized ready for use, and will use a (possibly shared) spin lock
+ * number assigned by the system. Note that in general it is unlikely that you would be nesting
+ * critical sections, however if you do so you *must* use \ref critical_section_init_with_lock_num
+ * to ensure that the spin lock's used are different.
+ *
+ * \param crit_sec Pointer to critical_section structure
+ */
+void critical_section_init(critical_section_t *crit_sec);
+
+/*! \brief  Initialise a critical_section structure assigning a specific spin lock number
+ *  \ingroup critical_section
+ * \param crit_sec Pointer to critical_section structure
+ * \param lock_num the specific spin lock number to use
+ */
+void critical_section_init_with_lock_num(critical_section_t *crit_sec, uint lock_num);
+
+/*! \brief  Enter a critical_section
+ *  \ingroup critical_section
+ *
+ * If the spin lock associated with this critical section is in use, then this
+ * method will block until it is released.
+ *
+ * \param crit_sec Pointer to critical_section structure
+ */
+static inline void critical_section_enter_blocking(critical_section_t *crit_sec) {
+    crit_sec->save = spin_lock_blocking(crit_sec->spin_lock);
+}
+
+/*! \brief  Release a critical_section
+ *  \ingroup critical_section
+ *
+ * \param crit_sec Pointer to critical_section structure
+ */
+static inline void critical_section_exit(critical_section_t *crit_sec) {
+    spin_unlock(crit_sec->spin_lock, crit_sec->save);
+}
+
+/*! \brief  De-Initialise a critical_section created by the critical_section_init method
+ *  \ingroup critical_section
+ *
+ * This method is only used to free the associated spin lock allocated via
+ * the critical_section_init method (it should not be used to de-initialize a spin lock
+ * created via critical_section_init_with_lock_num). After this call, the critical section is invalid
+ *
+ * \param crit_sec Pointer to critical_section structure
+ */
+void critical_section_deinit(critical_section_t *crit_sec);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/src/common/pico_sync/include/pico/lock_core.h b/src/common/pico_sync/include/pico/lock_core.h
new file mode 100644
index 0000000..bf8bee7
--- /dev/null
+++ b/src/common/pico_sync/include/pico/lock_core.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_LOCK_CORE_H
+#define _PICO_LOCK_CORE_H
+
+#include "pico.h"
+#include "pico/time.h"
+#include "hardware/sync.h"
+
+/** \file lock_core.h
+ *  \defgroup lock_core lock_core
+ *  \ingroup pico_sync
+ * \brief base synchronization/lock primitive support
+ *
+ * Most of the pico_sync locking primitives contain a lock_core_t structure member. This currently just holds a spin
+ * lock which is used only to protect the contents of the rest of the structure as part of implementing the synchronization
+ * primitive. As such, the spin_lock member of lock core is never still held on return from any function for the primitive.
+ *
+ * \ref critical_section is an exceptional case in that it does not have a lock_core_t and simply wraps a spin lock, providing
+ * methods to lock and unlock said spin lock.
+ *
+ * lock_core based structures work by locking the spin lock, checking state, and then deciding whether they additionally need to block
+ * or notify when the spin lock is released. In the blocking case, they will wake up again in the future, and try the process again.
+ *
+ * By default the SDK just uses the processors' events via SEV and WEV for notification and blocking as these are sufficient for
+ * cross core, and notification from interrupt handlers. However macros are defined in this file that abstract the wait
+ * and notify mechanisms to allow the SDK locking functions to effectively be used within an RTOS or other environment.
+ *
+ * When implementing an RTOS, it is desirable for the SDK synchronization primitives that wait, to block the calling task (and immediately yield),
+ * and those that notify, to wake a blocked task which isn't on processor. At least the wait macro implementation needs to be atomic with the protecting
+ * spin_lock unlock from the callers point of view; i.e. the task should unlock the spin lock when it starts its wait. Such implementation is
+ * up to the RTOS integration, however the macros are defined such that such operations are always combined into a single call
+ * (so they can be perfomed atomically) even though the default implementation does not need this, as a WFE which starts
+ * following the corresponding SEV is not missed.
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_LOCK_CORE, Enable/disable assertions in the lock core, type=bool, default=0, group=pico_sync
+#ifndef PARAM_ASSERTIONS_ENABLED_LOCK_CORE
+#define PARAM_ASSERTIONS_ENABLED_LOCK_CORE 0
+#endif
+
+/** \file lock_core.h
+ *  \ingroup lock_core
+ *
+ * Base implementation for locking primitives protected by a spin lock. The spin lock is only used to protect
+ * access to the remaining lock state (in primitives using lock_core); it is never left locked outside
+ * of the function implementations
+ */
+struct lock_core {
+    // spin lock protecting this lock's state
+    spin_lock_t *spin_lock;
+
+    // note any lock members in containing structures need not be volatile;
+    // they are protected by memory/compiler barriers when gaining and release spin locks
+};
+
+typedef struct lock_core lock_core_t;
+
+/*! \brief  Initialise a lock structure
+ *  \ingroup lock_core
+ *
+ * Inititalize a lock structure, providing the spin lock number to use for protecting internal state.
+ *
+ * \param core Pointer to the lock_core to initialize
+ * \param lock_num Spin lock number to use for the lock. As the spin lock is only used internally to the locking primitive
+ *                 method implementations, this does not need to be globally unique, however could suffer contention
+ */
+void lock_init(lock_core_t *core, uint lock_num);
+
+#ifndef lock_owner_id_t
+/*! \brief  type to use to store the 'owner' of a lock.
+ *  \ingroup lock_core
+ * By default this is int8_t as it only needs to store the core number or -1, however it may be
+ * overridden if a larger type is required (e.g. for an RTOS task id)
+ */
+#define lock_owner_id_t int8_t
+#endif
+
+#ifndef LOCK_INVALID_OWNER_ID
+/*! \brief  marker value to use for a lock_owner_id_t which does not refer to any valid owner
+ *  \ingroup lock_core
+ */
+#define LOCK_INVALID_OWNER_ID ((lock_owner_id_t)-1)
+#endif
+
+#ifndef lock_get_caller_owner_id
+/*! \brief  return the owner id for the caller
+ *  \ingroup lock_core
+ * By default this returns the calling core number, but may be overridden (e.g. to return an RTOS task id)
+ */
+#define lock_get_caller_owner_id() ((lock_owner_id_t)get_core_num())
+#ifndef lock_is_owner_id_valid
+#define lock_is_owner_id_valid(id) ((id)>=0)
+#endif
+#endif
+
+#ifndef lock_is_owner_id_valid
+#define lock_is_owner_id_valid(id) ((id) != LOCK_INVALID_OWNER_ID)
+#endif
+
+#ifndef lock_internal_spin_unlock_with_wait
+/*! \brief   Atomically unlock the lock's spin lock, and wait for a notification.
+ *  \ingroup lock_core
+ *
+ * _Atomic_ here refers to the fact that it should not be possible for a concurrent lock_internal_spin_unlock_with_notify
+ * to insert itself between the spin unlock and this wait in a way that the wait does not see the notification (i.e. causing
+ * a missed notification). In other words this method should always wake up in response to a lock_internal_spin_unlock_with_notify
+ * for the same lock, which completes after this call starts.
+ *
+ * In an ideal implementation, this method would return exactly after the corresponding lock_internal_spin_unlock_with_notify
+ * has subsequently been called on the same lock instance, however this method is free to return at _any_ point before that;
+ * this macro is _always_ used in a loop which locks the spin lock, checks the internal locking primitive state and then
+ * waits again if the calling thread should not proceed.
+ *
+ * By default this macro simply unlocks the spin lock, and then performs a WFE, but may be overridden
+ * (e.g. to actually block the RTOS task).
+ *
+ * \param lock the lock_core for the primitive which needs to block
+ * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the `PRIMASK`
+ *             state when the spin lock was acquire
+ */
+#define lock_internal_spin_unlock_with_wait(lock, save) spin_unlock((lock)->spin_lock, save), __wfe()
+#endif
+
+#ifndef lock_internal_spin_unlock_with_notify
+/*! \brief   Atomically unlock the lock's spin lock, and send a notification
+ *  \ingroup lock_core
+ *
+ * _Atomic_ here refers to the fact that it should not be possible for this notification to happen during a
+ * lock_internal_spin_unlock_with_wait in a way that that wait does not see the notification (i.e. causing
+ * a missed notification). In other words this method should always wake up any lock_internal_spin_unlock_with_wait
+ * which started before this call completes.
+ *
+ * In an ideal implementation, this method would wake up only the corresponding lock_internal_spin_unlock_with_wait
+ * that has been called on the same lock instance, however it is free to wake up any of them, as they will check
+ * their condition and then re-wait if necessary/
+ *
+ * By default this macro simply unlocks the spin lock, and then performs a SEV, but may be overridden
+ * (e.g. to actually un-block RTOS task(s)).
+ *
+ * \param lock the lock_core for the primitive which needs to block
+ * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the PRIMASK
+ *             state when the spin lock was acquire)
+ */
+#define lock_internal_spin_unlock_with_notify(lock, save) spin_unlock((lock)->spin_lock, save), __sev()
+#endif
+
+#ifndef lock_internal_spin_unlock_with_best_effort_wait_or_timeout
+/*! \brief   Atomically unlock the lock's spin lock, and wait for a notification or a timeout
+ *  \ingroup lock_core
+ *
+ * _Atomic_ here refers to the fact that it should not be possible for a concurrent lock_internal_spin_unlock_with_notify
+ * to insert itself between the spin unlock and this wait in a way that the wait does not see the notification (i.e. causing
+ * a missed notification). In other words this method should always wake up in response to a lock_internal_spin_unlock_with_notify
+ * for the same lock, which completes after this call starts.
+ *
+ * In an ideal implementation, this method would return exactly after the corresponding lock_internal_spin_unlock_with_notify
+ * has subsequently been called on the same lock instance or the timeout has been reached, however this method is free to return
+ * at _any_ point before that; this macro is _always_ used in a loop which locks the spin lock, checks the internal locking
+ * primitive state and then waits again if the calling thread should not proceed.
+ *
+ * By default this simply unlocks the spin lock, and then calls \ref best_effort_wfe_or_timeout
+ * but may be overridden (e.g. to actually block the RTOS task with a timeout).
+ *
+ * \param lock the lock_core for the primitive which needs to block
+ * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the PRIMASK
+ *             state when the spin lock was acquire)
+ * \param until the \ref absolute_time_t value
+ * \return true if the timeout has been reached
+ */
+#define lock_internal_spin_unlock_with_best_effort_wait_or_timeout(lock, save, until) ({ \
+    spin_unlock((lock)->spin_lock, save);                                                \
+    best_effort_wfe_or_timeout(until);                                                   \
+})
+#endif
+
+#ifndef sync_internal_yield_until_before
+/*! \brief   yield to other processing until some time before the requested time
+ *  \ingroup lock_core
+ *
+ * This method is provided for cases where the caller has no useful work to do
+ * until the specified time.
+ *
+ * By default this method does nothing, however it can be overridden (for example by an
+ * RTOS which is able to block the current task until the scheduler tick before
+ * the given time)
+ *
+ * \param until the \ref absolute_time_t value
+ */
+#define sync_internal_yield_until_before(until) ((void)0)
+#endif
+
+#endif
diff --git a/src/common/pico_sync/include/pico/mutex.h b/src/common/pico_sync/include/pico/mutex.h
new file mode 100644
index 0000000..e834dc5
--- /dev/null
+++ b/src/common/pico_sync/include/pico/mutex.h
@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PLATFORM_MUTEX_H
+#define _PLATFORM_MUTEX_H
+
+#include "pico/lock_core.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file mutex.h
+ *  \defgroup mutex mutex
+ *  \ingroup pico_sync
+ * \brief Mutex API for non IRQ mutual exclusion between cores
+ *
+ * Mutexes are application level locks usually used protecting data structures that might be used by
+ * multiple threads of execution. Unlike critical sections, the mutex protected code is not necessarily
+ * required/expected to complete quickly, as no other sytem wide locks are held on account of an acquired mutex.
+ *
+ * When acquired, the mutex has an owner (see \ref lock_get_caller_owner_id) which with the plain SDK is just
+ * the acquiring core, but in an RTOS it could be a task, or an IRQ handler context.
+ *
+ * Two variants of mutex are provided; \ref mutex_t (and associated mutex_ functions) is a regular mutex that cannot
+ * be acquired recursively by the same owner (a deadlock will occur if you try). \ref recursive_mutex_t
+ * (and associated recursive_mutex_ functions) is a recursive mutex that can be recursively obtained by
+ * the same caller, at the expense of some more overhead when acquiring and releasing.
+ *
+ * It is generally a bad idea to call blocking mutex_ or recursive_mutex_ functions from within an IRQ handler.
+ * It is valid to call \ref mutex_try_enter or \ref recursive_mutex_try_enter from within an IRQ handler, if the operation
+ * that would be conducted under lock can be skipped if the mutex is locked (at least by the same owner).
+ *
+ * NOTE: For backwards compatibility with version 1.2.0 of the SDK, if the define
+ * PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY is set to 1, then the the regular mutex_ functions
+ * may also be used for recursive mutexes. This flag will be removed in a future version of the SDK.
+ *
+ * See \ref critical_section.h for protecting access between multiple cores AND IRQ handlers
+ */
+
+/*! \brief recursive mutex instance
+ * \ingroup mutex
+ */
+typedef struct __packed_aligned  {
+    lock_core_t core;
+    lock_owner_id_t owner;      //! owner id LOCK_INVALID_OWNER_ID for unowned
+    uint8_t enter_count;        //! ownership count
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    bool recursive;
+#endif
+} recursive_mutex_t;
+
+/*! \brief regular (non recursive) mutex instance
+ * \ingroup mutex
+ */
+#if !PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+typedef struct __packed_aligned mutex {
+    lock_core_t core;
+    lock_owner_id_t owner;      //! owner id LOCK_INVALID_OWNER_ID for unowned
+} mutex_t;
+#else
+typedef recursive_mutex_t mutex_t; // they are one and the same when backwards compatible with SDK1.2.0
+#endif
+
+/*! \brief  Initialise a mutex structure
+ *  \ingroup mutex
+ *
+ * \param mtx Pointer to mutex structure
+ */
+void mutex_init(mutex_t *mtx);
+
+/*! \brief  Initialise a recursive mutex structure
+ *  \ingroup mutex
+ *
+ * A recursive mutex may be entered in a nested fashion by the same owner
+ *
+ * \param mtx Pointer to recursive mutex structure
+ */
+void recursive_mutex_init(recursive_mutex_t *mtx);
+
+/*! \brief  Take ownership of a mutex
+ *  \ingroup mutex
+ *
+ * This function will block until the caller can be granted ownership of the mutex.
+ * On return the caller owns the mutex
+ *
+ * \param mtx Pointer to mutex structure
+ */
+void mutex_enter_blocking(mutex_t *mtx);
+
+/*! \brief  Take ownership of a recursive mutex
+ *  \ingroup mutex
+ *
+ * This function will block until the caller can be granted ownership of the mutex.
+ * On return the caller owns the mutex
+ *
+ * \param mtx Pointer to recursive mutex structure
+ */
+void recursive_mutex_enter_blocking(recursive_mutex_t *mtx);
+
+/*! \brief Attempt to take ownership of a mutex
+ *  \ingroup mutex
+ *
+ * If the mutex wasn't owned, this will claim the mutex for the caller and return true.
+ * Otherwise (if the mutex was already owned) this will return false and the
+ * caller will NOT own the mutex.
+ *
+ * \param mtx Pointer to mutex structure
+ * \param owner_out If mutex was already owned, and this pointer is non-zero, it will be filled in with the owner id of the current owner of the mutex
+ * \return true if mutex now owned, false otherwise
+ */
+bool mutex_try_enter(mutex_t *mtx, uint32_t *owner_out);
+
+/*! \brief Attempt to take ownership of a recursive mutex
+ *  \ingroup mutex
+ *
+ * If the mutex wasn't owned or was owned by the caller, this will claim the mutex and return true.
+ * Otherwise (if the mutex was already owned by another owner) this will return false and the
+ * caller will NOT own the mutex.
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \param owner_out If mutex was already owned by another owner, and this pointer is non-zero,
+ *                  it will be filled in with the owner id of the current owner of the mutex
+ * \return true if the recursive mutex (now) owned, false otherwise
+ */
+bool recursive_mutex_try_enter(recursive_mutex_t *mtx, uint32_t *owner_out);
+
+/*! \brief Wait for mutex with timeout
+ *  \ingroup mutex
+ *
+ * Wait for up to the specific time to take ownership of the mutex. If the caller
+ * can be granted ownership of the mutex before the timeout expires, then true will be returned
+ * and the caller will own the mutex, otherwise false will be returned and the caller will NOT own the mutex.
+ *
+ * \param mtx Pointer to mutex structure
+ * \param timeout_ms The timeout in milliseconds.
+ * \return true if mutex now owned, false if timeout occurred before ownership could be granted
+ */
+bool mutex_enter_timeout_ms(mutex_t *mtx, uint32_t timeout_ms);
+
+/*! \brief Wait for recursive mutex with timeout
+ *  \ingroup mutex
+ *
+ * Wait for up to the specific time to take ownership of the recursive mutex. If the caller
+ * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires,
+ * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \param timeout_ms The timeout in milliseconds.
+ * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted
+ */
+bool recursive_mutex_enter_timeout_ms(recursive_mutex_t *mtx, uint32_t timeout_ms);
+
+/*! \brief Wait for mutex with timeout
+ *  \ingroup mutex
+ *
+ * Wait for up to the specific time to take ownership of the mutex. If the caller
+ * can be granted ownership of the mutex before the timeout expires, then true will be returned
+ * and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to mutex structure
+ * \param timeout_us The timeout in microseconds.
+ * \return true if mutex now owned, false if timeout occurred before ownership could be granted
+ */
+bool mutex_enter_timeout_us(mutex_t *mtx, uint32_t timeout_us);
+
+/*! \brief Wait for recursive mutex with timeout
+ *  \ingroup mutex
+ *
+ * Wait for up to the specific time to take ownership of the recursive mutex. If the caller
+ * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires,
+ * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to mutex structure
+ * \param timeout_us The timeout in microseconds.
+ * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted
+ */
+bool recursive_mutex_enter_timeout_us(recursive_mutex_t *mtx, uint32_t timeout_us);
+
+/*! \brief Wait for mutex until a specific time
+ *  \ingroup mutex
+ *
+ * Wait until the specific time to take ownership of the mutex. If the caller
+ * can be granted ownership of the mutex before the timeout expires, then true will be returned
+ * and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to mutex structure
+ * \param until The time after which to return if the caller cannot be granted ownership of the mutex
+ * \return true if mutex now owned, false if timeout occurred before ownership could be granted
+ */
+bool mutex_enter_block_until(mutex_t *mtx, absolute_time_t until);
+
+/*! \brief Wait for mutex until a specific time
+ *  \ingroup mutex
+ *
+ * Wait until the specific time to take ownership of the mutex. If the caller
+ * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires,
+ * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \param until The time after which to return if the caller cannot be granted ownership of the mutex
+ * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted
+ */
+bool recursive_mutex_enter_block_until(recursive_mutex_t *mtx, absolute_time_t until);
+
+/*! \brief  Release ownership of a mutex
+ *  \ingroup mutex
+ *
+ * \param mtx Pointer to mutex structure
+ */
+void mutex_exit(mutex_t *mtx);
+
+/*! \brief  Release ownership of a recursive mutex
+ *  \ingroup mutex
+ *
+ * \param mtx Pointer to recursive mutex structure
+ */
+void recursive_mutex_exit(recursive_mutex_t *mtx);
+
+/*! \brief Test for mutex initialized state
+ *  \ingroup mutex
+ *
+ * \param mtx Pointer to mutex structure
+ * \return true if the mutex is initialized, false otherwise
+ */
+static inline bool mutex_is_initialized(mutex_t *mtx) {
+    return mtx->core.spin_lock != 0;
+}
+
+/*! \brief Test for recursive mutex initialized state
+ *  \ingroup mutex
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \return true if the recursive mutex is initialized, false otherwise
+ */
+static inline bool recursive_mutex_is_initialized(recursive_mutex_t *mtx) {
+    return mtx->core.spin_lock != 0;
+}
+
+/*! \brief Helper macro for static definition of mutexes
+ *  \ingroup mutex
+ *
+ * A mutex defined as follows:
+ *
+ * ```c
+ * auto_init_mutex(my_mutex);
+ * ```
+ *
+ * Is equivalent to doing
+ *
+ * ```c
+ * static mutex_t my_mutex;
+ *
+ * void my_init_function() {
+ *    mutex_init(&my_mutex);
+ * }
+ * ```
+ *
+ * But the initialization of the mutex is performed automatically during runtime initialization
+ */
+#define auto_init_mutex(name) static __attribute__((section(".mutex_array"))) mutex_t name
+
+/*! \brief Helper macro for static definition of recursive mutexes
+ *  \ingroup mutex
+ *
+ * A recursive mutex defined as follows:
+ *
+ * ```c
+ * auto_init_recursive_mutex(my_recursive_mutex);
+ * ```
+ *
+ * Is equivalent to doing
+ *
+ * ```c
+ * static recursive_mutex_t my_recursive_mutex;
+ *
+ * void my_init_function() {
+ *    recursive_mutex_init(&my_recursive_mutex);
+ * }
+ * ```
+ *
+ * But the initialization of the mutex is performed automatically during runtime initialization
+ */
+#define auto_init_recursive_mutex(name) static __attribute__((section(".mutex_array"))) recursive_mutex_t name = { .core.spin_lock = (spin_lock_t *)1 /* marker for runtime_init */ }
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/src/common/pico_sync/include/pico/sem.h b/src/common/pico_sync/include/pico/sem.h
new file mode 100644
index 0000000..6244e32
--- /dev/null
+++ b/src/common/pico_sync/include/pico/sem.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PLATFORM_SEM_H
+#define _PLATFORM_SEM_H
+
+#include "pico/lock_core.h"
+
+/** \file sem.h
+ *  \defgroup sem sem
+ *  \ingroup pico_sync
+ *  \brief Semaphore API for restricting access to a resource
+ *
+ * A semaphore holds a number of available permits. `sem_acquire` methods will acquire a permit if available
+ * (reducing the available count by 1) or block if the number of available permits is 0.
+ * \ref sem_release() increases the number of available permits by one potentially unblocking a `sem_acquire` method.
+ *
+ * Note that \ref sem_release() may be called an arbitrary number of times, however the number of available
+ * permits is capped to the max_permit value specified during semaphore initialization.
+ *
+ * Although these semaphore related functions can be used from IRQ handlers, it is obviously preferable to only
+ * release semaphores from within an IRQ handler (i.e. avoid blocking)
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+typedef struct __packed_aligned semaphore {
+    struct lock_core core;
+    int16_t permits;
+    int16_t max_permits;
+} semaphore_t;
+
+
+/*! \brief  Initialise a semaphore structure
+ *  \ingroup sem
+ *
+ * \param sem Pointer to semaphore structure
+ * \param initial_permits How many permits are initially acquired
+ * \param max_permits  Total number of permits allowed for this semaphore
+ */
+void sem_init(semaphore_t *sem, int16_t initial_permits, int16_t max_permits);
+
+/*! \brief  Return number of available permits on the semaphore
+ *  \ingroup sem
+ *
+ * \param sem Pointer to semaphore structure
+ * \return The number of permits available on the semaphore.
+ */
+int sem_available(semaphore_t *sem);
+
+/*! \brief  Release a permit on a semaphore
+ *  \ingroup sem
+ *
+ * Increases the number of permits by one (unless the number of permits is already at the maximum).
+ * A blocked `sem_acquire` will be released if the number of permits is increased.
+ *
+ * \param sem Pointer to semaphore structure
+ * \return true if the number of permits available was increased.
+ */
+bool sem_release(semaphore_t *sem);
+
+/*! \brief  Reset semaphore to a specific number of available permits
+ *  \ingroup sem
+ *
+ * Reset value should be from 0 to the max_permits specified in the init function
+ *
+ * \param sem Pointer to semaphore structure
+ * \param permits the new number of available permits
+ */
+void sem_reset(semaphore_t *sem, int16_t permits);
+
+/*! \brief  Acquire a permit from the semaphore
+ *  \ingroup sem
+ *
+ * This function will block and wait if no permits are available.
+ *
+ * \param sem Pointer to semaphore structure
+ */
+void sem_acquire_blocking(semaphore_t *sem);
+
+/*! \brief  Acquire a permit from a semaphore, with timeout
+ *  \ingroup sem
+ *
+ * This function will block and wait if no permits are available, until the
+ * defined timeout has been reached. If the timeout is reached the function will
+ * return false, otherwise it will return true.
+ *
+ * \param sem Pointer to semaphore structure
+ * \param timeout_ms Time to wait to acquire the semaphore, in milliseconds.
+ * \return false if timeout reached, true if permit was acquired.
+ */
+bool sem_acquire_timeout_ms(semaphore_t *sem, uint32_t timeout_ms);
+
+/*! \brief  Acquire a permit from a semaphore, with timeout
+ *  \ingroup sem
+ *
+ * This function will block and wait if no permits are available, until the
+ * defined timeout has been reached. If the timeout is reached the function will
+ * return false, otherwise it will return true.
+ *
+ * \param sem Pointer to semaphore structure
+ * \param timeout_us Time to wait to acquire the semaphore, in microseconds.
+ * \return false if timeout reached, true if permit was acquired.
+ */
+bool sem_acquire_timeout_us(semaphore_t *sem, uint32_t timeout_us);
+
+/*! \brief Wait to acquire a permit from a semaphore until a specific time
+ *  \ingroup sem
+ *
+ * This function will block and wait if no permits are available, until the
+ * specified timeout time. If the timeout is reached the function will
+ * return false, otherwise it will return true.
+ *
+ * \param sem Pointer to semaphore structure
+ * \param until The time after which to return if the sem is not available.
+ * \return true if permit was acquired, false if the until time was reached before
+ * acquiring.
+ */
+bool sem_acquire_block_until(semaphore_t *sem, absolute_time_t until);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/src/common/pico_sync/include/pico/sync.h b/src/common/pico_sync/include/pico/sync.h
new file mode 100644
index 0000000..041bfd7
--- /dev/null
+++ b/src/common/pico_sync/include/pico/sync.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_SYNC_H
+#define _PICO_SYNC_H
+
+/** \file pico/sync.h
+ *  \defgroup pico_sync pico_sync
+ * Synchronization primitives and mutual exclusion
+ */
+
+#include "pico/sem.h"
+#include "pico/mutex.h"
+#include "pico/critical_section.h"
+
+#endif
diff --git a/src/common/pico_sync/lock_core.c b/src/common/pico_sync/lock_core.c
new file mode 100644
index 0000000..1bc8df9
--- /dev/null
+++ b/src/common/pico_sync/lock_core.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/lock_core.h"
+
+void lock_init(lock_core_t *core, uint lock_num) {
+    valid_params_if(LOCK_CORE, lock_num < NUM_SPIN_LOCKS);
+    core->spin_lock = spin_lock_instance(lock_num);
+}
+
diff --git a/src/common/pico_sync/mutex.c b/src/common/pico_sync/mutex.c
new file mode 100644
index 0000000..3ea81c7
--- /dev/null
+++ b/src/common/pico_sync/mutex.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/mutex.h"
+#include "pico/time.h"
+
+void mutex_init(mutex_t *mtx) {
+    lock_init(&mtx->core, next_striped_spin_lock_num());
+    mtx->owner = LOCK_INVALID_OWNER_ID;
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    mtx->recursive = false;
+#endif
+    __mem_fence_release();
+}
+
+void recursive_mutex_init(recursive_mutex_t *mtx) {
+    lock_init(&mtx->core, next_striped_spin_lock_num());
+    mtx->owner = LOCK_INVALID_OWNER_ID;
+    mtx->enter_count = 0;
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    mtx->recursive = true;
+#endif
+    __mem_fence_release();
+}
+
+void __time_critical_func(mutex_enter_blocking)(mutex_t *mtx) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    if (mtx->recursive) {
+        recursive_mutex_enter_blocking(mtx);
+        return;
+    }
+#endif
+    lock_owner_id_t caller = lock_get_caller_owner_id();
+    do {
+        uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+        if (!lock_is_owner_id_valid(mtx->owner)) {
+            mtx->owner = caller;
+            spin_unlock(mtx->core.spin_lock, save);
+            break;
+        }
+        lock_internal_spin_unlock_with_wait(&mtx->core, save);
+    } while (true);
+}
+
+void __time_critical_func(recursive_mutex_enter_blocking)(recursive_mutex_t *mtx) {
+    lock_owner_id_t caller = lock_get_caller_owner_id();
+    do {
+        uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+        if (mtx->owner == caller || !lock_is_owner_id_valid(mtx->owner)) {
+            mtx->owner = caller;
+            uint __unused total = ++mtx->enter_count;
+            spin_unlock(mtx->core.spin_lock, save);
+            assert(total); // check for overflow
+            return;
+        } else {
+            lock_internal_spin_unlock_with_wait(&mtx->core, save);
+        }
+    } while (true);
+}
+
+bool __time_critical_func(mutex_try_enter)(mutex_t *mtx, uint32_t *owner_out) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    if (mtx->recursive) {
+        return recursive_mutex_try_enter(mtx, owner_out);
+    }
+#endif
+    bool entered;
+    uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+    if (!lock_is_owner_id_valid(mtx->owner)) {
+        mtx->owner = lock_get_caller_owner_id();
+        entered = true;
+    } else {
+        if (owner_out) *owner_out = (uint32_t) mtx->owner;
+        entered = false;
+    }
+    spin_unlock(mtx->core.spin_lock, save);
+    return entered;
+}
+
+bool __time_critical_func(recursive_mutex_try_enter)(recursive_mutex_t *mtx, uint32_t *owner_out) {
+    bool entered;
+    lock_owner_id_t caller = lock_get_caller_owner_id();
+    uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+    if (!lock_is_owner_id_valid(mtx->owner) || mtx->owner == caller) {
+        mtx->owner = caller;
+        uint __unused total = ++mtx->enter_count;
+        assert(total); // check for overflow
+        entered = true;
+    } else {
+        if (owner_out) *owner_out = (uint32_t) mtx->owner;
+        entered = false;
+    }
+    spin_unlock(mtx->core.spin_lock, save);
+    return entered;
+}
+
+bool __time_critical_func(mutex_enter_timeout_ms)(mutex_t *mtx, uint32_t timeout_ms) {
+    return mutex_enter_block_until(mtx, make_timeout_time_ms(timeout_ms));
+}
+
+bool __time_critical_func(recursive_mutex_enter_timeout_ms)(recursive_mutex_t *mtx, uint32_t timeout_ms) {
+    return recursive_mutex_enter_block_until(mtx, make_timeout_time_ms(timeout_ms));
+}
+
+bool __time_critical_func(mutex_enter_timeout_us)(mutex_t *mtx, uint32_t timeout_us) {
+    return mutex_enter_block_until(mtx, make_timeout_time_us(timeout_us));
+}
+
+bool __time_critical_func(recursive_mutex_enter_timeout_us)(recursive_mutex_t *mtx, uint32_t timeout_us) {
+    return recursive_mutex_enter_block_until(mtx, make_timeout_time_us(timeout_us));
+}
+
+bool __time_critical_func(mutex_enter_block_until)(mutex_t *mtx, absolute_time_t until) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    if (mtx->recursive) {
+        return recursive_mutex_enter_block_until(mtx, until);
+    }
+#endif
+    assert(mtx->core.spin_lock);
+    lock_owner_id_t caller = lock_get_caller_owner_id();
+    do {
+        uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+        if (!lock_is_owner_id_valid(mtx->owner)) {
+            mtx->owner = caller;
+            spin_unlock(mtx->core.spin_lock, save);
+            return true;
+        } else {
+            if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&mtx->core, save, until)) {
+                // timed out
+                return false;
+            }
+            // not timed out; spin lock already unlocked, so loop again
+        }
+    } while (true);
+}
+
+bool __time_critical_func(recursive_mutex_enter_block_until)(recursive_mutex_t *mtx, absolute_time_t until) {
+    assert(mtx->core.spin_lock);
+    lock_owner_id_t caller = lock_get_caller_owner_id();
+    do {
+        uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+        if (!lock_is_owner_id_valid(mtx->owner) || mtx->owner == caller) {
+            mtx->owner = caller;
+            uint __unused total = ++mtx->enter_count;
+            spin_unlock(mtx->core.spin_lock, save);
+            assert(total); // check for overflow
+            return true;
+        } else {
+            if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&mtx->core, save, until)) {
+                // timed out
+                return false;
+            }
+            // not timed out; spin lock already unlocked, so loop again
+        }
+    } while (true);
+}
+
+void __time_critical_func(mutex_exit)(mutex_t *mtx) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+    if (mtx->recursive) {
+        recursive_mutex_exit(mtx);
+        return;
+    }
+#endif
+    uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+    assert(lock_is_owner_id_valid(mtx->owner));
+    mtx->owner = LOCK_INVALID_OWNER_ID;
+    lock_internal_spin_unlock_with_notify(&mtx->core, save);
+}
+
+void __time_critical_func(recursive_mutex_exit)(recursive_mutex_t *mtx) {
+    uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+    assert(lock_is_owner_id_valid(mtx->owner));
+    assert(mtx->enter_count);
+    if (!--mtx->enter_count) {
+        mtx->owner = LOCK_INVALID_OWNER_ID;
+        lock_internal_spin_unlock_with_notify(&mtx->core, save);
+    } else {
+        spin_unlock(mtx->core.spin_lock, save);
+    }
+}
\ No newline at end of file
diff --git a/src/common/pico_sync/sem.c b/src/common/pico_sync/sem.c
new file mode 100644
index 0000000..06b4946
--- /dev/null
+++ b/src/common/pico_sync/sem.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/sem.h"
+#include "pico/time.h"
+
+void sem_init(semaphore_t *sem, int16_t initial_permits, int16_t max_permits) {
+    lock_init(&sem->core, next_striped_spin_lock_num());
+    sem->permits = initial_permits;
+    sem->max_permits = max_permits;
+    __mem_fence_release();
+}
+
+int __time_critical_func(sem_available)(semaphore_t *sem) {
+    return *(volatile typeof(sem->permits) *) &sem->permits;
+}
+
+void __time_critical_func(sem_acquire_blocking)(semaphore_t *sem) {
+    do {
+        uint32_t save = spin_lock_blocking(sem->core.spin_lock);
+        if (sem->permits > 0) {
+            sem->permits--;
+            lock_internal_spin_unlock_with_notify(&sem->core, save);
+            break;
+        }
+        lock_internal_spin_unlock_with_wait(&sem->core, save);
+    } while (true);
+}
+
+bool __time_critical_func(sem_acquire_timeout_ms)(semaphore_t *sem, uint32_t timeout_ms) {
+    return sem_acquire_block_until(sem, make_timeout_time_ms(timeout_ms));
+}
+
+bool __time_critical_func(sem_acquire_timeout_us)(semaphore_t *sem, uint32_t timeout_us) {
+    return sem_acquire_block_until(sem, make_timeout_time_us(timeout_us));
+}
+
+bool __time_critical_func(sem_acquire_block_until)(semaphore_t *sem, absolute_time_t until) {
+    do {
+        uint32_t save = spin_lock_blocking(sem->core.spin_lock);
+        if (sem->permits > 0) {
+            sem->permits--;
+            lock_internal_spin_unlock_with_notify(&sem->core, save);
+            return true;
+        }
+        if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&sem->core, save, until)) {
+            return false;
+        }
+    } while (true);
+}
+
+// todo this should really have a blocking variant for when permits are maxed out
+bool __time_critical_func(sem_release)(semaphore_t *sem) {
+    uint32_t save = spin_lock_blocking(sem->core.spin_lock);
+    int32_t count = sem->permits;
+    if (count < sem->max_permits) {
+        sem->permits = (int16_t)(count + 1);
+        lock_internal_spin_unlock_with_notify(&sem->core, save);
+        return true;
+    } else {
+        spin_unlock(sem->core.spin_lock, save);
+        return false;
+    }
+}
+
+void __time_critical_func(sem_reset)(semaphore_t *sem, int16_t permits) {
+    assert(permits >= 0 && permits <= sem->max_permits);
+    uint32_t save = spin_lock_blocking(sem->core.spin_lock);
+    if (permits > sem->permits) {
+        sem->permits = permits;
+        lock_internal_spin_unlock_with_notify(&sem->core, save);
+    } else {
+        sem->permits = permits;
+        spin_unlock(sem->core.spin_lock, save);
+    }
+}
diff --git a/src/common/pico_time/CMakeLists.txt b/src/common/pico_time/CMakeLists.txt
new file mode 100644
index 0000000..9e497a7
--- /dev/null
+++ b/src/common/pico_time/CMakeLists.txt
@@ -0,0 +1,16 @@
+if (NOT TARGET pico_time_headers)
+    add_library(pico_time_headers INTERFACE)
+
+    target_include_directories(pico_time_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+    target_link_libraries(pico_time_headers INTERFACE hardware_timer)
+endif()
+
+if (NOT TARGET pico_time)
+    pico_add_impl_library(pico_time)
+
+    target_sources(pico_time INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/time.c
+            ${CMAKE_CURRENT_LIST_DIR}/timeout_helper.c)
+    target_link_libraries(pico_time INTERFACE pico_time_headers pico_sync pico_util)
+endif()
diff --git a/src/common/pico_time/include/pico/time.h b/src/common/pico_time/include/pico/time.h
new file mode 100644
index 0000000..c00b7a8
--- /dev/null
+++ b/src/common/pico_time/include/pico/time.h
@@ -0,0 +1,716 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_TIME_H
+#define _PICO_TIME_H
+
+#include "pico.h"
+#include "hardware/timer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file time.h
+ *  \defgroup pico_time pico_time
+ *
+ * API for accurate timestamps, sleeping, and time based callbacks
+ *
+ * \note The functions defined here provide a much more powerful and user friendly wrapping around the
+ * low level hardware timer functionality. For these functions (and any other SDK functionality
+ * e.g. timeouts, that relies on them) to work correctly, the hardware timer should not be modified. i.e. it is expected
+ * to be monotonically increasing once per microsecond. Fortunately there is no need to modify the hardware
+ * timer as any functionality you can think of that isn't already covered here can easily be modelled
+ * by adding or subtracting a constant value from the unmodified hardware timer.
+ *
+ * \sa \ref hardware_timer
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_TIME, Enable/disable assertions in the time module, type=bool, default=0, group=pico_time
+#ifndef PARAM_ASSERTIONS_ENABLED_TIME
+#define PARAM_ASSERTIONS_ENABLED_TIME 0
+#endif
+
+// PICO_CONFIG: PICO_TIME_SLEEP_OVERHEAD_ADJUST_US, How many microseconds to wake up early (and then busy_wait) to account for timer overhead when sleeping in low power mode, type=int, default=6, group=pico_time
+#ifndef PICO_TIME_SLEEP_OVERHEAD_ADJUST_US
+#define PICO_TIME_SLEEP_OVERHEAD_ADJUST_US 6
+#endif
+/*!
+ * \defgroup timestamp timestamp
+ *  \ingroup pico_time
+ * \brief Timestamp functions relating to points in time (including the current time)
+ *
+ * These are functions for dealing with timestamps (i.e. instants in time) represented by the type absolute_time_t. This opaque
+ * type is provided to help prevent accidental mixing of timestamps and relative time values.
+ */
+
+/*! \brief Return a representation of the current time.
+ * \ingroup timestamp
+ *
+ * Returns an opaque high fidelity representation of the current time sampled during the call.
+ *
+ * \return the absolute time (now) of the hardware timer
+ *
+ * \sa absolute_time_t
+ * \sa sleep_until()
+ * \sa time_us_64()
+ */
+static inline absolute_time_t get_absolute_time(void) {
+    absolute_time_t t;
+    update_us_since_boot(&t, time_us_64());
+    return t;
+}
+
+static inline uint32_t us_to_ms(uint64_t us) {
+    if (us >> 32u) {
+        return (uint32_t)(us / 1000u);
+    } else {
+        return ((uint32_t)us) / 1000u;
+    }
+}
+
+/*! fn to_ms_since_boot
+ * \ingroup timestamp
+ * \brief Convert a timestamp into a number of milliseconds since boot.
+ * \param t an absolute_time_t value to convert
+ * \return the number of microseconds since boot represented by t
+ * \sa to_us_since_boot()
+ */
+static inline uint32_t to_ms_since_boot(absolute_time_t t) {
+    uint64_t us = to_us_since_boot(t);
+    return us_to_ms(us);
+}
+
+/*! \brief Return a timestamp value obtained by adding a number of microseconds to another timestamp
+ * \ingroup timestamp
+ *
+ * \param t the base timestamp
+ * \param us the number of microseconds to add
+ * \return the timestamp representing the resulting time
+ */
+static inline absolute_time_t delayed_by_us(const absolute_time_t t, uint64_t us) {
+    absolute_time_t t2;
+    uint64_t base = to_us_since_boot(t);
+    uint64_t delayed = base + us;
+    if (delayed < base) {
+        delayed = (uint64_t)-1;
+    }
+    update_us_since_boot(&t2, delayed);
+    return t2;
+}
+
+/*! \brief Return a timestamp value obtained by adding a number of milliseconds to another timestamp
+ * \ingroup timestamp
+ *
+ * \param t the base timestamp
+ * \param ms the number of milliseconds to add
+ * \return the timestamp representing the resulting time
+ */
+static inline absolute_time_t delayed_by_ms(const absolute_time_t t, uint32_t ms) {
+    absolute_time_t t2;
+    uint64_t base = to_us_since_boot(t);
+    uint64_t delayed = base + ms * 1000ull;
+    if (delayed < base) {
+        delayed = (uint64_t)-1;
+    }
+    update_us_since_boot(&t2, delayed);
+    return t2;
+}
+
+/*! \brief Convenience method to get the timestamp a number of microseconds from the current time
+ * \ingroup timestamp
+ *
+ * \param us the number of microseconds to add to the current timestamp
+ * \return the future timestamp
+ */
+static inline absolute_time_t make_timeout_time_us(uint64_t us) {
+    return delayed_by_us(get_absolute_time(), us);
+}
+
+/*! \brief Convenience method to get the timestamp a number of milliseconds from the current time
+ * \ingroup timestamp
+ *
+ * \param ms the number of milliseconds to add to the current timestamp
+ * \return the future timestamp
+ */
+static inline absolute_time_t make_timeout_time_ms(uint32_t ms) {
+    return delayed_by_ms(get_absolute_time(), ms);
+}
+
+/*! \brief Return the difference in microseconds between two timestamps
+ * \ingroup timestamp
+ *
+ * \note be careful when diffing against large timestamps (e.g. \ref at_the_end_of_time)
+ * as the signed integer may overflow.
+ *
+ * \param from the first timestamp
+ * \param to the second timestamp
+ * \return the number of microseconds between the two timestamps (positive if `to` is after `from` except
+ * in case of overflow)
+ */
+static inline int64_t absolute_time_diff_us(absolute_time_t from, absolute_time_t to) {
+    return (int64_t)(to_us_since_boot(to) - to_us_since_boot(from));
+}
+
+/*! \brief The timestamp representing the end of time; this is actually not the maximum possible
+ * timestamp, but is set to 0x7fffffff_ffffffff microseconds to avoid sign overflows with time
+ * arithmetic. This is still over 7 million years, so should be sufficient.
+ * \ingroup timestamp
+ */
+extern const absolute_time_t at_the_end_of_time;
+
+/*! \brief The timestamp representing a null timestamp
+ * \ingroup timestamp
+ */
+extern const absolute_time_t nil_time;
+
+/*! \brief Determine if the given timestamp is nil
+ * \ingroup timestamp
+ *  \param t the timestamp
+ *  \return true if the timestamp is nil
+ *  \sa nil_time
+ */
+static inline bool is_nil_time(absolute_time_t t) {
+    return !to_us_since_boot(t);
+}
+
+/*!
+ * \defgroup sleep sleep
+ * \ingroup pico_time
+ * \brief Sleep functions for delaying execution in a lower power state.
+ *
+ * These functions allow the calling core to sleep. This is a lower powered sleep; waking and re-checking time on every processor
+ * event (WFE)
+ *
+ * \note  These functions should not be called from an IRQ handler.
+ *
+ * \note  Lower powered sleep requires use of the \link alarm_pool_get_default default alarm pool\endlink which may
+ * be disabled by the #PICO_TIME_DEFAULT_ALARM_POOL_DISABLED define or currently full in which case these functions
+ * become busy waits instead.
+ *
+ * \note  Whilst \a sleep_ functions are preferable to \a busy_wait functions from a power perspective, the \a busy_wait equivalent function
+ * may return slightly sooner after the target is reached.
+ *
+ * \sa busy_wait_until() \sa busy_wait_us() \sa busy_wait_us_32()
+ */
+
+/*! \brief Wait until after the given timestamp to return
+ * \ingroup sleep
+ *
+ * \note  This method attempts to perform a lower power (WFE) sleep
+ *
+ * \param target the time after which to return
+ * \sa sleep_us()
+ * \sa busy_wait_until()
+ * */
+void sleep_until(absolute_time_t target);
+
+/*! \brief Wait for the given number of microseconds before returning
+ * \ingroup sleep
+ *
+ * \note This method attempts to perform a lower power (WFE) sleep
+ *
+ * \param us the number of microseconds to sleep
+ * \sa busy_wait_us()
+ */
+void sleep_us(uint64_t us);
+
+/*! \brief Wait for the given number of milliseconds before returning
+ * \ingroup sleep
+ *
+ * \note This method attempts to perform a lower power sleep (using WFE) as much as possible.
+ *
+ * \param ms the number of milliseconds to sleep
+ */
+void sleep_ms(uint32_t ms);
+
+/*! \brief Helper method for blocking on a timeout
+ * \ingroup sleep
+ *
+ * This method will return in response to an event (as per __wfe) or
+ * when the target time is reached, or at any point before.
+ *
+ * This method can be used to implement a lower power polling loop waiting on
+ * some condition signalled by an event (__sev()).
+ *
+ * This is called \a best_effort because under certain circumstances (notably the default timer pool
+ * being disabled or full) the best effort is simply to return immediately without a __wfe, thus turning the calling
+ * code into a busy wait.
+ *
+ * Example usage:
+ * ```c
+ * bool my_function_with_timeout_us(uint64_t timeout_us) {
+ *     absolute_time_t timeout_time = make_timeout_time_us(timeout_us);
+ *     do {
+ *         // each time round the loop, we check to see if the condition
+ *         // we are waiting on has happened
+ *         if (my_check_done()) {
+ *             // do something
+ *             return true;
+ *         }
+ *         // will try to sleep until timeout or the next processor event 
+ *     } while (!best_effort_wfe_or_timeout(timeout_time));
+ *     return false; // timed out
+ * }
+ * ```
+ *
+ * @param timeout_timestamp the timeout time
+ * @return true if the target time is reached, false otherwise
+ */
+bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp);
+
+/*!
+ * \defgroup alarm alarm
+ * \ingroup pico_time
+ * \brief Alarm functions for scheduling future execution
+ *
+ *  Alarms are added to alarm pools, which may hold a certain fixed number of active alarms. Each alarm pool
+ *  utilizes one of four underlying hardware alarms, thus you may have up to four alarm pools. An alarm pool
+ *  calls (except when the callback would happen before or during being set) the callback on the core from which
+ *  the alarm pool was created. Callbacks are called from the hardware alarm IRQ handler, so care must
+ *  be taken in their implementation.
+ *
+ *  A default pool is created  the core specified by PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM
+ *  on core 0, and may be used by the method variants that take no alarm pool parameter.
+ *
+ * \sa struct alarm_pool
+ * \sa hardware_timer
+ */
+
+// PICO_CONFIG: PICO_TIME_DEFAULT_ALARM_POOL_DISABLED, Disable the default alarm pool, type=bool, default=0, advanced=true, group=pico_time
+#ifndef PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+/*!
+ * \brief If 1 then the default alarm pool is disabled (so no hardware alarm is claimed for the pool)
+ *
+ * \note Setting to 1 may cause some code not to compile as default timer pool related methods are removed
+ *
+ * \note When the default alarm pool is disabled, \a sleep_ methods and timeouts are no longer lower powered
+ * (they become \a busy_wait_)
+ *
+ * \ingroup alarm
+ * \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM
+ * \sa alarm_pool_get_default()
+ */
+#define PICO_TIME_DEFAULT_ALARM_POOL_DISABLED 0
+#endif
+
+// PICO_CONFIG: PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM, Select which HW alarm is used for the default alarm pool, min=0, max=3, default=3, advanced=true, group=pico_time
+#ifndef PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM
+/*!
+ * \brief Selects which hardware alarm is used for the default alarm pool
+ * \ingroup alarm
+ * \sa alarm_pool_get_default()
+ */
+#define PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM 3
+#endif
+
+// PICO_CONFIG: PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS, Selects the maximum number of concurrent timers in the default alarm pool, min=0, max=255, default=16, advanced=true, group=pico_time
+#ifndef PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS
+/*!
+ * \brief Selects the maximum number of concurrent timers in the default alarm pool
+ * \ingroup alarm
+ *
+ * \note For implementation reasons this is limited to PICO_PHEAP_MAX_ENTRIES which defaults to 255
+ * \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM
+ * \sa alarm_pool_get_default()
+ */
+#define PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS 16
+#endif
+
+/**
+ * \brief The identifier for an alarm
+ *
+ * \note this identifier is signed because -1 is used as an error condition when creating alarms
+ *
+ * \note alarm ids may be reused, however for convenience the implementation makes an attempt to defer
+ * reusing as long as possible. You should certainly expect it to be hundreds of ids before one is
+ * reused, although in most cases it is more. Nonetheless care must still be taken when cancelling
+ * alarms or other functionality based on alarms when the alarm may have expired, as eventually
+ * the alarm id may be reused for another alarm.
+ *
+ * \ingroup alarm
+ */
+typedef int32_t alarm_id_t; // note this is signed because we use -1 as a meaningful error value
+
+/**
+ * \brief User alarm callback
+ * \ingroup alarm
+ * \param id the alarm_id as returned when the alarm was added
+ * \param user_data the user data passed when the alarm was added
+ * \return <0 to reschedule the same alarm this many us from the time the alarm was previously scheduled to fire
+ * \return >0 to reschedule the same alarm this many us from the time this method returns
+ * \return 0 to not reschedule the alarm
+ */
+typedef int64_t (*alarm_callback_t)(alarm_id_t id, void *user_data);
+
+typedef struct alarm_pool alarm_pool_t;
+
+/**
+ * \brief Create the default alarm pool (if not already created or disabled)
+ * \ingroup alarm
+ */
+void alarm_pool_init_default(void);
+
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+/*!
+ * \brief The default alarm pool used when alarms are added without specifying an alarm pool,
+ *        and also used by the SDK to support lower power sleeps and timeouts.
+ *
+ * \ingroup alarm
+ * \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM
+ */
+alarm_pool_t *alarm_pool_get_default(void);
+#endif
+
+/**
+ * \brief Create an alarm pool
+ *
+ * The alarm pool will call callbacks from an alarm IRQ Handler on the core of this function is called from.
+ *
+ * In many situations there is never any need for anything other than the default alarm pool, however you
+ * might want to create another if you want alarm callbacks on core 1 or require alarm pools of
+ * different priority (IRQ priority based preemption of callbacks)
+ *
+ * \note This method will hard assert if the hardware alarm is already claimed.
+ *
+ * \ingroup alarm
+ * \param hardware_alarm_num the hardware alarm to use to back this pool
+ * \param max_timers the maximum number of timers
+ *        \note For implementation reasons this is limited to PICO_PHEAP_MAX_ENTRIES which defaults to 255
+ * \sa alarm_pool_get_default()
+ * \sa hardware_claiming
+ */
+alarm_pool_t *alarm_pool_create(uint hardware_alarm_num, uint max_timers);
+
+/**
+ * \brief Return the hardware alarm used by an alarm pool
+ * \ingroup alarm
+ * \param pool the pool
+ * \return the hardware alarm used by the pool
+ */
+uint alarm_pool_hardware_alarm_num(alarm_pool_t *pool);
+
+/**
+ * \brief Destroy the alarm pool, cancelling all alarms and freeing up the underlying hardware alarm
+ * \ingroup alarm
+ * \param pool the pool
+ * \return the hardware alarm used by the pool
+ */
+void alarm_pool_destroy(alarm_pool_t *pool);
+
+/*!
+ * \brief Add an alarm callback to be called at a specific time
+ * \ingroup alarm
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core the alarm pool was created on. If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback)
+ * @param time the timestamp when (after which) the callback should fire
+ * @param callback the callback function
+ * @param user_data user data to pass to the callback function
+ * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
+ * @return >0 the alarm id for an active (at the time of return) alarm
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
+ * @return -1 if there were no alarm slots available
+ */
+alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past);
+
+/*!
+ * \brief Add an alarm callback to be called after a delay specified in microseconds
+ * \ingroup alarm
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core the alarm pool was created on. If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback)
+ * @param us the delay (from now) in microseconds when (after which) the callback should fire
+ * @param callback the callback function
+ * @param user_data user data to pass to the callback function
+ * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
+ * @return >0 the alarm id
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
+ * @return -1 if there were no alarm slots available
+ */
+static inline alarm_id_t alarm_pool_add_alarm_in_us(alarm_pool_t *pool, uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) {
+    return alarm_pool_add_alarm_at(pool, delayed_by_us(get_absolute_time(), us), callback, user_data, fire_if_past);
+}
+
+/*!
+ * \brief Add an alarm callback to be called after a delay specified in milliseconds
+ * \ingroup alarm
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core the alarm pool was created on. If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback)
+ * @param ms the delay (from now) in milliseconds when (after which) the callback should fire
+ * @param callback the callback function
+ * @param user_data user data to pass to the callback function
+ * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
+ * @return >0 the alarm id
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
+ * @return -1 if there were no alarm slots available
+ */
+static inline alarm_id_t alarm_pool_add_alarm_in_ms(alarm_pool_t *pool, uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) {
+    return alarm_pool_add_alarm_at(pool, delayed_by_ms(get_absolute_time(), ms), callback, user_data, fire_if_past);
+}
+
+/*!
+ * \brief Cancel an alarm
+ * \ingroup alarm
+ * \param pool the alarm_pool containing the alarm
+ * \param alarm_id the alarm
+ * \return true if the alarm was cancelled, false if it didn't exist
+ * \sa alarm_id_t for a note on reuse of IDs
+ */
+bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id);
+
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+/*!
+ * \brief Add an alarm callback to be called at a specific time
+ * \ingroup alarm
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param time the timestamp when (after which) the callback should fire
+ * @param callback the callback function
+ * @param user_data user data to pass to the callback function
+ * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
+ * @return >0 the alarm id
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
+ * @return -1 if there were no alarm slots available
+ */
+static inline alarm_id_t add_alarm_at(absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past) {
+    return alarm_pool_add_alarm_at(alarm_pool_get_default(), time, callback, user_data, fire_if_past);
+}
+
+/*!
+ * \brief Add an alarm callback to be called after a delay specified in microseconds
+ * \ingroup alarm
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param us the delay (from now) in microseconds when (after which) the callback should fire
+ * @param callback the callback function
+ * @param user_data user data to pass to the callback function
+ * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
+ * @return >0 the alarm id
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
+ * @return -1 if there were no alarm slots available
+ */
+static inline alarm_id_t add_alarm_in_us(uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) {
+    return alarm_pool_add_alarm_in_us(alarm_pool_get_default(), us, callback, user_data, fire_if_past);
+}
+
+/*!
+ * \brief Add an alarm callback to be called after a delay specified in milliseconds
+ * \ingroup alarm
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param ms the delay (from now) in milliseconds when (after which) the callback should fire
+ * @param callback the callback function
+ * @param user_data user data to pass to the callback function
+ * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set,
+ *                     then the callback should be called during (by) this function instead 
+ * @return >0 the alarm id
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ *           The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ *           or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
+ * @return -1 if there were no alarm slots available
+ */
+static inline alarm_id_t add_alarm_in_ms(uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) {
+    return alarm_pool_add_alarm_in_ms(alarm_pool_get_default(), ms, callback, user_data, fire_if_past);
+}
+/*!
+ * \brief Cancel an alarm from the default alarm pool
+ * \ingroup alarm
+ * \param alarm_id the alarm
+ * \return true if the alarm was cancelled, false if it didn't exist
+ * \sa alarm_id_t for a note on reuse of IDs
+ */
+static inline bool cancel_alarm(alarm_id_t alarm_id) {
+    return alarm_pool_cancel_alarm(alarm_pool_get_default(), alarm_id);
+}
+
+#endif
+
+/*!
+ * \defgroup repeating_timer repeating_timer
+ * \ingroup pico_time
+ * \brief Repeating Timer functions for simple scheduling of repeated execution
+ *
+ * \note The regular \a alarm_ functionality can be used to make repeating alarms (by return non zero from the callback),
+ * however these methods abstract that further (at the cost of a user structure to store the repeat delay in (which
+ * the alarm framework does not have space for).
+ */
+
+typedef struct repeating_timer repeating_timer_t;
+
+/**
+ * \brief Callback for a repeating timer
+ * \ingroup repeating_timer
+ * \param rt repeating time structure containing information about the repeating time. user_data is of primary important to the user
+ * \return true to continue repeating, false to stop.
+ */
+typedef bool (*repeating_timer_callback_t)(repeating_timer_t *rt);
+
+/**
+ * \brief Information about a repeating timer
+ * \ingroup repeating_timer
+ * \return
+ */
+struct repeating_timer {
+    int64_t delay_us;
+    alarm_pool_t *pool;
+    alarm_id_t alarm_id;
+    repeating_timer_callback_t callback;
+    void *user_data;
+};
+
+/*!
+ * \brief Add a repeating timer that is called repeatedly at the specified interval in microseconds
+ * \ingroup repeating_timer
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core the alarm pool was created on. If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param pool the alarm pool to use for scheduling the repeating timer (this determines which hardware alarm is used, and which core calls the callback)
+ * @param delay_us the repeat delay in microseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1
+ * @param callback the repeating timer callback function
+ * @param user_data user data to pass to store in the repeating_timer structure for use by the callback.
+ * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space
+ * @return false if there were no alarm slots available to create the timer, true otherwise.
+ */
+bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out);
+
+/*!
+ * \brief Add a repeating timer that is called repeatedly at the specified interval in milliseconds
+ * \ingroup repeating_timer
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core the alarm pool was created on. If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param pool the alarm pool to use for scheduling the repeating timer (this determines which hardware alarm is used, and which core calls the callback)
+ * @param delay_ms the repeat delay in milliseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1 microsecond
+ * @param callback the repeating timer callback function
+ * @param user_data user data to pass to store in the repeating_timer structure for use by the callback.
+ * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space
+ * @return false if there were no alarm slots available to create the timer, true otherwise.
+ */
+static inline bool alarm_pool_add_repeating_timer_ms(alarm_pool_t *pool, int32_t delay_ms, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) {
+    return alarm_pool_add_repeating_timer_us(pool, delay_ms * (int64_t)1000, callback, user_data, out);
+}
+
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+/*!
+ * \brief Add a repeating timer that is called repeatedly at the specified interval in microseconds
+ * \ingroup repeating_timer
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param delay_us the repeat delay in microseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1
+ * @param callback the repeating timer callback function
+ * @param user_data user data to pass to store in the repeating_timer structure for use by the callback.
+ * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space
+ * @return false if there were no alarm slots available to create the timer, true otherwise.
+ */
+static inline bool add_repeating_timer_us(int64_t delay_us, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) {
+    return alarm_pool_add_repeating_timer_us(alarm_pool_get_default(), delay_us, callback, user_data, out);
+}
+
+/*!
+ * \brief Add a repeating timer that is called repeatedly at the specified interval in milliseconds
+ * \ingroup repeating_timer
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param delay_ms the repeat delay in milliseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1 microsecond
+ * @param callback the repeating timer callback function
+ * @param user_data user data to pass to store in the repeating_timer structure for use by the callback.
+ * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space
+ * @return false if there were no alarm slots available to create the timer, true otherwise.
+ */
+static inline bool add_repeating_timer_ms(int32_t delay_ms, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) {
+    return alarm_pool_add_repeating_timer_us(alarm_pool_get_default(), delay_ms * (int64_t)1000, callback, user_data, out);
+}
+#endif
+
+/**
+ * \brief Cancel a repeating timer
+ * \ingroup repeating_timer
+ * \param timer the repeating timer to cancel
+ * \return true if the repeating timer was cancelled, false if it didn't exist
+ * \sa alarm_id_t for a note on reuse of IDs
+ */
+bool cancel_repeating_timer(repeating_timer_t *timer);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/common/pico_time/include/pico/timeout_helper.h b/src/common/pico_time/include/pico/timeout_helper.h
new file mode 100644
index 0000000..e757f73
--- /dev/null
+++ b/src/common/pico_time/include/pico/timeout_helper.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_TIMEOUT_HELPER_H
+#define _PICO_TIMEOUT_HELPER_H
+
+#include "pico/time.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct timeout_state {
+    absolute_time_t next_timeout;
+    uint64_t param;
+} timeout_state_t;
+
+typedef bool (*check_timeout_fn)(timeout_state_t *ts);
+
+check_timeout_fn init_single_timeout_until(timeout_state_t *ts, absolute_time_t target);
+check_timeout_fn init_per_iteration_timeout_us(timeout_state_t *ts, uint64_t per_iteration_timeout_us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/src/common/pico_time/time.c b/src/common/pico_time/time.c
new file mode 100644
index 0000000..3a585f6
--- /dev/null
+++ b/src/common/pico_time/time.c
@@ -0,0 +1,413 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <limits.h>
+#include <inttypes.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "pico.h"
+#include "pico/time.h"
+#include "pico/util/pheap.h"
+#include "pico/sync.h"
+
+const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(nil_time, 0);
+const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(at_the_end_of_time, INT64_MAX);
+
+typedef struct alarm_pool_entry {
+    absolute_time_t target;
+    alarm_callback_t callback;
+    void *user_data;
+} alarm_pool_entry_t;
+
+typedef struct alarm_pool {
+    pheap_t *heap;
+    spin_lock_t *lock;
+    alarm_pool_entry_t *entries;
+    // one byte per entry, used to provide more longevity to public IDs than heap node ids do
+    // (this is increment every time the heap node id is re-used)
+    uint8_t *entry_ids_high;
+    alarm_id_t alarm_in_progress; // this is set during a callback from the IRQ handler... it can be cleared by alarm_cancel to prevent repeats
+    uint8_t hardware_alarm_num;
+} alarm_pool_t;
+
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+// To avoid bringing in calloc, we statically allocate the arrays and the heap
+PHEAP_DEFINE_STATIC(default_alarm_pool_heap, PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS);
+static alarm_pool_entry_t default_alarm_pool_entries[PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS];
+static uint8_t default_alarm_pool_entry_ids_high[PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS];
+static lock_core_t sleep_notifier;
+
+static alarm_pool_t default_alarm_pool = {
+        .heap = &default_alarm_pool_heap,
+        .entries = default_alarm_pool_entries,
+        .entry_ids_high = default_alarm_pool_entry_ids_high,
+};
+
+static inline bool default_alarm_pool_initialized(void) {
+    return default_alarm_pool.lock != NULL;
+}
+#endif
+
+static alarm_pool_t *pools[NUM_TIMERS];
+static void alarm_pool_post_alloc_init(alarm_pool_t *pool, uint hardware_alarm_num);
+
+
+static inline alarm_pool_entry_t *get_entry(alarm_pool_t *pool, pheap_node_id_t id) {
+    assert(id && id <= pool->heap->max_nodes);
+    return pool->entries + id - 1;
+}
+
+static inline uint8_t *get_entry_id_high(alarm_pool_t *pool, pheap_node_id_t id) {
+    assert(id && id <= pool->heap->max_nodes);
+    return pool->entry_ids_high + id - 1;
+}
+
+bool timer_pool_entry_comparator(void *user_data, pheap_node_id_t a, pheap_node_id_t b) {
+    alarm_pool_t *pool = (alarm_pool_t *)user_data;
+    return to_us_since_boot(get_entry(pool, a)->target) < to_us_since_boot(get_entry(pool, b)->target);
+}
+
+static inline alarm_id_t make_public_id(uint8_t id_high, pheap_node_id_t id) {
+    return (alarm_id_t)(((uint)id_high << 8u * sizeof(id)) | id);
+}
+
+void alarm_pool_init_default() {
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+    // allow multiple calls for ease of use from host tests
+    if (!default_alarm_pool_initialized()) {
+        ph_post_alloc_init(default_alarm_pool.heap, PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS,
+                           timer_pool_entry_comparator, &default_alarm_pool);
+        alarm_pool_post_alloc_init(&default_alarm_pool,
+                                   PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM);
+    }
+    lock_init(&sleep_notifier, PICO_SPINLOCK_ID_TIMER);
+#endif
+}
+
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+alarm_pool_t *alarm_pool_get_default() {
+    assert(default_alarm_pool_initialized());
+    return &default_alarm_pool;
+}
+#endif
+
+static pheap_node_id_t add_alarm_under_lock(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback,
+                                       void *user_data, pheap_node_id_t reuse_id, bool create_if_past, bool *missed) {
+    pheap_node_id_t id;
+    if (reuse_id) {
+        assert(!ph_contains_node(pool->heap, reuse_id));
+        id = reuse_id;
+    } else {
+        id = ph_new_node(pool->heap);
+    }
+    if (id) {
+        alarm_pool_entry_t *entry = get_entry(pool, id);
+        entry->target = time;
+        entry->callback = callback;
+        entry->user_data = user_data;
+        if (id == ph_insert_node(pool->heap, id)) {
+            bool is_missed = hardware_alarm_set_target(pool->hardware_alarm_num, time);
+            if (is_missed && !create_if_past) {
+                ph_remove_and_free_node(pool->heap, id);
+            }
+            if (missed) *missed = is_missed;
+        }
+    }
+    return id;
+}
+
+static void alarm_pool_alarm_callback(uint alarm_num) {
+    // note this is called from timer IRQ handler
+    alarm_pool_t *pool = pools[alarm_num];
+    bool again;
+    do {
+        absolute_time_t now = get_absolute_time();
+        alarm_callback_t callback = NULL;
+        absolute_time_t target = nil_time;
+        void *user_data = NULL;
+        uint8_t id_high;
+        again = false;
+        uint32_t save = spin_lock_blocking(pool->lock);
+        pheap_node_id_t next_id = ph_peek_head(pool->heap);
+        if (next_id) {
+            alarm_pool_entry_t *entry = get_entry(pool, next_id);
+            if (absolute_time_diff_us(now, entry->target) <= 0) {
+                // we don't free the id in case we need to re-add the timer
+                pheap_node_id_t __unused removed_id = ph_remove_head(pool->heap, false);
+                assert(removed_id == next_id); // will be true under lock
+                target = entry->target;
+                callback = entry->callback;
+                user_data = entry->user_data;
+                assert(callback);
+                id_high = *get_entry_id_high(pool, next_id);
+                pool->alarm_in_progress = make_public_id(id_high, removed_id);
+            } else {
+                if (hardware_alarm_set_target(alarm_num, entry->target)) {
+                    again = true;
+                }
+            }
+        }
+        spin_unlock(pool->lock, save);
+        if (callback) {
+            int64_t repeat = callback(make_public_id(id_high, next_id), user_data);
+            save = spin_lock_blocking(pool->lock);
+            // todo think more about whether we want to keep calling
+            if (repeat < 0 && pool->alarm_in_progress) {
+                assert(pool->alarm_in_progress == make_public_id(id_high, next_id));
+                add_alarm_under_lock(pool, delayed_by_us(target, (uint64_t)-repeat), callback, user_data, next_id, true, NULL);
+            } else if (repeat > 0 && pool->alarm_in_progress) {
+                assert(pool->alarm_in_progress == make_public_id(id_high, next_id));
+                add_alarm_under_lock(pool, delayed_by_us(get_absolute_time(), (uint64_t)repeat), callback, user_data, next_id,
+                                     true, NULL);
+            } else {
+                // need to return the id to the heap
+                ph_free_node(pool->heap, next_id);
+                (*get_entry_id_high(pool, next_id))++; // we bump it for next use of id
+            }
+            pool->alarm_in_progress = 0;
+            spin_unlock(pool->lock, save);
+            again = true;
+        }
+    } while (again);
+}
+
+// note the timer is create with IRQs on this core
+alarm_pool_t *alarm_pool_create(uint hardware_alarm_num, uint max_timers) {
+    alarm_pool_t *pool = (alarm_pool_t *) malloc(sizeof(alarm_pool_t));
+    pool->heap = ph_create(max_timers, timer_pool_entry_comparator, pool);
+    pool->entries = (alarm_pool_entry_t *)calloc(max_timers, sizeof(alarm_pool_entry_t));
+    pool->entry_ids_high = (uint8_t *)calloc(max_timers, sizeof(uint8_t));
+    alarm_pool_post_alloc_init(pool, hardware_alarm_num);
+    return pool;
+}
+
+void alarm_pool_post_alloc_init(alarm_pool_t *pool, uint hardware_alarm_num) {
+    hardware_alarm_claim(hardware_alarm_num);
+    hardware_alarm_cancel(hardware_alarm_num);
+    hardware_alarm_set_callback(hardware_alarm_num, alarm_pool_alarm_callback);
+    pool->lock = spin_lock_instance(next_striped_spin_lock_num());
+    pool->hardware_alarm_num = (uint8_t) hardware_alarm_num;
+    pools[hardware_alarm_num] = pool;
+}
+
+void alarm_pool_destroy(alarm_pool_t *pool) {
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+    if (pool == &default_alarm_pool) {
+        assert(false); // attempt to delete default alarm pool
+        return;
+    }
+#endif
+    assert(pools[pool->hardware_alarm_num] == pool);
+    pools[pool->hardware_alarm_num] = NULL;
+    // todo clear out timers
+    ph_destroy(pool->heap);
+    hardware_alarm_set_callback(pool->hardware_alarm_num, NULL);
+    hardware_alarm_unclaim(pool->hardware_alarm_num);
+    free(pool->entry_ids_high);
+    free(pool->entries);
+    free(pool);
+}
+
+alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback,
+                                   void *user_data, bool fire_if_past) {
+    bool missed = false;
+
+    alarm_id_t public_id;
+    do {
+        uint8_t id_high = 0;
+        uint32_t save = spin_lock_blocking(pool->lock);
+
+        pheap_node_id_t id = add_alarm_under_lock(pool, time, callback, user_data, 0, false, &missed);
+        if (id) id_high = *get_entry_id_high(pool, id);
+
+        spin_unlock(pool->lock, save);
+
+        if (!id) {
+            // no space in pheap to allocate an alarm
+            return -1;
+        }
+
+        // note that if missed was true, then the id was never added to the pheap (because we
+        // passed false for create_if_past arg above)
+        public_id = missed ? 0 : make_public_id(id_high, id);
+        if (missed && fire_if_past) {
+            // ... so if fire_if_past == true we call the callback
+            int64_t repeat = callback(public_id, user_data);
+            // if not repeated we have no id to return so set public_id to 0,
+            // otherwise we need to repeat, but will assign a new id next time
+            // todo arguably this does mean that the id passed to the first callback may differ from subsequent calls
+            if (!repeat) {
+                public_id = 0;
+                break;
+            } else if (repeat < 0) {
+                time = delayed_by_us(time, (uint64_t)-repeat);
+            } else {
+                time = delayed_by_us(get_absolute_time(), (uint64_t)repeat);
+            }
+        } else {
+            // either:
+            // a) missed == false && public_id is > 0
+            // b) missed == true && fire_if_past == false && public_id = 0
+            // but we are done in either case
+            break;
+        }
+    } while (true);
+    return public_id;
+}
+
+bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id) {
+    bool rc = false;
+    uint32_t save = spin_lock_blocking(pool->lock);
+    pheap_node_id_t id = (pheap_node_id_t) alarm_id;
+    if (ph_contains_node(pool->heap, id)) {
+        assert(alarm_id != pool->alarm_in_progress); // it shouldn't be in the heap if it is in progress
+        // check we have the right high value
+        uint8_t id_high = (uint8_t)((uint)alarm_id >> 8u * sizeof(pheap_node_id_t));
+        if (id_high == *get_entry_id_high(pool, id)) {
+            rc = ph_remove_and_free_node(pool->heap, id);
+            // note we don't bother to remove the actual hardware alarm timeout...
+            // it will either do callbacks or not depending on other alarms, and reset the next timeout itself
+            assert(rc);
+        }
+    } else {
+        if (alarm_id == pool->alarm_in_progress) {
+            // make sure the alarm doesn't repeat
+            pool->alarm_in_progress = 0;
+        }
+    }
+    spin_unlock(pool->lock, save);
+    return rc;
+}
+
+uint alarm_pool_hardware_alarm_num(alarm_pool_t *pool) {
+    return pool->hardware_alarm_num;
+}
+
+static void alarm_pool_dump_key(pheap_node_id_t id, void *user_data) {
+    alarm_pool_t *pool = (alarm_pool_t *)user_data;
+#if PICO_ON_DEVICE
+    printf("%lld (hi %02x)", to_us_since_boot(get_entry(pool, id)->target), *get_entry_id_high(pool, id));
+#else
+    printf("%"PRIu64, to_us_since_boot(get_entry(pool, id)->target));
+#endif
+}
+
+static int64_t repeating_timer_callback(__unused alarm_id_t id, void *user_data) {
+    repeating_timer_t *rt = (repeating_timer_t *)user_data;
+    assert(rt->alarm_id == id);
+    if (rt->callback(rt)) {
+        return rt->delay_us;
+    } else {
+        rt->alarm_id = 0;
+        return 0;
+    }
+}
+
+bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) {
+    if (!delay_us) delay_us = 1;
+    out->pool = pool;
+    out->callback = callback;
+    out->delay_us = delay_us;
+    out->user_data = user_data;
+    out->alarm_id = alarm_pool_add_alarm_at(pool, make_timeout_time_us((uint64_t)(delay_us >= 0 ? delay_us : -delay_us)),
+                                            repeating_timer_callback, out, true);
+    // note that if out->alarm_id is 0, then the callback was called during the above call (fire_if_past == true)
+    // and then the callback removed itself.
+    return out->alarm_id >= 0;
+}
+
+bool cancel_repeating_timer(repeating_timer_t *timer) {
+    bool rc = false;
+    if (timer->alarm_id) {
+        rc = alarm_pool_cancel_alarm(timer->pool, timer->alarm_id);
+        timer->alarm_id = 0;
+    }
+    return rc;
+}
+
+void alarm_pool_dump(alarm_pool_t *pool) {
+    uint32_t save = spin_lock_blocking(pool->lock);
+    ph_dump(pool->heap, alarm_pool_dump_key, pool);
+    spin_unlock(pool->lock, save);
+}
+
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+static int64_t sleep_until_callback(__unused alarm_id_t id, __unused void *user_data) {
+    uint32_t save = spin_lock_blocking(sleep_notifier.spin_lock);
+    lock_internal_spin_unlock_with_notify(&sleep_notifier, save);
+    return 0;
+}
+#endif
+
+void sleep_until(absolute_time_t t) {
+#if PICO_ON_DEVICE && !defined(NDEBUG)
+    if (__get_current_exception()) {
+        panic("Attempted to sleep inside of an exception handler; use busy_wait if you must");
+    }
+#endif
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+    uint64_t t_us = to_us_since_boot(t);
+    uint64_t t_before_us = t_us - PICO_TIME_SLEEP_OVERHEAD_ADJUST_US;
+    // needs to work in the first PICO_TIME_SLEEP_OVERHEAD_ADJUST_US of boot
+    if (t_before_us > t_us) t_before_us = 0;
+    absolute_time_t t_before;
+    update_us_since_boot(&t_before, t_before_us);
+    if (absolute_time_diff_us(get_absolute_time(), t_before) > 0) {
+        if (add_alarm_at(t_before, sleep_until_callback, NULL, false) >= 0) {
+            // able to add alarm for just before the time
+            while (!time_reached(t_before)) {
+                uint32_t save = spin_lock_blocking(sleep_notifier.spin_lock);
+                lock_internal_spin_unlock_with_wait(&sleep_notifier, save);
+            }
+        }
+    }
+#else
+    // hook in case we're in RTOS; note we assume using the alarm pool is better always if available.
+    sync_internal_yield_until_before(t);
+#endif
+    // now wait until the exact time
+    busy_wait_until(t);
+}
+
+void sleep_us(uint64_t us) {
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+    sleep_until(make_timeout_time_us(us));
+#else
+    if (us < PICO_TIME_SLEEP_OVERHEAD_ADJUST_US) {
+        busy_wait_us(us);
+    } else {
+        // hook in case we're in RTOS; note we assume using the alarm pool is better always if available.
+        absolute_time_t t = make_timeout_time_us(us - PICO_TIME_SLEEP_OVERHEAD_ADJUST_US);
+        sync_internal_yield_until_before(t);
+
+        // then wait the rest of thw way
+        busy_wait_until(t);
+    }
+#endif
+}
+
+void sleep_ms(uint32_t ms) {
+    sleep_us(ms * 1000ull);
+}
+
+bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp) {
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+    alarm_id_t id;
+    id = add_alarm_at(timeout_timestamp, sleep_until_callback, NULL, false);
+    if (id <= 0) {
+        tight_loop_contents();
+        return time_reached(timeout_timestamp);
+    } else {
+        __wfe();
+        // we need to clean up if it wasn't us that caused the wfe; if it was this will be a noop.
+        cancel_alarm(id);
+        return time_reached(timeout_timestamp);
+    }
+#else
+    tight_loop_contents();
+    return time_reached(timeout_timestamp);
+#endif
+}
diff --git a/src/common/pico_time/timeout_helper.c b/src/common/pico_time/timeout_helper.c
new file mode 100644
index 0000000..d9abe5a
--- /dev/null
+++ b/src/common/pico_time/timeout_helper.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/timeout_helper.h"
+
+static bool check_single_timeout_us(timeout_state_t *ts) {
+    return time_reached(ts->next_timeout);
+}
+
+check_timeout_fn init_single_timeout_until(timeout_state_t *ts, absolute_time_t target) {
+    ts->next_timeout = target;
+    return check_single_timeout_us;
+}
+
+static bool check_per_iteration_timeout_us(timeout_state_t *ts) {
+    if (time_reached(ts->next_timeout)) {
+        return true;
+    }
+    ts->next_timeout = make_timeout_time_us(ts->param);
+    return false;
+}
+
+check_timeout_fn init_per_iteration_timeout_us(timeout_state_t *ts, uint64_t per_iteration_timeout_us) {
+    ts->next_timeout = make_timeout_time_us(per_iteration_timeout_us);
+    ts->param = per_iteration_timeout_us;
+    return check_per_iteration_timeout_us;
+}
diff --git a/src/common/pico_usb_reset_interface/CMakeLists.txt b/src/common/pico_usb_reset_interface/CMakeLists.txt
new file mode 100644
index 0000000..369375c
--- /dev/null
+++ b/src/common/pico_usb_reset_interface/CMakeLists.txt
@@ -0,0 +1,2 @@
+add_library(pico_usb_reset_interface_headers INTERFACE)
+target_include_directories(pico_usb_reset_interface_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
diff --git a/src/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h b/src/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h
new file mode 100644
index 0000000..153acf8
--- /dev/null
+++ b/src/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_USB_RESET_INTERFACE_H
+#define _PICO_USB_RESET_INTERFACE_H
+
+/** \file usb_reset_interface.h
+ *  \defgroup pico_usb_reset_interface pico_usb_reset_interface
+ *
+ * Definition for the reset interface that may be exposed by the pico_stdio_usb library
+ */
+
+// VENDOR sub-class for the reset interface
+#define RESET_INTERFACE_SUBCLASS 0x00
+// VENDOR protocol for the reset interface
+#define RESET_INTERFACE_PROTOCOL 0x01
+
+// CONTROL requests:
+
+// reset to BOOTSEL
+#define RESET_REQUEST_BOOTSEL 0x01
+// regular flash boot
+#define RESET_REQUEST_FLASH 0x02
+
+#endif
\ No newline at end of file
diff --git a/src/common/pico_util/CMakeLists.txt b/src/common/pico_util/CMakeLists.txt
new file mode 100644
index 0000000..3eb6998
--- /dev/null
+++ b/src/common/pico_util/CMakeLists.txt
@@ -0,0 +1,15 @@
+if (NOT TARGET pico_util_headers)
+    add_library(pico_util_headers INTERFACE)
+    target_include_directories(pico_util_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+    target_link_libraries(pico_util_headers INTERFACE pico_base_headers hardware_sync)
+endif()
+
+if (NOT TARGET pico_util)
+    pico_add_impl_library(pico_util)
+    target_sources(pico_util INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/datetime.c
+            ${CMAKE_CURRENT_LIST_DIR}/pheap.c
+            ${CMAKE_CURRENT_LIST_DIR}/queue.c
+    )
+    target_link_libraries(pico_util INTERFACE pico_util_headers)
+endif()
diff --git a/src/common/pico_util/datetime.c b/src/common/pico_util/datetime.c
new file mode 100644
index 0000000..e035515
--- /dev/null
+++ b/src/common/pico_util/datetime.c
@@ -0,0 +1,41 @@
+#include "pico/util/datetime.h"
+
+#include <stdio.h>
+
+static const char *DATETIME_MONTHS[12] = {
+        "January",
+        "February",
+        "March",
+        "April",
+        "May",
+        "June",
+        "July",
+        "August",
+        "September",
+        "October",
+        "November",
+        "December"
+};
+
+static const char *DATETIME_DOWS[7] = {
+        "Sunday",
+        "Monday",
+        "Tuesday",
+        "Wednesday",
+        "Thursday",
+        "Friday",
+        "Saturday",
+};
+
+void datetime_to_str(char *buf, uint buf_size, const datetime_t *t) {
+    snprintf(buf,
+             buf_size,
+             "%s %d %s %d:%02d:%02d %d",
+             DATETIME_DOWS[t->dotw],
+             t->day,
+             DATETIME_MONTHS[t->month - 1],
+             t->hour,
+             t->min,
+             t->sec,
+             t->year);
+};
\ No newline at end of file
diff --git a/src/common/pico_util/doc.h b/src/common/pico_util/doc.h
new file mode 100644
index 0000000..4485b5d
--- /dev/null
+++ b/src/common/pico_util/doc.h
@@ -0,0 +1,4 @@
+/**
+ * \defgroup pico_util pico_util
+ * \brief Useful data structures and utility functions
+ */
diff --git a/src/common/pico_util/include/pico/util/datetime.h b/src/common/pico_util/include/pico/util/datetime.h
new file mode 100644
index 0000000..bb32835
--- /dev/null
+++ b/src/common/pico_util/include/pico/util/datetime.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_DATETIME_H
+#define _PICO_DATETIME_H
+
+#include "pico.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file datetime.h
+ * \defgroup util_datetime datetime
+ * \brief Date/Time formatting
+ * \ingroup pico_util
+ */
+
+/*! \brief  Convert a datetime_t structure to a string
+ *  \ingroup util_datetime
+ *
+ * \param buf character buffer to accept generated string
+ * \param buf_size The size of the passed in buffer
+ * \param t The datetime to be converted.
+ */
+void datetime_to_str(char *buf, uint buf_size, const datetime_t *t);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/src/common/pico_util/include/pico/util/pheap.h b/src/common/pico_util/include/pico/util/pheap.h
new file mode 100644
index 0000000..25351b4
--- /dev/null
+++ b/src/common/pico_util/include/pico/util/pheap.h
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_UTIL_PHEAP_H
+#define _PICO_UTIL_PHEAP_H
+
+#include "pico.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PHEAP, Enable/disable assertions in the pheap module, type=bool, default=0, group=pico_util
+#ifndef PARAM_ASSERTIONS_ENABLED_PHEAP
+#define PARAM_ASSERTIONS_ENABLED_PHEAP 0
+#endif
+
+/**
+ * \file pheap.h
+ * \defgroup util_pheap pheap
+ * Pairing Heap Implementation
+ * \ingroup pico_util
+ *
+ * pheap defines a simple pairing heap. the implementation simply tracks array indexes, it is up to
+ * the user to provide storage for heap entries and a comparison function.
+ *
+ * NOTE: this class is not safe for concurrent usage. It should be externally protected. Furthermore
+ * if used concurrently, the caller needs to protect around their use of the returned id.
+ * for example, ph_remove_and_free_head returns the id of an element that is no longer in the heap.
+ *
+ * The user can still use this to look at the data in their companion array, however obviously further operations
+ * on the heap may cause them to overwrite that data as the id may be reused on subsequent operations
+ *
+ */
+// PICO_CONFIG: PICO_PHEAP_MAX_ENTRIES, Maximum number of entries in the pheap, min=1, max=65534, default=255, group=pico_util
+#ifndef PICO_PHEAP_MAX_ENTRIES
+#define PICO_PHEAP_MAX_ENTRIES 255
+#endif
+
+// public heap_node ids are numbered from 1 (0 means none)
+#if PICO_PHEAP_MAX_ENTRIES < 256
+typedef uint8_t pheap_node_id_t;
+#elif PICO_PHEAP_MAX_ENTRIES < 65535
+typedef uint16_t pheap_node_id_t;
+#else
+#error invalid PICO_PHEAP_MAX_ENTRIES
+#endif
+
+typedef struct pheap_node {
+    pheap_node_id_t child, sibling, parent;
+} pheap_node_t;
+
+/**
+ * A user comparator function for nodes in a pairing heap.
+ *
+ * \return true if a < b in natural order. Note this relative ordering must be stable from call to call.
+ */
+typedef bool (*pheap_comparator)(void *user_data, pheap_node_id_t a, pheap_node_id_t b);
+
+typedef struct pheap {
+    pheap_node_t *nodes;
+    pheap_comparator comparator;
+    void *user_data;
+    pheap_node_id_t max_nodes;
+    pheap_node_id_t root_id;
+    // we remove from head and add to tail to stop reusing the same ids
+    pheap_node_id_t free_head_id;
+    pheap_node_id_t free_tail_id;
+} pheap_t;
+
+/**
+ * Create a pairing heap, which effectively maintains an efficient sorted ordering
+ * of nodes. The heap itself stores no user per-node state, it is expected
+ * that the user maintains a companion array. A comparator function must
+ * be provided so that the heap implementation can determine the relative ordering of nodes
+ *
+ * \param max_nodes the maximum number of nodes that may be in the heap (this is bounded by
+ *                  PICO_PHEAP_MAX_ENTRIES which defaults to 255 to be able to store indexes
+ *                  in a single byte).
+ * \param comparator the node comparison function
+ * \param user_data a user data pointer associated with the heap that is provided in callbacks
+ * \return a newly allocated and initialized heap
+ */
+pheap_t *ph_create(uint max_nodes, pheap_comparator comparator, void *user_data);
+
+/**
+ * Removes all nodes from the pairing heap
+ * \param heap the heap
+ */
+void ph_clear(pheap_t *heap);
+
+/**
+ * De-allocates a pairing heap
+ *
+ * Note this method must *ONLY* be called on heaps created by ph_create()
+ * \param heap the heap
+ */
+void ph_destroy(pheap_t *heap);
+
+// internal method
+static inline pheap_node_t *ph_get_node(pheap_t *heap, pheap_node_id_t id) {
+    assert(id && id <= heap->max_nodes);
+    return heap->nodes + id - 1;
+}
+
+// internal method
+static void ph_add_child_node(pheap_t *heap, pheap_node_id_t parent_id, pheap_node_id_t child_id) {
+    pheap_node_t *n = ph_get_node(heap, parent_id);
+    assert(parent_id);
+    assert(child_id);
+    assert(parent_id != child_id);
+    pheap_node_t *c = ph_get_node(heap, child_id);
+    c->parent = parent_id;
+    if (!n->child) {
+        n->child = child_id;
+    } else {
+        c->sibling = n->child;
+        n->child = child_id;
+    }
+}
+
+// internal method
+static pheap_node_id_t ph_merge_nodes(pheap_t *heap, pheap_node_id_t a, pheap_node_id_t b) {
+    if (!a) return b;
+    if (!b) return a;
+    if (heap->comparator(heap->user_data, a, b)) {
+        ph_add_child_node(heap, a, b);
+        return a;
+    } else {
+        ph_add_child_node(heap, b, a);
+        return b;
+    }
+}
+
+/**
+ * Allocate a new node from the unused space in the heap
+ *
+ * \param heap the heap
+ * \return an identifier for the node, or 0 if the heap is full
+ */
+static inline pheap_node_id_t ph_new_node(pheap_t *heap) {
+    if (!heap->free_head_id) return 0;
+    pheap_node_id_t id = heap->free_head_id;
+    pheap_node_t *hn = ph_get_node(heap, id);
+    heap->free_head_id = hn->sibling;
+    if (!heap->free_head_id) heap->free_tail_id = 0;
+    hn->child = hn->sibling = hn->parent = 0;
+    return id;
+}
+
+/**
+ * Inserts a node into the heap.
+ *
+ * This method inserts a node (previously allocated by ph_new_node())
+ * into the heap, determining the correct order by calling
+ * the heap's comparator
+ *
+ * \param heap the heap
+ * \param id the id of the node to insert
+ * \return the id of the new head of the pairing heap (i.e. node that compares first)
+ */
+static inline pheap_node_id_t ph_insert_node(pheap_t *heap, pheap_node_id_t id) {
+    assert(id);
+    pheap_node_t *hn = ph_get_node(heap, id);
+    hn->child = hn->sibling = hn->parent = 0;
+    heap->root_id = ph_merge_nodes(heap, heap->root_id, id);
+    return heap->root_id;
+}
+
+/**
+ * Returns the head node in the heap, i.e. the node
+ * which compares first, but without removing it from the heap.
+ *
+ * \param heap the heap
+ * \return the current head node id
+ */
+static inline pheap_node_id_t ph_peek_head(pheap_t *heap) {
+    return heap->root_id;
+}
+
+/**
+ * Remove the head node from the pairing heap. This head node is
+ * the node which compares first in the logical ordering provided
+ * by the comparator.
+ *
+ * Note that in the case of free == true, the returned id is no longer
+ * allocated and may be re-used by future node allocations, so the caller
+ * should retrieve any per node state from the companion array before modifying
+ * the heap further.
+ *
+ * @param heap the heap
+ * @param free true if the id is also to be freed; false if not - useful if the caller
+ *        may wish to re-insert an item with the same id)
+ * @return the old head node id.
+ */
+pheap_node_id_t ph_remove_head(pheap_t *heap, bool free);
+
+/**
+ * Remove the head node from the pairing heap. This head node is
+ * the node which compares first in the logical ordering provided
+ * by the comparator.
+ *
+ * Note that the returned id will be freed, and thus may be re-used by future node allocations,
+ * so the caller should retrieve any per node state from the companion array before modifying
+ * the heap further.
+ *
+ * @param heap the heap
+ * @return the old head node id.
+ */
+static inline pheap_node_id_t ph_remove_and_free_head(pheap_t *heap) {
+    return ph_remove_head(heap, true);
+}
+
+/**
+ * Remove and free an arbitrary node from the pairing heap. This is a more
+ * costly operation than removing the head via ph_remove_and_free_head()
+ *
+ * @param heap the heap
+ * @param id the id of the node to free
+ * @return true if the the node was in the heap, false otherwise
+ */
+bool ph_remove_and_free_node(pheap_t *heap, pheap_node_id_t id);
+
+/**
+ * Determine if the heap contains a given node. Note containment refers
+ * to whether the node is inserted (ph_insert_node()) vs allocated (ph_new_node())
+ *
+ * @param heap the heap
+ * @param id the id of the node
+ * @return true if the heap contains a node with the given id, false otherwise.
+ */
+static inline bool ph_contains_node(pheap_t *heap, pheap_node_id_t id) {
+    return id == heap->root_id || ph_get_node(heap, id)->parent;
+}
+
+
+/**
+ * Free a node that is not currently in the heap, but has been allocated
+ *
+ * @param heap the heap
+ * @param id the id of the node
+ */
+static inline void ph_free_node(pheap_t *heap, pheap_node_id_t id) {
+    assert(id && !ph_contains_node(heap, id));
+    if (heap->free_tail_id) {
+        ph_get_node(heap, heap->free_tail_id)->sibling = id;
+    }
+    heap->free_tail_id = id;
+}
+
+/**
+ * Print a representation of the heap for debugging
+ *
+ * @param heap the heap
+ * @param dump_key a method to print a node value
+ * @param user_data the user data to pass to the dump_key method
+ */
+void ph_dump(pheap_t *heap, void (*dump_key)(pheap_node_id_t id, void *user_data), void *user_data);
+
+/**
+ * Initialize a statically allocated heap (ph_create() using the C heap).
+ * The heap member `nodes` must be allocated of size max_nodes.
+ *
+ * @param heap the heap
+ * @param max_nodes the max number of nodes in the heap (matching the size of the heap's nodes array)
+ * @param comparator the comparator for the heap
+ * @param user_data the user data for the heap.
+ */
+void ph_post_alloc_init(pheap_t *heap, uint max_nodes, pheap_comparator comparator, void *user_data);
+
+/**
+ * Define a statically allocated pairing heap. This must be initialized
+ * by ph_post_alloc_init
+ */
+#define PHEAP_DEFINE_STATIC(name, _max_nodes) \
+    static_assert(_max_nodes && _max_nodes < (1u << (8 * sizeof(pheap_node_id_t))), ""); \
+    static pheap_node_t name ## _nodes[_max_nodes]; \
+    static pheap_t name = { \
+            .nodes = name ## _nodes, \
+            .max_nodes = _max_nodes \
+    };
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/common/pico_util/include/pico/util/queue.h b/src/common/pico_util/include/pico/util/queue.h
new file mode 100644
index 0000000..097578a
--- /dev/null
+++ b/src/common/pico_util/include/pico/util/queue.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _UTIL_QUEUE_H
+#define _UTIL_QUEUE_H
+
+#include "pico.h"
+#include "hardware/sync.h"
+
+// PICO_CONFIG: PICO_QUEUE_MAX_LEVEL, Maintain a field for the highest level that has been reached by a queue, type=bool, default=0, advanced=true, group=queue
+#ifndef PICO_QUEUE_MAX_LEVEL
+#define PICO_QUEUE_MAX_LEVEL 0
+#endif
+
+/** \file queue.h
+ * \defgroup queue queue
+ * Multi-core and IRQ safe queue implementation.
+ *
+ * Note that this queue stores values of a specified size, and pushed values are copied into the queue
+ * \ingroup pico_util
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "pico/lock_core.h"
+
+typedef struct {
+    lock_core_t core;
+    uint8_t *data;
+    uint16_t wptr;
+    uint16_t rptr;
+    uint16_t element_size;
+    uint16_t element_count;
+#if PICO_QUEUE_MAX_LEVEL
+    uint16_t max_level;
+#endif
+} queue_t;
+
+/*! \brief Initialise a queue with a specific spinlock for concurrency protection
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param element_size Size of each value in the queue
+ * \param element_count Maximum number of entries in the queue
+ * \param spinlock_num The spin ID used to protect the queue
+ */
+void queue_init_with_spinlock(queue_t *q, uint element_size, uint element_count, uint spinlock_num);
+
+/*! \brief Initialise a queue, allocating a (possibly shared) spinlock
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param element_size Size of each value in the queue
+ * \param element_count Maximum number of entries in the queue
+ */
+static inline void queue_init(queue_t *q, uint element_size, uint element_count) {
+    return queue_init_with_spinlock(q, element_size, element_count, next_striped_spin_lock_num());
+}
+
+/*! \brief Destroy the specified queue.
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ *
+ * Does not deallocate the queue_t structure itself.
+ */
+void queue_free(queue_t *q);
+
+/*! \brief Unsafe check of level of the specified queue.
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \return Number of entries in the queue
+ *
+ * This does not use the spinlock, so may return incorrect results if the
+ * spin lock is not externally locked
+ */
+static inline uint queue_get_level_unsafe(queue_t *q) {
+    int32_t rc = (int32_t)q->wptr - (int32_t)q->rptr;
+    if (rc < 0) {
+        rc += q->element_count + 1;
+    }
+    return (uint)rc;
+}
+
+/*! \brief Check of level of the specified queue.
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \return Number of entries in the queue
+ */
+static inline uint queue_get_level(queue_t *q) {
+    uint32_t save = spin_lock_blocking(q->core.spin_lock);
+    uint level = queue_get_level_unsafe(q);
+    spin_unlock(q->core.spin_lock, save);
+    return level;
+}
+
+/*! \brief Returns the highest level reached by the specified queue since it was created
+ *         or since the max level was reset
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \return Maximum level of the queue
+ */
+#if PICO_QUEUE_MAX_LEVEL
+static inline uint queue_get_max_level(queue_t *q) {
+    return q->max_level;
+}
+#endif
+
+/*! \brief Reset the highest level reached of the specified queue.
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ */
+#if PICO_QUEUE_MAX_LEVEL
+static inline void queue_reset_max_level(queue_t *q) {
+    uint32_t save = spin_lock_blocking(q->core.spin_lock);
+    q->max_level = queue_get_level_unsafe(q);
+    spin_unlock(q->core.spin_lock, save);
+}
+#endif
+
+/*! \brief Check if queue is empty
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \return true if queue is empty, false otherwise
+ *
+ * This function is interrupt and multicore safe.
+ */
+static inline bool queue_is_empty(queue_t *q) {
+    return queue_get_level(q) == 0;
+}
+
+/*! \brief Check if queue is full
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \return true if queue is full, false otherwise
+ *
+ * This function is interrupt and multicore safe.
+ */
+static inline bool queue_is_full(queue_t *q) {
+    return queue_get_level(q) == q->element_count;
+}
+
+// nonblocking queue access functions:
+
+/*! \brief Non-blocking add value queue if not full
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param data Pointer to value to be copied into the queue
+ * \return true if the value was added
+ *
+ * If the queue is full this function will return immediately with false, otherwise
+ * the data is copied into a new value added to the queue, and this function will return true.
+ */
+bool queue_try_add(queue_t *q, const void *data);
+
+/*! \brief Non-blocking removal of entry from the queue if non empty
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param data Pointer to the location to receive the removed value
+ * \return true if a value was removed
+ *
+ * If the queue is not empty function will copy the removed value into the location provided and return
+ * immediately with true, otherwise the function will return immediately with false.
+ */
+bool queue_try_remove(queue_t *q, void *data);
+
+/*! \brief Non-blocking peek at the next item to be removed from the queue
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param data Pointer to the location to receive the peeked value
+ * \return true if there was a value to peek
+ *
+ * If the queue is not empty this function will return immediately with true with the peeked entry
+ * copied into the location specified by the data parameter, otherwise the function will return false.
+ */
+bool queue_try_peek(queue_t *q, void *data);
+
+// blocking queue access functions:
+
+/*! \brief Blocking add of value to queue
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param data Pointer to value to be copied into the queue
+ *
+ * If the queue is full this function will block, until a removal happens on the queue
+ */
+void queue_add_blocking(queue_t *q, const void *data);
+
+/*! \brief Blocking remove entry from queue
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param data Pointer to the location to receive the removed value
+ *
+ * If the queue is empty this function will block until a value is added.
+ */
+void queue_remove_blocking(queue_t *q, void *data);
+
+/*! \brief Blocking peek at next value to be removed from queue
+ *  \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param data Pointer to the location to receive the peeked value
+ *
+ * If the queue is empty function will block until a value is added
+ */
+void queue_peek_blocking(queue_t *q, void *data);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/src/common/pico_util/pheap.c b/src/common/pico_util/pheap.c
new file mode 100644
index 0000000..fc80435
--- /dev/null
+++ b/src/common/pico_util/pheap.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "pico/util/pheap.h"
+
+pheap_t *ph_create(uint max_nodes, pheap_comparator comparator, void *user_data) {
+    invalid_params_if(PHEAP, !max_nodes || max_nodes >= (1u << (8 * sizeof(pheap_node_id_t))));
+    pheap_t *heap = calloc(1, sizeof(pheap_t));
+    heap->nodes = calloc(max_nodes, sizeof(pheap_node_t));
+    ph_post_alloc_init(heap, max_nodes, comparator, user_data);
+    return heap;
+}
+
+void ph_post_alloc_init(pheap_t *heap, uint max_nodes, pheap_comparator comparator, void *user_data) {
+    invalid_params_if(PHEAP, !max_nodes || max_nodes >= (1u << (8 * sizeof(pheap_node_id_t))));
+    heap->max_nodes = (pheap_node_id_t) max_nodes;
+    heap->comparator = comparator;
+    heap->user_data = user_data;
+    ph_clear(heap);
+}
+
+void ph_clear(pheap_t *heap) {
+    heap->root_id = 0;
+    heap->free_head_id = 1;
+    heap->free_tail_id = heap->max_nodes;
+    for(pheap_node_id_t i = 1; i < heap->max_nodes; i++) {
+        ph_get_node(heap, i)->sibling = (pheap_node_id_t)(i + 1);
+    }
+    ph_get_node(heap, heap->max_nodes)->sibling = 0;
+}
+
+void ph_destroy(pheap_t *heap) {
+    free(heap->nodes);
+    free(heap);
+}
+
+pheap_node_id_t ph_merge_two_pass(pheap_t *heap, pheap_node_id_t id) {
+    if (!id || !ph_get_node(heap, id)->sibling) {
+        return id;
+    } else {
+        pheap_node_id_t a, b, new_node;
+        a = id;
+        b = ph_get_node(heap, id)->sibling;
+        new_node = ph_get_node(heap, b)->sibling;
+        ph_get_node(heap, a)->sibling = ph_get_node(heap, b)->sibling = 0;
+        return ph_merge_nodes(heap, ph_merge_nodes(heap, a, b), ph_merge_two_pass(heap, new_node));
+    }
+}
+
+static pheap_node_id_t ph_remove_any_head(pheap_t *heap, pheap_node_id_t root_id, bool free) {
+    assert(root_id);
+//    printf("Removing head %d (parent %d sibling %d)\n", root_id, ph_get_node(heap, root_id)->parent, ph_get_node(heap, root_id)->sibling);
+    assert(!ph_get_node(heap, root_id)->sibling);
+    assert(!ph_get_node(heap, root_id)->parent);
+    pheap_node_id_t new_root_id = ph_merge_two_pass(heap, ph_get_node(heap, root_id)->child);
+    if (free) {
+        if (heap->free_tail_id) {
+            ph_get_node(heap, heap->free_tail_id)->sibling = root_id;
+        }
+        heap->free_tail_id = root_id;
+    }
+    if (new_root_id) ph_get_node(heap, new_root_id)->parent = 0;
+    ph_get_node(heap, root_id)->sibling = 0;
+    return new_root_id;
+}
+
+pheap_node_id_t ph_remove_head(pheap_t *heap, bool free) {
+    pheap_node_id_t old_root_id = ph_peek_head(heap);
+    heap->root_id = ph_remove_any_head(heap, old_root_id, free);
+    return old_root_id;
+}
+
+bool ph_remove_and_free_node(pheap_t *heap, pheap_node_id_t id) {
+    // 1) trivial cases
+    if (!id) return false;
+    if (id == heap->root_id) {
+        ph_remove_and_free_head(heap);
+        return true;
+    }
+    // 2) unlink the node from the tree
+    pheap_node_t *node = ph_get_node(heap, id);
+    if (!node->parent) return false; // not in tree
+    pheap_node_t *parent = ph_get_node(heap, node->parent);
+    if (parent->child == id) {
+        parent->child = node->sibling;
+    } else {
+        pheap_node_id_t prev_sibling_id = parent->child;
+        bool __unused found = false;
+        do {
+            pheap_node_t *prev_sibling = ph_get_node(heap, prev_sibling_id);
+            if (prev_sibling->sibling == id) {
+                prev_sibling->sibling = node->sibling;
+                found = true;
+                break;
+            }
+            prev_sibling_id = prev_sibling->sibling;
+        } while (prev_sibling_id);
+        assert(found);
+    }
+    node->sibling = node->parent = 0;
+//    ph_dump(heap, NULL, NULL);
+    // 3) remove it from the head of its own subtree
+    pheap_node_id_t new_sub_tree = ph_remove_any_head(heap, id, true);
+    assert(new_sub_tree != heap->root_id);
+    heap->root_id = ph_merge_nodes(heap, heap->root_id, new_sub_tree);
+    return true;
+}
+
+static uint ph_dump_node(pheap_t *heap, pheap_node_id_t id, void (*dump_key)(pheap_node_id_t, void *), void *user_data, uint indent) {
+    uint count = 0;
+    if (id) {
+        count++;
+        for (uint i = 0; i < indent * 2; i++) {
+            putchar(' ');
+        }
+        pheap_node_t *node = ph_get_node(heap, id);
+        printf("%d (c=%d s=%d p=%d) ", id, node->child, node->sibling, node->parent);
+        if (dump_key) dump_key(id, user_data);
+        printf("\n");
+        count += ph_dump_node(heap, node->child, dump_key, user_data, indent + 1);
+        count += ph_dump_node(heap, node->sibling, dump_key, user_data, indent);
+    }
+    return count;
+}
+
+void ph_dump(pheap_t *heap, void (*dump_key)(pheap_node_id_t, void *), void *user_data) {
+    uint count = ph_dump_node(heap, heap->root_id, dump_key, user_data, 0);
+    printf("node_count %d\n", count);
+}
\ No newline at end of file
diff --git a/src/common/pico_util/queue.c b/src/common/pico_util/queue.c
new file mode 100644
index 0000000..a5c8e18
--- /dev/null
+++ b/src/common/pico_util/queue.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include "pico/util/queue.h"
+
+void queue_init_with_spinlock(queue_t *q, uint element_size, uint element_count, uint spinlock_num) {
+    lock_init(&q->core, spinlock_num);
+    q->data = (uint8_t *)calloc(element_count + 1, element_size);
+    q->element_count = (uint16_t)element_count;
+    q->element_size = (uint16_t)element_size;
+    q->wptr = 0;
+    q->rptr = 0;
+}
+
+void queue_free(queue_t *q) {
+    free(q->data);
+}
+
+static inline void *element_ptr(queue_t *q, uint index) {
+    assert(index <= q->element_count);
+    return q->data + index * q->element_size;
+}
+
+static inline uint16_t inc_index(queue_t *q, uint16_t index) {
+    if (++index > q->element_count) { // > because we have element_count + 1 elements
+        index = 0;
+    }
+
+#if PICO_QUEUE_MAX_LEVEL
+    uint16_t level = queue_get_level_unsafe(q);
+    if (level > q->max_level) {
+        q->max_level = level;
+    }
+#endif
+
+    return index;
+}
+
+static bool queue_add_internal(queue_t *q, const void *data, bool block) {
+    do {
+        uint32_t save = spin_lock_blocking(q->core.spin_lock);
+        if (queue_get_level_unsafe(q) != q->element_count) {
+            memcpy(element_ptr(q, q->wptr), data, q->element_size);
+            q->wptr = inc_index(q, q->wptr);
+            lock_internal_spin_unlock_with_notify(&q->core, save);
+            return true;
+        }
+        if (block) {
+            lock_internal_spin_unlock_with_wait(&q->core, save);
+        } else {
+            spin_unlock(q->core.spin_lock, save);
+            return false;
+        }
+    } while (true);
+}
+
+static bool queue_remove_internal(queue_t *q, void *data, bool block) {
+    do {
+        uint32_t save = spin_lock_blocking(q->core.spin_lock);
+        if (queue_get_level_unsafe(q) != 0) {
+            memcpy(data, element_ptr(q, q->rptr), q->element_size);
+            q->rptr = inc_index(q, q->rptr);
+            lock_internal_spin_unlock_with_notify(&q->core, save);
+            return true;
+        }
+        if (block) {
+            lock_internal_spin_unlock_with_wait(&q->core, save);
+        } else {
+            spin_unlock(q->core.spin_lock, save);
+            return false;
+        }
+    } while (true);
+}
+
+static bool queue_peek_internal(queue_t *q, void *data, bool block) {
+    do {
+        uint32_t save = spin_lock_blocking(q->core.spin_lock);
+        if (queue_get_level_unsafe(q) != 0) {
+            memcpy(data, element_ptr(q, q->rptr), q->element_size);
+            lock_internal_spin_unlock_with_notify(&q->core, save);
+            return true;
+        }
+        if (block) {
+            lock_internal_spin_unlock_with_wait(&q->core, save);
+        } else {
+            spin_unlock(q->core.spin_lock, save);
+            return false;
+        }
+    } while (true);
+}
+
+bool queue_try_add(queue_t *q, const void *data) {
+    return queue_add_internal(q, data, false);
+}
+
+bool queue_try_remove(queue_t *q, void *data) {
+    return queue_remove_internal(q, data, false);
+}
+
+bool queue_try_peek(queue_t *q, void *data) {
+    return queue_peek_internal(q, data, false);
+}
+
+void queue_add_blocking(queue_t *q, const void *data) {
+    queue_add_internal(q, data, true);
+}
+
+void queue_remove_blocking(queue_t *q, void *data) {
+    queue_remove_internal(q, data, true);
+}
+
+void queue_peek_blocking(queue_t *q, void *data) {
+    queue_peek_internal(q, data, true);
+}
diff --git a/src/host.cmake b/src/host.cmake
new file mode 100644
index 0000000..5a3f358
--- /dev/null
+++ b/src/host.cmake
@@ -0,0 +1,10 @@
+# For targeting the host for testing purposes
+
+function(pico_add_extra_outputs TARGET)
+endfunction()
+
+set(PICO_NO_HARDWARE "1" CACHE INTERNAL "")
+set(PICO_ON_DEVICE "0" CACHE INTERNAL "")
+
+add_subdirectory(common)
+add_subdirectory(host)
\ No newline at end of file
diff --git a/src/host/CMakeLists.txt b/src/host/CMakeLists.txt
new file mode 100644
index 0000000..9edcd7b
--- /dev/null
+++ b/src/host/CMakeLists.txt
@@ -0,0 +1,37 @@
+pico_add_subdirectory(hardware_divider)
+pico_add_subdirectory(hardware_gpio)
+pico_add_subdirectory(hardware_sync)
+pico_add_subdirectory(hardware_timer)
+pico_add_subdirectory(hardware_uart)
+pico_add_subdirectory(pico_bit_ops)
+pico_add_subdirectory(pico_divider)
+pico_add_subdirectory(pico_multicore)
+pico_add_subdirectory(pico_platform)
+pico_add_subdirectory(pico_printf)
+pico_add_subdirectory(pico_stdio)
+pico_add_subdirectory(pico_stdlib)
+
+pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR})
+
+macro(pico_set_float_implementation TARGET IMPL)
+    # ignore
+endmacro()
+
+macro(pico_set_double_implementation TARGET IMPL)
+    # ignore
+endmacro()
+
+macro(pico_set_binary_type TARGET IMPL)
+    # ignore
+endmacro()
+
+macro(pico_set_boot_stage2 TARGET IMPL)
+    # ignore
+endmacro()
+
+set(PICO_HOST_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "")
+function(pico_define_boot_stage2 NAME)
+    add_executable(${NAME} ${PICO_HOST_DIR}/boot_stage2.c)
+endfunction()
+
+pico_promote_common_scope_vars()
\ No newline at end of file
diff --git a/src/host/README.md b/src/host/README.md
new file mode 100644
index 0000000..c6d8962
--- /dev/null
+++ b/src/host/README.md
@@ -0,0 +1,14 @@
+This is a basic set of replacement library implementations sufficient to get simple applications
+running on your computer (Raspberry Pi OS, Linux, macOS or Windows using Cygwin or Windows Subsystem for Linux).
+It is selected by `PICO_PLATFORM=host` in your CMake build
+
+This can be extremely useful for testing and debugging higher level application code, or porting code which is not yet small enough 
+to run on the RP2040 device itself.
+
+This base level host library provides a minimal environment to compile programs, but is likely sufficient for programs
+that don't access hardware directly.
+
+It is possible however to inject additional SDK library implementations/simulations to provide 
+more complete functionality. For an example of this see the [pico-host-sdl](https://github.com/raspberrypi/pico-host-sdl) 
+which uses the SDL2 library to add additional library support for pico_multicore, timers/alarms in pico-time and 
+pico-audio/pico-scanvideo from [pico-extras](https://github.com/raspberrypi/pico-extras)
diff --git a/src/host/boot_stage2.c b/src/host/boot_stage2.c
new file mode 100644
index 0000000..52794b1
--- /dev/null
+++ b/src/host/boot_stage2.c
@@ -0,0 +1,3 @@
+void main() {
+
+}
\ No newline at end of file
diff --git a/src/host/hardware_divider/CMakeLists.txt b/src/host/hardware_divider/CMakeLists.txt
new file mode 100644
index 0000000..a6156c0
--- /dev/null
+++ b/src/host/hardware_divider/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(divider)
\ No newline at end of file
diff --git a/src/host/hardware_divider/divider.c b/src/host/hardware_divider/divider.c
new file mode 100644
index 0000000..a133179
--- /dev/null
+++ b/src/host/hardware_divider/divider.c
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/divider.h"
+
+__thread uint64_t hw_divider_result_threadlocal;
diff --git a/src/host/hardware_divider/include/hardware/divider.h b/src/host/hardware_divider/include/hardware/divider.h
new file mode 100644
index 0000000..c126688
--- /dev/null
+++ b/src/host/hardware_divider/include/hardware/divider.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_DIVIDER_H
+#define _HARDWARE_DIVIDER_H
+
+#include "pico/types.h"
+
+typedef uint64_t divmod_result_t;
+
+static inline int __sign_of(int32_t v) {
+    return v > 0 ? 1 : (v < 0 ? -1 : 0);
+}
+
+// divides unsigned values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0
+static inline uint64_t hw_divider_divmod_u32(uint32_t a, uint32_t b) {
+    if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-1); // todo check this
+    return (((uint64_t)(a%b))<<32u) | (a/b);
+}
+
+// divides signed values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0
+static inline uint64_t hw_divider_divmod_s32(int32_t a, int32_t b) {
+    if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-__sign_of(a));
+    return (((uint64_t)(a%b))<<32u) | (uint32_t)(a/b);
+}
+
+extern __thread divmod_result_t hw_divider_result_threadlocal;
+
+static inline void hw_divider_divmod_s32_start(int32_t a, int32_t b) {
+    hw_divider_result_threadlocal = hw_divider_divmod_s32(a, b);
+}
+
+static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) {
+    hw_divider_result_threadlocal = hw_divider_divmod_u32(a, b);
+}
+
+static inline divmod_result_t hw_divider_result_wait() {
+    return hw_divider_result_threadlocal;
+}
+
+static inline uint64_t hw_divider_result_nowait() {
+    return hw_divider_result_threadlocal;
+}
+
+inline static uint32_t to_quotient_u32(unsigned long long int r) {
+    return (uint32_t) r;
+}
+
+inline static int32_t to_quotient_s32(unsigned long long int r) {
+    return (int32_t)(uint32_t)r;
+}
+
+inline static uint32_t to_remainder_u32(unsigned long long int r) {
+    return (uint32_t)(r >> 32u);
+}
+
+inline static int32_t to_remainder_s32(unsigned long long int r) {
+    return (int32_t)(r >> 32u);
+}
+
+static inline uint32_t hw_divider_u32_quotient_wait() {
+    return to_quotient_u32(hw_divider_result_wait());
+}
+
+static inline uint32_t hw_divider_u32_remainder_wait() {
+    return to_remainder_u32(hw_divider_result_wait());
+}
+
+static inline int32_t hw_divider_s32_quotient_wait() {
+    return to_quotient_s32(hw_divider_result_wait());
+}
+
+static inline int32_t hw_divider_s32_remainder_wait() {
+    return to_remainder_s32(hw_divider_result_wait());
+}
+
+static inline uint32_t hw_divider_u32_quotient(uint32_t a, uint32_t b) {
+    return b ? (a / b) : (uint32_t)(-1);
+}
+
+static inline uint32_t hw_divider_u32_remainder(uint32_t a, uint32_t b) {
+    return b ? (a % b) : a;
+}
+
+static inline int32_t hw_divider_s32_quotient(int32_t a, int32_t b) {
+    return b ? (a / b) : -__sign_of(a);
+}
+
+static inline int32_t hw_divider_s32_remainder(int32_t a, int32_t b) {
+    return b ? (a % b) : a;
+}
+
+static inline uint32_t hw_divider_u32_quotient_inlined(uint32_t a, uint32_t b) {
+    return hw_divider_u32_quotient(a,b);
+}
+
+static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b) {
+    return hw_divider_u32_remainder(a,b);
+}
+
+static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) {
+    return hw_divider_s32_quotient(a,b);
+}
+
+static inline int32_t hw_divider_s32_remainder_inlined(int32_t a, int32_t b) {
+    return hw_divider_s32_remainder(a,b);
+}
+
+typedef uint64_t hw_divider_state_t;
+
+static inline void hw_divider_save_state(hw_divider_state_t *dest) {
+    *dest = hw_divider_result_threadlocal;
+}
+
+static inline void hw_divider_restore_state(hw_divider_state_t *src) {
+    hw_divider_result_threadlocal = *src;
+}
+
+#endif // _HARDWARE_DIVIDER_H
diff --git a/src/host/hardware_gpio/CMakeLists.txt b/src/host/hardware_gpio/CMakeLists.txt
new file mode 100644
index 0000000..1bfb078
--- /dev/null
+++ b/src/host/hardware_gpio/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(gpio)
\ No newline at end of file
diff --git a/src/host/hardware_gpio/gpio.c b/src/host/hardware_gpio/gpio.c
new file mode 100644
index 0000000..1cbcbed
--- /dev/null
+++ b/src/host/hardware_gpio/gpio.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/gpio.h"
+
+// todo weak or replace? probably weak
+void gpio_set_function(uint gpio, enum gpio_function fn) {
+
+}
+
+void gpio_pull_up(uint gpio) {
+
+}
+
+void gpio_pull_down(uint gpio) {
+
+}
+
+void gpio_disable_pulls(uint gpio) {
+
+}
+
+void gpio_set_pulls(uint gpio, bool up, bool down) {
+
+}
+
+void gpio_set_irqover(uint gpio, uint value) {
+
+}
+
+void gpio_set_outover(uint gpio, uint value) {
+
+}
+
+void gpio_set_inover(uint gpio, uint value) {
+
+}
+
+void gpio_set_oeover(uint gpio, uint value) {
+
+}
+
+void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled){
+
+}
+
+bool gpio_is_input_hysteresis_enabled(uint gpio){
+    return true;
+}
+
+void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew){
+
+}
+
+enum gpio_slew_rate gpio_get_slew_rate(uint gpio){
+    return GPIO_SLEW_RATE_FAST;
+}
+
+void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive){
+
+}
+
+enum gpio_drive_strength gpio_get_drive_strength(uint gpio){
+    return GPIO_DRIVE_STRENGTH_4MA;
+}
+
+
+void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enable) {
+
+}
+
+void gpio_acknowledge_irq(uint gpio, uint32_t events) {
+
+}
+
+void gpio_init(uint gpio) {
+
+}
+
+PICO_WEAK_FUNCTION_DEF(gpio_get)
+
+bool PICO_WEAK_FUNCTION_IMPL_NAME(gpio_get)(uint gpio) {
+    return 0;
+}
+
+uint32_t gpio_get_all() {
+    return 0;
+}
+
+void gpio_set_mask(uint32_t mask) {
+
+}
+
+void gpio_clr_mask(uint32_t mask) {
+
+}
+
+void gpio_xor_mask(uint32_t mask) {
+
+}
+
+void gpio_put_masked(uint32_t mask, uint32_t value) {
+
+}
+
+void gpio_put_all(uint32_t value) {
+
+}
+
+void gpio_put(uint gpio, int value) {
+
+}
+
+void gpio_set_dir_out_masked(uint32_t mask) {
+
+}
+
+void gpio_set_dir_in_masked(uint32_t mask) {
+
+}
+
+void gpio_set_dir_masked(uint32_t mask, uint32_t value) {
+
+}
+
+void gpio_set_dir_all_bits(uint32_t value) {
+
+}
+
+void gpio_set_dir(uint gpio, bool out) {
+
+}
+
+void gpio_debug_pins_init() {
+
+}
+
+void gpio_set_input_enabled(uint gpio, bool enable) {
+
+}
+
+void gpio_init_mask(uint gpio_mask) {
+
+}
diff --git a/src/host/hardware_gpio/include/hardware/gpio.h b/src/host/hardware_gpio/include/hardware/gpio.h
new file mode 100644
index 0000000..b2b83a1
--- /dev/null
+++ b/src/host/hardware_gpio/include/hardware/gpio.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_GPIO_H_
+#define _HARDWARE_GPIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "pico.h"
+
+enum gpio_function {
+    GPIO_FUNC_XIP = 0,
+    GPIO_FUNC_SPI = 1,
+    GPIO_FUNC_UART = 2,
+    GPIO_FUNC_I2C = 3,
+    GPIO_FUNC_PWM = 4,
+    GPIO_FUNC_SIO = 5,
+    GPIO_FUNC_PIO0 = 6,
+    GPIO_FUNC_PIO1 = 7,
+    GPIO_FUNC_GPCK = 8,
+    GPIO_FUNC_USB = 9,
+    GPIO_FUNC_NULL = 0xf,
+};
+
+enum gpio_slew_rate {
+    GPIO_SLEW_RATE_SLOW = 0,  ///< Slew rate limiting enabled
+    GPIO_SLEW_RATE_FAST = 1   ///< Slew rate limiting disabled
+};
+
+enum gpio_drive_strength {
+    GPIO_DRIVE_STRENGTH_2MA = 0, ///< 2 mA nominal drive strength
+    GPIO_DRIVE_STRENGTH_4MA = 1, ///< 4 mA nominal drive strength
+    GPIO_DRIVE_STRENGTH_8MA = 2, ///< 8 mA nominal drive strength
+    GPIO_DRIVE_STRENGTH_12MA = 3 ///< 12 mA nominal drive strength
+};
+
+#define GPIO_OUT 1
+#define GPIO_IN 0
+
+#define NUM_BANK0_GPIOS 30
+
+// ----------------------------------------------------------------------------
+// Pad Controls + IO Muxing
+// ----------------------------------------------------------------------------
+// Declarations for gpio.c
+
+void gpio_set_function(uint gpio, enum gpio_function fn);
+
+enum gpio_function gpio_get_function(uint gpio);
+
+void gpio_pull_up(uint gpio);
+
+void gpio_pull_down(uint gpio);
+
+void gpio_disable_pulls(uint gpio);
+
+void gpio_set_pulls(uint gpio, bool up, bool down);
+
+void gpio_set_irqover(uint gpio, uint value);
+
+void gpio_set_outover(uint gpio, uint value);
+
+void gpio_set_inover(uint gpio, uint value);
+
+void gpio_set_oeover(uint gpio, uint value);
+
+void gpio_set_input_enabled(uint gpio, bool enable);
+
+void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled);
+
+bool gpio_is_input_hysteresis_enabled(uint gpio);
+
+void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew);
+
+enum gpio_slew_rate gpio_get_slew_rate(uint gpio);
+
+void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive);
+
+enum gpio_drive_strength gpio_get_drive_strength(uint gpio);
+
+// Configure a GPIO for direct input/output from software
+void gpio_init(uint gpio);
+
+void gpio_init_mask(uint gpio_mask);
+
+// ----------------------------------------------------------------------------
+// Input
+// ----------------------------------------------------------------------------
+
+// Get the value of a single GPIO
+bool gpio_get(uint gpio);
+
+// Get raw value of all
+uint32_t gpio_get_all();
+
+// ----------------------------------------------------------------------------
+// Output
+// ----------------------------------------------------------------------------
+
+// Drive high every GPIO appearing in mask
+void gpio_set_mask(uint32_t mask);
+
+void gpio_clr_mask(uint32_t mask);
+
+// Toggle every GPIO appearing in mask
+void gpio_xor_mask(uint32_t mask);
+
+
+// For each 1 bit in "mask", drive that pin to the value given by
+// corresponding bit in "value", leaving other pins unchanged.
+// Since this uses the TOGL alias, it is concurrency-safe with e.g. an IRQ
+// bashing different pins from the same core.
+void gpio_put_masked(uint32_t mask, uint32_t value);
+
+// Drive all pins simultaneously
+void gpio_put_all(uint32_t value);
+
+
+// Drive a single GPIO high/low
+void gpio_put(uint gpio, int value);
+
+// ----------------------------------------------------------------------------
+// Direction
+// ----------------------------------------------------------------------------
+
+// Switch all GPIOs in "mask" to output
+void gpio_set_dir_out_masked(uint32_t mask);
+
+// Switch all GPIOs in "mask" to input
+void gpio_set_dir_in_masked(uint32_t mask);
+
+// For each 1 bit in "mask", switch that pin to the direction given by
+// corresponding bit in "value", leaving other pins unchanged.
+// E.g. gpio_set_dir_masked(0x3, 0x2); -> set pin 0 to input, pin 1 to output,
+// simultaneously.
+void gpio_set_dir_masked(uint32_t mask, uint32_t value);
+
+// Set direction of all pins simultaneously.
+// For each bit in value,
+// 1 = out
+// 0 = in
+void gpio_set_dir_all_bits(uint32_t value);
+
+// Set a single GPIO to input/output.
+// true = out
+// 0 = in
+void gpio_set_dir(uint gpio, bool out);
+
+// debugging
+#ifndef PICO_DEBUG_PIN_BASE
+#define PICO_DEBUG_PIN_BASE 19u
+#endif
+
+// note these two macros may only be used once per compilation unit
+#define CU_REGISTER_DEBUG_PINS(p, ...)
+#define CU_SELECT_DEBUG_PINS(x)
+#define DEBUG_PINS_ENABLED(p) false
+
+#define DEBUG_PINS_SET(p, v) ((void)0)
+#define DEBUG_PINS_CLR(p, v) ((void)0)
+#define DEBUG_PINS_XOR(p, v) ((void)0)
+
+void gpio_debug_pins_init();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/host/hardware_sync/CMakeLists.txt b/src/host/hardware_sync/CMakeLists.txt
new file mode 100644
index 0000000..4f69177
--- /dev/null
+++ b/src/host/hardware_sync/CMakeLists.txt
@@ -0,0 +1,12 @@
+pico_simple_hardware_headers_target(sync)
+
+if (NOT TARGET hardware_sync)
+    add_library(hardware_sync INTERFACE)
+
+    target_sources(hardware_sync INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/sync_core0_only.c
+    )
+
+    target_link_libraries(hardware_sync INTERFACE hardware_sync_headers pico_platform)
+endif()
+
diff --git a/src/host/hardware_sync/include/hardware/sync.h b/src/host/hardware_sync/include/hardware/sync.h
new file mode 100644
index 0000000..a27ea01
--- /dev/null
+++ b/src/host/hardware_sync/include/hardware/sync.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_SYNC_H
+#define _HARDWARE_SYNC_H
+
+#include "pico.h"
+
+#ifndef __cplusplus
+
+#if (__STDC_VERSION__ >= 201112L)
+#include <stdatomic.h>
+#else
+enum {
+    memory_order_acquire, memory_order_release
+};
+static inline void atomic_thread_fence(uint x) {}
+#endif
+
+#else
+
+#include <atomic>
+
+#endif
+
+#ifndef PICO_SPINLOCK_ID_TIMER
+#define PICO_SPINLOCK_ID_TIMER 10
+#endif
+
+#ifndef PICO_SPINLOCK_ID_STRIPED_FIRST
+#define PICO_SPINLOCK_ID_STRIPED_FIRST 16
+#endif
+
+#ifndef PICO_SPINLOCK_ID_STRIPED_LAST
+#define PICO_SPINLOCK_ID_STRIPED_LAST 23
+#endif
+
+typedef struct _spin_lock_t spin_lock_t;
+
+inline static void __mem_fence_acquire() {
+#ifndef __cplusplus
+    atomic_thread_fence(memory_order_acquire);
+#else
+    std::atomic_thread_fence(std::memory_order_acquire);
+#endif
+}
+
+inline static void __mem_fence_release() {
+#ifndef __cplusplus
+    atomic_thread_fence(memory_order_release);
+#else
+    std::atomic_thread_fence(std::memory_order_release);
+#endif
+}
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void __sev();
+
+void __wev();
+
+void __wfi();
+
+void __wfe();
+
+uint32_t save_and_disable_interrupts();
+
+void restore_interrupts(uint32_t status);
+
+uint spin_lock_get_num(spin_lock_t *lock);
+
+spin_lock_t *spin_lock_instance(uint lock_num);
+
+void spin_lock_unsafe_blocking(spin_lock_t *lock);
+
+void spin_unlock_unsafe(spin_lock_t *lock);
+
+uint32_t spin_lock_blocking(spin_lock_t *lock);
+
+bool is_spin_locked(const spin_lock_t *lock);
+
+void spin_unlock(spin_lock_t *lock, uint32_t saved_irq);
+
+uint get_core_num();
+
+spin_lock_t *spin_lock_init(uint lock_num);
+
+void clear_spin_locks(void);
+
+uint next_striped_spin_lock_num();
+
+void spin_lock_claim(uint lock_num);
+void spin_lock_claim_mask(uint32_t lock_num_mask);
+void spin_lock_unclaim(uint lock_num);
+int spin_lock_claim_unused(bool required);
+uint spin_lock_num(spin_lock_t *lock);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/src/host/hardware_sync/sync_core0_only.c b/src/host/hardware_sync/sync_core0_only.c
new file mode 100644
index 0000000..878eba6
--- /dev/null
+++ b/src/host/hardware_sync/sync_core0_only.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/sync.h"
+#include "hardware/platform_defs.h"
+
+// This is a dummy implementation that is single threaded
+
+static struct _spin_lock_t {
+    bool locked;
+} _spinlocks[NUM_SPIN_LOCKS];
+
+PICO_WEAK_FUNCTION_DEF(save_and_disable_interrupts)
+
+//static uint8_t striped_spin_lock_num;
+
+uint32_t PICO_WEAK_FUNCTION_IMPL_NAME(save_and_disable_interrupts)() {
+    return 0;
+}
+
+PICO_WEAK_FUNCTION_DEF(restore_interrupts)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(restore_interrupts)(uint32_t status) {
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_instance)
+
+spin_lock_t *PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_instance)(uint lock_num) {
+    assert(lock_num < NUM_SPIN_LOCKS);
+    return &_spinlocks[lock_num];
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_get_num)
+
+uint PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_get_num)(spin_lock_t *lock) {
+    return lock - _spinlocks;
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_init)
+
+spin_lock_t *PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_init)(uint lock_num) {
+    spin_lock_t *lock = spin_lock_instance(lock_num);
+    spin_unlock_unsafe(lock);
+    return lock;
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_unsafe_blocking)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_unsafe_blocking)(spin_lock_t *lock) {
+    lock->locked = true;
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_blocking)
+
+uint32_t PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_blocking)(spin_lock_t *lock) {
+    spin_lock_unsafe_blocking(lock);
+    return 1; // todo wrong value
+}
+
+PICO_WEAK_FUNCTION_DEF(is_spin_locked)
+
+bool PICO_WEAK_FUNCTION_IMPL_NAME(is_spin_locked)(const spin_lock_t *lock) {
+    return lock->locked;
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_unlock_unsafe)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(spin_unlock_unsafe)(spin_lock_t *lock) {
+    lock->locked = false;
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_unlock)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(spin_unlock)(spin_lock_t *lock, uint32_t saved_irq) {
+    spin_unlock_unsafe(lock);
+}
+
+PICO_WEAK_FUNCTION_DEF(__sev)
+
+volatile bool event_fired;
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(__sev)() {
+    event_fired = true;
+}
+
+PICO_WEAK_FUNCTION_DEF(__wfi)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(__wfi)() {
+    panic("Can't wait on irq for host core0 only implementation");
+}
+
+PICO_WEAK_FUNCTION_DEF(__wfe)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(__wfe)() {
+    while (!event_fired) tight_loop_contents();
+}
+
+PICO_WEAK_FUNCTION_DEF(get_core_num)
+
+uint PICO_WEAK_FUNCTION_IMPL_NAME(get_core_num)() {
+    return 0;
+}
+
+PICO_WEAK_FUNCTION_DEF(clear_spin_locks)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(clear_spin_locks)(void) {
+    for (uint i = 0; i < NUM_SPIN_LOCKS; i++) {
+        spin_unlock_unsafe(spin_lock_instance(i));
+    }
+}
+
+PICO_WEAK_FUNCTION_DEF(next_striped_spin_lock_num)
+uint PICO_WEAK_FUNCTION_IMPL_NAME(next_striped_spin_lock_num)() {
+    return 0;
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_claim)
+void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_claim)(uint lock_num) {
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_claim_mask)
+void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_claim_mask)(uint32_t mask) {
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_unclaim)
+void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_unclaim)(uint lock_num) {
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_claim_unused)
+int PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_claim_unused)(bool required) {
+    return 0;
+}
+
+PICO_WEAK_FUNCTION_DEF(spin_lock_num)
+uint PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_num)(spin_lock_t *lock) {
+    return 0;
+}
\ No newline at end of file
diff --git a/src/host/hardware_timer/CMakeLists.txt b/src/host/hardware_timer/CMakeLists.txt
new file mode 100644
index 0000000..ba00444
--- /dev/null
+++ b/src/host/hardware_timer/CMakeLists.txt
@@ -0,0 +1,16 @@
+pico_simple_hardware_target(timer)
+
+target_compile_definitions(hardware_timer INTERFACE
+    PICO_HARDWARE_TIMER_RESOLUTION_US=1000 # to loosen tests a little
+)
+
+if (NOT DEFINED PICO_TIME_NO_ALARM_SUPPORT)
+    # we don't have alarm pools in the basic host support, though pico_host_sdl adds it
+    set(PICO_TIME_NO_ALARM_SUPPORT "1" CACHE INTERNAL "")
+endif()
+
+if (PICO_TIME_NO_ALARM_SUPPORT)
+    target_compile_definitions(hardware_timer INTERFACE
+            PICO_TIME_DEFAULT_ALARM_POOL_DISABLED=1
+    )
+endif()
\ No newline at end of file
diff --git a/src/host/hardware_timer/include/hardware/timer.h b/src/host/hardware_timer/include/hardware/timer.h
new file mode 100644
index 0000000..3ddf427
--- /dev/null
+++ b/src/host/hardware_timer/include/hardware/timer.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_TIMER_H
+#define _HARDWARE_TIMER_H
+
+#include "pico.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifndef PARAM_ASSERTIONS_ENABLED_TIMER
+#define PARAM_ASSERTIONS_ENABLED_TIMER 0
+#endif
+
+static inline void check_hardware_alarm_num_param(uint alarm_num) {
+    invalid_params_if(TIMER, alarm_num >= NUM_TIMERS);
+}
+
+uint32_t time_us_32();
+uint64_t time_us_64();
+void busy_wait_us_32(uint32_t delay_us);
+void busy_wait_us(uint64_t delay_us);
+void busy_wait_until(absolute_time_t t);
+bool time_reached(absolute_time_t t);
+typedef void (*hardware_alarm_callback_t)(uint alarm_num);
+void hardware_alarm_claim(uint alarm_num);
+void hardware_alarm_unclaim(uint alarm_num);
+void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback);
+bool hardware_alarm_set_target(uint alarm_num, absolute_time_t t);
+void hardware_alarm_cancel(uint alarm_num);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/host/hardware_timer/timer.c b/src/host/hardware_timer/timer.c
new file mode 100644
index 0000000..30f6a20
--- /dev/null
+++ b/src/host/hardware_timer/timer.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/timer.h"
+#if defined(__unix__) || defined(__APPLE__)
+#include <unistd.h>
+#include <sys/time.h>
+#include <time.h>
+
+#endif
+
+// in our case not a busy wait
+PICO_WEAK_FUNCTION_DEF(busy_wait_us)
+void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_us_32)(uint32_t delay_us) {
+#if defined(__unix__) || defined(__APPLE__)
+    usleep(delay_us);
+#else
+    assert(false);
+#endif
+}
+PICO_WEAK_FUNCTION_DEF(busy_wait_us)
+void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_us)(uint64_t delay_us) {
+    absolute_time_t t;
+    update_us_since_boot(&t, time_us_64() + delay_us);
+    busy_wait_until(t);
+}
+
+// this may or may not wrap
+PICO_WEAK_FUNCTION_DEF(time_us_64)
+uint64_t PICO_WEAK_FUNCTION_IMPL_NAME(time_us_64)() {
+#if defined(__unix__) || defined(__APPLE__)
+//    struct timeval tv;
+//    gettimeofday(&tv, NULL);
+//    return tv.tv_sec * (uint64_t) 1000000 + tv.tv_usec;
+    struct timespec ts;
+    clock_gettime(CLOCK_MONOTONIC, &ts);
+    return ts.tv_sec * (uint64_t) 1000000 + ts.tv_nsec / 1000;
+#else
+    panic_unsupported();
+#endif
+}
+
+PICO_WEAK_FUNCTION_DEF(timer_us_32)
+uint32_t PICO_WEAK_FUNCTION_IMPL_NAME(timer_us_32)() {
+    return (uint32_t) time_us_64();
+}
+
+PICO_WEAK_FUNCTION_DEF(time_reached)
+bool PICO_WEAK_FUNCTION_IMPL_NAME(time_reached)(absolute_time_t t) {
+    uint64_t target = to_us_since_boot(t);
+    return time_us_64() >= target;
+}
+
+PICO_WEAK_FUNCTION_DEF(busy_wait_until)
+void PICO_WEAK_FUNCTION_IMPL_NAME(busy_wait_until)(absolute_time_t target) {
+#if defined(__unix__)
+    struct timespec tspec;
+    tspec.tv_sec = to_us_since_boot(target) / 1000000;
+    tspec.tv_nsec = (to_us_since_boot(target) % 1000000) * 1000;
+    clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &tspec, NULL);
+#else
+    const int chunk = 1u<<30u;
+    uint64_t target_us = to_us_since_boot(target);
+    uint64_t time_us = time_us_64();
+    while ((int64_t)(target_us - time_us) >= chunk) {
+        busy_wait_us_32(chunk);
+        time_us = time_us_64();
+    }
+    if (target_us > time_us) {
+        busy_wait_us_32(target_us - time_us);
+    }
+#endif
+}
+
+static uint8_t claimed_alarms;
+
+void hardware_alarm_claim(uint alarm_num) {
+    assert(!(claimed_alarms & (1u << alarm_num)));
+    claimed_alarms |= 1u <<alarm_num;
+}
+
+void hardware_alarm_unclaim(uint alarm_num) {
+    assert(claimed_alarms & (1u << alarm_num));
+    claimed_alarms &= ~(1u <<alarm_num);
+}
+
+PICO_WEAK_FUNCTION_DEF(hardware_alarm_set_callback)
+void PICO_WEAK_FUNCTION_IMPL_NAME(hardware_alarm_set_callback)(uint alarm_num, hardware_alarm_callback_t callback) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(hardware_alarm_set_target)
+bool PICO_WEAK_FUNCTION_IMPL_NAME(hardware_alarm_set_target)(uint alarm_num, absolute_time_t target) {
+    panic_unsupported();
+}
+
+PICO_WEAK_FUNCTION_DEF(hardware_alarm_cancel)
+void PICO_WEAK_FUNCTION_IMPL_NAME(hardware_alarm_cancel)(uint alarm_num) {
+    panic_unsupported();
+}
diff --git a/src/host/hardware_uart/CMakeLists.txt b/src/host/hardware_uart/CMakeLists.txt
new file mode 100644
index 0000000..9fe65d5
--- /dev/null
+++ b/src/host/hardware_uart/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(uart)
\ No newline at end of file
diff --git a/src/host/hardware_uart/include/hardware/uart.h b/src/host/hardware_uart/include/hardware/uart.h
new file mode 100644
index 0000000..0c5e890
--- /dev/null
+++ b/src/host/hardware_uart/include/hardware/uart.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_UART_H
+#define _HARDWARE_UART_H
+
+#include "pico.h"
+
+#ifndef PARAM_ASSERTIONS_ENABLED_UART
+#define PARAM_ASSERTIONS_ENABLED_UART 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct uart_inst uart_inst_t;
+
+extern uart_inst_t * const uart0;
+extern uart_inst_t * const uart1;
+#define uart_default uart0
+
+typedef enum {
+    UART_PARITY_NONE,
+    UART_PARITY_EVEN,
+    UART_PARITY_ODD
+} uart_parity_t;
+
+// ----------------------------------------------------------------------------
+// Setup
+
+// Put the UART into a known state, and enable it. Must be called before other
+// functions.
+uint uart_init(uart_inst_t *uart, uint baudrate);
+
+// Disable the UART if it is no longer used. Must be reinitialised before
+// being used again.
+void uart_deinit(uart_inst_t *uart);
+
+// Set baud rate as close as possible to requested, and return actual rate.
+uint uart_set_baudrate(uart_inst_t *uart, uint baudrate);
+
+// cts: enable flow control of TX by clear-to-send input
+// rts: enable assertion of request-to-send output by RX flow control
+void uart_set_hw_flow(uart_inst_t *uart, bool cts, bool rts);
+
+// Configure how the UART serialises and deserialises data on the wire
+void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_bits, uart_parity_t parity);
+
+// Enable the UART's interrupt output. Need to install an interrupt handler first.
+void uart_set_irq_enables(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data);
+
+// ----------------------------------------------------------------------------
+// Generic input/output
+
+// If returns 0, no space is available in the UART to write more data.
+// If returns nonzero, at least that many bytes can be written without blocking.
+size_t uart_is_writable(uart_inst_t *uart);
+
+// If returns 0, no data is available to be read from UART.
+// If returns nonzero, at least that many bytes can be written without blocking.
+size_t uart_is_readable(uart_inst_t *uart);
+
+// Write len bytes directly from src to the UART
+void uart_write_blocking(uart_inst_t *uart, const uint8_t *src, size_t len);
+
+// Read len bytes directly from the UART to dst
+void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t len);
+
+// ----------------------------------------------------------------------------
+// UART-specific operations and aliases
+
+void uart_putc(uart_inst_t *uart, char c);
+
+void uart_puts(uart_inst_t *uart, const char *s);
+
+char uart_getc(uart_inst_t *uart);
+
+// en: assert break condition (TX held low) if true. Clear break condition if false.
+void uart_set_break(uart_inst_t *uart, bool en);
+
+void uart_default_tx_wait_blocking();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/host/hardware_uart/uart.c b/src/host/hardware_uart/uart.c
new file mode 100644
index 0000000..e610402
--- /dev/null
+++ b/src/host/hardware_uart/uart.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include "hardware/uart.h"
+
+#if defined(__unix) || defined(__APPLE__)
+#define _XOPEN_SOURCE 600 /* for ONLCR */
+#define __BSD_VISIBLE 1 /* for ONLCR in *BSD */
+
+#include <unistd.h>
+#include <termios.h>
+#include <fcntl.h>
+#include <stdlib.h>
+
+#ifndef FNONBLOCK
+#define FNONBLOCK O_NONBLOCK
+#endif
+
+struct termios _tty;
+static tcflag_t _res_oflg = 0;
+static tcflag_t _res_lflg = 0;
+
+void _resettty(void) {
+    if (!isatty(STDIN_FILENO))
+        return;
+
+    /* reset tty: */
+    _tty.c_oflag = _res_oflg;
+    _tty.c_lflag = _res_lflg;
+    tcsetattr(STDIN_FILENO, TCSADRAIN, &_tty);
+}
+
+void _inittty(void) {
+    if (!isatty(STDIN_FILENO))
+        return;
+
+    /* save tty: */
+    tcgetattr(STDIN_FILENO, &_tty);
+    _res_oflg = _tty.c_oflag;
+    _res_lflg = _tty.c_lflag;
+
+    /* set raw: */
+    _tty.c_lflag &= ~(ICANON | ICRNL);// | ISIG);
+    //_tty.c_oflag &= ~ONLCR;
+    tcsetattr(STDIN_FILENO, TCSANOW, &_tty);
+
+    fcntl(STDIN_FILENO, F_SETFL, FNONBLOCK);
+    atexit(_resettty);
+}
+
+#else
+void _inittty() {}
+#endif
+
+typedef struct {
+    bool dummy;
+} uart_hw_t;
+
+uart_inst_t *const uart0;
+uart_inst_t *const uart1;
+
+static int _nextchar = EOF;
+
+static bool _peekchar() {
+    if (_nextchar == EOF) {
+        _nextchar = getchar();
+    }
+    return _nextchar != EOF;
+}
+
+uint uart_init(uart_inst_t *uart, uint baud_rate) {
+    _inittty();
+    return baud_rate;
+}
+
+size_t uart_is_writable(uart_inst_t *uart) {
+    return 1;
+}
+
+// If returns 0, no data is available to be read from UART.
+// If returns nonzero, at least that many bytes can be written without blocking.
+size_t uart_is_readable(uart_inst_t *uart) {
+    return _peekchar() ? 1 : 0;
+}
+
+// Write len bytes directly from src to the UART
+void uart_write_blocking(uart_inst_t *uart, const uint8_t *src, size_t len) {
+    for (size_t i = 0; i < len; i++) {
+        uart_putc(uart, src[i]);
+    }
+}
+
+// Read len bytes directly from the UART to dst
+void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t len) {
+    for (size_t i = 0; i < len; i++) {
+        dst[i] = uart_getc(uart);
+    }
+}
+
+// ----------------------------------------------------------------------------
+// UART-specific operations and aliases
+
+void uart_putc(uart_inst_t *uart, char c) {
+    putchar(c);
+}
+
+void uart_puts(uart_inst_t *uart, const char *s) {
+    puts(s);
+}
+
+char uart_getc(uart_inst_t *uart) {
+    while (!_peekchar()) {
+        tight_loop_contents();
+    }
+    char rc = (char) _nextchar;
+    _nextchar = EOF;
+    return rc;
+}
+
+void uart_default_tx_wait_blocking() {
+
+}
diff --git a/src/host/pico_bit_ops/CMakeLists.txt b/src/host/pico_bit_ops/CMakeLists.txt
new file mode 100644
index 0000000..7732b1e
--- /dev/null
+++ b/src/host/pico_bit_ops/CMakeLists.txt
@@ -0,0 +1,9 @@
+pico_add_impl_library(pico_bit_ops)
+
+target_sources(pico_bit_ops INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/bit_ops.c)
+
+target_link_libraries(pico_bit_ops INTERFACE pico_bit_ops_headers)
+
+macro(pico_set_bit_ops_implementation TARGET IMPL)
+endmacro()
\ No newline at end of file
diff --git a/src/host/pico_bit_ops/bit_ops.c b/src/host/pico_bit_ops/bit_ops.c
new file mode 100644
index 0000000..11f69fe
--- /dev/null
+++ b/src/host/pico_bit_ops/bit_ops.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/bit_ops.h"
+
+uint32_t __rev(uint32_t v) {
+    v = ((v & 0x55555555u) << 1u) | ((v >> 1u) & 0x55555555u);
+    v = ((v & 0x33333333u) << 2u) | ((v >> 2u) & 0x33333333u);
+    v = ((v & 0x0f0f0f0fu) << 4u) | ((v >> 4u) & 0x0f0f0f0fu);
+    return (v << 24u) | ((v & 0xff00u) << 8u) | ((v >> 8u) & 0xff00u) | (v >> 24u);
+}
+
+uint64_t __revll(uint64_t v) {
+    v = ((v & 0x5555555555555555u) << 1u) | ((v >> 1u) & 0x5555555555555555u);
+    v = ((v & 0x3333333333333333u) << 2u) | ((v >> 2u) & 0x3333333333333333u);
+    v = ((v & 0x0f0f0f0f0f0f0f0fu) << 4u) | ((v >> 4u) & 0x0f0f0f0f0f0f0f0fu);
+    v = ((v & 0x00ff00ff00ff00ffu) << 8u) | ((v >> 8u) & 0x00ff00ff00ff00ffu);
+    return (v << 48u) | ((v & 0xffff0000u) << 16u) | ((v >> 16u) & 0xffff0000u) | (v >> 48u);
+}
diff --git a/src/host/pico_divider/CMakeLists.txt b/src/host/pico_divider/CMakeLists.txt
new file mode 100644
index 0000000..f6936dd
--- /dev/null
+++ b/src/host/pico_divider/CMakeLists.txt
@@ -0,0 +1,9 @@
+pico_add_impl_library(pico_divider)
+
+target_sources(pico_divider INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/divider.c)
+
+target_link_libraries(pico_divider INTERFACE pico_divider_headers)
+
+macro(pico_set_divider_implementation TARGET IMPL)
+endmacro()
\ No newline at end of file
diff --git a/src/host/pico_divider/divider.c b/src/host/pico_divider/divider.c
new file mode 100644
index 0000000..df0e275
--- /dev/null
+++ b/src/host/pico_divider/divider.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/divider.h"
+
+// These functions save/restore divider state, so are safe to call from interrupts
+int32_t div_s32s32(int32_t a, int32_t b) {
+    return hw_divider_s32_quotient(a, b);
+}
+
+divmod_result_t divmod_s32s32(int32_t a, int32_t b) {
+    return hw_divider_divmod_s32(a, b);
+}
+
+uint32_t div_u32u32(uint32_t a, uint32_t b) {
+    return hw_divider_u32_quotient(a, b);
+}
+
+divmod_result_t divmod_u32u32(uint32_t a, uint32_t b) {
+    return hw_divider_divmod_u32(a, b);
+}
+
+static inline int __sign_of_64(int32_t v) {
+    return v > 0 ? 1 : (v < 0 ? -1 : 0);
+}
+
+typedef struct {
+    uint64_t quotient;
+    uint64_t remainder;
+} qr_u64;
+
+typedef struct {
+    int64_t quotient;
+    int64_t remainder;
+} qr_s64;
+
+// divides unsigned values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0
+static inline qr_u64 udiv64(uint64_t a, uint64_t b) {
+    qr_u64 rc;
+    if (!b) {
+        rc.quotient = (uint64_t)-1; // todo check this
+        rc.remainder = a;
+    } else {
+        rc.quotient = a/b;
+        rc.remainder = a%b;
+    }
+    return rc;
+}
+
+// divides signed values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0
+static inline qr_s64 div64(int64_t a, int64_t b) {
+    qr_s64 rc;
+    if (!b) {
+        rc.quotient = (uint64_t)(-__sign_of_64(a));
+        rc.remainder = a;
+    } else {
+        rc.quotient = a/b;
+        rc.remainder = a%b;
+    }
+    return rc;
+}
+
+int64_t div_s64s64(int64_t a, int64_t b) {
+    qr_s64 qr = div64(a, b);
+    return qr.quotient;
+}
+
+int64_t divmod_s64s64_rem(int64_t a, int64_t b, int64_t *rem) {
+    qr_s64 qr = div64(a, b);
+    *rem = qr.remainder;
+    return qr.quotient;
+}
+
+int64_t divmod_s64s64(int64_t a, int64_t b) {
+    qr_s64 qr = div64(a, b);
+    return qr.quotient;
+}
+
+uint64_t div_u64u64(uint64_t a, uint64_t b) {
+    qr_u64 qr = udiv64(a, b);
+    return qr.quotient;
+}
+
+uint64_t divmod_u64u64_rem(uint64_t a, uint64_t b, uint64_t *rem) {
+    qr_u64 qr = udiv64(a, b);
+    *rem = qr.remainder;
+    return qr.quotient;
+}
+
+uint64_t divmod_u64u64(uint64_t a, uint64_t b) {
+    qr_u64 qr = udiv64(a, b);
+    return qr.quotient;
+}
+
+// these functions are slightly faster, but unsafe the divider state, so are not generally safe to be called from interrupts
+
+int32_t div_s32s32_unsafe(int32_t a, int32_t b) { return div_s32s32(a,b); }
+int32_t divmod_s32s32_rem_unsafe(int32_t a, int32_t b, int32_t *rem) { return divmod_s32s32_rem(a, b, rem); }
+int64_t divmod_s32s32_unsafe(int32_t a, int32_t b) { return divmod_s32s32(a, b); }
+
+uint32_t div_u32u32_unsafe(uint32_t a, uint32_t b) { return div_u32u32(a, b); }
+uint32_t divmod_u32u32_rem_unsafe(uint32_t a, uint32_t b, uint32_t *rem) { return divmod_u32u32_rem(a, b, rem); }
+uint64_t divmod_u32u32_unsafe(uint32_t a, uint32_t b) { return divmod_u32u32(a, b); }
+
+int64_t div_s64s64_unsafe(int64_t a, int64_t b) { return div_s64s64(a, b); }
+int64_t divmod_s64s64_rem_unsafe(int64_t a, int64_t b, int64_t *rem) { return divmod_s64s64_rem(a, b, rem); }
+int64_t divmod_s64s64_unsafe(int64_t a, int64_t b) { return divmod_s64s64(a, b); }
+
+uint64_t div_u64u64_unsafe(uint64_t a, uint64_t b) { return div_u64u64(a, b); }
+uint64_t divmod_u64u64_rem_unsafe(uint64_t a, uint64_t b, uint64_t *rem) { return divmod_u64u64_rem(a, b, rem); }
+uint64_t divmod_u64u64_unsafe(uint64_t a, uint64_t b) { return divmod_u64u64(a, b); }
diff --git a/src/host/pico_multicore/CMakeLists.txt b/src/host/pico_multicore/CMakeLists.txt
new file mode 100644
index 0000000..5b90fa3
--- /dev/null
+++ b/src/host/pico_multicore/CMakeLists.txt
@@ -0,0 +1,8 @@
+if (NOT TARGET pico_multicore)
+    pico_add_impl_library(pico_multicore)
+
+    target_include_directories(pico_multicore INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+endif()
+
+
+
diff --git a/src/host/pico_multicore/include/pico/multicore.h b/src/host/pico_multicore/include/pico/multicore.h
new file mode 100644
index 0000000..1be1694
--- /dev/null
+++ b/src/host/pico_multicore/include/pico/multicore.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_MULTICORE_H
+#define _PICO_MULTICORE_H
+
+#include "pico/types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void multicore_reset_core1(void);
+void multicore_launch_core1(void (*entry)(void));
+void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes);
+void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table);
+
+bool multicore_fifo_rvalid(void);
+bool multicore_fifo_wready(void);
+void multicore_fifo_push_blocking(uint32_t data);
+bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us);
+uint32_t multicore_fifo_pop_blocking();
+bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out);
+void multicore_fifo_drain(void);
+void multicore_fifo_clear_irq(void);
+uint32_t multicore_fifo_get_status(void);
+
+// call this from the lockout victim thread
+void multicore_lockout_victim_init(void);
+
+// start locking out the other core (it will be
+bool multicore_lockout_start_timeout_us(uint64_t timeout_us);
+void multicore_lockout_start_blocking(void);
+
+bool multicore_lockout_end_timeout_us(uint64_t timeout_us);
+void multicore_lockout_end_blocking(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/host/pico_platform/CMakeLists.txt b/src/host/pico_platform/CMakeLists.txt
new file mode 100644
index 0000000..c78e330
--- /dev/null
+++ b/src/host/pico_platform/CMakeLists.txt
@@ -0,0 +1,31 @@
+# This file may be included directly by a build to get common SDK macros and types
+
+if (NOT TARGET pico_platform_headers)
+    add_library(pico_platform_headers INTERFACE)
+
+    target_compile_definitions(pico_platform_headers INTERFACE
+            PICO_NO_HARDWARE=1
+            PICO_ON_DEVICE=0
+            PICO_BUILD=1
+    )
+
+    target_include_directories(pico_platform_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+endif()
+
+if (NOT TARGET pico_platform)
+    if (COMMAND pico_add_platform_library)
+        pico_add_platform_library(pico_platform)
+    else()
+        add_library(pico_platform INTERFACE)
+    endif()
+
+    target_sources(pico_platform INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/platform_base.c
+    )
+
+    target_link_libraries(pico_platform INTERFACE pico_platform_headers pico_bit_ops ${PICO_PLATFORM_EXTRA_LIBRARIES})
+endif()
+
+function(pico_add_platform_library TARGET)
+    target_link_libraries(pico_platform INTERFACE ${TARGET})
+endfunction()
diff --git a/src/host/pico_platform/include/hardware/platform_defs.h b/src/host/pico_platform/include/hardware/platform_defs.h
new file mode 100644
index 0000000..6d0aa84
--- /dev/null
+++ b/src/host/pico_platform/include/hardware/platform_defs.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_PLATFORM_DEFS_H
+#define _HARDWARE_PLATFORM_DEFS_H
+
+#define NUM_CORES 2u
+
+#define NUM_DMA_CHANNELS 12u
+
+#define NUM_TIMERS 4u
+
+#define NUM_IRQS 32u
+
+#define NUM_SPIN_LOCKS 32u
+
+#define XOSC_MHZ 12
+
+#define NUM_SPIN_LOCKS 32u
+
+#ifndef _u
+#define _u(x) x ## u
+#endif
+
+#endif
diff --git a/src/host/pico_platform/include/pico/platform.h b/src/host/pico_platform/include/pico/platform.h
new file mode 100644
index 0000000..27e5c08
--- /dev/null
+++ b/src/host/pico_platform/include/pico/platform.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_PLATFORM_H_
+#define _PICO_PLATFORM_H_
+
+#include "hardware/platform_defs.h"
+#include <stddef.h>
+
+#ifdef __unix__
+
+#include <sys/cdefs.h>
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define __not_in_flash(group)
+#define __not_in_flash_func(func) func
+#define __no_inline_not_in_flash_func(func)
+#define __in_flash(group)
+#define __scratch_x(group)
+#define __scratch_y(group)
+
+#ifndef _MSC_VER
+#define __packed __attribute__((packed))
+#define __packed_aligned __packed __attribute((aligned))
+#else
+// MSVC requires #pragma pack which isn't compatible with a single attribute style define
+#define __packed
+#define __packed_aligned
+#endif
+
+#define __time_critical_func(x) x
+#define __after_data(group)
+
+//int running_on_fpga() { return false; }
+extern void tight_loop_contents();
+
+#ifndef __STRING
+#define __STRING(x) #x
+#endif
+
+#ifndef _MSC_VER
+#ifndef __noreturn
+#define __noreturn __attribute((noreturn))
+#endif
+
+#ifndef __unused
+#define __unused __attribute__((unused))
+#endif
+
+#ifndef __noinline
+#define __noinline __attribute__((noinline))
+#endif
+
+#ifndef __aligned
+#define __aligned(x) __attribute__((aligned(x)))
+#endif
+
+#define PICO_WEAK_FUNCTION_DEF(x) _Pragma(__STRING(weak x))
+#define PICO_WEAK_FUNCTION_IMPL_NAME(x) x
+
+#else
+#ifndef __noreturn
+#define __noreturn __declspec(noreturn)
+#endif
+
+#ifndef __unused
+#define __unused
+#endif
+
+#ifndef __noinline
+#define __noinline __declspec(noinline)
+#endif
+
+#ifndef __aligned
+#define __aligned(x) __declspec(align(x))
+#endif
+
+#ifndef __CONCAT
+#define __CONCAT(x,y) x ## y
+#endif
+
+#define __thread __declspec( thread )
+
+#define PICO_WEAK_FUNCTION_DEF(x) __pragma(comment(linker, __STRING(/alternatename:_##x=_##x##__weak)));
+#define PICO_WEAK_FUNCTION_IMPL_NAME(x) x ## __weak
+
+static __noreturn void __builtin_unreachable() {
+}
+
+#include <intrin.h>
+#define __builtin_clz __lzcnt
+#endif
+
+#ifndef count_of
+#define count_of(a) (sizeof(a)/sizeof((a)[0]))
+#endif
+
+#ifndef MAX
+#define MAX(a, b) ((a)>(b)?(a):(b))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) ((b)>(a)?(a):(b))
+#endif
+
+// abort in our case
+void __noreturn __breakpoint();
+
+void __noreturn panic_unsupported();
+
+void __noreturn panic(const char *fmt, ...);
+
+// arggggghhhh there is a weak function called sem_init used by SDL
+#define sem_init sem_init_alternative
+
+extern uint32_t host_safe_hw_ptr_impl(uintptr_t x);
+// return a 32 bit handle for a raw ptr; DMA chaining for example embeds pointers in 32 bit values
+// which of course does not work if we're running the code natively on a 64 bit platforms. Therefore
+// we provide this macro which allows that code to provide a 64->32 bit mapping in host mode
+#define host_safe_hw_ptr(x) host_safe_hw_ptr_impl((uintptr_t)(x))
+void *decode_host_safe_hw_ptr(uint32_t ptr);
+
+#define __fast_mul(a,b) ((a)*(b))
+
+typedef unsigned int uint;
+
+static inline int32_t __mul_instruction(int32_t a,int32_t b)
+{
+    return a*b;
+}
+
+static inline void __compiler_memory_barrier(void) {
+}
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/src/host/pico_platform/platform_base.c b/src/host/pico_platform/platform_base.c
new file mode 100644
index 0000000..be1dbd4
--- /dev/null
+++ b/src/host/pico_platform/platform_base.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <stdarg.h>
+#include <stdio.h>
+
+#include "pico.h"
+
+PICO_WEAK_FUNCTION_DEF(tight_loop_contents)
+
+void PICO_WEAK_FUNCTION_IMPL_NAME(tight_loop_contents)() {
+
+}
+
+void __noreturn panic_unsupported() {
+    panic("not supported");
+}
+
+void hard_assertion_failure(void) {
+    panic("Hard assert");
+}
+
+void panic(const char *fmt, ...) {
+    va_list args;
+
+    puts("*** PANIC ***\n");
+    if (fmt) {
+        va_start(args, fmt);
+        vprintf(fmt, args);
+        va_end(args);
+    }
+
+    puts("\n");
+
+    __breakpoint();
+}
+
+void __breakpoint() {
+    #ifdef _MSC_VER
+        __debugbreak();
+    #else
+        __builtin_trap();
+    #endif
+}
\ No newline at end of file
diff --git a/src/host/pico_printf/CMakeLists.txt b/src/host/pico_printf/CMakeLists.txt
new file mode 100644
index 0000000..8bfbdee
--- /dev/null
+++ b/src/host/pico_printf/CMakeLists.txt
@@ -0,0 +1,6 @@
+if (NOT TARGET pico_printf)
+    pico_add_impl_library(pico_printf)
+    function(pico_set_printf_implementation)
+    endfunction()
+endif()
+
diff --git a/src/host/pico_stdio/CMakeLists.txt b/src/host/pico_stdio/CMakeLists.txt
new file mode 100644
index 0000000..428c1a9
--- /dev/null
+++ b/src/host/pico_stdio/CMakeLists.txt
@@ -0,0 +1,20 @@
+if (NOT TARGET pico_stdio)
+    pico_add_impl_library(pico_stdio)
+
+    target_include_directories(pico_stdio INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+    target_sources(pico_stdio INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/stdio.c
+            )
+    pico_add_impl_library(pico_stdio_usb)
+    pico_add_impl_library(pico_stdio_uart)
+    pico_add_impl_library(pico_stdio_semihosting)
+    
+    function(pico_enable_stdio_uart)
+    endfunction()
+    function(pico_enable_stdio_usb)
+    endfunction()
+    function(pico_enable_stdio_semihosting)
+    endfunction()
+endif()
+
diff --git a/src/host/pico_stdio/include/pico/stdio.h b/src/host/pico_stdio/include/pico/stdio.h
new file mode 100644
index 0000000..de0bde1
--- /dev/null
+++ b/src/host/pico_stdio/include/pico/stdio.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _PICO_STDIO_H
+#define _PICO_STDIO_H
+
+typedef struct stdio_driver stdio_driver_t;
+
+#define STDIO_ERROR -1
+#define STDIO_NO_INPUT -2
+
+static inline void stdio_usb_init() {}
+void stdio_uart_init();
+static inline void stdio_init_all() { stdio_uart_init(); }
+static inline void stdio_filter_driver(stdio_driver_t *driver) {}
+static inline void stdio_set_translate_crlf(stdio_driver_t *driver, bool enabled) {}
+static inline bool stdio_usb_connected(void) { return true; }
+int getchar_timeout_us(uint32_t timeout_us);
+#define puts_raw puts
+#define putchar_raw putchar
+
+#endif
diff --git a/src/host/pico_stdio/stdio.c b/src/host/pico_stdio/stdio.c
new file mode 100644
index 0000000..87be91d
--- /dev/null
+++ b/src/host/pico_stdio/stdio.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/stdlib.h"
+#include "hardware/uart.h"
+
+int getchar_timeout_us(uint32_t timeout_us) {
+    absolute_time_t t = make_timeout_time_us(timeout_us);
+    while (!uart_is_readable(uart_default)) {
+        if (absolute_time_diff_us(t, get_absolute_time()) > 0) {
+            return STDIO_NO_INPUT;
+        }
+        sleep_ms(1);
+    }
+    return uart_getc(uart_default);
+}
+
+void stdio_uart_init() {
+    uart_init(uart_default, 0);
+}
\ No newline at end of file
diff --git a/src/host/pico_stdlib/CMakeLists.txt b/src/host/pico_stdlib/CMakeLists.txt
new file mode 100644
index 0000000..257798c
--- /dev/null
+++ b/src/host/pico_stdlib/CMakeLists.txt
@@ -0,0 +1,19 @@
+if (NOT TARGET pico_stdlib)
+    pico_add_impl_library(pico_stdlib)
+
+    target_sources(pico_stdlib INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/stdlib.c
+    )
+
+    target_link_libraries(pico_stdlib INTERFACE
+            pico_stdlib_headers
+            pico_platform
+            pico_time
+            pico_divider
+            pico_binary_info
+            pico_printf
+            pico_stdio
+            hardware_gpio
+    )
+endif()
+
diff --git a/src/host/pico_stdlib/stdlib.c b/src/host/pico_stdlib/stdlib.c
new file mode 100644
index 0000000..166bd5f
--- /dev/null
+++ b/src/host/pico_stdlib/stdlib.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/stdlib.h"
+
+void setup_default_uart() {
+
+}
+
+void set_sys_clock_48mhz() {
+
+}
+
+bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_out, uint *postdiv1_out, uint *postdiv2_out) {
+    *vco_out = 1000000;
+    *postdiv1_out = 0;
+    *postdiv2_out = 0;
+    return true;
+}
+
+void set_sys_clock_pll(__unused uint32_t vco_freq, __unused uint post_div1, __unused uint post_div2) {
+
+}
+
diff --git a/src/rp2040.cmake b/src/rp2040.cmake
new file mode 100644
index 0000000..c68df45
--- /dev/null
+++ b/src/rp2040.cmake
@@ -0,0 +1,6 @@
+# include everything needed to build against rp2040
+
+include(rp2_common.cmake)
+
+add_subdirectory(rp2040)
+
diff --git a/src/rp2040/CMakeLists.txt b/src/rp2040/CMakeLists.txt
new file mode 100644
index 0000000..a19ea5c
--- /dev/null
+++ b/src/rp2040/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Targets specific to B0 silicon
+pico_add_subdirectory(hardware_regs)
+pico_add_subdirectory(hardware_structs)
+
+pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR})
+pico_add_doxygen_exclude(${CMAKE_CURRENT_LIST_DIR}/hardware_regs) # very very big
+
+pico_promote_common_scope_vars()
\ No newline at end of file
diff --git a/src/rp2040/README.md b/src/rp2040/README.md
new file mode 100644
index 0000000..b705b35
--- /dev/null
+++ b/src/rp2040/README.md
@@ -0,0 +1,7 @@
+This directory contains header files defining the RP2040 hardware. It is selected when
+`PICO_PLATFORM=rp2040` (the default) is specified for the build
+
+`hardware_regs` contains low level hardware register #defines autogenerated from the RP2040 chip definition itself.
+
+`hardware_structs` contains C structures for accessing memory mapped registers
+
diff --git a/src/rp2040/hardware_regs/CMakeLists.txt b/src/rp2040/hardware_regs/CMakeLists.txt
new file mode 100644
index 0000000..46358ca
--- /dev/null
+++ b/src/rp2040/hardware_regs/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_library(hardware_regs INTERFACE)
+target_include_directories(hardware_regs INTERFACE include)
+target_link_libraries(hardware_regs INTERFACE hardware_base)
diff --git a/src/rp2040/hardware_regs/include/hardware/platform_defs.h b/src/rp2040/hardware_regs/include/hardware/platform_defs.h
new file mode 100644
index 0000000..08c7159
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/platform_defs.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_PLATFORM_DEFS_H
+#define _HARDWARE_PLATFORM_DEFS_H
+
+// This header is included from C and assembler - intended mostly for #defines; guard other stuff with #ifdef __ASSEMBLER__
+
+#ifndef _u
+#ifdef __ASSEMBLER__
+#define _u(x) x
+#else
+#define _u(x) x ## u
+#endif
+#endif
+
+#define NUM_CORES _u(2)
+#define NUM_DMA_CHANNELS _u(12)
+#define NUM_DMA_TIMERS _u(4)
+#define NUM_IRQS _u(32)
+#define NUM_PIOS _u(2)
+#define NUM_PIO_STATE_MACHINES _u(4)
+#define NUM_PWM_SLICES _u(8)
+#define NUM_SPIN_LOCKS _u(32)
+#define NUM_UARTS _u(2)
+#define NUM_I2CS _u(2)
+#define NUM_SPIS _u(2)
+#define NUM_TIMERS _u(4)
+#define NUM_ADC_CHANNELS _u(5)
+
+#define NUM_BANK0_GPIOS _u(30)
+#define NUM_QSPI_GPIOS _u(6)
+
+#define PIO_INSTRUCTION_COUNT _u(32)
+
+// PICO_CONFIG: XOSC_MHZ, The crystal oscillator frequency in Mhz, type=int, default=12, advanced=true, group=hardware_base
+#ifndef XOSC_MHZ
+#define XOSC_MHZ _u(12)
+#endif
+
+#endif
+
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/adc.h b/src/rp2040/hardware_regs/include/hardware/regs/adc.h
new file mode 100644
index 0000000..47510be
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/adc.h
@@ -0,0 +1,314 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : ADC
+// Version        : 2
+// Bus type       : apb
+// Description    : Control and data interface to SAR ADC
+// =============================================================================
+#ifndef HARDWARE_REGS_ADC_DEFINED
+#define HARDWARE_REGS_ADC_DEFINED
+// =============================================================================
+// Register    : ADC_CS
+// Description : ADC Control and Status
+#define ADC_CS_OFFSET _u(0x00000000)
+#define ADC_CS_BITS   _u(0x001f770f)
+#define ADC_CS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : ADC_CS_RROBIN
+// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to
+//               disable.
+//               Otherwise, the ADC will cycle through each enabled channel in a
+//               round-robin fashion.
+//               The first channel to be sampled will be the one currently
+//               indicated by AINSEL.
+//               AINSEL will be updated after each conversion with the
+//               newly-selected channel.
+#define ADC_CS_RROBIN_RESET  _u(0x00)
+#define ADC_CS_RROBIN_BITS   _u(0x001f0000)
+#define ADC_CS_RROBIN_MSB    _u(20)
+#define ADC_CS_RROBIN_LSB    _u(16)
+#define ADC_CS_RROBIN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ADC_CS_AINSEL
+// Description : Select analog mux input. Updated automatically in round-robin
+//               mode.
+#define ADC_CS_AINSEL_RESET  _u(0x0)
+#define ADC_CS_AINSEL_BITS   _u(0x00007000)
+#define ADC_CS_AINSEL_MSB    _u(14)
+#define ADC_CS_AINSEL_LSB    _u(12)
+#define ADC_CS_AINSEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ADC_CS_ERR_STICKY
+// Description : Some past ADC conversion encountered an error. Write 1 to
+//               clear.
+#define ADC_CS_ERR_STICKY_RESET  _u(0x0)
+#define ADC_CS_ERR_STICKY_BITS   _u(0x00000400)
+#define ADC_CS_ERR_STICKY_MSB    _u(10)
+#define ADC_CS_ERR_STICKY_LSB    _u(10)
+#define ADC_CS_ERR_STICKY_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : ADC_CS_ERR
+// Description : The most recent ADC conversion encountered an error; result is
+//               undefined or noisy.
+#define ADC_CS_ERR_RESET  _u(0x0)
+#define ADC_CS_ERR_BITS   _u(0x00000200)
+#define ADC_CS_ERR_MSB    _u(9)
+#define ADC_CS_ERR_LSB    _u(9)
+#define ADC_CS_ERR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : ADC_CS_READY
+// Description : 1 if the ADC is ready to start a new conversion. Implies any
+//               previous conversion has completed.
+//               0 whilst conversion in progress.
+#define ADC_CS_READY_RESET  _u(0x0)
+#define ADC_CS_READY_BITS   _u(0x00000100)
+#define ADC_CS_READY_MSB    _u(8)
+#define ADC_CS_READY_LSB    _u(8)
+#define ADC_CS_READY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : ADC_CS_START_MANY
+// Description : Continuously perform conversions whilst this bit is 1. A new
+//               conversion will start immediately after the previous finishes.
+#define ADC_CS_START_MANY_RESET  _u(0x0)
+#define ADC_CS_START_MANY_BITS   _u(0x00000008)
+#define ADC_CS_START_MANY_MSB    _u(3)
+#define ADC_CS_START_MANY_LSB    _u(3)
+#define ADC_CS_START_MANY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ADC_CS_START_ONCE
+// Description : Start a single conversion. Self-clearing. Ignored if start_many
+//               is asserted.
+#define ADC_CS_START_ONCE_RESET  _u(0x0)
+#define ADC_CS_START_ONCE_BITS   _u(0x00000004)
+#define ADC_CS_START_ONCE_MSB    _u(2)
+#define ADC_CS_START_ONCE_LSB    _u(2)
+#define ADC_CS_START_ONCE_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : ADC_CS_TS_EN
+// Description : Power on temperature sensor. 1 - enabled. 0 - disabled.
+#define ADC_CS_TS_EN_RESET  _u(0x0)
+#define ADC_CS_TS_EN_BITS   _u(0x00000002)
+#define ADC_CS_TS_EN_MSB    _u(1)
+#define ADC_CS_TS_EN_LSB    _u(1)
+#define ADC_CS_TS_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ADC_CS_EN
+// Description : Power on ADC and enable its clock.
+//               1 - enabled. 0 - disabled.
+#define ADC_CS_EN_RESET  _u(0x0)
+#define ADC_CS_EN_BITS   _u(0x00000001)
+#define ADC_CS_EN_MSB    _u(0)
+#define ADC_CS_EN_LSB    _u(0)
+#define ADC_CS_EN_ACCESS "RW"
+// =============================================================================
+// Register    : ADC_RESULT
+// Description : Result of most recent ADC conversion
+#define ADC_RESULT_OFFSET _u(0x00000004)
+#define ADC_RESULT_BITS   _u(0x00000fff)
+#define ADC_RESULT_RESET  _u(0x00000000)
+#define ADC_RESULT_MSB    _u(11)
+#define ADC_RESULT_LSB    _u(0)
+#define ADC_RESULT_ACCESS "RO"
+// =============================================================================
+// Register    : ADC_FCS
+// Description : FIFO control and status
+#define ADC_FCS_OFFSET _u(0x00000008)
+#define ADC_FCS_BITS   _u(0x0f0f0f0f)
+#define ADC_FCS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : ADC_FCS_THRESH
+// Description : DREQ/IRQ asserted when level >= threshold
+#define ADC_FCS_THRESH_RESET  _u(0x0)
+#define ADC_FCS_THRESH_BITS   _u(0x0f000000)
+#define ADC_FCS_THRESH_MSB    _u(27)
+#define ADC_FCS_THRESH_LSB    _u(24)
+#define ADC_FCS_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ADC_FCS_LEVEL
+// Description : The number of conversion results currently waiting in the FIFO
+#define ADC_FCS_LEVEL_RESET  _u(0x0)
+#define ADC_FCS_LEVEL_BITS   _u(0x000f0000)
+#define ADC_FCS_LEVEL_MSB    _u(19)
+#define ADC_FCS_LEVEL_LSB    _u(16)
+#define ADC_FCS_LEVEL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : ADC_FCS_OVER
+// Description : 1 if the FIFO has been overflowed. Write 1 to clear.
+#define ADC_FCS_OVER_RESET  _u(0x0)
+#define ADC_FCS_OVER_BITS   _u(0x00000800)
+#define ADC_FCS_OVER_MSB    _u(11)
+#define ADC_FCS_OVER_LSB    _u(11)
+#define ADC_FCS_OVER_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : ADC_FCS_UNDER
+// Description : 1 if the FIFO has been underflowed. Write 1 to clear.
+#define ADC_FCS_UNDER_RESET  _u(0x0)
+#define ADC_FCS_UNDER_BITS   _u(0x00000400)
+#define ADC_FCS_UNDER_MSB    _u(10)
+#define ADC_FCS_UNDER_LSB    _u(10)
+#define ADC_FCS_UNDER_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : ADC_FCS_FULL
+// Description : None
+#define ADC_FCS_FULL_RESET  _u(0x0)
+#define ADC_FCS_FULL_BITS   _u(0x00000200)
+#define ADC_FCS_FULL_MSB    _u(9)
+#define ADC_FCS_FULL_LSB    _u(9)
+#define ADC_FCS_FULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : ADC_FCS_EMPTY
+// Description : None
+#define ADC_FCS_EMPTY_RESET  _u(0x0)
+#define ADC_FCS_EMPTY_BITS   _u(0x00000100)
+#define ADC_FCS_EMPTY_MSB    _u(8)
+#define ADC_FCS_EMPTY_LSB    _u(8)
+#define ADC_FCS_EMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : ADC_FCS_DREQ_EN
+// Description : If 1: assert DMA requests when FIFO contains data
+#define ADC_FCS_DREQ_EN_RESET  _u(0x0)
+#define ADC_FCS_DREQ_EN_BITS   _u(0x00000008)
+#define ADC_FCS_DREQ_EN_MSB    _u(3)
+#define ADC_FCS_DREQ_EN_LSB    _u(3)
+#define ADC_FCS_DREQ_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ADC_FCS_ERR
+// Description : If 1: conversion error bit appears in the FIFO alongside the
+//               result
+#define ADC_FCS_ERR_RESET  _u(0x0)
+#define ADC_FCS_ERR_BITS   _u(0x00000004)
+#define ADC_FCS_ERR_MSB    _u(2)
+#define ADC_FCS_ERR_LSB    _u(2)
+#define ADC_FCS_ERR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ADC_FCS_SHIFT
+// Description : If 1: FIFO results are right-shifted to be one byte in size.
+//               Enables DMA to byte buffers.
+#define ADC_FCS_SHIFT_RESET  _u(0x0)
+#define ADC_FCS_SHIFT_BITS   _u(0x00000002)
+#define ADC_FCS_SHIFT_MSB    _u(1)
+#define ADC_FCS_SHIFT_LSB    _u(1)
+#define ADC_FCS_SHIFT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ADC_FCS_EN
+// Description : If 1: write result to the FIFO after each conversion.
+#define ADC_FCS_EN_RESET  _u(0x0)
+#define ADC_FCS_EN_BITS   _u(0x00000001)
+#define ADC_FCS_EN_MSB    _u(0)
+#define ADC_FCS_EN_LSB    _u(0)
+#define ADC_FCS_EN_ACCESS "RW"
+// =============================================================================
+// Register    : ADC_FIFO
+// Description : Conversion result FIFO
+#define ADC_FIFO_OFFSET _u(0x0000000c)
+#define ADC_FIFO_BITS   _u(0x00008fff)
+#define ADC_FIFO_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : ADC_FIFO_ERR
+// Description : 1 if this particular sample experienced a conversion error.
+//               Remains in the same location if the sample is shifted.
+#define ADC_FIFO_ERR_RESET  "-"
+#define ADC_FIFO_ERR_BITS   _u(0x00008000)
+#define ADC_FIFO_ERR_MSB    _u(15)
+#define ADC_FIFO_ERR_LSB    _u(15)
+#define ADC_FIFO_ERR_ACCESS "RF"
+// -----------------------------------------------------------------------------
+// Field       : ADC_FIFO_VAL
+// Description : None
+#define ADC_FIFO_VAL_RESET  "-"
+#define ADC_FIFO_VAL_BITS   _u(0x00000fff)
+#define ADC_FIFO_VAL_MSB    _u(11)
+#define ADC_FIFO_VAL_LSB    _u(0)
+#define ADC_FIFO_VAL_ACCESS "RF"
+// =============================================================================
+// Register    : ADC_DIV
+// Description : Clock divider. If non-zero, CS_START_MANY will start
+//               conversions
+//               at regular intervals rather than back-to-back.
+//               The divider is reset when either of these fields are written.
+//               Total period is 1 + INT + FRAC / 256
+#define ADC_DIV_OFFSET _u(0x00000010)
+#define ADC_DIV_BITS   _u(0x00ffffff)
+#define ADC_DIV_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : ADC_DIV_INT
+// Description : Integer part of clock divisor.
+#define ADC_DIV_INT_RESET  _u(0x0000)
+#define ADC_DIV_INT_BITS   _u(0x00ffff00)
+#define ADC_DIV_INT_MSB    _u(23)
+#define ADC_DIV_INT_LSB    _u(8)
+#define ADC_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ADC_DIV_FRAC
+// Description : Fractional part of clock divisor. First-order delta-sigma.
+#define ADC_DIV_FRAC_RESET  _u(0x00)
+#define ADC_DIV_FRAC_BITS   _u(0x000000ff)
+#define ADC_DIV_FRAC_MSB    _u(7)
+#define ADC_DIV_FRAC_LSB    _u(0)
+#define ADC_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : ADC_INTR
+// Description : Raw Interrupts
+#define ADC_INTR_OFFSET _u(0x00000014)
+#define ADC_INTR_BITS   _u(0x00000001)
+#define ADC_INTR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : ADC_INTR_FIFO
+// Description : Triggered when the sample FIFO reaches a certain level.
+//               This level can be programmed via the FCS_THRESH field.
+#define ADC_INTR_FIFO_RESET  _u(0x0)
+#define ADC_INTR_FIFO_BITS   _u(0x00000001)
+#define ADC_INTR_FIFO_MSB    _u(0)
+#define ADC_INTR_FIFO_LSB    _u(0)
+#define ADC_INTR_FIFO_ACCESS "RO"
+// =============================================================================
+// Register    : ADC_INTE
+// Description : Interrupt Enable
+#define ADC_INTE_OFFSET _u(0x00000018)
+#define ADC_INTE_BITS   _u(0x00000001)
+#define ADC_INTE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : ADC_INTE_FIFO
+// Description : Triggered when the sample FIFO reaches a certain level.
+//               This level can be programmed via the FCS_THRESH field.
+#define ADC_INTE_FIFO_RESET  _u(0x0)
+#define ADC_INTE_FIFO_BITS   _u(0x00000001)
+#define ADC_INTE_FIFO_MSB    _u(0)
+#define ADC_INTE_FIFO_LSB    _u(0)
+#define ADC_INTE_FIFO_ACCESS "RW"
+// =============================================================================
+// Register    : ADC_INTF
+// Description : Interrupt Force
+#define ADC_INTF_OFFSET _u(0x0000001c)
+#define ADC_INTF_BITS   _u(0x00000001)
+#define ADC_INTF_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : ADC_INTF_FIFO
+// Description : Triggered when the sample FIFO reaches a certain level.
+//               This level can be programmed via the FCS_THRESH field.
+#define ADC_INTF_FIFO_RESET  _u(0x0)
+#define ADC_INTF_FIFO_BITS   _u(0x00000001)
+#define ADC_INTF_FIFO_MSB    _u(0)
+#define ADC_INTF_FIFO_LSB    _u(0)
+#define ADC_INTF_FIFO_ACCESS "RW"
+// =============================================================================
+// Register    : ADC_INTS
+// Description : Interrupt status after masking & forcing
+#define ADC_INTS_OFFSET _u(0x00000020)
+#define ADC_INTS_BITS   _u(0x00000001)
+#define ADC_INTS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : ADC_INTS_FIFO
+// Description : Triggered when the sample FIFO reaches a certain level.
+//               This level can be programmed via the FCS_THRESH field.
+#define ADC_INTS_FIFO_RESET  _u(0x0)
+#define ADC_INTS_FIFO_BITS   _u(0x00000001)
+#define ADC_INTS_FIFO_MSB    _u(0)
+#define ADC_INTS_FIFO_LSB    _u(0)
+#define ADC_INTS_FIFO_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_ADC_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/addressmap.h b/src/rp2040/hardware_regs/include/hardware/regs/addressmap.h
new file mode 100644
index 0000000..b39ab45
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/addressmap.h
@@ -0,0 +1,74 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _ADDRESSMAP_H_
+#define _ADDRESSMAP_H_
+
+#include "hardware/platform_defs.h"
+
+// Register address offsets for atomic RMW aliases
+#define REG_ALIAS_RW_BITS  (0x0u << 12u)
+#define REG_ALIAS_XOR_BITS (0x1u << 12u)
+#define REG_ALIAS_SET_BITS (0x2u << 12u)
+#define REG_ALIAS_CLR_BITS (0x3u << 12u)
+
+#define ROM_BASE _u(0x00000000)
+#define XIP_BASE _u(0x10000000)
+#define XIP_MAIN_BASE _u(0x10000000)
+#define XIP_NOALLOC_BASE _u(0x11000000)
+#define XIP_NOCACHE_BASE _u(0x12000000)
+#define XIP_NOCACHE_NOALLOC_BASE _u(0x13000000)
+#define XIP_CTRL_BASE _u(0x14000000)
+#define XIP_SRAM_BASE _u(0x15000000)
+#define XIP_SRAM_END _u(0x15004000)
+#define XIP_SSI_BASE _u(0x18000000)
+#define SRAM_BASE _u(0x20000000)
+#define SRAM_STRIPED_BASE _u(0x20000000)
+#define SRAM_STRIPED_END _u(0x20040000)
+#define SRAM4_BASE _u(0x20040000)
+#define SRAM5_BASE _u(0x20041000)
+#define SRAM_END _u(0x20042000)
+#define SRAM0_BASE _u(0x21000000)
+#define SRAM1_BASE _u(0x21010000)
+#define SRAM2_BASE _u(0x21020000)
+#define SRAM3_BASE _u(0x21030000)
+#define SYSINFO_BASE _u(0x40000000)
+#define SYSCFG_BASE _u(0x40004000)
+#define CLOCKS_BASE _u(0x40008000)
+#define RESETS_BASE _u(0x4000c000)
+#define PSM_BASE _u(0x40010000)
+#define IO_BANK0_BASE _u(0x40014000)
+#define IO_QSPI_BASE _u(0x40018000)
+#define PADS_BANK0_BASE _u(0x4001c000)
+#define PADS_QSPI_BASE _u(0x40020000)
+#define XOSC_BASE _u(0x40024000)
+#define PLL_SYS_BASE _u(0x40028000)
+#define PLL_USB_BASE _u(0x4002c000)
+#define BUSCTRL_BASE _u(0x40030000)
+#define UART0_BASE _u(0x40034000)
+#define UART1_BASE _u(0x40038000)
+#define SPI0_BASE _u(0x4003c000)
+#define SPI1_BASE _u(0x40040000)
+#define I2C0_BASE _u(0x40044000)
+#define I2C1_BASE _u(0x40048000)
+#define ADC_BASE _u(0x4004c000)
+#define PWM_BASE _u(0x40050000)
+#define TIMER_BASE _u(0x40054000)
+#define WATCHDOG_BASE _u(0x40058000)
+#define RTC_BASE _u(0x4005c000)
+#define ROSC_BASE _u(0x40060000)
+#define VREG_AND_CHIP_RESET_BASE _u(0x40064000)
+#define TBMAN_BASE _u(0x4006c000)
+#define DMA_BASE _u(0x50000000)
+#define USBCTRL_DPRAM_BASE _u(0x50100000)
+#define USBCTRL_BASE _u(0x50100000)
+#define USBCTRL_REGS_BASE _u(0x50110000)
+#define PIO0_BASE _u(0x50200000)
+#define PIO1_BASE _u(0x50300000)
+#define XIP_AUX_BASE _u(0x50400000)
+#define SIO_BASE _u(0xd0000000)
+#define PPB_BASE _u(0xe0000000)
+
+#endif // _ADDRESSMAP_H_
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/busctrl.h b/src/rp2040/hardware_regs/include/hardware/regs/busctrl.h
new file mode 100644
index 0000000..8be0d86
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/busctrl.h
@@ -0,0 +1,324 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : BUSCTRL
+// Version        : 1
+// Bus type       : apb
+// Description    : Register block for busfabric control signals and performance
+//                  counters
+// =============================================================================
+#ifndef HARDWARE_REGS_BUSCTRL_DEFINED
+#define HARDWARE_REGS_BUSCTRL_DEFINED
+// =============================================================================
+// Register    : BUSCTRL_BUS_PRIORITY
+// Description : Set the priority of each master for bus arbitration.
+#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000)
+#define BUSCTRL_BUS_PRIORITY_BITS   _u(0x00001111)
+#define BUSCTRL_BUS_PRIORITY_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : BUSCTRL_BUS_PRIORITY_DMA_W
+// Description : 0 - low priority, 1 - high priority
+#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET  _u(0x0)
+#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS   _u(0x00001000)
+#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB    _u(12)
+#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB    _u(12)
+#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : BUSCTRL_BUS_PRIORITY_DMA_R
+// Description : 0 - low priority, 1 - high priority
+#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET  _u(0x0)
+#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS   _u(0x00000100)
+#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB    _u(8)
+#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB    _u(8)
+#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : BUSCTRL_BUS_PRIORITY_PROC1
+// Description : 0 - low priority, 1 - high priority
+#define BUSCTRL_BUS_PRIORITY_PROC1_RESET  _u(0x0)
+#define BUSCTRL_BUS_PRIORITY_PROC1_BITS   _u(0x00000010)
+#define BUSCTRL_BUS_PRIORITY_PROC1_MSB    _u(4)
+#define BUSCTRL_BUS_PRIORITY_PROC1_LSB    _u(4)
+#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : BUSCTRL_BUS_PRIORITY_PROC0
+// Description : 0 - low priority, 1 - high priority
+#define BUSCTRL_BUS_PRIORITY_PROC0_RESET  _u(0x0)
+#define BUSCTRL_BUS_PRIORITY_PROC0_BITS   _u(0x00000001)
+#define BUSCTRL_BUS_PRIORITY_PROC0_MSB    _u(0)
+#define BUSCTRL_BUS_PRIORITY_PROC0_LSB    _u(0)
+#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW"
+// =============================================================================
+// Register    : BUSCTRL_BUS_PRIORITY_ACK
+// Description : Bus priority acknowledge
+//               Goes to 1 once all arbiters have registered the new global
+//               priority levels.
+//               Arbiters update their local priority when servicing a new
+//               nonsequential access.
+//               In normal circumstances this will happen almost immediately.
+#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004)
+#define BUSCTRL_BUS_PRIORITY_ACK_BITS   _u(0x00000001)
+#define BUSCTRL_BUS_PRIORITY_ACK_RESET  _u(0x00000000)
+#define BUSCTRL_BUS_PRIORITY_ACK_MSB    _u(0)
+#define BUSCTRL_BUS_PRIORITY_ACK_LSB    _u(0)
+#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO"
+// =============================================================================
+// Register    : BUSCTRL_PERFCTR0
+// Description : Bus fabric performance counter 0
+//               Busfabric saturating performance counter 0
+//               Count some event signal from the busfabric arbiters.
+//               Write any value to clear. Select an event to count using
+//               PERFSEL0
+#define BUSCTRL_PERFCTR0_OFFSET _u(0x00000008)
+#define BUSCTRL_PERFCTR0_BITS   _u(0x00ffffff)
+#define BUSCTRL_PERFCTR0_RESET  _u(0x00000000)
+#define BUSCTRL_PERFCTR0_MSB    _u(23)
+#define BUSCTRL_PERFCTR0_LSB    _u(0)
+#define BUSCTRL_PERFCTR0_ACCESS "WC"
+// =============================================================================
+// Register    : BUSCTRL_PERFSEL0
+// Description : Bus fabric performance event select for PERFCTR0
+//               Select an event for PERFCTR0. Count either contested accesses,
+//               or all accesses, on a downstream port of the main crossbar.
+//               0x00 -> apb_contested
+//               0x01 -> apb
+//               0x02 -> fastperi_contested
+//               0x03 -> fastperi
+//               0x04 -> sram5_contested
+//               0x05 -> sram5
+//               0x06 -> sram4_contested
+//               0x07 -> sram4
+//               0x08 -> sram3_contested
+//               0x09 -> sram3
+//               0x0a -> sram2_contested
+//               0x0b -> sram2
+//               0x0c -> sram1_contested
+//               0x0d -> sram1
+//               0x0e -> sram0_contested
+//               0x0f -> sram0
+//               0x10 -> xip_main_contested
+//               0x11 -> xip_main
+//               0x12 -> rom_contested
+//               0x13 -> rom
+#define BUSCTRL_PERFSEL0_OFFSET                   _u(0x0000000c)
+#define BUSCTRL_PERFSEL0_BITS                     _u(0x0000001f)
+#define BUSCTRL_PERFSEL0_RESET                    _u(0x0000001f)
+#define BUSCTRL_PERFSEL0_MSB                      _u(4)
+#define BUSCTRL_PERFSEL0_LSB                      _u(0)
+#define BUSCTRL_PERFSEL0_ACCESS                   "RW"
+#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED      _u(0x00)
+#define BUSCTRL_PERFSEL0_VALUE_APB                _u(0x01)
+#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED _u(0x02)
+#define BUSCTRL_PERFSEL0_VALUE_FASTPERI           _u(0x03)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED    _u(0x04)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM5              _u(0x05)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED    _u(0x06)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM4              _u(0x07)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED    _u(0x08)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM3              _u(0x09)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED    _u(0x0a)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM2              _u(0x0b)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED    _u(0x0c)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM1              _u(0x0d)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED    _u(0x0e)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM0              _u(0x0f)
+#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED _u(0x10)
+#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN           _u(0x11)
+#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED      _u(0x12)
+#define BUSCTRL_PERFSEL0_VALUE_ROM                _u(0x13)
+// =============================================================================
+// Register    : BUSCTRL_PERFCTR1
+// Description : Bus fabric performance counter 1
+//               Busfabric saturating performance counter 1
+//               Count some event signal from the busfabric arbiters.
+//               Write any value to clear. Select an event to count using
+//               PERFSEL1
+#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000010)
+#define BUSCTRL_PERFCTR1_BITS   _u(0x00ffffff)
+#define BUSCTRL_PERFCTR1_RESET  _u(0x00000000)
+#define BUSCTRL_PERFCTR1_MSB    _u(23)
+#define BUSCTRL_PERFCTR1_LSB    _u(0)
+#define BUSCTRL_PERFCTR1_ACCESS "WC"
+// =============================================================================
+// Register    : BUSCTRL_PERFSEL1
+// Description : Bus fabric performance event select for PERFCTR1
+//               Select an event for PERFCTR1. Count either contested accesses,
+//               or all accesses, on a downstream port of the main crossbar.
+//               0x00 -> apb_contested
+//               0x01 -> apb
+//               0x02 -> fastperi_contested
+//               0x03 -> fastperi
+//               0x04 -> sram5_contested
+//               0x05 -> sram5
+//               0x06 -> sram4_contested
+//               0x07 -> sram4
+//               0x08 -> sram3_contested
+//               0x09 -> sram3
+//               0x0a -> sram2_contested
+//               0x0b -> sram2
+//               0x0c -> sram1_contested
+//               0x0d -> sram1
+//               0x0e -> sram0_contested
+//               0x0f -> sram0
+//               0x10 -> xip_main_contested
+//               0x11 -> xip_main
+//               0x12 -> rom_contested
+//               0x13 -> rom
+#define BUSCTRL_PERFSEL1_OFFSET                   _u(0x00000014)
+#define BUSCTRL_PERFSEL1_BITS                     _u(0x0000001f)
+#define BUSCTRL_PERFSEL1_RESET                    _u(0x0000001f)
+#define BUSCTRL_PERFSEL1_MSB                      _u(4)
+#define BUSCTRL_PERFSEL1_LSB                      _u(0)
+#define BUSCTRL_PERFSEL1_ACCESS                   "RW"
+#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED      _u(0x00)
+#define BUSCTRL_PERFSEL1_VALUE_APB                _u(0x01)
+#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED _u(0x02)
+#define BUSCTRL_PERFSEL1_VALUE_FASTPERI           _u(0x03)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED    _u(0x04)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM5              _u(0x05)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED    _u(0x06)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM4              _u(0x07)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED    _u(0x08)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM3              _u(0x09)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED    _u(0x0a)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM2              _u(0x0b)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED    _u(0x0c)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM1              _u(0x0d)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED    _u(0x0e)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM0              _u(0x0f)
+#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED _u(0x10)
+#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN           _u(0x11)
+#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED      _u(0x12)
+#define BUSCTRL_PERFSEL1_VALUE_ROM                _u(0x13)
+// =============================================================================
+// Register    : BUSCTRL_PERFCTR2
+// Description : Bus fabric performance counter 2
+//               Busfabric saturating performance counter 2
+//               Count some event signal from the busfabric arbiters.
+//               Write any value to clear. Select an event to count using
+//               PERFSEL2
+#define BUSCTRL_PERFCTR2_OFFSET _u(0x00000018)
+#define BUSCTRL_PERFCTR2_BITS   _u(0x00ffffff)
+#define BUSCTRL_PERFCTR2_RESET  _u(0x00000000)
+#define BUSCTRL_PERFCTR2_MSB    _u(23)
+#define BUSCTRL_PERFCTR2_LSB    _u(0)
+#define BUSCTRL_PERFCTR2_ACCESS "WC"
+// =============================================================================
+// Register    : BUSCTRL_PERFSEL2
+// Description : Bus fabric performance event select for PERFCTR2
+//               Select an event for PERFCTR2. Count either contested accesses,
+//               or all accesses, on a downstream port of the main crossbar.
+//               0x00 -> apb_contested
+//               0x01 -> apb
+//               0x02 -> fastperi_contested
+//               0x03 -> fastperi
+//               0x04 -> sram5_contested
+//               0x05 -> sram5
+//               0x06 -> sram4_contested
+//               0x07 -> sram4
+//               0x08 -> sram3_contested
+//               0x09 -> sram3
+//               0x0a -> sram2_contested
+//               0x0b -> sram2
+//               0x0c -> sram1_contested
+//               0x0d -> sram1
+//               0x0e -> sram0_contested
+//               0x0f -> sram0
+//               0x10 -> xip_main_contested
+//               0x11 -> xip_main
+//               0x12 -> rom_contested
+//               0x13 -> rom
+#define BUSCTRL_PERFSEL2_OFFSET                   _u(0x0000001c)
+#define BUSCTRL_PERFSEL2_BITS                     _u(0x0000001f)
+#define BUSCTRL_PERFSEL2_RESET                    _u(0x0000001f)
+#define BUSCTRL_PERFSEL2_MSB                      _u(4)
+#define BUSCTRL_PERFSEL2_LSB                      _u(0)
+#define BUSCTRL_PERFSEL2_ACCESS                   "RW"
+#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED      _u(0x00)
+#define BUSCTRL_PERFSEL2_VALUE_APB                _u(0x01)
+#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED _u(0x02)
+#define BUSCTRL_PERFSEL2_VALUE_FASTPERI           _u(0x03)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED    _u(0x04)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM5              _u(0x05)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED    _u(0x06)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM4              _u(0x07)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED    _u(0x08)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM3              _u(0x09)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED    _u(0x0a)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM2              _u(0x0b)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED    _u(0x0c)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM1              _u(0x0d)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED    _u(0x0e)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM0              _u(0x0f)
+#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED _u(0x10)
+#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN           _u(0x11)
+#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED      _u(0x12)
+#define BUSCTRL_PERFSEL2_VALUE_ROM                _u(0x13)
+// =============================================================================
+// Register    : BUSCTRL_PERFCTR3
+// Description : Bus fabric performance counter 3
+//               Busfabric saturating performance counter 3
+//               Count some event signal from the busfabric arbiters.
+//               Write any value to clear. Select an event to count using
+//               PERFSEL3
+#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000020)
+#define BUSCTRL_PERFCTR3_BITS   _u(0x00ffffff)
+#define BUSCTRL_PERFCTR3_RESET  _u(0x00000000)
+#define BUSCTRL_PERFCTR3_MSB    _u(23)
+#define BUSCTRL_PERFCTR3_LSB    _u(0)
+#define BUSCTRL_PERFCTR3_ACCESS "WC"
+// =============================================================================
+// Register    : BUSCTRL_PERFSEL3
+// Description : Bus fabric performance event select for PERFCTR3
+//               Select an event for PERFCTR3. Count either contested accesses,
+//               or all accesses, on a downstream port of the main crossbar.
+//               0x00 -> apb_contested
+//               0x01 -> apb
+//               0x02 -> fastperi_contested
+//               0x03 -> fastperi
+//               0x04 -> sram5_contested
+//               0x05 -> sram5
+//               0x06 -> sram4_contested
+//               0x07 -> sram4
+//               0x08 -> sram3_contested
+//               0x09 -> sram3
+//               0x0a -> sram2_contested
+//               0x0b -> sram2
+//               0x0c -> sram1_contested
+//               0x0d -> sram1
+//               0x0e -> sram0_contested
+//               0x0f -> sram0
+//               0x10 -> xip_main_contested
+//               0x11 -> xip_main
+//               0x12 -> rom_contested
+//               0x13 -> rom
+#define BUSCTRL_PERFSEL3_OFFSET                   _u(0x00000024)
+#define BUSCTRL_PERFSEL3_BITS                     _u(0x0000001f)
+#define BUSCTRL_PERFSEL3_RESET                    _u(0x0000001f)
+#define BUSCTRL_PERFSEL3_MSB                      _u(4)
+#define BUSCTRL_PERFSEL3_LSB                      _u(0)
+#define BUSCTRL_PERFSEL3_ACCESS                   "RW"
+#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED      _u(0x00)
+#define BUSCTRL_PERFSEL3_VALUE_APB                _u(0x01)
+#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED _u(0x02)
+#define BUSCTRL_PERFSEL3_VALUE_FASTPERI           _u(0x03)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED    _u(0x04)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM5              _u(0x05)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED    _u(0x06)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM4              _u(0x07)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED    _u(0x08)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM3              _u(0x09)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED    _u(0x0a)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM2              _u(0x0b)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED    _u(0x0c)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM1              _u(0x0d)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED    _u(0x0e)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM0              _u(0x0f)
+#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED _u(0x10)
+#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN           _u(0x11)
+#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED      _u(0x12)
+#define BUSCTRL_PERFSEL3_VALUE_ROM                _u(0x13)
+// =============================================================================
+#endif // HARDWARE_REGS_BUSCTRL_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/clocks.h b/src/rp2040/hardware_regs/include/hardware/regs/clocks.h
new file mode 100644
index 0000000..c0d2eab
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/clocks.h
@@ -0,0 +1,2409 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : CLOCKS
+// Version        : 1
+// Bus type       : apb
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_CLOCKS_DEFINED
+#define HARDWARE_REGS_CLOCKS_DEFINED
+// =============================================================================
+// Register    : CLOCKS_CLK_GPOUT0_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_GPOUT0_CTRL_OFFSET _u(0x00000000)
+#define CLOCKS_CLK_GPOUT0_CTRL_BITS   _u(0x00131de0)
+#define CLOCKS_CLK_GPOUT0_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT0_CTRL_NUDGE
+// Description : An edge on this signal shifts the phase of the output by 1
+//               cycle of the input clock
+//               This can be done at any time
+#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS   _u(0x00100000)
+#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB    _u(20)
+#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB    _u(20)
+#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT0_CTRL_PHASE
+// Description : This delays the enable signal by up to 3 cycles of the input
+//               clock
+//               This must be set before the clock is enabled to have any effect
+#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS   _u(0x00030000)
+#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB    _u(17)
+#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB    _u(16)
+#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT0_CTRL_DC50
+// Description : Enables duty cycle correction for odd divisors
+#define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS   _u(0x00001000)
+#define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB    _u(12)
+#define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB    _u(12)
+#define CLOCKS_CLK_GPOUT0_CTRL_DC50_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT0_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS   _u(0x00000800)
+#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB    _u(11)
+#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB    _u(11)
+#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT0_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS   _u(0x00000400)
+#define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB    _u(10)
+#define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB    _u(10)
+#define CLOCKS_CLK_GPOUT0_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT0_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+//               0x0 -> clksrc_pll_sys
+//               0x1 -> clksrc_gpin0
+//               0x2 -> clksrc_gpin1
+//               0x3 -> clksrc_pll_usb
+//               0x4 -> rosc_clksrc
+//               0x5 -> xosc_clksrc
+//               0x6 -> clk_sys
+//               0x7 -> clk_usb
+//               0x8 -> clk_adc
+//               0x9 -> clk_rtc
+//               0xa -> clk_ref
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET                _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS                 _u(0x000001e0)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB                  _u(8)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB                  _u(5)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS               "RW"
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x1)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x2)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC    _u(0x4)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x5)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS        _u(0x6)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB        _u(0x7)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC        _u(0x8)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC        _u(0x9)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF        _u(0xa)
+// =============================================================================
+// Register    : CLOCKS_CLK_GPOUT0_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_GPOUT0_DIV_OFFSET _u(0x00000004)
+#define CLOCKS_CLK_GPOUT0_DIV_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT0_DIV_RESET  _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT0_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_GPOUT0_DIV_INT_RESET  _u(0x000001)
+#define CLOCKS_CLK_GPOUT0_DIV_INT_BITS   _u(0xffffff00)
+#define CLOCKS_CLK_GPOUT0_DIV_INT_MSB    _u(31)
+#define CLOCKS_CLK_GPOUT0_DIV_INT_LSB    _u(8)
+#define CLOCKS_CLK_GPOUT0_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT0_DIV_FRAC
+// Description : Fractional component of the divisor
+#define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET  _u(0x00)
+#define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS   _u(0x000000ff)
+#define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB    _u(7)
+#define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB    _u(0)
+#define CLOCKS_CLK_GPOUT0_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_CLK_GPOUT0_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+//               (one-hot).
+//               This slice does not have a glitchless mux (only the AUX_SRC
+//               field is present, not SRC) so this register is hardwired to
+//               0x1.
+#define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET _u(0x00000008)
+#define CLOCKS_CLK_GPOUT0_SELECTED_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT0_SELECTED_RESET  _u(0x00000001)
+#define CLOCKS_CLK_GPOUT0_SELECTED_MSB    _u(31)
+#define CLOCKS_CLK_GPOUT0_SELECTED_LSB    _u(0)
+#define CLOCKS_CLK_GPOUT0_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_CLK_GPOUT1_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_GPOUT1_CTRL_OFFSET _u(0x0000000c)
+#define CLOCKS_CLK_GPOUT1_CTRL_BITS   _u(0x00131de0)
+#define CLOCKS_CLK_GPOUT1_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT1_CTRL_NUDGE
+// Description : An edge on this signal shifts the phase of the output by 1
+//               cycle of the input clock
+//               This can be done at any time
+#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS   _u(0x00100000)
+#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB    _u(20)
+#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB    _u(20)
+#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT1_CTRL_PHASE
+// Description : This delays the enable signal by up to 3 cycles of the input
+//               clock
+//               This must be set before the clock is enabled to have any effect
+#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS   _u(0x00030000)
+#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB    _u(17)
+#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB    _u(16)
+#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT1_CTRL_DC50
+// Description : Enables duty cycle correction for odd divisors
+#define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS   _u(0x00001000)
+#define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB    _u(12)
+#define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB    _u(12)
+#define CLOCKS_CLK_GPOUT1_CTRL_DC50_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT1_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS   _u(0x00000800)
+#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB    _u(11)
+#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB    _u(11)
+#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT1_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS   _u(0x00000400)
+#define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB    _u(10)
+#define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB    _u(10)
+#define CLOCKS_CLK_GPOUT1_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT1_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+//               0x0 -> clksrc_pll_sys
+//               0x1 -> clksrc_gpin0
+//               0x2 -> clksrc_gpin1
+//               0x3 -> clksrc_pll_usb
+//               0x4 -> rosc_clksrc
+//               0x5 -> xosc_clksrc
+//               0x6 -> clk_sys
+//               0x7 -> clk_usb
+//               0x8 -> clk_adc
+//               0x9 -> clk_rtc
+//               0xa -> clk_ref
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET                _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS                 _u(0x000001e0)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB                  _u(8)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB                  _u(5)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS               "RW"
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x1)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x2)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC    _u(0x4)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x5)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS        _u(0x6)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB        _u(0x7)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC        _u(0x8)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC        _u(0x9)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF        _u(0xa)
+// =============================================================================
+// Register    : CLOCKS_CLK_GPOUT1_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_GPOUT1_DIV_OFFSET _u(0x00000010)
+#define CLOCKS_CLK_GPOUT1_DIV_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT1_DIV_RESET  _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT1_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_GPOUT1_DIV_INT_RESET  _u(0x000001)
+#define CLOCKS_CLK_GPOUT1_DIV_INT_BITS   _u(0xffffff00)
+#define CLOCKS_CLK_GPOUT1_DIV_INT_MSB    _u(31)
+#define CLOCKS_CLK_GPOUT1_DIV_INT_LSB    _u(8)
+#define CLOCKS_CLK_GPOUT1_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT1_DIV_FRAC
+// Description : Fractional component of the divisor
+#define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET  _u(0x00)
+#define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS   _u(0x000000ff)
+#define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB    _u(7)
+#define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB    _u(0)
+#define CLOCKS_CLK_GPOUT1_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_CLK_GPOUT1_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+//               (one-hot).
+//               This slice does not have a glitchless mux (only the AUX_SRC
+//               field is present, not SRC) so this register is hardwired to
+//               0x1.
+#define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET _u(0x00000014)
+#define CLOCKS_CLK_GPOUT1_SELECTED_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT1_SELECTED_RESET  _u(0x00000001)
+#define CLOCKS_CLK_GPOUT1_SELECTED_MSB    _u(31)
+#define CLOCKS_CLK_GPOUT1_SELECTED_LSB    _u(0)
+#define CLOCKS_CLK_GPOUT1_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_CLK_GPOUT2_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_GPOUT2_CTRL_OFFSET _u(0x00000018)
+#define CLOCKS_CLK_GPOUT2_CTRL_BITS   _u(0x00131de0)
+#define CLOCKS_CLK_GPOUT2_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT2_CTRL_NUDGE
+// Description : An edge on this signal shifts the phase of the output by 1
+//               cycle of the input clock
+//               This can be done at any time
+#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS   _u(0x00100000)
+#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB    _u(20)
+#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB    _u(20)
+#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT2_CTRL_PHASE
+// Description : This delays the enable signal by up to 3 cycles of the input
+//               clock
+//               This must be set before the clock is enabled to have any effect
+#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS   _u(0x00030000)
+#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB    _u(17)
+#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB    _u(16)
+#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT2_CTRL_DC50
+// Description : Enables duty cycle correction for odd divisors
+#define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS   _u(0x00001000)
+#define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB    _u(12)
+#define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB    _u(12)
+#define CLOCKS_CLK_GPOUT2_CTRL_DC50_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT2_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS   _u(0x00000800)
+#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB    _u(11)
+#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB    _u(11)
+#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT2_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS   _u(0x00000400)
+#define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB    _u(10)
+#define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB    _u(10)
+#define CLOCKS_CLK_GPOUT2_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT2_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+//               0x0 -> clksrc_pll_sys
+//               0x1 -> clksrc_gpin0
+//               0x2 -> clksrc_gpin1
+//               0x3 -> clksrc_pll_usb
+//               0x4 -> rosc_clksrc_ph
+//               0x5 -> xosc_clksrc
+//               0x6 -> clk_sys
+//               0x7 -> clk_usb
+//               0x8 -> clk_adc
+//               0x9 -> clk_rtc
+//               0xa -> clk_ref
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET                _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS                 _u(0x000001e0)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB                  _u(8)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB                  _u(5)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS               "RW"
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x1)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x2)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x5)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS        _u(0x6)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB        _u(0x7)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC        _u(0x8)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC        _u(0x9)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF        _u(0xa)
+// =============================================================================
+// Register    : CLOCKS_CLK_GPOUT2_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_GPOUT2_DIV_OFFSET _u(0x0000001c)
+#define CLOCKS_CLK_GPOUT2_DIV_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT2_DIV_RESET  _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT2_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_GPOUT2_DIV_INT_RESET  _u(0x000001)
+#define CLOCKS_CLK_GPOUT2_DIV_INT_BITS   _u(0xffffff00)
+#define CLOCKS_CLK_GPOUT2_DIV_INT_MSB    _u(31)
+#define CLOCKS_CLK_GPOUT2_DIV_INT_LSB    _u(8)
+#define CLOCKS_CLK_GPOUT2_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT2_DIV_FRAC
+// Description : Fractional component of the divisor
+#define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET  _u(0x00)
+#define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS   _u(0x000000ff)
+#define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB    _u(7)
+#define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB    _u(0)
+#define CLOCKS_CLK_GPOUT2_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_CLK_GPOUT2_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+//               (one-hot).
+//               This slice does not have a glitchless mux (only the AUX_SRC
+//               field is present, not SRC) so this register is hardwired to
+//               0x1.
+#define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET _u(0x00000020)
+#define CLOCKS_CLK_GPOUT2_SELECTED_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT2_SELECTED_RESET  _u(0x00000001)
+#define CLOCKS_CLK_GPOUT2_SELECTED_MSB    _u(31)
+#define CLOCKS_CLK_GPOUT2_SELECTED_LSB    _u(0)
+#define CLOCKS_CLK_GPOUT2_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_CLK_GPOUT3_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_GPOUT3_CTRL_OFFSET _u(0x00000024)
+#define CLOCKS_CLK_GPOUT3_CTRL_BITS   _u(0x00131de0)
+#define CLOCKS_CLK_GPOUT3_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT3_CTRL_NUDGE
+// Description : An edge on this signal shifts the phase of the output by 1
+//               cycle of the input clock
+//               This can be done at any time
+#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS   _u(0x00100000)
+#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB    _u(20)
+#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB    _u(20)
+#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT3_CTRL_PHASE
+// Description : This delays the enable signal by up to 3 cycles of the input
+//               clock
+//               This must be set before the clock is enabled to have any effect
+#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS   _u(0x00030000)
+#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB    _u(17)
+#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB    _u(16)
+#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT3_CTRL_DC50
+// Description : Enables duty cycle correction for odd divisors
+#define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS   _u(0x00001000)
+#define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB    _u(12)
+#define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB    _u(12)
+#define CLOCKS_CLK_GPOUT3_CTRL_DC50_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT3_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS   _u(0x00000800)
+#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB    _u(11)
+#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB    _u(11)
+#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT3_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET  _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS   _u(0x00000400)
+#define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB    _u(10)
+#define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB    _u(10)
+#define CLOCKS_CLK_GPOUT3_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT3_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+//               0x0 -> clksrc_pll_sys
+//               0x1 -> clksrc_gpin0
+//               0x2 -> clksrc_gpin1
+//               0x3 -> clksrc_pll_usb
+//               0x4 -> rosc_clksrc_ph
+//               0x5 -> xosc_clksrc
+//               0x6 -> clk_sys
+//               0x7 -> clk_usb
+//               0x8 -> clk_adc
+//               0x9 -> clk_rtc
+//               0xa -> clk_ref
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET                _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS                 _u(0x000001e0)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB                  _u(8)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB                  _u(5)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS               "RW"
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x1)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x2)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x5)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS        _u(0x6)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB        _u(0x7)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC        _u(0x8)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC        _u(0x9)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF        _u(0xa)
+// =============================================================================
+// Register    : CLOCKS_CLK_GPOUT3_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_GPOUT3_DIV_OFFSET _u(0x00000028)
+#define CLOCKS_CLK_GPOUT3_DIV_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT3_DIV_RESET  _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT3_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_GPOUT3_DIV_INT_RESET  _u(0x000001)
+#define CLOCKS_CLK_GPOUT3_DIV_INT_BITS   _u(0xffffff00)
+#define CLOCKS_CLK_GPOUT3_DIV_INT_MSB    _u(31)
+#define CLOCKS_CLK_GPOUT3_DIV_INT_LSB    _u(8)
+#define CLOCKS_CLK_GPOUT3_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_GPOUT3_DIV_FRAC
+// Description : Fractional component of the divisor
+#define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET  _u(0x00)
+#define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS   _u(0x000000ff)
+#define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB    _u(7)
+#define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB    _u(0)
+#define CLOCKS_CLK_GPOUT3_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_CLK_GPOUT3_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+//               (one-hot).
+//               This slice does not have a glitchless mux (only the AUX_SRC
+//               field is present, not SRC) so this register is hardwired to
+//               0x1.
+#define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET _u(0x0000002c)
+#define CLOCKS_CLK_GPOUT3_SELECTED_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT3_SELECTED_RESET  _u(0x00000001)
+#define CLOCKS_CLK_GPOUT3_SELECTED_MSB    _u(31)
+#define CLOCKS_CLK_GPOUT3_SELECTED_LSB    _u(0)
+#define CLOCKS_CLK_GPOUT3_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_CLK_REF_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_REF_CTRL_OFFSET _u(0x00000030)
+#define CLOCKS_CLK_REF_CTRL_BITS   _u(0x00000063)
+#define CLOCKS_CLK_REF_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_REF_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+//               0x0 -> clksrc_pll_usb
+//               0x1 -> clksrc_gpin0
+//               0x2 -> clksrc_gpin1
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET                _u(0x0)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS                 _u(0x00000060)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB                  _u(6)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB                  _u(5)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS               "RW"
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x1)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_REF_CTRL_SRC
+// Description : Selects the clock source glitchlessly, can be changed
+//               on-the-fly
+//               0x0 -> rosc_clksrc_ph
+//               0x1 -> clksrc_clk_ref_aux
+//               0x2 -> xosc_clksrc
+#define CLOCKS_CLK_REF_CTRL_SRC_RESET                    "-"
+#define CLOCKS_CLK_REF_CTRL_SRC_BITS                     _u(0x00000003)
+#define CLOCKS_CLK_REF_CTRL_SRC_MSB                      _u(1)
+#define CLOCKS_CLK_REF_CTRL_SRC_LSB                      _u(0)
+#define CLOCKS_CLK_REF_CTRL_SRC_ACCESS                   "RW"
+#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH     _u(0x0)
+#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX _u(0x1)
+#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC        _u(0x2)
+// =============================================================================
+// Register    : CLOCKS_CLK_REF_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_REF_DIV_OFFSET _u(0x00000034)
+#define CLOCKS_CLK_REF_DIV_BITS   _u(0x00000300)
+#define CLOCKS_CLK_REF_DIV_RESET  _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_REF_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_REF_DIV_INT_RESET  _u(0x1)
+#define CLOCKS_CLK_REF_DIV_INT_BITS   _u(0x00000300)
+#define CLOCKS_CLK_REF_DIV_INT_MSB    _u(9)
+#define CLOCKS_CLK_REF_DIV_INT_LSB    _u(8)
+#define CLOCKS_CLK_REF_DIV_INT_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_CLK_REF_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+//               (one-hot).
+//               The glitchless multiplexer does not switch instantaneously (to
+//               avoid glitches), so software should poll this register to wait
+//               for the switch to complete. This register contains one decoded
+//               bit for each of the clock sources enumerated in the CTRL SRC
+//               field. At most one of these bits will be set at any time,
+//               indicating that clock is currently present at the output of the
+//               glitchless mux. Whilst switching is in progress, this register
+//               may briefly show all-0s.
+#define CLOCKS_CLK_REF_SELECTED_OFFSET _u(0x00000038)
+#define CLOCKS_CLK_REF_SELECTED_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_REF_SELECTED_RESET  _u(0x00000001)
+#define CLOCKS_CLK_REF_SELECTED_MSB    _u(31)
+#define CLOCKS_CLK_REF_SELECTED_LSB    _u(0)
+#define CLOCKS_CLK_REF_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_CLK_SYS_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_SYS_CTRL_OFFSET _u(0x0000003c)
+#define CLOCKS_CLK_SYS_CTRL_BITS   _u(0x000000e1)
+#define CLOCKS_CLK_SYS_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_SYS_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+//               0x0 -> clksrc_pll_sys
+//               0x1 -> clksrc_pll_usb
+//               0x2 -> rosc_clksrc
+//               0x3 -> xosc_clksrc
+//               0x4 -> clksrc_gpin0
+//               0x5 -> clksrc_gpin1
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET                _u(0x0)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS                 _u(0x000000e0)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB                  _u(7)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB                  _u(5)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS               "RW"
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x1)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC    _u(0x2)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x3)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x4)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x5)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_SYS_CTRL_SRC
+// Description : Selects the clock source glitchlessly, can be changed
+//               on-the-fly
+//               0x0 -> clk_ref
+//               0x1 -> clksrc_clk_sys_aux
+#define CLOCKS_CLK_SYS_CTRL_SRC_RESET                    _u(0x0)
+#define CLOCKS_CLK_SYS_CTRL_SRC_BITS                     _u(0x00000001)
+#define CLOCKS_CLK_SYS_CTRL_SRC_MSB                      _u(0)
+#define CLOCKS_CLK_SYS_CTRL_SRC_LSB                      _u(0)
+#define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS                   "RW"
+#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF            _u(0x0)
+#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX _u(0x1)
+// =============================================================================
+// Register    : CLOCKS_CLK_SYS_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_SYS_DIV_OFFSET _u(0x00000040)
+#define CLOCKS_CLK_SYS_DIV_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_SYS_DIV_RESET  _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_SYS_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_SYS_DIV_INT_RESET  _u(0x000001)
+#define CLOCKS_CLK_SYS_DIV_INT_BITS   _u(0xffffff00)
+#define CLOCKS_CLK_SYS_DIV_INT_MSB    _u(31)
+#define CLOCKS_CLK_SYS_DIV_INT_LSB    _u(8)
+#define CLOCKS_CLK_SYS_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_SYS_DIV_FRAC
+// Description : Fractional component of the divisor
+#define CLOCKS_CLK_SYS_DIV_FRAC_RESET  _u(0x00)
+#define CLOCKS_CLK_SYS_DIV_FRAC_BITS   _u(0x000000ff)
+#define CLOCKS_CLK_SYS_DIV_FRAC_MSB    _u(7)
+#define CLOCKS_CLK_SYS_DIV_FRAC_LSB    _u(0)
+#define CLOCKS_CLK_SYS_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_CLK_SYS_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+//               (one-hot).
+//               The glitchless multiplexer does not switch instantaneously (to
+//               avoid glitches), so software should poll this register to wait
+//               for the switch to complete. This register contains one decoded
+//               bit for each of the clock sources enumerated in the CTRL SRC
+//               field. At most one of these bits will be set at any time,
+//               indicating that clock is currently present at the output of the
+//               glitchless mux. Whilst switching is in progress, this register
+//               may briefly show all-0s.
+#define CLOCKS_CLK_SYS_SELECTED_OFFSET _u(0x00000044)
+#define CLOCKS_CLK_SYS_SELECTED_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_SYS_SELECTED_RESET  _u(0x00000001)
+#define CLOCKS_CLK_SYS_SELECTED_MSB    _u(31)
+#define CLOCKS_CLK_SYS_SELECTED_LSB    _u(0)
+#define CLOCKS_CLK_SYS_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_CLK_PERI_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_PERI_CTRL_OFFSET _u(0x00000048)
+#define CLOCKS_CLK_PERI_CTRL_BITS   _u(0x00000ce0)
+#define CLOCKS_CLK_PERI_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_PERI_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET  _u(0x0)
+#define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS   _u(0x00000800)
+#define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB    _u(11)
+#define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB    _u(11)
+#define CLOCKS_CLK_PERI_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_PERI_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_PERI_CTRL_KILL_RESET  _u(0x0)
+#define CLOCKS_CLK_PERI_CTRL_KILL_BITS   _u(0x00000400)
+#define CLOCKS_CLK_PERI_CTRL_KILL_MSB    _u(10)
+#define CLOCKS_CLK_PERI_CTRL_KILL_LSB    _u(10)
+#define CLOCKS_CLK_PERI_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_PERI_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+//               0x0 -> clk_sys
+//               0x1 -> clksrc_pll_sys
+//               0x2 -> clksrc_pll_usb
+//               0x3 -> rosc_clksrc_ph
+//               0x4 -> xosc_clksrc
+//               0x5 -> clksrc_gpin0
+//               0x6 -> clksrc_gpin1
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET                _u(0x0)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS                 _u(0x000000e0)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB                  _u(7)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB                  _u(5)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS               "RW"
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS        _u(0x0)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x3)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x4)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x5)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x6)
+// =============================================================================
+// Register    : CLOCKS_CLK_PERI_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+//               (one-hot).
+//               This slice does not have a glitchless mux (only the AUX_SRC
+//               field is present, not SRC) so this register is hardwired to
+//               0x1.
+#define CLOCKS_CLK_PERI_SELECTED_OFFSET _u(0x00000050)
+#define CLOCKS_CLK_PERI_SELECTED_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_PERI_SELECTED_RESET  _u(0x00000001)
+#define CLOCKS_CLK_PERI_SELECTED_MSB    _u(31)
+#define CLOCKS_CLK_PERI_SELECTED_LSB    _u(0)
+#define CLOCKS_CLK_PERI_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_CLK_USB_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_USB_CTRL_OFFSET _u(0x00000054)
+#define CLOCKS_CLK_USB_CTRL_BITS   _u(0x00130ce0)
+#define CLOCKS_CLK_USB_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_USB_CTRL_NUDGE
+// Description : An edge on this signal shifts the phase of the output by 1
+//               cycle of the input clock
+//               This can be done at any time
+#define CLOCKS_CLK_USB_CTRL_NUDGE_RESET  _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_NUDGE_BITS   _u(0x00100000)
+#define CLOCKS_CLK_USB_CTRL_NUDGE_MSB    _u(20)
+#define CLOCKS_CLK_USB_CTRL_NUDGE_LSB    _u(20)
+#define CLOCKS_CLK_USB_CTRL_NUDGE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_USB_CTRL_PHASE
+// Description : This delays the enable signal by up to 3 cycles of the input
+//               clock
+//               This must be set before the clock is enabled to have any effect
+#define CLOCKS_CLK_USB_CTRL_PHASE_RESET  _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_PHASE_BITS   _u(0x00030000)
+#define CLOCKS_CLK_USB_CTRL_PHASE_MSB    _u(17)
+#define CLOCKS_CLK_USB_CTRL_PHASE_LSB    _u(16)
+#define CLOCKS_CLK_USB_CTRL_PHASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_USB_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_USB_CTRL_ENABLE_RESET  _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_ENABLE_BITS   _u(0x00000800)
+#define CLOCKS_CLK_USB_CTRL_ENABLE_MSB    _u(11)
+#define CLOCKS_CLK_USB_CTRL_ENABLE_LSB    _u(11)
+#define CLOCKS_CLK_USB_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_USB_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_USB_CTRL_KILL_RESET  _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_KILL_BITS   _u(0x00000400)
+#define CLOCKS_CLK_USB_CTRL_KILL_MSB    _u(10)
+#define CLOCKS_CLK_USB_CTRL_KILL_LSB    _u(10)
+#define CLOCKS_CLK_USB_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_USB_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+//               0x0 -> clksrc_pll_usb
+//               0x1 -> clksrc_pll_sys
+//               0x2 -> rosc_clksrc_ph
+//               0x3 -> xosc_clksrc
+//               0x4 -> clksrc_gpin0
+//               0x5 -> clksrc_gpin1
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET                _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS                 _u(0x000000e0)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB                  _u(7)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB                  _u(5)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS               "RW"
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x3)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x4)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x5)
+// =============================================================================
+// Register    : CLOCKS_CLK_USB_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_USB_DIV_OFFSET _u(0x00000058)
+#define CLOCKS_CLK_USB_DIV_BITS   _u(0x00000300)
+#define CLOCKS_CLK_USB_DIV_RESET  _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_USB_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_USB_DIV_INT_RESET  _u(0x1)
+#define CLOCKS_CLK_USB_DIV_INT_BITS   _u(0x00000300)
+#define CLOCKS_CLK_USB_DIV_INT_MSB    _u(9)
+#define CLOCKS_CLK_USB_DIV_INT_LSB    _u(8)
+#define CLOCKS_CLK_USB_DIV_INT_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_CLK_USB_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+//               (one-hot).
+//               This slice does not have a glitchless mux (only the AUX_SRC
+//               field is present, not SRC) so this register is hardwired to
+//               0x1.
+#define CLOCKS_CLK_USB_SELECTED_OFFSET _u(0x0000005c)
+#define CLOCKS_CLK_USB_SELECTED_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_USB_SELECTED_RESET  _u(0x00000001)
+#define CLOCKS_CLK_USB_SELECTED_MSB    _u(31)
+#define CLOCKS_CLK_USB_SELECTED_LSB    _u(0)
+#define CLOCKS_CLK_USB_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_CLK_ADC_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_ADC_CTRL_OFFSET _u(0x00000060)
+#define CLOCKS_CLK_ADC_CTRL_BITS   _u(0x00130ce0)
+#define CLOCKS_CLK_ADC_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_ADC_CTRL_NUDGE
+// Description : An edge on this signal shifts the phase of the output by 1
+//               cycle of the input clock
+//               This can be done at any time
+#define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET  _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS   _u(0x00100000)
+#define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB    _u(20)
+#define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB    _u(20)
+#define CLOCKS_CLK_ADC_CTRL_NUDGE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_ADC_CTRL_PHASE
+// Description : This delays the enable signal by up to 3 cycles of the input
+//               clock
+//               This must be set before the clock is enabled to have any effect
+#define CLOCKS_CLK_ADC_CTRL_PHASE_RESET  _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_PHASE_BITS   _u(0x00030000)
+#define CLOCKS_CLK_ADC_CTRL_PHASE_MSB    _u(17)
+#define CLOCKS_CLK_ADC_CTRL_PHASE_LSB    _u(16)
+#define CLOCKS_CLK_ADC_CTRL_PHASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_ADC_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET  _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS   _u(0x00000800)
+#define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB    _u(11)
+#define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB    _u(11)
+#define CLOCKS_CLK_ADC_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_ADC_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_ADC_CTRL_KILL_RESET  _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_KILL_BITS   _u(0x00000400)
+#define CLOCKS_CLK_ADC_CTRL_KILL_MSB    _u(10)
+#define CLOCKS_CLK_ADC_CTRL_KILL_LSB    _u(10)
+#define CLOCKS_CLK_ADC_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_ADC_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+//               0x0 -> clksrc_pll_usb
+//               0x1 -> clksrc_pll_sys
+//               0x2 -> rosc_clksrc_ph
+//               0x3 -> xosc_clksrc
+//               0x4 -> clksrc_gpin0
+//               0x5 -> clksrc_gpin1
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET                _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS                 _u(0x000000e0)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB                  _u(7)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB                  _u(5)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS               "RW"
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x3)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x4)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x5)
+// =============================================================================
+// Register    : CLOCKS_CLK_ADC_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_ADC_DIV_OFFSET _u(0x00000064)
+#define CLOCKS_CLK_ADC_DIV_BITS   _u(0x00000300)
+#define CLOCKS_CLK_ADC_DIV_RESET  _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_ADC_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_ADC_DIV_INT_RESET  _u(0x1)
+#define CLOCKS_CLK_ADC_DIV_INT_BITS   _u(0x00000300)
+#define CLOCKS_CLK_ADC_DIV_INT_MSB    _u(9)
+#define CLOCKS_CLK_ADC_DIV_INT_LSB    _u(8)
+#define CLOCKS_CLK_ADC_DIV_INT_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_CLK_ADC_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+//               (one-hot).
+//               This slice does not have a glitchless mux (only the AUX_SRC
+//               field is present, not SRC) so this register is hardwired to
+//               0x1.
+#define CLOCKS_CLK_ADC_SELECTED_OFFSET _u(0x00000068)
+#define CLOCKS_CLK_ADC_SELECTED_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_ADC_SELECTED_RESET  _u(0x00000001)
+#define CLOCKS_CLK_ADC_SELECTED_MSB    _u(31)
+#define CLOCKS_CLK_ADC_SELECTED_LSB    _u(0)
+#define CLOCKS_CLK_ADC_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_CLK_RTC_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_RTC_CTRL_OFFSET _u(0x0000006c)
+#define CLOCKS_CLK_RTC_CTRL_BITS   _u(0x00130ce0)
+#define CLOCKS_CLK_RTC_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_RTC_CTRL_NUDGE
+// Description : An edge on this signal shifts the phase of the output by 1
+//               cycle of the input clock
+//               This can be done at any time
+#define CLOCKS_CLK_RTC_CTRL_NUDGE_RESET  _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_NUDGE_BITS   _u(0x00100000)
+#define CLOCKS_CLK_RTC_CTRL_NUDGE_MSB    _u(20)
+#define CLOCKS_CLK_RTC_CTRL_NUDGE_LSB    _u(20)
+#define CLOCKS_CLK_RTC_CTRL_NUDGE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_RTC_CTRL_PHASE
+// Description : This delays the enable signal by up to 3 cycles of the input
+//               clock
+//               This must be set before the clock is enabled to have any effect
+#define CLOCKS_CLK_RTC_CTRL_PHASE_RESET  _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_PHASE_BITS   _u(0x00030000)
+#define CLOCKS_CLK_RTC_CTRL_PHASE_MSB    _u(17)
+#define CLOCKS_CLK_RTC_CTRL_PHASE_LSB    _u(16)
+#define CLOCKS_CLK_RTC_CTRL_PHASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_RTC_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_RTC_CTRL_ENABLE_RESET  _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_ENABLE_BITS   _u(0x00000800)
+#define CLOCKS_CLK_RTC_CTRL_ENABLE_MSB    _u(11)
+#define CLOCKS_CLK_RTC_CTRL_ENABLE_LSB    _u(11)
+#define CLOCKS_CLK_RTC_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_RTC_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_RTC_CTRL_KILL_RESET  _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_KILL_BITS   _u(0x00000400)
+#define CLOCKS_CLK_RTC_CTRL_KILL_MSB    _u(10)
+#define CLOCKS_CLK_RTC_CTRL_KILL_LSB    _u(10)
+#define CLOCKS_CLK_RTC_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_RTC_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+//               0x0 -> clksrc_pll_usb
+//               0x1 -> clksrc_pll_sys
+//               0x2 -> rosc_clksrc_ph
+//               0x3 -> xosc_clksrc
+//               0x4 -> clksrc_gpin0
+//               0x5 -> clksrc_gpin1
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET                _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS                 _u(0x000000e0)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB                  _u(7)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB                  _u(5)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_ACCESS               "RW"
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x3)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x4)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x5)
+// =============================================================================
+// Register    : CLOCKS_CLK_RTC_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_RTC_DIV_OFFSET _u(0x00000070)
+#define CLOCKS_CLK_RTC_DIV_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_RTC_DIV_RESET  _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_RTC_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_RTC_DIV_INT_RESET  _u(0x000001)
+#define CLOCKS_CLK_RTC_DIV_INT_BITS   _u(0xffffff00)
+#define CLOCKS_CLK_RTC_DIV_INT_MSB    _u(31)
+#define CLOCKS_CLK_RTC_DIV_INT_LSB    _u(8)
+#define CLOCKS_CLK_RTC_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_RTC_DIV_FRAC
+// Description : Fractional component of the divisor
+#define CLOCKS_CLK_RTC_DIV_FRAC_RESET  _u(0x00)
+#define CLOCKS_CLK_RTC_DIV_FRAC_BITS   _u(0x000000ff)
+#define CLOCKS_CLK_RTC_DIV_FRAC_MSB    _u(7)
+#define CLOCKS_CLK_RTC_DIV_FRAC_LSB    _u(0)
+#define CLOCKS_CLK_RTC_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_CLK_RTC_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+//               (one-hot).
+//               This slice does not have a glitchless mux (only the AUX_SRC
+//               field is present, not SRC) so this register is hardwired to
+//               0x1.
+#define CLOCKS_CLK_RTC_SELECTED_OFFSET _u(0x00000074)
+#define CLOCKS_CLK_RTC_SELECTED_BITS   _u(0xffffffff)
+#define CLOCKS_CLK_RTC_SELECTED_RESET  _u(0x00000001)
+#define CLOCKS_CLK_RTC_SELECTED_MSB    _u(31)
+#define CLOCKS_CLK_RTC_SELECTED_LSB    _u(0)
+#define CLOCKS_CLK_RTC_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_CLK_SYS_RESUS_CTRL
+// Description : None
+#define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET _u(0x00000078)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_BITS   _u(0x000111ff)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_RESET  _u(0x000000ff)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR
+// Description : For clearing the resus after the fault that triggered it has
+//               been corrected
+#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET  _u(0x0)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS   _u(0x00010000)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB    _u(16)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB    _u(16)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_SYS_RESUS_CTRL_FRCE
+// Description : Force a resus, for test purposes only
+#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET  _u(0x0)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS   _u(0x00001000)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB    _u(12)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB    _u(12)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE
+// Description : Enable resus
+#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET  _u(0x0)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS   _u(0x00000100)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB    _u(8)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB    _u(8)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT
+// Description : This is expressed as a number of clk_ref cycles
+//               and must be >= 2x clk_ref_freq/min_clk_tst_freq
+#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET  _u(0xff)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS   _u(0x000000ff)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB    _u(7)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB    _u(0)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_CLK_SYS_RESUS_STATUS
+// Description : None
+#define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET _u(0x0000007c)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_BITS   _u(0x00000001)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED
+// Description : Clock has been resuscitated, correct the error then send
+//               ctrl_clear=1
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET  _u(0x0)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS   _u(0x00000001)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB    _u(0)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB    _u(0)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_FC0_REF_KHZ
+// Description : Reference clock frequency in kHz
+#define CLOCKS_FC0_REF_KHZ_OFFSET _u(0x00000080)
+#define CLOCKS_FC0_REF_KHZ_BITS   _u(0x000fffff)
+#define CLOCKS_FC0_REF_KHZ_RESET  _u(0x00000000)
+#define CLOCKS_FC0_REF_KHZ_MSB    _u(19)
+#define CLOCKS_FC0_REF_KHZ_LSB    _u(0)
+#define CLOCKS_FC0_REF_KHZ_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_FC0_MIN_KHZ
+// Description : Minimum pass frequency in kHz. This is optional. Set to 0 if
+//               you are not using the pass/fail flags
+#define CLOCKS_FC0_MIN_KHZ_OFFSET _u(0x00000084)
+#define CLOCKS_FC0_MIN_KHZ_BITS   _u(0x01ffffff)
+#define CLOCKS_FC0_MIN_KHZ_RESET  _u(0x00000000)
+#define CLOCKS_FC0_MIN_KHZ_MSB    _u(24)
+#define CLOCKS_FC0_MIN_KHZ_LSB    _u(0)
+#define CLOCKS_FC0_MIN_KHZ_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_FC0_MAX_KHZ
+// Description : Maximum pass frequency in kHz. This is optional. Set to
+//               0x1ffffff if you are not using the pass/fail flags
+#define CLOCKS_FC0_MAX_KHZ_OFFSET _u(0x00000088)
+#define CLOCKS_FC0_MAX_KHZ_BITS   _u(0x01ffffff)
+#define CLOCKS_FC0_MAX_KHZ_RESET  _u(0x01ffffff)
+#define CLOCKS_FC0_MAX_KHZ_MSB    _u(24)
+#define CLOCKS_FC0_MAX_KHZ_LSB    _u(0)
+#define CLOCKS_FC0_MAX_KHZ_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_FC0_DELAY
+// Description : Delays the start of frequency counting to allow the mux to
+//               settle
+//               Delay is measured in multiples of the reference clock period
+#define CLOCKS_FC0_DELAY_OFFSET _u(0x0000008c)
+#define CLOCKS_FC0_DELAY_BITS   _u(0x00000007)
+#define CLOCKS_FC0_DELAY_RESET  _u(0x00000001)
+#define CLOCKS_FC0_DELAY_MSB    _u(2)
+#define CLOCKS_FC0_DELAY_LSB    _u(0)
+#define CLOCKS_FC0_DELAY_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_FC0_INTERVAL
+// Description : The test interval is 0.98us * 2**interval, but let's call it
+//               1us * 2**interval
+//               The default gives a test interval of 250us
+#define CLOCKS_FC0_INTERVAL_OFFSET _u(0x00000090)
+#define CLOCKS_FC0_INTERVAL_BITS   _u(0x0000000f)
+#define CLOCKS_FC0_INTERVAL_RESET  _u(0x00000008)
+#define CLOCKS_FC0_INTERVAL_MSB    _u(3)
+#define CLOCKS_FC0_INTERVAL_LSB    _u(0)
+#define CLOCKS_FC0_INTERVAL_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_FC0_SRC
+// Description : Clock sent to frequency counter, set to 0 when not required
+//               Writing to this register initiates the frequency count
+//               0x00 -> NULL
+//               0x01 -> pll_sys_clksrc_primary
+//               0x02 -> pll_usb_clksrc_primary
+//               0x03 -> rosc_clksrc
+//               0x04 -> rosc_clksrc_ph
+//               0x05 -> xosc_clksrc
+//               0x06 -> clksrc_gpin0
+//               0x07 -> clksrc_gpin1
+//               0x08 -> clk_ref
+//               0x09 -> clk_sys
+//               0x0a -> clk_peri
+//               0x0b -> clk_usb
+//               0x0c -> clk_adc
+//               0x0d -> clk_rtc
+#define CLOCKS_FC0_SRC_OFFSET                       _u(0x00000094)
+#define CLOCKS_FC0_SRC_BITS                         _u(0x000000ff)
+#define CLOCKS_FC0_SRC_RESET                        _u(0x00000000)
+#define CLOCKS_FC0_SRC_MSB                          _u(7)
+#define CLOCKS_FC0_SRC_LSB                          _u(0)
+#define CLOCKS_FC0_SRC_ACCESS                       "RW"
+#define CLOCKS_FC0_SRC_VALUE_NULL                   _u(0x00)
+#define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY _u(0x01)
+#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY _u(0x02)
+#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC            _u(0x03)
+#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH         _u(0x04)
+#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC            _u(0x05)
+#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0           _u(0x06)
+#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1           _u(0x07)
+#define CLOCKS_FC0_SRC_VALUE_CLK_REF                _u(0x08)
+#define CLOCKS_FC0_SRC_VALUE_CLK_SYS                _u(0x09)
+#define CLOCKS_FC0_SRC_VALUE_CLK_PERI               _u(0x0a)
+#define CLOCKS_FC0_SRC_VALUE_CLK_USB                _u(0x0b)
+#define CLOCKS_FC0_SRC_VALUE_CLK_ADC                _u(0x0c)
+#define CLOCKS_FC0_SRC_VALUE_CLK_RTC                _u(0x0d)
+// =============================================================================
+// Register    : CLOCKS_FC0_STATUS
+// Description : Frequency counter status
+#define CLOCKS_FC0_STATUS_OFFSET _u(0x00000098)
+#define CLOCKS_FC0_STATUS_BITS   _u(0x11111111)
+#define CLOCKS_FC0_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_FC0_STATUS_DIED
+// Description : Test clock stopped during test
+#define CLOCKS_FC0_STATUS_DIED_RESET  _u(0x0)
+#define CLOCKS_FC0_STATUS_DIED_BITS   _u(0x10000000)
+#define CLOCKS_FC0_STATUS_DIED_MSB    _u(28)
+#define CLOCKS_FC0_STATUS_DIED_LSB    _u(28)
+#define CLOCKS_FC0_STATUS_DIED_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_FC0_STATUS_FAST
+// Description : Test clock faster than expected, only valid when status_done=1
+#define CLOCKS_FC0_STATUS_FAST_RESET  _u(0x0)
+#define CLOCKS_FC0_STATUS_FAST_BITS   _u(0x01000000)
+#define CLOCKS_FC0_STATUS_FAST_MSB    _u(24)
+#define CLOCKS_FC0_STATUS_FAST_LSB    _u(24)
+#define CLOCKS_FC0_STATUS_FAST_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_FC0_STATUS_SLOW
+// Description : Test clock slower than expected, only valid when status_done=1
+#define CLOCKS_FC0_STATUS_SLOW_RESET  _u(0x0)
+#define CLOCKS_FC0_STATUS_SLOW_BITS   _u(0x00100000)
+#define CLOCKS_FC0_STATUS_SLOW_MSB    _u(20)
+#define CLOCKS_FC0_STATUS_SLOW_LSB    _u(20)
+#define CLOCKS_FC0_STATUS_SLOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_FC0_STATUS_FAIL
+// Description : Test failed
+#define CLOCKS_FC0_STATUS_FAIL_RESET  _u(0x0)
+#define CLOCKS_FC0_STATUS_FAIL_BITS   _u(0x00010000)
+#define CLOCKS_FC0_STATUS_FAIL_MSB    _u(16)
+#define CLOCKS_FC0_STATUS_FAIL_LSB    _u(16)
+#define CLOCKS_FC0_STATUS_FAIL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_FC0_STATUS_WAITING
+// Description : Waiting for test clock to start
+#define CLOCKS_FC0_STATUS_WAITING_RESET  _u(0x0)
+#define CLOCKS_FC0_STATUS_WAITING_BITS   _u(0x00001000)
+#define CLOCKS_FC0_STATUS_WAITING_MSB    _u(12)
+#define CLOCKS_FC0_STATUS_WAITING_LSB    _u(12)
+#define CLOCKS_FC0_STATUS_WAITING_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_FC0_STATUS_RUNNING
+// Description : Test running
+#define CLOCKS_FC0_STATUS_RUNNING_RESET  _u(0x0)
+#define CLOCKS_FC0_STATUS_RUNNING_BITS   _u(0x00000100)
+#define CLOCKS_FC0_STATUS_RUNNING_MSB    _u(8)
+#define CLOCKS_FC0_STATUS_RUNNING_LSB    _u(8)
+#define CLOCKS_FC0_STATUS_RUNNING_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_FC0_STATUS_DONE
+// Description : Test complete
+#define CLOCKS_FC0_STATUS_DONE_RESET  _u(0x0)
+#define CLOCKS_FC0_STATUS_DONE_BITS   _u(0x00000010)
+#define CLOCKS_FC0_STATUS_DONE_MSB    _u(4)
+#define CLOCKS_FC0_STATUS_DONE_LSB    _u(4)
+#define CLOCKS_FC0_STATUS_DONE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_FC0_STATUS_PASS
+// Description : Test passed
+#define CLOCKS_FC0_STATUS_PASS_RESET  _u(0x0)
+#define CLOCKS_FC0_STATUS_PASS_BITS   _u(0x00000001)
+#define CLOCKS_FC0_STATUS_PASS_MSB    _u(0)
+#define CLOCKS_FC0_STATUS_PASS_LSB    _u(0)
+#define CLOCKS_FC0_STATUS_PASS_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_FC0_RESULT
+// Description : Result of frequency measurement, only valid when status_done=1
+#define CLOCKS_FC0_RESULT_OFFSET _u(0x0000009c)
+#define CLOCKS_FC0_RESULT_BITS   _u(0x3fffffff)
+#define CLOCKS_FC0_RESULT_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_FC0_RESULT_KHZ
+// Description : None
+#define CLOCKS_FC0_RESULT_KHZ_RESET  _u(0x0000000)
+#define CLOCKS_FC0_RESULT_KHZ_BITS   _u(0x3fffffe0)
+#define CLOCKS_FC0_RESULT_KHZ_MSB    _u(29)
+#define CLOCKS_FC0_RESULT_KHZ_LSB    _u(5)
+#define CLOCKS_FC0_RESULT_KHZ_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_FC0_RESULT_FRAC
+// Description : None
+#define CLOCKS_FC0_RESULT_FRAC_RESET  _u(0x00)
+#define CLOCKS_FC0_RESULT_FRAC_BITS   _u(0x0000001f)
+#define CLOCKS_FC0_RESULT_FRAC_MSB    _u(4)
+#define CLOCKS_FC0_RESULT_FRAC_LSB    _u(0)
+#define CLOCKS_FC0_RESULT_FRAC_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_WAKE_EN0
+// Description : enable clock in wake mode
+#define CLOCKS_WAKE_EN0_OFFSET _u(0x000000a0)
+#define CLOCKS_WAKE_EN0_BITS   _u(0xffffffff)
+#define CLOCKS_WAKE_EN0_RESET  _u(0xffffffff)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_SRAM3
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS   _u(0x80000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_MSB    _u(31)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_LSB    _u(31)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_SRAM2
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS   _u(0x40000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_MSB    _u(30)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_LSB    _u(30)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_SRAM1
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS   _u(0x20000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_MSB    _u(29)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_LSB    _u(29)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_SRAM0
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS   _u(0x10000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_MSB    _u(28)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_LSB    _u(28)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_SPI1
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS   _u(0x08000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_MSB    _u(27)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_LSB    _u(27)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_PERI_SPI1
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS   _u(0x04000000)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_MSB    _u(26)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_LSB    _u(26)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_SPI0
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS   _u(0x02000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_MSB    _u(25)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_LSB    _u(25)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_PERI_SPI0
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS   _u(0x01000000)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_MSB    _u(24)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_LSB    _u(24)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_SIO
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS   _u(0x00800000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB    _u(23)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB    _u(23)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_RTC
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_BITS   _u(0x00400000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_MSB    _u(22)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_LSB    _u(22)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_RTC_RTC
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_BITS   _u(0x00200000)
+#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_MSB    _u(21)
+#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_LSB    _u(21)
+#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_ROSC
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS   _u(0x00100000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB    _u(20)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB    _u(20)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_ROM
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS   _u(0x00080000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB    _u(19)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB    _u(19)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_RESETS
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS   _u(0x00040000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB    _u(18)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB    _u(18)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_PWM
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS   _u(0x00020000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB    _u(17)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB    _u(17)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_PSM
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS   _u(0x00010000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB    _u(16)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB    _u(16)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS   _u(0x00008000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB    _u(15)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB    _u(15)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS   _u(0x00004000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB    _u(14)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB    _u(14)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_PIO1
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS   _u(0x00002000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB    _u(13)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB    _u(13)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_PIO0
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS   _u(0x00001000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB    _u(12)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB    _u(12)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_PADS
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS   _u(0x00000800)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB    _u(11)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB    _u(11)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS   _u(0x00000400)
+#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB    _u(10)
+#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB    _u(10)
+#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_JTAG
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS   _u(0x00000200)
+#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB    _u(9)
+#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB    _u(9)
+#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_IO
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS   _u(0x00000100)
+#define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB    _u(8)
+#define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB    _u(8)
+#define CLOCKS_WAKE_EN0_CLK_SYS_IO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_I2C1
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS   _u(0x00000080)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB    _u(7)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB    _u(7)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_I2C0
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS   _u(0x00000040)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB    _u(6)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB    _u(6)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_DMA
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS   _u(0x00000020)
+#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB    _u(5)
+#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB    _u(5)
+#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS   _u(0x00000010)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB    _u(4)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB    _u(4)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS   _u(0x00000008)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB    _u(3)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB    _u(3)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_ADC
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS   _u(0x00000004)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB    _u(2)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB    _u(2)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_ADC_ADC
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_BITS   _u(0x00000002)
+#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_MSB    _u(1)
+#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_LSB    _u(1)
+#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS   _u(0x00000001)
+#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB    _u(0)
+#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB    _u(0)
+#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_WAKE_EN1
+// Description : enable clock in wake mode
+#define CLOCKS_WAKE_EN1_OFFSET _u(0x000000a4)
+#define CLOCKS_WAKE_EN1_BITS   _u(0x00007fff)
+#define CLOCKS_WAKE_EN1_RESET  _u(0x00007fff)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_SYS_XOSC
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS   _u(0x00004000)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB    _u(14)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB    _u(14)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_SYS_XIP
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS   _u(0x00002000)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB    _u(13)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB    _u(13)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS   _u(0x00001000)
+#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB    _u(12)
+#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB    _u(12)
+#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_USB_USBCTRL
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_BITS   _u(0x00000800)
+#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_MSB    _u(11)
+#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_LSB    _u(11)
+#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS   _u(0x00000400)
+#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB    _u(10)
+#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB    _u(10)
+#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_SYS_UART1
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS   _u(0x00000200)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB    _u(9)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB    _u(9)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_PERI_UART1
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS   _u(0x00000100)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB    _u(8)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB    _u(8)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_SYS_UART0
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS   _u(0x00000080)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB    _u(7)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB    _u(7)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_PERI_UART0
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS   _u(0x00000040)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB    _u(6)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB    _u(6)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_SYS_TIMER
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS   _u(0x00000020)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_MSB    _u(5)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_LSB    _u(5)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_SYS_TBMAN
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS   _u(0x00000010)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB    _u(4)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB    _u(4)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS   _u(0x00000008)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB    _u(3)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB    _u(3)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS   _u(0x00000004)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB    _u(2)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB    _u(2)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_SYS_SRAM5
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS   _u(0x00000002)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB    _u(1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB    _u(1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_WAKE_EN1_CLK_SYS_SRAM4
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET  _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS   _u(0x00000001)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB    _u(0)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB    _u(0)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_SLEEP_EN0
+// Description : enable clock in sleep mode
+#define CLOCKS_SLEEP_EN0_OFFSET _u(0x000000a8)
+#define CLOCKS_SLEEP_EN0_BITS   _u(0xffffffff)
+#define CLOCKS_SLEEP_EN0_RESET  _u(0xffffffff)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_BITS   _u(0x80000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_MSB    _u(31)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_LSB    _u(31)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_BITS   _u(0x40000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_MSB    _u(30)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_LSB    _u(30)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_BITS   _u(0x20000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_MSB    _u(29)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_LSB    _u(29)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_BITS   _u(0x10000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_MSB    _u(28)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_LSB    _u(28)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_SPI1
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS   _u(0x08000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_MSB    _u(27)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_LSB    _u(27)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_PERI_SPI1
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS   _u(0x04000000)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_MSB    _u(26)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_LSB    _u(26)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_SPI0
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS   _u(0x02000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_MSB    _u(25)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_LSB    _u(25)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_PERI_SPI0
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS   _u(0x01000000)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_MSB    _u(24)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_LSB    _u(24)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_SIO
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS   _u(0x00800000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB    _u(23)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB    _u(23)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_RTC
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_BITS   _u(0x00400000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_MSB    _u(22)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_LSB    _u(22)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_RTC_RTC
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS   _u(0x00200000)
+#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_MSB    _u(21)
+#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_LSB    _u(21)
+#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_ROSC
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS   _u(0x00100000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB    _u(20)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB    _u(20)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_ROM
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS   _u(0x00080000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB    _u(19)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB    _u(19)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_RESETS
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS   _u(0x00040000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB    _u(18)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB    _u(18)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_PWM
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS   _u(0x00020000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB    _u(17)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB    _u(17)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_PSM
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS   _u(0x00010000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB    _u(16)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB    _u(16)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS   _u(0x00008000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB    _u(15)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB    _u(15)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS   _u(0x00004000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB    _u(14)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB    _u(14)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_PIO1
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS   _u(0x00002000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB    _u(13)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB    _u(13)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_PIO0
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS   _u(0x00001000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB    _u(12)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB    _u(12)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_PADS
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS   _u(0x00000800)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB    _u(11)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB    _u(11)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS   _u(0x00000400)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB    _u(10)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB    _u(10)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_JTAG
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS   _u(0x00000200)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB    _u(9)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB    _u(9)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_IO
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS   _u(0x00000100)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB    _u(8)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB    _u(8)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_I2C1
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS   _u(0x00000080)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB    _u(7)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB    _u(7)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_I2C0
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS   _u(0x00000040)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB    _u(6)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB    _u(6)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_DMA
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS   _u(0x00000020)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB    _u(5)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB    _u(5)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS   _u(0x00000010)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB    _u(4)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB    _u(4)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS   _u(0x00000008)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB    _u(3)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB    _u(3)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_ADC
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS   _u(0x00000004)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB    _u(2)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB    _u(2)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_ADC_ADC
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_BITS   _u(0x00000002)
+#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_MSB    _u(1)
+#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_LSB    _u(1)
+#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS   _u(0x00000001)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB    _u(0)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB    _u(0)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_SLEEP_EN1
+// Description : enable clock in sleep mode
+#define CLOCKS_SLEEP_EN1_OFFSET _u(0x000000ac)
+#define CLOCKS_SLEEP_EN1_BITS   _u(0x00007fff)
+#define CLOCKS_SLEEP_EN1_RESET  _u(0x00007fff)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_SYS_XOSC
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS   _u(0x00004000)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB    _u(14)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB    _u(14)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_SYS_XIP
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS   _u(0x00002000)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB    _u(13)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB    _u(13)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS   _u(0x00001000)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB    _u(12)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB    _u(12)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_BITS   _u(0x00000800)
+#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_MSB    _u(11)
+#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_LSB    _u(11)
+#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS   _u(0x00000400)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB    _u(10)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB    _u(10)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_SYS_UART1
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS   _u(0x00000200)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB    _u(9)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB    _u(9)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_PERI_UART1
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS   _u(0x00000100)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB    _u(8)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB    _u(8)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_SYS_UART0
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS   _u(0x00000080)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB    _u(7)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB    _u(7)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_PERI_UART0
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS   _u(0x00000040)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB    _u(6)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB    _u(6)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS   _u(0x00000020)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_MSB    _u(5)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_LSB    _u(5)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS   _u(0x00000010)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB    _u(4)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB    _u(4)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS   _u(0x00000008)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB    _u(3)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB    _u(3)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS   _u(0x00000004)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB    _u(2)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB    _u(2)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS   _u(0x00000002)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB    _u(1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB    _u(1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET  _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS   _u(0x00000001)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB    _u(0)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB    _u(0)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_ENABLED0
+// Description : indicates the state of the clock enable
+#define CLOCKS_ENABLED0_OFFSET _u(0x000000b0)
+#define CLOCKS_ENABLED0_BITS   _u(0xffffffff)
+#define CLOCKS_ENABLED0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_SRAM3
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_BITS   _u(0x80000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_MSB    _u(31)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_LSB    _u(31)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_SRAM2
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_BITS   _u(0x40000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_MSB    _u(30)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_LSB    _u(30)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_SRAM1
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_BITS   _u(0x20000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_MSB    _u(29)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_LSB    _u(29)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_SRAM0
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_BITS   _u(0x10000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_MSB    _u(28)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_LSB    _u(28)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_SPI1
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_SPI1_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI1_BITS   _u(0x08000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI1_MSB    _u(27)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI1_LSB    _u(27)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_PERI_SPI1
+// Description : None
+#define CLOCKS_ENABLED0_CLK_PERI_SPI1_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI1_BITS   _u(0x04000000)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI1_MSB    _u(26)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI1_LSB    _u(26)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_SPI0
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_SPI0_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI0_BITS   _u(0x02000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI0_MSB    _u(25)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI0_LSB    _u(25)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_PERI_SPI0
+// Description : None
+#define CLOCKS_ENABLED0_CLK_PERI_SPI0_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI0_BITS   _u(0x01000000)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI0_MSB    _u(24)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI0_LSB    _u(24)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_SIO
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS   _u(0x00800000)
+#define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB    _u(23)
+#define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB    _u(23)
+#define CLOCKS_ENABLED0_CLK_SYS_SIO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_RTC
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_RTC_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_RTC_BITS   _u(0x00400000)
+#define CLOCKS_ENABLED0_CLK_SYS_RTC_MSB    _u(22)
+#define CLOCKS_ENABLED0_CLK_SYS_RTC_LSB    _u(22)
+#define CLOCKS_ENABLED0_CLK_SYS_RTC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_RTC_RTC
+// Description : None
+#define CLOCKS_ENABLED0_CLK_RTC_RTC_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_RTC_RTC_BITS   _u(0x00200000)
+#define CLOCKS_ENABLED0_CLK_RTC_RTC_MSB    _u(21)
+#define CLOCKS_ENABLED0_CLK_RTC_RTC_LSB    _u(21)
+#define CLOCKS_ENABLED0_CLK_RTC_RTC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_ROSC
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS   _u(0x00100000)
+#define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB    _u(20)
+#define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB    _u(20)
+#define CLOCKS_ENABLED0_CLK_SYS_ROSC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_ROM
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS   _u(0x00080000)
+#define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB    _u(19)
+#define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB    _u(19)
+#define CLOCKS_ENABLED0_CLK_SYS_ROM_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_RESETS
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS   _u(0x00040000)
+#define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB    _u(18)
+#define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB    _u(18)
+#define CLOCKS_ENABLED0_CLK_SYS_RESETS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_PWM
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS   _u(0x00020000)
+#define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB    _u(17)
+#define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB    _u(17)
+#define CLOCKS_ENABLED0_CLK_SYS_PWM_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_PSM
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS   _u(0x00010000)
+#define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB    _u(16)
+#define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB    _u(16)
+#define CLOCKS_ENABLED0_CLK_SYS_PSM_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_PLL_USB
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS   _u(0x00008000)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB    _u(15)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB    _u(15)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_PLL_SYS
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS   _u(0x00004000)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB    _u(14)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB    _u(14)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_PIO1
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS   _u(0x00002000)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB    _u(13)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB    _u(13)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_PIO0
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS   _u(0x00001000)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB    _u(12)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB    _u(12)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_PADS
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS   _u(0x00000800)
+#define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB    _u(11)
+#define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB    _u(11)
+#define CLOCKS_ENABLED0_CLK_SYS_PADS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_BITS   _u(0x00000400)
+#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_MSB    _u(10)
+#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_LSB    _u(10)
+#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_JTAG
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS   _u(0x00000200)
+#define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB    _u(9)
+#define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB    _u(9)
+#define CLOCKS_ENABLED0_CLK_SYS_JTAG_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_IO
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_IO_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_IO_BITS   _u(0x00000100)
+#define CLOCKS_ENABLED0_CLK_SYS_IO_MSB    _u(8)
+#define CLOCKS_ENABLED0_CLK_SYS_IO_LSB    _u(8)
+#define CLOCKS_ENABLED0_CLK_SYS_IO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_I2C1
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS   _u(0x00000080)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB    _u(7)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB    _u(7)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_I2C0
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS   _u(0x00000040)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB    _u(6)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB    _u(6)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_DMA
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS   _u(0x00000020)
+#define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB    _u(5)
+#define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB    _u(5)
+#define CLOCKS_ENABLED0_CLK_SYS_DMA_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS   _u(0x00000010)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB    _u(4)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB    _u(4)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_BUSCTRL
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS   _u(0x00000008)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB    _u(3)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB    _u(3)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_ADC
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS   _u(0x00000004)
+#define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB    _u(2)
+#define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB    _u(2)
+#define CLOCKS_ENABLED0_CLK_SYS_ADC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_ADC_ADC
+// Description : None
+#define CLOCKS_ENABLED0_CLK_ADC_ADC_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_ADC_ADC_BITS   _u(0x00000002)
+#define CLOCKS_ENABLED0_CLK_ADC_ADC_MSB    _u(1)
+#define CLOCKS_ENABLED0_CLK_ADC_ADC_LSB    _u(1)
+#define CLOCKS_ENABLED0_CLK_ADC_ADC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED0_CLK_SYS_CLOCKS
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET  _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS   _u(0x00000001)
+#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB    _u(0)
+#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB    _u(0)
+#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_ENABLED1
+// Description : indicates the state of the clock enable
+#define CLOCKS_ENABLED1_OFFSET _u(0x000000b4)
+#define CLOCKS_ENABLED1_BITS   _u(0x00007fff)
+#define CLOCKS_ENABLED1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_SYS_XOSC
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS   _u(0x00004000)
+#define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB    _u(14)
+#define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB    _u(14)
+#define CLOCKS_ENABLED1_CLK_SYS_XOSC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_SYS_XIP
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS   _u(0x00002000)
+#define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB    _u(13)
+#define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB    _u(13)
+#define CLOCKS_ENABLED1_CLK_SYS_XIP_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_SYS_WATCHDOG
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS   _u(0x00001000)
+#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB    _u(12)
+#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB    _u(12)
+#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_USB_USBCTRL
+// Description : None
+#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_BITS   _u(0x00000800)
+#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_MSB    _u(11)
+#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_LSB    _u(11)
+#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_SYS_USBCTRL
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS   _u(0x00000400)
+#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB    _u(10)
+#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB    _u(10)
+#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_SYS_UART1
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS   _u(0x00000200)
+#define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB    _u(9)
+#define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB    _u(9)
+#define CLOCKS_ENABLED1_CLK_SYS_UART1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_PERI_UART1
+// Description : None
+#define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS   _u(0x00000100)
+#define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB    _u(8)
+#define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB    _u(8)
+#define CLOCKS_ENABLED1_CLK_PERI_UART1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_SYS_UART0
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS   _u(0x00000080)
+#define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB    _u(7)
+#define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB    _u(7)
+#define CLOCKS_ENABLED1_CLK_SYS_UART0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_PERI_UART0
+// Description : None
+#define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS   _u(0x00000040)
+#define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB    _u(6)
+#define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB    _u(6)
+#define CLOCKS_ENABLED1_CLK_PERI_UART0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_SYS_TIMER
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_TIMER_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_TIMER_BITS   _u(0x00000020)
+#define CLOCKS_ENABLED1_CLK_SYS_TIMER_MSB    _u(5)
+#define CLOCKS_ENABLED1_CLK_SYS_TIMER_LSB    _u(5)
+#define CLOCKS_ENABLED1_CLK_SYS_TIMER_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_SYS_TBMAN
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS   _u(0x00000010)
+#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB    _u(4)
+#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB    _u(4)
+#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_SYS_SYSINFO
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS   _u(0x00000008)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB    _u(3)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB    _u(3)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_SYS_SYSCFG
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS   _u(0x00000004)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB    _u(2)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB    _u(2)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_SYS_SRAM5
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS   _u(0x00000002)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB    _u(1)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB    _u(1)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_ENABLED1_CLK_SYS_SRAM4
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET  _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS   _u(0x00000001)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB    _u(0)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB    _u(0)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_INTR
+// Description : Raw Interrupts
+#define CLOCKS_INTR_OFFSET _u(0x000000b8)
+#define CLOCKS_INTR_BITS   _u(0x00000001)
+#define CLOCKS_INTR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_INTR_CLK_SYS_RESUS
+// Description : None
+#define CLOCKS_INTR_CLK_SYS_RESUS_RESET  _u(0x0)
+#define CLOCKS_INTR_CLK_SYS_RESUS_BITS   _u(0x00000001)
+#define CLOCKS_INTR_CLK_SYS_RESUS_MSB    _u(0)
+#define CLOCKS_INTR_CLK_SYS_RESUS_LSB    _u(0)
+#define CLOCKS_INTR_CLK_SYS_RESUS_ACCESS "RO"
+// =============================================================================
+// Register    : CLOCKS_INTE
+// Description : Interrupt Enable
+#define CLOCKS_INTE_OFFSET _u(0x000000bc)
+#define CLOCKS_INTE_BITS   _u(0x00000001)
+#define CLOCKS_INTE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_INTE_CLK_SYS_RESUS
+// Description : None
+#define CLOCKS_INTE_CLK_SYS_RESUS_RESET  _u(0x0)
+#define CLOCKS_INTE_CLK_SYS_RESUS_BITS   _u(0x00000001)
+#define CLOCKS_INTE_CLK_SYS_RESUS_MSB    _u(0)
+#define CLOCKS_INTE_CLK_SYS_RESUS_LSB    _u(0)
+#define CLOCKS_INTE_CLK_SYS_RESUS_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_INTF
+// Description : Interrupt Force
+#define CLOCKS_INTF_OFFSET _u(0x000000c0)
+#define CLOCKS_INTF_BITS   _u(0x00000001)
+#define CLOCKS_INTF_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_INTF_CLK_SYS_RESUS
+// Description : None
+#define CLOCKS_INTF_CLK_SYS_RESUS_RESET  _u(0x0)
+#define CLOCKS_INTF_CLK_SYS_RESUS_BITS   _u(0x00000001)
+#define CLOCKS_INTF_CLK_SYS_RESUS_MSB    _u(0)
+#define CLOCKS_INTF_CLK_SYS_RESUS_LSB    _u(0)
+#define CLOCKS_INTF_CLK_SYS_RESUS_ACCESS "RW"
+// =============================================================================
+// Register    : CLOCKS_INTS
+// Description : Interrupt status after masking & forcing
+#define CLOCKS_INTS_OFFSET _u(0x000000c4)
+#define CLOCKS_INTS_BITS   _u(0x00000001)
+#define CLOCKS_INTS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : CLOCKS_INTS_CLK_SYS_RESUS
+// Description : None
+#define CLOCKS_INTS_CLK_SYS_RESUS_RESET  _u(0x0)
+#define CLOCKS_INTS_CLK_SYS_RESUS_BITS   _u(0x00000001)
+#define CLOCKS_INTS_CLK_SYS_RESUS_MSB    _u(0)
+#define CLOCKS_INTS_CLK_SYS_RESUS_LSB    _u(0)
+#define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_CLOCKS_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/dma.h b/src/rp2040/hardware_regs/include/hardware/regs/dma.h
new file mode 100644
index 0000000..042c3c1
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/dma.h
@@ -0,0 +1,5313 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : DMA
+// Version        : 1
+// Bus type       : apb
+// Description    : DMA with separate read and write masters
+// =============================================================================
+#ifndef HARDWARE_REGS_DMA_DEFINED
+#define HARDWARE_REGS_DMA_DEFINED
+// =============================================================================
+// Register    : DMA_CH0_READ_ADDR
+// Description : DMA Channel 0 Read Address pointer
+//               This register updates automatically each time a read completes.
+//               The current value is the next address to be read by this
+//               channel.
+#define DMA_CH0_READ_ADDR_OFFSET _u(0x00000000)
+#define DMA_CH0_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH0_READ_ADDR_RESET  _u(0x00000000)
+#define DMA_CH0_READ_ADDR_MSB    _u(31)
+#define DMA_CH0_READ_ADDR_LSB    _u(0)
+#define DMA_CH0_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_WRITE_ADDR
+// Description : DMA Channel 0 Write Address pointer
+//               This register updates automatically each time a write
+//               completes. The current value is the next address to be written
+//               by this channel.
+#define DMA_CH0_WRITE_ADDR_OFFSET _u(0x00000004)
+#define DMA_CH0_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH0_WRITE_ADDR_RESET  _u(0x00000000)
+#define DMA_CH0_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH0_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH0_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_TRANS_COUNT
+// Description : DMA Channel 0 Transfer Count
+//               Program the number of bus transfers a channel will perform
+//               before halting. Note that, if transfers are larger than one
+//               byte in size, this is not equal to the number of bytes
+//               transferred (see CTRL_DATA_SIZE).
+//
+//               When the channel is active, reading this register shows the
+//               number of transfers remaining, updating automatically each time
+//               a write transfer completes.
+//
+//               Writing this register sets the RELOAD value for the transfer
+//               counter. Each time this channel is triggered, the RELOAD value
+//               is copied into the live transfer counter. The channel can be
+//               started multiple times, and will perform the same number of
+//               transfers each time, as programmed by most recent write.
+//
+//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+//               is used as a trigger, the written value is used immediately as
+//               the length of the new transfer sequence, as well as being
+//               written to RELOAD.
+#define DMA_CH0_TRANS_COUNT_OFFSET _u(0x00000008)
+#define DMA_CH0_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH0_TRANS_COUNT_RESET  _u(0x00000000)
+#define DMA_CH0_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH0_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH0_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_CTRL_TRIG
+// Description : DMA Channel 0 Control and Status
+#define DMA_CH0_CTRL_TRIG_OFFSET _u(0x0000000c)
+#define DMA_CH0_CTRL_TRIG_BITS   _u(0xe1ffffff)
+#define DMA_CH0_CTRL_TRIG_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+//               halts when it encounters any bus error, and always raises its
+//               channel IRQ flag.
+#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET  _u(0x0)
+#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS   _u(0x80000000)
+#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB    _u(31)
+#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB    _u(31)
+#define DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+//               clear.
+//               READ_ADDR shows the approximate address where the bus error was
+//               encountered (will not to be earlier, or more than 3 transfers
+//               later)
+#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET  _u(0x0)
+#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS   _u(0x40000000)
+#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB    _u(30)
+#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB    _u(30)
+#define DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+//               clear.
+//               WRITE_ADDR shows the approximate address where the bus error
+//               was encountered (will not to be earlier, or more than 5
+//               transfers later)
+#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET  _u(0x0)
+#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS   _u(0x20000000)
+#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB    _u(29)
+#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB    _u(29)
+#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+//               sequence, and low when the last transfer of that sequence
+//               completes. Clearing EN while BUSY is high pauses the channel,
+//               and BUSY will stay high while paused.
+//
+//               To terminate a sequence early (and clear the BUSY flag), see
+//               CHAN_ABORT.
+#define DMA_CH0_CTRL_TRIG_BUSY_RESET  _u(0x0)
+#define DMA_CH0_CTRL_TRIG_BUSY_BITS   _u(0x01000000)
+#define DMA_CH0_CTRL_TRIG_BUSY_MSB    _u(24)
+#define DMA_CH0_CTRL_TRIG_BUSY_LSB    _u(24)
+#define DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+//               hardware, and each transfer will advance the state of the
+//               checksum. This only applies if the sniff hardware is enabled,
+//               and has this channel selected.
+//
+//               This allows checksum to be enabled or disabled on a
+//               per-control- block basis.
+#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET  _u(0x0)
+#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS   _u(0x00800000)
+#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB    _u(23)
+#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB    _u(23)
+#define DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+//               For byte data, this has no effect. For halfword data, the two
+//               bytes of each halfword are swapped. For word data, the four
+//               bytes of each word are swapped to reverse order.
+#define DMA_CH0_CTRL_TRIG_BSWAP_RESET  _u(0x0)
+#define DMA_CH0_CTRL_TRIG_BSWAP_BITS   _u(0x00400000)
+#define DMA_CH0_CTRL_TRIG_BSWAP_MSB    _u(22)
+#define DMA_CH0_CTRL_TRIG_BSWAP_LSB    _u(22)
+#define DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+//               every transfer block. Instead, an IRQ is raised when NULL is
+//               written to a trigger register, indicating the end of a control
+//               block chain.
+//
+//               This reduces the number of interrupts to be serviced by the CPU
+//               when transferring a DMA chain of many small control blocks.
+#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET  _u(0x0)
+#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS   _u(0x00200000)
+#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB    _u(21)
+#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB    _u(21)
+#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+//               The channel uses the transfer request signal to pace its data
+//               transfer rate. Sources for TREQ signals are internal (TIMERS)
+//               or external (DREQ, a Data Request from the system).
+//               0x0 to 0x3a -> select DREQ n as TREQ
+//               0x3b -> Select Timer 0 as TREQ
+//               0x3c -> Select Timer 1 as TREQ
+//               0x3d -> Select Timer 2 as TREQ (Optional)
+//               0x3e -> Select Timer 3 as TREQ (Optional)
+//               0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET           _u(0x00)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS            _u(0x001f8000)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB             _u(20)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB             _u(15)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS          "RW"
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    _u(0x3b)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    _u(0x3c)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    _u(0x3d)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    _u(0x3e)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+//               channel)_.
+//               Reset value is equal to channel number (0).
+#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET  _u(0x0)
+#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
+#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
+#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
+#define DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
+//               boundary. If 1, write addresses are wrapped.
+#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET  _u(0x0)
+#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS   _u(0x00000400)
+#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB    _u(10)
+#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB    _u(10)
+#define DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+//               0, only the lower n bits of the address will change. This wraps
+//               the address on a (1 << n) byte boundary, facilitating access to
+//               naturally-aligned ring buffers.
+//
+//               Ring sizes between 2 and 32768 bytes are possible. This can
+//               apply to either read or write addresses, based on value of
+//               RING_SEL.
+//               0x0 -> RING_NONE
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET           _u(0x0)
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS            _u(0x000003c0)
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB             _u(9)
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB             _u(6)
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS          "RW"
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+//               each write is directed to the same, initial address.
+//
+//               Generally this should be disabled for memory-to-peripheral
+//               transfers.
+#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET  _u(0x0)
+#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS   _u(0x00000020)
+#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB    _u(5)
+#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB    _u(5)
+#define DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+//               each read is directed to the same, initial address.
+//
+//               Generally this should be disabled for peripheral-to-memory
+//               transfers.
+#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET  _u(0x0)
+#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS   _u(0x00000010)
+#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB    _u(4)
+#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB    _u(4)
+#define DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+//               with each transfer.
+//               0x0 -> SIZE_BYTE
+//               0x1 -> SIZE_HALFWORD
+//               0x2 -> SIZE_WORD
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET               _u(0x0)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS                _u(0x0000000c)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB                 _u(3)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB                 _u(2)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS              "RW"
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     _u(0x0)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+//               scheduling: in each scheduling round, all high priority
+//               channels are considered first, and then only a single low
+//               priority channel, before returning to the high priority
+//               channels.
+//
+//               This only affects the order in which the DMA schedules
+//               channels. The DMA's bus priority is not changed. If the DMA is
+//               not saturated then a low priority channel will see no loss of
+//               throughput.
+#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET  _u(0x0)
+#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS   _u(0x00000002)
+#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB    _u(1)
+#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB    _u(1)
+#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH0_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+//               When 1, the channel will respond to triggering events, which
+//               will cause it to become BUSY and start transferring data. When
+//               0, the channel will ignore triggers, stop issuing transfers,
+//               and pause the current transfer sequence (i.e. BUSY will remain
+//               high if already high)
+#define DMA_CH0_CTRL_TRIG_EN_RESET  _u(0x0)
+#define DMA_CH0_CTRL_TRIG_EN_BITS   _u(0x00000001)
+#define DMA_CH0_CTRL_TRIG_EN_MSB    _u(0)
+#define DMA_CH0_CTRL_TRIG_EN_LSB    _u(0)
+#define DMA_CH0_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_AL1_CTRL
+// Description : Alias for channel 0 CTRL register
+#define DMA_CH0_AL1_CTRL_OFFSET _u(0x00000010)
+#define DMA_CH0_AL1_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH0_AL1_CTRL_RESET  "-"
+#define DMA_CH0_AL1_CTRL_MSB    _u(31)
+#define DMA_CH0_AL1_CTRL_LSB    _u(0)
+#define DMA_CH0_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_AL1_READ_ADDR
+// Description : Alias for channel 0 READ_ADDR register
+#define DMA_CH0_AL1_READ_ADDR_OFFSET _u(0x00000014)
+#define DMA_CH0_AL1_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH0_AL1_READ_ADDR_RESET  "-"
+#define DMA_CH0_AL1_READ_ADDR_MSB    _u(31)
+#define DMA_CH0_AL1_READ_ADDR_LSB    _u(0)
+#define DMA_CH0_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_AL1_WRITE_ADDR
+// Description : Alias for channel 0 WRITE_ADDR register
+#define DMA_CH0_AL1_WRITE_ADDR_OFFSET _u(0x00000018)
+#define DMA_CH0_AL1_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH0_AL1_WRITE_ADDR_RESET  "-"
+#define DMA_CH0_AL1_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH0_AL1_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 0 TRANS_COUNT register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000001c)
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET  "-"
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_AL2_CTRL
+// Description : Alias for channel 0 CTRL register
+#define DMA_CH0_AL2_CTRL_OFFSET _u(0x00000020)
+#define DMA_CH0_AL2_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH0_AL2_CTRL_RESET  "-"
+#define DMA_CH0_AL2_CTRL_MSB    _u(31)
+#define DMA_CH0_AL2_CTRL_LSB    _u(0)
+#define DMA_CH0_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_AL2_TRANS_COUNT
+// Description : Alias for channel 0 TRANS_COUNT register
+#define DMA_CH0_AL2_TRANS_COUNT_OFFSET _u(0x00000024)
+#define DMA_CH0_AL2_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH0_AL2_TRANS_COUNT_RESET  "-"
+#define DMA_CH0_AL2_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH0_AL2_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_AL2_READ_ADDR
+// Description : Alias for channel 0 READ_ADDR register
+#define DMA_CH0_AL2_READ_ADDR_OFFSET _u(0x00000028)
+#define DMA_CH0_AL2_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH0_AL2_READ_ADDR_RESET  "-"
+#define DMA_CH0_AL2_READ_ADDR_MSB    _u(31)
+#define DMA_CH0_AL2_READ_ADDR_LSB    _u(0)
+#define DMA_CH0_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 0 WRITE_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000002c)
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET  "-"
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_AL3_CTRL
+// Description : Alias for channel 0 CTRL register
+#define DMA_CH0_AL3_CTRL_OFFSET _u(0x00000030)
+#define DMA_CH0_AL3_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH0_AL3_CTRL_RESET  "-"
+#define DMA_CH0_AL3_CTRL_MSB    _u(31)
+#define DMA_CH0_AL3_CTRL_LSB    _u(0)
+#define DMA_CH0_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_AL3_WRITE_ADDR
+// Description : Alias for channel 0 WRITE_ADDR register
+#define DMA_CH0_AL3_WRITE_ADDR_OFFSET _u(0x00000034)
+#define DMA_CH0_AL3_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH0_AL3_WRITE_ADDR_RESET  "-"
+#define DMA_CH0_AL3_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH0_AL3_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_AL3_TRANS_COUNT
+// Description : Alias for channel 0 TRANS_COUNT register
+#define DMA_CH0_AL3_TRANS_COUNT_OFFSET _u(0x00000038)
+#define DMA_CH0_AL3_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH0_AL3_TRANS_COUNT_RESET  "-"
+#define DMA_CH0_AL3_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH0_AL3_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH0_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 0 READ_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000003c)
+#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH0_AL3_READ_ADDR_TRIG_RESET  "-"
+#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_READ_ADDR
+// Description : DMA Channel 1 Read Address pointer
+//               This register updates automatically each time a read completes.
+//               The current value is the next address to be read by this
+//               channel.
+#define DMA_CH1_READ_ADDR_OFFSET _u(0x00000040)
+#define DMA_CH1_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH1_READ_ADDR_RESET  _u(0x00000000)
+#define DMA_CH1_READ_ADDR_MSB    _u(31)
+#define DMA_CH1_READ_ADDR_LSB    _u(0)
+#define DMA_CH1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_WRITE_ADDR
+// Description : DMA Channel 1 Write Address pointer
+//               This register updates automatically each time a write
+//               completes. The current value is the next address to be written
+//               by this channel.
+#define DMA_CH1_WRITE_ADDR_OFFSET _u(0x00000044)
+#define DMA_CH1_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH1_WRITE_ADDR_RESET  _u(0x00000000)
+#define DMA_CH1_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH1_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_TRANS_COUNT
+// Description : DMA Channel 1 Transfer Count
+//               Program the number of bus transfers a channel will perform
+//               before halting. Note that, if transfers are larger than one
+//               byte in size, this is not equal to the number of bytes
+//               transferred (see CTRL_DATA_SIZE).
+//
+//               When the channel is active, reading this register shows the
+//               number of transfers remaining, updating automatically each time
+//               a write transfer completes.
+//
+//               Writing this register sets the RELOAD value for the transfer
+//               counter. Each time this channel is triggered, the RELOAD value
+//               is copied into the live transfer counter. The channel can be
+//               started multiple times, and will perform the same number of
+//               transfers each time, as programmed by most recent write.
+//
+//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+//               is used as a trigger, the written value is used immediately as
+//               the length of the new transfer sequence, as well as being
+//               written to RELOAD.
+#define DMA_CH1_TRANS_COUNT_OFFSET _u(0x00000048)
+#define DMA_CH1_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH1_TRANS_COUNT_RESET  _u(0x00000000)
+#define DMA_CH1_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH1_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH1_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_CTRL_TRIG
+// Description : DMA Channel 1 Control and Status
+#define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c)
+#define DMA_CH1_CTRL_TRIG_BITS   _u(0xe1ffffff)
+#define DMA_CH1_CTRL_TRIG_RESET  _u(0x00000800)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+//               halts when it encounters any bus error, and always raises its
+//               channel IRQ flag.
+#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET  _u(0x0)
+#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS   _u(0x80000000)
+#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB    _u(31)
+#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB    _u(31)
+#define DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+//               clear.
+//               READ_ADDR shows the approximate address where the bus error was
+//               encountered (will not to be earlier, or more than 3 transfers
+//               later)
+#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET  _u(0x0)
+#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS   _u(0x40000000)
+#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB    _u(30)
+#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB    _u(30)
+#define DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+//               clear.
+//               WRITE_ADDR shows the approximate address where the bus error
+//               was encountered (will not to be earlier, or more than 5
+//               transfers later)
+#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET  _u(0x0)
+#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS   _u(0x20000000)
+#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB    _u(29)
+#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB    _u(29)
+#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+//               sequence, and low when the last transfer of that sequence
+//               completes. Clearing EN while BUSY is high pauses the channel,
+//               and BUSY will stay high while paused.
+//
+//               To terminate a sequence early (and clear the BUSY flag), see
+//               CHAN_ABORT.
+#define DMA_CH1_CTRL_TRIG_BUSY_RESET  _u(0x0)
+#define DMA_CH1_CTRL_TRIG_BUSY_BITS   _u(0x01000000)
+#define DMA_CH1_CTRL_TRIG_BUSY_MSB    _u(24)
+#define DMA_CH1_CTRL_TRIG_BUSY_LSB    _u(24)
+#define DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+//               hardware, and each transfer will advance the state of the
+//               checksum. This only applies if the sniff hardware is enabled,
+//               and has this channel selected.
+//
+//               This allows checksum to be enabled or disabled on a
+//               per-control- block basis.
+#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET  _u(0x0)
+#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS   _u(0x00800000)
+#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB    _u(23)
+#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB    _u(23)
+#define DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+//               For byte data, this has no effect. For halfword data, the two
+//               bytes of each halfword are swapped. For word data, the four
+//               bytes of each word are swapped to reverse order.
+#define DMA_CH1_CTRL_TRIG_BSWAP_RESET  _u(0x0)
+#define DMA_CH1_CTRL_TRIG_BSWAP_BITS   _u(0x00400000)
+#define DMA_CH1_CTRL_TRIG_BSWAP_MSB    _u(22)
+#define DMA_CH1_CTRL_TRIG_BSWAP_LSB    _u(22)
+#define DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+//               every transfer block. Instead, an IRQ is raised when NULL is
+//               written to a trigger register, indicating the end of a control
+//               block chain.
+//
+//               This reduces the number of interrupts to be serviced by the CPU
+//               when transferring a DMA chain of many small control blocks.
+#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET  _u(0x0)
+#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS   _u(0x00200000)
+#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB    _u(21)
+#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB    _u(21)
+#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+//               The channel uses the transfer request signal to pace its data
+//               transfer rate. Sources for TREQ signals are internal (TIMERS)
+//               or external (DREQ, a Data Request from the system).
+//               0x0 to 0x3a -> select DREQ n as TREQ
+//               0x3b -> Select Timer 0 as TREQ
+//               0x3c -> Select Timer 1 as TREQ
+//               0x3d -> Select Timer 2 as TREQ (Optional)
+//               0x3e -> Select Timer 3 as TREQ (Optional)
+//               0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET           _u(0x00)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS            _u(0x001f8000)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB             _u(20)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB             _u(15)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS          "RW"
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    _u(0x3b)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    _u(0x3c)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    _u(0x3d)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    _u(0x3e)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+//               channel)_.
+//               Reset value is equal to channel number (1).
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET  _u(0x1)
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
+//               boundary. If 1, write addresses are wrapped.
+#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET  _u(0x0)
+#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS   _u(0x00000400)
+#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB    _u(10)
+#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB    _u(10)
+#define DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+//               0, only the lower n bits of the address will change. This wraps
+//               the address on a (1 << n) byte boundary, facilitating access to
+//               naturally-aligned ring buffers.
+//
+//               Ring sizes between 2 and 32768 bytes are possible. This can
+//               apply to either read or write addresses, based on value of
+//               RING_SEL.
+//               0x0 -> RING_NONE
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET           _u(0x0)
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS            _u(0x000003c0)
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB             _u(9)
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB             _u(6)
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS          "RW"
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+//               each write is directed to the same, initial address.
+//
+//               Generally this should be disabled for memory-to-peripheral
+//               transfers.
+#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET  _u(0x0)
+#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS   _u(0x00000020)
+#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB    _u(5)
+#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB    _u(5)
+#define DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+//               each read is directed to the same, initial address.
+//
+//               Generally this should be disabled for peripheral-to-memory
+//               transfers.
+#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET  _u(0x0)
+#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS   _u(0x00000010)
+#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB    _u(4)
+#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB    _u(4)
+#define DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+//               with each transfer.
+//               0x0 -> SIZE_BYTE
+//               0x1 -> SIZE_HALFWORD
+//               0x2 -> SIZE_WORD
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET               _u(0x0)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS                _u(0x0000000c)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB                 _u(3)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB                 _u(2)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS              "RW"
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     _u(0x0)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+//               scheduling: in each scheduling round, all high priority
+//               channels are considered first, and then only a single low
+//               priority channel, before returning to the high priority
+//               channels.
+//
+//               This only affects the order in which the DMA schedules
+//               channels. The DMA's bus priority is not changed. If the DMA is
+//               not saturated then a low priority channel will see no loss of
+//               throughput.
+#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET  _u(0x0)
+#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS   _u(0x00000002)
+#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB    _u(1)
+#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB    _u(1)
+#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH1_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+//               When 1, the channel will respond to triggering events, which
+//               will cause it to become BUSY and start transferring data. When
+//               0, the channel will ignore triggers, stop issuing transfers,
+//               and pause the current transfer sequence (i.e. BUSY will remain
+//               high if already high)
+#define DMA_CH1_CTRL_TRIG_EN_RESET  _u(0x0)
+#define DMA_CH1_CTRL_TRIG_EN_BITS   _u(0x00000001)
+#define DMA_CH1_CTRL_TRIG_EN_MSB    _u(0)
+#define DMA_CH1_CTRL_TRIG_EN_LSB    _u(0)
+#define DMA_CH1_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_AL1_CTRL
+// Description : Alias for channel 1 CTRL register
+#define DMA_CH1_AL1_CTRL_OFFSET _u(0x00000050)
+#define DMA_CH1_AL1_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH1_AL1_CTRL_RESET  "-"
+#define DMA_CH1_AL1_CTRL_MSB    _u(31)
+#define DMA_CH1_AL1_CTRL_LSB    _u(0)
+#define DMA_CH1_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_AL1_READ_ADDR
+// Description : Alias for channel 1 READ_ADDR register
+#define DMA_CH1_AL1_READ_ADDR_OFFSET _u(0x00000054)
+#define DMA_CH1_AL1_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH1_AL1_READ_ADDR_RESET  "-"
+#define DMA_CH1_AL1_READ_ADDR_MSB    _u(31)
+#define DMA_CH1_AL1_READ_ADDR_LSB    _u(0)
+#define DMA_CH1_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_AL1_WRITE_ADDR
+// Description : Alias for channel 1 WRITE_ADDR register
+#define DMA_CH1_AL1_WRITE_ADDR_OFFSET _u(0x00000058)
+#define DMA_CH1_AL1_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH1_AL1_WRITE_ADDR_RESET  "-"
+#define DMA_CH1_AL1_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH1_AL1_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 1 TRANS_COUNT register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000005c)
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET  "-"
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_AL2_CTRL
+// Description : Alias for channel 1 CTRL register
+#define DMA_CH1_AL2_CTRL_OFFSET _u(0x00000060)
+#define DMA_CH1_AL2_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH1_AL2_CTRL_RESET  "-"
+#define DMA_CH1_AL2_CTRL_MSB    _u(31)
+#define DMA_CH1_AL2_CTRL_LSB    _u(0)
+#define DMA_CH1_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_AL2_TRANS_COUNT
+// Description : Alias for channel 1 TRANS_COUNT register
+#define DMA_CH1_AL2_TRANS_COUNT_OFFSET _u(0x00000064)
+#define DMA_CH1_AL2_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH1_AL2_TRANS_COUNT_RESET  "-"
+#define DMA_CH1_AL2_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH1_AL2_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_AL2_READ_ADDR
+// Description : Alias for channel 1 READ_ADDR register
+#define DMA_CH1_AL2_READ_ADDR_OFFSET _u(0x00000068)
+#define DMA_CH1_AL2_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH1_AL2_READ_ADDR_RESET  "-"
+#define DMA_CH1_AL2_READ_ADDR_MSB    _u(31)
+#define DMA_CH1_AL2_READ_ADDR_LSB    _u(0)
+#define DMA_CH1_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 1 WRITE_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000006c)
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET  "-"
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_AL3_CTRL
+// Description : Alias for channel 1 CTRL register
+#define DMA_CH1_AL3_CTRL_OFFSET _u(0x00000070)
+#define DMA_CH1_AL3_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH1_AL3_CTRL_RESET  "-"
+#define DMA_CH1_AL3_CTRL_MSB    _u(31)
+#define DMA_CH1_AL3_CTRL_LSB    _u(0)
+#define DMA_CH1_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_AL3_WRITE_ADDR
+// Description : Alias for channel 1 WRITE_ADDR register
+#define DMA_CH1_AL3_WRITE_ADDR_OFFSET _u(0x00000074)
+#define DMA_CH1_AL3_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH1_AL3_WRITE_ADDR_RESET  "-"
+#define DMA_CH1_AL3_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH1_AL3_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_AL3_TRANS_COUNT
+// Description : Alias for channel 1 TRANS_COUNT register
+#define DMA_CH1_AL3_TRANS_COUNT_OFFSET _u(0x00000078)
+#define DMA_CH1_AL3_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH1_AL3_TRANS_COUNT_RESET  "-"
+#define DMA_CH1_AL3_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH1_AL3_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH1_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 1 READ_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000007c)
+#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH1_AL3_READ_ADDR_TRIG_RESET  "-"
+#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_READ_ADDR
+// Description : DMA Channel 2 Read Address pointer
+//               This register updates automatically each time a read completes.
+//               The current value is the next address to be read by this
+//               channel.
+#define DMA_CH2_READ_ADDR_OFFSET _u(0x00000080)
+#define DMA_CH2_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH2_READ_ADDR_RESET  _u(0x00000000)
+#define DMA_CH2_READ_ADDR_MSB    _u(31)
+#define DMA_CH2_READ_ADDR_LSB    _u(0)
+#define DMA_CH2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_WRITE_ADDR
+// Description : DMA Channel 2 Write Address pointer
+//               This register updates automatically each time a write
+//               completes. The current value is the next address to be written
+//               by this channel.
+#define DMA_CH2_WRITE_ADDR_OFFSET _u(0x00000084)
+#define DMA_CH2_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH2_WRITE_ADDR_RESET  _u(0x00000000)
+#define DMA_CH2_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH2_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH2_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_TRANS_COUNT
+// Description : DMA Channel 2 Transfer Count
+//               Program the number of bus transfers a channel will perform
+//               before halting. Note that, if transfers are larger than one
+//               byte in size, this is not equal to the number of bytes
+//               transferred (see CTRL_DATA_SIZE).
+//
+//               When the channel is active, reading this register shows the
+//               number of transfers remaining, updating automatically each time
+//               a write transfer completes.
+//
+//               Writing this register sets the RELOAD value for the transfer
+//               counter. Each time this channel is triggered, the RELOAD value
+//               is copied into the live transfer counter. The channel can be
+//               started multiple times, and will perform the same number of
+//               transfers each time, as programmed by most recent write.
+//
+//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+//               is used as a trigger, the written value is used immediately as
+//               the length of the new transfer sequence, as well as being
+//               written to RELOAD.
+#define DMA_CH2_TRANS_COUNT_OFFSET _u(0x00000088)
+#define DMA_CH2_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH2_TRANS_COUNT_RESET  _u(0x00000000)
+#define DMA_CH2_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH2_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_CTRL_TRIG
+// Description : DMA Channel 2 Control and Status
+#define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c)
+#define DMA_CH2_CTRL_TRIG_BITS   _u(0xe1ffffff)
+#define DMA_CH2_CTRL_TRIG_RESET  _u(0x00001000)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+//               halts when it encounters any bus error, and always raises its
+//               channel IRQ flag.
+#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET  _u(0x0)
+#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS   _u(0x80000000)
+#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB    _u(31)
+#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB    _u(31)
+#define DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+//               clear.
+//               READ_ADDR shows the approximate address where the bus error was
+//               encountered (will not to be earlier, or more than 3 transfers
+//               later)
+#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET  _u(0x0)
+#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS   _u(0x40000000)
+#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB    _u(30)
+#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB    _u(30)
+#define DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+//               clear.
+//               WRITE_ADDR shows the approximate address where the bus error
+//               was encountered (will not to be earlier, or more than 5
+//               transfers later)
+#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET  _u(0x0)
+#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS   _u(0x20000000)
+#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB    _u(29)
+#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB    _u(29)
+#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+//               sequence, and low when the last transfer of that sequence
+//               completes. Clearing EN while BUSY is high pauses the channel,
+//               and BUSY will stay high while paused.
+//
+//               To terminate a sequence early (and clear the BUSY flag), see
+//               CHAN_ABORT.
+#define DMA_CH2_CTRL_TRIG_BUSY_RESET  _u(0x0)
+#define DMA_CH2_CTRL_TRIG_BUSY_BITS   _u(0x01000000)
+#define DMA_CH2_CTRL_TRIG_BUSY_MSB    _u(24)
+#define DMA_CH2_CTRL_TRIG_BUSY_LSB    _u(24)
+#define DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+//               hardware, and each transfer will advance the state of the
+//               checksum. This only applies if the sniff hardware is enabled,
+//               and has this channel selected.
+//
+//               This allows checksum to be enabled or disabled on a
+//               per-control- block basis.
+#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET  _u(0x0)
+#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS   _u(0x00800000)
+#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB    _u(23)
+#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB    _u(23)
+#define DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+//               For byte data, this has no effect. For halfword data, the two
+//               bytes of each halfword are swapped. For word data, the four
+//               bytes of each word are swapped to reverse order.
+#define DMA_CH2_CTRL_TRIG_BSWAP_RESET  _u(0x0)
+#define DMA_CH2_CTRL_TRIG_BSWAP_BITS   _u(0x00400000)
+#define DMA_CH2_CTRL_TRIG_BSWAP_MSB    _u(22)
+#define DMA_CH2_CTRL_TRIG_BSWAP_LSB    _u(22)
+#define DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+//               every transfer block. Instead, an IRQ is raised when NULL is
+//               written to a trigger register, indicating the end of a control
+//               block chain.
+//
+//               This reduces the number of interrupts to be serviced by the CPU
+//               when transferring a DMA chain of many small control blocks.
+#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET  _u(0x0)
+#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS   _u(0x00200000)
+#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB    _u(21)
+#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB    _u(21)
+#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+//               The channel uses the transfer request signal to pace its data
+//               transfer rate. Sources for TREQ signals are internal (TIMERS)
+//               or external (DREQ, a Data Request from the system).
+//               0x0 to 0x3a -> select DREQ n as TREQ
+//               0x3b -> Select Timer 0 as TREQ
+//               0x3c -> Select Timer 1 as TREQ
+//               0x3d -> Select Timer 2 as TREQ (Optional)
+//               0x3e -> Select Timer 3 as TREQ (Optional)
+//               0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET           _u(0x00)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS            _u(0x001f8000)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB             _u(20)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB             _u(15)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS          "RW"
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    _u(0x3b)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    _u(0x3c)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    _u(0x3d)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    _u(0x3e)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+//               channel)_.
+//               Reset value is equal to channel number (2).
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET  _u(0x2)
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
+//               boundary. If 1, write addresses are wrapped.
+#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET  _u(0x0)
+#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS   _u(0x00000400)
+#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB    _u(10)
+#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB    _u(10)
+#define DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+//               0, only the lower n bits of the address will change. This wraps
+//               the address on a (1 << n) byte boundary, facilitating access to
+//               naturally-aligned ring buffers.
+//
+//               Ring sizes between 2 and 32768 bytes are possible. This can
+//               apply to either read or write addresses, based on value of
+//               RING_SEL.
+//               0x0 -> RING_NONE
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET           _u(0x0)
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS            _u(0x000003c0)
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB             _u(9)
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB             _u(6)
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS          "RW"
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+//               each write is directed to the same, initial address.
+//
+//               Generally this should be disabled for memory-to-peripheral
+//               transfers.
+#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET  _u(0x0)
+#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS   _u(0x00000020)
+#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB    _u(5)
+#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB    _u(5)
+#define DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+//               each read is directed to the same, initial address.
+//
+//               Generally this should be disabled for peripheral-to-memory
+//               transfers.
+#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET  _u(0x0)
+#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS   _u(0x00000010)
+#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB    _u(4)
+#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB    _u(4)
+#define DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+//               with each transfer.
+//               0x0 -> SIZE_BYTE
+//               0x1 -> SIZE_HALFWORD
+//               0x2 -> SIZE_WORD
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET               _u(0x0)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS                _u(0x0000000c)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB                 _u(3)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB                 _u(2)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS              "RW"
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     _u(0x0)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+//               scheduling: in each scheduling round, all high priority
+//               channels are considered first, and then only a single low
+//               priority channel, before returning to the high priority
+//               channels.
+//
+//               This only affects the order in which the DMA schedules
+//               channels. The DMA's bus priority is not changed. If the DMA is
+//               not saturated then a low priority channel will see no loss of
+//               throughput.
+#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET  _u(0x0)
+#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS   _u(0x00000002)
+#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB    _u(1)
+#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB    _u(1)
+#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH2_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+//               When 1, the channel will respond to triggering events, which
+//               will cause it to become BUSY and start transferring data. When
+//               0, the channel will ignore triggers, stop issuing transfers,
+//               and pause the current transfer sequence (i.e. BUSY will remain
+//               high if already high)
+#define DMA_CH2_CTRL_TRIG_EN_RESET  _u(0x0)
+#define DMA_CH2_CTRL_TRIG_EN_BITS   _u(0x00000001)
+#define DMA_CH2_CTRL_TRIG_EN_MSB    _u(0)
+#define DMA_CH2_CTRL_TRIG_EN_LSB    _u(0)
+#define DMA_CH2_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_AL1_CTRL
+// Description : Alias for channel 2 CTRL register
+#define DMA_CH2_AL1_CTRL_OFFSET _u(0x00000090)
+#define DMA_CH2_AL1_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH2_AL1_CTRL_RESET  "-"
+#define DMA_CH2_AL1_CTRL_MSB    _u(31)
+#define DMA_CH2_AL1_CTRL_LSB    _u(0)
+#define DMA_CH2_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_AL1_READ_ADDR
+// Description : Alias for channel 2 READ_ADDR register
+#define DMA_CH2_AL1_READ_ADDR_OFFSET _u(0x00000094)
+#define DMA_CH2_AL1_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH2_AL1_READ_ADDR_RESET  "-"
+#define DMA_CH2_AL1_READ_ADDR_MSB    _u(31)
+#define DMA_CH2_AL1_READ_ADDR_LSB    _u(0)
+#define DMA_CH2_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_AL1_WRITE_ADDR
+// Description : Alias for channel 2 WRITE_ADDR register
+#define DMA_CH2_AL1_WRITE_ADDR_OFFSET _u(0x00000098)
+#define DMA_CH2_AL1_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH2_AL1_WRITE_ADDR_RESET  "-"
+#define DMA_CH2_AL1_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH2_AL1_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 2 TRANS_COUNT register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000009c)
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET  "-"
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_AL2_CTRL
+// Description : Alias for channel 2 CTRL register
+#define DMA_CH2_AL2_CTRL_OFFSET _u(0x000000a0)
+#define DMA_CH2_AL2_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH2_AL2_CTRL_RESET  "-"
+#define DMA_CH2_AL2_CTRL_MSB    _u(31)
+#define DMA_CH2_AL2_CTRL_LSB    _u(0)
+#define DMA_CH2_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_AL2_TRANS_COUNT
+// Description : Alias for channel 2 TRANS_COUNT register
+#define DMA_CH2_AL2_TRANS_COUNT_OFFSET _u(0x000000a4)
+#define DMA_CH2_AL2_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH2_AL2_TRANS_COUNT_RESET  "-"
+#define DMA_CH2_AL2_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH2_AL2_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_AL2_READ_ADDR
+// Description : Alias for channel 2 READ_ADDR register
+#define DMA_CH2_AL2_READ_ADDR_OFFSET _u(0x000000a8)
+#define DMA_CH2_AL2_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH2_AL2_READ_ADDR_RESET  "-"
+#define DMA_CH2_AL2_READ_ADDR_MSB    _u(31)
+#define DMA_CH2_AL2_READ_ADDR_LSB    _u(0)
+#define DMA_CH2_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 2 WRITE_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ac)
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET  "-"
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_AL3_CTRL
+// Description : Alias for channel 2 CTRL register
+#define DMA_CH2_AL3_CTRL_OFFSET _u(0x000000b0)
+#define DMA_CH2_AL3_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH2_AL3_CTRL_RESET  "-"
+#define DMA_CH2_AL3_CTRL_MSB    _u(31)
+#define DMA_CH2_AL3_CTRL_LSB    _u(0)
+#define DMA_CH2_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_AL3_WRITE_ADDR
+// Description : Alias for channel 2 WRITE_ADDR register
+#define DMA_CH2_AL3_WRITE_ADDR_OFFSET _u(0x000000b4)
+#define DMA_CH2_AL3_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH2_AL3_WRITE_ADDR_RESET  "-"
+#define DMA_CH2_AL3_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH2_AL3_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_AL3_TRANS_COUNT
+// Description : Alias for channel 2 TRANS_COUNT register
+#define DMA_CH2_AL3_TRANS_COUNT_OFFSET _u(0x000000b8)
+#define DMA_CH2_AL3_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH2_AL3_TRANS_COUNT_RESET  "-"
+#define DMA_CH2_AL3_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH2_AL3_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH2_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 2 READ_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000bc)
+#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH2_AL3_READ_ADDR_TRIG_RESET  "-"
+#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_READ_ADDR
+// Description : DMA Channel 3 Read Address pointer
+//               This register updates automatically each time a read completes.
+//               The current value is the next address to be read by this
+//               channel.
+#define DMA_CH3_READ_ADDR_OFFSET _u(0x000000c0)
+#define DMA_CH3_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH3_READ_ADDR_RESET  _u(0x00000000)
+#define DMA_CH3_READ_ADDR_MSB    _u(31)
+#define DMA_CH3_READ_ADDR_LSB    _u(0)
+#define DMA_CH3_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_WRITE_ADDR
+// Description : DMA Channel 3 Write Address pointer
+//               This register updates automatically each time a write
+//               completes. The current value is the next address to be written
+//               by this channel.
+#define DMA_CH3_WRITE_ADDR_OFFSET _u(0x000000c4)
+#define DMA_CH3_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH3_WRITE_ADDR_RESET  _u(0x00000000)
+#define DMA_CH3_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH3_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_TRANS_COUNT
+// Description : DMA Channel 3 Transfer Count
+//               Program the number of bus transfers a channel will perform
+//               before halting. Note that, if transfers are larger than one
+//               byte in size, this is not equal to the number of bytes
+//               transferred (see CTRL_DATA_SIZE).
+//
+//               When the channel is active, reading this register shows the
+//               number of transfers remaining, updating automatically each time
+//               a write transfer completes.
+//
+//               Writing this register sets the RELOAD value for the transfer
+//               counter. Each time this channel is triggered, the RELOAD value
+//               is copied into the live transfer counter. The channel can be
+//               started multiple times, and will perform the same number of
+//               transfers each time, as programmed by most recent write.
+//
+//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+//               is used as a trigger, the written value is used immediately as
+//               the length of the new transfer sequence, as well as being
+//               written to RELOAD.
+#define DMA_CH3_TRANS_COUNT_OFFSET _u(0x000000c8)
+#define DMA_CH3_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH3_TRANS_COUNT_RESET  _u(0x00000000)
+#define DMA_CH3_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH3_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_CTRL_TRIG
+// Description : DMA Channel 3 Control and Status
+#define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc)
+#define DMA_CH3_CTRL_TRIG_BITS   _u(0xe1ffffff)
+#define DMA_CH3_CTRL_TRIG_RESET  _u(0x00001800)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+//               halts when it encounters any bus error, and always raises its
+//               channel IRQ flag.
+#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET  _u(0x0)
+#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS   _u(0x80000000)
+#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB    _u(31)
+#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB    _u(31)
+#define DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+//               clear.
+//               READ_ADDR shows the approximate address where the bus error was
+//               encountered (will not to be earlier, or more than 3 transfers
+//               later)
+#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET  _u(0x0)
+#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS   _u(0x40000000)
+#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB    _u(30)
+#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB    _u(30)
+#define DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+//               clear.
+//               WRITE_ADDR shows the approximate address where the bus error
+//               was encountered (will not to be earlier, or more than 5
+//               transfers later)
+#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET  _u(0x0)
+#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS   _u(0x20000000)
+#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB    _u(29)
+#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB    _u(29)
+#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+//               sequence, and low when the last transfer of that sequence
+//               completes. Clearing EN while BUSY is high pauses the channel,
+//               and BUSY will stay high while paused.
+//
+//               To terminate a sequence early (and clear the BUSY flag), see
+//               CHAN_ABORT.
+#define DMA_CH3_CTRL_TRIG_BUSY_RESET  _u(0x0)
+#define DMA_CH3_CTRL_TRIG_BUSY_BITS   _u(0x01000000)
+#define DMA_CH3_CTRL_TRIG_BUSY_MSB    _u(24)
+#define DMA_CH3_CTRL_TRIG_BUSY_LSB    _u(24)
+#define DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+//               hardware, and each transfer will advance the state of the
+//               checksum. This only applies if the sniff hardware is enabled,
+//               and has this channel selected.
+//
+//               This allows checksum to be enabled or disabled on a
+//               per-control- block basis.
+#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET  _u(0x0)
+#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS   _u(0x00800000)
+#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB    _u(23)
+#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB    _u(23)
+#define DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+//               For byte data, this has no effect. For halfword data, the two
+//               bytes of each halfword are swapped. For word data, the four
+//               bytes of each word are swapped to reverse order.
+#define DMA_CH3_CTRL_TRIG_BSWAP_RESET  _u(0x0)
+#define DMA_CH3_CTRL_TRIG_BSWAP_BITS   _u(0x00400000)
+#define DMA_CH3_CTRL_TRIG_BSWAP_MSB    _u(22)
+#define DMA_CH3_CTRL_TRIG_BSWAP_LSB    _u(22)
+#define DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+//               every transfer block. Instead, an IRQ is raised when NULL is
+//               written to a trigger register, indicating the end of a control
+//               block chain.
+//
+//               This reduces the number of interrupts to be serviced by the CPU
+//               when transferring a DMA chain of many small control blocks.
+#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET  _u(0x0)
+#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS   _u(0x00200000)
+#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB    _u(21)
+#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB    _u(21)
+#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+//               The channel uses the transfer request signal to pace its data
+//               transfer rate. Sources for TREQ signals are internal (TIMERS)
+//               or external (DREQ, a Data Request from the system).
+//               0x0 to 0x3a -> select DREQ n as TREQ
+//               0x3b -> Select Timer 0 as TREQ
+//               0x3c -> Select Timer 1 as TREQ
+//               0x3d -> Select Timer 2 as TREQ (Optional)
+//               0x3e -> Select Timer 3 as TREQ (Optional)
+//               0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET           _u(0x00)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS            _u(0x001f8000)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB             _u(20)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB             _u(15)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS          "RW"
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    _u(0x3b)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    _u(0x3c)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    _u(0x3d)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    _u(0x3e)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+//               channel)_.
+//               Reset value is equal to channel number (3).
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET  _u(0x3)
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
+//               boundary. If 1, write addresses are wrapped.
+#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET  _u(0x0)
+#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS   _u(0x00000400)
+#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB    _u(10)
+#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB    _u(10)
+#define DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+//               0, only the lower n bits of the address will change. This wraps
+//               the address on a (1 << n) byte boundary, facilitating access to
+//               naturally-aligned ring buffers.
+//
+//               Ring sizes between 2 and 32768 bytes are possible. This can
+//               apply to either read or write addresses, based on value of
+//               RING_SEL.
+//               0x0 -> RING_NONE
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET           _u(0x0)
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS            _u(0x000003c0)
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB             _u(9)
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB             _u(6)
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS          "RW"
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+//               each write is directed to the same, initial address.
+//
+//               Generally this should be disabled for memory-to-peripheral
+//               transfers.
+#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET  _u(0x0)
+#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS   _u(0x00000020)
+#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB    _u(5)
+#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB    _u(5)
+#define DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+//               each read is directed to the same, initial address.
+//
+//               Generally this should be disabled for peripheral-to-memory
+//               transfers.
+#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET  _u(0x0)
+#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS   _u(0x00000010)
+#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB    _u(4)
+#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB    _u(4)
+#define DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+//               with each transfer.
+//               0x0 -> SIZE_BYTE
+//               0x1 -> SIZE_HALFWORD
+//               0x2 -> SIZE_WORD
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET               _u(0x0)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS                _u(0x0000000c)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB                 _u(3)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB                 _u(2)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS              "RW"
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     _u(0x0)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+//               scheduling: in each scheduling round, all high priority
+//               channels are considered first, and then only a single low
+//               priority channel, before returning to the high priority
+//               channels.
+//
+//               This only affects the order in which the DMA schedules
+//               channels. The DMA's bus priority is not changed. If the DMA is
+//               not saturated then a low priority channel will see no loss of
+//               throughput.
+#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET  _u(0x0)
+#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS   _u(0x00000002)
+#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB    _u(1)
+#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB    _u(1)
+#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH3_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+//               When 1, the channel will respond to triggering events, which
+//               will cause it to become BUSY and start transferring data. When
+//               0, the channel will ignore triggers, stop issuing transfers,
+//               and pause the current transfer sequence (i.e. BUSY will remain
+//               high if already high)
+#define DMA_CH3_CTRL_TRIG_EN_RESET  _u(0x0)
+#define DMA_CH3_CTRL_TRIG_EN_BITS   _u(0x00000001)
+#define DMA_CH3_CTRL_TRIG_EN_MSB    _u(0)
+#define DMA_CH3_CTRL_TRIG_EN_LSB    _u(0)
+#define DMA_CH3_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_AL1_CTRL
+// Description : Alias for channel 3 CTRL register
+#define DMA_CH3_AL1_CTRL_OFFSET _u(0x000000d0)
+#define DMA_CH3_AL1_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH3_AL1_CTRL_RESET  "-"
+#define DMA_CH3_AL1_CTRL_MSB    _u(31)
+#define DMA_CH3_AL1_CTRL_LSB    _u(0)
+#define DMA_CH3_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_AL1_READ_ADDR
+// Description : Alias for channel 3 READ_ADDR register
+#define DMA_CH3_AL1_READ_ADDR_OFFSET _u(0x000000d4)
+#define DMA_CH3_AL1_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH3_AL1_READ_ADDR_RESET  "-"
+#define DMA_CH3_AL1_READ_ADDR_MSB    _u(31)
+#define DMA_CH3_AL1_READ_ADDR_LSB    _u(0)
+#define DMA_CH3_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_AL1_WRITE_ADDR
+// Description : Alias for channel 3 WRITE_ADDR register
+#define DMA_CH3_AL1_WRITE_ADDR_OFFSET _u(0x000000d8)
+#define DMA_CH3_AL1_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH3_AL1_WRITE_ADDR_RESET  "-"
+#define DMA_CH3_AL1_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH3_AL1_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 3 TRANS_COUNT register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000000dc)
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET  "-"
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_AL2_CTRL
+// Description : Alias for channel 3 CTRL register
+#define DMA_CH3_AL2_CTRL_OFFSET _u(0x000000e0)
+#define DMA_CH3_AL2_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH3_AL2_CTRL_RESET  "-"
+#define DMA_CH3_AL2_CTRL_MSB    _u(31)
+#define DMA_CH3_AL2_CTRL_LSB    _u(0)
+#define DMA_CH3_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_AL2_TRANS_COUNT
+// Description : Alias for channel 3 TRANS_COUNT register
+#define DMA_CH3_AL2_TRANS_COUNT_OFFSET _u(0x000000e4)
+#define DMA_CH3_AL2_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH3_AL2_TRANS_COUNT_RESET  "-"
+#define DMA_CH3_AL2_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH3_AL2_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_AL2_READ_ADDR
+// Description : Alias for channel 3 READ_ADDR register
+#define DMA_CH3_AL2_READ_ADDR_OFFSET _u(0x000000e8)
+#define DMA_CH3_AL2_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH3_AL2_READ_ADDR_RESET  "-"
+#define DMA_CH3_AL2_READ_ADDR_MSB    _u(31)
+#define DMA_CH3_AL2_READ_ADDR_LSB    _u(0)
+#define DMA_CH3_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 3 WRITE_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ec)
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET  "-"
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_AL3_CTRL
+// Description : Alias for channel 3 CTRL register
+#define DMA_CH3_AL3_CTRL_OFFSET _u(0x000000f0)
+#define DMA_CH3_AL3_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH3_AL3_CTRL_RESET  "-"
+#define DMA_CH3_AL3_CTRL_MSB    _u(31)
+#define DMA_CH3_AL3_CTRL_LSB    _u(0)
+#define DMA_CH3_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_AL3_WRITE_ADDR
+// Description : Alias for channel 3 WRITE_ADDR register
+#define DMA_CH3_AL3_WRITE_ADDR_OFFSET _u(0x000000f4)
+#define DMA_CH3_AL3_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH3_AL3_WRITE_ADDR_RESET  "-"
+#define DMA_CH3_AL3_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH3_AL3_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_AL3_TRANS_COUNT
+// Description : Alias for channel 3 TRANS_COUNT register
+#define DMA_CH3_AL3_TRANS_COUNT_OFFSET _u(0x000000f8)
+#define DMA_CH3_AL3_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH3_AL3_TRANS_COUNT_RESET  "-"
+#define DMA_CH3_AL3_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH3_AL3_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH3_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 3 READ_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000fc)
+#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH3_AL3_READ_ADDR_TRIG_RESET  "-"
+#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_READ_ADDR
+// Description : DMA Channel 4 Read Address pointer
+//               This register updates automatically each time a read completes.
+//               The current value is the next address to be read by this
+//               channel.
+#define DMA_CH4_READ_ADDR_OFFSET _u(0x00000100)
+#define DMA_CH4_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH4_READ_ADDR_RESET  _u(0x00000000)
+#define DMA_CH4_READ_ADDR_MSB    _u(31)
+#define DMA_CH4_READ_ADDR_LSB    _u(0)
+#define DMA_CH4_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_WRITE_ADDR
+// Description : DMA Channel 4 Write Address pointer
+//               This register updates automatically each time a write
+//               completes. The current value is the next address to be written
+//               by this channel.
+#define DMA_CH4_WRITE_ADDR_OFFSET _u(0x00000104)
+#define DMA_CH4_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH4_WRITE_ADDR_RESET  _u(0x00000000)
+#define DMA_CH4_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH4_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH4_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_TRANS_COUNT
+// Description : DMA Channel 4 Transfer Count
+//               Program the number of bus transfers a channel will perform
+//               before halting. Note that, if transfers are larger than one
+//               byte in size, this is not equal to the number of bytes
+//               transferred (see CTRL_DATA_SIZE).
+//
+//               When the channel is active, reading this register shows the
+//               number of transfers remaining, updating automatically each time
+//               a write transfer completes.
+//
+//               Writing this register sets the RELOAD value for the transfer
+//               counter. Each time this channel is triggered, the RELOAD value
+//               is copied into the live transfer counter. The channel can be
+//               started multiple times, and will perform the same number of
+//               transfers each time, as programmed by most recent write.
+//
+//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+//               is used as a trigger, the written value is used immediately as
+//               the length of the new transfer sequence, as well as being
+//               written to RELOAD.
+#define DMA_CH4_TRANS_COUNT_OFFSET _u(0x00000108)
+#define DMA_CH4_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH4_TRANS_COUNT_RESET  _u(0x00000000)
+#define DMA_CH4_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH4_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH4_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_CTRL_TRIG
+// Description : DMA Channel 4 Control and Status
+#define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c)
+#define DMA_CH4_CTRL_TRIG_BITS   _u(0xe1ffffff)
+#define DMA_CH4_CTRL_TRIG_RESET  _u(0x00002000)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+//               halts when it encounters any bus error, and always raises its
+//               channel IRQ flag.
+#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET  _u(0x0)
+#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS   _u(0x80000000)
+#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB    _u(31)
+#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB    _u(31)
+#define DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+//               clear.
+//               READ_ADDR shows the approximate address where the bus error was
+//               encountered (will not to be earlier, or more than 3 transfers
+//               later)
+#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET  _u(0x0)
+#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS   _u(0x40000000)
+#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB    _u(30)
+#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB    _u(30)
+#define DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+//               clear.
+//               WRITE_ADDR shows the approximate address where the bus error
+//               was encountered (will not to be earlier, or more than 5
+//               transfers later)
+#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET  _u(0x0)
+#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS   _u(0x20000000)
+#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB    _u(29)
+#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB    _u(29)
+#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+//               sequence, and low when the last transfer of that sequence
+//               completes. Clearing EN while BUSY is high pauses the channel,
+//               and BUSY will stay high while paused.
+//
+//               To terminate a sequence early (and clear the BUSY flag), see
+//               CHAN_ABORT.
+#define DMA_CH4_CTRL_TRIG_BUSY_RESET  _u(0x0)
+#define DMA_CH4_CTRL_TRIG_BUSY_BITS   _u(0x01000000)
+#define DMA_CH4_CTRL_TRIG_BUSY_MSB    _u(24)
+#define DMA_CH4_CTRL_TRIG_BUSY_LSB    _u(24)
+#define DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+//               hardware, and each transfer will advance the state of the
+//               checksum. This only applies if the sniff hardware is enabled,
+//               and has this channel selected.
+//
+//               This allows checksum to be enabled or disabled on a
+//               per-control- block basis.
+#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET  _u(0x0)
+#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS   _u(0x00800000)
+#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB    _u(23)
+#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB    _u(23)
+#define DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+//               For byte data, this has no effect. For halfword data, the two
+//               bytes of each halfword are swapped. For word data, the four
+//               bytes of each word are swapped to reverse order.
+#define DMA_CH4_CTRL_TRIG_BSWAP_RESET  _u(0x0)
+#define DMA_CH4_CTRL_TRIG_BSWAP_BITS   _u(0x00400000)
+#define DMA_CH4_CTRL_TRIG_BSWAP_MSB    _u(22)
+#define DMA_CH4_CTRL_TRIG_BSWAP_LSB    _u(22)
+#define DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+//               every transfer block. Instead, an IRQ is raised when NULL is
+//               written to a trigger register, indicating the end of a control
+//               block chain.
+//
+//               This reduces the number of interrupts to be serviced by the CPU
+//               when transferring a DMA chain of many small control blocks.
+#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET  _u(0x0)
+#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS   _u(0x00200000)
+#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB    _u(21)
+#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB    _u(21)
+#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+//               The channel uses the transfer request signal to pace its data
+//               transfer rate. Sources for TREQ signals are internal (TIMERS)
+//               or external (DREQ, a Data Request from the system).
+//               0x0 to 0x3a -> select DREQ n as TREQ
+//               0x3b -> Select Timer 0 as TREQ
+//               0x3c -> Select Timer 1 as TREQ
+//               0x3d -> Select Timer 2 as TREQ (Optional)
+//               0x3e -> Select Timer 3 as TREQ (Optional)
+//               0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET           _u(0x00)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS            _u(0x001f8000)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB             _u(20)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB             _u(15)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS          "RW"
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    _u(0x3b)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    _u(0x3c)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    _u(0x3d)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    _u(0x3e)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+//               channel)_.
+//               Reset value is equal to channel number (4).
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET  _u(0x4)
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
+//               boundary. If 1, write addresses are wrapped.
+#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET  _u(0x0)
+#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS   _u(0x00000400)
+#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB    _u(10)
+#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB    _u(10)
+#define DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+//               0, only the lower n bits of the address will change. This wraps
+//               the address on a (1 << n) byte boundary, facilitating access to
+//               naturally-aligned ring buffers.
+//
+//               Ring sizes between 2 and 32768 bytes are possible. This can
+//               apply to either read or write addresses, based on value of
+//               RING_SEL.
+//               0x0 -> RING_NONE
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET           _u(0x0)
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS            _u(0x000003c0)
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB             _u(9)
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB             _u(6)
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS          "RW"
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+//               each write is directed to the same, initial address.
+//
+//               Generally this should be disabled for memory-to-peripheral
+//               transfers.
+#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET  _u(0x0)
+#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS   _u(0x00000020)
+#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB    _u(5)
+#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB    _u(5)
+#define DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+//               each read is directed to the same, initial address.
+//
+//               Generally this should be disabled for peripheral-to-memory
+//               transfers.
+#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET  _u(0x0)
+#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS   _u(0x00000010)
+#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB    _u(4)
+#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB    _u(4)
+#define DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+//               with each transfer.
+//               0x0 -> SIZE_BYTE
+//               0x1 -> SIZE_HALFWORD
+//               0x2 -> SIZE_WORD
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET               _u(0x0)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS                _u(0x0000000c)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB                 _u(3)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB                 _u(2)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS              "RW"
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     _u(0x0)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+//               scheduling: in each scheduling round, all high priority
+//               channels are considered first, and then only a single low
+//               priority channel, before returning to the high priority
+//               channels.
+//
+//               This only affects the order in which the DMA schedules
+//               channels. The DMA's bus priority is not changed. If the DMA is
+//               not saturated then a low priority channel will see no loss of
+//               throughput.
+#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET  _u(0x0)
+#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS   _u(0x00000002)
+#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB    _u(1)
+#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB    _u(1)
+#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH4_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+//               When 1, the channel will respond to triggering events, which
+//               will cause it to become BUSY and start transferring data. When
+//               0, the channel will ignore triggers, stop issuing transfers,
+//               and pause the current transfer sequence (i.e. BUSY will remain
+//               high if already high)
+#define DMA_CH4_CTRL_TRIG_EN_RESET  _u(0x0)
+#define DMA_CH4_CTRL_TRIG_EN_BITS   _u(0x00000001)
+#define DMA_CH4_CTRL_TRIG_EN_MSB    _u(0)
+#define DMA_CH4_CTRL_TRIG_EN_LSB    _u(0)
+#define DMA_CH4_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_AL1_CTRL
+// Description : Alias for channel 4 CTRL register
+#define DMA_CH4_AL1_CTRL_OFFSET _u(0x00000110)
+#define DMA_CH4_AL1_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH4_AL1_CTRL_RESET  "-"
+#define DMA_CH4_AL1_CTRL_MSB    _u(31)
+#define DMA_CH4_AL1_CTRL_LSB    _u(0)
+#define DMA_CH4_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_AL1_READ_ADDR
+// Description : Alias for channel 4 READ_ADDR register
+#define DMA_CH4_AL1_READ_ADDR_OFFSET _u(0x00000114)
+#define DMA_CH4_AL1_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH4_AL1_READ_ADDR_RESET  "-"
+#define DMA_CH4_AL1_READ_ADDR_MSB    _u(31)
+#define DMA_CH4_AL1_READ_ADDR_LSB    _u(0)
+#define DMA_CH4_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_AL1_WRITE_ADDR
+// Description : Alias for channel 4 WRITE_ADDR register
+#define DMA_CH4_AL1_WRITE_ADDR_OFFSET _u(0x00000118)
+#define DMA_CH4_AL1_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH4_AL1_WRITE_ADDR_RESET  "-"
+#define DMA_CH4_AL1_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH4_AL1_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 4 TRANS_COUNT register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000011c)
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET  "-"
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_AL2_CTRL
+// Description : Alias for channel 4 CTRL register
+#define DMA_CH4_AL2_CTRL_OFFSET _u(0x00000120)
+#define DMA_CH4_AL2_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH4_AL2_CTRL_RESET  "-"
+#define DMA_CH4_AL2_CTRL_MSB    _u(31)
+#define DMA_CH4_AL2_CTRL_LSB    _u(0)
+#define DMA_CH4_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_AL2_TRANS_COUNT
+// Description : Alias for channel 4 TRANS_COUNT register
+#define DMA_CH4_AL2_TRANS_COUNT_OFFSET _u(0x00000124)
+#define DMA_CH4_AL2_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH4_AL2_TRANS_COUNT_RESET  "-"
+#define DMA_CH4_AL2_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH4_AL2_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_AL2_READ_ADDR
+// Description : Alias for channel 4 READ_ADDR register
+#define DMA_CH4_AL2_READ_ADDR_OFFSET _u(0x00000128)
+#define DMA_CH4_AL2_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH4_AL2_READ_ADDR_RESET  "-"
+#define DMA_CH4_AL2_READ_ADDR_MSB    _u(31)
+#define DMA_CH4_AL2_READ_ADDR_LSB    _u(0)
+#define DMA_CH4_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 4 WRITE_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000012c)
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET  "-"
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_AL3_CTRL
+// Description : Alias for channel 4 CTRL register
+#define DMA_CH4_AL3_CTRL_OFFSET _u(0x00000130)
+#define DMA_CH4_AL3_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH4_AL3_CTRL_RESET  "-"
+#define DMA_CH4_AL3_CTRL_MSB    _u(31)
+#define DMA_CH4_AL3_CTRL_LSB    _u(0)
+#define DMA_CH4_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_AL3_WRITE_ADDR
+// Description : Alias for channel 4 WRITE_ADDR register
+#define DMA_CH4_AL3_WRITE_ADDR_OFFSET _u(0x00000134)
+#define DMA_CH4_AL3_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH4_AL3_WRITE_ADDR_RESET  "-"
+#define DMA_CH4_AL3_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH4_AL3_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_AL3_TRANS_COUNT
+// Description : Alias for channel 4 TRANS_COUNT register
+#define DMA_CH4_AL3_TRANS_COUNT_OFFSET _u(0x00000138)
+#define DMA_CH4_AL3_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH4_AL3_TRANS_COUNT_RESET  "-"
+#define DMA_CH4_AL3_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH4_AL3_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH4_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 4 READ_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000013c)
+#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH4_AL3_READ_ADDR_TRIG_RESET  "-"
+#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_READ_ADDR
+// Description : DMA Channel 5 Read Address pointer
+//               This register updates automatically each time a read completes.
+//               The current value is the next address to be read by this
+//               channel.
+#define DMA_CH5_READ_ADDR_OFFSET _u(0x00000140)
+#define DMA_CH5_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH5_READ_ADDR_RESET  _u(0x00000000)
+#define DMA_CH5_READ_ADDR_MSB    _u(31)
+#define DMA_CH5_READ_ADDR_LSB    _u(0)
+#define DMA_CH5_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_WRITE_ADDR
+// Description : DMA Channel 5 Write Address pointer
+//               This register updates automatically each time a write
+//               completes. The current value is the next address to be written
+//               by this channel.
+#define DMA_CH5_WRITE_ADDR_OFFSET _u(0x00000144)
+#define DMA_CH5_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH5_WRITE_ADDR_RESET  _u(0x00000000)
+#define DMA_CH5_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH5_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH5_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_TRANS_COUNT
+// Description : DMA Channel 5 Transfer Count
+//               Program the number of bus transfers a channel will perform
+//               before halting. Note that, if transfers are larger than one
+//               byte in size, this is not equal to the number of bytes
+//               transferred (see CTRL_DATA_SIZE).
+//
+//               When the channel is active, reading this register shows the
+//               number of transfers remaining, updating automatically each time
+//               a write transfer completes.
+//
+//               Writing this register sets the RELOAD value for the transfer
+//               counter. Each time this channel is triggered, the RELOAD value
+//               is copied into the live transfer counter. The channel can be
+//               started multiple times, and will perform the same number of
+//               transfers each time, as programmed by most recent write.
+//
+//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+//               is used as a trigger, the written value is used immediately as
+//               the length of the new transfer sequence, as well as being
+//               written to RELOAD.
+#define DMA_CH5_TRANS_COUNT_OFFSET _u(0x00000148)
+#define DMA_CH5_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH5_TRANS_COUNT_RESET  _u(0x00000000)
+#define DMA_CH5_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH5_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH5_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_CTRL_TRIG
+// Description : DMA Channel 5 Control and Status
+#define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c)
+#define DMA_CH5_CTRL_TRIG_BITS   _u(0xe1ffffff)
+#define DMA_CH5_CTRL_TRIG_RESET  _u(0x00002800)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+//               halts when it encounters any bus error, and always raises its
+//               channel IRQ flag.
+#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET  _u(0x0)
+#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS   _u(0x80000000)
+#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB    _u(31)
+#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB    _u(31)
+#define DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+//               clear.
+//               READ_ADDR shows the approximate address where the bus error was
+//               encountered (will not to be earlier, or more than 3 transfers
+//               later)
+#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET  _u(0x0)
+#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS   _u(0x40000000)
+#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB    _u(30)
+#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB    _u(30)
+#define DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+//               clear.
+//               WRITE_ADDR shows the approximate address where the bus error
+//               was encountered (will not to be earlier, or more than 5
+//               transfers later)
+#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET  _u(0x0)
+#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS   _u(0x20000000)
+#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB    _u(29)
+#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB    _u(29)
+#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+//               sequence, and low when the last transfer of that sequence
+//               completes. Clearing EN while BUSY is high pauses the channel,
+//               and BUSY will stay high while paused.
+//
+//               To terminate a sequence early (and clear the BUSY flag), see
+//               CHAN_ABORT.
+#define DMA_CH5_CTRL_TRIG_BUSY_RESET  _u(0x0)
+#define DMA_CH5_CTRL_TRIG_BUSY_BITS   _u(0x01000000)
+#define DMA_CH5_CTRL_TRIG_BUSY_MSB    _u(24)
+#define DMA_CH5_CTRL_TRIG_BUSY_LSB    _u(24)
+#define DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+//               hardware, and each transfer will advance the state of the
+//               checksum. This only applies if the sniff hardware is enabled,
+//               and has this channel selected.
+//
+//               This allows checksum to be enabled or disabled on a
+//               per-control- block basis.
+#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET  _u(0x0)
+#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS   _u(0x00800000)
+#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB    _u(23)
+#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB    _u(23)
+#define DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+//               For byte data, this has no effect. For halfword data, the two
+//               bytes of each halfword are swapped. For word data, the four
+//               bytes of each word are swapped to reverse order.
+#define DMA_CH5_CTRL_TRIG_BSWAP_RESET  _u(0x0)
+#define DMA_CH5_CTRL_TRIG_BSWAP_BITS   _u(0x00400000)
+#define DMA_CH5_CTRL_TRIG_BSWAP_MSB    _u(22)
+#define DMA_CH5_CTRL_TRIG_BSWAP_LSB    _u(22)
+#define DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+//               every transfer block. Instead, an IRQ is raised when NULL is
+//               written to a trigger register, indicating the end of a control
+//               block chain.
+//
+//               This reduces the number of interrupts to be serviced by the CPU
+//               when transferring a DMA chain of many small control blocks.
+#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET  _u(0x0)
+#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS   _u(0x00200000)
+#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB    _u(21)
+#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB    _u(21)
+#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+//               The channel uses the transfer request signal to pace its data
+//               transfer rate. Sources for TREQ signals are internal (TIMERS)
+//               or external (DREQ, a Data Request from the system).
+//               0x0 to 0x3a -> select DREQ n as TREQ
+//               0x3b -> Select Timer 0 as TREQ
+//               0x3c -> Select Timer 1 as TREQ
+//               0x3d -> Select Timer 2 as TREQ (Optional)
+//               0x3e -> Select Timer 3 as TREQ (Optional)
+//               0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET           _u(0x00)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS            _u(0x001f8000)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB             _u(20)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB             _u(15)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS          "RW"
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    _u(0x3b)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    _u(0x3c)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    _u(0x3d)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    _u(0x3e)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+//               channel)_.
+//               Reset value is equal to channel number (5).
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET  _u(0x5)
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
+//               boundary. If 1, write addresses are wrapped.
+#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET  _u(0x0)
+#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS   _u(0x00000400)
+#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB    _u(10)
+#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB    _u(10)
+#define DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+//               0, only the lower n bits of the address will change. This wraps
+//               the address on a (1 << n) byte boundary, facilitating access to
+//               naturally-aligned ring buffers.
+//
+//               Ring sizes between 2 and 32768 bytes are possible. This can
+//               apply to either read or write addresses, based on value of
+//               RING_SEL.
+//               0x0 -> RING_NONE
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET           _u(0x0)
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS            _u(0x000003c0)
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB             _u(9)
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB             _u(6)
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS          "RW"
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+//               each write is directed to the same, initial address.
+//
+//               Generally this should be disabled for memory-to-peripheral
+//               transfers.
+#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET  _u(0x0)
+#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS   _u(0x00000020)
+#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB    _u(5)
+#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB    _u(5)
+#define DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+//               each read is directed to the same, initial address.
+//
+//               Generally this should be disabled for peripheral-to-memory
+//               transfers.
+#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET  _u(0x0)
+#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS   _u(0x00000010)
+#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB    _u(4)
+#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB    _u(4)
+#define DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+//               with each transfer.
+//               0x0 -> SIZE_BYTE
+//               0x1 -> SIZE_HALFWORD
+//               0x2 -> SIZE_WORD
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET               _u(0x0)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS                _u(0x0000000c)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB                 _u(3)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB                 _u(2)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS              "RW"
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     _u(0x0)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+//               scheduling: in each scheduling round, all high priority
+//               channels are considered first, and then only a single low
+//               priority channel, before returning to the high priority
+//               channels.
+//
+//               This only affects the order in which the DMA schedules
+//               channels. The DMA's bus priority is not changed. If the DMA is
+//               not saturated then a low priority channel will see no loss of
+//               throughput.
+#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET  _u(0x0)
+#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS   _u(0x00000002)
+#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB    _u(1)
+#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB    _u(1)
+#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH5_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+//               When 1, the channel will respond to triggering events, which
+//               will cause it to become BUSY and start transferring data. When
+//               0, the channel will ignore triggers, stop issuing transfers,
+//               and pause the current transfer sequence (i.e. BUSY will remain
+//               high if already high)
+#define DMA_CH5_CTRL_TRIG_EN_RESET  _u(0x0)
+#define DMA_CH5_CTRL_TRIG_EN_BITS   _u(0x00000001)
+#define DMA_CH5_CTRL_TRIG_EN_MSB    _u(0)
+#define DMA_CH5_CTRL_TRIG_EN_LSB    _u(0)
+#define DMA_CH5_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_AL1_CTRL
+// Description : Alias for channel 5 CTRL register
+#define DMA_CH5_AL1_CTRL_OFFSET _u(0x00000150)
+#define DMA_CH5_AL1_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH5_AL1_CTRL_RESET  "-"
+#define DMA_CH5_AL1_CTRL_MSB    _u(31)
+#define DMA_CH5_AL1_CTRL_LSB    _u(0)
+#define DMA_CH5_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_AL1_READ_ADDR
+// Description : Alias for channel 5 READ_ADDR register
+#define DMA_CH5_AL1_READ_ADDR_OFFSET _u(0x00000154)
+#define DMA_CH5_AL1_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH5_AL1_READ_ADDR_RESET  "-"
+#define DMA_CH5_AL1_READ_ADDR_MSB    _u(31)
+#define DMA_CH5_AL1_READ_ADDR_LSB    _u(0)
+#define DMA_CH5_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_AL1_WRITE_ADDR
+// Description : Alias for channel 5 WRITE_ADDR register
+#define DMA_CH5_AL1_WRITE_ADDR_OFFSET _u(0x00000158)
+#define DMA_CH5_AL1_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH5_AL1_WRITE_ADDR_RESET  "-"
+#define DMA_CH5_AL1_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH5_AL1_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 5 TRANS_COUNT register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000015c)
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET  "-"
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_AL2_CTRL
+// Description : Alias for channel 5 CTRL register
+#define DMA_CH5_AL2_CTRL_OFFSET _u(0x00000160)
+#define DMA_CH5_AL2_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH5_AL2_CTRL_RESET  "-"
+#define DMA_CH5_AL2_CTRL_MSB    _u(31)
+#define DMA_CH5_AL2_CTRL_LSB    _u(0)
+#define DMA_CH5_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_AL2_TRANS_COUNT
+// Description : Alias for channel 5 TRANS_COUNT register
+#define DMA_CH5_AL2_TRANS_COUNT_OFFSET _u(0x00000164)
+#define DMA_CH5_AL2_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH5_AL2_TRANS_COUNT_RESET  "-"
+#define DMA_CH5_AL2_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH5_AL2_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_AL2_READ_ADDR
+// Description : Alias for channel 5 READ_ADDR register
+#define DMA_CH5_AL2_READ_ADDR_OFFSET _u(0x00000168)
+#define DMA_CH5_AL2_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH5_AL2_READ_ADDR_RESET  "-"
+#define DMA_CH5_AL2_READ_ADDR_MSB    _u(31)
+#define DMA_CH5_AL2_READ_ADDR_LSB    _u(0)
+#define DMA_CH5_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 5 WRITE_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000016c)
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET  "-"
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_AL3_CTRL
+// Description : Alias for channel 5 CTRL register
+#define DMA_CH5_AL3_CTRL_OFFSET _u(0x00000170)
+#define DMA_CH5_AL3_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH5_AL3_CTRL_RESET  "-"
+#define DMA_CH5_AL3_CTRL_MSB    _u(31)
+#define DMA_CH5_AL3_CTRL_LSB    _u(0)
+#define DMA_CH5_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_AL3_WRITE_ADDR
+// Description : Alias for channel 5 WRITE_ADDR register
+#define DMA_CH5_AL3_WRITE_ADDR_OFFSET _u(0x00000174)
+#define DMA_CH5_AL3_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH5_AL3_WRITE_ADDR_RESET  "-"
+#define DMA_CH5_AL3_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH5_AL3_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_AL3_TRANS_COUNT
+// Description : Alias for channel 5 TRANS_COUNT register
+#define DMA_CH5_AL3_TRANS_COUNT_OFFSET _u(0x00000178)
+#define DMA_CH5_AL3_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH5_AL3_TRANS_COUNT_RESET  "-"
+#define DMA_CH5_AL3_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH5_AL3_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH5_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 5 READ_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000017c)
+#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH5_AL3_READ_ADDR_TRIG_RESET  "-"
+#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_READ_ADDR
+// Description : DMA Channel 6 Read Address pointer
+//               This register updates automatically each time a read completes.
+//               The current value is the next address to be read by this
+//               channel.
+#define DMA_CH6_READ_ADDR_OFFSET _u(0x00000180)
+#define DMA_CH6_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH6_READ_ADDR_RESET  _u(0x00000000)
+#define DMA_CH6_READ_ADDR_MSB    _u(31)
+#define DMA_CH6_READ_ADDR_LSB    _u(0)
+#define DMA_CH6_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_WRITE_ADDR
+// Description : DMA Channel 6 Write Address pointer
+//               This register updates automatically each time a write
+//               completes. The current value is the next address to be written
+//               by this channel.
+#define DMA_CH6_WRITE_ADDR_OFFSET _u(0x00000184)
+#define DMA_CH6_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH6_WRITE_ADDR_RESET  _u(0x00000000)
+#define DMA_CH6_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH6_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH6_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_TRANS_COUNT
+// Description : DMA Channel 6 Transfer Count
+//               Program the number of bus transfers a channel will perform
+//               before halting. Note that, if transfers are larger than one
+//               byte in size, this is not equal to the number of bytes
+//               transferred (see CTRL_DATA_SIZE).
+//
+//               When the channel is active, reading this register shows the
+//               number of transfers remaining, updating automatically each time
+//               a write transfer completes.
+//
+//               Writing this register sets the RELOAD value for the transfer
+//               counter. Each time this channel is triggered, the RELOAD value
+//               is copied into the live transfer counter. The channel can be
+//               started multiple times, and will perform the same number of
+//               transfers each time, as programmed by most recent write.
+//
+//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+//               is used as a trigger, the written value is used immediately as
+//               the length of the new transfer sequence, as well as being
+//               written to RELOAD.
+#define DMA_CH6_TRANS_COUNT_OFFSET _u(0x00000188)
+#define DMA_CH6_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH6_TRANS_COUNT_RESET  _u(0x00000000)
+#define DMA_CH6_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH6_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH6_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_CTRL_TRIG
+// Description : DMA Channel 6 Control and Status
+#define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c)
+#define DMA_CH6_CTRL_TRIG_BITS   _u(0xe1ffffff)
+#define DMA_CH6_CTRL_TRIG_RESET  _u(0x00003000)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+//               halts when it encounters any bus error, and always raises its
+//               channel IRQ flag.
+#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET  _u(0x0)
+#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS   _u(0x80000000)
+#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB    _u(31)
+#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB    _u(31)
+#define DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+//               clear.
+//               READ_ADDR shows the approximate address where the bus error was
+//               encountered (will not to be earlier, or more than 3 transfers
+//               later)
+#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET  _u(0x0)
+#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS   _u(0x40000000)
+#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB    _u(30)
+#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB    _u(30)
+#define DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+//               clear.
+//               WRITE_ADDR shows the approximate address where the bus error
+//               was encountered (will not to be earlier, or more than 5
+//               transfers later)
+#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET  _u(0x0)
+#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS   _u(0x20000000)
+#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB    _u(29)
+#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB    _u(29)
+#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+//               sequence, and low when the last transfer of that sequence
+//               completes. Clearing EN while BUSY is high pauses the channel,
+//               and BUSY will stay high while paused.
+//
+//               To terminate a sequence early (and clear the BUSY flag), see
+//               CHAN_ABORT.
+#define DMA_CH6_CTRL_TRIG_BUSY_RESET  _u(0x0)
+#define DMA_CH6_CTRL_TRIG_BUSY_BITS   _u(0x01000000)
+#define DMA_CH6_CTRL_TRIG_BUSY_MSB    _u(24)
+#define DMA_CH6_CTRL_TRIG_BUSY_LSB    _u(24)
+#define DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+//               hardware, and each transfer will advance the state of the
+//               checksum. This only applies if the sniff hardware is enabled,
+//               and has this channel selected.
+//
+//               This allows checksum to be enabled or disabled on a
+//               per-control- block basis.
+#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET  _u(0x0)
+#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS   _u(0x00800000)
+#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB    _u(23)
+#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB    _u(23)
+#define DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+//               For byte data, this has no effect. For halfword data, the two
+//               bytes of each halfword are swapped. For word data, the four
+//               bytes of each word are swapped to reverse order.
+#define DMA_CH6_CTRL_TRIG_BSWAP_RESET  _u(0x0)
+#define DMA_CH6_CTRL_TRIG_BSWAP_BITS   _u(0x00400000)
+#define DMA_CH6_CTRL_TRIG_BSWAP_MSB    _u(22)
+#define DMA_CH6_CTRL_TRIG_BSWAP_LSB    _u(22)
+#define DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+//               every transfer block. Instead, an IRQ is raised when NULL is
+//               written to a trigger register, indicating the end of a control
+//               block chain.
+//
+//               This reduces the number of interrupts to be serviced by the CPU
+//               when transferring a DMA chain of many small control blocks.
+#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET  _u(0x0)
+#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS   _u(0x00200000)
+#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB    _u(21)
+#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB    _u(21)
+#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+//               The channel uses the transfer request signal to pace its data
+//               transfer rate. Sources for TREQ signals are internal (TIMERS)
+//               or external (DREQ, a Data Request from the system).
+//               0x0 to 0x3a -> select DREQ n as TREQ
+//               0x3b -> Select Timer 0 as TREQ
+//               0x3c -> Select Timer 1 as TREQ
+//               0x3d -> Select Timer 2 as TREQ (Optional)
+//               0x3e -> Select Timer 3 as TREQ (Optional)
+//               0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET           _u(0x00)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS            _u(0x001f8000)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB             _u(20)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB             _u(15)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS          "RW"
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    _u(0x3b)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    _u(0x3c)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    _u(0x3d)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    _u(0x3e)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+//               channel)_.
+//               Reset value is equal to channel number (6).
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET  _u(0x6)
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
+//               boundary. If 1, write addresses are wrapped.
+#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET  _u(0x0)
+#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS   _u(0x00000400)
+#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB    _u(10)
+#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB    _u(10)
+#define DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+//               0, only the lower n bits of the address will change. This wraps
+//               the address on a (1 << n) byte boundary, facilitating access to
+//               naturally-aligned ring buffers.
+//
+//               Ring sizes between 2 and 32768 bytes are possible. This can
+//               apply to either read or write addresses, based on value of
+//               RING_SEL.
+//               0x0 -> RING_NONE
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET           _u(0x0)
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS            _u(0x000003c0)
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB             _u(9)
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB             _u(6)
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS          "RW"
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+//               each write is directed to the same, initial address.
+//
+//               Generally this should be disabled for memory-to-peripheral
+//               transfers.
+#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET  _u(0x0)
+#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS   _u(0x00000020)
+#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB    _u(5)
+#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB    _u(5)
+#define DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+//               each read is directed to the same, initial address.
+//
+//               Generally this should be disabled for peripheral-to-memory
+//               transfers.
+#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET  _u(0x0)
+#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS   _u(0x00000010)
+#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB    _u(4)
+#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB    _u(4)
+#define DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+//               with each transfer.
+//               0x0 -> SIZE_BYTE
+//               0x1 -> SIZE_HALFWORD
+//               0x2 -> SIZE_WORD
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET               _u(0x0)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS                _u(0x0000000c)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB                 _u(3)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB                 _u(2)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS              "RW"
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     _u(0x0)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+//               scheduling: in each scheduling round, all high priority
+//               channels are considered first, and then only a single low
+//               priority channel, before returning to the high priority
+//               channels.
+//
+//               This only affects the order in which the DMA schedules
+//               channels. The DMA's bus priority is not changed. If the DMA is
+//               not saturated then a low priority channel will see no loss of
+//               throughput.
+#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET  _u(0x0)
+#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS   _u(0x00000002)
+#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB    _u(1)
+#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB    _u(1)
+#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH6_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+//               When 1, the channel will respond to triggering events, which
+//               will cause it to become BUSY and start transferring data. When
+//               0, the channel will ignore triggers, stop issuing transfers,
+//               and pause the current transfer sequence (i.e. BUSY will remain
+//               high if already high)
+#define DMA_CH6_CTRL_TRIG_EN_RESET  _u(0x0)
+#define DMA_CH6_CTRL_TRIG_EN_BITS   _u(0x00000001)
+#define DMA_CH6_CTRL_TRIG_EN_MSB    _u(0)
+#define DMA_CH6_CTRL_TRIG_EN_LSB    _u(0)
+#define DMA_CH6_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_AL1_CTRL
+// Description : Alias for channel 6 CTRL register
+#define DMA_CH6_AL1_CTRL_OFFSET _u(0x00000190)
+#define DMA_CH6_AL1_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH6_AL1_CTRL_RESET  "-"
+#define DMA_CH6_AL1_CTRL_MSB    _u(31)
+#define DMA_CH6_AL1_CTRL_LSB    _u(0)
+#define DMA_CH6_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_AL1_READ_ADDR
+// Description : Alias for channel 6 READ_ADDR register
+#define DMA_CH6_AL1_READ_ADDR_OFFSET _u(0x00000194)
+#define DMA_CH6_AL1_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH6_AL1_READ_ADDR_RESET  "-"
+#define DMA_CH6_AL1_READ_ADDR_MSB    _u(31)
+#define DMA_CH6_AL1_READ_ADDR_LSB    _u(0)
+#define DMA_CH6_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_AL1_WRITE_ADDR
+// Description : Alias for channel 6 WRITE_ADDR register
+#define DMA_CH6_AL1_WRITE_ADDR_OFFSET _u(0x00000198)
+#define DMA_CH6_AL1_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH6_AL1_WRITE_ADDR_RESET  "-"
+#define DMA_CH6_AL1_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH6_AL1_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 6 TRANS_COUNT register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000019c)
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET  "-"
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_AL2_CTRL
+// Description : Alias for channel 6 CTRL register
+#define DMA_CH6_AL2_CTRL_OFFSET _u(0x000001a0)
+#define DMA_CH6_AL2_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH6_AL2_CTRL_RESET  "-"
+#define DMA_CH6_AL2_CTRL_MSB    _u(31)
+#define DMA_CH6_AL2_CTRL_LSB    _u(0)
+#define DMA_CH6_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_AL2_TRANS_COUNT
+// Description : Alias for channel 6 TRANS_COUNT register
+#define DMA_CH6_AL2_TRANS_COUNT_OFFSET _u(0x000001a4)
+#define DMA_CH6_AL2_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH6_AL2_TRANS_COUNT_RESET  "-"
+#define DMA_CH6_AL2_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH6_AL2_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_AL2_READ_ADDR
+// Description : Alias for channel 6 READ_ADDR register
+#define DMA_CH6_AL2_READ_ADDR_OFFSET _u(0x000001a8)
+#define DMA_CH6_AL2_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH6_AL2_READ_ADDR_RESET  "-"
+#define DMA_CH6_AL2_READ_ADDR_MSB    _u(31)
+#define DMA_CH6_AL2_READ_ADDR_LSB    _u(0)
+#define DMA_CH6_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 6 WRITE_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ac)
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET  "-"
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_AL3_CTRL
+// Description : Alias for channel 6 CTRL register
+#define DMA_CH6_AL3_CTRL_OFFSET _u(0x000001b0)
+#define DMA_CH6_AL3_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH6_AL3_CTRL_RESET  "-"
+#define DMA_CH6_AL3_CTRL_MSB    _u(31)
+#define DMA_CH6_AL3_CTRL_LSB    _u(0)
+#define DMA_CH6_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_AL3_WRITE_ADDR
+// Description : Alias for channel 6 WRITE_ADDR register
+#define DMA_CH6_AL3_WRITE_ADDR_OFFSET _u(0x000001b4)
+#define DMA_CH6_AL3_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH6_AL3_WRITE_ADDR_RESET  "-"
+#define DMA_CH6_AL3_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH6_AL3_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_AL3_TRANS_COUNT
+// Description : Alias for channel 6 TRANS_COUNT register
+#define DMA_CH6_AL3_TRANS_COUNT_OFFSET _u(0x000001b8)
+#define DMA_CH6_AL3_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH6_AL3_TRANS_COUNT_RESET  "-"
+#define DMA_CH6_AL3_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH6_AL3_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH6_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 6 READ_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001bc)
+#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH6_AL3_READ_ADDR_TRIG_RESET  "-"
+#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_READ_ADDR
+// Description : DMA Channel 7 Read Address pointer
+//               This register updates automatically each time a read completes.
+//               The current value is the next address to be read by this
+//               channel.
+#define DMA_CH7_READ_ADDR_OFFSET _u(0x000001c0)
+#define DMA_CH7_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH7_READ_ADDR_RESET  _u(0x00000000)
+#define DMA_CH7_READ_ADDR_MSB    _u(31)
+#define DMA_CH7_READ_ADDR_LSB    _u(0)
+#define DMA_CH7_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_WRITE_ADDR
+// Description : DMA Channel 7 Write Address pointer
+//               This register updates automatically each time a write
+//               completes. The current value is the next address to be written
+//               by this channel.
+#define DMA_CH7_WRITE_ADDR_OFFSET _u(0x000001c4)
+#define DMA_CH7_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH7_WRITE_ADDR_RESET  _u(0x00000000)
+#define DMA_CH7_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH7_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH7_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_TRANS_COUNT
+// Description : DMA Channel 7 Transfer Count
+//               Program the number of bus transfers a channel will perform
+//               before halting. Note that, if transfers are larger than one
+//               byte in size, this is not equal to the number of bytes
+//               transferred (see CTRL_DATA_SIZE).
+//
+//               When the channel is active, reading this register shows the
+//               number of transfers remaining, updating automatically each time
+//               a write transfer completes.
+//
+//               Writing this register sets the RELOAD value for the transfer
+//               counter. Each time this channel is triggered, the RELOAD value
+//               is copied into the live transfer counter. The channel can be
+//               started multiple times, and will perform the same number of
+//               transfers each time, as programmed by most recent write.
+//
+//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+//               is used as a trigger, the written value is used immediately as
+//               the length of the new transfer sequence, as well as being
+//               written to RELOAD.
+#define DMA_CH7_TRANS_COUNT_OFFSET _u(0x000001c8)
+#define DMA_CH7_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH7_TRANS_COUNT_RESET  _u(0x00000000)
+#define DMA_CH7_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH7_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH7_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_CTRL_TRIG
+// Description : DMA Channel 7 Control and Status
+#define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc)
+#define DMA_CH7_CTRL_TRIG_BITS   _u(0xe1ffffff)
+#define DMA_CH7_CTRL_TRIG_RESET  _u(0x00003800)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+//               halts when it encounters any bus error, and always raises its
+//               channel IRQ flag.
+#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET  _u(0x0)
+#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS   _u(0x80000000)
+#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB    _u(31)
+#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB    _u(31)
+#define DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+//               clear.
+//               READ_ADDR shows the approximate address where the bus error was
+//               encountered (will not to be earlier, or more than 3 transfers
+//               later)
+#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET  _u(0x0)
+#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS   _u(0x40000000)
+#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB    _u(30)
+#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB    _u(30)
+#define DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+//               clear.
+//               WRITE_ADDR shows the approximate address where the bus error
+//               was encountered (will not to be earlier, or more than 5
+//               transfers later)
+#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET  _u(0x0)
+#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS   _u(0x20000000)
+#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB    _u(29)
+#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB    _u(29)
+#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+//               sequence, and low when the last transfer of that sequence
+//               completes. Clearing EN while BUSY is high pauses the channel,
+//               and BUSY will stay high while paused.
+//
+//               To terminate a sequence early (and clear the BUSY flag), see
+//               CHAN_ABORT.
+#define DMA_CH7_CTRL_TRIG_BUSY_RESET  _u(0x0)
+#define DMA_CH7_CTRL_TRIG_BUSY_BITS   _u(0x01000000)
+#define DMA_CH7_CTRL_TRIG_BUSY_MSB    _u(24)
+#define DMA_CH7_CTRL_TRIG_BUSY_LSB    _u(24)
+#define DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+//               hardware, and each transfer will advance the state of the
+//               checksum. This only applies if the sniff hardware is enabled,
+//               and has this channel selected.
+//
+//               This allows checksum to be enabled or disabled on a
+//               per-control- block basis.
+#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET  _u(0x0)
+#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS   _u(0x00800000)
+#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB    _u(23)
+#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB    _u(23)
+#define DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+//               For byte data, this has no effect. For halfword data, the two
+//               bytes of each halfword are swapped. For word data, the four
+//               bytes of each word are swapped to reverse order.
+#define DMA_CH7_CTRL_TRIG_BSWAP_RESET  _u(0x0)
+#define DMA_CH7_CTRL_TRIG_BSWAP_BITS   _u(0x00400000)
+#define DMA_CH7_CTRL_TRIG_BSWAP_MSB    _u(22)
+#define DMA_CH7_CTRL_TRIG_BSWAP_LSB    _u(22)
+#define DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+//               every transfer block. Instead, an IRQ is raised when NULL is
+//               written to a trigger register, indicating the end of a control
+//               block chain.
+//
+//               This reduces the number of interrupts to be serviced by the CPU
+//               when transferring a DMA chain of many small control blocks.
+#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET  _u(0x0)
+#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS   _u(0x00200000)
+#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB    _u(21)
+#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB    _u(21)
+#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+//               The channel uses the transfer request signal to pace its data
+//               transfer rate. Sources for TREQ signals are internal (TIMERS)
+//               or external (DREQ, a Data Request from the system).
+//               0x0 to 0x3a -> select DREQ n as TREQ
+//               0x3b -> Select Timer 0 as TREQ
+//               0x3c -> Select Timer 1 as TREQ
+//               0x3d -> Select Timer 2 as TREQ (Optional)
+//               0x3e -> Select Timer 3 as TREQ (Optional)
+//               0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET           _u(0x00)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS            _u(0x001f8000)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB             _u(20)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB             _u(15)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS          "RW"
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    _u(0x3b)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    _u(0x3c)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    _u(0x3d)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    _u(0x3e)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+//               channel)_.
+//               Reset value is equal to channel number (7).
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET  _u(0x7)
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
+//               boundary. If 1, write addresses are wrapped.
+#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET  _u(0x0)
+#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS   _u(0x00000400)
+#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB    _u(10)
+#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB    _u(10)
+#define DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+//               0, only the lower n bits of the address will change. This wraps
+//               the address on a (1 << n) byte boundary, facilitating access to
+//               naturally-aligned ring buffers.
+//
+//               Ring sizes between 2 and 32768 bytes are possible. This can
+//               apply to either read or write addresses, based on value of
+//               RING_SEL.
+//               0x0 -> RING_NONE
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET           _u(0x0)
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS            _u(0x000003c0)
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB             _u(9)
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB             _u(6)
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS          "RW"
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+//               each write is directed to the same, initial address.
+//
+//               Generally this should be disabled for memory-to-peripheral
+//               transfers.
+#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET  _u(0x0)
+#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS   _u(0x00000020)
+#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB    _u(5)
+#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB    _u(5)
+#define DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+//               each read is directed to the same, initial address.
+//
+//               Generally this should be disabled for peripheral-to-memory
+//               transfers.
+#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET  _u(0x0)
+#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS   _u(0x00000010)
+#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB    _u(4)
+#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB    _u(4)
+#define DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+//               with each transfer.
+//               0x0 -> SIZE_BYTE
+//               0x1 -> SIZE_HALFWORD
+//               0x2 -> SIZE_WORD
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET               _u(0x0)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS                _u(0x0000000c)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB                 _u(3)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB                 _u(2)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS              "RW"
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     _u(0x0)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+//               scheduling: in each scheduling round, all high priority
+//               channels are considered first, and then only a single low
+//               priority channel, before returning to the high priority
+//               channels.
+//
+//               This only affects the order in which the DMA schedules
+//               channels. The DMA's bus priority is not changed. If the DMA is
+//               not saturated then a low priority channel will see no loss of
+//               throughput.
+#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET  _u(0x0)
+#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS   _u(0x00000002)
+#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB    _u(1)
+#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB    _u(1)
+#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH7_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+//               When 1, the channel will respond to triggering events, which
+//               will cause it to become BUSY and start transferring data. When
+//               0, the channel will ignore triggers, stop issuing transfers,
+//               and pause the current transfer sequence (i.e. BUSY will remain
+//               high if already high)
+#define DMA_CH7_CTRL_TRIG_EN_RESET  _u(0x0)
+#define DMA_CH7_CTRL_TRIG_EN_BITS   _u(0x00000001)
+#define DMA_CH7_CTRL_TRIG_EN_MSB    _u(0)
+#define DMA_CH7_CTRL_TRIG_EN_LSB    _u(0)
+#define DMA_CH7_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_AL1_CTRL
+// Description : Alias for channel 7 CTRL register
+#define DMA_CH7_AL1_CTRL_OFFSET _u(0x000001d0)
+#define DMA_CH7_AL1_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH7_AL1_CTRL_RESET  "-"
+#define DMA_CH7_AL1_CTRL_MSB    _u(31)
+#define DMA_CH7_AL1_CTRL_LSB    _u(0)
+#define DMA_CH7_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_AL1_READ_ADDR
+// Description : Alias for channel 7 READ_ADDR register
+#define DMA_CH7_AL1_READ_ADDR_OFFSET _u(0x000001d4)
+#define DMA_CH7_AL1_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH7_AL1_READ_ADDR_RESET  "-"
+#define DMA_CH7_AL1_READ_ADDR_MSB    _u(31)
+#define DMA_CH7_AL1_READ_ADDR_LSB    _u(0)
+#define DMA_CH7_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_AL1_WRITE_ADDR
+// Description : Alias for channel 7 WRITE_ADDR register
+#define DMA_CH7_AL1_WRITE_ADDR_OFFSET _u(0x000001d8)
+#define DMA_CH7_AL1_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH7_AL1_WRITE_ADDR_RESET  "-"
+#define DMA_CH7_AL1_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH7_AL1_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 7 TRANS_COUNT register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000001dc)
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET  "-"
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_AL2_CTRL
+// Description : Alias for channel 7 CTRL register
+#define DMA_CH7_AL2_CTRL_OFFSET _u(0x000001e0)
+#define DMA_CH7_AL2_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH7_AL2_CTRL_RESET  "-"
+#define DMA_CH7_AL2_CTRL_MSB    _u(31)
+#define DMA_CH7_AL2_CTRL_LSB    _u(0)
+#define DMA_CH7_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_AL2_TRANS_COUNT
+// Description : Alias for channel 7 TRANS_COUNT register
+#define DMA_CH7_AL2_TRANS_COUNT_OFFSET _u(0x000001e4)
+#define DMA_CH7_AL2_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH7_AL2_TRANS_COUNT_RESET  "-"
+#define DMA_CH7_AL2_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH7_AL2_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_AL2_READ_ADDR
+// Description : Alias for channel 7 READ_ADDR register
+#define DMA_CH7_AL2_READ_ADDR_OFFSET _u(0x000001e8)
+#define DMA_CH7_AL2_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH7_AL2_READ_ADDR_RESET  "-"
+#define DMA_CH7_AL2_READ_ADDR_MSB    _u(31)
+#define DMA_CH7_AL2_READ_ADDR_LSB    _u(0)
+#define DMA_CH7_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 7 WRITE_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ec)
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET  "-"
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_AL3_CTRL
+// Description : Alias for channel 7 CTRL register
+#define DMA_CH7_AL3_CTRL_OFFSET _u(0x000001f0)
+#define DMA_CH7_AL3_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH7_AL3_CTRL_RESET  "-"
+#define DMA_CH7_AL3_CTRL_MSB    _u(31)
+#define DMA_CH7_AL3_CTRL_LSB    _u(0)
+#define DMA_CH7_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_AL3_WRITE_ADDR
+// Description : Alias for channel 7 WRITE_ADDR register
+#define DMA_CH7_AL3_WRITE_ADDR_OFFSET _u(0x000001f4)
+#define DMA_CH7_AL3_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH7_AL3_WRITE_ADDR_RESET  "-"
+#define DMA_CH7_AL3_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH7_AL3_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_AL3_TRANS_COUNT
+// Description : Alias for channel 7 TRANS_COUNT register
+#define DMA_CH7_AL3_TRANS_COUNT_OFFSET _u(0x000001f8)
+#define DMA_CH7_AL3_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH7_AL3_TRANS_COUNT_RESET  "-"
+#define DMA_CH7_AL3_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH7_AL3_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH7_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 7 READ_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001fc)
+#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH7_AL3_READ_ADDR_TRIG_RESET  "-"
+#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_READ_ADDR
+// Description : DMA Channel 8 Read Address pointer
+//               This register updates automatically each time a read completes.
+//               The current value is the next address to be read by this
+//               channel.
+#define DMA_CH8_READ_ADDR_OFFSET _u(0x00000200)
+#define DMA_CH8_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH8_READ_ADDR_RESET  _u(0x00000000)
+#define DMA_CH8_READ_ADDR_MSB    _u(31)
+#define DMA_CH8_READ_ADDR_LSB    _u(0)
+#define DMA_CH8_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_WRITE_ADDR
+// Description : DMA Channel 8 Write Address pointer
+//               This register updates automatically each time a write
+//               completes. The current value is the next address to be written
+//               by this channel.
+#define DMA_CH8_WRITE_ADDR_OFFSET _u(0x00000204)
+#define DMA_CH8_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH8_WRITE_ADDR_RESET  _u(0x00000000)
+#define DMA_CH8_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH8_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH8_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_TRANS_COUNT
+// Description : DMA Channel 8 Transfer Count
+//               Program the number of bus transfers a channel will perform
+//               before halting. Note that, if transfers are larger than one
+//               byte in size, this is not equal to the number of bytes
+//               transferred (see CTRL_DATA_SIZE).
+//
+//               When the channel is active, reading this register shows the
+//               number of transfers remaining, updating automatically each time
+//               a write transfer completes.
+//
+//               Writing this register sets the RELOAD value for the transfer
+//               counter. Each time this channel is triggered, the RELOAD value
+//               is copied into the live transfer counter. The channel can be
+//               started multiple times, and will perform the same number of
+//               transfers each time, as programmed by most recent write.
+//
+//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+//               is used as a trigger, the written value is used immediately as
+//               the length of the new transfer sequence, as well as being
+//               written to RELOAD.
+#define DMA_CH8_TRANS_COUNT_OFFSET _u(0x00000208)
+#define DMA_CH8_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH8_TRANS_COUNT_RESET  _u(0x00000000)
+#define DMA_CH8_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH8_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH8_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_CTRL_TRIG
+// Description : DMA Channel 8 Control and Status
+#define DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c)
+#define DMA_CH8_CTRL_TRIG_BITS   _u(0xe1ffffff)
+#define DMA_CH8_CTRL_TRIG_RESET  _u(0x00004000)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+//               halts when it encounters any bus error, and always raises its
+//               channel IRQ flag.
+#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET  _u(0x0)
+#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS   _u(0x80000000)
+#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB    _u(31)
+#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB    _u(31)
+#define DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+//               clear.
+//               READ_ADDR shows the approximate address where the bus error was
+//               encountered (will not to be earlier, or more than 3 transfers
+//               later)
+#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET  _u(0x0)
+#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS   _u(0x40000000)
+#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB    _u(30)
+#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB    _u(30)
+#define DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+//               clear.
+//               WRITE_ADDR shows the approximate address where the bus error
+//               was encountered (will not to be earlier, or more than 5
+//               transfers later)
+#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET  _u(0x0)
+#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS   _u(0x20000000)
+#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB    _u(29)
+#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB    _u(29)
+#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+//               sequence, and low when the last transfer of that sequence
+//               completes. Clearing EN while BUSY is high pauses the channel,
+//               and BUSY will stay high while paused.
+//
+//               To terminate a sequence early (and clear the BUSY flag), see
+//               CHAN_ABORT.
+#define DMA_CH8_CTRL_TRIG_BUSY_RESET  _u(0x0)
+#define DMA_CH8_CTRL_TRIG_BUSY_BITS   _u(0x01000000)
+#define DMA_CH8_CTRL_TRIG_BUSY_MSB    _u(24)
+#define DMA_CH8_CTRL_TRIG_BUSY_LSB    _u(24)
+#define DMA_CH8_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+//               hardware, and each transfer will advance the state of the
+//               checksum. This only applies if the sniff hardware is enabled,
+//               and has this channel selected.
+//
+//               This allows checksum to be enabled or disabled on a
+//               per-control- block basis.
+#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET  _u(0x0)
+#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS   _u(0x00800000)
+#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB    _u(23)
+#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB    _u(23)
+#define DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+//               For byte data, this has no effect. For halfword data, the two
+//               bytes of each halfword are swapped. For word data, the four
+//               bytes of each word are swapped to reverse order.
+#define DMA_CH8_CTRL_TRIG_BSWAP_RESET  _u(0x0)
+#define DMA_CH8_CTRL_TRIG_BSWAP_BITS   _u(0x00400000)
+#define DMA_CH8_CTRL_TRIG_BSWAP_MSB    _u(22)
+#define DMA_CH8_CTRL_TRIG_BSWAP_LSB    _u(22)
+#define DMA_CH8_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+//               every transfer block. Instead, an IRQ is raised when NULL is
+//               written to a trigger register, indicating the end of a control
+//               block chain.
+//
+//               This reduces the number of interrupts to be serviced by the CPU
+//               when transferring a DMA chain of many small control blocks.
+#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET  _u(0x0)
+#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS   _u(0x00200000)
+#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB    _u(21)
+#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB    _u(21)
+#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+//               The channel uses the transfer request signal to pace its data
+//               transfer rate. Sources for TREQ signals are internal (TIMERS)
+//               or external (DREQ, a Data Request from the system).
+//               0x0 to 0x3a -> select DREQ n as TREQ
+//               0x3b -> Select Timer 0 as TREQ
+//               0x3c -> Select Timer 1 as TREQ
+//               0x3d -> Select Timer 2 as TREQ (Optional)
+//               0x3e -> Select Timer 3 as TREQ (Optional)
+//               0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET           _u(0x00)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS            _u(0x001f8000)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB             _u(20)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB             _u(15)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS          "RW"
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    _u(0x3b)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    _u(0x3c)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    _u(0x3d)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    _u(0x3e)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+//               channel)_.
+//               Reset value is equal to channel number (8).
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET  _u(0x8)
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
+//               boundary. If 1, write addresses are wrapped.
+#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET  _u(0x0)
+#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS   _u(0x00000400)
+#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB    _u(10)
+#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB    _u(10)
+#define DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+//               0, only the lower n bits of the address will change. This wraps
+//               the address on a (1 << n) byte boundary, facilitating access to
+//               naturally-aligned ring buffers.
+//
+//               Ring sizes between 2 and 32768 bytes are possible. This can
+//               apply to either read or write addresses, based on value of
+//               RING_SEL.
+//               0x0 -> RING_NONE
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET           _u(0x0)
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS            _u(0x000003c0)
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB             _u(9)
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB             _u(6)
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS          "RW"
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+//               each write is directed to the same, initial address.
+//
+//               Generally this should be disabled for memory-to-peripheral
+//               transfers.
+#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET  _u(0x0)
+#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS   _u(0x00000020)
+#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB    _u(5)
+#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB    _u(5)
+#define DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+//               each read is directed to the same, initial address.
+//
+//               Generally this should be disabled for peripheral-to-memory
+//               transfers.
+#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET  _u(0x0)
+#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS   _u(0x00000010)
+#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB    _u(4)
+#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB    _u(4)
+#define DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+//               with each transfer.
+//               0x0 -> SIZE_BYTE
+//               0x1 -> SIZE_HALFWORD
+//               0x2 -> SIZE_WORD
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET               _u(0x0)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS                _u(0x0000000c)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB                 _u(3)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB                 _u(2)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS              "RW"
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     _u(0x0)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+//               scheduling: in each scheduling round, all high priority
+//               channels are considered first, and then only a single low
+//               priority channel, before returning to the high priority
+//               channels.
+//
+//               This only affects the order in which the DMA schedules
+//               channels. The DMA's bus priority is not changed. If the DMA is
+//               not saturated then a low priority channel will see no loss of
+//               throughput.
+#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET  _u(0x0)
+#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS   _u(0x00000002)
+#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB    _u(1)
+#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB    _u(1)
+#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH8_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+//               When 1, the channel will respond to triggering events, which
+//               will cause it to become BUSY and start transferring data. When
+//               0, the channel will ignore triggers, stop issuing transfers,
+//               and pause the current transfer sequence (i.e. BUSY will remain
+//               high if already high)
+#define DMA_CH8_CTRL_TRIG_EN_RESET  _u(0x0)
+#define DMA_CH8_CTRL_TRIG_EN_BITS   _u(0x00000001)
+#define DMA_CH8_CTRL_TRIG_EN_MSB    _u(0)
+#define DMA_CH8_CTRL_TRIG_EN_LSB    _u(0)
+#define DMA_CH8_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_AL1_CTRL
+// Description : Alias for channel 8 CTRL register
+#define DMA_CH8_AL1_CTRL_OFFSET _u(0x00000210)
+#define DMA_CH8_AL1_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH8_AL1_CTRL_RESET  "-"
+#define DMA_CH8_AL1_CTRL_MSB    _u(31)
+#define DMA_CH8_AL1_CTRL_LSB    _u(0)
+#define DMA_CH8_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_AL1_READ_ADDR
+// Description : Alias for channel 8 READ_ADDR register
+#define DMA_CH8_AL1_READ_ADDR_OFFSET _u(0x00000214)
+#define DMA_CH8_AL1_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH8_AL1_READ_ADDR_RESET  "-"
+#define DMA_CH8_AL1_READ_ADDR_MSB    _u(31)
+#define DMA_CH8_AL1_READ_ADDR_LSB    _u(0)
+#define DMA_CH8_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_AL1_WRITE_ADDR
+// Description : Alias for channel 8 WRITE_ADDR register
+#define DMA_CH8_AL1_WRITE_ADDR_OFFSET _u(0x00000218)
+#define DMA_CH8_AL1_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH8_AL1_WRITE_ADDR_RESET  "-"
+#define DMA_CH8_AL1_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH8_AL1_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 8 TRANS_COUNT register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000021c)
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET  "-"
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_AL2_CTRL
+// Description : Alias for channel 8 CTRL register
+#define DMA_CH8_AL2_CTRL_OFFSET _u(0x00000220)
+#define DMA_CH8_AL2_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH8_AL2_CTRL_RESET  "-"
+#define DMA_CH8_AL2_CTRL_MSB    _u(31)
+#define DMA_CH8_AL2_CTRL_LSB    _u(0)
+#define DMA_CH8_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_AL2_TRANS_COUNT
+// Description : Alias for channel 8 TRANS_COUNT register
+#define DMA_CH8_AL2_TRANS_COUNT_OFFSET _u(0x00000224)
+#define DMA_CH8_AL2_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH8_AL2_TRANS_COUNT_RESET  "-"
+#define DMA_CH8_AL2_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH8_AL2_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_AL2_READ_ADDR
+// Description : Alias for channel 8 READ_ADDR register
+#define DMA_CH8_AL2_READ_ADDR_OFFSET _u(0x00000228)
+#define DMA_CH8_AL2_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH8_AL2_READ_ADDR_RESET  "-"
+#define DMA_CH8_AL2_READ_ADDR_MSB    _u(31)
+#define DMA_CH8_AL2_READ_ADDR_LSB    _u(0)
+#define DMA_CH8_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 8 WRITE_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000022c)
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET  "-"
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_AL3_CTRL
+// Description : Alias for channel 8 CTRL register
+#define DMA_CH8_AL3_CTRL_OFFSET _u(0x00000230)
+#define DMA_CH8_AL3_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH8_AL3_CTRL_RESET  "-"
+#define DMA_CH8_AL3_CTRL_MSB    _u(31)
+#define DMA_CH8_AL3_CTRL_LSB    _u(0)
+#define DMA_CH8_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_AL3_WRITE_ADDR
+// Description : Alias for channel 8 WRITE_ADDR register
+#define DMA_CH8_AL3_WRITE_ADDR_OFFSET _u(0x00000234)
+#define DMA_CH8_AL3_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH8_AL3_WRITE_ADDR_RESET  "-"
+#define DMA_CH8_AL3_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH8_AL3_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_AL3_TRANS_COUNT
+// Description : Alias for channel 8 TRANS_COUNT register
+#define DMA_CH8_AL3_TRANS_COUNT_OFFSET _u(0x00000238)
+#define DMA_CH8_AL3_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH8_AL3_TRANS_COUNT_RESET  "-"
+#define DMA_CH8_AL3_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH8_AL3_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH8_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 8 READ_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000023c)
+#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH8_AL3_READ_ADDR_TRIG_RESET  "-"
+#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_READ_ADDR
+// Description : DMA Channel 9 Read Address pointer
+//               This register updates automatically each time a read completes.
+//               The current value is the next address to be read by this
+//               channel.
+#define DMA_CH9_READ_ADDR_OFFSET _u(0x00000240)
+#define DMA_CH9_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH9_READ_ADDR_RESET  _u(0x00000000)
+#define DMA_CH9_READ_ADDR_MSB    _u(31)
+#define DMA_CH9_READ_ADDR_LSB    _u(0)
+#define DMA_CH9_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_WRITE_ADDR
+// Description : DMA Channel 9 Write Address pointer
+//               This register updates automatically each time a write
+//               completes. The current value is the next address to be written
+//               by this channel.
+#define DMA_CH9_WRITE_ADDR_OFFSET _u(0x00000244)
+#define DMA_CH9_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH9_WRITE_ADDR_RESET  _u(0x00000000)
+#define DMA_CH9_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH9_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH9_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_TRANS_COUNT
+// Description : DMA Channel 9 Transfer Count
+//               Program the number of bus transfers a channel will perform
+//               before halting. Note that, if transfers are larger than one
+//               byte in size, this is not equal to the number of bytes
+//               transferred (see CTRL_DATA_SIZE).
+//
+//               When the channel is active, reading this register shows the
+//               number of transfers remaining, updating automatically each time
+//               a write transfer completes.
+//
+//               Writing this register sets the RELOAD value for the transfer
+//               counter. Each time this channel is triggered, the RELOAD value
+//               is copied into the live transfer counter. The channel can be
+//               started multiple times, and will perform the same number of
+//               transfers each time, as programmed by most recent write.
+//
+//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+//               is used as a trigger, the written value is used immediately as
+//               the length of the new transfer sequence, as well as being
+//               written to RELOAD.
+#define DMA_CH9_TRANS_COUNT_OFFSET _u(0x00000248)
+#define DMA_CH9_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH9_TRANS_COUNT_RESET  _u(0x00000000)
+#define DMA_CH9_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH9_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH9_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_CTRL_TRIG
+// Description : DMA Channel 9 Control and Status
+#define DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c)
+#define DMA_CH9_CTRL_TRIG_BITS   _u(0xe1ffffff)
+#define DMA_CH9_CTRL_TRIG_RESET  _u(0x00004800)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+//               halts when it encounters any bus error, and always raises its
+//               channel IRQ flag.
+#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET  _u(0x0)
+#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS   _u(0x80000000)
+#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB    _u(31)
+#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB    _u(31)
+#define DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+//               clear.
+//               READ_ADDR shows the approximate address where the bus error was
+//               encountered (will not to be earlier, or more than 3 transfers
+//               later)
+#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET  _u(0x0)
+#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS   _u(0x40000000)
+#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB    _u(30)
+#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB    _u(30)
+#define DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+//               clear.
+//               WRITE_ADDR shows the approximate address where the bus error
+//               was encountered (will not to be earlier, or more than 5
+//               transfers later)
+#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET  _u(0x0)
+#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS   _u(0x20000000)
+#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB    _u(29)
+#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB    _u(29)
+#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+//               sequence, and low when the last transfer of that sequence
+//               completes. Clearing EN while BUSY is high pauses the channel,
+//               and BUSY will stay high while paused.
+//
+//               To terminate a sequence early (and clear the BUSY flag), see
+//               CHAN_ABORT.
+#define DMA_CH9_CTRL_TRIG_BUSY_RESET  _u(0x0)
+#define DMA_CH9_CTRL_TRIG_BUSY_BITS   _u(0x01000000)
+#define DMA_CH9_CTRL_TRIG_BUSY_MSB    _u(24)
+#define DMA_CH9_CTRL_TRIG_BUSY_LSB    _u(24)
+#define DMA_CH9_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+//               hardware, and each transfer will advance the state of the
+//               checksum. This only applies if the sniff hardware is enabled,
+//               and has this channel selected.
+//
+//               This allows checksum to be enabled or disabled on a
+//               per-control- block basis.
+#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET  _u(0x0)
+#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS   _u(0x00800000)
+#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB    _u(23)
+#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB    _u(23)
+#define DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+//               For byte data, this has no effect. For halfword data, the two
+//               bytes of each halfword are swapped. For word data, the four
+//               bytes of each word are swapped to reverse order.
+#define DMA_CH9_CTRL_TRIG_BSWAP_RESET  _u(0x0)
+#define DMA_CH9_CTRL_TRIG_BSWAP_BITS   _u(0x00400000)
+#define DMA_CH9_CTRL_TRIG_BSWAP_MSB    _u(22)
+#define DMA_CH9_CTRL_TRIG_BSWAP_LSB    _u(22)
+#define DMA_CH9_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+//               every transfer block. Instead, an IRQ is raised when NULL is
+//               written to a trigger register, indicating the end of a control
+//               block chain.
+//
+//               This reduces the number of interrupts to be serviced by the CPU
+//               when transferring a DMA chain of many small control blocks.
+#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET  _u(0x0)
+#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS   _u(0x00200000)
+#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB    _u(21)
+#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB    _u(21)
+#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+//               The channel uses the transfer request signal to pace its data
+//               transfer rate. Sources for TREQ signals are internal (TIMERS)
+//               or external (DREQ, a Data Request from the system).
+//               0x0 to 0x3a -> select DREQ n as TREQ
+//               0x3b -> Select Timer 0 as TREQ
+//               0x3c -> Select Timer 1 as TREQ
+//               0x3d -> Select Timer 2 as TREQ (Optional)
+//               0x3e -> Select Timer 3 as TREQ (Optional)
+//               0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET           _u(0x00)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS            _u(0x001f8000)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB             _u(20)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB             _u(15)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS          "RW"
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    _u(0x3b)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    _u(0x3c)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    _u(0x3d)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    _u(0x3e)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+//               channel)_.
+//               Reset value is equal to channel number (9).
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET  _u(0x9)
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
+//               boundary. If 1, write addresses are wrapped.
+#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET  _u(0x0)
+#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS   _u(0x00000400)
+#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB    _u(10)
+#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB    _u(10)
+#define DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+//               0, only the lower n bits of the address will change. This wraps
+//               the address on a (1 << n) byte boundary, facilitating access to
+//               naturally-aligned ring buffers.
+//
+//               Ring sizes between 2 and 32768 bytes are possible. This can
+//               apply to either read or write addresses, based on value of
+//               RING_SEL.
+//               0x0 -> RING_NONE
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET           _u(0x0)
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS            _u(0x000003c0)
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB             _u(9)
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB             _u(6)
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS          "RW"
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+//               each write is directed to the same, initial address.
+//
+//               Generally this should be disabled for memory-to-peripheral
+//               transfers.
+#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET  _u(0x0)
+#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS   _u(0x00000020)
+#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB    _u(5)
+#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB    _u(5)
+#define DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+//               each read is directed to the same, initial address.
+//
+//               Generally this should be disabled for peripheral-to-memory
+//               transfers.
+#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET  _u(0x0)
+#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS   _u(0x00000010)
+#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB    _u(4)
+#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB    _u(4)
+#define DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+//               with each transfer.
+//               0x0 -> SIZE_BYTE
+//               0x1 -> SIZE_HALFWORD
+//               0x2 -> SIZE_WORD
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET               _u(0x0)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS                _u(0x0000000c)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB                 _u(3)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB                 _u(2)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS              "RW"
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     _u(0x0)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+//               scheduling: in each scheduling round, all high priority
+//               channels are considered first, and then only a single low
+//               priority channel, before returning to the high priority
+//               channels.
+//
+//               This only affects the order in which the DMA schedules
+//               channels. The DMA's bus priority is not changed. If the DMA is
+//               not saturated then a low priority channel will see no loss of
+//               throughput.
+#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET  _u(0x0)
+#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS   _u(0x00000002)
+#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB    _u(1)
+#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB    _u(1)
+#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH9_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+//               When 1, the channel will respond to triggering events, which
+//               will cause it to become BUSY and start transferring data. When
+//               0, the channel will ignore triggers, stop issuing transfers,
+//               and pause the current transfer sequence (i.e. BUSY will remain
+//               high if already high)
+#define DMA_CH9_CTRL_TRIG_EN_RESET  _u(0x0)
+#define DMA_CH9_CTRL_TRIG_EN_BITS   _u(0x00000001)
+#define DMA_CH9_CTRL_TRIG_EN_MSB    _u(0)
+#define DMA_CH9_CTRL_TRIG_EN_LSB    _u(0)
+#define DMA_CH9_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_AL1_CTRL
+// Description : Alias for channel 9 CTRL register
+#define DMA_CH9_AL1_CTRL_OFFSET _u(0x00000250)
+#define DMA_CH9_AL1_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH9_AL1_CTRL_RESET  "-"
+#define DMA_CH9_AL1_CTRL_MSB    _u(31)
+#define DMA_CH9_AL1_CTRL_LSB    _u(0)
+#define DMA_CH9_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_AL1_READ_ADDR
+// Description : Alias for channel 9 READ_ADDR register
+#define DMA_CH9_AL1_READ_ADDR_OFFSET _u(0x00000254)
+#define DMA_CH9_AL1_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH9_AL1_READ_ADDR_RESET  "-"
+#define DMA_CH9_AL1_READ_ADDR_MSB    _u(31)
+#define DMA_CH9_AL1_READ_ADDR_LSB    _u(0)
+#define DMA_CH9_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_AL1_WRITE_ADDR
+// Description : Alias for channel 9 WRITE_ADDR register
+#define DMA_CH9_AL1_WRITE_ADDR_OFFSET _u(0x00000258)
+#define DMA_CH9_AL1_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH9_AL1_WRITE_ADDR_RESET  "-"
+#define DMA_CH9_AL1_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH9_AL1_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 9 TRANS_COUNT register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000025c)
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET  "-"
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_AL2_CTRL
+// Description : Alias for channel 9 CTRL register
+#define DMA_CH9_AL2_CTRL_OFFSET _u(0x00000260)
+#define DMA_CH9_AL2_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH9_AL2_CTRL_RESET  "-"
+#define DMA_CH9_AL2_CTRL_MSB    _u(31)
+#define DMA_CH9_AL2_CTRL_LSB    _u(0)
+#define DMA_CH9_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_AL2_TRANS_COUNT
+// Description : Alias for channel 9 TRANS_COUNT register
+#define DMA_CH9_AL2_TRANS_COUNT_OFFSET _u(0x00000264)
+#define DMA_CH9_AL2_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH9_AL2_TRANS_COUNT_RESET  "-"
+#define DMA_CH9_AL2_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH9_AL2_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_AL2_READ_ADDR
+// Description : Alias for channel 9 READ_ADDR register
+#define DMA_CH9_AL2_READ_ADDR_OFFSET _u(0x00000268)
+#define DMA_CH9_AL2_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH9_AL2_READ_ADDR_RESET  "-"
+#define DMA_CH9_AL2_READ_ADDR_MSB    _u(31)
+#define DMA_CH9_AL2_READ_ADDR_LSB    _u(0)
+#define DMA_CH9_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 9 WRITE_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000026c)
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET  "-"
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_AL3_CTRL
+// Description : Alias for channel 9 CTRL register
+#define DMA_CH9_AL3_CTRL_OFFSET _u(0x00000270)
+#define DMA_CH9_AL3_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH9_AL3_CTRL_RESET  "-"
+#define DMA_CH9_AL3_CTRL_MSB    _u(31)
+#define DMA_CH9_AL3_CTRL_LSB    _u(0)
+#define DMA_CH9_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_AL3_WRITE_ADDR
+// Description : Alias for channel 9 WRITE_ADDR register
+#define DMA_CH9_AL3_WRITE_ADDR_OFFSET _u(0x00000274)
+#define DMA_CH9_AL3_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH9_AL3_WRITE_ADDR_RESET  "-"
+#define DMA_CH9_AL3_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH9_AL3_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_AL3_TRANS_COUNT
+// Description : Alias for channel 9 TRANS_COUNT register
+#define DMA_CH9_AL3_TRANS_COUNT_OFFSET _u(0x00000278)
+#define DMA_CH9_AL3_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH9_AL3_TRANS_COUNT_RESET  "-"
+#define DMA_CH9_AL3_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH9_AL3_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH9_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 9 READ_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000027c)
+#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH9_AL3_READ_ADDR_TRIG_RESET  "-"
+#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_READ_ADDR
+// Description : DMA Channel 10 Read Address pointer
+//               This register updates automatically each time a read completes.
+//               The current value is the next address to be read by this
+//               channel.
+#define DMA_CH10_READ_ADDR_OFFSET _u(0x00000280)
+#define DMA_CH10_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH10_READ_ADDR_RESET  _u(0x00000000)
+#define DMA_CH10_READ_ADDR_MSB    _u(31)
+#define DMA_CH10_READ_ADDR_LSB    _u(0)
+#define DMA_CH10_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_WRITE_ADDR
+// Description : DMA Channel 10 Write Address pointer
+//               This register updates automatically each time a write
+//               completes. The current value is the next address to be written
+//               by this channel.
+#define DMA_CH10_WRITE_ADDR_OFFSET _u(0x00000284)
+#define DMA_CH10_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH10_WRITE_ADDR_RESET  _u(0x00000000)
+#define DMA_CH10_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH10_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH10_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_TRANS_COUNT
+// Description : DMA Channel 10 Transfer Count
+//               Program the number of bus transfers a channel will perform
+//               before halting. Note that, if transfers are larger than one
+//               byte in size, this is not equal to the number of bytes
+//               transferred (see CTRL_DATA_SIZE).
+//
+//               When the channel is active, reading this register shows the
+//               number of transfers remaining, updating automatically each time
+//               a write transfer completes.
+//
+//               Writing this register sets the RELOAD value for the transfer
+//               counter. Each time this channel is triggered, the RELOAD value
+//               is copied into the live transfer counter. The channel can be
+//               started multiple times, and will perform the same number of
+//               transfers each time, as programmed by most recent write.
+//
+//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+//               is used as a trigger, the written value is used immediately as
+//               the length of the new transfer sequence, as well as being
+//               written to RELOAD.
+#define DMA_CH10_TRANS_COUNT_OFFSET _u(0x00000288)
+#define DMA_CH10_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH10_TRANS_COUNT_RESET  _u(0x00000000)
+#define DMA_CH10_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH10_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH10_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_CTRL_TRIG
+// Description : DMA Channel 10 Control and Status
+#define DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c)
+#define DMA_CH10_CTRL_TRIG_BITS   _u(0xe1ffffff)
+#define DMA_CH10_CTRL_TRIG_RESET  _u(0x00005000)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+//               halts when it encounters any bus error, and always raises its
+//               channel IRQ flag.
+#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET  _u(0x0)
+#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS   _u(0x80000000)
+#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB    _u(31)
+#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB    _u(31)
+#define DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+//               clear.
+//               READ_ADDR shows the approximate address where the bus error was
+//               encountered (will not to be earlier, or more than 3 transfers
+//               later)
+#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET  _u(0x0)
+#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS   _u(0x40000000)
+#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB    _u(30)
+#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB    _u(30)
+#define DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+//               clear.
+//               WRITE_ADDR shows the approximate address where the bus error
+//               was encountered (will not to be earlier, or more than 5
+//               transfers later)
+#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET  _u(0x0)
+#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS   _u(0x20000000)
+#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB    _u(29)
+#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB    _u(29)
+#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+//               sequence, and low when the last transfer of that sequence
+//               completes. Clearing EN while BUSY is high pauses the channel,
+//               and BUSY will stay high while paused.
+//
+//               To terminate a sequence early (and clear the BUSY flag), see
+//               CHAN_ABORT.
+#define DMA_CH10_CTRL_TRIG_BUSY_RESET  _u(0x0)
+#define DMA_CH10_CTRL_TRIG_BUSY_BITS   _u(0x01000000)
+#define DMA_CH10_CTRL_TRIG_BUSY_MSB    _u(24)
+#define DMA_CH10_CTRL_TRIG_BUSY_LSB    _u(24)
+#define DMA_CH10_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+//               hardware, and each transfer will advance the state of the
+//               checksum. This only applies if the sniff hardware is enabled,
+//               and has this channel selected.
+//
+//               This allows checksum to be enabled or disabled on a
+//               per-control- block basis.
+#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET  _u(0x0)
+#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS   _u(0x00800000)
+#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB    _u(23)
+#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB    _u(23)
+#define DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+//               For byte data, this has no effect. For halfword data, the two
+//               bytes of each halfword are swapped. For word data, the four
+//               bytes of each word are swapped to reverse order.
+#define DMA_CH10_CTRL_TRIG_BSWAP_RESET  _u(0x0)
+#define DMA_CH10_CTRL_TRIG_BSWAP_BITS   _u(0x00400000)
+#define DMA_CH10_CTRL_TRIG_BSWAP_MSB    _u(22)
+#define DMA_CH10_CTRL_TRIG_BSWAP_LSB    _u(22)
+#define DMA_CH10_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+//               every transfer block. Instead, an IRQ is raised when NULL is
+//               written to a trigger register, indicating the end of a control
+//               block chain.
+//
+//               This reduces the number of interrupts to be serviced by the CPU
+//               when transferring a DMA chain of many small control blocks.
+#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET  _u(0x0)
+#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS   _u(0x00200000)
+#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB    _u(21)
+#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB    _u(21)
+#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+//               The channel uses the transfer request signal to pace its data
+//               transfer rate. Sources for TREQ signals are internal (TIMERS)
+//               or external (DREQ, a Data Request from the system).
+//               0x0 to 0x3a -> select DREQ n as TREQ
+//               0x3b -> Select Timer 0 as TREQ
+//               0x3c -> Select Timer 1 as TREQ
+//               0x3d -> Select Timer 2 as TREQ (Optional)
+//               0x3e -> Select Timer 3 as TREQ (Optional)
+//               0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET           _u(0x00)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS            _u(0x001f8000)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB             _u(20)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB             _u(15)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS          "RW"
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    _u(0x3b)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    _u(0x3c)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    _u(0x3d)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    _u(0x3e)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+//               channel)_.
+//               Reset value is equal to channel number (10).
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET  _u(0xa)
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
+//               boundary. If 1, write addresses are wrapped.
+#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET  _u(0x0)
+#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS   _u(0x00000400)
+#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB    _u(10)
+#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB    _u(10)
+#define DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+//               0, only the lower n bits of the address will change. This wraps
+//               the address on a (1 << n) byte boundary, facilitating access to
+//               naturally-aligned ring buffers.
+//
+//               Ring sizes between 2 and 32768 bytes are possible. This can
+//               apply to either read or write addresses, based on value of
+//               RING_SEL.
+//               0x0 -> RING_NONE
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET           _u(0x0)
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS            _u(0x000003c0)
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB             _u(9)
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB             _u(6)
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS          "RW"
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+//               each write is directed to the same, initial address.
+//
+//               Generally this should be disabled for memory-to-peripheral
+//               transfers.
+#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET  _u(0x0)
+#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS   _u(0x00000020)
+#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB    _u(5)
+#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB    _u(5)
+#define DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+//               each read is directed to the same, initial address.
+//
+//               Generally this should be disabled for peripheral-to-memory
+//               transfers.
+#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET  _u(0x0)
+#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS   _u(0x00000010)
+#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB    _u(4)
+#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB    _u(4)
+#define DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+//               with each transfer.
+//               0x0 -> SIZE_BYTE
+//               0x1 -> SIZE_HALFWORD
+//               0x2 -> SIZE_WORD
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET               _u(0x0)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS                _u(0x0000000c)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB                 _u(3)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB                 _u(2)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS              "RW"
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     _u(0x0)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+//               scheduling: in each scheduling round, all high priority
+//               channels are considered first, and then only a single low
+//               priority channel, before returning to the high priority
+//               channels.
+//
+//               This only affects the order in which the DMA schedules
+//               channels. The DMA's bus priority is not changed. If the DMA is
+//               not saturated then a low priority channel will see no loss of
+//               throughput.
+#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET  _u(0x0)
+#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS   _u(0x00000002)
+#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB    _u(1)
+#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB    _u(1)
+#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH10_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+//               When 1, the channel will respond to triggering events, which
+//               will cause it to become BUSY and start transferring data. When
+//               0, the channel will ignore triggers, stop issuing transfers,
+//               and pause the current transfer sequence (i.e. BUSY will remain
+//               high if already high)
+#define DMA_CH10_CTRL_TRIG_EN_RESET  _u(0x0)
+#define DMA_CH10_CTRL_TRIG_EN_BITS   _u(0x00000001)
+#define DMA_CH10_CTRL_TRIG_EN_MSB    _u(0)
+#define DMA_CH10_CTRL_TRIG_EN_LSB    _u(0)
+#define DMA_CH10_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_AL1_CTRL
+// Description : Alias for channel 10 CTRL register
+#define DMA_CH10_AL1_CTRL_OFFSET _u(0x00000290)
+#define DMA_CH10_AL1_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH10_AL1_CTRL_RESET  "-"
+#define DMA_CH10_AL1_CTRL_MSB    _u(31)
+#define DMA_CH10_AL1_CTRL_LSB    _u(0)
+#define DMA_CH10_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_AL1_READ_ADDR
+// Description : Alias for channel 10 READ_ADDR register
+#define DMA_CH10_AL1_READ_ADDR_OFFSET _u(0x00000294)
+#define DMA_CH10_AL1_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH10_AL1_READ_ADDR_RESET  "-"
+#define DMA_CH10_AL1_READ_ADDR_MSB    _u(31)
+#define DMA_CH10_AL1_READ_ADDR_LSB    _u(0)
+#define DMA_CH10_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_AL1_WRITE_ADDR
+// Description : Alias for channel 10 WRITE_ADDR register
+#define DMA_CH10_AL1_WRITE_ADDR_OFFSET _u(0x00000298)
+#define DMA_CH10_AL1_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH10_AL1_WRITE_ADDR_RESET  "-"
+#define DMA_CH10_AL1_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH10_AL1_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 10 TRANS_COUNT register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000029c)
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET  "-"
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_AL2_CTRL
+// Description : Alias for channel 10 CTRL register
+#define DMA_CH10_AL2_CTRL_OFFSET _u(0x000002a0)
+#define DMA_CH10_AL2_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH10_AL2_CTRL_RESET  "-"
+#define DMA_CH10_AL2_CTRL_MSB    _u(31)
+#define DMA_CH10_AL2_CTRL_LSB    _u(0)
+#define DMA_CH10_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_AL2_TRANS_COUNT
+// Description : Alias for channel 10 TRANS_COUNT register
+#define DMA_CH10_AL2_TRANS_COUNT_OFFSET _u(0x000002a4)
+#define DMA_CH10_AL2_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH10_AL2_TRANS_COUNT_RESET  "-"
+#define DMA_CH10_AL2_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH10_AL2_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_AL2_READ_ADDR
+// Description : Alias for channel 10 READ_ADDR register
+#define DMA_CH10_AL2_READ_ADDR_OFFSET _u(0x000002a8)
+#define DMA_CH10_AL2_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH10_AL2_READ_ADDR_RESET  "-"
+#define DMA_CH10_AL2_READ_ADDR_MSB    _u(31)
+#define DMA_CH10_AL2_READ_ADDR_LSB    _u(0)
+#define DMA_CH10_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 10 WRITE_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ac)
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET  "-"
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_AL3_CTRL
+// Description : Alias for channel 10 CTRL register
+#define DMA_CH10_AL3_CTRL_OFFSET _u(0x000002b0)
+#define DMA_CH10_AL3_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH10_AL3_CTRL_RESET  "-"
+#define DMA_CH10_AL3_CTRL_MSB    _u(31)
+#define DMA_CH10_AL3_CTRL_LSB    _u(0)
+#define DMA_CH10_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_AL3_WRITE_ADDR
+// Description : Alias for channel 10 WRITE_ADDR register
+#define DMA_CH10_AL3_WRITE_ADDR_OFFSET _u(0x000002b4)
+#define DMA_CH10_AL3_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH10_AL3_WRITE_ADDR_RESET  "-"
+#define DMA_CH10_AL3_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH10_AL3_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_AL3_TRANS_COUNT
+// Description : Alias for channel 10 TRANS_COUNT register
+#define DMA_CH10_AL3_TRANS_COUNT_OFFSET _u(0x000002b8)
+#define DMA_CH10_AL3_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH10_AL3_TRANS_COUNT_RESET  "-"
+#define DMA_CH10_AL3_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH10_AL3_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH10_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 10 READ_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002bc)
+#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH10_AL3_READ_ADDR_TRIG_RESET  "-"
+#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_READ_ADDR
+// Description : DMA Channel 11 Read Address pointer
+//               This register updates automatically each time a read completes.
+//               The current value is the next address to be read by this
+//               channel.
+#define DMA_CH11_READ_ADDR_OFFSET _u(0x000002c0)
+#define DMA_CH11_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH11_READ_ADDR_RESET  _u(0x00000000)
+#define DMA_CH11_READ_ADDR_MSB    _u(31)
+#define DMA_CH11_READ_ADDR_LSB    _u(0)
+#define DMA_CH11_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_WRITE_ADDR
+// Description : DMA Channel 11 Write Address pointer
+//               This register updates automatically each time a write
+//               completes. The current value is the next address to be written
+//               by this channel.
+#define DMA_CH11_WRITE_ADDR_OFFSET _u(0x000002c4)
+#define DMA_CH11_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH11_WRITE_ADDR_RESET  _u(0x00000000)
+#define DMA_CH11_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH11_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH11_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_TRANS_COUNT
+// Description : DMA Channel 11 Transfer Count
+//               Program the number of bus transfers a channel will perform
+//               before halting. Note that, if transfers are larger than one
+//               byte in size, this is not equal to the number of bytes
+//               transferred (see CTRL_DATA_SIZE).
+//
+//               When the channel is active, reading this register shows the
+//               number of transfers remaining, updating automatically each time
+//               a write transfer completes.
+//
+//               Writing this register sets the RELOAD value for the transfer
+//               counter. Each time this channel is triggered, the RELOAD value
+//               is copied into the live transfer counter. The channel can be
+//               started multiple times, and will perform the same number of
+//               transfers each time, as programmed by most recent write.
+//
+//               The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+//               is used as a trigger, the written value is used immediately as
+//               the length of the new transfer sequence, as well as being
+//               written to RELOAD.
+#define DMA_CH11_TRANS_COUNT_OFFSET _u(0x000002c8)
+#define DMA_CH11_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH11_TRANS_COUNT_RESET  _u(0x00000000)
+#define DMA_CH11_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH11_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH11_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_CTRL_TRIG
+// Description : DMA Channel 11 Control and Status
+#define DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc)
+#define DMA_CH11_CTRL_TRIG_BITS   _u(0xe1ffffff)
+#define DMA_CH11_CTRL_TRIG_RESET  _u(0x00005800)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+//               halts when it encounters any bus error, and always raises its
+//               channel IRQ flag.
+#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET  _u(0x0)
+#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS   _u(0x80000000)
+#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB    _u(31)
+#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB    _u(31)
+#define DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+//               clear.
+//               READ_ADDR shows the approximate address where the bus error was
+//               encountered (will not to be earlier, or more than 3 transfers
+//               later)
+#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET  _u(0x0)
+#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS   _u(0x40000000)
+#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB    _u(30)
+#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB    _u(30)
+#define DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+//               clear.
+//               WRITE_ADDR shows the approximate address where the bus error
+//               was encountered (will not to be earlier, or more than 5
+//               transfers later)
+#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET  _u(0x0)
+#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS   _u(0x20000000)
+#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB    _u(29)
+#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB    _u(29)
+#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+//               sequence, and low when the last transfer of that sequence
+//               completes. Clearing EN while BUSY is high pauses the channel,
+//               and BUSY will stay high while paused.
+//
+//               To terminate a sequence early (and clear the BUSY flag), see
+//               CHAN_ABORT.
+#define DMA_CH11_CTRL_TRIG_BUSY_RESET  _u(0x0)
+#define DMA_CH11_CTRL_TRIG_BUSY_BITS   _u(0x01000000)
+#define DMA_CH11_CTRL_TRIG_BUSY_MSB    _u(24)
+#define DMA_CH11_CTRL_TRIG_BUSY_LSB    _u(24)
+#define DMA_CH11_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+//               hardware, and each transfer will advance the state of the
+//               checksum. This only applies if the sniff hardware is enabled,
+//               and has this channel selected.
+//
+//               This allows checksum to be enabled or disabled on a
+//               per-control- block basis.
+#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET  _u(0x0)
+#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS   _u(0x00800000)
+#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB    _u(23)
+#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB    _u(23)
+#define DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+//               For byte data, this has no effect. For halfword data, the two
+//               bytes of each halfword are swapped. For word data, the four
+//               bytes of each word are swapped to reverse order.
+#define DMA_CH11_CTRL_TRIG_BSWAP_RESET  _u(0x0)
+#define DMA_CH11_CTRL_TRIG_BSWAP_BITS   _u(0x00400000)
+#define DMA_CH11_CTRL_TRIG_BSWAP_MSB    _u(22)
+#define DMA_CH11_CTRL_TRIG_BSWAP_LSB    _u(22)
+#define DMA_CH11_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+//               every transfer block. Instead, an IRQ is raised when NULL is
+//               written to a trigger register, indicating the end of a control
+//               block chain.
+//
+//               This reduces the number of interrupts to be serviced by the CPU
+//               when transferring a DMA chain of many small control blocks.
+#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET  _u(0x0)
+#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS   _u(0x00200000)
+#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB    _u(21)
+#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB    _u(21)
+#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+//               The channel uses the transfer request signal to pace its data
+//               transfer rate. Sources for TREQ signals are internal (TIMERS)
+//               or external (DREQ, a Data Request from the system).
+//               0x0 to 0x3a -> select DREQ n as TREQ
+//               0x3b -> Select Timer 0 as TREQ
+//               0x3c -> Select Timer 1 as TREQ
+//               0x3d -> Select Timer 2 as TREQ (Optional)
+//               0x3e -> Select Timer 3 as TREQ (Optional)
+//               0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET           _u(0x00)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS            _u(0x001f8000)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB             _u(20)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB             _u(15)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS          "RW"
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0    _u(0x3b)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1    _u(0x3c)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2    _u(0x3d)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3    _u(0x3e)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+//               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+//               channel)_.
+//               Reset value is equal to channel number (11).
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET  _u(0xb)
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+//               If 0, read addresses are wrapped on a (1 << RING_SIZE)
+//               boundary. If 1, write addresses are wrapped.
+#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET  _u(0x0)
+#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS   _u(0x00000400)
+#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB    _u(10)
+#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB    _u(10)
+#define DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+//               0, only the lower n bits of the address will change. This wraps
+//               the address on a (1 << n) byte boundary, facilitating access to
+//               naturally-aligned ring buffers.
+//
+//               Ring sizes between 2 and 32768 bytes are possible. This can
+//               apply to either read or write addresses, based on value of
+//               RING_SEL.
+//               0x0 -> RING_NONE
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET           _u(0x0)
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS            _u(0x000003c0)
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB             _u(9)
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB             _u(6)
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS          "RW"
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+//               each write is directed to the same, initial address.
+//
+//               Generally this should be disabled for memory-to-peripheral
+//               transfers.
+#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET  _u(0x0)
+#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS   _u(0x00000020)
+#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB    _u(5)
+#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB    _u(5)
+#define DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+//               each read is directed to the same, initial address.
+//
+//               Generally this should be disabled for peripheral-to-memory
+//               transfers.
+#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET  _u(0x0)
+#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS   _u(0x00000010)
+#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB    _u(4)
+#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB    _u(4)
+#define DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+//               READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+//               with each transfer.
+//               0x0 -> SIZE_BYTE
+//               0x1 -> SIZE_HALFWORD
+//               0x2 -> SIZE_WORD
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET               _u(0x0)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS                _u(0x0000000c)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB                 _u(3)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB                 _u(2)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS              "RW"
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE     _u(0x0)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD     _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+//               scheduling: in each scheduling round, all high priority
+//               channels are considered first, and then only a single low
+//               priority channel, before returning to the high priority
+//               channels.
+//
+//               This only affects the order in which the DMA schedules
+//               channels. The DMA's bus priority is not changed. If the DMA is
+//               not saturated then a low priority channel will see no loss of
+//               throughput.
+#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET  _u(0x0)
+#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS   _u(0x00000002)
+#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB    _u(1)
+#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB    _u(1)
+#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_CH11_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+//               When 1, the channel will respond to triggering events, which
+//               will cause it to become BUSY and start transferring data. When
+//               0, the channel will ignore triggers, stop issuing transfers,
+//               and pause the current transfer sequence (i.e. BUSY will remain
+//               high if already high)
+#define DMA_CH11_CTRL_TRIG_EN_RESET  _u(0x0)
+#define DMA_CH11_CTRL_TRIG_EN_BITS   _u(0x00000001)
+#define DMA_CH11_CTRL_TRIG_EN_MSB    _u(0)
+#define DMA_CH11_CTRL_TRIG_EN_LSB    _u(0)
+#define DMA_CH11_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_AL1_CTRL
+// Description : Alias for channel 11 CTRL register
+#define DMA_CH11_AL1_CTRL_OFFSET _u(0x000002d0)
+#define DMA_CH11_AL1_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH11_AL1_CTRL_RESET  "-"
+#define DMA_CH11_AL1_CTRL_MSB    _u(31)
+#define DMA_CH11_AL1_CTRL_LSB    _u(0)
+#define DMA_CH11_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_AL1_READ_ADDR
+// Description : Alias for channel 11 READ_ADDR register
+#define DMA_CH11_AL1_READ_ADDR_OFFSET _u(0x000002d4)
+#define DMA_CH11_AL1_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH11_AL1_READ_ADDR_RESET  "-"
+#define DMA_CH11_AL1_READ_ADDR_MSB    _u(31)
+#define DMA_CH11_AL1_READ_ADDR_LSB    _u(0)
+#define DMA_CH11_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_AL1_WRITE_ADDR
+// Description : Alias for channel 11 WRITE_ADDR register
+#define DMA_CH11_AL1_WRITE_ADDR_OFFSET _u(0x000002d8)
+#define DMA_CH11_AL1_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH11_AL1_WRITE_ADDR_RESET  "-"
+#define DMA_CH11_AL1_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH11_AL1_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 11 TRANS_COUNT register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000002dc)
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET  "-"
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB    _u(31)
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB    _u(0)
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_AL2_CTRL
+// Description : Alias for channel 11 CTRL register
+#define DMA_CH11_AL2_CTRL_OFFSET _u(0x000002e0)
+#define DMA_CH11_AL2_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH11_AL2_CTRL_RESET  "-"
+#define DMA_CH11_AL2_CTRL_MSB    _u(31)
+#define DMA_CH11_AL2_CTRL_LSB    _u(0)
+#define DMA_CH11_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_AL2_TRANS_COUNT
+// Description : Alias for channel 11 TRANS_COUNT register
+#define DMA_CH11_AL2_TRANS_COUNT_OFFSET _u(0x000002e4)
+#define DMA_CH11_AL2_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH11_AL2_TRANS_COUNT_RESET  "-"
+#define DMA_CH11_AL2_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH11_AL2_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_AL2_READ_ADDR
+// Description : Alias for channel 11 READ_ADDR register
+#define DMA_CH11_AL2_READ_ADDR_OFFSET _u(0x000002e8)
+#define DMA_CH11_AL2_READ_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH11_AL2_READ_ADDR_RESET  "-"
+#define DMA_CH11_AL2_READ_ADDR_MSB    _u(31)
+#define DMA_CH11_AL2_READ_ADDR_LSB    _u(0)
+#define DMA_CH11_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 11 WRITE_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ec)
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET  "-"
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_AL3_CTRL
+// Description : Alias for channel 11 CTRL register
+#define DMA_CH11_AL3_CTRL_OFFSET _u(0x000002f0)
+#define DMA_CH11_AL3_CTRL_BITS   _u(0xffffffff)
+#define DMA_CH11_AL3_CTRL_RESET  "-"
+#define DMA_CH11_AL3_CTRL_MSB    _u(31)
+#define DMA_CH11_AL3_CTRL_LSB    _u(0)
+#define DMA_CH11_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_AL3_WRITE_ADDR
+// Description : Alias for channel 11 WRITE_ADDR register
+#define DMA_CH11_AL3_WRITE_ADDR_OFFSET _u(0x000002f4)
+#define DMA_CH11_AL3_WRITE_ADDR_BITS   _u(0xffffffff)
+#define DMA_CH11_AL3_WRITE_ADDR_RESET  "-"
+#define DMA_CH11_AL3_WRITE_ADDR_MSB    _u(31)
+#define DMA_CH11_AL3_WRITE_ADDR_LSB    _u(0)
+#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_AL3_TRANS_COUNT
+// Description : Alias for channel 11 TRANS_COUNT register
+#define DMA_CH11_AL3_TRANS_COUNT_OFFSET _u(0x000002f8)
+#define DMA_CH11_AL3_TRANS_COUNT_BITS   _u(0xffffffff)
+#define DMA_CH11_AL3_TRANS_COUNT_RESET  "-"
+#define DMA_CH11_AL3_TRANS_COUNT_MSB    _u(31)
+#define DMA_CH11_AL3_TRANS_COUNT_LSB    _u(0)
+#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_CH11_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 11 READ_ADDR register
+//               This is a trigger register (0xc). Writing a nonzero value will
+//               reload the channel counter and start the channel.
+#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002fc)
+#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS   _u(0xffffffff)
+#define DMA_CH11_AL3_READ_ADDR_TRIG_RESET  "-"
+#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB    _u(31)
+#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB    _u(0)
+#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_INTR
+// Description : Interrupt Status (raw)
+//               Raw interrupt status for DMA Channels 0..15. Bit n corresponds
+//               to channel n. Ignores any masking or forcing. Channel
+//               interrupts can be cleared by writing a bit mask to INTR, INTS0
+//               or INTS1.
+//
+//               Channel interrupts can be routed to either of two system-level
+//               IRQs based on INTE0 and INTE1.
+//
+//               This can be used vector different channel interrupts to
+//               different ISRs: this might be done to allow NVIC IRQ preemption
+//               for more time-critical channels, or to spread IRQ load across
+//               different cores.
+//
+//               It is also valid to ignore this behaviour and just use
+//               INTE0/INTS0/IRQ 0.
+#define DMA_INTR_OFFSET _u(0x00000400)
+#define DMA_INTR_BITS   _u(0x0000ffff)
+#define DMA_INTR_RESET  _u(0x00000000)
+#define DMA_INTR_MSB    _u(15)
+#define DMA_INTR_LSB    _u(0)
+#define DMA_INTR_ACCESS "RO"
+// =============================================================================
+// Register    : DMA_INTE0
+// Description : Interrupt Enables for IRQ 0
+//               Set bit n to pass interrupts from channel n to DMA IRQ 0.
+#define DMA_INTE0_OFFSET _u(0x00000404)
+#define DMA_INTE0_BITS   _u(0x0000ffff)
+#define DMA_INTE0_RESET  _u(0x00000000)
+#define DMA_INTE0_MSB    _u(15)
+#define DMA_INTE0_LSB    _u(0)
+#define DMA_INTE0_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_INTF0
+// Description : Force Interrupts
+//               Write 1s to force the corresponding bits in INTE0. The
+//               interrupt remains asserted until INTF0 is cleared.
+#define DMA_INTF0_OFFSET _u(0x00000408)
+#define DMA_INTF0_BITS   _u(0x0000ffff)
+#define DMA_INTF0_RESET  _u(0x00000000)
+#define DMA_INTF0_MSB    _u(15)
+#define DMA_INTF0_LSB    _u(0)
+#define DMA_INTF0_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_INTS0
+// Description : Interrupt Status for IRQ 0
+//               Indicates active channel interrupt requests which are currently
+//               causing IRQ 0 to be asserted.
+//               Channel interrupts can be cleared by writing a bit mask here.
+#define DMA_INTS0_OFFSET _u(0x0000040c)
+#define DMA_INTS0_BITS   _u(0x0000ffff)
+#define DMA_INTS0_RESET  _u(0x00000000)
+#define DMA_INTS0_MSB    _u(15)
+#define DMA_INTS0_LSB    _u(0)
+#define DMA_INTS0_ACCESS "WC"
+// =============================================================================
+// Register    : DMA_INTE1
+// Description : Interrupt Enables for IRQ 1
+//               Set bit n to pass interrupts from channel n to DMA IRQ 1.
+#define DMA_INTE1_OFFSET _u(0x00000414)
+#define DMA_INTE1_BITS   _u(0x0000ffff)
+#define DMA_INTE1_RESET  _u(0x00000000)
+#define DMA_INTE1_MSB    _u(15)
+#define DMA_INTE1_LSB    _u(0)
+#define DMA_INTE1_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_INTF1
+// Description : Force Interrupts for IRQ 1
+//               Write 1s to force the corresponding bits in INTE0. The
+//               interrupt remains asserted until INTF0 is cleared.
+#define DMA_INTF1_OFFSET _u(0x00000418)
+#define DMA_INTF1_BITS   _u(0x0000ffff)
+#define DMA_INTF1_RESET  _u(0x00000000)
+#define DMA_INTF1_MSB    _u(15)
+#define DMA_INTF1_LSB    _u(0)
+#define DMA_INTF1_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_INTS1
+// Description : Interrupt Status (masked) for IRQ 1
+//               Indicates active channel interrupt requests which are currently
+//               causing IRQ 1 to be asserted.
+//               Channel interrupts can be cleared by writing a bit mask here.
+#define DMA_INTS1_OFFSET _u(0x0000041c)
+#define DMA_INTS1_BITS   _u(0x0000ffff)
+#define DMA_INTS1_RESET  _u(0x00000000)
+#define DMA_INTS1_MSB    _u(15)
+#define DMA_INTS1_LSB    _u(0)
+#define DMA_INTS1_ACCESS "WC"
+// =============================================================================
+// Register    : DMA_TIMER0
+// Description : Pacing (X/Y) Fractional Timer
+//               The pacing timer produces TREQ assertions at a rate set by
+//               ((X/Y) * sys_clk). This equation is evaluated every sys_clk
+//               cycles and therefore can only generate TREQs at a rate of 1 per
+//               sys_clk (i.e. permanent TREQ) or less.
+#define DMA_TIMER0_OFFSET _u(0x00000420)
+#define DMA_TIMER0_BITS   _u(0xffffffff)
+#define DMA_TIMER0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : DMA_TIMER0_X
+// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
+//               fractional timer.
+#define DMA_TIMER0_X_RESET  _u(0x0000)
+#define DMA_TIMER0_X_BITS   _u(0xffff0000)
+#define DMA_TIMER0_X_MSB    _u(31)
+#define DMA_TIMER0_X_LSB    _u(16)
+#define DMA_TIMER0_X_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_TIMER0_Y
+// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
+//               fractional timer.
+#define DMA_TIMER0_Y_RESET  _u(0x0000)
+#define DMA_TIMER0_Y_BITS   _u(0x0000ffff)
+#define DMA_TIMER0_Y_MSB    _u(15)
+#define DMA_TIMER0_Y_LSB    _u(0)
+#define DMA_TIMER0_Y_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_TIMER1
+// Description : Pacing (X/Y) Fractional Timer
+//               The pacing timer produces TREQ assertions at a rate set by
+//               ((X/Y) * sys_clk). This equation is evaluated every sys_clk
+//               cycles and therefore can only generate TREQs at a rate of 1 per
+//               sys_clk (i.e. permanent TREQ) or less.
+#define DMA_TIMER1_OFFSET _u(0x00000424)
+#define DMA_TIMER1_BITS   _u(0xffffffff)
+#define DMA_TIMER1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : DMA_TIMER1_X
+// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
+//               fractional timer.
+#define DMA_TIMER1_X_RESET  _u(0x0000)
+#define DMA_TIMER1_X_BITS   _u(0xffff0000)
+#define DMA_TIMER1_X_MSB    _u(31)
+#define DMA_TIMER1_X_LSB    _u(16)
+#define DMA_TIMER1_X_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_TIMER1_Y
+// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
+//               fractional timer.
+#define DMA_TIMER1_Y_RESET  _u(0x0000)
+#define DMA_TIMER1_Y_BITS   _u(0x0000ffff)
+#define DMA_TIMER1_Y_MSB    _u(15)
+#define DMA_TIMER1_Y_LSB    _u(0)
+#define DMA_TIMER1_Y_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_TIMER2
+// Description : Pacing (X/Y) Fractional Timer
+//               The pacing timer produces TREQ assertions at a rate set by
+//               ((X/Y) * sys_clk). This equation is evaluated every sys_clk
+//               cycles and therefore can only generate TREQs at a rate of 1 per
+//               sys_clk (i.e. permanent TREQ) or less.
+#define DMA_TIMER2_OFFSET _u(0x00000428)
+#define DMA_TIMER2_BITS   _u(0xffffffff)
+#define DMA_TIMER2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : DMA_TIMER2_X
+// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
+//               fractional timer.
+#define DMA_TIMER2_X_RESET  _u(0x0000)
+#define DMA_TIMER2_X_BITS   _u(0xffff0000)
+#define DMA_TIMER2_X_MSB    _u(31)
+#define DMA_TIMER2_X_LSB    _u(16)
+#define DMA_TIMER2_X_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_TIMER2_Y
+// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
+//               fractional timer.
+#define DMA_TIMER2_Y_RESET  _u(0x0000)
+#define DMA_TIMER2_Y_BITS   _u(0x0000ffff)
+#define DMA_TIMER2_Y_MSB    _u(15)
+#define DMA_TIMER2_Y_LSB    _u(0)
+#define DMA_TIMER2_Y_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_TIMER3
+// Description : Pacing (X/Y) Fractional Timer
+//               The pacing timer produces TREQ assertions at a rate set by
+//               ((X/Y) * sys_clk). This equation is evaluated every sys_clk
+//               cycles and therefore can only generate TREQs at a rate of 1 per
+//               sys_clk (i.e. permanent TREQ) or less.
+#define DMA_TIMER3_OFFSET _u(0x0000042c)
+#define DMA_TIMER3_BITS   _u(0xffffffff)
+#define DMA_TIMER3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : DMA_TIMER3_X
+// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
+//               fractional timer.
+#define DMA_TIMER3_X_RESET  _u(0x0000)
+#define DMA_TIMER3_X_BITS   _u(0xffff0000)
+#define DMA_TIMER3_X_MSB    _u(31)
+#define DMA_TIMER3_X_LSB    _u(16)
+#define DMA_TIMER3_X_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_TIMER3_Y
+// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
+//               fractional timer.
+#define DMA_TIMER3_Y_RESET  _u(0x0000)
+#define DMA_TIMER3_Y_BITS   _u(0x0000ffff)
+#define DMA_TIMER3_Y_MSB    _u(15)
+#define DMA_TIMER3_Y_LSB    _u(0)
+#define DMA_TIMER3_Y_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_MULTI_CHAN_TRIGGER
+// Description : Trigger one or more channels simultaneously
+//               Each bit in this register corresponds to a DMA channel. Writing
+//               a 1 to the relevant bit is the same as writing to that
+//               channel's trigger register; the channel will start if it is
+//               currently enabled and not already busy.
+#define DMA_MULTI_CHAN_TRIGGER_OFFSET _u(0x00000430)
+#define DMA_MULTI_CHAN_TRIGGER_BITS   _u(0x0000ffff)
+#define DMA_MULTI_CHAN_TRIGGER_RESET  _u(0x00000000)
+#define DMA_MULTI_CHAN_TRIGGER_MSB    _u(15)
+#define DMA_MULTI_CHAN_TRIGGER_LSB    _u(0)
+#define DMA_MULTI_CHAN_TRIGGER_ACCESS "SC"
+// =============================================================================
+// Register    : DMA_SNIFF_CTRL
+// Description : Sniffer Control
+#define DMA_SNIFF_CTRL_OFFSET _u(0x00000434)
+#define DMA_SNIFF_CTRL_BITS   _u(0x00000fff)
+#define DMA_SNIFF_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : DMA_SNIFF_CTRL_OUT_INV
+// Description : If set, the result appears inverted (bitwise complement) when
+//               read. This does not affect the way the checksum is calculated;
+//               the result is transformed on-the-fly between the result
+//               register and the bus.
+#define DMA_SNIFF_CTRL_OUT_INV_RESET  _u(0x0)
+#define DMA_SNIFF_CTRL_OUT_INV_BITS   _u(0x00000800)
+#define DMA_SNIFF_CTRL_OUT_INV_MSB    _u(11)
+#define DMA_SNIFF_CTRL_OUT_INV_LSB    _u(11)
+#define DMA_SNIFF_CTRL_OUT_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_SNIFF_CTRL_OUT_REV
+// Description : If set, the result appears bit-reversed when read. This does
+//               not affect the way the checksum is calculated; the result is
+//               transformed on-the-fly between the result register and the bus.
+#define DMA_SNIFF_CTRL_OUT_REV_RESET  _u(0x0)
+#define DMA_SNIFF_CTRL_OUT_REV_BITS   _u(0x00000400)
+#define DMA_SNIFF_CTRL_OUT_REV_MSB    _u(10)
+#define DMA_SNIFF_CTRL_OUT_REV_LSB    _u(10)
+#define DMA_SNIFF_CTRL_OUT_REV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_SNIFF_CTRL_BSWAP
+// Description : Locally perform a byte reverse on the sniffed data, before
+//               feeding into checksum.
+//
+//               Note that the sniff hardware is downstream of the DMA channel
+//               byteswap performed in the read master: if channel CTRL_BSWAP
+//               and SNIFF_CTRL_BSWAP are both enabled, their effects cancel
+//               from the sniffer's point of view.
+#define DMA_SNIFF_CTRL_BSWAP_RESET  _u(0x0)
+#define DMA_SNIFF_CTRL_BSWAP_BITS   _u(0x00000200)
+#define DMA_SNIFF_CTRL_BSWAP_MSB    _u(9)
+#define DMA_SNIFF_CTRL_BSWAP_LSB    _u(9)
+#define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_SNIFF_CTRL_CALC
+// Description : 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial)
+//               0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit
+//               reversed data
+//               0x2 -> Calculate a CRC-16-CCITT
+//               0x3 -> Calculate a CRC-16-CCITT with bit reversed data
+//               0xe -> XOR reduction over all data. == 1 if the total 1
+//               population count is odd.
+//               0xf -> Calculate a simple 32-bit checksum (addition with a 32
+//               bit accumulator)
+#define DMA_SNIFF_CTRL_CALC_RESET        _u(0x0)
+#define DMA_SNIFF_CTRL_CALC_BITS         _u(0x000001e0)
+#define DMA_SNIFF_CTRL_CALC_MSB          _u(8)
+#define DMA_SNIFF_CTRL_CALC_LSB          _u(5)
+#define DMA_SNIFF_CTRL_CALC_ACCESS       "RW"
+#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32  _u(0x0)
+#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R _u(0x1)
+#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16  _u(0x2)
+#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R _u(0x3)
+#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN   _u(0xe)
+#define DMA_SNIFF_CTRL_CALC_VALUE_SUM    _u(0xf)
+// -----------------------------------------------------------------------------
+// Field       : DMA_SNIFF_CTRL_DMACH
+// Description : DMA channel for Sniffer to observe
+#define DMA_SNIFF_CTRL_DMACH_RESET  _u(0x0)
+#define DMA_SNIFF_CTRL_DMACH_BITS   _u(0x0000001e)
+#define DMA_SNIFF_CTRL_DMACH_MSB    _u(4)
+#define DMA_SNIFF_CTRL_DMACH_LSB    _u(1)
+#define DMA_SNIFF_CTRL_DMACH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : DMA_SNIFF_CTRL_EN
+// Description : Enable sniffer
+#define DMA_SNIFF_CTRL_EN_RESET  _u(0x0)
+#define DMA_SNIFF_CTRL_EN_BITS   _u(0x00000001)
+#define DMA_SNIFF_CTRL_EN_MSB    _u(0)
+#define DMA_SNIFF_CTRL_EN_LSB    _u(0)
+#define DMA_SNIFF_CTRL_EN_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_SNIFF_DATA
+// Description : Data accumulator for sniff hardware
+//               Write an initial seed value here before starting a DMA transfer
+//               on the channel indicated by SNIFF_CTRL_DMACH. The hardware will
+//               update this register each time it observes a read from the
+//               indicated channel. Once the channel completes, the final result
+//               can be read from this register.
+#define DMA_SNIFF_DATA_OFFSET _u(0x00000438)
+#define DMA_SNIFF_DATA_BITS   _u(0xffffffff)
+#define DMA_SNIFF_DATA_RESET  _u(0x00000000)
+#define DMA_SNIFF_DATA_MSB    _u(31)
+#define DMA_SNIFF_DATA_LSB    _u(0)
+#define DMA_SNIFF_DATA_ACCESS "RW"
+// =============================================================================
+// Register    : DMA_FIFO_LEVELS
+// Description : Debug RAF, WAF, TDF levels
+#define DMA_FIFO_LEVELS_OFFSET _u(0x00000440)
+#define DMA_FIFO_LEVELS_BITS   _u(0x00ffffff)
+#define DMA_FIFO_LEVELS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : DMA_FIFO_LEVELS_RAF_LVL
+// Description : Current Read-Address-FIFO fill level
+#define DMA_FIFO_LEVELS_RAF_LVL_RESET  _u(0x00)
+#define DMA_FIFO_LEVELS_RAF_LVL_BITS   _u(0x00ff0000)
+#define DMA_FIFO_LEVELS_RAF_LVL_MSB    _u(23)
+#define DMA_FIFO_LEVELS_RAF_LVL_LSB    _u(16)
+#define DMA_FIFO_LEVELS_RAF_LVL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_FIFO_LEVELS_WAF_LVL
+// Description : Current Write-Address-FIFO fill level
+#define DMA_FIFO_LEVELS_WAF_LVL_RESET  _u(0x00)
+#define DMA_FIFO_LEVELS_WAF_LVL_BITS   _u(0x0000ff00)
+#define DMA_FIFO_LEVELS_WAF_LVL_MSB    _u(15)
+#define DMA_FIFO_LEVELS_WAF_LVL_LSB    _u(8)
+#define DMA_FIFO_LEVELS_WAF_LVL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : DMA_FIFO_LEVELS_TDF_LVL
+// Description : Current Transfer-Data-FIFO fill level
+#define DMA_FIFO_LEVELS_TDF_LVL_RESET  _u(0x00)
+#define DMA_FIFO_LEVELS_TDF_LVL_BITS   _u(0x000000ff)
+#define DMA_FIFO_LEVELS_TDF_LVL_MSB    _u(7)
+#define DMA_FIFO_LEVELS_TDF_LVL_LSB    _u(0)
+#define DMA_FIFO_LEVELS_TDF_LVL_ACCESS "RO"
+// =============================================================================
+// Register    : DMA_CHAN_ABORT
+// Description : Abort an in-progress transfer sequence on one or more channels
+//               Each bit corresponds to a channel. Writing a 1 aborts whatever
+//               transfer sequence is in progress on that channel. The bit will
+//               remain high until any in-flight transfers have been flushed
+//               through the address and data FIFOs.
+//
+//               After writing, this register must be polled until it returns
+//               all-zero. Until this point, it is unsafe to restart the
+//               channel.
+#define DMA_CHAN_ABORT_OFFSET _u(0x00000444)
+#define DMA_CHAN_ABORT_BITS   _u(0x0000ffff)
+#define DMA_CHAN_ABORT_RESET  _u(0x00000000)
+#define DMA_CHAN_ABORT_MSB    _u(15)
+#define DMA_CHAN_ABORT_LSB    _u(0)
+#define DMA_CHAN_ABORT_ACCESS "SC"
+// =============================================================================
+// Register    : DMA_N_CHANNELS
+// Description : The number of channels this DMA instance is equipped with. This
+//               DMA supports up to 16 hardware channels, but can be configured
+//               with as few as one, to minimise silicon area.
+#define DMA_N_CHANNELS_OFFSET _u(0x00000448)
+#define DMA_N_CHANNELS_BITS   _u(0x0000001f)
+#define DMA_N_CHANNELS_RESET  "-"
+#define DMA_N_CHANNELS_MSB    _u(4)
+#define DMA_N_CHANNELS_LSB    _u(0)
+#define DMA_N_CHANNELS_ACCESS "RO"
+// =============================================================================
+// Register    : DMA_CH0_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+//               expects it can perform on the peripheral without
+//               overflow/underflow. Write any value: clears the counter, and
+//               cause channel to re-initiate DREQ handshake.
+#define DMA_CH0_DBG_CTDREQ_OFFSET _u(0x00000800)
+#define DMA_CH0_DBG_CTDREQ_BITS   _u(0x0000003f)
+#define DMA_CH0_DBG_CTDREQ_RESET  _u(0x00000000)
+#define DMA_CH0_DBG_CTDREQ_MSB    _u(5)
+#define DMA_CH0_DBG_CTDREQ_LSB    _u(0)
+#define DMA_CH0_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register    : DMA_CH0_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+//               of the next transfer
+#define DMA_CH0_DBG_TCR_OFFSET _u(0x00000804)
+#define DMA_CH0_DBG_TCR_BITS   _u(0xffffffff)
+#define DMA_CH0_DBG_TCR_RESET  _u(0x00000000)
+#define DMA_CH0_DBG_TCR_MSB    _u(31)
+#define DMA_CH0_DBG_TCR_LSB    _u(0)
+#define DMA_CH0_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register    : DMA_CH1_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+//               expects it can perform on the peripheral without
+//               overflow/underflow. Write any value: clears the counter, and
+//               cause channel to re-initiate DREQ handshake.
+#define DMA_CH1_DBG_CTDREQ_OFFSET _u(0x00000840)
+#define DMA_CH1_DBG_CTDREQ_BITS   _u(0x0000003f)
+#define DMA_CH1_DBG_CTDREQ_RESET  _u(0x00000000)
+#define DMA_CH1_DBG_CTDREQ_MSB    _u(5)
+#define DMA_CH1_DBG_CTDREQ_LSB    _u(0)
+#define DMA_CH1_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register    : DMA_CH1_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+//               of the next transfer
+#define DMA_CH1_DBG_TCR_OFFSET _u(0x00000844)
+#define DMA_CH1_DBG_TCR_BITS   _u(0xffffffff)
+#define DMA_CH1_DBG_TCR_RESET  _u(0x00000000)
+#define DMA_CH1_DBG_TCR_MSB    _u(31)
+#define DMA_CH1_DBG_TCR_LSB    _u(0)
+#define DMA_CH1_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register    : DMA_CH2_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+//               expects it can perform on the peripheral without
+//               overflow/underflow. Write any value: clears the counter, and
+//               cause channel to re-initiate DREQ handshake.
+#define DMA_CH2_DBG_CTDREQ_OFFSET _u(0x00000880)
+#define DMA_CH2_DBG_CTDREQ_BITS   _u(0x0000003f)
+#define DMA_CH2_DBG_CTDREQ_RESET  _u(0x00000000)
+#define DMA_CH2_DBG_CTDREQ_MSB    _u(5)
+#define DMA_CH2_DBG_CTDREQ_LSB    _u(0)
+#define DMA_CH2_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register    : DMA_CH2_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+//               of the next transfer
+#define DMA_CH2_DBG_TCR_OFFSET _u(0x00000884)
+#define DMA_CH2_DBG_TCR_BITS   _u(0xffffffff)
+#define DMA_CH2_DBG_TCR_RESET  _u(0x00000000)
+#define DMA_CH2_DBG_TCR_MSB    _u(31)
+#define DMA_CH2_DBG_TCR_LSB    _u(0)
+#define DMA_CH2_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register    : DMA_CH3_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+//               expects it can perform on the peripheral without
+//               overflow/underflow. Write any value: clears the counter, and
+//               cause channel to re-initiate DREQ handshake.
+#define DMA_CH3_DBG_CTDREQ_OFFSET _u(0x000008c0)
+#define DMA_CH3_DBG_CTDREQ_BITS   _u(0x0000003f)
+#define DMA_CH3_DBG_CTDREQ_RESET  _u(0x00000000)
+#define DMA_CH3_DBG_CTDREQ_MSB    _u(5)
+#define DMA_CH3_DBG_CTDREQ_LSB    _u(0)
+#define DMA_CH3_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register    : DMA_CH3_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+//               of the next transfer
+#define DMA_CH3_DBG_TCR_OFFSET _u(0x000008c4)
+#define DMA_CH3_DBG_TCR_BITS   _u(0xffffffff)
+#define DMA_CH3_DBG_TCR_RESET  _u(0x00000000)
+#define DMA_CH3_DBG_TCR_MSB    _u(31)
+#define DMA_CH3_DBG_TCR_LSB    _u(0)
+#define DMA_CH3_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register    : DMA_CH4_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+//               expects it can perform on the peripheral without
+//               overflow/underflow. Write any value: clears the counter, and
+//               cause channel to re-initiate DREQ handshake.
+#define DMA_CH4_DBG_CTDREQ_OFFSET _u(0x00000900)
+#define DMA_CH4_DBG_CTDREQ_BITS   _u(0x0000003f)
+#define DMA_CH4_DBG_CTDREQ_RESET  _u(0x00000000)
+#define DMA_CH4_DBG_CTDREQ_MSB    _u(5)
+#define DMA_CH4_DBG_CTDREQ_LSB    _u(0)
+#define DMA_CH4_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register    : DMA_CH4_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+//               of the next transfer
+#define DMA_CH4_DBG_TCR_OFFSET _u(0x00000904)
+#define DMA_CH4_DBG_TCR_BITS   _u(0xffffffff)
+#define DMA_CH4_DBG_TCR_RESET  _u(0x00000000)
+#define DMA_CH4_DBG_TCR_MSB    _u(31)
+#define DMA_CH4_DBG_TCR_LSB    _u(0)
+#define DMA_CH4_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register    : DMA_CH5_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+//               expects it can perform on the peripheral without
+//               overflow/underflow. Write any value: clears the counter, and
+//               cause channel to re-initiate DREQ handshake.
+#define DMA_CH5_DBG_CTDREQ_OFFSET _u(0x00000940)
+#define DMA_CH5_DBG_CTDREQ_BITS   _u(0x0000003f)
+#define DMA_CH5_DBG_CTDREQ_RESET  _u(0x00000000)
+#define DMA_CH5_DBG_CTDREQ_MSB    _u(5)
+#define DMA_CH5_DBG_CTDREQ_LSB    _u(0)
+#define DMA_CH5_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register    : DMA_CH5_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+//               of the next transfer
+#define DMA_CH5_DBG_TCR_OFFSET _u(0x00000944)
+#define DMA_CH5_DBG_TCR_BITS   _u(0xffffffff)
+#define DMA_CH5_DBG_TCR_RESET  _u(0x00000000)
+#define DMA_CH5_DBG_TCR_MSB    _u(31)
+#define DMA_CH5_DBG_TCR_LSB    _u(0)
+#define DMA_CH5_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register    : DMA_CH6_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+//               expects it can perform on the peripheral without
+//               overflow/underflow. Write any value: clears the counter, and
+//               cause channel to re-initiate DREQ handshake.
+#define DMA_CH6_DBG_CTDREQ_OFFSET _u(0x00000980)
+#define DMA_CH6_DBG_CTDREQ_BITS   _u(0x0000003f)
+#define DMA_CH6_DBG_CTDREQ_RESET  _u(0x00000000)
+#define DMA_CH6_DBG_CTDREQ_MSB    _u(5)
+#define DMA_CH6_DBG_CTDREQ_LSB    _u(0)
+#define DMA_CH6_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register    : DMA_CH6_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+//               of the next transfer
+#define DMA_CH6_DBG_TCR_OFFSET _u(0x00000984)
+#define DMA_CH6_DBG_TCR_BITS   _u(0xffffffff)
+#define DMA_CH6_DBG_TCR_RESET  _u(0x00000000)
+#define DMA_CH6_DBG_TCR_MSB    _u(31)
+#define DMA_CH6_DBG_TCR_LSB    _u(0)
+#define DMA_CH6_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register    : DMA_CH7_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+//               expects it can perform on the peripheral without
+//               overflow/underflow. Write any value: clears the counter, and
+//               cause channel to re-initiate DREQ handshake.
+#define DMA_CH7_DBG_CTDREQ_OFFSET _u(0x000009c0)
+#define DMA_CH7_DBG_CTDREQ_BITS   _u(0x0000003f)
+#define DMA_CH7_DBG_CTDREQ_RESET  _u(0x00000000)
+#define DMA_CH7_DBG_CTDREQ_MSB    _u(5)
+#define DMA_CH7_DBG_CTDREQ_LSB    _u(0)
+#define DMA_CH7_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register    : DMA_CH7_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+//               of the next transfer
+#define DMA_CH7_DBG_TCR_OFFSET _u(0x000009c4)
+#define DMA_CH7_DBG_TCR_BITS   _u(0xffffffff)
+#define DMA_CH7_DBG_TCR_RESET  _u(0x00000000)
+#define DMA_CH7_DBG_TCR_MSB    _u(31)
+#define DMA_CH7_DBG_TCR_LSB    _u(0)
+#define DMA_CH7_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register    : DMA_CH8_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+//               expects it can perform on the peripheral without
+//               overflow/underflow. Write any value: clears the counter, and
+//               cause channel to re-initiate DREQ handshake.
+#define DMA_CH8_DBG_CTDREQ_OFFSET _u(0x00000a00)
+#define DMA_CH8_DBG_CTDREQ_BITS   _u(0x0000003f)
+#define DMA_CH8_DBG_CTDREQ_RESET  _u(0x00000000)
+#define DMA_CH8_DBG_CTDREQ_MSB    _u(5)
+#define DMA_CH8_DBG_CTDREQ_LSB    _u(0)
+#define DMA_CH8_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register    : DMA_CH8_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+//               of the next transfer
+#define DMA_CH8_DBG_TCR_OFFSET _u(0x00000a04)
+#define DMA_CH8_DBG_TCR_BITS   _u(0xffffffff)
+#define DMA_CH8_DBG_TCR_RESET  _u(0x00000000)
+#define DMA_CH8_DBG_TCR_MSB    _u(31)
+#define DMA_CH8_DBG_TCR_LSB    _u(0)
+#define DMA_CH8_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register    : DMA_CH9_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+//               expects it can perform on the peripheral without
+//               overflow/underflow. Write any value: clears the counter, and
+//               cause channel to re-initiate DREQ handshake.
+#define DMA_CH9_DBG_CTDREQ_OFFSET _u(0x00000a40)
+#define DMA_CH9_DBG_CTDREQ_BITS   _u(0x0000003f)
+#define DMA_CH9_DBG_CTDREQ_RESET  _u(0x00000000)
+#define DMA_CH9_DBG_CTDREQ_MSB    _u(5)
+#define DMA_CH9_DBG_CTDREQ_LSB    _u(0)
+#define DMA_CH9_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register    : DMA_CH9_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+//               of the next transfer
+#define DMA_CH9_DBG_TCR_OFFSET _u(0x00000a44)
+#define DMA_CH9_DBG_TCR_BITS   _u(0xffffffff)
+#define DMA_CH9_DBG_TCR_RESET  _u(0x00000000)
+#define DMA_CH9_DBG_TCR_MSB    _u(31)
+#define DMA_CH9_DBG_TCR_LSB    _u(0)
+#define DMA_CH9_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register    : DMA_CH10_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+//               expects it can perform on the peripheral without
+//               overflow/underflow. Write any value: clears the counter, and
+//               cause channel to re-initiate DREQ handshake.
+#define DMA_CH10_DBG_CTDREQ_OFFSET _u(0x00000a80)
+#define DMA_CH10_DBG_CTDREQ_BITS   _u(0x0000003f)
+#define DMA_CH10_DBG_CTDREQ_RESET  _u(0x00000000)
+#define DMA_CH10_DBG_CTDREQ_MSB    _u(5)
+#define DMA_CH10_DBG_CTDREQ_LSB    _u(0)
+#define DMA_CH10_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register    : DMA_CH10_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+//               of the next transfer
+#define DMA_CH10_DBG_TCR_OFFSET _u(0x00000a84)
+#define DMA_CH10_DBG_TCR_BITS   _u(0xffffffff)
+#define DMA_CH10_DBG_TCR_RESET  _u(0x00000000)
+#define DMA_CH10_DBG_TCR_MSB    _u(31)
+#define DMA_CH10_DBG_TCR_LSB    _u(0)
+#define DMA_CH10_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register    : DMA_CH11_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+//               expects it can perform on the peripheral without
+//               overflow/underflow. Write any value: clears the counter, and
+//               cause channel to re-initiate DREQ handshake.
+#define DMA_CH11_DBG_CTDREQ_OFFSET _u(0x00000ac0)
+#define DMA_CH11_DBG_CTDREQ_BITS   _u(0x0000003f)
+#define DMA_CH11_DBG_CTDREQ_RESET  _u(0x00000000)
+#define DMA_CH11_DBG_CTDREQ_MSB    _u(5)
+#define DMA_CH11_DBG_CTDREQ_LSB    _u(0)
+#define DMA_CH11_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register    : DMA_CH11_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+//               of the next transfer
+#define DMA_CH11_DBG_TCR_OFFSET _u(0x00000ac4)
+#define DMA_CH11_DBG_TCR_BITS   _u(0xffffffff)
+#define DMA_CH11_DBG_TCR_RESET  _u(0x00000000)
+#define DMA_CH11_DBG_TCR_MSB    _u(31)
+#define DMA_CH11_DBG_TCR_LSB    _u(0)
+#define DMA_CH11_DBG_TCR_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_DMA_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/dreq.h b/src/rp2040/hardware_regs/include/hardware/regs/dreq.h
new file mode 100644
index 0000000..9de9dd5
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/dreq.h
@@ -0,0 +1,50 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _DREQ_H_
+#define _DREQ_H_
+
+#define DREQ_PIO0_TX0 0x0
+#define DREQ_PIO0_TX1 0x1
+#define DREQ_PIO0_TX2 0x2
+#define DREQ_PIO0_TX3 0x3
+#define DREQ_PIO0_RX0 0x4
+#define DREQ_PIO0_RX1 0x5
+#define DREQ_PIO0_RX2 0x6
+#define DREQ_PIO0_RX3 0x7
+#define DREQ_PIO1_TX0 0x8
+#define DREQ_PIO1_TX1 0x9
+#define DREQ_PIO1_TX2 0xa
+#define DREQ_PIO1_TX3 0xb
+#define DREQ_PIO1_RX0 0xc
+#define DREQ_PIO1_RX1 0xd
+#define DREQ_PIO1_RX2 0xe
+#define DREQ_PIO1_RX3 0xf
+#define DREQ_SPI0_TX 0x10
+#define DREQ_SPI0_RX 0x11
+#define DREQ_SPI1_TX 0x12
+#define DREQ_SPI1_RX 0x13
+#define DREQ_UART0_TX 0x14
+#define DREQ_UART0_RX 0x15
+#define DREQ_UART1_TX 0x16
+#define DREQ_UART1_RX 0x17
+#define DREQ_PWM_WRAP0 0x18
+#define DREQ_PWM_WRAP1 0x19
+#define DREQ_PWM_WRAP2 0x1a
+#define DREQ_PWM_WRAP3 0x1b
+#define DREQ_PWM_WRAP4 0x1c
+#define DREQ_PWM_WRAP5 0x1d
+#define DREQ_PWM_WRAP6 0x1e
+#define DREQ_PWM_WRAP7 0x1f
+#define DREQ_I2C0_TX 0x20
+#define DREQ_I2C0_RX 0x21
+#define DREQ_I2C1_TX 0x22
+#define DREQ_I2C1_RX 0x23
+#define DREQ_ADC 0x24
+#define DREQ_XIP_STREAM 0x25
+#define DREQ_XIP_SSITX 0x26
+#define DREQ_XIP_SSIRX 0x27
+
+#endif // _DREQ_H_
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/i2c.h b/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
new file mode 100644
index 0000000..dcddb06
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/i2c.h
@@ -0,0 +1,2713 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : I2C
+// Version        : 1
+// Bus type       : apb
+// Description    : DW_apb_i2c address block
+//
+//                  List of configuration constants for the Synopsys I2C
+//                  hardware (you may see references to these in I2C register
+//                  header; these are *fixed* values, set at hardware design
+//                  time):
+//
+//                  IC_ULTRA_FAST_MODE ................ 0x0
+//                  IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
+//                  IC_UFM_SCL_LOW_COUNT .............. 0x0008
+//                  IC_UFM_SCL_HIGH_COUNT ............. 0x0006
+//                  IC_TX_TL .......................... 0x0
+//                  IC_TX_CMD_BLOCK ................... 0x1
+//                  IC_HAS_DMA ........................ 0x1
+//                  IC_HAS_ASYNC_FIFO ................. 0x0
+//                  IC_SMBUS_ARP ...................... 0x0
+//                  IC_FIRST_DATA_BYTE_STATUS ......... 0x1
+//                  IC_INTR_IO ........................ 0x1
+//                  IC_MASTER_MODE .................... 0x1
+//                  IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
+//                  IC_INTR_POL ....................... 0x1
+//                  IC_OPTIONAL_SAR ................... 0x0
+//                  IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
+//                  IC_DEFAULT_SLAVE_ADDR ............. 0x055
+//                  IC_DEFAULT_HS_SPKLEN .............. 0x1
+//                  IC_FS_SCL_HIGH_COUNT .............. 0x0006
+//                  IC_HS_SCL_LOW_COUNT ............... 0x0008
+//                  IC_DEVICE_ID_VALUE ................ 0x0
+//                  IC_10BITADDR_MASTER ............... 0x0
+//                  IC_CLK_FREQ_OPTIMIZATION .......... 0x0
+//                  IC_DEFAULT_FS_SPKLEN .............. 0x7
+//                  IC_ADD_ENCODED_PARAMS ............. 0x0
+//                  IC_DEFAULT_SDA_HOLD ............... 0x000001
+//                  IC_DEFAULT_SDA_SETUP .............. 0x64
+//                  IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
+//                  IC_CLOCK_PERIOD ................... 100
+//                  IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
+//                  IC_RESTART_EN ..................... 0x1
+//                  IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
+//                  IC_BUS_CLEAR_FEATURE .............. 0x0
+//                  IC_CAP_LOADING .................... 100
+//                  IC_FS_SCL_LOW_COUNT ............... 0x000d
+//                  APB_DATA_WIDTH .................... 32
+//                  IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+//                  IC_SLV_DATA_NACK_ONLY ............. 0x1
+//                  IC_10BITADDR_SLAVE ................ 0x0
+//                  IC_CLK_TYPE ....................... 0x0
+//                  IC_SMBUS_UDID_MSB ................. 0x0
+//                  IC_SMBUS_SUSPEND_ALERT ............ 0x0
+//                  IC_HS_SCL_HIGH_COUNT .............. 0x0006
+//                  IC_SLV_RESTART_DET_EN ............. 0x1
+//                  IC_SMBUS .......................... 0x0
+//                  IC_OPTIONAL_SAR_DEFAULT ........... 0x0
+//                  IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
+//                  IC_USE_COUNTS ..................... 0x0
+//                  IC_RX_BUFFER_DEPTH ................ 16
+//                  IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+//                  IC_RX_FULL_HLD_BUS_EN ............. 0x1
+//                  IC_SLAVE_DISABLE .................. 0x1
+//                  IC_RX_TL .......................... 0x0
+//                  IC_DEVICE_ID ...................... 0x0
+//                  IC_HC_COUNT_VALUES ................ 0x0
+//                  I2C_DYNAMIC_TAR_UPDATE ............ 0
+//                  IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
+//                  IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
+//                  IC_HS_MASTER_CODE ................. 0x1
+//                  IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
+//                  IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
+//                  IC_SS_SCL_HIGH_COUNT .............. 0x0028
+//                  IC_SS_SCL_LOW_COUNT ............... 0x002f
+//                  IC_MAX_SPEED_MODE ................. 0x2
+//                  IC_STAT_FOR_CLK_STRETCH ........... 0x0
+//                  IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
+//                  IC_DEFAULT_UFM_SPKLEN ............. 0x1
+//                  IC_TX_BUFFER_DEPTH ................ 16
+// =============================================================================
+#ifndef HARDWARE_REGS_I2C_DEFINED
+#define HARDWARE_REGS_I2C_DEFINED
+// =============================================================================
+// Register    : I2C_IC_CON
+// Description : I2C Control Register. This register can be written only when
+//               the DW_apb_i2c is disabled, which corresponds to the
+//               IC_ENABLE[0] register being set to 0. Writes at other times
+//               have no effect.
+//
+//               Read/Write Access: - bit 10 is read only. - bit 11 is read only
+//               - bit 16 is read only - bit 17 is read only - bits 18 and 19
+//               are read only.
+#define I2C_IC_CON_OFFSET _u(0x00000000)
+#define I2C_IC_CON_BITS   _u(0x000007ff)
+#define I2C_IC_CON_RESET  _u(0x00000065)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE
+// Description : Master issues the STOP_DET interrupt irrespective of whether
+//               master is active or not
+#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET  _u(0x0)
+#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS   _u(0x00000400)
+#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB    _u(10)
+#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB    _u(10)
+#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL
+// Description : This bit controls whether DW_apb_i2c should hold the bus when
+//               the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as
+//               described in the IC_RX_FULL_HLD_BUS_EN parameter.
+//
+//               Reset value: 0x0.
+//               0x0 -> Overflow when RX_FIFO is full
+//               0x1 -> Hold bus when RX_FIFO is full
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET          _u(0x0)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS           _u(0x00000200)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB            _u(9)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB            _u(9)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS         "RW"
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED  _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CON_TX_EMPTY_CTRL
+// Description : This bit controls the generation of the TX_EMPTY interrupt, as
+//               described in the IC_RAW_INTR_STAT register.
+//
+//               Reset value: 0x0.
+//               0x0 -> Default behaviour of TX_EMPTY interrupt
+//               0x1 -> Controlled generation of TX_EMPTY interrupt
+#define I2C_IC_CON_TX_EMPTY_CTRL_RESET          _u(0x0)
+#define I2C_IC_CON_TX_EMPTY_CTRL_BITS           _u(0x00000100)
+#define I2C_IC_CON_TX_EMPTY_CTRL_MSB            _u(8)
+#define I2C_IC_CON_TX_EMPTY_CTRL_LSB            _u(8)
+#define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS         "RW"
+#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED  _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CON_STOP_DET_IFADDRESSED
+// Description : In slave mode: - 1'b1:  issues the STOP_DET interrupt only when
+//               it is addressed. - 1'b0:  issues the STOP_DET irrespective of
+//               whether it's addressed or not. Reset value: 0x0
+//
+//               NOTE: During a general call address, this slave does not issue
+//               the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if
+//               the slave responds to the general call address by generating
+//               ACK. The STOP_DET interrupt is generated only when the
+//               transmitted address matches the slave address (SAR).
+//               0x0 -> slave issues STOP_DET intr always
+//               0x1 -> slave issues STOP_DET intr only if addressed
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET          _u(0x0)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS           _u(0x00000080)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB            _u(7)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB            _u(7)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS         "RW"
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED  _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CON_IC_SLAVE_DISABLE
+// Description : This bit controls whether I2C has its slave disabled, which
+//               means once the presetn signal is applied, then this bit is set
+//               and the slave is disabled.
+//
+//               If this bit is set (slave is disabled), DW_apb_i2c functions
+//               only as a master and does not perform any action that requires
+//               a slave.
+//
+//               NOTE: Software should ensure that if this bit is written with
+//               0, then bit 0 should also be written with a 0.
+//               0x0 -> Slave mode is enabled
+//               0x1 -> Slave mode is disabled
+#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET                _u(0x1)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS                 _u(0x00000040)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB                  _u(6)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB                  _u(6)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS               "RW"
+#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED  _u(0x0)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CON_IC_RESTART_EN
+// Description : Determines whether RESTART conditions may be sent when acting
+//               as a master. Some older slaves do not support handling RESTART
+//               conditions; however, RESTART conditions are used in several
+//               DW_apb_i2c operations. When RESTART is disabled, the master is
+//               prohibited from performing the following functions: - Sending a
+//               START BYTE - Performing any high-speed mode operation -
+//               High-speed mode operation - Performing direction changes in
+//               combined format mode - Performing a read operation with a
+//               10-bit address By replacing RESTART condition followed by a
+//               STOP and a subsequent START condition, split operations are
+//               broken down into multiple DW_apb_i2c transfers. If the above
+//               operations are performed, it will result in setting bit 6
+//               (TX_ABRT) of the IC_RAW_INTR_STAT register.
+//
+//               Reset value: ENABLED
+//               0x0 -> Master restart disabled
+//               0x1 -> Master restart enabled
+#define I2C_IC_CON_IC_RESTART_EN_RESET          _u(0x1)
+#define I2C_IC_CON_IC_RESTART_EN_BITS           _u(0x00000020)
+#define I2C_IC_CON_IC_RESTART_EN_MSB            _u(5)
+#define I2C_IC_CON_IC_RESTART_EN_LSB            _u(5)
+#define I2C_IC_CON_IC_RESTART_EN_ACCESS         "RW"
+#define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED  _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CON_IC_10BITADDR_MASTER
+// Description : Controls whether the DW_apb_i2c starts its transfers in 7- or
+//               10-bit addressing mode when acting as a master. - 0: 7-bit
+//               addressing - 1: 10-bit addressing
+//               0x0 -> Master 7Bit addressing mode
+//               0x1 -> Master 10Bit addressing mode
+#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET             _u(0x0)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS              _u(0x00000010)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB               _u(4)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB               _u(4)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS            "RW"
+#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS  _u(0x0)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CON_IC_10BITADDR_SLAVE
+// Description : When acting as a slave, this bit controls whether the
+//               DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit
+//               addressing. The DW_apb_i2c ignores transactions that involve
+//               10-bit addressing; for 7-bit addressing, only the lower 7 bits
+//               of the IC_SAR register are compared. - 1: 10-bit addressing.
+//               The DW_apb_i2c responds to only 10-bit addressing transfers
+//               that match the full 10 bits of the IC_SAR register.
+//               0x0 -> Slave 7Bit addressing
+//               0x1 -> Slave 10Bit addressing
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET             _u(0x0)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS              _u(0x00000008)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB               _u(3)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB               _u(3)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS            "RW"
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS  _u(0x0)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CON_SPEED
+// Description : These bits control at which speed the DW_apb_i2c operates; its
+//               setting is relevant only if one is operating the DW_apb_i2c in
+//               master mode. Hardware protects against illegal values being
+//               programmed by software. These bits must be programmed
+//               appropriately for slave mode also, as it is used to capture
+//               correct value of spike filter as per the speed mode.
+//
+//               This register should be programmed only with a value in the
+//               range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates
+//               this register with the value of IC_MAX_SPEED_MODE.
+//
+//               1: standard mode (100 kbit/s)
+//
+//               2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)
+//
+//               3: high speed mode (3.4 Mbit/s)
+//
+//               Note: This field is not applicable when IC_ULTRA_FAST_MODE=1
+//               0x1 -> Standard Speed mode of operation
+//               0x2 -> Fast or Fast Plus mode of operation
+//               0x3 -> High Speed mode of operation
+#define I2C_IC_CON_SPEED_RESET          _u(0x2)
+#define I2C_IC_CON_SPEED_BITS           _u(0x00000006)
+#define I2C_IC_CON_SPEED_MSB            _u(2)
+#define I2C_IC_CON_SPEED_LSB            _u(1)
+#define I2C_IC_CON_SPEED_ACCESS         "RW"
+#define I2C_IC_CON_SPEED_VALUE_STANDARD _u(0x1)
+#define I2C_IC_CON_SPEED_VALUE_FAST     _u(0x2)
+#define I2C_IC_CON_SPEED_VALUE_HIGH     _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CON_MASTER_MODE
+// Description : This bit controls whether the DW_apb_i2c master is enabled.
+//
+//               NOTE: Software should ensure that if this bit is written with
+//               '1' then bit 6 should also be written with a '1'.
+//               0x0 -> Master mode is disabled
+//               0x1 -> Master mode is enabled
+#define I2C_IC_CON_MASTER_MODE_RESET          _u(0x1)
+#define I2C_IC_CON_MASTER_MODE_BITS           _u(0x00000001)
+#define I2C_IC_CON_MASTER_MODE_MSB            _u(0)
+#define I2C_IC_CON_MASTER_MODE_LSB            _u(0)
+#define I2C_IC_CON_MASTER_MODE_ACCESS         "RW"
+#define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED  _u(0x1)
+// =============================================================================
+// Register    : I2C_IC_TAR
+// Description : I2C Target Address Register
+//
+//               This register is 12 bits wide, and bits 31:12 are reserved.
+//               This register can be written to only when IC_ENABLE[0] is set
+//               to 0.
+//
+//               Note: If the software or application is aware that the
+//               DW_apb_i2c is not using the TAR address for the pending
+//               commands in the Tx FIFO, then it is possible to update the TAR
+//               address even while the Tx FIFO has entries (IC_STATUS[2]= 0). -
+//               It is not necessary to perform any write to this register if
+//               DW_apb_i2c is enabled as an I2C slave only.
+#define I2C_IC_TAR_OFFSET _u(0x00000004)
+#define I2C_IC_TAR_BITS   _u(0x00000fff)
+#define I2C_IC_TAR_RESET  _u(0x00000055)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TAR_SPECIAL
+// Description : This bit indicates whether software performs a Device-ID or
+//               General Call or START BYTE command. - 0: ignore bit 10
+//               GC_OR_START and use IC_TAR normally - 1: perform special I2C
+//               command as specified in Device_ID or GC_OR_START bit Reset
+//               value: 0x0
+//               0x0 -> Disables programming of GENERAL_CALL or START_BYTE
+//               transmission
+//               0x1 -> Enables programming of GENERAL_CALL or START_BYTE
+//               transmission
+#define I2C_IC_TAR_SPECIAL_RESET          _u(0x0)
+#define I2C_IC_TAR_SPECIAL_BITS           _u(0x00000800)
+#define I2C_IC_TAR_SPECIAL_MSB            _u(11)
+#define I2C_IC_TAR_SPECIAL_LSB            _u(11)
+#define I2C_IC_TAR_SPECIAL_ACCESS         "RW"
+#define I2C_IC_TAR_SPECIAL_VALUE_DISABLED _u(0x0)
+#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED  _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TAR_GC_OR_START
+// Description : If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to
+//               0, then this bit indicates whether a General Call or START byte
+//               command is to be performed by the DW_apb_i2c. - 0: General Call
+//               Address - after issuing a General Call, only writes may be
+//               performed. Attempting to issue a read command results in
+//               setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The
+//               DW_apb_i2c remains in General Call mode until the SPECIAL bit
+//               value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0
+//               0x0 -> GENERAL_CALL byte transmission
+//               0x1 -> START byte transmission
+#define I2C_IC_TAR_GC_OR_START_RESET              _u(0x0)
+#define I2C_IC_TAR_GC_OR_START_BITS               _u(0x00000400)
+#define I2C_IC_TAR_GC_OR_START_MSB                _u(10)
+#define I2C_IC_TAR_GC_OR_START_LSB                _u(10)
+#define I2C_IC_TAR_GC_OR_START_ACCESS             "RW"
+#define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL _u(0x0)
+#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TAR_IC_TAR
+// Description : This is the target address for any master transaction. When
+//               transmitting a General Call, these bits are ignored. To
+//               generate a START BYTE, the CPU needs to write only once into
+//               these bits.
+//
+//               If the IC_TAR and IC_SAR are the same, loopback exists but the
+//               FIFOs are shared between master and slave, so full loopback is
+//               not feasible. Only one direction loopback mode is supported
+//               (simplex), not duplex. A master cannot transmit to itself; it
+//               can transmit to only a slave.
+#define I2C_IC_TAR_IC_TAR_RESET  _u(0x055)
+#define I2C_IC_TAR_IC_TAR_BITS   _u(0x000003ff)
+#define I2C_IC_TAR_IC_TAR_MSB    _u(9)
+#define I2C_IC_TAR_IC_TAR_LSB    _u(0)
+#define I2C_IC_TAR_IC_TAR_ACCESS "RW"
+// =============================================================================
+// Register    : I2C_IC_SAR
+// Description : I2C Slave Address Register
+#define I2C_IC_SAR_OFFSET _u(0x00000008)
+#define I2C_IC_SAR_BITS   _u(0x000003ff)
+#define I2C_IC_SAR_RESET  _u(0x00000055)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_SAR_IC_SAR
+// Description : The IC_SAR holds the slave address when the I2C is operating as
+//               a slave. For 7-bit addressing, only IC_SAR[6:0] is used.
+//
+//               This register can be written only when the I2C interface is
+//               disabled, which corresponds to the IC_ENABLE[0] register being
+//               set to 0. Writes at other times have no effect.
+//
+//               Note: The default values cannot be any of the reserved address
+//               locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct
+//               operation of the device is not guaranteed if you program the
+//               IC_SAR or IC_TAR to a reserved value. Refer to
+//               <<table_I2C_firstbyte_bit_defs>> for a complete list of these
+//               reserved values.
+#define I2C_IC_SAR_IC_SAR_RESET  _u(0x055)
+#define I2C_IC_SAR_IC_SAR_BITS   _u(0x000003ff)
+#define I2C_IC_SAR_IC_SAR_MSB    _u(9)
+#define I2C_IC_SAR_IC_SAR_LSB    _u(0)
+#define I2C_IC_SAR_IC_SAR_ACCESS "RW"
+// =============================================================================
+// Register    : I2C_IC_DATA_CMD
+// Description : I2C Rx/Tx Data Buffer and Command Register; this is the
+//               register the CPU writes to when filling the TX FIFO and the CPU
+//               reads from when retrieving bytes from RX FIFO.
+//
+//               The size of the register changes as follows:
+//
+//               Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits
+//               when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when
+//               IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when
+//               IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c
+//               to continue acknowledging reads, a read command should be
+//               written for every byte that is to be received; otherwise the
+//               DW_apb_i2c will stop acknowledging.
+#define I2C_IC_DATA_CMD_OFFSET _u(0x00000010)
+#define I2C_IC_DATA_CMD_BITS   _u(0x00000fff)
+#define I2C_IC_DATA_CMD_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_DATA_CMD_FIRST_DATA_BYTE
+// Description : Indicates the first data byte received after the address phase
+//               for receive transfer in Master receiver or Slave receiver mode.
+//
+//               Reset value : 0x0
+//
+//               NOTE:  In case of APB_DATA_WIDTH=8,
+//
+//               1. The user has to perform two APB Reads to IC_DATA_CMD in
+//               order to get status on 11 bit.
+//
+//               2. In order to read the 11 bit, the user has to perform the
+//               first data byte read [7:0] (offset 0x10) and then perform the
+//               second read [15:8] (offset 0x11) in order to know the status of
+//               11 bit (whether the data received in previous read is a first
+//               data byte or not).
+//
+//               3. The 11th bit is an optional read field, user can ignore 2nd
+//               byte read [15:8] (offset 0x11) if not interested in
+//               FIRST_DATA_BYTE status.
+//               0x0 -> Sequential data byte received
+//               0x1 -> Non sequential data byte received
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET          _u(0x0)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS           _u(0x00000800)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB            _u(11)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB            _u(11)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS         "RO"
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_DATA_CMD_RESTART
+// Description : This bit controls whether a RESTART is issued before the byte
+//               is sent or received.
+//
+//               1 - If IC_RESTART_EN is 1, a RESTART is issued before the data
+//               is sent/received (according to the value of CMD), regardless of
+//               whether or not the transfer direction is changing from the
+//               previous command; if IC_RESTART_EN is 0, a STOP followed by a
+//               START is issued instead.
+//
+//               0 - If IC_RESTART_EN is 1, a RESTART is issued only if the
+//               transfer direction is changing from the previous command; if
+//               IC_RESTART_EN is 0, a STOP followed by a START is issued
+//               instead.
+//
+//               Reset value: 0x0
+//               0x0 -> Don't Issue RESTART before this command
+//               0x1 -> Issue RESTART before this command
+#define I2C_IC_DATA_CMD_RESTART_RESET         _u(0x0)
+#define I2C_IC_DATA_CMD_RESTART_BITS          _u(0x00000400)
+#define I2C_IC_DATA_CMD_RESTART_MSB           _u(10)
+#define I2C_IC_DATA_CMD_RESTART_LSB           _u(10)
+#define I2C_IC_DATA_CMD_RESTART_ACCESS        "SC"
+#define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE _u(0x0)
+#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE  _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_DATA_CMD_STOP
+// Description : This bit controls whether a STOP is issued after the byte is
+//               sent or received.
+//
+//               - 1 - STOP is issued after this byte, regardless of whether or
+//               not the Tx FIFO is empty. If the Tx FIFO is not empty, the
+//               master immediately tries to start a new transfer by issuing a
+//               START and arbitrating for the bus. - 0 - STOP is not issued
+//               after this byte, regardless of whether or not the Tx FIFO is
+//               empty. If the Tx FIFO is not empty, the master continues the
+//               current transfer by sending/receiving data bytes according to
+//               the value of the CMD bit. If the Tx FIFO is empty, the master
+//               holds the SCL line low and stalls the bus until a new command
+//               is available in the Tx FIFO. Reset value: 0x0
+//               0x0 -> Don't Issue STOP after this command
+//               0x1 -> Issue STOP after this command
+#define I2C_IC_DATA_CMD_STOP_RESET         _u(0x0)
+#define I2C_IC_DATA_CMD_STOP_BITS          _u(0x00000200)
+#define I2C_IC_DATA_CMD_STOP_MSB           _u(9)
+#define I2C_IC_DATA_CMD_STOP_LSB           _u(9)
+#define I2C_IC_DATA_CMD_STOP_ACCESS        "SC"
+#define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE _u(0x0)
+#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE  _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_DATA_CMD_CMD
+// Description : This bit controls whether a read or a write is performed. This
+//               bit does not control the direction when the DW_apb_i2con acts
+//               as a slave. It controls only the direction when it acts as a
+//               master.
+//
+//               When a command is entered in the TX FIFO, this bit
+//               distinguishes the write and read commands. In slave-receiver
+//               mode, this bit is a 'don't care' because writes to this
+//               register are not required. In slave-transmitter mode, a '0'
+//               indicates that the data in IC_DATA_CMD is to be transmitted.
+//
+//               When programming this bit, you should remember the following:
+//               attempting to perform a read operation after a General Call
+//               command has been sent results in a TX_ABRT interrupt (bit 6 of
+//               the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the
+//               IC_TAR register has been cleared. If a '1' is written to this
+//               bit after receiving a RD_REQ interrupt, then a TX_ABRT
+//               interrupt occurs.
+//
+//               Reset value: 0x0
+//               0x0 -> Master Write Command
+//               0x1 -> Master Read Command
+#define I2C_IC_DATA_CMD_CMD_RESET       _u(0x0)
+#define I2C_IC_DATA_CMD_CMD_BITS        _u(0x00000100)
+#define I2C_IC_DATA_CMD_CMD_MSB         _u(8)
+#define I2C_IC_DATA_CMD_CMD_LSB         _u(8)
+#define I2C_IC_DATA_CMD_CMD_ACCESS      "SC"
+#define I2C_IC_DATA_CMD_CMD_VALUE_WRITE _u(0x0)
+#define I2C_IC_DATA_CMD_CMD_VALUE_READ  _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_DATA_CMD_DAT
+// Description : This register contains the data to be transmitted or received
+//               on the I2C bus. If you are writing to this register and want to
+//               perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c.
+//               However, when you read this register, these bits return the
+//               value of data received on the DW_apb_i2c interface.
+//
+//               Reset value: 0x0
+#define I2C_IC_DATA_CMD_DAT_RESET  _u(0x00)
+#define I2C_IC_DATA_CMD_DAT_BITS   _u(0x000000ff)
+#define I2C_IC_DATA_CMD_DAT_MSB    _u(7)
+#define I2C_IC_DATA_CMD_DAT_LSB    _u(0)
+#define I2C_IC_DATA_CMD_DAT_ACCESS "RW"
+// =============================================================================
+// Register    : I2C_IC_SS_SCL_HCNT
+// Description : Standard Speed I2C Clock SCL High Count Register
+#define I2C_IC_SS_SCL_HCNT_OFFSET _u(0x00000014)
+#define I2C_IC_SS_SCL_HCNT_BITS   _u(0x0000ffff)
+#define I2C_IC_SS_SCL_HCNT_RESET  _u(0x00000028)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT
+// Description : This register must be set before any I2C bus transaction can
+//               take place to ensure proper I/O timing. This register sets the
+//               SCL clock high-period count for standard speed. For more
+//               information, refer to 'IC_CLK Frequency Configuration'.
+//
+//               This register can be written only when the I2C interface is
+//               disabled which corresponds to the IC_ENABLE[0] register being
+//               set to 0. Writes at other times have no effect.
+//
+//               The minimum valid value is 6; hardware prevents values less
+//               than this being written, and if attempted results in 6 being
+//               set. For designs with APB_DATA_WIDTH = 8, the order of
+//               programming is important to ensure the correct operation of the
+//               DW_apb_i2c. The lower byte must be programmed first. Then the
+//               upper byte is programmed.
+//
+//               NOTE: This register must not be programmed to a value higher
+//               than 65525, because DW_apb_i2c uses a 16-bit counter to flag an
+//               I2C bus idle condition when this counter reaches a value of
+//               IC_SS_SCL_HCNT + 10.
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET  _u(0x0028)
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_BITS   _u(0x0000ffff)
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB    _u(15)
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB    _u(0)
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_ACCESS "RW"
+// =============================================================================
+// Register    : I2C_IC_SS_SCL_LCNT
+// Description : Standard Speed I2C Clock SCL Low Count Register
+#define I2C_IC_SS_SCL_LCNT_OFFSET _u(0x00000018)
+#define I2C_IC_SS_SCL_LCNT_BITS   _u(0x0000ffff)
+#define I2C_IC_SS_SCL_LCNT_RESET  _u(0x0000002f)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT
+// Description : This register must be set before any I2C bus transaction can
+//               take place to ensure proper I/O timing. This register sets the
+//               SCL clock low period count for standard speed. For more
+//               information, refer to 'IC_CLK Frequency Configuration'
+//
+//               This register can be written only when the I2C interface is
+//               disabled which corresponds to the IC_ENABLE[0] register being
+//               set to 0. Writes at other times have no effect.
+//
+//               The minimum valid value is 8; hardware prevents values less
+//               than this being written, and if attempted, results in 8 being
+//               set. For designs with APB_DATA_WIDTH = 8, the order of
+//               programming is important to ensure the correct operation of
+//               DW_apb_i2c. The lower byte must be programmed first, and then
+//               the upper byte is programmed.
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET  _u(0x002f)
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_BITS   _u(0x0000ffff)
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB    _u(15)
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB    _u(0)
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_ACCESS "RW"
+// =============================================================================
+// Register    : I2C_IC_FS_SCL_HCNT
+// Description : Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
+#define I2C_IC_FS_SCL_HCNT_OFFSET _u(0x0000001c)
+#define I2C_IC_FS_SCL_HCNT_BITS   _u(0x0000ffff)
+#define I2C_IC_FS_SCL_HCNT_RESET  _u(0x00000006)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT
+// Description : This register must be set before any I2C bus transaction can
+//               take place to ensure proper I/O timing. This register sets the
+//               SCL clock high-period count for fast mode or fast mode plus. It
+//               is used in high-speed mode to send the Master Code and START
+//               BYTE or General CALL. For more information, refer to 'IC_CLK
+//               Frequency Configuration'.
+//
+//               This register goes away and becomes read-only returning 0s if
+//               IC_MAX_SPEED_MODE = standard. This register can be written only
+//               when the I2C interface is disabled, which corresponds to the
+//               IC_ENABLE[0] register being set to 0. Writes at other times
+//               have no effect.
+//
+//               The minimum valid value is 6; hardware prevents values less
+//               than this being written, and if attempted results in 6 being
+//               set. For designs with APB_DATA_WIDTH == 8 the order of
+//               programming is important to ensure the correct operation of the
+//               DW_apb_i2c. The lower byte must be programmed first. Then the
+//               upper byte is programmed.
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET  _u(0x0006)
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS   _u(0x0000ffff)
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB    _u(15)
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB    _u(0)
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_ACCESS "RW"
+// =============================================================================
+// Register    : I2C_IC_FS_SCL_LCNT
+// Description : Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
+#define I2C_IC_FS_SCL_LCNT_OFFSET _u(0x00000020)
+#define I2C_IC_FS_SCL_LCNT_BITS   _u(0x0000ffff)
+#define I2C_IC_FS_SCL_LCNT_RESET  _u(0x0000000d)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT
+// Description : This register must be set before any I2C bus transaction can
+//               take place to ensure proper I/O timing. This register sets the
+//               SCL clock low period count for fast speed. It is used in
+//               high-speed mode to send the Master Code and START BYTE or
+//               General CALL. For more information, refer to 'IC_CLK Frequency
+//               Configuration'.
+//
+//               This register goes away and becomes read-only returning 0s if
+//               IC_MAX_SPEED_MODE = standard.
+//
+//               This register can be written only when the I2C interface is
+//               disabled, which corresponds to the IC_ENABLE[0] register being
+//               set to 0. Writes at other times have no effect.
+//
+//               The minimum valid value is 8; hardware prevents values less
+//               than this being written, and if attempted results in 8 being
+//               set. For designs with APB_DATA_WIDTH = 8 the order of
+//               programming is important to ensure the correct operation of the
+//               DW_apb_i2c. The lower byte must be programmed first. Then the
+//               upper byte is programmed. If the value is less than 8 then the
+//               count value gets changed to 8.
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET  _u(0x000d)
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS   _u(0x0000ffff)
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB    _u(15)
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB    _u(0)
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_ACCESS "RW"
+// =============================================================================
+// Register    : I2C_IC_INTR_STAT
+// Description : I2C Interrupt Status Register
+//
+//               Each bit in this register has a corresponding mask bit in the
+//               IC_INTR_MASK register. These bits are cleared by reading the
+//               matching interrupt clear register. The unmasked raw versions of
+//               these bits are available in the IC_RAW_INTR_STAT register.
+#define I2C_IC_INTR_STAT_OFFSET _u(0x0000002c)
+#define I2C_IC_INTR_STAT_BITS   _u(0x00001fff)
+#define I2C_IC_INTR_STAT_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_STAT_R_RESTART_DET
+// Description : See IC_RAW_INTR_STAT for a detailed description of
+//               R_RESTART_DET bit.
+//
+//               Reset value: 0x0
+//               0x0 -> R_RESTART_DET interrupt is inactive
+//               0x1 -> R_RESTART_DET interrupt is active
+#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET          _u(0x0)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS           _u(0x00001000)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB            _u(12)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB            _u(12)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS         "RO"
+#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_STAT_R_GEN_CALL
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL
+//               bit.
+//
+//               Reset value: 0x0
+//               0x0 -> R_GEN_CALL interrupt is inactive
+//               0x1 -> R_GEN_CALL interrupt is active
+#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET          _u(0x0)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS           _u(0x00000800)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB            _u(11)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB            _u(11)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS         "RO"
+#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_STAT_R_START_DET
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_START_DET
+//               bit.
+//
+//               Reset value: 0x0
+//               0x0 -> R_START_DET interrupt is inactive
+//               0x1 -> R_START_DET interrupt is active
+#define I2C_IC_INTR_STAT_R_START_DET_RESET          _u(0x0)
+#define I2C_IC_INTR_STAT_R_START_DET_BITS           _u(0x00000400)
+#define I2C_IC_INTR_STAT_R_START_DET_MSB            _u(10)
+#define I2C_IC_INTR_STAT_R_START_DET_LSB            _u(10)
+#define I2C_IC_INTR_STAT_R_START_DET_ACCESS         "RO"
+#define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_STAT_R_STOP_DET
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET
+//               bit.
+//
+//               Reset value: 0x0
+//               0x0 -> R_STOP_DET interrupt is inactive
+//               0x1 -> R_STOP_DET interrupt is active
+#define I2C_IC_INTR_STAT_R_STOP_DET_RESET          _u(0x0)
+#define I2C_IC_INTR_STAT_R_STOP_DET_BITS           _u(0x00000200)
+#define I2C_IC_INTR_STAT_R_STOP_DET_MSB            _u(9)
+#define I2C_IC_INTR_STAT_R_STOP_DET_LSB            _u(9)
+#define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS         "RO"
+#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_STAT_R_ACTIVITY
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY
+//               bit.
+//
+//               Reset value: 0x0
+//               0x0 -> R_ACTIVITY interrupt is inactive
+//               0x1 -> R_ACTIVITY interrupt is active
+#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET          _u(0x0)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS           _u(0x00000100)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB            _u(8)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB            _u(8)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS         "RO"
+#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_STAT_R_RX_DONE
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE
+//               bit.
+//
+//               Reset value: 0x0
+//               0x0 -> R_RX_DONE interrupt is inactive
+//               0x1 -> R_RX_DONE interrupt is active
+#define I2C_IC_INTR_STAT_R_RX_DONE_RESET          _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_DONE_BITS           _u(0x00000080)
+#define I2C_IC_INTR_STAT_R_RX_DONE_MSB            _u(7)
+#define I2C_IC_INTR_STAT_R_RX_DONE_LSB            _u(7)
+#define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS         "RO"
+#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_STAT_R_TX_ABRT
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT
+//               bit.
+//
+//               Reset value: 0x0
+//               0x0 -> R_TX_ABRT interrupt is inactive
+//               0x1 -> R_TX_ABRT interrupt is active
+#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET          _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS           _u(0x00000040)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB            _u(6)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB            _u(6)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS         "RO"
+#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_STAT_R_RD_REQ
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ
+//               bit.
+//
+//               Reset value: 0x0
+//               0x0 -> R_RD_REQ interrupt is inactive
+//               0x1 -> R_RD_REQ interrupt is active
+#define I2C_IC_INTR_STAT_R_RD_REQ_RESET          _u(0x0)
+#define I2C_IC_INTR_STAT_R_RD_REQ_BITS           _u(0x00000020)
+#define I2C_IC_INTR_STAT_R_RD_REQ_MSB            _u(5)
+#define I2C_IC_INTR_STAT_R_RD_REQ_LSB            _u(5)
+#define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS         "RO"
+#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_STAT_R_TX_EMPTY
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY
+//               bit.
+//
+//               Reset value: 0x0
+//               0x0 -> R_TX_EMPTY interrupt is inactive
+//               0x1 -> R_TX_EMPTY interrupt is active
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET          _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS           _u(0x00000010)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB            _u(4)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB            _u(4)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS         "RO"
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_STAT_R_TX_OVER
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER
+//               bit.
+//
+//               Reset value: 0x0
+//               0x0 -> R_TX_OVER interrupt is inactive
+//               0x1 -> R_TX_OVER interrupt is active
+#define I2C_IC_INTR_STAT_R_TX_OVER_RESET          _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_OVER_BITS           _u(0x00000008)
+#define I2C_IC_INTR_STAT_R_TX_OVER_MSB            _u(3)
+#define I2C_IC_INTR_STAT_R_TX_OVER_LSB            _u(3)
+#define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS         "RO"
+#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_STAT_R_RX_FULL
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL
+//               bit.
+//
+//               Reset value: 0x0
+//               0x0 -> R_RX_FULL interrupt is inactive
+//               0x1 -> R_RX_FULL interrupt is active
+#define I2C_IC_INTR_STAT_R_RX_FULL_RESET          _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_FULL_BITS           _u(0x00000004)
+#define I2C_IC_INTR_STAT_R_RX_FULL_MSB            _u(2)
+#define I2C_IC_INTR_STAT_R_RX_FULL_LSB            _u(2)
+#define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS         "RO"
+#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_STAT_R_RX_OVER
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER
+//               bit.
+//
+//               Reset value: 0x0
+//               0x0 -> R_RX_OVER interrupt is inactive
+//               0x1 -> R_RX_OVER interrupt is active
+#define I2C_IC_INTR_STAT_R_RX_OVER_RESET          _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_OVER_BITS           _u(0x00000002)
+#define I2C_IC_INTR_STAT_R_RX_OVER_MSB            _u(1)
+#define I2C_IC_INTR_STAT_R_RX_OVER_LSB            _u(1)
+#define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS         "RO"
+#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_STAT_R_RX_UNDER
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER
+//               bit.
+//
+//               Reset value: 0x0
+//               0x0 -> RX_UNDER interrupt is inactive
+//               0x1 -> RX_UNDER interrupt is active
+#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET          _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS           _u(0x00000001)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB            _u(0)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB            _u(0)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS         "RO"
+#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE   _u(0x1)
+// =============================================================================
+// Register    : I2C_IC_INTR_MASK
+// Description : I2C Interrupt Mask Register.
+//
+//               These bits mask their corresponding interrupt status bits. This
+//               register is active low; a value of 0 masks the interrupt,
+//               whereas a value of 1 unmasks the interrupt.
+#define I2C_IC_INTR_MASK_OFFSET _u(0x00000030)
+#define I2C_IC_INTR_MASK_BITS   _u(0x00001fff)
+#define I2C_IC_INTR_MASK_RESET  _u(0x000008ff)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_MASK_M_RESTART_DET
+// Description : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT
+//               register.
+//
+//               Reset value: 0x0
+//               0x0 -> RESTART_DET interrupt is masked
+//               0x1 -> RESTART_DET interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET          _u(0x0)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS           _u(0x00001000)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB            _u(12)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB            _u(12)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS         "RW"
+#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED  _u(0x0)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_MASK_M_GEN_CALL
+// Description : This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT
+//               register.
+//
+//               Reset value: 0x1
+//               0x0 -> GEN_CALL interrupt is masked
+//               0x1 -> GEN_CALL interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET          _u(0x1)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS           _u(0x00000800)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB            _u(11)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB            _u(11)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS         "RW"
+#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED  _u(0x0)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_MASK_M_START_DET
+// Description : This bit masks the R_START_DET interrupt in IC_INTR_STAT
+//               register.
+//
+//               Reset value: 0x0
+//               0x0 -> START_DET interrupt is masked
+//               0x1 -> START_DET interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_START_DET_RESET          _u(0x0)
+#define I2C_IC_INTR_MASK_M_START_DET_BITS           _u(0x00000400)
+#define I2C_IC_INTR_MASK_M_START_DET_MSB            _u(10)
+#define I2C_IC_INTR_MASK_M_START_DET_LSB            _u(10)
+#define I2C_IC_INTR_MASK_M_START_DET_ACCESS         "RW"
+#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED  _u(0x0)
+#define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_MASK_M_STOP_DET
+// Description : This bit masks the R_STOP_DET interrupt in IC_INTR_STAT
+//               register.
+//
+//               Reset value: 0x0
+//               0x0 -> STOP_DET interrupt is masked
+//               0x1 -> STOP_DET interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_STOP_DET_RESET          _u(0x0)
+#define I2C_IC_INTR_MASK_M_STOP_DET_BITS           _u(0x00000200)
+#define I2C_IC_INTR_MASK_M_STOP_DET_MSB            _u(9)
+#define I2C_IC_INTR_MASK_M_STOP_DET_LSB            _u(9)
+#define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS         "RW"
+#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED  _u(0x0)
+#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_MASK_M_ACTIVITY
+// Description : This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT
+//               register.
+//
+//               Reset value: 0x0
+//               0x0 -> ACTIVITY interrupt is masked
+//               0x1 -> ACTIVITY interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET          _u(0x0)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS           _u(0x00000100)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB            _u(8)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB            _u(8)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS         "RW"
+#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED  _u(0x0)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_MASK_M_RX_DONE
+// Description : This bit masks the R_RX_DONE interrupt in IC_INTR_STAT
+//               register.
+//
+//               Reset value: 0x1
+//               0x0 -> RX_DONE interrupt is masked
+//               0x1 -> RX_DONE interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_RX_DONE_RESET          _u(0x1)
+#define I2C_IC_INTR_MASK_M_RX_DONE_BITS           _u(0x00000080)
+#define I2C_IC_INTR_MASK_M_RX_DONE_MSB            _u(7)
+#define I2C_IC_INTR_MASK_M_RX_DONE_LSB            _u(7)
+#define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS         "RW"
+#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED  _u(0x0)
+#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_MASK_M_TX_ABRT
+// Description : This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT
+//               register.
+//
+//               Reset value: 0x1
+//               0x0 -> TX_ABORT interrupt is masked
+//               0x1 -> TX_ABORT interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET          _u(0x1)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS           _u(0x00000040)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB            _u(6)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB            _u(6)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS         "RW"
+#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED  _u(0x0)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_MASK_M_RD_REQ
+// Description : This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.
+//
+//               Reset value: 0x1
+//               0x0 -> RD_REQ interrupt is masked
+//               0x1 -> RD_REQ interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_RD_REQ_RESET          _u(0x1)
+#define I2C_IC_INTR_MASK_M_RD_REQ_BITS           _u(0x00000020)
+#define I2C_IC_INTR_MASK_M_RD_REQ_MSB            _u(5)
+#define I2C_IC_INTR_MASK_M_RD_REQ_LSB            _u(5)
+#define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS         "RW"
+#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED  _u(0x0)
+#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_MASK_M_TX_EMPTY
+// Description : This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT
+//               register.
+//
+//               Reset value: 0x1
+//               0x0 -> TX_EMPTY interrupt is masked
+//               0x1 -> TX_EMPTY interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET          _u(0x1)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS           _u(0x00000010)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB            _u(4)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB            _u(4)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS         "RW"
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED  _u(0x0)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_MASK_M_TX_OVER
+// Description : This bit masks the R_TX_OVER interrupt in IC_INTR_STAT
+//               register.
+//
+//               Reset value: 0x1
+//               0x0 -> TX_OVER interrupt is masked
+//               0x1 -> TX_OVER interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_TX_OVER_RESET          _u(0x1)
+#define I2C_IC_INTR_MASK_M_TX_OVER_BITS           _u(0x00000008)
+#define I2C_IC_INTR_MASK_M_TX_OVER_MSB            _u(3)
+#define I2C_IC_INTR_MASK_M_TX_OVER_LSB            _u(3)
+#define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS         "RW"
+#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED  _u(0x0)
+#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_MASK_M_RX_FULL
+// Description : This bit masks the R_RX_FULL interrupt in IC_INTR_STAT
+//               register.
+//
+//               Reset value: 0x1
+//               0x0 -> RX_FULL interrupt is masked
+//               0x1 -> RX_FULL interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_RX_FULL_RESET          _u(0x1)
+#define I2C_IC_INTR_MASK_M_RX_FULL_BITS           _u(0x00000004)
+#define I2C_IC_INTR_MASK_M_RX_FULL_MSB            _u(2)
+#define I2C_IC_INTR_MASK_M_RX_FULL_LSB            _u(2)
+#define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS         "RW"
+#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED  _u(0x0)
+#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_MASK_M_RX_OVER
+// Description : This bit masks the R_RX_OVER interrupt in IC_INTR_STAT
+//               register.
+//
+//               Reset value: 0x1
+//               0x0 -> RX_OVER interrupt is masked
+//               0x1 -> RX_OVER interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_RX_OVER_RESET          _u(0x1)
+#define I2C_IC_INTR_MASK_M_RX_OVER_BITS           _u(0x00000002)
+#define I2C_IC_INTR_MASK_M_RX_OVER_MSB            _u(1)
+#define I2C_IC_INTR_MASK_M_RX_OVER_LSB            _u(1)
+#define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS         "RW"
+#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED  _u(0x0)
+#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_INTR_MASK_M_RX_UNDER
+// Description : This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT
+//               register.
+//
+//               Reset value: 0x1
+//               0x0 -> RX_UNDER interrupt is masked
+//               0x1 -> RX_UNDER interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET          _u(0x1)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS           _u(0x00000001)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB            _u(0)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB            _u(0)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS         "RW"
+#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED  _u(0x0)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED _u(0x1)
+// =============================================================================
+// Register    : I2C_IC_RAW_INTR_STAT
+// Description : I2C Raw Interrupt Status Register
+//
+//               Unlike the IC_INTR_STAT register, these bits are not masked so
+//               they always show the true status of the DW_apb_i2c.
+#define I2C_IC_RAW_INTR_STAT_OFFSET _u(0x00000034)
+#define I2C_IC_RAW_INTR_STAT_BITS   _u(0x00001fff)
+#define I2C_IC_RAW_INTR_STAT_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RAW_INTR_STAT_RESTART_DET
+// Description : Indicates whether a RESTART condition has occurred on the I2C
+//               interface when DW_apb_i2c is operating in Slave mode and the
+//               slave is being addressed. Enabled only when
+//               IC_SLV_RESTART_DET_EN=1.
+//
+//               Note: However, in high-speed mode or during a START BYTE
+//               transfer, the RESTART comes before the address field as per the
+//               I2C protocol. In this case, the slave is not the addressed
+//               slave when the RESTART is issued, therefore DW_apb_i2c does not
+//               generate the RESTART_DET interrupt.
+//
+//               Reset value: 0x0
+//               0x0 -> RESTART_DET interrupt is inactive
+//               0x1 -> RESTART_DET interrupt is active
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET          _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS           _u(0x00001000)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB            _u(12)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB            _u(12)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS         "RO"
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RAW_INTR_STAT_GEN_CALL
+// Description : Set only when a General Call address is received and it is
+//               acknowledged. It stays set until it is cleared either by
+//               disabling DW_apb_i2c or when the CPU reads bit 0 of the
+//               IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data
+//               in the Rx buffer.
+//
+//               Reset value: 0x0
+//               0x0 -> GEN_CALL interrupt is inactive
+//               0x1 -> GEN_CALL interrupt is active
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET          _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS           _u(0x00000800)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB            _u(11)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB            _u(11)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS         "RO"
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RAW_INTR_STAT_START_DET
+// Description : Indicates whether a START or RESTART condition has occurred on
+//               the I2C interface regardless of whether DW_apb_i2c is operating
+//               in slave or master mode.
+//
+//               Reset value: 0x0
+//               0x0 -> START_DET interrupt is inactive
+//               0x1 -> START_DET interrupt is active
+#define I2C_IC_RAW_INTR_STAT_START_DET_RESET          _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_START_DET_BITS           _u(0x00000400)
+#define I2C_IC_RAW_INTR_STAT_START_DET_MSB            _u(10)
+#define I2C_IC_RAW_INTR_STAT_START_DET_LSB            _u(10)
+#define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS         "RO"
+#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RAW_INTR_STAT_STOP_DET
+// Description : Indicates whether a STOP condition has occurred on the I2C
+//               interface regardless of whether DW_apb_i2c is operating in
+//               slave or master mode.
+//
+//               In Slave Mode: - If IC_CON[7]=1'b1  (STOP_DET_IFADDRESSED), the
+//               STOP_DET interrupt will be issued only if slave is addressed.
+//               Note: During a general call address, this slave does not issue
+//               a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the
+//               slave responds to the general call address by generating ACK.
+//               The STOP_DET interrupt is generated only when the transmitted
+//               address matches the slave address (SAR). - If IC_CON[7]=1'b0
+//               (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued
+//               irrespective of whether it is being addressed. In Master Mode:
+//               - If IC_CON[10]=1'b1  (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET
+//               interrupt will be issued only if Master is active. - If
+//               IC_CON[10]=1'b0  (STOP_DET_IFADDRESSED),the STOP_DET interrupt
+//               will be issued irrespective of whether master is active or not.
+//               Reset value: 0x0
+//               0x0 -> STOP_DET interrupt is inactive
+//               0x1 -> STOP_DET interrupt is active
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET          _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS           _u(0x00000200)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB            _u(9)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB            _u(9)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS         "RO"
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RAW_INTR_STAT_ACTIVITY
+// Description : This bit captures DW_apb_i2c activity and stays set until it is
+//               cleared. There are four ways to clear it: - Disabling the
+//               DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the
+//               IC_CLR_INTR register - System reset Once this bit is set, it
+//               stays set unless one of the four methods is used to clear it.
+//               Even if the DW_apb_i2c module is idle, this bit remains set
+//               until cleared, indicating that there was activity on the bus.
+//
+//               Reset value: 0x0
+//               0x0 -> RAW_INTR_ACTIVITY interrupt is inactive
+//               0x1 -> RAW_INTR_ACTIVITY interrupt is active
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET          _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS           _u(0x00000100)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB            _u(8)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB            _u(8)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS         "RO"
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RAW_INTR_STAT_RX_DONE
+// Description : When the DW_apb_i2c is acting as a slave-transmitter, this bit
+//               is set to 1 if the master does not acknowledge a transmitted
+//               byte. This occurs on the last byte of the transmission,
+//               indicating that the transmission is done.
+//
+//               Reset value: 0x0
+//               0x0 -> RX_DONE interrupt is inactive
+//               0x1 -> RX_DONE interrupt is active
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET          _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS           _u(0x00000080)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB            _u(7)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB            _u(7)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS         "RO"
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RAW_INTR_STAT_TX_ABRT
+// Description : This bit indicates if DW_apb_i2c, as an I2C transmitter, is
+//               unable to complete the intended actions on the contents of the
+//               transmit FIFO. This situation can occur both as an I2C master
+//               or an I2C slave, and is referred to as a 'transmit abort'. When
+//               this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates
+//               the reason why the transmit abort takes places.
+//
+//               Note:  The DW_apb_i2c flushes/resets/empties the TX_FIFO and
+//               RX_FIFO whenever there is a transmit abort caused by any of the
+//               events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs
+//               remains in this flushed state until the register IC_CLR_TX_ABRT
+//               is read. Once this read is performed, the Tx FIFO is then ready
+//               to accept more data bytes from the APB interface.
+//
+//               Reset value: 0x0
+//               0x0 -> TX_ABRT interrupt is inactive
+//               0x1 -> TX_ABRT interrupt is active
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET          _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS           _u(0x00000040)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB            _u(6)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB            _u(6)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS         "RO"
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RAW_INTR_STAT_RD_REQ
+// Description : This bit is set to 1 when DW_apb_i2c is acting as a slave and
+//               another I2C master is attempting to read data from DW_apb_i2c.
+//               The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until
+//               this interrupt is serviced, which means that the slave has been
+//               addressed by a remote master that is asking for data to be
+//               transferred. The processor must respond to this interrupt and
+//               then write the requested data to the IC_DATA_CMD register. This
+//               bit is set to 0 just after the processor reads the
+//               IC_CLR_RD_REQ register.
+//
+//               Reset value: 0x0
+//               0x0 -> RD_REQ interrupt is inactive
+//               0x1 -> RD_REQ interrupt is active
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET          _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS           _u(0x00000020)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB            _u(5)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB            _u(5)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS         "RO"
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RAW_INTR_STAT_TX_EMPTY
+// Description : The behavior of the TX_EMPTY interrupt status differs based on
+//               the TX_EMPTY_CTRL selection in the IC_CON register. - When
+//               TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit
+//               buffer is at or below the threshold value set in the IC_TX_TL
+//               register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when
+//               the transmit buffer is at or below the threshold value set in
+//               the IC_TX_TL register and the transmission of the address/data
+//               from the internal shift register for the most recently popped
+//               command is completed. It is automatically cleared by hardware
+//               when the buffer level goes above the threshold. When
+//               IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in
+//               reset. There the TX FIFO looks like it has no data within it,
+//               so this bit is set to 1, provided there is activity in the
+//               master or slave state machines. When there is no longer any
+//               activity, then with ic_en=0, this bit is set to 0.
+//
+//               Reset value: 0x0.
+//               0x0 -> TX_EMPTY interrupt is inactive
+//               0x1 -> TX_EMPTY interrupt is active
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET          _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS           _u(0x00000010)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB            _u(4)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB            _u(4)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS         "RO"
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RAW_INTR_STAT_TX_OVER
+// Description : Set during transmit if the transmit buffer is filled to
+//               IC_TX_BUFFER_DEPTH and the processor attempts to issue another
+//               I2C command by writing to the IC_DATA_CMD register. When the
+//               module is disabled, this bit keeps its level until the master
+//               or slave state machines go into idle, and when ic_en goes to 0,
+//               this interrupt is cleared.
+//
+//               Reset value: 0x0
+//               0x0 -> TX_OVER interrupt is inactive
+//               0x1 -> TX_OVER interrupt is active
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET          _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS           _u(0x00000008)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB            _u(3)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB            _u(3)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS         "RO"
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RAW_INTR_STAT_RX_FULL
+// Description : Set when the receive buffer reaches or goes above the RX_TL
+//               threshold in the IC_RX_TL register. It is automatically cleared
+//               by hardware when buffer level goes below the threshold. If the
+//               module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and
+//               held in reset; therefore the RX FIFO is not full. So this bit
+//               is cleared once the IC_ENABLE bit 0 is programmed with a 0,
+//               regardless of the activity that continues.
+//
+//               Reset value: 0x0
+//               0x0 -> RX_FULL interrupt is inactive
+//               0x1 -> RX_FULL interrupt is active
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET          _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS           _u(0x00000004)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB            _u(2)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB            _u(2)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS         "RO"
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RAW_INTR_STAT_RX_OVER
+// Description : Set if the receive buffer is completely filled to
+//               IC_RX_BUFFER_DEPTH and an additional byte is received from an
+//               external I2C device. The DW_apb_i2c acknowledges this, but any
+//               data bytes received after the FIFO is full are lost. If the
+//               module is disabled (IC_ENABLE[0]=0), this bit keeps its level
+//               until the master or slave state machines go into idle, and when
+//               ic_en goes to 0, this interrupt is cleared.
+//
+//               Note:  If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL)
+//               is programmed to HIGH, then the RX_OVER interrupt never occurs,
+//               because the Rx FIFO never overflows.
+//
+//               Reset value: 0x0
+//               0x0 -> RX_OVER interrupt is inactive
+//               0x1 -> RX_OVER interrupt is active
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET          _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS           _u(0x00000002)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB            _u(1)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB            _u(1)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS         "RO"
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RAW_INTR_STAT_RX_UNDER
+// Description : Set if the processor attempts to read the receive buffer when
+//               it is empty by reading from the IC_DATA_CMD register. If the
+//               module is disabled (IC_ENABLE[0]=0), this bit keeps its level
+//               until the master or slave state machines go into idle, and when
+//               ic_en goes to 0, this interrupt is cleared.
+//
+//               Reset value: 0x0
+//               0x0 -> RX_UNDER interrupt is inactive
+//               0x1 -> RX_UNDER interrupt is active
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET          _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS           _u(0x00000001)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB            _u(0)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB            _u(0)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS         "RO"
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE   _u(0x1)
+// =============================================================================
+// Register    : I2C_IC_RX_TL
+// Description : I2C Receive FIFO Threshold Register
+#define I2C_IC_RX_TL_OFFSET _u(0x00000038)
+#define I2C_IC_RX_TL_BITS   _u(0x000000ff)
+#define I2C_IC_RX_TL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RX_TL_RX_TL
+// Description : Receive FIFO Threshold Level.
+//
+//               Controls the level of entries (or above) that triggers the
+//               RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The
+//               valid range is 0-255, with the additional restriction that
+//               hardware does not allow this value to be set to a value larger
+//               than the depth of the buffer. If an attempt is made to do that,
+//               the actual value set will be the maximum depth of the buffer. A
+//               value of 0 sets the threshold for 1 entry, and a value of 255
+//               sets the threshold for 256 entries.
+#define I2C_IC_RX_TL_RX_TL_RESET  _u(0x00)
+#define I2C_IC_RX_TL_RX_TL_BITS   _u(0x000000ff)
+#define I2C_IC_RX_TL_RX_TL_MSB    _u(7)
+#define I2C_IC_RX_TL_RX_TL_LSB    _u(0)
+#define I2C_IC_RX_TL_RX_TL_ACCESS "RW"
+// =============================================================================
+// Register    : I2C_IC_TX_TL
+// Description : I2C Transmit FIFO Threshold Register
+#define I2C_IC_TX_TL_OFFSET _u(0x0000003c)
+#define I2C_IC_TX_TL_BITS   _u(0x000000ff)
+#define I2C_IC_TX_TL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_TL_TX_TL
+// Description : Transmit FIFO Threshold Level.
+//
+//               Controls the level of entries (or below) that trigger the
+//               TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The
+//               valid range is 0-255, with the additional restriction that it
+//               may not be set to value larger than the depth of the buffer. If
+//               an attempt is made to do that, the actual value set will be the
+//               maximum depth of the buffer. A value of 0 sets the threshold
+//               for 0 entries, and a value of 255 sets the threshold for 255
+//               entries.
+#define I2C_IC_TX_TL_TX_TL_RESET  _u(0x00)
+#define I2C_IC_TX_TL_TX_TL_BITS   _u(0x000000ff)
+#define I2C_IC_TX_TL_TX_TL_MSB    _u(7)
+#define I2C_IC_TX_TL_TX_TL_LSB    _u(0)
+#define I2C_IC_TX_TL_TX_TL_ACCESS "RW"
+// =============================================================================
+// Register    : I2C_IC_CLR_INTR
+// Description : Clear Combined and Individual Interrupt Register
+#define I2C_IC_CLR_INTR_OFFSET _u(0x00000040)
+#define I2C_IC_CLR_INTR_BITS   _u(0x00000001)
+#define I2C_IC_CLR_INTR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CLR_INTR_CLR_INTR
+// Description : Read this register to clear the combined interrupt, all
+//               individual interrupts, and the IC_TX_ABRT_SOURCE register. This
+//               bit does not clear hardware clearable interrupts but software
+//               clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE
+//               register for an exception to clearing IC_TX_ABRT_SOURCE.
+//
+//               Reset value: 0x0
+#define I2C_IC_CLR_INTR_CLR_INTR_RESET  _u(0x0)
+#define I2C_IC_CLR_INTR_CLR_INTR_BITS   _u(0x00000001)
+#define I2C_IC_CLR_INTR_CLR_INTR_MSB    _u(0)
+#define I2C_IC_CLR_INTR_CLR_INTR_LSB    _u(0)
+#define I2C_IC_CLR_INTR_CLR_INTR_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_CLR_RX_UNDER
+// Description : Clear RX_UNDER Interrupt Register
+#define I2C_IC_CLR_RX_UNDER_OFFSET _u(0x00000044)
+#define I2C_IC_CLR_RX_UNDER_BITS   _u(0x00000001)
+#define I2C_IC_CLR_RX_UNDER_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER
+// Description : Read this register to clear the RX_UNDER interrupt (bit 0) of
+//               the IC_RAW_INTR_STAT register.
+//
+//               Reset value: 0x0
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET  _u(0x0)
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_BITS   _u(0x00000001)
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB    _u(0)
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB    _u(0)
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_CLR_RX_OVER
+// Description : Clear RX_OVER Interrupt Register
+#define I2C_IC_CLR_RX_OVER_OFFSET _u(0x00000048)
+#define I2C_IC_CLR_RX_OVER_BITS   _u(0x00000001)
+#define I2C_IC_CLR_RX_OVER_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CLR_RX_OVER_CLR_RX_OVER
+// Description : Read this register to clear the RX_OVER interrupt (bit 1) of
+//               the IC_RAW_INTR_STAT register.
+//
+//               Reset value: 0x0
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET  _u(0x0)
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_BITS   _u(0x00000001)
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB    _u(0)
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB    _u(0)
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_CLR_TX_OVER
+// Description : Clear TX_OVER Interrupt Register
+#define I2C_IC_CLR_TX_OVER_OFFSET _u(0x0000004c)
+#define I2C_IC_CLR_TX_OVER_BITS   _u(0x00000001)
+#define I2C_IC_CLR_TX_OVER_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CLR_TX_OVER_CLR_TX_OVER
+// Description : Read this register to clear the TX_OVER interrupt (bit 3) of
+//               the IC_RAW_INTR_STAT register.
+//
+//               Reset value: 0x0
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET  _u(0x0)
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_BITS   _u(0x00000001)
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB    _u(0)
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB    _u(0)
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_CLR_RD_REQ
+// Description : Clear RD_REQ Interrupt Register
+#define I2C_IC_CLR_RD_REQ_OFFSET _u(0x00000050)
+#define I2C_IC_CLR_RD_REQ_BITS   _u(0x00000001)
+#define I2C_IC_CLR_RD_REQ_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CLR_RD_REQ_CLR_RD_REQ
+// Description : Read this register to clear the RD_REQ interrupt (bit 5) of the
+//               IC_RAW_INTR_STAT register.
+//
+//               Reset value: 0x0
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET  _u(0x0)
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_BITS   _u(0x00000001)
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB    _u(0)
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB    _u(0)
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_CLR_TX_ABRT
+// Description : Clear TX_ABRT Interrupt Register
+#define I2C_IC_CLR_TX_ABRT_OFFSET _u(0x00000054)
+#define I2C_IC_CLR_TX_ABRT_BITS   _u(0x00000001)
+#define I2C_IC_CLR_TX_ABRT_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT
+// Description : Read this register to clear the TX_ABRT interrupt (bit 6) of
+//               the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE
+//               register. This also releases the TX FIFO from the flushed/reset
+//               state, allowing more writes to the TX FIFO. Refer to Bit 9 of
+//               the IC_TX_ABRT_SOURCE register for an exception to clearing
+//               IC_TX_ABRT_SOURCE.
+//
+//               Reset value: 0x0
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET  _u(0x0)
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_BITS   _u(0x00000001)
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB    _u(0)
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB    _u(0)
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_CLR_RX_DONE
+// Description : Clear RX_DONE Interrupt Register
+#define I2C_IC_CLR_RX_DONE_OFFSET _u(0x00000058)
+#define I2C_IC_CLR_RX_DONE_BITS   _u(0x00000001)
+#define I2C_IC_CLR_RX_DONE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CLR_RX_DONE_CLR_RX_DONE
+// Description : Read this register to clear the RX_DONE interrupt (bit 7) of
+//               the IC_RAW_INTR_STAT register.
+//
+//               Reset value: 0x0
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET  _u(0x0)
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_BITS   _u(0x00000001)
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB    _u(0)
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB    _u(0)
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_CLR_ACTIVITY
+// Description : Clear ACTIVITY Interrupt Register
+#define I2C_IC_CLR_ACTIVITY_OFFSET _u(0x0000005c)
+#define I2C_IC_CLR_ACTIVITY_BITS   _u(0x00000001)
+#define I2C_IC_CLR_ACTIVITY_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY
+// Description : Reading this register clears the ACTIVITY interrupt if the I2C
+//               is not active anymore. If the I2C module is still active on the
+//               bus, the ACTIVITY interrupt bit continues to be set. It is
+//               automatically cleared by hardware if the module is disabled and
+//               if there is no further activity on the bus. The value read from
+//               this register to get status of the ACTIVITY interrupt (bit 8)
+//               of the IC_RAW_INTR_STAT register.
+//
+//               Reset value: 0x0
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET  _u(0x0)
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_BITS   _u(0x00000001)
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB    _u(0)
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB    _u(0)
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_CLR_STOP_DET
+// Description : Clear STOP_DET Interrupt Register
+#define I2C_IC_CLR_STOP_DET_OFFSET _u(0x00000060)
+#define I2C_IC_CLR_STOP_DET_BITS   _u(0x00000001)
+#define I2C_IC_CLR_STOP_DET_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CLR_STOP_DET_CLR_STOP_DET
+// Description : Read this register to clear the STOP_DET interrupt (bit 9) of
+//               the IC_RAW_INTR_STAT register.
+//
+//               Reset value: 0x0
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET  _u(0x0)
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_BITS   _u(0x00000001)
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB    _u(0)
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB    _u(0)
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_CLR_START_DET
+// Description : Clear START_DET Interrupt Register
+#define I2C_IC_CLR_START_DET_OFFSET _u(0x00000064)
+#define I2C_IC_CLR_START_DET_BITS   _u(0x00000001)
+#define I2C_IC_CLR_START_DET_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CLR_START_DET_CLR_START_DET
+// Description : Read this register to clear the START_DET interrupt (bit 10) of
+//               the IC_RAW_INTR_STAT register.
+//
+//               Reset value: 0x0
+#define I2C_IC_CLR_START_DET_CLR_START_DET_RESET  _u(0x0)
+#define I2C_IC_CLR_START_DET_CLR_START_DET_BITS   _u(0x00000001)
+#define I2C_IC_CLR_START_DET_CLR_START_DET_MSB    _u(0)
+#define I2C_IC_CLR_START_DET_CLR_START_DET_LSB    _u(0)
+#define I2C_IC_CLR_START_DET_CLR_START_DET_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_CLR_GEN_CALL
+// Description : Clear GEN_CALL Interrupt Register
+#define I2C_IC_CLR_GEN_CALL_OFFSET _u(0x00000068)
+#define I2C_IC_CLR_GEN_CALL_BITS   _u(0x00000001)
+#define I2C_IC_CLR_GEN_CALL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL
+// Description : Read this register to clear the GEN_CALL interrupt (bit 11) of
+//               IC_RAW_INTR_STAT register.
+//
+//               Reset value: 0x0
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET  _u(0x0)
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_BITS   _u(0x00000001)
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB    _u(0)
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB    _u(0)
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_ENABLE
+// Description : I2C Enable Register
+#define I2C_IC_ENABLE_OFFSET _u(0x0000006c)
+#define I2C_IC_ENABLE_BITS   _u(0x00000007)
+#define I2C_IC_ENABLE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_ENABLE_TX_CMD_BLOCK
+// Description : In Master mode: - 1'b1: Blocks the transmission of data on I2C
+//               bus even if Tx FIFO has data to transmit. - 1'b0: The
+//               transmission of data starts on I2C bus automatically, as soon
+//               as the first data is available in the Tx FIFO. Note: To block
+//               the execution of Master commands, set the TX_CMD_BLOCK bit only
+//               when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle
+//               state (IC_STATUS[5] == 0). Any further commands put in the Tx
+//               FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset
+//               value:  IC_TX_CMD_BLOCK_DEFAULT
+//               0x0 -> Tx Command execution not blocked
+//               0x1 -> Tx Command execution blocked
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET             _u(0x0)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS              _u(0x00000004)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB               _u(2)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB               _u(2)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS            "RW"
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED _u(0x0)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED     _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_ENABLE_ABORT
+// Description : When set, the controller initiates the transfer abort. - 0:
+//               ABORT not initiated or ABORT done - 1: ABORT operation in
+//               progress The software can abort the I2C transfer in master mode
+//               by setting this bit. The software can set this bit only when
+//               ENABLE is already set; otherwise, the controller ignores any
+//               write to ABORT bit. The software cannot clear the ABORT bit
+//               once set. In response to an ABORT, the controller issues a STOP
+//               and flushes the Tx FIFO after completing the current transfer,
+//               then sets the TX_ABORT interrupt after the abort operation. The
+//               ABORT bit is cleared automatically after the abort operation.
+//
+//               For a detailed description on how to abort I2C transfers, refer
+//               to 'Aborting I2C Transfers'.
+//
+//               Reset value: 0x0
+//               0x0 -> ABORT operation not in progress
+//               0x1 -> ABORT operation in progress
+#define I2C_IC_ENABLE_ABORT_RESET         _u(0x0)
+#define I2C_IC_ENABLE_ABORT_BITS          _u(0x00000002)
+#define I2C_IC_ENABLE_ABORT_MSB           _u(1)
+#define I2C_IC_ENABLE_ABORT_LSB           _u(1)
+#define I2C_IC_ENABLE_ABORT_ACCESS        "RW"
+#define I2C_IC_ENABLE_ABORT_VALUE_DISABLE _u(0x0)
+#define I2C_IC_ENABLE_ABORT_VALUE_ENABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_ENABLE_ENABLE
+// Description : Controls whether the DW_apb_i2c is enabled. - 0: Disables
+//               DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1:
+//               Enables DW_apb_i2c Software can disable DW_apb_i2c while it is
+//               active. However, it is important that care be taken to ensure
+//               that DW_apb_i2c is disabled properly. A recommended procedure
+//               is described in 'Disabling DW_apb_i2c'.
+//
+//               When DW_apb_i2c is disabled, the following occurs: - The TX
+//               FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT
+//               register are still active until DW_apb_i2c goes into IDLE
+//               state. If the module is transmitting, it stops as well as
+//               deletes the contents of the transmit buffer after the current
+//               transfer is complete. If the module is receiving, the
+//               DW_apb_i2c stops the current transfer at the end of the current
+//               byte and does not acknowledge the transfer.
+//
+//               In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE
+//               parameter set to asynchronous (1), there is a two ic_clk delay
+//               when enabling or disabling the DW_apb_i2c. For a detailed
+//               description on how to disable DW_apb_i2c, refer to 'Disabling
+//               DW_apb_i2c'
+//
+//               Reset value: 0x0
+//               0x0 -> I2C is disabled
+//               0x1 -> I2C is enabled
+#define I2C_IC_ENABLE_ENABLE_RESET          _u(0x0)
+#define I2C_IC_ENABLE_ENABLE_BITS           _u(0x00000001)
+#define I2C_IC_ENABLE_ENABLE_MSB            _u(0)
+#define I2C_IC_ENABLE_ENABLE_LSB            _u(0)
+#define I2C_IC_ENABLE_ENABLE_ACCESS         "RW"
+#define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED _u(0x0)
+#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED  _u(0x1)
+// =============================================================================
+// Register    : I2C_IC_STATUS
+// Description : I2C Status Register
+//
+//               This is a read-only register used to indicate the current
+//               transfer status and FIFO status. The status register may be
+//               read at any time. None of the bits in this register request an
+//               interrupt.
+//
+//               When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE
+//               register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set
+//               to 0 When the master or slave state machines goes to idle and
+//               ic_en=0: - Bits 5 and 6 are set to 0
+#define I2C_IC_STATUS_OFFSET _u(0x00000070)
+#define I2C_IC_STATUS_BITS   _u(0x0000007f)
+#define I2C_IC_STATUS_RESET  _u(0x00000006)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_STATUS_SLV_ACTIVITY
+// Description : Slave FSM Activity Status. When the Slave Finite State Machine
+//               (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM
+//               is in IDLE state so the Slave part of DW_apb_i2c is not Active
+//               - 1: Slave FSM is not in IDLE state so the Slave part of
+//               DW_apb_i2c is Active Reset value: 0x0
+//               0x0 -> Slave is idle
+//               0x1 -> Slave not idle
+#define I2C_IC_STATUS_SLV_ACTIVITY_RESET        _u(0x0)
+#define I2C_IC_STATUS_SLV_ACTIVITY_BITS         _u(0x00000040)
+#define I2C_IC_STATUS_SLV_ACTIVITY_MSB          _u(6)
+#define I2C_IC_STATUS_SLV_ACTIVITY_LSB          _u(6)
+#define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS       "RO"
+#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE   _u(0x0)
+#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_STATUS_MST_ACTIVITY
+// Description : Master FSM Activity Status. When the Master Finite State
+//               Machine (FSM) is not in the IDLE state, this bit is set. - 0:
+//               Master FSM is in IDLE state so the Master part of DW_apb_i2c is
+//               not Active - 1: Master FSM is not in IDLE state so the Master
+//               part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is,
+//               ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.
+//
+//               Reset value: 0x0
+//               0x0 -> Master is idle
+//               0x1 -> Master not idle
+#define I2C_IC_STATUS_MST_ACTIVITY_RESET        _u(0x0)
+#define I2C_IC_STATUS_MST_ACTIVITY_BITS         _u(0x00000020)
+#define I2C_IC_STATUS_MST_ACTIVITY_MSB          _u(5)
+#define I2C_IC_STATUS_MST_ACTIVITY_LSB          _u(5)
+#define I2C_IC_STATUS_MST_ACTIVITY_ACCESS       "RO"
+#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE   _u(0x0)
+#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_STATUS_RFF
+// Description : Receive FIFO Completely Full. When the receive FIFO is
+//               completely full, this bit is set. When the receive FIFO
+//               contains one or more empty location, this bit is cleared. - 0:
+//               Receive FIFO is not full - 1: Receive FIFO is full Reset value:
+//               0x0
+//               0x0 -> Rx FIFO not full
+//               0x1 -> Rx FIFO is full
+#define I2C_IC_STATUS_RFF_RESET          _u(0x0)
+#define I2C_IC_STATUS_RFF_BITS           _u(0x00000010)
+#define I2C_IC_STATUS_RFF_MSB            _u(4)
+#define I2C_IC_STATUS_RFF_LSB            _u(4)
+#define I2C_IC_STATUS_RFF_ACCESS         "RO"
+#define I2C_IC_STATUS_RFF_VALUE_NOT_FULL _u(0x0)
+#define I2C_IC_STATUS_RFF_VALUE_FULL     _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_STATUS_RFNE
+// Description : Receive FIFO Not Empty. This bit is set when the receive FIFO
+//               contains one or more entries; it is cleared when the receive
+//               FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is
+//               not empty Reset value: 0x0
+//               0x0 -> Rx FIFO is empty
+//               0x1 -> Rx FIFO not empty
+#define I2C_IC_STATUS_RFNE_RESET           _u(0x0)
+#define I2C_IC_STATUS_RFNE_BITS            _u(0x00000008)
+#define I2C_IC_STATUS_RFNE_MSB             _u(3)
+#define I2C_IC_STATUS_RFNE_LSB             _u(3)
+#define I2C_IC_STATUS_RFNE_ACCESS          "RO"
+#define I2C_IC_STATUS_RFNE_VALUE_EMPTY     _u(0x0)
+#define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_STATUS_TFE
+// Description : Transmit FIFO Completely Empty. When the transmit FIFO is
+//               completely empty, this bit is set. When it contains one or more
+//               valid entries, this bit is cleared. This bit field does not
+//               request an interrupt. - 0: Transmit FIFO is not empty - 1:
+//               Transmit FIFO is empty Reset value: 0x1
+//               0x0 -> Tx FIFO not empty
+//               0x1 -> Tx FIFO is empty
+#define I2C_IC_STATUS_TFE_RESET           _u(0x1)
+#define I2C_IC_STATUS_TFE_BITS            _u(0x00000004)
+#define I2C_IC_STATUS_TFE_MSB             _u(2)
+#define I2C_IC_STATUS_TFE_LSB             _u(2)
+#define I2C_IC_STATUS_TFE_ACCESS          "RO"
+#define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY _u(0x0)
+#define I2C_IC_STATUS_TFE_VALUE_EMPTY     _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_STATUS_TFNF
+// Description : Transmit FIFO Not Full. Set when the transmit FIFO contains one
+//               or more empty locations, and is cleared when the FIFO is full.
+//               - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset
+//               value: 0x1
+//               0x0 -> Tx FIFO is full
+//               0x1 -> Tx FIFO not full
+#define I2C_IC_STATUS_TFNF_RESET          _u(0x1)
+#define I2C_IC_STATUS_TFNF_BITS           _u(0x00000002)
+#define I2C_IC_STATUS_TFNF_MSB            _u(1)
+#define I2C_IC_STATUS_TFNF_LSB            _u(1)
+#define I2C_IC_STATUS_TFNF_ACCESS         "RO"
+#define I2C_IC_STATUS_TFNF_VALUE_FULL     _u(0x0)
+#define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_STATUS_ACTIVITY
+// Description : I2C Activity Status. Reset value: 0x0
+//               0x0 -> I2C is idle
+//               0x1 -> I2C is active
+#define I2C_IC_STATUS_ACTIVITY_RESET          _u(0x0)
+#define I2C_IC_STATUS_ACTIVITY_BITS           _u(0x00000001)
+#define I2C_IC_STATUS_ACTIVITY_MSB            _u(0)
+#define I2C_IC_STATUS_ACTIVITY_LSB            _u(0)
+#define I2C_IC_STATUS_ACTIVITY_ACCESS         "RO"
+#define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE   _u(0x1)
+// =============================================================================
+// Register    : I2C_IC_TXFLR
+// Description : I2C Transmit FIFO Level Register This register contains the
+//               number of valid data entries in the transmit FIFO buffer. It is
+//               cleared whenever: - The I2C is disabled - There is a transmit
+//               abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT
+//               register - The slave bulk transmit mode is aborted The register
+//               increments whenever data is placed into the transmit FIFO and
+//               decrements when data is taken from the transmit FIFO.
+#define I2C_IC_TXFLR_OFFSET _u(0x00000074)
+#define I2C_IC_TXFLR_BITS   _u(0x0000001f)
+#define I2C_IC_TXFLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TXFLR_TXFLR
+// Description : Transmit FIFO Level. Contains the number of valid data entries
+//               in the transmit FIFO.
+//
+//               Reset value: 0x0
+#define I2C_IC_TXFLR_TXFLR_RESET  _u(0x00)
+#define I2C_IC_TXFLR_TXFLR_BITS   _u(0x0000001f)
+#define I2C_IC_TXFLR_TXFLR_MSB    _u(4)
+#define I2C_IC_TXFLR_TXFLR_LSB    _u(0)
+#define I2C_IC_TXFLR_TXFLR_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_RXFLR
+// Description : I2C Receive FIFO Level Register This register contains the
+//               number of valid data entries in the receive FIFO buffer. It is
+//               cleared whenever: - The I2C is disabled - Whenever there is a
+//               transmit abort caused by any of the events tracked in
+//               IC_TX_ABRT_SOURCE The register increments whenever data is
+//               placed into the receive FIFO and decrements when data is taken
+//               from the receive FIFO.
+#define I2C_IC_RXFLR_OFFSET _u(0x00000078)
+#define I2C_IC_RXFLR_BITS   _u(0x0000001f)
+#define I2C_IC_RXFLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_RXFLR_RXFLR
+// Description : Receive FIFO Level. Contains the number of valid data entries
+//               in the receive FIFO.
+//
+//               Reset value: 0x0
+#define I2C_IC_RXFLR_RXFLR_RESET  _u(0x00)
+#define I2C_IC_RXFLR_RXFLR_BITS   _u(0x0000001f)
+#define I2C_IC_RXFLR_RXFLR_MSB    _u(4)
+#define I2C_IC_RXFLR_RXFLR_LSB    _u(0)
+#define I2C_IC_RXFLR_RXFLR_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_SDA_HOLD
+// Description : I2C SDA Hold Time Length Register
+//
+//               The bits [15:0] of this register are used to control the hold
+//               time of SDA during transmit in both slave and master mode
+//               (after SCL goes from HIGH to LOW).
+//
+//               The bits [23:16] of this register are used to extend the SDA
+//               transition (if any) whenever SCL is HIGH in the receiver in
+//               either master or slave mode.
+//
+//               Writes to this register succeed only when IC_ENABLE[0]=0.
+//
+//               The values in this register are in units of ic_clk period. The
+//               value programmed in IC_SDA_TX_HOLD must be greater than the
+//               minimum hold time in each mode (one cycle in master mode, seven
+//               cycles in slave mode) for the value to be implemented.
+//
+//               The programmed SDA hold time during transmit (IC_SDA_TX_HOLD)
+//               cannot exceed at any time the duration of the low part of scl.
+//               Therefore the programmed value cannot be larger than
+//               N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of
+//               the scl period measured in ic_clk cycles.
+#define I2C_IC_SDA_HOLD_OFFSET _u(0x0000007c)
+#define I2C_IC_SDA_HOLD_BITS   _u(0x00ffffff)
+#define I2C_IC_SDA_HOLD_RESET  _u(0x00000001)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD
+// Description : Sets the required SDA hold time in units of ic_clk period, when
+//               DW_apb_i2c acts as a receiver.
+//
+//               Reset value: IC_DEFAULT_SDA_HOLD[23:16].
+#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET  _u(0x00)
+#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_BITS   _u(0x00ff0000)
+#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB    _u(23)
+#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB    _u(16)
+#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD
+// Description : Sets the required SDA hold time in units of ic_clk period, when
+//               DW_apb_i2c acts as a transmitter.
+//
+//               Reset value: IC_DEFAULT_SDA_HOLD[15:0].
+#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET  _u(0x0001)
+#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS   _u(0x0000ffff)
+#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB    _u(15)
+#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB    _u(0)
+#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_ACCESS "RW"
+// =============================================================================
+// Register    : I2C_IC_TX_ABRT_SOURCE
+// Description : I2C Transmit Abort Source Register
+//
+//               This register has 32 bits that indicate the source of the
+//               TX_ABRT bit. Except for Bit 9, this register is cleared
+//               whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR
+//               register is read. To clear Bit 9, the source of the
+//               ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled
+//               (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or
+//               the GC_OR_START bit must be cleared (IC_TAR[10]).
+//
+//               Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this
+//               bit can be cleared in the same manner as other bits in this
+//               register. If the source of the ABRT_SBYTE_NORSTRT is not fixed
+//               before attempting to clear this bit, Bit 9 clears for one cycle
+//               and is then re-asserted.
+#define I2C_IC_TX_ABRT_SOURCE_OFFSET _u(0x00000080)
+#define I2C_IC_TX_ABRT_SOURCE_BITS   _u(0xff81ffff)
+#define I2C_IC_TX_ABRT_SOURCE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT
+// Description : This field indicates the number of Tx FIFO Data Commands which
+//               are flushed due to TX_ABRT interrupt. It is cleared whenever
+//               I2C is disabled.
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master-Transmitter or Slave-Transmitter
+#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET  _u(0x000)
+#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_BITS   _u(0xff800000)
+#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB    _u(31)
+#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB    _u(23)
+#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT
+// Description : This is a master-mode-only bit. Master has detected the
+//               transfer abort (IC_ENABLE[1])
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master-Transmitter
+//               0x0 -> Transfer abort detected by master- scenario not present
+//               0x1 -> Transfer abort detected by master
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET                          _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS                           _u(0x00010000)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB                            _u(16)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB                            _u(16)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS                         "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID      _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX
+// Description : 1: When the processor side responds to a slave mode request for
+//               data to be transmitted to a remote master and user writes a 1
+//               in CMD (bit 8) of IC_DATA_CMD register.
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Slave-Transmitter
+//               0x0 -> Slave trying to transmit to remote master in read mode-
+//               scenario not present
+//               0x1 -> Slave trying to transmit to remote master in read mode
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET                           _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS                            _u(0x00008000)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB                             _u(15)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB                             _u(15)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS                          "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID      _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST
+// Description : This field indicates that a Slave has lost the bus while
+//               transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is
+//               set at the same time. Note:  Even though the slave never 'owns'
+//               the bus, something could go wrong on the bus. This is a fail
+//               safe check. For instance, during a data transmission at the
+//               low-to-high transition of SCL, if what is on the data bus is
+//               not what is supposed to be transmitted, then DW_apb_i2c no
+//               longer own the bus.
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Slave-Transmitter
+//               0x0 -> Slave lost arbitration to remote master- scenario not
+//               present
+//               0x1 -> Slave lost arbitration to remote master
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET                            _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS                             _u(0x00004000)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB                              _u(14)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB                              _u(14)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS                           "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID      _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO
+// Description : This field specifies that the Slave has received a read command
+//               and some data exists in the TX FIFO, so the slave issues a
+//               TX_ABRT interrupt to flush old data in TX FIFO.
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Slave-Transmitter
+//               0x0 -> Slave flushes existing data in TX-FIFO upon getting read
+//               command- scenario not present
+//               0x1 -> Slave flushes existing data in TX-FIFO upon getting read
+//               command
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET                                _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS                                 _u(0x00002000)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB                                  _u(13)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB                                  _u(13)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS                               "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID      _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ARB_LOST
+// Description : This field specifies that the Master has lost arbitration, or
+//               if IC_TX_ABRT_SOURCE[14] is also set, then the slave
+//               transmitter has lost arbitration.
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master-Transmitter or Slave-Transmitter
+//               0x0 -> Master or Slave-Transmitter lost arbitration- scenario
+//               not present
+//               0x1 -> Master or Slave-Transmitter lost arbitration
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET                     _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS                      _u(0x00001000)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB                       _u(12)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB                       _u(12)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS                    "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID      _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS
+// Description : This field indicates that the User tries to initiate a Master
+//               operation with the Master mode disabled.
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver
+//               0x0 -> User initiating master operation when MASTER disabled-
+//               scenario not present
+//               0x1 -> User initiating master operation when MASTER disabled
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET                           _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS                            _u(0x00000800)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB                             _u(11)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB                             _u(11)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS                          "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID      _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT
+// Description : This field indicates that the restart is disabled
+//               (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read
+//               command in 10-bit addressing mode.
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master-Receiver
+//               0x0 -> Master not trying to read in 10Bit addressing mode when
+//               RESTART disabled
+//               0x1 -> Master trying to read in 10Bit addressing mode when
+//               RESTART disabled
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET                       _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS                        _u(0x00000400)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB                         _u(10)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB                         _u(10)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS                      "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID      _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT
+// Description : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be
+//               fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL
+//               bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must
+//               be cleared (IC_TAR[10]). Once the source of the
+//               ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in
+//               the same manner as other bits in this register. If the source
+//               of the ABRT_SBYTE_NORSTRT is not fixed before attempting to
+//               clear this bit, bit 9 clears for one cycle and then gets
+//               reasserted. When this field is set to 1, the restart is
+//               disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is
+//               trying to send a START Byte.
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master
+//               0x0 -> User trying to send START byte when RESTART disabled-
+//               scenario not present
+//               0x1 -> User trying to send START byte when RESTART disabled
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET                              _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS                               _u(0x00000200)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB                                _u(9)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB                                _u(9)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS                             "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID      _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT
+// Description : This field indicates that the restart is disabled
+//               (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to
+//               use the master to transfer data in High Speed mode.
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver
+//               0x0 -> User trying to switch Master to HS mode when RESTART
+//               disabled- scenario not present
+//               0x1 -> User trying to switch Master to HS mode when RESTART
+//               disabled
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET                           _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS                            _u(0x00000100)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB                             _u(8)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB                             _u(8)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS                          "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID      _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET
+// Description : This field indicates that the Master has sent a START Byte and
+//               the START Byte was acknowledged (wrong behavior).
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master
+//               0x0 -> ACK detected for START byte- scenario not present
+//               0x1 -> ACK detected for START byte
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET                             _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS                              _u(0x00000080)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB                               _u(7)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB                               _u(7)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS                            "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID      _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET
+// Description : This field indicates that the Master is in High Speed mode and
+//               the High Speed Master code was acknowledged (wrong behavior).
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master
+//               0x0 -> HS Master code ACKed in HS Mode- scenario not present
+//               0x1 -> HS Master code ACKed in HS Mode
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET                       _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS                        _u(0x00000040)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB                         _u(6)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB                         _u(6)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS                      "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID      _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ
+// Description : This field indicates that DW_apb_i2c in the master mode has
+//               sent a General Call but the user programmed the byte following
+//               the General Call to be a read from the bus (IC_DATA_CMD[9] is
+//               set to 1).
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master-Transmitter
+//               0x0 -> GCALL is followed by read from bus-scenario not present
+//               0x1 -> GCALL is followed by read from bus
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET                           _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS                            _u(0x00000020)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB                             _u(5)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB                             _u(5)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS                          "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID      _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK
+// Description : This field indicates that DW_apb_i2c in master mode has sent a
+//               General Call and no slave on the bus acknowledged the General
+//               Call.
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master-Transmitter
+//               0x0 -> GCALL not ACKed by any slave-scenario not present
+//               0x1 -> GCALL not ACKed by any slave
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET                            _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS                             _u(0x00000010)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB                              _u(4)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB                              _u(4)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS                           "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID      _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK
+// Description : This field indicates the master-mode only bit. When the master
+//               receives an acknowledgement for the address, but when it sends
+//               data byte(s) following the address, it did not receive an
+//               acknowledge from the remote slave(s).
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master-Transmitter
+//               0x0 -> Transmitted data non-ACKed by addressed slave-scenario
+//               not present
+//               0x1 -> Transmitted data not ACKed by addressed slave
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET                             _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS                              _u(0x00000008)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB                               _u(3)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB                               _u(3)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS                            "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID      _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK
+// Description : This field indicates that the Master is in 10-bit address mode
+//               and that the second address byte of the 10-bit address was not
+//               acknowledged by any slave.
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver
+//               0x0 -> This abort is not generated
+//               0x1 -> Byte 2 of 10Bit Address not ACKed by any slave
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET          _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS           _u(0x00000004)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB            _u(2)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB            _u(2)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS         "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK
+// Description : This field indicates that the Master is in 10-bit address mode
+//               and the first 10-bit address byte was not acknowledged by any
+//               slave.
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver
+//               0x0 -> This abort is not generated
+//               0x1 -> Byte 1 of 10Bit Address not ACKed by any slave
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET          _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS           _u(0x00000002)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB            _u(1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB            _u(1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS         "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK
+// Description : This field indicates that the Master is in 7-bit addressing
+//               mode and the address sent was not acknowledged by any slave.
+//
+//               Reset value: 0x0
+//
+//               Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver
+//               0x0 -> This abort is not generated
+//               0x1 -> This abort is generated because of NOACK for 7-bit
+//               address
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET          _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS           _u(0x00000001)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB            _u(0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB            _u(0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS         "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE   _u(0x1)
+// =============================================================================
+// Register    : I2C_IC_SLV_DATA_NACK_ONLY
+// Description : Generate Slave Data NACK Register
+//
+//               The register is used to generate a NACK for the data part of a
+//               transfer when DW_apb_i2c is acting as a slave-receiver. This
+//               register only exists when the IC_SLV_DATA_NACK_ONLY parameter
+//               is set to 1. When this parameter disabled, this register does
+//               not exist and writing to the register's address has no effect.
+//
+//               A write can occur on this register if both of the following
+//               conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0)
+//               - Slave part is inactive (IC_STATUS[6] = 0) Note: The
+//               IC_STATUS[6] is a register read-back location for the internal
+//               slv_activity signal; the user should poll this before writing
+//               the ic_slv_data_nack_only bit.
+#define I2C_IC_SLV_DATA_NACK_ONLY_OFFSET _u(0x00000084)
+#define I2C_IC_SLV_DATA_NACK_ONLY_BITS   _u(0x00000001)
+#define I2C_IC_SLV_DATA_NACK_ONLY_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_SLV_DATA_NACK_ONLY_NACK
+// Description : Generate NACK. This NACK generation only occurs when DW_apb_i2c
+//               is a slave-receiver. If this register is set to a value of 1,
+//               it can only generate a NACK after a data byte is received;
+//               hence, the data transfer is aborted and the data received is
+//               not pushed to the receive buffer.
+//
+//               When the register is set to a value of 0, it generates
+//               NACK/ACK, depending on normal criteria. - 1: generate NACK
+//               after data byte received - 0: generate NACK/ACK normally Reset
+//               value: 0x0
+//               0x0 -> Slave receiver generates NACK normally
+//               0x1 -> Slave receiver generates NACK upon data reception only
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET          _u(0x0)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS           _u(0x00000001)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB            _u(0)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB            _u(0)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS         "RW"
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED _u(0x0)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED  _u(0x1)
+// =============================================================================
+// Register    : I2C_IC_DMA_CR
+// Description : DMA Control Register
+//
+//               The register is used to enable the DMA Controller interface
+//               operation. There is a separate bit for transmit and receive.
+//               This can be programmed regardless of the state of IC_ENABLE.
+#define I2C_IC_DMA_CR_OFFSET _u(0x00000088)
+#define I2C_IC_DMA_CR_BITS   _u(0x00000003)
+#define I2C_IC_DMA_CR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_DMA_CR_TDMAE
+// Description : Transmit DMA Enable. This bit enables/disables the transmit
+//               FIFO DMA channel. Reset value: 0x0
+//               0x0 -> transmit FIFO DMA channel disabled
+//               0x1 -> Transmit FIFO DMA channel enabled
+#define I2C_IC_DMA_CR_TDMAE_RESET          _u(0x0)
+#define I2C_IC_DMA_CR_TDMAE_BITS           _u(0x00000002)
+#define I2C_IC_DMA_CR_TDMAE_MSB            _u(1)
+#define I2C_IC_DMA_CR_TDMAE_LSB            _u(1)
+#define I2C_IC_DMA_CR_TDMAE_ACCESS         "RW"
+#define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED _u(0x0)
+#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED  _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_DMA_CR_RDMAE
+// Description : Receive DMA Enable. This bit enables/disables the receive FIFO
+//               DMA channel. Reset value: 0x0
+//               0x0 -> Receive FIFO DMA channel disabled
+//               0x1 -> Receive FIFO DMA channel enabled
+#define I2C_IC_DMA_CR_RDMAE_RESET          _u(0x0)
+#define I2C_IC_DMA_CR_RDMAE_BITS           _u(0x00000001)
+#define I2C_IC_DMA_CR_RDMAE_MSB            _u(0)
+#define I2C_IC_DMA_CR_RDMAE_LSB            _u(0)
+#define I2C_IC_DMA_CR_RDMAE_ACCESS         "RW"
+#define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED _u(0x0)
+#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED  _u(0x1)
+// =============================================================================
+// Register    : I2C_IC_DMA_TDLR
+// Description : DMA Transmit Data Level Register
+#define I2C_IC_DMA_TDLR_OFFSET _u(0x0000008c)
+#define I2C_IC_DMA_TDLR_BITS   _u(0x0000000f)
+#define I2C_IC_DMA_TDLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_DMA_TDLR_DMATDL
+// Description : Transmit Data Level. This bit field controls the level at which
+//               a DMA request is made by the transmit logic. It is equal to the
+//               watermark level; that is, the dma_tx_req signal is generated
+//               when the number of valid data entries in the transmit FIFO is
+//               equal to or below this field value, and TDMAE = 1.
+//
+//               Reset value: 0x0
+#define I2C_IC_DMA_TDLR_DMATDL_RESET  _u(0x0)
+#define I2C_IC_DMA_TDLR_DMATDL_BITS   _u(0x0000000f)
+#define I2C_IC_DMA_TDLR_DMATDL_MSB    _u(3)
+#define I2C_IC_DMA_TDLR_DMATDL_LSB    _u(0)
+#define I2C_IC_DMA_TDLR_DMATDL_ACCESS "RW"
+// =============================================================================
+// Register    : I2C_IC_DMA_RDLR
+// Description : I2C Receive Data Level Register
+#define I2C_IC_DMA_RDLR_OFFSET _u(0x00000090)
+#define I2C_IC_DMA_RDLR_BITS   _u(0x0000000f)
+#define I2C_IC_DMA_RDLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_DMA_RDLR_DMARDL
+// Description : Receive Data Level. This bit field controls the level at which
+//               a DMA request is made by the receive logic. The watermark level
+//               = DMARDL+1; that is, dma_rx_req is generated when the number of
+//               valid data entries in the receive FIFO is equal to or more than
+//               this field value + 1, and RDMAE =1. For instance, when DMARDL
+//               is 0, then dma_rx_req is asserted when 1 or more data entries
+//               are present in the receive FIFO.
+//
+//               Reset value: 0x0
+#define I2C_IC_DMA_RDLR_DMARDL_RESET  _u(0x0)
+#define I2C_IC_DMA_RDLR_DMARDL_BITS   _u(0x0000000f)
+#define I2C_IC_DMA_RDLR_DMARDL_MSB    _u(3)
+#define I2C_IC_DMA_RDLR_DMARDL_LSB    _u(0)
+#define I2C_IC_DMA_RDLR_DMARDL_ACCESS "RW"
+// =============================================================================
+// Register    : I2C_IC_SDA_SETUP
+// Description : I2C SDA Setup Register
+//
+//               This register controls the amount of time delay (in terms of
+//               number of ic_clk clock periods) introduced in the rising edge
+//               of SCL - relative to SDA changing - when DW_apb_i2c services a
+//               read request in a slave-transmitter operation. The relevant I2C
+//               requirement is tSU:DAT (note 4) as detailed in the I2C Bus
+//               Specification. This register must be programmed with a value
+//               equal to or greater than 2.
+//
+//               Writes to this register succeed only when IC_ENABLE[0] = 0.
+//
+//               Note: The length of setup time is calculated using
+//               [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires
+//               10 ic_clk periods of setup time, they should program a value of
+//               11. The IC_SDA_SETUP register is only used by the DW_apb_i2c
+//               when operating as a slave transmitter.
+#define I2C_IC_SDA_SETUP_OFFSET _u(0x00000094)
+#define I2C_IC_SDA_SETUP_BITS   _u(0x000000ff)
+#define I2C_IC_SDA_SETUP_RESET  _u(0x00000064)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_SDA_SETUP_SDA_SETUP
+// Description : SDA Setup. It is recommended that if the required delay is
+//               1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP
+//               should be programmed to a value of 11. IC_SDA_SETUP must be
+//               programmed with a minimum value of 2.
+#define I2C_IC_SDA_SETUP_SDA_SETUP_RESET  _u(0x64)
+#define I2C_IC_SDA_SETUP_SDA_SETUP_BITS   _u(0x000000ff)
+#define I2C_IC_SDA_SETUP_SDA_SETUP_MSB    _u(7)
+#define I2C_IC_SDA_SETUP_SDA_SETUP_LSB    _u(0)
+#define I2C_IC_SDA_SETUP_SDA_SETUP_ACCESS "RW"
+// =============================================================================
+// Register    : I2C_IC_ACK_GENERAL_CALL
+// Description : I2C ACK General Call Register
+//
+//               The register controls whether DW_apb_i2c responds with a ACK or
+//               NACK when it receives an I2C General Call address.
+//
+//               This register is applicable only when the DW_apb_i2c is in
+//               slave mode.
+#define I2C_IC_ACK_GENERAL_CALL_OFFSET _u(0x00000098)
+#define I2C_IC_ACK_GENERAL_CALL_BITS   _u(0x00000001)
+#define I2C_IC_ACK_GENERAL_CALL_RESET  _u(0x00000001)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL
+// Description : ACK General Call. When set to 1, DW_apb_i2c responds with a ACK
+//               (by asserting ic_data_oe) when it receives a General Call.
+//               Otherwise, DW_apb_i2c responds with a NACK (by negating
+//               ic_data_oe).
+//               0x0 -> Generate NACK for a General Call
+//               0x1 -> Generate ACK for a General Call
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET          _u(0x1)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS           _u(0x00000001)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB            _u(0)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB            _u(0)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS         "RW"
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED _u(0x0)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED  _u(0x1)
+// =============================================================================
+// Register    : I2C_IC_ENABLE_STATUS
+// Description : I2C Enable Status Register
+//
+//               The register is used to report the DW_apb_i2c hardware status
+//               when the IC_ENABLE[0] register is set from 1 to 0; that is,
+//               when DW_apb_i2c is disabled.
+//
+//               If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0,
+//               and bit 0 is forced to 1.
+//
+//               If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as
+//               soon as bit 0 is read as '0'.
+//
+//               Note: When IC_ENABLE[0] has been set to 0, a delay occurs for
+//               bit 0 to be read as 0 because disabling the DW_apb_i2c depends
+//               on I2C bus activities.
+#define I2C_IC_ENABLE_STATUS_OFFSET _u(0x0000009c)
+#define I2C_IC_ENABLE_STATUS_BITS   _u(0x00000007)
+#define I2C_IC_ENABLE_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST
+// Description : Slave Received Data Lost. This bit indicates if a
+//               Slave-Receiver operation has been aborted with at least one
+//               data byte received from an I2C transfer due to the setting bit
+//               0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is
+//               deemed to have been actively engaged in an aborted I2C transfer
+//               (with matching address) and the data phase of the I2C transfer
+//               has been entered, even though a data byte has been responded
+//               with a NACK.
+//
+//               Note:  If the remote I2C master terminates the transfer with a
+//               STOP condition before the DW_apb_i2c has a chance to NACK a
+//               transfer, and IC_ENABLE[0] has been set to 0, then this bit is
+//               also set to 1.
+//
+//               When read as 0, DW_apb_i2c is deemed to have been disabled
+//               without being actively involved in the data phase of a
+//               Slave-Receiver transfer.
+//
+//               Note:  The CPU can safely read this bit when IC_EN (bit 0) is
+//               read as 0.
+//
+//               Reset value: 0x0
+//               0x0 -> Slave RX Data is not lost
+//               0x1 -> Slave RX Data is lost
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET          _u(0x0)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS           _u(0x00000004)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB            _u(2)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB            _u(2)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS         "RO"
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY
+// Description : Slave Disabled While Busy (Transmit, Receive). This bit
+//               indicates if a potential or active Slave operation has been
+//               aborted due to the setting bit 0 of the IC_ENABLE register from
+//               1 to 0. This bit is set when the CPU writes a 0 to the
+//               IC_ENABLE register while:
+//
+//               (a) DW_apb_i2c is receiving the address byte of the
+//               Slave-Transmitter operation from a remote master;
+//
+//               OR,
+//
+//               (b) address and data bytes of the Slave-Receiver operation from
+//               a remote master.
+//
+//               When read as 1, DW_apb_i2c is deemed to have forced a NACK
+//               during any part of an I2C transfer, irrespective of whether the
+//               I2C address matches the slave address set in DW_apb_i2c (IC_SAR
+//               register) OR if the transfer is completed before IC_ENABLE is
+//               set to 0 but has not taken effect.
+//
+//               Note:  If the remote I2C master terminates the transfer with a
+//               STOP condition before the DW_apb_i2c has a chance to NACK a
+//               transfer, and IC_ENABLE[0] has been set to 0, then this bit
+//               will also be set to 1.
+//
+//               When read as 0, DW_apb_i2c is deemed to have been disabled when
+//               there is master activity, or when the I2C bus is idle.
+//
+//               Note:  The CPU can safely read this bit when IC_EN (bit 0) is
+//               read as 0.
+//
+//               Reset value: 0x0
+//               0x0 -> Slave is disabled when it is idle
+//               0x1 -> Slave is disabled when it is active
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET          _u(0x0)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS           _u(0x00000002)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB            _u(1)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB            _u(1)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS         "RO"
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE   _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_ENABLE_STATUS_IC_EN
+// Description : ic_en Status. This bit always reflects the value driven on the
+//               output port ic_en. - When read as 1, DW_apb_i2c is deemed to be
+//               in an enabled state. - When read as 0, DW_apb_i2c is deemed
+//               completely inactive. Note:  The CPU can safely read this bit
+//               anytime. When this bit is read as 0, the CPU can safely read
+//               SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).
+//
+//               Reset value: 0x0
+//               0x0 -> I2C disabled
+//               0x1 -> I2C enabled
+#define I2C_IC_ENABLE_STATUS_IC_EN_RESET          _u(0x0)
+#define I2C_IC_ENABLE_STATUS_IC_EN_BITS           _u(0x00000001)
+#define I2C_IC_ENABLE_STATUS_IC_EN_MSB            _u(0)
+#define I2C_IC_ENABLE_STATUS_IC_EN_LSB            _u(0)
+#define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS         "RO"
+#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED _u(0x0)
+#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED  _u(0x1)
+// =============================================================================
+// Register    : I2C_IC_FS_SPKLEN
+// Description : I2C SS, FS or FM+ spike suppression limit
+//
+//               This register is used to store the duration, measured in ic_clk
+//               cycles, of the longest spike that is filtered out by the spike
+//               suppression logic when the component is operating in SS, FS or
+//               FM+ modes. The relevant I2C requirement is tSP (table 4) as
+//               detailed in the I2C Bus Specification. This register must be
+//               programmed with a minimum value of 1.
+#define I2C_IC_FS_SPKLEN_OFFSET _u(0x000000a0)
+#define I2C_IC_FS_SPKLEN_BITS   _u(0x000000ff)
+#define I2C_IC_FS_SPKLEN_RESET  _u(0x00000007)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_FS_SPKLEN_IC_FS_SPKLEN
+// Description : This register must be set before any I2C bus transaction can
+//               take place to ensure stable operation. This register sets the
+//               duration, measured in ic_clk cycles, of the longest spike in
+//               the SCL or SDA lines that will be filtered out by the spike
+//               suppression logic. This register can be written only when the
+//               I2C interface is disabled which corresponds to the IC_ENABLE[0]
+//               register being set to 0. Writes at other times have no effect.
+//               The minimum valid value is 1; hardware prevents values less
+//               than this being written, and if attempted results in 1 being
+//               set. or more information, refer to 'Spike Suppression'.
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET  _u(0x07)
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_BITS   _u(0x000000ff)
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB    _u(7)
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB    _u(0)
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_ACCESS "RW"
+// =============================================================================
+// Register    : I2C_IC_CLR_RESTART_DET
+// Description : Clear RESTART_DET Interrupt Register
+#define I2C_IC_CLR_RESTART_DET_OFFSET _u(0x000000a8)
+#define I2C_IC_CLR_RESTART_DET_BITS   _u(0x00000001)
+#define I2C_IC_CLR_RESTART_DET_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET
+// Description : Read this register to clear the RESTART_DET interrupt (bit 12)
+//               of IC_RAW_INTR_STAT register.
+//
+//               Reset value: 0x0
+#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET  _u(0x0)
+#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_BITS   _u(0x00000001)
+#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB    _u(0)
+#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB    _u(0)
+#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_COMP_PARAM_1
+// Description : Component Parameter Register 1
+//
+//               Note This register is not implemented and therefore reads as 0.
+//               If it was implemented it would be a constant read-only register
+//               that contains encoded information about the component's
+//               parameter settings. Fields shown below are the settings for
+//               those parameters
+#define I2C_IC_COMP_PARAM_1_OFFSET _u(0x000000f4)
+#define I2C_IC_COMP_PARAM_1_BITS   _u(0x00ffffff)
+#define I2C_IC_COMP_PARAM_1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH
+// Description : TX Buffer Depth = 16
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET  _u(0x00)
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_BITS   _u(0x00ff0000)
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB    _u(23)
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB    _u(16)
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH
+// Description : RX Buffer Depth = 16
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET  _u(0x00)
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_BITS   _u(0x0000ff00)
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB    _u(15)
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB    _u(8)
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS
+// Description : Encoded parameters not visible
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET  _u(0x0)
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_BITS   _u(0x00000080)
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB    _u(7)
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB    _u(7)
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_COMP_PARAM_1_HAS_DMA
+// Description : DMA handshaking signals are enabled
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_RESET  _u(0x0)
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_BITS   _u(0x00000040)
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_MSB    _u(6)
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_LSB    _u(6)
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_COMP_PARAM_1_INTR_IO
+// Description : COMBINED Interrupt outputs
+#define I2C_IC_COMP_PARAM_1_INTR_IO_RESET  _u(0x0)
+#define I2C_IC_COMP_PARAM_1_INTR_IO_BITS   _u(0x00000020)
+#define I2C_IC_COMP_PARAM_1_INTR_IO_MSB    _u(5)
+#define I2C_IC_COMP_PARAM_1_INTR_IO_LSB    _u(5)
+#define I2C_IC_COMP_PARAM_1_INTR_IO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES
+// Description : Programmable count values for each mode.
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET  _u(0x0)
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_BITS   _u(0x00000010)
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB    _u(4)
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB    _u(4)
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE
+// Description : MAX SPEED MODE = FAST MODE
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET  _u(0x0)
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_BITS   _u(0x0000000c)
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB    _u(3)
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB    _u(2)
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH
+// Description : APB data bus width is 32 bits
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET  _u(0x0)
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_BITS   _u(0x00000003)
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB    _u(1)
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB    _u(0)
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_COMP_VERSION
+// Description : I2C Component Version Register
+#define I2C_IC_COMP_VERSION_OFFSET _u(0x000000f8)
+#define I2C_IC_COMP_VERSION_BITS   _u(0xffffffff)
+#define I2C_IC_COMP_VERSION_RESET  _u(0x3230312a)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_COMP_VERSION_IC_COMP_VERSION
+// Description : None
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET  _u(0x3230312a)
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS   _u(0xffffffff)
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB    _u(31)
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB    _u(0)
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_ACCESS "RO"
+// =============================================================================
+// Register    : I2C_IC_COMP_TYPE
+// Description : I2C Component Type Register
+#define I2C_IC_COMP_TYPE_OFFSET _u(0x000000fc)
+#define I2C_IC_COMP_TYPE_BITS   _u(0xffffffff)
+#define I2C_IC_COMP_TYPE_RESET  _u(0x44570140)
+// -----------------------------------------------------------------------------
+// Field       : I2C_IC_COMP_TYPE_IC_COMP_TYPE
+// Description : Designware Component Type number = 0x44_57_01_40. This assigned
+//               unique hex value is constant and is derived from the two ASCII
+//               letters 'DW' followed by a 16-bit unsigned number.
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET  _u(0x44570140)
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_BITS   _u(0xffffffff)
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB    _u(31)
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB    _u(0)
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_I2C_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/intctrl.h b/src/rp2040/hardware_regs/include/hardware/regs/intctrl.h
new file mode 100644
index 0000000..dec7e36
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/intctrl.h
@@ -0,0 +1,63 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _INTCTRL_H_
+#define _INTCTRL_H_
+
+#define TIMER_IRQ_0 0
+#define TIMER_IRQ_1 1
+#define TIMER_IRQ_2 2
+#define TIMER_IRQ_3 3
+#define PWM_IRQ_WRAP 4
+#define USBCTRL_IRQ 5
+#define XIP_IRQ 6
+#define PIO0_IRQ_0 7
+#define PIO0_IRQ_1 8
+#define PIO1_IRQ_0 9
+#define PIO1_IRQ_1 10
+#define DMA_IRQ_0 11
+#define DMA_IRQ_1 12
+#define IO_IRQ_BANK0 13
+#define IO_IRQ_QSPI 14
+#define SIO_IRQ_PROC0 15
+#define SIO_IRQ_PROC1 16
+#define CLOCKS_IRQ 17
+#define SPI0_IRQ 18
+#define SPI1_IRQ 19
+#define UART0_IRQ 20
+#define UART1_IRQ 21
+#define ADC_IRQ_FIFO 22
+#define I2C0_IRQ 23
+#define I2C1_IRQ 24
+#define RTC_IRQ 25
+
+#define isr_timer_0 isr_irq0
+#define isr_timer_1 isr_irq1
+#define isr_timer_2 isr_irq2
+#define isr_timer_3 isr_irq3
+#define isr_pwm_wrap isr_irq4
+#define isr_usbctrl isr_irq5
+#define isr_xip isr_irq6
+#define isr_pio0_0 isr_irq7
+#define isr_pio0_1 isr_irq8
+#define isr_pio1_0 isr_irq9
+#define isr_pio1_1 isr_irq10
+#define isr_dma_0 isr_irq11
+#define isr_dma_1 isr_irq12
+#define isr_io_bank0 isr_irq13
+#define isr_io_qspi isr_irq14
+#define isr_sio_proc0 isr_irq15
+#define isr_sio_proc1 isr_irq16
+#define isr_clocks isr_irq17
+#define isr_spi0 isr_irq18
+#define isr_spi1 isr_irq19
+#define isr_uart0 isr_irq20
+#define isr_uart1 isr_irq21
+#define isr_adc_fifo isr_irq22
+#define isr_i2c0 isr_irq23
+#define isr_i2c1 isr_irq24
+#define isr_rtc isr_irq25
+
+#endif // _INTCTRL_H_
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h b/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h
new file mode 100644
index 0000000..26f139e
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h
@@ -0,0 +1,14937 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : IO_BANK0
+// Version        : 1
+// Bus type       : apb
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_IO_BANK0_DEFINED
+#define HARDWARE_REGS_IO_BANK0_DEFINED
+// =============================================================================
+// Register    : IO_BANK0_GPIO0_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000)
+#define IO_BANK0_GPIO0_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO0_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO0_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO0_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO0_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO0_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO0_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO0_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO0_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO0_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO0_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO0_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO0_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO0_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO0_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO0_CTRL_OFFSET _u(0x00000004)
+#define IO_BANK0_GPIO0_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO0_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO0_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO0_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO0_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO0_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO0_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO0_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO0_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO0_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x00 -> jtag_tck
+//               0x01 -> spi0_rx
+//               0x02 -> uart0_tx
+//               0x03 -> i2c0_sda
+//               0x04 -> pwm_a_0
+//               0x05 -> sio_0
+//               0x06 -> pio0_0
+//               0x07 -> pio1_0
+//               0x09 -> usb_muxing_overcurr_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET                            _u(0x1f)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB                              _u(4)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB                              _u(0)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS                           "RW"
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK                   _u(0x00)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX                    _u(0x01)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX                   _u(0x02)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA                   _u(0x03)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0                    _u(0x04)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0                      _u(0x05)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0                     _u(0x06)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0                     _u(0x07)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO1_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO1_STATUS_OFFSET _u(0x00000008)
+#define IO_BANK0_GPIO1_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO1_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO1_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO1_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO1_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO1_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO1_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO1_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO1_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO1_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO1_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO1_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO1_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO1_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO1_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO1_CTRL_OFFSET _u(0x0000000c)
+#define IO_BANK0_GPIO1_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO1_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO1_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO1_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO1_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO1_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO1_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO1_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO1_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO1_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x00 -> jtag_tms
+//               0x01 -> spi0_ss_n
+//               0x02 -> uart0_rx
+//               0x03 -> i2c0_scl
+//               0x04 -> pwm_b_0
+//               0x05 -> sio_1
+//               0x06 -> pio0_1
+//               0x07 -> pio1_1
+//               0x09 -> usb_muxing_vbus_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET                        _u(0x1f)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB                          _u(4)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB                          _u(0)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS                       "RW"
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS               _u(0x00)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N              _u(0x01)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX               _u(0x02)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL               _u(0x03)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0                _u(0x04)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1                  _u(0x05)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1                 _u(0x06)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1                 _u(0x07)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO2_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO2_STATUS_OFFSET _u(0x00000010)
+#define IO_BANK0_GPIO2_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO2_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO2_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO2_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO2_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO2_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO2_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO2_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO2_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO2_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO2_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO2_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO2_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO2_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO2_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO2_CTRL_OFFSET _u(0x00000014)
+#define IO_BANK0_GPIO2_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO2_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO2_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO2_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO2_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO2_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO2_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO2_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO2_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO2_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x00 -> jtag_tdi
+//               0x01 -> spi0_sclk
+//               0x02 -> uart0_cts
+//               0x03 -> i2c1_sda
+//               0x04 -> pwm_a_1
+//               0x05 -> sio_2
+//               0x06 -> pio0_2
+//               0x07 -> pio1_2
+//               0x09 -> usb_muxing_vbus_en
+//               0x1f -> null
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET                    _u(0x1f)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS                     _u(0x0000001f)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB                      _u(4)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB                      _u(0)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS                   "RW"
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI           _u(0x00)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK          _u(0x01)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS          _u(0x02)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA           _u(0x03)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1            _u(0x04)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2              _u(0x05)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2             _u(0x06)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2             _u(0x07)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL               _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO3_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO3_STATUS_OFFSET _u(0x00000018)
+#define IO_BANK0_GPIO3_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO3_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO3_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO3_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO3_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO3_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO3_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO3_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO3_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO3_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO3_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO3_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO3_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO3_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO3_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO3_CTRL_OFFSET _u(0x0000001c)
+#define IO_BANK0_GPIO3_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO3_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO3_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO3_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO3_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO3_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO3_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO3_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO3_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO3_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x00 -> jtag_tdo
+//               0x01 -> spi0_tx
+//               0x02 -> uart0_rts
+//               0x03 -> i2c1_scl
+//               0x04 -> pwm_b_1
+//               0x05 -> sio_3
+//               0x06 -> pio0_3
+//               0x07 -> pio1_3
+//               0x09 -> usb_muxing_overcurr_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET                            _u(0x1f)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB                              _u(4)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB                              _u(0)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS                           "RW"
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO                   _u(0x00)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX                    _u(0x01)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS                  _u(0x02)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL                   _u(0x03)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1                    _u(0x04)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3                      _u(0x05)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3                     _u(0x06)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3                     _u(0x07)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO4_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO4_STATUS_OFFSET _u(0x00000020)
+#define IO_BANK0_GPIO4_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO4_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO4_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO4_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO4_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO4_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO4_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO4_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO4_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO4_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO4_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO4_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO4_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO4_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO4_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO4_CTRL_OFFSET _u(0x00000024)
+#define IO_BANK0_GPIO4_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO4_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO4_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO4_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO4_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO4_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO4_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO4_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO4_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO4_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi0_rx
+//               0x02 -> uart1_tx
+//               0x03 -> i2c0_sda
+//               0x04 -> pwm_a_2
+//               0x05 -> sio_4
+//               0x06 -> pio0_4
+//               0x07 -> pio1_4
+//               0x09 -> usb_muxing_vbus_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET                        _u(0x1f)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB                          _u(4)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB                          _u(0)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS                       "RW"
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX                _u(0x01)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX               _u(0x02)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA               _u(0x03)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2                _u(0x04)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4                  _u(0x05)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4                 _u(0x06)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4                 _u(0x07)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO5_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO5_STATUS_OFFSET _u(0x00000028)
+#define IO_BANK0_GPIO5_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO5_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO5_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO5_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO5_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO5_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO5_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO5_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO5_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO5_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO5_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO5_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO5_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO5_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO5_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO5_CTRL_OFFSET _u(0x0000002c)
+#define IO_BANK0_GPIO5_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO5_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO5_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO5_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO5_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO5_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO5_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO5_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO5_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO5_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi0_ss_n
+//               0x02 -> uart1_rx
+//               0x03 -> i2c0_scl
+//               0x04 -> pwm_b_2
+//               0x05 -> sio_5
+//               0x06 -> pio0_5
+//               0x07 -> pio1_5
+//               0x09 -> usb_muxing_vbus_en
+//               0x1f -> null
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET                    _u(0x1f)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS                     _u(0x0000001f)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB                      _u(4)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB                      _u(0)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS                   "RW"
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N          _u(0x01)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX           _u(0x02)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL           _u(0x03)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2            _u(0x04)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5              _u(0x05)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5             _u(0x06)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5             _u(0x07)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL               _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO6_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO6_STATUS_OFFSET _u(0x00000030)
+#define IO_BANK0_GPIO6_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO6_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO6_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO6_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO6_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO6_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO6_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO6_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO6_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO6_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO6_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO6_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO6_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO6_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO6_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO6_CTRL_OFFSET _u(0x00000034)
+#define IO_BANK0_GPIO6_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO6_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO6_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO6_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO6_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO6_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO6_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO6_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO6_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO6_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi0_sclk
+//               0x02 -> uart1_cts
+//               0x03 -> i2c1_sda
+//               0x04 -> pwm_a_3
+//               0x05 -> sio_6
+//               0x06 -> pio0_6
+//               0x07 -> pio1_6
+//               0x08 -> usb_muxing_extphy_softcon
+//               0x09 -> usb_muxing_overcurr_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET                            _u(0x1f)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB                              _u(4)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB                              _u(0)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS                           "RW"
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK                  _u(0x01)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS                  _u(0x02)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA                   _u(0x03)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3                    _u(0x04)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6                      _u(0x05)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6                     _u(0x06)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6                     _u(0x07)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON  _u(0x08)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO7_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO7_STATUS_OFFSET _u(0x00000038)
+#define IO_BANK0_GPIO7_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO7_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO7_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO7_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO7_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO7_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO7_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO7_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO7_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO7_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO7_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO7_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO7_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO7_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO7_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO7_CTRL_OFFSET _u(0x0000003c)
+#define IO_BANK0_GPIO7_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO7_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO7_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO7_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO7_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO7_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO7_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO7_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO7_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO7_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi0_tx
+//               0x02 -> uart1_rts
+//               0x03 -> i2c1_scl
+//               0x04 -> pwm_b_3
+//               0x05 -> sio_7
+//               0x06 -> pio0_7
+//               0x07 -> pio1_7
+//               0x08 -> usb_muxing_extphy_oe_n
+//               0x09 -> usb_muxing_vbus_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET                        _u(0x1f)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB                          _u(4)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB                          _u(0)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS                       "RW"
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX                _u(0x01)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS              _u(0x02)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL               _u(0x03)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3                _u(0x04)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7                  _u(0x05)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7                 _u(0x06)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7                 _u(0x07)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N _u(0x08)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO8_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO8_STATUS_OFFSET _u(0x00000040)
+#define IO_BANK0_GPIO8_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO8_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO8_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO8_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO8_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO8_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO8_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO8_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO8_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO8_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO8_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO8_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO8_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO8_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO8_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO8_CTRL_OFFSET _u(0x00000044)
+#define IO_BANK0_GPIO8_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO8_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO8_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO8_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO8_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO8_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO8_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO8_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO8_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO8_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi1_rx
+//               0x02 -> uart1_tx
+//               0x03 -> i2c0_sda
+//               0x04 -> pwm_a_4
+//               0x05 -> sio_8
+//               0x06 -> pio0_8
+//               0x07 -> pio1_8
+//               0x08 -> usb_muxing_extphy_rcv
+//               0x09 -> usb_muxing_vbus_en
+//               0x1f -> null
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET                       _u(0x1f)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS                        _u(0x0000001f)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB                         _u(4)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB                         _u(0)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS                      "RW"
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX               _u(0x01)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX              _u(0x02)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA              _u(0x03)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4               _u(0x04)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8                 _u(0x05)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8                _u(0x06)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8                _u(0x07)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV _u(0x08)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN    _u(0x09)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL                  _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO9_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO9_STATUS_OFFSET _u(0x00000048)
+#define IO_BANK0_GPIO9_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO9_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO9_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO9_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO9_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO9_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO9_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO9_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO9_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO9_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO9_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO9_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO9_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO9_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO9_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO9_CTRL_OFFSET _u(0x0000004c)
+#define IO_BANK0_GPIO9_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO9_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO9_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO9_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO9_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO9_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO9_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO9_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO9_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO9_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi1_ss_n
+//               0x02 -> uart1_rx
+//               0x03 -> i2c0_scl
+//               0x04 -> pwm_b_4
+//               0x05 -> sio_9
+//               0x06 -> pio0_9
+//               0x07 -> pio1_9
+//               0x08 -> usb_muxing_extphy_vp
+//               0x09 -> usb_muxing_overcurr_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET                            _u(0x1f)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB                              _u(4)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB                              _u(0)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS                           "RW"
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N                  _u(0x01)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX                   _u(0x02)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL                   _u(0x03)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4                    _u(0x04)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9                      _u(0x05)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9                     _u(0x06)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9                     _u(0x07)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP       _u(0x08)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO10_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO10_STATUS_OFFSET _u(0x00000050)
+#define IO_BANK0_GPIO10_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO10_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO10_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO10_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO10_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO10_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO10_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO10_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO10_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO10_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO10_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO10_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO10_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO10_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO10_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO10_CTRL_OFFSET _u(0x00000054)
+#define IO_BANK0_GPIO10_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO10_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO10_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO10_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO10_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO10_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO10_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO10_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO10_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO10_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi1_sclk
+//               0x02 -> uart1_cts
+//               0x03 -> i2c1_sda
+//               0x04 -> pwm_a_5
+//               0x05 -> sio_10
+//               0x06 -> pio0_10
+//               0x07 -> pio1_10
+//               0x08 -> usb_muxing_extphy_vm
+//               0x09 -> usb_muxing_vbus_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET                        _u(0x1f)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB                          _u(4)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB                          _u(0)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS                       "RW"
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK              _u(0x01)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS              _u(0x02)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA               _u(0x03)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5                _u(0x04)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10                 _u(0x05)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10                _u(0x06)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10                _u(0x07)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM   _u(0x08)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO11_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO11_STATUS_OFFSET _u(0x00000058)
+#define IO_BANK0_GPIO11_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO11_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO11_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO11_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO11_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO11_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO11_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO11_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO11_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO11_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO11_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO11_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO11_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO11_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO11_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO11_CTRL_OFFSET _u(0x0000005c)
+#define IO_BANK0_GPIO11_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO11_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO11_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO11_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO11_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO11_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO11_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO11_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO11_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO11_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi1_tx
+//               0x02 -> uart1_rts
+//               0x03 -> i2c1_scl
+//               0x04 -> pwm_b_5
+//               0x05 -> sio_11
+//               0x06 -> pio0_11
+//               0x07 -> pio1_11
+//               0x08 -> usb_muxing_extphy_suspnd
+//               0x09 -> usb_muxing_vbus_en
+//               0x1f -> null
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET                          _u(0x1f)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS                           _u(0x0000001f)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB                            _u(4)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB                            _u(0)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS                         "RW"
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX                  _u(0x01)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS                _u(0x02)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL                 _u(0x03)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5                  _u(0x04)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11                   _u(0x05)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11                  _u(0x06)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11                  _u(0x07)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND _u(0x08)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN       _u(0x09)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL                     _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO12_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO12_STATUS_OFFSET _u(0x00000060)
+#define IO_BANK0_GPIO12_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO12_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO12_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO12_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO12_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO12_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO12_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO12_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO12_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO12_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO12_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO12_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO12_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO12_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO12_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO12_CTRL_OFFSET _u(0x00000064)
+#define IO_BANK0_GPIO12_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO12_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO12_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO12_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO12_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO12_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO12_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO12_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO12_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO12_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi1_rx
+//               0x02 -> uart0_tx
+//               0x03 -> i2c0_sda
+//               0x04 -> pwm_a_6
+//               0x05 -> sio_12
+//               0x06 -> pio0_12
+//               0x07 -> pio1_12
+//               0x08 -> usb_muxing_extphy_speed
+//               0x09 -> usb_muxing_overcurr_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET                            _u(0x1f)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB                              _u(4)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB                              _u(0)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS                           "RW"
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX                    _u(0x01)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX                   _u(0x02)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA                   _u(0x03)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6                    _u(0x04)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12                     _u(0x05)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12                    _u(0x06)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12                    _u(0x07)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED    _u(0x08)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO13_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO13_STATUS_OFFSET _u(0x00000068)
+#define IO_BANK0_GPIO13_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO13_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO13_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO13_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO13_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO13_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO13_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO13_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO13_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO13_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO13_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO13_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO13_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO13_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO13_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO13_CTRL_OFFSET _u(0x0000006c)
+#define IO_BANK0_GPIO13_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO13_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO13_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO13_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO13_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO13_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO13_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO13_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO13_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO13_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi1_ss_n
+//               0x02 -> uart0_rx
+//               0x03 -> i2c0_scl
+//               0x04 -> pwm_b_6
+//               0x05 -> sio_13
+//               0x06 -> pio0_13
+//               0x07 -> pio1_13
+//               0x08 -> usb_muxing_extphy_vpo
+//               0x09 -> usb_muxing_vbus_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET                        _u(0x1f)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB                          _u(4)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB                          _u(0)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS                       "RW"
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N              _u(0x01)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX               _u(0x02)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL               _u(0x03)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6                _u(0x04)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13                 _u(0x05)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13                _u(0x06)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13                _u(0x07)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO  _u(0x08)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO14_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO14_STATUS_OFFSET _u(0x00000070)
+#define IO_BANK0_GPIO14_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO14_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO14_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO14_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO14_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO14_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO14_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO14_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO14_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO14_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO14_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO14_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO14_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO14_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO14_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO14_CTRL_OFFSET _u(0x00000074)
+#define IO_BANK0_GPIO14_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO14_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO14_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO14_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO14_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO14_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO14_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO14_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO14_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO14_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi1_sclk
+//               0x02 -> uart0_cts
+//               0x03 -> i2c1_sda
+//               0x04 -> pwm_a_7
+//               0x05 -> sio_14
+//               0x06 -> pio0_14
+//               0x07 -> pio1_14
+//               0x08 -> usb_muxing_extphy_vmo
+//               0x09 -> usb_muxing_vbus_en
+//               0x1f -> null
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET                       _u(0x1f)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS                        _u(0x0000001f)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB                         _u(4)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB                         _u(0)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS                      "RW"
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK             _u(0x01)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS             _u(0x02)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA              _u(0x03)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7               _u(0x04)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14                _u(0x05)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14               _u(0x06)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14               _u(0x07)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO _u(0x08)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN    _u(0x09)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL                  _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO15_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO15_STATUS_OFFSET _u(0x00000078)
+#define IO_BANK0_GPIO15_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO15_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO15_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO15_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO15_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO15_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO15_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO15_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO15_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO15_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO15_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO15_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO15_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO15_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO15_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO15_CTRL_OFFSET _u(0x0000007c)
+#define IO_BANK0_GPIO15_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO15_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO15_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO15_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO15_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO15_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO15_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO15_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO15_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO15_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi1_tx
+//               0x02 -> uart0_rts
+//               0x03 -> i2c1_scl
+//               0x04 -> pwm_b_7
+//               0x05 -> sio_15
+//               0x06 -> pio0_15
+//               0x07 -> pio1_15
+//               0x08 -> usb_muxing_digital_dp
+//               0x09 -> usb_muxing_overcurr_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET                            _u(0x1f)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB                              _u(4)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB                              _u(0)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS                           "RW"
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX                    _u(0x01)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS                  _u(0x02)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL                   _u(0x03)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7                    _u(0x04)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15                     _u(0x05)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15                    _u(0x06)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15                    _u(0x07)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP      _u(0x08)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO16_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO16_STATUS_OFFSET _u(0x00000080)
+#define IO_BANK0_GPIO16_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO16_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO16_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO16_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO16_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO16_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO16_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO16_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO16_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO16_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO16_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO16_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO16_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO16_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO16_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO16_CTRL_OFFSET _u(0x00000084)
+#define IO_BANK0_GPIO16_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO16_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO16_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO16_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO16_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO16_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO16_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO16_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO16_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO16_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi0_rx
+//               0x02 -> uart0_tx
+//               0x03 -> i2c0_sda
+//               0x04 -> pwm_a_0
+//               0x05 -> sio_16
+//               0x06 -> pio0_16
+//               0x07 -> pio1_16
+//               0x08 -> usb_muxing_digital_dm
+//               0x09 -> usb_muxing_vbus_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET                        _u(0x1f)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB                          _u(4)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB                          _u(0)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS                       "RW"
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX                _u(0x01)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX               _u(0x02)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA               _u(0x03)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0                _u(0x04)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16                 _u(0x05)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16                _u(0x06)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16                _u(0x07)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM  _u(0x08)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO17_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO17_STATUS_OFFSET _u(0x00000088)
+#define IO_BANK0_GPIO17_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO17_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO17_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO17_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO17_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO17_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO17_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO17_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO17_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO17_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO17_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO17_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO17_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO17_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO17_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO17_CTRL_OFFSET _u(0x0000008c)
+#define IO_BANK0_GPIO17_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO17_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO17_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO17_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO17_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO17_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO17_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO17_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO17_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO17_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi0_ss_n
+//               0x02 -> uart0_rx
+//               0x03 -> i2c0_scl
+//               0x04 -> pwm_b_0
+//               0x05 -> sio_17
+//               0x06 -> pio0_17
+//               0x07 -> pio1_17
+//               0x09 -> usb_muxing_vbus_en
+//               0x1f -> null
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET                    _u(0x1f)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS                     _u(0x0000001f)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB                      _u(4)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB                      _u(0)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS                   "RW"
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N          _u(0x01)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX           _u(0x02)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL           _u(0x03)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0            _u(0x04)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17             _u(0x05)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17            _u(0x06)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17            _u(0x07)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL               _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO18_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO18_STATUS_OFFSET _u(0x00000090)
+#define IO_BANK0_GPIO18_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO18_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO18_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO18_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO18_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO18_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO18_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO18_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO18_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO18_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO18_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO18_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO18_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO18_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO18_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO18_CTRL_OFFSET _u(0x00000094)
+#define IO_BANK0_GPIO18_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO18_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO18_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO18_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO18_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO18_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO18_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO18_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO18_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO18_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi0_sclk
+//               0x02 -> uart0_cts
+//               0x03 -> i2c1_sda
+//               0x04 -> pwm_a_1
+//               0x05 -> sio_18
+//               0x06 -> pio0_18
+//               0x07 -> pio1_18
+//               0x09 -> usb_muxing_overcurr_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET                            _u(0x1f)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB                              _u(4)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB                              _u(0)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS                           "RW"
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK                  _u(0x01)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS                  _u(0x02)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA                   _u(0x03)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1                    _u(0x04)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18                     _u(0x05)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18                    _u(0x06)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18                    _u(0x07)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO19_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO19_STATUS_OFFSET _u(0x00000098)
+#define IO_BANK0_GPIO19_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO19_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO19_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO19_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO19_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO19_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO19_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO19_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO19_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO19_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO19_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO19_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO19_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO19_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO19_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO19_CTRL_OFFSET _u(0x0000009c)
+#define IO_BANK0_GPIO19_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO19_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO19_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO19_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO19_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO19_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO19_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO19_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO19_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO19_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi0_tx
+//               0x02 -> uart0_rts
+//               0x03 -> i2c1_scl
+//               0x04 -> pwm_b_1
+//               0x05 -> sio_19
+//               0x06 -> pio0_19
+//               0x07 -> pio1_19
+//               0x09 -> usb_muxing_vbus_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET                        _u(0x1f)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB                          _u(4)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB                          _u(0)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS                       "RW"
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX                _u(0x01)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS              _u(0x02)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL               _u(0x03)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1                _u(0x04)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19                 _u(0x05)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19                _u(0x06)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19                _u(0x07)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO20_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO20_STATUS_OFFSET _u(0x000000a0)
+#define IO_BANK0_GPIO20_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO20_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO20_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO20_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO20_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO20_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO20_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO20_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO20_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO20_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO20_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO20_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO20_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO20_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO20_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO20_CTRL_OFFSET _u(0x000000a4)
+#define IO_BANK0_GPIO20_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO20_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO20_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO20_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO20_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO20_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO20_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO20_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO20_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO20_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi0_rx
+//               0x02 -> uart1_tx
+//               0x03 -> i2c0_sda
+//               0x04 -> pwm_a_2
+//               0x05 -> sio_20
+//               0x06 -> pio0_20
+//               0x07 -> pio1_20
+//               0x08 -> clocks_gpin_0
+//               0x09 -> usb_muxing_vbus_en
+//               0x1f -> null
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET                    _u(0x1f)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS                     _u(0x0000001f)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB                      _u(4)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB                      _u(0)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS                   "RW"
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX            _u(0x01)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX           _u(0x02)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA           _u(0x03)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2            _u(0x04)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20             _u(0x05)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20            _u(0x06)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20            _u(0x07)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0      _u(0x08)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL               _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO21_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO21_STATUS_OFFSET _u(0x000000a8)
+#define IO_BANK0_GPIO21_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO21_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO21_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO21_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO21_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO21_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO21_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO21_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO21_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO21_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO21_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO21_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO21_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO21_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO21_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO21_CTRL_OFFSET _u(0x000000ac)
+#define IO_BANK0_GPIO21_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO21_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO21_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO21_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO21_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO21_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO21_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO21_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO21_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO21_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi0_ss_n
+//               0x02 -> uart1_rx
+//               0x03 -> i2c0_scl
+//               0x04 -> pwm_b_2
+//               0x05 -> sio_21
+//               0x06 -> pio0_21
+//               0x07 -> pio1_21
+//               0x08 -> clocks_gpout_0
+//               0x09 -> usb_muxing_overcurr_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET                            _u(0x1f)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB                              _u(4)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB                              _u(0)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS                           "RW"
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N                  _u(0x01)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX                   _u(0x02)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL                   _u(0x03)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2                    _u(0x04)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21                     _u(0x05)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21                    _u(0x06)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21                    _u(0x07)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0             _u(0x08)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO22_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO22_STATUS_OFFSET _u(0x000000b0)
+#define IO_BANK0_GPIO22_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO22_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO22_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO22_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO22_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO22_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO22_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO22_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO22_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO22_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO22_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO22_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO22_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO22_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO22_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO22_CTRL_OFFSET _u(0x000000b4)
+#define IO_BANK0_GPIO22_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO22_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO22_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO22_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO22_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO22_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO22_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO22_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO22_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO22_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi0_sclk
+//               0x02 -> uart1_cts
+//               0x03 -> i2c1_sda
+//               0x04 -> pwm_a_3
+//               0x05 -> sio_22
+//               0x06 -> pio0_22
+//               0x07 -> pio1_22
+//               0x08 -> clocks_gpin_1
+//               0x09 -> usb_muxing_vbus_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET                        _u(0x1f)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB                          _u(4)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB                          _u(0)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS                       "RW"
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK              _u(0x01)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS              _u(0x02)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA               _u(0x03)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3                _u(0x04)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22                 _u(0x05)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22                _u(0x06)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22                _u(0x07)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1          _u(0x08)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO23_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO23_STATUS_OFFSET _u(0x000000b8)
+#define IO_BANK0_GPIO23_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO23_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO23_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO23_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO23_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO23_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO23_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO23_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO23_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO23_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO23_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO23_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO23_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO23_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO23_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO23_CTRL_OFFSET _u(0x000000bc)
+#define IO_BANK0_GPIO23_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO23_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO23_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO23_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO23_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO23_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO23_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO23_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO23_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO23_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi0_tx
+//               0x02 -> uart1_rts
+//               0x03 -> i2c1_scl
+//               0x04 -> pwm_b_3
+//               0x05 -> sio_23
+//               0x06 -> pio0_23
+//               0x07 -> pio1_23
+//               0x08 -> clocks_gpout_1
+//               0x09 -> usb_muxing_vbus_en
+//               0x1f -> null
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET                    _u(0x1f)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS                     _u(0x0000001f)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB                      _u(4)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB                      _u(0)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS                   "RW"
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX            _u(0x01)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS          _u(0x02)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL           _u(0x03)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3            _u(0x04)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23             _u(0x05)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23            _u(0x06)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23            _u(0x07)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1     _u(0x08)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL               _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO24_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO24_STATUS_OFFSET _u(0x000000c0)
+#define IO_BANK0_GPIO24_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO24_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO24_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO24_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO24_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO24_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO24_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO24_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO24_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO24_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO24_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO24_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO24_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO24_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO24_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO24_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO24_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO24_CTRL_OFFSET _u(0x000000c4)
+#define IO_BANK0_GPIO24_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO24_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO24_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO24_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO24_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO24_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO24_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO24_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO24_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO24_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi1_rx
+//               0x02 -> uart1_tx
+//               0x03 -> i2c0_sda
+//               0x04 -> pwm_a_4
+//               0x05 -> sio_24
+//               0x06 -> pio0_24
+//               0x07 -> pio1_24
+//               0x08 -> clocks_gpout_2
+//               0x09 -> usb_muxing_overcurr_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET                            _u(0x1f)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB                              _u(4)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB                              _u(0)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS                           "RW"
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX                    _u(0x01)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX                   _u(0x02)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA                   _u(0x03)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4                    _u(0x04)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24                     _u(0x05)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24                    _u(0x06)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24                    _u(0x07)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2             _u(0x08)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO25_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO25_STATUS_OFFSET _u(0x000000c8)
+#define IO_BANK0_GPIO25_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO25_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO25_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO25_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO25_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO25_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO25_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO25_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO25_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO25_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO25_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO25_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO25_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO25_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO25_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO25_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO25_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO25_CTRL_OFFSET _u(0x000000cc)
+#define IO_BANK0_GPIO25_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO25_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO25_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO25_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO25_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO25_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO25_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO25_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO25_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO25_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi1_ss_n
+//               0x02 -> uart1_rx
+//               0x03 -> i2c0_scl
+//               0x04 -> pwm_b_4
+//               0x05 -> sio_25
+//               0x06 -> pio0_25
+//               0x07 -> pio1_25
+//               0x08 -> clocks_gpout_3
+//               0x09 -> usb_muxing_vbus_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET                        _u(0x1f)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB                          _u(4)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB                          _u(0)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS                       "RW"
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N              _u(0x01)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX               _u(0x02)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL               _u(0x03)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4                _u(0x04)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25                 _u(0x05)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25                _u(0x06)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25                _u(0x07)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3         _u(0x08)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO26_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO26_STATUS_OFFSET _u(0x000000d0)
+#define IO_BANK0_GPIO26_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO26_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO26_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO26_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO26_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO26_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO26_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO26_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO26_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO26_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO26_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO26_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO26_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO26_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO26_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO26_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO26_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO26_CTRL_OFFSET _u(0x000000d4)
+#define IO_BANK0_GPIO26_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO26_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO26_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO26_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO26_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO26_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO26_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO26_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO26_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO26_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi1_sclk
+//               0x02 -> uart1_cts
+//               0x03 -> i2c1_sda
+//               0x04 -> pwm_a_5
+//               0x05 -> sio_26
+//               0x06 -> pio0_26
+//               0x07 -> pio1_26
+//               0x09 -> usb_muxing_vbus_en
+//               0x1f -> null
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET                    _u(0x1f)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS                     _u(0x0000001f)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB                      _u(4)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB                      _u(0)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS                   "RW"
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK          _u(0x01)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS          _u(0x02)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA           _u(0x03)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5            _u(0x04)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26             _u(0x05)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26            _u(0x06)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26            _u(0x07)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL               _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO27_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO27_STATUS_OFFSET _u(0x000000d8)
+#define IO_BANK0_GPIO27_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO27_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO27_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO27_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO27_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO27_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO27_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO27_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO27_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO27_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO27_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO27_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO27_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO27_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO27_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO27_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO27_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO27_CTRL_OFFSET _u(0x000000dc)
+#define IO_BANK0_GPIO27_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO27_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO27_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO27_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO27_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO27_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO27_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO27_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO27_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO27_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi1_tx
+//               0x02 -> uart1_rts
+//               0x03 -> i2c1_scl
+//               0x04 -> pwm_b_5
+//               0x05 -> sio_27
+//               0x06 -> pio0_27
+//               0x07 -> pio1_27
+//               0x09 -> usb_muxing_overcurr_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET                            _u(0x1f)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB                              _u(4)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB                              _u(0)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS                           "RW"
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX                    _u(0x01)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS                  _u(0x02)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL                   _u(0x03)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5                    _u(0x04)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27                     _u(0x05)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27                    _u(0x06)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27                    _u(0x07)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO28_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO28_STATUS_OFFSET _u(0x000000e0)
+#define IO_BANK0_GPIO28_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO28_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO28_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO28_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO28_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO28_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO28_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO28_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO28_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO28_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO28_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO28_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO28_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO28_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO28_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO28_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO28_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO28_CTRL_OFFSET _u(0x000000e4)
+#define IO_BANK0_GPIO28_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO28_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO28_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO28_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO28_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO28_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO28_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO28_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO28_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO28_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi1_rx
+//               0x02 -> uart0_tx
+//               0x03 -> i2c0_sda
+//               0x04 -> pwm_a_6
+//               0x05 -> sio_28
+//               0x06 -> pio0_28
+//               0x07 -> pio1_28
+//               0x09 -> usb_muxing_vbus_detect
+//               0x1f -> null
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET                        _u(0x1f)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB                          _u(4)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB                          _u(0)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS                       "RW"
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX                _u(0x01)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX               _u(0x02)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA               _u(0x03)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6                _u(0x04)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28                 _u(0x05)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28                _u(0x06)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28                _u(0x07)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_GPIO29_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO29_STATUS_OFFSET _u(0x000000e8)
+#define IO_BANK0_GPIO29_STATUS_BITS   _u(0x050a3300)
+#define IO_BANK0_GPIO29_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO29_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO29_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO29_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO29_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_BANK0_GPIO29_STATUS_INTOPERI_MSB    _u(19)
+#define IO_BANK0_GPIO29_STATUS_INTOPERI_LSB    _u(19)
+#define IO_BANK0_GPIO29_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO29_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_BANK0_GPIO29_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO29_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB    _u(13)
+#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB    _u(13)
+#define IO_BANK0_GPIO29_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO29_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO29_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO29_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_GPIO29_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO29_CTRL_OFFSET _u(0x000000ec)
+#define IO_BANK0_GPIO29_CTRL_BITS   _u(0x3003331f)
+#define IO_BANK0_GPIO29_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO29_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB          _u(29)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB          _u(28)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO29_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_BANK0_GPIO29_CTRL_INOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_BANK0_GPIO29_CTRL_INOVER_MSB          _u(17)
+#define IO_BANK0_GPIO29_CTRL_INOVER_LSB          _u(16)
+#define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO29_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB           _u(13)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB           _u(12)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS        "RW"
+#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO29_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB          _u(9)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB          _u(8)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_GPIO29_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x01 -> spi1_ss_n
+//               0x02 -> uart0_rx
+//               0x03 -> i2c0_scl
+//               0x04 -> pwm_b_6
+//               0x05 -> sio_29
+//               0x06 -> pio0_29
+//               0x07 -> pio1_29
+//               0x09 -> usb_muxing_vbus_en
+//               0x1f -> null
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET                    _u(0x1f)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS                     _u(0x0000001f)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB                      _u(4)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB                      _u(0)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS                   "RW"
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N          _u(0x01)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX           _u(0x02)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL           _u(0x03)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6            _u(0x04)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29             _u(0x05)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29            _u(0x06)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29            _u(0x07)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL               _u(0x1f)
+// =============================================================================
+// Register    : IO_BANK0_INTR0
+// Description : Raw Interrupts
+#define IO_BANK0_INTR0_OFFSET _u(0x000000f0)
+#define IO_BANK0_INTR0_BITS   _u(0xffffffff)
+#define IO_BANK0_INTR0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_INTR1
+// Description : Raw Interrupts
+#define IO_BANK0_INTR1_OFFSET _u(0x000000f4)
+#define IO_BANK0_INTR1_BITS   _u(0xffffffff)
+#define IO_BANK0_INTR1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_INTR2
+// Description : Raw Interrupts
+#define IO_BANK0_INTR2_OFFSET _u(0x000000f8)
+#define IO_BANK0_INTR2_BITS   _u(0xffffffff)
+#define IO_BANK0_INTR2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_INTR3
+// Description : Raw Interrupts
+#define IO_BANK0_INTR3_OFFSET _u(0x000000fc)
+#define IO_BANK0_INTR3_BITS   _u(0x00ffffff)
+#define IO_BANK0_INTR3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_INTR3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_PROC0_INTE0
+// Description : Interrupt Enable for proc0
+#define IO_BANK0_PROC0_INTE0_OFFSET _u(0x00000100)
+#define IO_BANK0_PROC0_INTE0_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC0_INTE0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC0_INTE1
+// Description : Interrupt Enable for proc0
+#define IO_BANK0_PROC0_INTE1_OFFSET _u(0x00000104)
+#define IO_BANK0_PROC0_INTE1_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC0_INTE1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC0_INTE2
+// Description : Interrupt Enable for proc0
+#define IO_BANK0_PROC0_INTE2_OFFSET _u(0x00000108)
+#define IO_BANK0_PROC0_INTE2_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC0_INTE2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC0_INTE3
+// Description : Interrupt Enable for proc0
+#define IO_BANK0_PROC0_INTE3_OFFSET _u(0x0000010c)
+#define IO_BANK0_PROC0_INTE3_BITS   _u(0x00ffffff)
+#define IO_BANK0_PROC0_INTE3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC0_INTF0
+// Description : Interrupt Force for proc0
+#define IO_BANK0_PROC0_INTF0_OFFSET _u(0x00000110)
+#define IO_BANK0_PROC0_INTF0_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC0_INTF0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC0_INTF1
+// Description : Interrupt Force for proc0
+#define IO_BANK0_PROC0_INTF1_OFFSET _u(0x00000114)
+#define IO_BANK0_PROC0_INTF1_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC0_INTF1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC0_INTF2
+// Description : Interrupt Force for proc0
+#define IO_BANK0_PROC0_INTF2_OFFSET _u(0x00000118)
+#define IO_BANK0_PROC0_INTF2_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC0_INTF2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC0_INTF3
+// Description : Interrupt Force for proc0
+#define IO_BANK0_PROC0_INTF3_OFFSET _u(0x0000011c)
+#define IO_BANK0_PROC0_INTF3_BITS   _u(0x00ffffff)
+#define IO_BANK0_PROC0_INTF3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC0_INTS0
+// Description : Interrupt status after masking & forcing for proc0
+#define IO_BANK0_PROC0_INTS0_OFFSET _u(0x00000120)
+#define IO_BANK0_PROC0_INTS0_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC0_INTS0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_PROC0_INTS1
+// Description : Interrupt status after masking & forcing for proc0
+#define IO_BANK0_PROC0_INTS1_OFFSET _u(0x00000124)
+#define IO_BANK0_PROC0_INTS1_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC0_INTS1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_PROC0_INTS2
+// Description : Interrupt status after masking & forcing for proc0
+#define IO_BANK0_PROC0_INTS2_OFFSET _u(0x00000128)
+#define IO_BANK0_PROC0_INTS2_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC0_INTS2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_PROC0_INTS3
+// Description : Interrupt status after masking & forcing for proc0
+#define IO_BANK0_PROC0_INTS3_OFFSET _u(0x0000012c)
+#define IO_BANK0_PROC0_INTS3_BITS   _u(0x00ffffff)
+#define IO_BANK0_PROC0_INTS3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_PROC1_INTE0
+// Description : Interrupt Enable for proc1
+#define IO_BANK0_PROC1_INTE0_OFFSET _u(0x00000130)
+#define IO_BANK0_PROC1_INTE0_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC1_INTE0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC1_INTE1
+// Description : Interrupt Enable for proc1
+#define IO_BANK0_PROC1_INTE1_OFFSET _u(0x00000134)
+#define IO_BANK0_PROC1_INTE1_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC1_INTE1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC1_INTE2
+// Description : Interrupt Enable for proc1
+#define IO_BANK0_PROC1_INTE2_OFFSET _u(0x00000138)
+#define IO_BANK0_PROC1_INTE2_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC1_INTE2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC1_INTE3
+// Description : Interrupt Enable for proc1
+#define IO_BANK0_PROC1_INTE3_OFFSET _u(0x0000013c)
+#define IO_BANK0_PROC1_INTE3_BITS   _u(0x00ffffff)
+#define IO_BANK0_PROC1_INTE3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC1_INTF0
+// Description : Interrupt Force for proc1
+#define IO_BANK0_PROC1_INTF0_OFFSET _u(0x00000140)
+#define IO_BANK0_PROC1_INTF0_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC1_INTF0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC1_INTF1
+// Description : Interrupt Force for proc1
+#define IO_BANK0_PROC1_INTF1_OFFSET _u(0x00000144)
+#define IO_BANK0_PROC1_INTF1_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC1_INTF1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC1_INTF2
+// Description : Interrupt Force for proc1
+#define IO_BANK0_PROC1_INTF2_OFFSET _u(0x00000148)
+#define IO_BANK0_PROC1_INTF2_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC1_INTF2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC1_INTF3
+// Description : Interrupt Force for proc1
+#define IO_BANK0_PROC1_INTF3_OFFSET _u(0x0000014c)
+#define IO_BANK0_PROC1_INTF3_BITS   _u(0x00ffffff)
+#define IO_BANK0_PROC1_INTF3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_PROC1_INTS0
+// Description : Interrupt status after masking & forcing for proc1
+#define IO_BANK0_PROC1_INTS0_OFFSET _u(0x00000150)
+#define IO_BANK0_PROC1_INTS0_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC1_INTS0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_PROC1_INTS1
+// Description : Interrupt status after masking & forcing for proc1
+#define IO_BANK0_PROC1_INTS1_OFFSET _u(0x00000154)
+#define IO_BANK0_PROC1_INTS1_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC1_INTS1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_PROC1_INTS2
+// Description : Interrupt status after masking & forcing for proc1
+#define IO_BANK0_PROC1_INTS2_OFFSET _u(0x00000158)
+#define IO_BANK0_PROC1_INTS2_BITS   _u(0xffffffff)
+#define IO_BANK0_PROC1_INTS2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_PROC1_INTS3
+// Description : Interrupt status after masking & forcing for proc1
+#define IO_BANK0_PROC1_INTS3_OFFSET _u(0x0000015c)
+#define IO_BANK0_PROC1_INTS3_BITS   _u(0x00ffffff)
+#define IO_BANK0_PROC1_INTS3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_DORMANT_WAKE_INTE0
+// Description : Interrupt Enable for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET _u(0x00000160)
+#define IO_BANK0_DORMANT_WAKE_INTE0_BITS   _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTE0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_DORMANT_WAKE_INTE1
+// Description : Interrupt Enable for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET _u(0x00000164)
+#define IO_BANK0_DORMANT_WAKE_INTE1_BITS   _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTE1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_DORMANT_WAKE_INTE2
+// Description : Interrupt Enable for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET _u(0x00000168)
+#define IO_BANK0_DORMANT_WAKE_INTE2_BITS   _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTE2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_DORMANT_WAKE_INTE3
+// Description : Interrupt Enable for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET _u(0x0000016c)
+#define IO_BANK0_DORMANT_WAKE_INTE3_BITS   _u(0x00ffffff)
+#define IO_BANK0_DORMANT_WAKE_INTE3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_DORMANT_WAKE_INTF0
+// Description : Interrupt Force for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET _u(0x00000170)
+#define IO_BANK0_DORMANT_WAKE_INTF0_BITS   _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTF0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_DORMANT_WAKE_INTF1
+// Description : Interrupt Force for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET _u(0x00000174)
+#define IO_BANK0_DORMANT_WAKE_INTF1_BITS   _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTF1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_DORMANT_WAKE_INTF2
+// Description : Interrupt Force for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET _u(0x00000178)
+#define IO_BANK0_DORMANT_WAKE_INTF2_BITS   _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTF2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_DORMANT_WAKE_INTF3
+// Description : Interrupt Force for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET _u(0x0000017c)
+#define IO_BANK0_DORMANT_WAKE_INTF3_BITS   _u(0x00ffffff)
+#define IO_BANK0_DORMANT_WAKE_INTF3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_BANK0_DORMANT_WAKE_INTS0
+// Description : Interrupt status after masking & forcing for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET _u(0x00000180)
+#define IO_BANK0_DORMANT_WAKE_INTS0_BITS   _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTS0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_DORMANT_WAKE_INTS1
+// Description : Interrupt status after masking & forcing for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET _u(0x00000184)
+#define IO_BANK0_DORMANT_WAKE_INTS1_BITS   _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTS1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_DORMANT_WAKE_INTS2
+// Description : Interrupt status after masking & forcing for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET _u(0x00000188)
+#define IO_BANK0_DORMANT_WAKE_INTS2_BITS   _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTS2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB    _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB    _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB    _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB    _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB    _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB    _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB    _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB    _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_BANK0_DORMANT_WAKE_INTS3
+// Description : Interrupt status after masking & forcing for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET _u(0x0000018c)
+#define IO_BANK0_DORMANT_WAKE_INTS3_BITS   _u(0x00ffffff)
+#define IO_BANK0_DORMANT_WAKE_INTS3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB    _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB    _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB    _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB    _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB    _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB    _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB    _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB    _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB    _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB    _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB    _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB    _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB    _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB    _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB    _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB    _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB    _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB    _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB    _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB    _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB    _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB    _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB    _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB    _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_IO_BANK0_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h b/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h
new file mode 100644
index 0000000..7c381b7
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h
@@ -0,0 +1,2931 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : IO_QSPI
+// Version        : 1
+// Bus type       : apb
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_IO_QSPI_DEFINED
+#define HARDWARE_REGS_IO_QSPI_DEFINED
+// =============================================================================
+// Register    : IO_QSPI_GPIO_QSPI_SCLK_STATUS
+// Description : GPIO status
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET _u(0x00000000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS   _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_MSB    _u(19)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_LSB    _u(19)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB    _u(13)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB    _u(13)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_QSPI_GPIO_QSPI_SCLK_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET _u(0x00000004)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS   _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB          _u(29)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB          _u(28)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB          _u(17)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB          _u(16)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB           _u(13)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB           _u(12)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS        "RW"
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB          _u(9)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB          _u(8)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x00 -> xip_sclk
+//               0x05 -> sio_30
+//               0x1f -> null
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET          _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS           _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB            _u(4)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB            _u(0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS         "RW"
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30   _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL     _u(0x1f)
+// =============================================================================
+// Register    : IO_QSPI_GPIO_QSPI_SS_STATUS
+// Description : GPIO status
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET _u(0x00000008)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS   _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_MSB    _u(19)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_LSB    _u(19)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB    _u(13)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB    _u(13)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_QSPI_GPIO_QSPI_SS_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET _u(0x0000000c)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS   _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB          _u(29)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB          _u(28)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB          _u(17)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB          _u(16)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB           _u(13)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB           _u(12)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS        "RW"
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB          _u(9)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB          _u(8)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x00 -> xip_ss_n
+//               0x05 -> sio_31
+//               0x1f -> null
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET          _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS           _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB            _u(4)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB            _u(0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS         "RW"
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31   _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL     _u(0x1f)
+// =============================================================================
+// Register    : IO_QSPI_GPIO_QSPI_SD0_STATUS
+// Description : GPIO status
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET _u(0x00000010)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS   _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_MSB    _u(19)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_LSB    _u(19)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB    _u(13)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB    _u(13)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_QSPI_GPIO_QSPI_SD0_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET _u(0x00000014)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS   _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB          _u(29)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB          _u(28)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB          _u(17)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB          _u(16)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB           _u(13)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB           _u(12)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS        "RW"
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB          _u(9)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB          _u(8)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x00 -> xip_sd0
+//               0x05 -> sio_32
+//               0x1f -> null
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET         _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS          _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB           _u(4)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB           _u(0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS        "RW"
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32  _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL    _u(0x1f)
+// =============================================================================
+// Register    : IO_QSPI_GPIO_QSPI_SD1_STATUS
+// Description : GPIO status
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET _u(0x00000018)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS   _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_MSB    _u(19)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_LSB    _u(19)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB    _u(13)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB    _u(13)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_QSPI_GPIO_QSPI_SD1_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET _u(0x0000001c)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS   _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB          _u(29)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB          _u(28)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB          _u(17)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB          _u(16)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB           _u(13)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB           _u(12)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS        "RW"
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB          _u(9)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB          _u(8)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x00 -> xip_sd1
+//               0x05 -> sio_33
+//               0x1f -> null
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET         _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS          _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB           _u(4)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB           _u(0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS        "RW"
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33  _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL    _u(0x1f)
+// =============================================================================
+// Register    : IO_QSPI_GPIO_QSPI_SD2_STATUS
+// Description : GPIO status
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET _u(0x00000020)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS   _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_MSB    _u(19)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_LSB    _u(19)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB    _u(13)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB    _u(13)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_QSPI_GPIO_QSPI_SD2_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET _u(0x00000024)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS   _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB          _u(29)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB          _u(28)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB          _u(17)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB          _u(16)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB           _u(13)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB           _u(12)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS        "RW"
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB          _u(9)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB          _u(8)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x00 -> xip_sd2
+//               0x05 -> sio_34
+//               0x1f -> null
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET         _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS          _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB           _u(4)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB           _u(0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS        "RW"
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34  _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL    _u(0x1f)
+// =============================================================================
+// Register    : IO_QSPI_GPIO_QSPI_SD3_STATUS
+// Description : GPIO status
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET _u(0x00000028)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS   _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS   _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB    _u(26)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB    _u(26)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_MSB    _u(24)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_LSB    _u(24)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_BITS   _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_MSB    _u(19)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_LSB    _u(19)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS   _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB    _u(17)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB    _u(17)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS   _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB    _u(13)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB    _u(13)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+//               override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_BITS   _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_MSB    _u(12)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_LSB    _u(12)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS   _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB    _u(9)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB    _u(9)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+//               override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_RESET  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_MSB    _u(8)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_LSB    _u(8)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register    : IO_QSPI_GPIO_QSPI_SD3_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET _u(0x0000002c)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS   _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET  _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+//               0x1 -> invert the interrupt
+//               0x2 -> drive interrupt low
+//               0x3 -> drive interrupt high
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS         _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB          _u(29)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB          _u(28)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+//               0x1 -> invert the peri input
+//               0x2 -> drive peri input low
+//               0x3 -> drive peri input high
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS         _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB          _u(17)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB          _u(16)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+//               funcsel
+//               0x1 -> drive output enable from inverse of peripheral signal
+//               selected by funcsel
+//               0x2 -> disable output
+//               0x3 -> enable output
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET         _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS          _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB           _u(13)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB           _u(12)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS        "RW"
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+//               0x1 -> drive output from inverse of peripheral signal selected
+//               by funcsel
+//               0x2 -> drive output low
+//               0x3 -> drive output high
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET        _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS         _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB          _u(9)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB          _u(8)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS       "RW"
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+//               31 == NULL
+//               0x00 -> xip_sd3
+//               0x05 -> sio_35
+//               0x1f -> null
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET         _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS          _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB           _u(4)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB           _u(0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS        "RW"
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35  _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL    _u(0x1f)
+// =============================================================================
+// Register    : IO_QSPI_INTR
+// Description : Raw Interrupts
+#define IO_QSPI_INTR_OFFSET _u(0x00000030)
+#define IO_QSPI_INTR_BITS   _u(0x00ffffff)
+#define IO_QSPI_INTR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_QSPI_PROC0_INTE
+// Description : Interrupt Enable for proc0
+#define IO_QSPI_PROC0_INTE_OFFSET _u(0x00000034)
+#define IO_QSPI_PROC0_INTE_BITS   _u(0x00ffffff)
+#define IO_QSPI_PROC0_INTE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_QSPI_PROC0_INTF
+// Description : Interrupt Force for proc0
+#define IO_QSPI_PROC0_INTF_OFFSET _u(0x00000038)
+#define IO_QSPI_PROC0_INTF_BITS   _u(0x00ffffff)
+#define IO_QSPI_PROC0_INTF_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_QSPI_PROC0_INTS
+// Description : Interrupt status after masking & forcing for proc0
+#define IO_QSPI_PROC0_INTS_OFFSET _u(0x0000003c)
+#define IO_QSPI_PROC0_INTS_BITS   _u(0x00ffffff)
+#define IO_QSPI_PROC0_INTS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_QSPI_PROC1_INTE
+// Description : Interrupt Enable for proc1
+#define IO_QSPI_PROC1_INTE_OFFSET _u(0x00000040)
+#define IO_QSPI_PROC1_INTE_BITS   _u(0x00ffffff)
+#define IO_QSPI_PROC1_INTE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_QSPI_PROC1_INTF
+// Description : Interrupt Force for proc1
+#define IO_QSPI_PROC1_INTF_OFFSET _u(0x00000044)
+#define IO_QSPI_PROC1_INTF_BITS   _u(0x00ffffff)
+#define IO_QSPI_PROC1_INTF_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_QSPI_PROC1_INTS
+// Description : Interrupt status after masking & forcing for proc1
+#define IO_QSPI_PROC1_INTS_OFFSET _u(0x00000048)
+#define IO_QSPI_PROC1_INTS_BITS   _u(0x00ffffff)
+#define IO_QSPI_PROC1_INTS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register    : IO_QSPI_DORMANT_WAKE_INTE
+// Description : Interrupt Enable for dormant_wake
+#define IO_QSPI_DORMANT_WAKE_INTE_OFFSET _u(0x0000004c)
+#define IO_QSPI_DORMANT_WAKE_INTE_BITS   _u(0x00ffffff)
+#define IO_QSPI_DORMANT_WAKE_INTE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_QSPI_DORMANT_WAKE_INTF
+// Description : Interrupt Force for dormant_wake
+#define IO_QSPI_DORMANT_WAKE_INTF_OFFSET _u(0x00000050)
+#define IO_QSPI_DORMANT_WAKE_INTF_BITS   _u(0x00ffffff)
+#define IO_QSPI_DORMANT_WAKE_INTF_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register    : IO_QSPI_DORMANT_WAKE_INTS
+// Description : Interrupt status after masking & forcing for dormant_wake
+#define IO_QSPI_DORMANT_WAKE_INTS_OFFSET _u(0x00000054)
+#define IO_QSPI_DORMANT_WAKE_INTS_BITS   _u(0x00ffffff)
+#define IO_QSPI_DORMANT_WAKE_INTS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS   _u(0x00800000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB    _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB    _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS   _u(0x00400000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB    _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB    _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS   _u(0x00200000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB    _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB    _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS   _u(0x00100000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB    _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB    _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS   _u(0x00080000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB    _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB    _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS   _u(0x00040000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB    _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB    _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS   _u(0x00020000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB    _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB    _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS   _u(0x00010000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB    _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB    _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS   _u(0x00008000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB    _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB    _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS   _u(0x00004000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB    _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB    _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS   _u(0x00002000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB    _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB    _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS   _u(0x00001000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB    _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB    _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS   _u(0x00000800)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB    _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB    _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS   _u(0x00000400)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB    _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB    _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS   _u(0x00000200)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB    _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB    _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS   _u(0x00000100)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB    _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB    _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS   _u(0x00000080)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB    _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB    _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS   _u(0x00000040)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB    _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB    _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS   _u(0x00000020)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB    _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB    _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS   _u(0x00000010)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB    _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB    _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS   _u(0x00000008)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB    _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB    _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS   _u(0x00000004)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB    _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB    _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS   _u(0x00000002)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB    _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB    _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET  _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS   _u(0x00000001)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB    _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB    _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_IO_QSPI_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/m0plus.h b/src/rp2040/hardware_regs/include/hardware/regs/m0plus.h
new file mode 100644
index 0000000..cef5ab0
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/m0plus.h
@@ -0,0 +1,1149 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : M0PLUS
+// Version        : 1
+// Bus type       : ahbl
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_M0PLUS_DEFINED
+#define HARDWARE_REGS_M0PLUS_DEFINED
+// =============================================================================
+// Register    : M0PLUS_SYST_CSR
+// Description : Use the SysTick Control and Status Register to enable the
+//               SysTick features.
+#define M0PLUS_SYST_CSR_OFFSET _u(0x0000e010)
+#define M0PLUS_SYST_CSR_BITS   _u(0x00010007)
+#define M0PLUS_SYST_CSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CSR_COUNTFLAG
+// Description : Returns 1 if timer counted to 0 since last time this was read.
+//               Clears on read by application or debugger.
+#define M0PLUS_SYST_CSR_COUNTFLAG_RESET  _u(0x0)
+#define M0PLUS_SYST_CSR_COUNTFLAG_BITS   _u(0x00010000)
+#define M0PLUS_SYST_CSR_COUNTFLAG_MSB    _u(16)
+#define M0PLUS_SYST_CSR_COUNTFLAG_LSB    _u(16)
+#define M0PLUS_SYST_CSR_COUNTFLAG_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CSR_CLKSOURCE
+// Description : SysTick clock source. Always reads as one if SYST_CALIB reports
+//               NOREF.
+//               Selects the SysTick timer clock source:
+//               0 = External reference clock.
+//               1 = Processor clock.
+#define M0PLUS_SYST_CSR_CLKSOURCE_RESET  _u(0x0)
+#define M0PLUS_SYST_CSR_CLKSOURCE_BITS   _u(0x00000004)
+#define M0PLUS_SYST_CSR_CLKSOURCE_MSB    _u(2)
+#define M0PLUS_SYST_CSR_CLKSOURCE_LSB    _u(2)
+#define M0PLUS_SYST_CSR_CLKSOURCE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CSR_TICKINT
+// Description : Enables SysTick exception request:
+//               0 = Counting down to zero does not assert the SysTick exception
+//               request.
+//               1 = Counting down to zero to asserts the SysTick exception
+//               request.
+#define M0PLUS_SYST_CSR_TICKINT_RESET  _u(0x0)
+#define M0PLUS_SYST_CSR_TICKINT_BITS   _u(0x00000002)
+#define M0PLUS_SYST_CSR_TICKINT_MSB    _u(1)
+#define M0PLUS_SYST_CSR_TICKINT_LSB    _u(1)
+#define M0PLUS_SYST_CSR_TICKINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CSR_ENABLE
+// Description : Enable SysTick counter:
+//               0 = Counter disabled.
+//               1 = Counter enabled.
+#define M0PLUS_SYST_CSR_ENABLE_RESET  _u(0x0)
+#define M0PLUS_SYST_CSR_ENABLE_BITS   _u(0x00000001)
+#define M0PLUS_SYST_CSR_ENABLE_MSB    _u(0)
+#define M0PLUS_SYST_CSR_ENABLE_LSB    _u(0)
+#define M0PLUS_SYST_CSR_ENABLE_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_SYST_RVR
+// Description : Use the SysTick Reload Value Register to specify the start
+//               value to load into the current value register when the counter
+//               reaches 0. It can be any value between 0 and 0x00FFFFFF. A
+//               start value of 0 is possible, but has no effect because the
+//               SysTick interrupt and COUNTFLAG are activated when counting
+//               from 1 to 0. The reset value of this register is UNKNOWN.
+//               To generate a multi-shot timer with a period of N processor
+//               clock cycles, use a RELOAD value of N-1. For example, if the
+//               SysTick interrupt is required every 100 clock pulses, set
+//               RELOAD to 99.
+#define M0PLUS_SYST_RVR_OFFSET _u(0x0000e014)
+#define M0PLUS_SYST_RVR_BITS   _u(0x00ffffff)
+#define M0PLUS_SYST_RVR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_RVR_RELOAD
+// Description : Value to load into the SysTick Current Value Register when the
+//               counter reaches 0.
+#define M0PLUS_SYST_RVR_RELOAD_RESET  _u(0x000000)
+#define M0PLUS_SYST_RVR_RELOAD_BITS   _u(0x00ffffff)
+#define M0PLUS_SYST_RVR_RELOAD_MSB    _u(23)
+#define M0PLUS_SYST_RVR_RELOAD_LSB    _u(0)
+#define M0PLUS_SYST_RVR_RELOAD_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_SYST_CVR
+// Description : Use the SysTick Current Value Register to find the current
+//               value in the register. The reset value of this register is
+//               UNKNOWN.
+#define M0PLUS_SYST_CVR_OFFSET _u(0x0000e018)
+#define M0PLUS_SYST_CVR_BITS   _u(0x00ffffff)
+#define M0PLUS_SYST_CVR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CVR_CURRENT
+// Description : Reads return the current value of the SysTick counter. This
+//               register is write-clear. Writing to it with any value clears
+//               the register to 0. Clearing this register also clears the
+//               COUNTFLAG bit of the SysTick Control and Status Register.
+#define M0PLUS_SYST_CVR_CURRENT_RESET  _u(0x000000)
+#define M0PLUS_SYST_CVR_CURRENT_BITS   _u(0x00ffffff)
+#define M0PLUS_SYST_CVR_CURRENT_MSB    _u(23)
+#define M0PLUS_SYST_CVR_CURRENT_LSB    _u(0)
+#define M0PLUS_SYST_CVR_CURRENT_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_SYST_CALIB
+// Description : Use the SysTick Calibration Value Register to enable software
+//               to scale to any required speed using divide and multiply.
+#define M0PLUS_SYST_CALIB_OFFSET _u(0x0000e01c)
+#define M0PLUS_SYST_CALIB_BITS   _u(0xc0ffffff)
+#define M0PLUS_SYST_CALIB_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CALIB_NOREF
+// Description : If reads as 1, the Reference clock is not provided - the
+//               CLKSOURCE bit of the SysTick Control and Status register will
+//               be forced to 1 and cannot be cleared to 0.
+#define M0PLUS_SYST_CALIB_NOREF_RESET  _u(0x0)
+#define M0PLUS_SYST_CALIB_NOREF_BITS   _u(0x80000000)
+#define M0PLUS_SYST_CALIB_NOREF_MSB    _u(31)
+#define M0PLUS_SYST_CALIB_NOREF_LSB    _u(31)
+#define M0PLUS_SYST_CALIB_NOREF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CALIB_SKEW
+// Description : If reads as 1, the calibration value for 10ms is inexact (due
+//               to clock frequency).
+#define M0PLUS_SYST_CALIB_SKEW_RESET  _u(0x0)
+#define M0PLUS_SYST_CALIB_SKEW_BITS   _u(0x40000000)
+#define M0PLUS_SYST_CALIB_SKEW_MSB    _u(30)
+#define M0PLUS_SYST_CALIB_SKEW_LSB    _u(30)
+#define M0PLUS_SYST_CALIB_SKEW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CALIB_TENMS
+// Description : An optional Reload value to be used for 10ms (100Hz) timing,
+//               subject to system clock skew errors. If the value reads as 0,
+//               the calibration value is not known.
+#define M0PLUS_SYST_CALIB_TENMS_RESET  _u(0x000000)
+#define M0PLUS_SYST_CALIB_TENMS_BITS   _u(0x00ffffff)
+#define M0PLUS_SYST_CALIB_TENMS_MSB    _u(23)
+#define M0PLUS_SYST_CALIB_TENMS_LSB    _u(0)
+#define M0PLUS_SYST_CALIB_TENMS_ACCESS "RO"
+// =============================================================================
+// Register    : M0PLUS_NVIC_ISER
+// Description : Use the Interrupt Set-Enable Register to enable interrupts and
+//               determine which interrupts are currently enabled.
+//               If a pending interrupt is enabled, the NVIC activates the
+//               interrupt based on its priority. If an interrupt is not
+//               enabled, asserting its interrupt signal changes the interrupt
+//               state to pending, but the NVIC never activates the interrupt,
+//               regardless of its priority.
+#define M0PLUS_NVIC_ISER_OFFSET _u(0x0000e100)
+#define M0PLUS_NVIC_ISER_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ISER_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_ISER_SETENA
+// Description : Interrupt set-enable bits.
+//               Write:
+//               0 = No effect.
+//               1 = Enable interrupt.
+//               Read:
+//               0 = Interrupt disabled.
+//               1 = Interrupt enabled.
+#define M0PLUS_NVIC_ISER_SETENA_RESET  _u(0x00000000)
+#define M0PLUS_NVIC_ISER_SETENA_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ISER_SETENA_MSB    _u(31)
+#define M0PLUS_NVIC_ISER_SETENA_LSB    _u(0)
+#define M0PLUS_NVIC_ISER_SETENA_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_ICER
+// Description : Use the Interrupt Clear-Enable Registers to disable interrupts
+//               and determine which interrupts are currently enabled.
+#define M0PLUS_NVIC_ICER_OFFSET _u(0x0000e180)
+#define M0PLUS_NVIC_ICER_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ICER_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_ICER_CLRENA
+// Description : Interrupt clear-enable bits.
+//               Write:
+//               0 = No effect.
+//               1 = Disable interrupt.
+//               Read:
+//               0 = Interrupt disabled.
+//               1 = Interrupt enabled.
+#define M0PLUS_NVIC_ICER_CLRENA_RESET  _u(0x00000000)
+#define M0PLUS_NVIC_ICER_CLRENA_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ICER_CLRENA_MSB    _u(31)
+#define M0PLUS_NVIC_ICER_CLRENA_LSB    _u(0)
+#define M0PLUS_NVIC_ICER_CLRENA_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_ISPR
+// Description : The NVIC_ISPR forces interrupts into the pending state, and
+//               shows which interrupts are pending.
+#define M0PLUS_NVIC_ISPR_OFFSET _u(0x0000e200)
+#define M0PLUS_NVIC_ISPR_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ISPR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_ISPR_SETPEND
+// Description : Interrupt set-pending bits.
+//               Write:
+//               0 = No effect.
+//               1 = Changes interrupt state to pending.
+//               Read:
+//               0 = Interrupt is not pending.
+//               1 = Interrupt is pending.
+//               Note: Writing 1 to the NVIC_ISPR bit corresponding to:
+//               An interrupt that is pending has no effect.
+//               A disabled interrupt sets the state of that interrupt to
+//               pending.
+#define M0PLUS_NVIC_ISPR_SETPEND_RESET  _u(0x00000000)
+#define M0PLUS_NVIC_ISPR_SETPEND_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ISPR_SETPEND_MSB    _u(31)
+#define M0PLUS_NVIC_ISPR_SETPEND_LSB    _u(0)
+#define M0PLUS_NVIC_ISPR_SETPEND_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_ICPR
+// Description : Use the Interrupt Clear-Pending Register to clear pending
+//               interrupts and determine which interrupts are currently
+//               pending.
+#define M0PLUS_NVIC_ICPR_OFFSET _u(0x0000e280)
+#define M0PLUS_NVIC_ICPR_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ICPR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_ICPR_CLRPEND
+// Description : Interrupt clear-pending bits.
+//               Write:
+//               0 = No effect.
+//               1 = Removes pending state and interrupt.
+//               Read:
+//               0 = Interrupt is not pending.
+//               1 = Interrupt is pending.
+#define M0PLUS_NVIC_ICPR_CLRPEND_RESET  _u(0x00000000)
+#define M0PLUS_NVIC_ICPR_CLRPEND_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ICPR_CLRPEND_MSB    _u(31)
+#define M0PLUS_NVIC_ICPR_CLRPEND_LSB    _u(0)
+#define M0PLUS_NVIC_ICPR_CLRPEND_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR0
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+//               Note: Writing 1 to an NVIC_ICPR bit does not affect the active
+//               state of the corresponding interrupt.
+//               These registers are only word-accessible
+#define M0PLUS_NVIC_IPR0_OFFSET _u(0x0000e400)
+#define M0PLUS_NVIC_IPR0_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR0_IP_3
+// Description : Priority of interrupt 3
+#define M0PLUS_NVIC_IPR0_IP_3_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_3_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR0_IP_3_MSB    _u(31)
+#define M0PLUS_NVIC_IPR0_IP_3_LSB    _u(30)
+#define M0PLUS_NVIC_IPR0_IP_3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR0_IP_2
+// Description : Priority of interrupt 2
+#define M0PLUS_NVIC_IPR0_IP_2_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_2_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR0_IP_2_MSB    _u(23)
+#define M0PLUS_NVIC_IPR0_IP_2_LSB    _u(22)
+#define M0PLUS_NVIC_IPR0_IP_2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR0_IP_1
+// Description : Priority of interrupt 1
+#define M0PLUS_NVIC_IPR0_IP_1_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_1_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR0_IP_1_MSB    _u(15)
+#define M0PLUS_NVIC_IPR0_IP_1_LSB    _u(14)
+#define M0PLUS_NVIC_IPR0_IP_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR0_IP_0
+// Description : Priority of interrupt 0
+#define M0PLUS_NVIC_IPR0_IP_0_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_0_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR0_IP_0_MSB    _u(7)
+#define M0PLUS_NVIC_IPR0_IP_0_LSB    _u(6)
+#define M0PLUS_NVIC_IPR0_IP_0_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR1
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR1_OFFSET _u(0x0000e404)
+#define M0PLUS_NVIC_IPR1_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR1_IP_7
+// Description : Priority of interrupt 7
+#define M0PLUS_NVIC_IPR1_IP_7_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_7_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR1_IP_7_MSB    _u(31)
+#define M0PLUS_NVIC_IPR1_IP_7_LSB    _u(30)
+#define M0PLUS_NVIC_IPR1_IP_7_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR1_IP_6
+// Description : Priority of interrupt 6
+#define M0PLUS_NVIC_IPR1_IP_6_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_6_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR1_IP_6_MSB    _u(23)
+#define M0PLUS_NVIC_IPR1_IP_6_LSB    _u(22)
+#define M0PLUS_NVIC_IPR1_IP_6_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR1_IP_5
+// Description : Priority of interrupt 5
+#define M0PLUS_NVIC_IPR1_IP_5_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_5_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR1_IP_5_MSB    _u(15)
+#define M0PLUS_NVIC_IPR1_IP_5_LSB    _u(14)
+#define M0PLUS_NVIC_IPR1_IP_5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR1_IP_4
+// Description : Priority of interrupt 4
+#define M0PLUS_NVIC_IPR1_IP_4_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_4_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR1_IP_4_MSB    _u(7)
+#define M0PLUS_NVIC_IPR1_IP_4_LSB    _u(6)
+#define M0PLUS_NVIC_IPR1_IP_4_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR2
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR2_OFFSET _u(0x0000e408)
+#define M0PLUS_NVIC_IPR2_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR2_IP_11
+// Description : Priority of interrupt 11
+#define M0PLUS_NVIC_IPR2_IP_11_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_11_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR2_IP_11_MSB    _u(31)
+#define M0PLUS_NVIC_IPR2_IP_11_LSB    _u(30)
+#define M0PLUS_NVIC_IPR2_IP_11_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR2_IP_10
+// Description : Priority of interrupt 10
+#define M0PLUS_NVIC_IPR2_IP_10_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_10_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR2_IP_10_MSB    _u(23)
+#define M0PLUS_NVIC_IPR2_IP_10_LSB    _u(22)
+#define M0PLUS_NVIC_IPR2_IP_10_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR2_IP_9
+// Description : Priority of interrupt 9
+#define M0PLUS_NVIC_IPR2_IP_9_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_9_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR2_IP_9_MSB    _u(15)
+#define M0PLUS_NVIC_IPR2_IP_9_LSB    _u(14)
+#define M0PLUS_NVIC_IPR2_IP_9_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR2_IP_8
+// Description : Priority of interrupt 8
+#define M0PLUS_NVIC_IPR2_IP_8_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_8_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR2_IP_8_MSB    _u(7)
+#define M0PLUS_NVIC_IPR2_IP_8_LSB    _u(6)
+#define M0PLUS_NVIC_IPR2_IP_8_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR3
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR3_OFFSET _u(0x0000e40c)
+#define M0PLUS_NVIC_IPR3_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR3_IP_15
+// Description : Priority of interrupt 15
+#define M0PLUS_NVIC_IPR3_IP_15_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_15_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR3_IP_15_MSB    _u(31)
+#define M0PLUS_NVIC_IPR3_IP_15_LSB    _u(30)
+#define M0PLUS_NVIC_IPR3_IP_15_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR3_IP_14
+// Description : Priority of interrupt 14
+#define M0PLUS_NVIC_IPR3_IP_14_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_14_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR3_IP_14_MSB    _u(23)
+#define M0PLUS_NVIC_IPR3_IP_14_LSB    _u(22)
+#define M0PLUS_NVIC_IPR3_IP_14_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR3_IP_13
+// Description : Priority of interrupt 13
+#define M0PLUS_NVIC_IPR3_IP_13_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_13_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR3_IP_13_MSB    _u(15)
+#define M0PLUS_NVIC_IPR3_IP_13_LSB    _u(14)
+#define M0PLUS_NVIC_IPR3_IP_13_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR3_IP_12
+// Description : Priority of interrupt 12
+#define M0PLUS_NVIC_IPR3_IP_12_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_12_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR3_IP_12_MSB    _u(7)
+#define M0PLUS_NVIC_IPR3_IP_12_LSB    _u(6)
+#define M0PLUS_NVIC_IPR3_IP_12_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR4
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR4_OFFSET _u(0x0000e410)
+#define M0PLUS_NVIC_IPR4_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR4_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR4_IP_19
+// Description : Priority of interrupt 19
+#define M0PLUS_NVIC_IPR4_IP_19_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_19_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR4_IP_19_MSB    _u(31)
+#define M0PLUS_NVIC_IPR4_IP_19_LSB    _u(30)
+#define M0PLUS_NVIC_IPR4_IP_19_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR4_IP_18
+// Description : Priority of interrupt 18
+#define M0PLUS_NVIC_IPR4_IP_18_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_18_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR4_IP_18_MSB    _u(23)
+#define M0PLUS_NVIC_IPR4_IP_18_LSB    _u(22)
+#define M0PLUS_NVIC_IPR4_IP_18_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR4_IP_17
+// Description : Priority of interrupt 17
+#define M0PLUS_NVIC_IPR4_IP_17_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_17_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR4_IP_17_MSB    _u(15)
+#define M0PLUS_NVIC_IPR4_IP_17_LSB    _u(14)
+#define M0PLUS_NVIC_IPR4_IP_17_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR4_IP_16
+// Description : Priority of interrupt 16
+#define M0PLUS_NVIC_IPR4_IP_16_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_16_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR4_IP_16_MSB    _u(7)
+#define M0PLUS_NVIC_IPR4_IP_16_LSB    _u(6)
+#define M0PLUS_NVIC_IPR4_IP_16_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR5
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR5_OFFSET _u(0x0000e414)
+#define M0PLUS_NVIC_IPR5_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR5_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR5_IP_23
+// Description : Priority of interrupt 23
+#define M0PLUS_NVIC_IPR5_IP_23_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_23_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR5_IP_23_MSB    _u(31)
+#define M0PLUS_NVIC_IPR5_IP_23_LSB    _u(30)
+#define M0PLUS_NVIC_IPR5_IP_23_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR5_IP_22
+// Description : Priority of interrupt 22
+#define M0PLUS_NVIC_IPR5_IP_22_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_22_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR5_IP_22_MSB    _u(23)
+#define M0PLUS_NVIC_IPR5_IP_22_LSB    _u(22)
+#define M0PLUS_NVIC_IPR5_IP_22_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR5_IP_21
+// Description : Priority of interrupt 21
+#define M0PLUS_NVIC_IPR5_IP_21_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_21_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR5_IP_21_MSB    _u(15)
+#define M0PLUS_NVIC_IPR5_IP_21_LSB    _u(14)
+#define M0PLUS_NVIC_IPR5_IP_21_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR5_IP_20
+// Description : Priority of interrupt 20
+#define M0PLUS_NVIC_IPR5_IP_20_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_20_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR5_IP_20_MSB    _u(7)
+#define M0PLUS_NVIC_IPR5_IP_20_LSB    _u(6)
+#define M0PLUS_NVIC_IPR5_IP_20_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR6
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR6_OFFSET _u(0x0000e418)
+#define M0PLUS_NVIC_IPR6_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR6_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR6_IP_27
+// Description : Priority of interrupt 27
+#define M0PLUS_NVIC_IPR6_IP_27_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_27_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR6_IP_27_MSB    _u(31)
+#define M0PLUS_NVIC_IPR6_IP_27_LSB    _u(30)
+#define M0PLUS_NVIC_IPR6_IP_27_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR6_IP_26
+// Description : Priority of interrupt 26
+#define M0PLUS_NVIC_IPR6_IP_26_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_26_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR6_IP_26_MSB    _u(23)
+#define M0PLUS_NVIC_IPR6_IP_26_LSB    _u(22)
+#define M0PLUS_NVIC_IPR6_IP_26_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR6_IP_25
+// Description : Priority of interrupt 25
+#define M0PLUS_NVIC_IPR6_IP_25_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_25_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR6_IP_25_MSB    _u(15)
+#define M0PLUS_NVIC_IPR6_IP_25_LSB    _u(14)
+#define M0PLUS_NVIC_IPR6_IP_25_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR6_IP_24
+// Description : Priority of interrupt 24
+#define M0PLUS_NVIC_IPR6_IP_24_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_24_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR6_IP_24_MSB    _u(7)
+#define M0PLUS_NVIC_IPR6_IP_24_LSB    _u(6)
+#define M0PLUS_NVIC_IPR6_IP_24_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR7
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR7_OFFSET _u(0x0000e41c)
+#define M0PLUS_NVIC_IPR7_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR7_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR7_IP_31
+// Description : Priority of interrupt 31
+#define M0PLUS_NVIC_IPR7_IP_31_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_31_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR7_IP_31_MSB    _u(31)
+#define M0PLUS_NVIC_IPR7_IP_31_LSB    _u(30)
+#define M0PLUS_NVIC_IPR7_IP_31_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR7_IP_30
+// Description : Priority of interrupt 30
+#define M0PLUS_NVIC_IPR7_IP_30_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_30_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR7_IP_30_MSB    _u(23)
+#define M0PLUS_NVIC_IPR7_IP_30_LSB    _u(22)
+#define M0PLUS_NVIC_IPR7_IP_30_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR7_IP_29
+// Description : Priority of interrupt 29
+#define M0PLUS_NVIC_IPR7_IP_29_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_29_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR7_IP_29_MSB    _u(15)
+#define M0PLUS_NVIC_IPR7_IP_29_LSB    _u(14)
+#define M0PLUS_NVIC_IPR7_IP_29_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR7_IP_28
+// Description : Priority of interrupt 28
+#define M0PLUS_NVIC_IPR7_IP_28_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_28_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR7_IP_28_MSB    _u(7)
+#define M0PLUS_NVIC_IPR7_IP_28_LSB    _u(6)
+#define M0PLUS_NVIC_IPR7_IP_28_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_CPUID
+// Description : Read the CPU ID Base Register to determine: the ID number of
+//               the processor core, the version number of the processor core,
+//               the implementation details of the processor core.
+#define M0PLUS_CPUID_OFFSET _u(0x0000ed00)
+#define M0PLUS_CPUID_BITS   _u(0xffffffff)
+#define M0PLUS_CPUID_RESET  _u(0x410cc601)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_CPUID_IMPLEMENTER
+// Description : Implementor code: 0x41 = ARM
+#define M0PLUS_CPUID_IMPLEMENTER_RESET  _u(0x41)
+#define M0PLUS_CPUID_IMPLEMENTER_BITS   _u(0xff000000)
+#define M0PLUS_CPUID_IMPLEMENTER_MSB    _u(31)
+#define M0PLUS_CPUID_IMPLEMENTER_LSB    _u(24)
+#define M0PLUS_CPUID_IMPLEMENTER_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_CPUID_VARIANT
+// Description : Major revision number n in the rnpm revision status:
+//               0x0 = Revision 0.
+#define M0PLUS_CPUID_VARIANT_RESET  _u(0x0)
+#define M0PLUS_CPUID_VARIANT_BITS   _u(0x00f00000)
+#define M0PLUS_CPUID_VARIANT_MSB    _u(23)
+#define M0PLUS_CPUID_VARIANT_LSB    _u(20)
+#define M0PLUS_CPUID_VARIANT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_CPUID_ARCHITECTURE
+// Description : Constant that defines the architecture of the processor:
+//               0xC = ARMv6-M architecture.
+#define M0PLUS_CPUID_ARCHITECTURE_RESET  _u(0xc)
+#define M0PLUS_CPUID_ARCHITECTURE_BITS   _u(0x000f0000)
+#define M0PLUS_CPUID_ARCHITECTURE_MSB    _u(19)
+#define M0PLUS_CPUID_ARCHITECTURE_LSB    _u(16)
+#define M0PLUS_CPUID_ARCHITECTURE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_CPUID_PARTNO
+// Description : Number of processor within family: 0xC60 = Cortex-M0+
+#define M0PLUS_CPUID_PARTNO_RESET  _u(0xc60)
+#define M0PLUS_CPUID_PARTNO_BITS   _u(0x0000fff0)
+#define M0PLUS_CPUID_PARTNO_MSB    _u(15)
+#define M0PLUS_CPUID_PARTNO_LSB    _u(4)
+#define M0PLUS_CPUID_PARTNO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_CPUID_REVISION
+// Description : Minor revision number m in the rnpm revision status:
+//               0x1 = Patch 1.
+#define M0PLUS_CPUID_REVISION_RESET  _u(0x1)
+#define M0PLUS_CPUID_REVISION_BITS   _u(0x0000000f)
+#define M0PLUS_CPUID_REVISION_MSB    _u(3)
+#define M0PLUS_CPUID_REVISION_LSB    _u(0)
+#define M0PLUS_CPUID_REVISION_ACCESS "RO"
+// =============================================================================
+// Register    : M0PLUS_ICSR
+// Description : Use the Interrupt Control State Register to set a pending
+//               Non-Maskable Interrupt (NMI), set or clear a pending PendSV,
+//               set or clear a pending SysTick, check for pending exceptions,
+//               check the vector number of the highest priority pended
+//               exception, check the vector number of the active exception.
+#define M0PLUS_ICSR_OFFSET _u(0x0000ed04)
+#define M0PLUS_ICSR_BITS   _u(0x9edff1ff)
+#define M0PLUS_ICSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_NMIPENDSET
+// Description : Setting this bit will activate an NMI. Since NMI is the highest
+//               priority exception, it will activate as soon as it is
+//               registered.
+//               NMI set-pending bit.
+//               Write:
+//               0 = No effect.
+//               1 = Changes NMI exception state to pending.
+//               Read:
+//               0 = NMI exception is not pending.
+//               1 = NMI exception is pending.
+//               Because NMI is the highest-priority exception, normally the
+//               processor enters the NMI
+//               exception handler as soon as it detects a write of 1 to this
+//               bit. Entering the handler then clears
+//               this bit to 0. This means a read of this bit by the NMI
+//               exception handler returns 1 only if the
+//               NMI signal is reasserted while the processor is executing that
+//               handler.
+#define M0PLUS_ICSR_NMIPENDSET_RESET  _u(0x0)
+#define M0PLUS_ICSR_NMIPENDSET_BITS   _u(0x80000000)
+#define M0PLUS_ICSR_NMIPENDSET_MSB    _u(31)
+#define M0PLUS_ICSR_NMIPENDSET_LSB    _u(31)
+#define M0PLUS_ICSR_NMIPENDSET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_PENDSVSET
+// Description : PendSV set-pending bit.
+//               Write:
+//               0 = No effect.
+//               1 = Changes PendSV exception state to pending.
+//               Read:
+//               0 = PendSV exception is not pending.
+//               1 = PendSV exception is pending.
+//               Writing 1 to this bit is the only way to set the PendSV
+//               exception state to pending.
+#define M0PLUS_ICSR_PENDSVSET_RESET  _u(0x0)
+#define M0PLUS_ICSR_PENDSVSET_BITS   _u(0x10000000)
+#define M0PLUS_ICSR_PENDSVSET_MSB    _u(28)
+#define M0PLUS_ICSR_PENDSVSET_LSB    _u(28)
+#define M0PLUS_ICSR_PENDSVSET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_PENDSVCLR
+// Description : PendSV clear-pending bit.
+//               Write:
+//               0 = No effect.
+//               1 = Removes the pending state from the PendSV exception.
+#define M0PLUS_ICSR_PENDSVCLR_RESET  _u(0x0)
+#define M0PLUS_ICSR_PENDSVCLR_BITS   _u(0x08000000)
+#define M0PLUS_ICSR_PENDSVCLR_MSB    _u(27)
+#define M0PLUS_ICSR_PENDSVCLR_LSB    _u(27)
+#define M0PLUS_ICSR_PENDSVCLR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_PENDSTSET
+// Description : SysTick exception set-pending bit.
+//               Write:
+//               0 = No effect.
+//               1 = Changes SysTick exception state to pending.
+//               Read:
+//               0 = SysTick exception is not pending.
+//               1 = SysTick exception is pending.
+#define M0PLUS_ICSR_PENDSTSET_RESET  _u(0x0)
+#define M0PLUS_ICSR_PENDSTSET_BITS   _u(0x04000000)
+#define M0PLUS_ICSR_PENDSTSET_MSB    _u(26)
+#define M0PLUS_ICSR_PENDSTSET_LSB    _u(26)
+#define M0PLUS_ICSR_PENDSTSET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_PENDSTCLR
+// Description : SysTick exception clear-pending bit.
+//               Write:
+//               0 = No effect.
+//               1 = Removes the pending state from the SysTick exception.
+//               This bit is WO. On a register read its value is Unknown.
+#define M0PLUS_ICSR_PENDSTCLR_RESET  _u(0x0)
+#define M0PLUS_ICSR_PENDSTCLR_BITS   _u(0x02000000)
+#define M0PLUS_ICSR_PENDSTCLR_MSB    _u(25)
+#define M0PLUS_ICSR_PENDSTCLR_LSB    _u(25)
+#define M0PLUS_ICSR_PENDSTCLR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_ISRPREEMPT
+// Description : The system can only access this bit when the core is halted. It
+//               indicates that a pending interrupt is to be taken in the next
+//               running cycle. If C_MASKINTS is clear in the Debug Halting
+//               Control and Status Register, the interrupt is serviced.
+#define M0PLUS_ICSR_ISRPREEMPT_RESET  _u(0x0)
+#define M0PLUS_ICSR_ISRPREEMPT_BITS   _u(0x00800000)
+#define M0PLUS_ICSR_ISRPREEMPT_MSB    _u(23)
+#define M0PLUS_ICSR_ISRPREEMPT_LSB    _u(23)
+#define M0PLUS_ICSR_ISRPREEMPT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_ISRPENDING
+// Description : External interrupt pending flag
+#define M0PLUS_ICSR_ISRPENDING_RESET  _u(0x0)
+#define M0PLUS_ICSR_ISRPENDING_BITS   _u(0x00400000)
+#define M0PLUS_ICSR_ISRPENDING_MSB    _u(22)
+#define M0PLUS_ICSR_ISRPENDING_LSB    _u(22)
+#define M0PLUS_ICSR_ISRPENDING_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_VECTPENDING
+// Description : Indicates the exception number for the highest priority pending
+//               exception: 0 = no pending exceptions. Non zero = The pending
+//               state includes the effect of memory-mapped enable and mask
+//               registers. It does not include the PRIMASK special-purpose
+//               register qualifier.
+#define M0PLUS_ICSR_VECTPENDING_RESET  _u(0x000)
+#define M0PLUS_ICSR_VECTPENDING_BITS   _u(0x001ff000)
+#define M0PLUS_ICSR_VECTPENDING_MSB    _u(20)
+#define M0PLUS_ICSR_VECTPENDING_LSB    _u(12)
+#define M0PLUS_ICSR_VECTPENDING_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_VECTACTIVE
+// Description : Active exception number field. Reset clears the VECTACTIVE
+//               field.
+#define M0PLUS_ICSR_VECTACTIVE_RESET  _u(0x000)
+#define M0PLUS_ICSR_VECTACTIVE_BITS   _u(0x000001ff)
+#define M0PLUS_ICSR_VECTACTIVE_MSB    _u(8)
+#define M0PLUS_ICSR_VECTACTIVE_LSB    _u(0)
+#define M0PLUS_ICSR_VECTACTIVE_ACCESS "RO"
+// =============================================================================
+// Register    : M0PLUS_VTOR
+// Description : The VTOR holds the vector table offset address.
+#define M0PLUS_VTOR_OFFSET _u(0x0000ed08)
+#define M0PLUS_VTOR_BITS   _u(0xffffff00)
+#define M0PLUS_VTOR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_VTOR_TBLOFF
+// Description : Bits [31:8] of the indicate the vector table offset address.
+#define M0PLUS_VTOR_TBLOFF_RESET  _u(0x000000)
+#define M0PLUS_VTOR_TBLOFF_BITS   _u(0xffffff00)
+#define M0PLUS_VTOR_TBLOFF_MSB    _u(31)
+#define M0PLUS_VTOR_TBLOFF_LSB    _u(8)
+#define M0PLUS_VTOR_TBLOFF_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_AIRCR
+// Description : Use the Application Interrupt and Reset Control Register to:
+//               determine data endianness, clear all active state information
+//               from debug halt mode, request a system reset.
+#define M0PLUS_AIRCR_OFFSET _u(0x0000ed0c)
+#define M0PLUS_AIRCR_BITS   _u(0xffff8006)
+#define M0PLUS_AIRCR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_AIRCR_VECTKEY
+// Description : Register key:
+//               Reads as Unknown
+//               On writes, write 0x05FA to VECTKEY, otherwise the write is
+//               ignored.
+#define M0PLUS_AIRCR_VECTKEY_RESET  _u(0x0000)
+#define M0PLUS_AIRCR_VECTKEY_BITS   _u(0xffff0000)
+#define M0PLUS_AIRCR_VECTKEY_MSB    _u(31)
+#define M0PLUS_AIRCR_VECTKEY_LSB    _u(16)
+#define M0PLUS_AIRCR_VECTKEY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_AIRCR_ENDIANESS
+// Description : Data endianness implemented:
+//               0 = Little-endian.
+#define M0PLUS_AIRCR_ENDIANESS_RESET  _u(0x0)
+#define M0PLUS_AIRCR_ENDIANESS_BITS   _u(0x00008000)
+#define M0PLUS_AIRCR_ENDIANESS_MSB    _u(15)
+#define M0PLUS_AIRCR_ENDIANESS_LSB    _u(15)
+#define M0PLUS_AIRCR_ENDIANESS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_AIRCR_SYSRESETREQ
+// Description : Writing 1 to this bit causes the SYSRESETREQ signal to the
+//               outer system to be asserted to request a reset. The intention
+//               is to force a large system reset of all major components except
+//               for debug. The C_HALT bit in the DHCSR is cleared as a result
+//               of the system reset requested. The debugger does not lose
+//               contact with the device.
+#define M0PLUS_AIRCR_SYSRESETREQ_RESET  _u(0x0)
+#define M0PLUS_AIRCR_SYSRESETREQ_BITS   _u(0x00000004)
+#define M0PLUS_AIRCR_SYSRESETREQ_MSB    _u(2)
+#define M0PLUS_AIRCR_SYSRESETREQ_LSB    _u(2)
+#define M0PLUS_AIRCR_SYSRESETREQ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_AIRCR_VECTCLRACTIVE
+// Description : Clears all active state information for fixed and configurable
+//               exceptions. This bit: is self-clearing, can only be set by the
+//               DAP when the core is halted.  When set: clears all active
+//               exception status of the processor, forces a return to Thread
+//               mode, forces an IPSR of 0. A debugger must re-initialize the
+//               stack.
+#define M0PLUS_AIRCR_VECTCLRACTIVE_RESET  _u(0x0)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_BITS   _u(0x00000002)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_MSB    _u(1)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_LSB    _u(1)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_SCR
+// Description : System Control Register. Use the System Control Register for
+//               power-management functions: signal to the system when the
+//               processor can enter a low power state, control how the
+//               processor enters and exits low power states.
+#define M0PLUS_SCR_OFFSET _u(0x0000ed10)
+#define M0PLUS_SCR_BITS   _u(0x00000016)
+#define M0PLUS_SCR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SCR_SEVONPEND
+// Description : Send Event on Pending bit:
+//               0 = Only enabled interrupts or events can wakeup the processor,
+//               disabled interrupts are excluded.
+//               1 = Enabled events and all interrupts, including disabled
+//               interrupts, can wakeup the processor.
+//               When an event or interrupt becomes pending, the event signal
+//               wakes up the processor from WFE. If the
+//               processor is not waiting for an event, the event is registered
+//               and affects the next WFE.
+//               The processor also wakes up on execution of an SEV instruction
+//               or an external event.
+#define M0PLUS_SCR_SEVONPEND_RESET  _u(0x0)
+#define M0PLUS_SCR_SEVONPEND_BITS   _u(0x00000010)
+#define M0PLUS_SCR_SEVONPEND_MSB    _u(4)
+#define M0PLUS_SCR_SEVONPEND_LSB    _u(4)
+#define M0PLUS_SCR_SEVONPEND_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SCR_SLEEPDEEP
+// Description : Controls whether the processor uses sleep or deep sleep as its
+//               low power mode:
+//               0 = Sleep.
+//               1 = Deep sleep.
+#define M0PLUS_SCR_SLEEPDEEP_RESET  _u(0x0)
+#define M0PLUS_SCR_SLEEPDEEP_BITS   _u(0x00000004)
+#define M0PLUS_SCR_SLEEPDEEP_MSB    _u(2)
+#define M0PLUS_SCR_SLEEPDEEP_LSB    _u(2)
+#define M0PLUS_SCR_SLEEPDEEP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SCR_SLEEPONEXIT
+// Description : Indicates sleep-on-exit when returning from Handler mode to
+//               Thread mode:
+//               0 = Do not sleep when returning to Thread mode.
+//               1 = Enter sleep, or deep sleep, on return from an ISR to Thread
+//               mode.
+//               Setting this bit to 1 enables an interrupt driven application
+//               to avoid returning to an empty main application.
+#define M0PLUS_SCR_SLEEPONEXIT_RESET  _u(0x0)
+#define M0PLUS_SCR_SLEEPONEXIT_BITS   _u(0x00000002)
+#define M0PLUS_SCR_SLEEPONEXIT_MSB    _u(1)
+#define M0PLUS_SCR_SLEEPONEXIT_LSB    _u(1)
+#define M0PLUS_SCR_SLEEPONEXIT_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_CCR
+// Description : The Configuration and Control Register permanently enables
+//               stack alignment and causes unaligned accesses to result in a
+//               Hard Fault.
+#define M0PLUS_CCR_OFFSET _u(0x0000ed14)
+#define M0PLUS_CCR_BITS   _u(0x00000208)
+#define M0PLUS_CCR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_CCR_STKALIGN
+// Description : Always reads as one, indicates 8-byte stack alignment on
+//               exception entry. On exception entry, the processor uses bit[9]
+//               of the stacked PSR to indicate the stack alignment. On return
+//               from the exception it uses this stacked bit to restore the
+//               correct stack alignment.
+#define M0PLUS_CCR_STKALIGN_RESET  _u(0x0)
+#define M0PLUS_CCR_STKALIGN_BITS   _u(0x00000200)
+#define M0PLUS_CCR_STKALIGN_MSB    _u(9)
+#define M0PLUS_CCR_STKALIGN_LSB    _u(9)
+#define M0PLUS_CCR_STKALIGN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_CCR_UNALIGN_TRP
+// Description : Always reads as one, indicates that all unaligned accesses
+//               generate a HardFault.
+#define M0PLUS_CCR_UNALIGN_TRP_RESET  _u(0x0)
+#define M0PLUS_CCR_UNALIGN_TRP_BITS   _u(0x00000008)
+#define M0PLUS_CCR_UNALIGN_TRP_MSB    _u(3)
+#define M0PLUS_CCR_UNALIGN_TRP_LSB    _u(3)
+#define M0PLUS_CCR_UNALIGN_TRP_ACCESS "RO"
+// =============================================================================
+// Register    : M0PLUS_SHPR2
+// Description : System handlers are a special class of exception handler that
+//               can have their priority set to any of the priority levels. Use
+//               the System Handler Priority Register 2 to set the priority of
+//               SVCall.
+#define M0PLUS_SHPR2_OFFSET _u(0x0000ed1c)
+#define M0PLUS_SHPR2_BITS   _u(0xc0000000)
+#define M0PLUS_SHPR2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SHPR2_PRI_11
+// Description : Priority of system handler 11, SVCall
+#define M0PLUS_SHPR2_PRI_11_RESET  _u(0x0)
+#define M0PLUS_SHPR2_PRI_11_BITS   _u(0xc0000000)
+#define M0PLUS_SHPR2_PRI_11_MSB    _u(31)
+#define M0PLUS_SHPR2_PRI_11_LSB    _u(30)
+#define M0PLUS_SHPR2_PRI_11_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_SHPR3
+// Description : System handlers are a special class of exception handler that
+//               can have their priority set to any of the priority levels. Use
+//               the System Handler Priority Register 3 to set the priority of
+//               PendSV and SysTick.
+#define M0PLUS_SHPR3_OFFSET _u(0x0000ed20)
+#define M0PLUS_SHPR3_BITS   _u(0xc0c00000)
+#define M0PLUS_SHPR3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SHPR3_PRI_15
+// Description : Priority of system handler 15, SysTick
+#define M0PLUS_SHPR3_PRI_15_RESET  _u(0x0)
+#define M0PLUS_SHPR3_PRI_15_BITS   _u(0xc0000000)
+#define M0PLUS_SHPR3_PRI_15_MSB    _u(31)
+#define M0PLUS_SHPR3_PRI_15_LSB    _u(30)
+#define M0PLUS_SHPR3_PRI_15_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SHPR3_PRI_14
+// Description : Priority of system handler 14, PendSV
+#define M0PLUS_SHPR3_PRI_14_RESET  _u(0x0)
+#define M0PLUS_SHPR3_PRI_14_BITS   _u(0x00c00000)
+#define M0PLUS_SHPR3_PRI_14_MSB    _u(23)
+#define M0PLUS_SHPR3_PRI_14_LSB    _u(22)
+#define M0PLUS_SHPR3_PRI_14_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_SHCSR
+// Description : Use the System Handler Control and State Register to determine
+//               or clear the pending status of SVCall.
+#define M0PLUS_SHCSR_OFFSET _u(0x0000ed24)
+#define M0PLUS_SHCSR_BITS   _u(0x00008000)
+#define M0PLUS_SHCSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SHCSR_SVCALLPENDED
+// Description : Reads as 1 if SVCall is Pending.  Write 1 to set pending
+//               SVCall, write 0 to clear pending SVCall.
+#define M0PLUS_SHCSR_SVCALLPENDED_RESET  _u(0x0)
+#define M0PLUS_SHCSR_SVCALLPENDED_BITS   _u(0x00008000)
+#define M0PLUS_SHCSR_SVCALLPENDED_MSB    _u(15)
+#define M0PLUS_SHCSR_SVCALLPENDED_LSB    _u(15)
+#define M0PLUS_SHCSR_SVCALLPENDED_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_MPU_TYPE
+// Description : Read the MPU Type Register to determine if the processor
+//               implements an MPU, and how many regions the MPU supports.
+#define M0PLUS_MPU_TYPE_OFFSET _u(0x0000ed90)
+#define M0PLUS_MPU_TYPE_BITS   _u(0x00ffff01)
+#define M0PLUS_MPU_TYPE_RESET  _u(0x00000800)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_TYPE_IREGION
+// Description : Instruction region. Reads as zero as ARMv6-M only supports a
+//               unified MPU.
+#define M0PLUS_MPU_TYPE_IREGION_RESET  _u(0x00)
+#define M0PLUS_MPU_TYPE_IREGION_BITS   _u(0x00ff0000)
+#define M0PLUS_MPU_TYPE_IREGION_MSB    _u(23)
+#define M0PLUS_MPU_TYPE_IREGION_LSB    _u(16)
+#define M0PLUS_MPU_TYPE_IREGION_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_TYPE_DREGION
+// Description : Number of regions supported by the MPU.
+#define M0PLUS_MPU_TYPE_DREGION_RESET  _u(0x08)
+#define M0PLUS_MPU_TYPE_DREGION_BITS   _u(0x0000ff00)
+#define M0PLUS_MPU_TYPE_DREGION_MSB    _u(15)
+#define M0PLUS_MPU_TYPE_DREGION_LSB    _u(8)
+#define M0PLUS_MPU_TYPE_DREGION_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_TYPE_SEPARATE
+// Description : Indicates support for separate instruction and data address
+//               maps. Reads as 0 as ARMv6-M only supports a unified MPU.
+#define M0PLUS_MPU_TYPE_SEPARATE_RESET  _u(0x0)
+#define M0PLUS_MPU_TYPE_SEPARATE_BITS   _u(0x00000001)
+#define M0PLUS_MPU_TYPE_SEPARATE_MSB    _u(0)
+#define M0PLUS_MPU_TYPE_SEPARATE_LSB    _u(0)
+#define M0PLUS_MPU_TYPE_SEPARATE_ACCESS "RO"
+// =============================================================================
+// Register    : M0PLUS_MPU_CTRL
+// Description : Use the MPU Control Register to enable and disable the MPU, and
+//               to control whether the default memory map is enabled as a
+//               background region for privileged accesses, and whether the MPU
+//               is enabled for HardFaults and NMIs.
+#define M0PLUS_MPU_CTRL_OFFSET _u(0x0000ed94)
+#define M0PLUS_MPU_CTRL_BITS   _u(0x00000007)
+#define M0PLUS_MPU_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_CTRL_PRIVDEFENA
+// Description : Controls whether the default memory map is enabled as a
+//               background region for privileged accesses. This bit is ignored
+//               when ENABLE is clear.
+//               0 = If the MPU is enabled, disables use of the default memory
+//               map. Any memory access to a location not
+//               covered by any enabled region causes a fault.
+//               1 = If the MPU is enabled, enables use of the default memory
+//               map as a background region for privileged software accesses.
+//               When enabled, the background region acts as if it is region
+//               number -1. Any region that is defined and enabled has priority
+//               over this default map.
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_RESET  _u(0x0)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_BITS   _u(0x00000004)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_MSB    _u(2)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_LSB    _u(2)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_CTRL_HFNMIENA
+// Description : Controls the use of the MPU for HardFaults and NMIs. Setting
+//               this bit when ENABLE is clear results in UNPREDICTABLE
+//               behaviour.
+//               When the MPU is enabled:
+//               0 = MPU is disabled during HardFault and NMI handlers,
+//               regardless of the value of the ENABLE bit.
+//               1 = the MPU is enabled during HardFault and NMI handlers.
+#define M0PLUS_MPU_CTRL_HFNMIENA_RESET  _u(0x0)
+#define M0PLUS_MPU_CTRL_HFNMIENA_BITS   _u(0x00000002)
+#define M0PLUS_MPU_CTRL_HFNMIENA_MSB    _u(1)
+#define M0PLUS_MPU_CTRL_HFNMIENA_LSB    _u(1)
+#define M0PLUS_MPU_CTRL_HFNMIENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_CTRL_ENABLE
+// Description : Enables the MPU. If the MPU is disabled, privileged and
+//               unprivileged accesses use the default memory map.
+//               0 = MPU disabled.
+//               1 = MPU enabled.
+#define M0PLUS_MPU_CTRL_ENABLE_RESET  _u(0x0)
+#define M0PLUS_MPU_CTRL_ENABLE_BITS   _u(0x00000001)
+#define M0PLUS_MPU_CTRL_ENABLE_MSB    _u(0)
+#define M0PLUS_MPU_CTRL_ENABLE_LSB    _u(0)
+#define M0PLUS_MPU_CTRL_ENABLE_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_MPU_RNR
+// Description : Use the MPU Region Number Register to select the region
+//               currently accessed by MPU_RBAR and MPU_RASR.
+#define M0PLUS_MPU_RNR_OFFSET _u(0x0000ed98)
+#define M0PLUS_MPU_RNR_BITS   _u(0x0000000f)
+#define M0PLUS_MPU_RNR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RNR_REGION
+// Description : Indicates the MPU region referenced by the MPU_RBAR and
+//               MPU_RASR registers.
+//               The MPU supports 8 memory regions, so the permitted values of
+//               this field are 0-7.
+#define M0PLUS_MPU_RNR_REGION_RESET  _u(0x0)
+#define M0PLUS_MPU_RNR_REGION_BITS   _u(0x0000000f)
+#define M0PLUS_MPU_RNR_REGION_MSB    _u(3)
+#define M0PLUS_MPU_RNR_REGION_LSB    _u(0)
+#define M0PLUS_MPU_RNR_REGION_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_MPU_RBAR
+// Description : Read the MPU Region Base Address Register to determine the base
+//               address of the region identified by MPU_RNR. Write to update
+//               the base address of said region or that of a specified region,
+//               with whose number MPU_RNR will also be updated.
+#define M0PLUS_MPU_RBAR_OFFSET _u(0x0000ed9c)
+#define M0PLUS_MPU_RBAR_BITS   _u(0xffffff1f)
+#define M0PLUS_MPU_RBAR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RBAR_ADDR
+// Description : Base address of the region.
+#define M0PLUS_MPU_RBAR_ADDR_RESET  _u(0x000000)
+#define M0PLUS_MPU_RBAR_ADDR_BITS   _u(0xffffff00)
+#define M0PLUS_MPU_RBAR_ADDR_MSB    _u(31)
+#define M0PLUS_MPU_RBAR_ADDR_LSB    _u(8)
+#define M0PLUS_MPU_RBAR_ADDR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RBAR_VALID
+// Description : On writes, indicates whether the write must update the base
+//               address of the region identified by the REGION field, updating
+//               the MPU_RNR to indicate this new region.
+//               Write:
+//               0 = MPU_RNR not changed, and the processor:
+//               Updates the base address for the region specified in the
+//               MPU_RNR.
+//               Ignores the value of the REGION field.
+//               1 = The processor:
+//               Updates the value of the MPU_RNR to the value of the REGION
+//               field.
+//               Updates the base address for the region specified in the REGION
+//               field.
+//               Always reads as zero.
+#define M0PLUS_MPU_RBAR_VALID_RESET  _u(0x0)
+#define M0PLUS_MPU_RBAR_VALID_BITS   _u(0x00000010)
+#define M0PLUS_MPU_RBAR_VALID_MSB    _u(4)
+#define M0PLUS_MPU_RBAR_VALID_LSB    _u(4)
+#define M0PLUS_MPU_RBAR_VALID_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RBAR_REGION
+// Description : On writes, specifies the number of the region whose base
+//               address to update provided VALID is set written as 1. On reads,
+//               returns bits [3:0] of MPU_RNR.
+#define M0PLUS_MPU_RBAR_REGION_RESET  _u(0x0)
+#define M0PLUS_MPU_RBAR_REGION_BITS   _u(0x0000000f)
+#define M0PLUS_MPU_RBAR_REGION_MSB    _u(3)
+#define M0PLUS_MPU_RBAR_REGION_LSB    _u(0)
+#define M0PLUS_MPU_RBAR_REGION_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_MPU_RASR
+// Description : Use the MPU Region Attribute and Size Register to define the
+//               size, access behaviour and memory type of the region identified
+//               by MPU_RNR, and enable that region.
+#define M0PLUS_MPU_RASR_OFFSET _u(0x0000eda0)
+#define M0PLUS_MPU_RASR_BITS   _u(0xffffff3f)
+#define M0PLUS_MPU_RASR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RASR_ATTRS
+// Description : The MPU Region Attribute field. Use to define the region
+//               attribute control.
+//               28 = XN: Instruction access disable bit:
+//               0 = Instruction fetches enabled.
+//               1 = Instruction fetches disabled.
+//               26:24 = AP: Access permission field
+//               18 = S: Shareable bit
+//               17 = C: Cacheable bit
+//               16 = B: Bufferable bit
+#define M0PLUS_MPU_RASR_ATTRS_RESET  _u(0x0000)
+#define M0PLUS_MPU_RASR_ATTRS_BITS   _u(0xffff0000)
+#define M0PLUS_MPU_RASR_ATTRS_MSB    _u(31)
+#define M0PLUS_MPU_RASR_ATTRS_LSB    _u(16)
+#define M0PLUS_MPU_RASR_ATTRS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RASR_SRD
+// Description : Subregion Disable. For regions of 256 bytes or larger, each bit
+//               of this field controls whether one of the eight equal
+//               subregions is enabled.
+#define M0PLUS_MPU_RASR_SRD_RESET  _u(0x00)
+#define M0PLUS_MPU_RASR_SRD_BITS   _u(0x0000ff00)
+#define M0PLUS_MPU_RASR_SRD_MSB    _u(15)
+#define M0PLUS_MPU_RASR_SRD_LSB    _u(8)
+#define M0PLUS_MPU_RASR_SRD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RASR_SIZE
+// Description : Indicates the region size. Region size in bytes = 2^(SIZE+1).
+//               The minimum permitted value is 7 (b00111) = 256Bytes
+#define M0PLUS_MPU_RASR_SIZE_RESET  _u(0x00)
+#define M0PLUS_MPU_RASR_SIZE_BITS   _u(0x0000003e)
+#define M0PLUS_MPU_RASR_SIZE_MSB    _u(5)
+#define M0PLUS_MPU_RASR_SIZE_LSB    _u(1)
+#define M0PLUS_MPU_RASR_SIZE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RASR_ENABLE
+// Description : Enables the region.
+#define M0PLUS_MPU_RASR_ENABLE_RESET  _u(0x0)
+#define M0PLUS_MPU_RASR_ENABLE_BITS   _u(0x00000001)
+#define M0PLUS_MPU_RASR_ENABLE_MSB    _u(0)
+#define M0PLUS_MPU_RASR_ENABLE_LSB    _u(0)
+#define M0PLUS_MPU_RASR_ENABLE_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_M0PLUS_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h b/src/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h
new file mode 100644
index 0000000..06102ac
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h
@@ -0,0 +1,2300 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : PADS_BANK0
+// Version        : 1
+// Bus type       : apb
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_PADS_BANK0_DEFINED
+#define HARDWARE_REGS_PADS_BANK0_DEFINED
+// =============================================================================
+// Register    : PADS_BANK0_VOLTAGE_SELECT
+// Description : Voltage select. Per bank control
+//               0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
+//               0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
+#define PADS_BANK0_VOLTAGE_SELECT_OFFSET    _u(0x00000000)
+#define PADS_BANK0_VOLTAGE_SELECT_BITS      _u(0x00000001)
+#define PADS_BANK0_VOLTAGE_SELECT_RESET     _u(0x00000000)
+#define PADS_BANK0_VOLTAGE_SELECT_MSB       _u(0)
+#define PADS_BANK0_VOLTAGE_SELECT_LSB       _u(0)
+#define PADS_BANK0_VOLTAGE_SELECT_ACCESS    "RW"
+#define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)
+#define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)
+// =============================================================================
+// Register    : PADS_BANK0_GPIO0
+// Description : Pad control register
+#define PADS_BANK0_GPIO0_OFFSET _u(0x00000004)
+#define PADS_BANK0_GPIO0_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO0_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO0_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO0_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO0_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO0_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO0_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO0_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO0_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO0_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO0_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO0_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO0_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO0_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO0_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO0_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO0_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO0_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO0_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO0_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO0_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO0_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO0_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO0_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO0_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO0_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO0_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO0_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO0_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO0_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO0_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO0_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO0_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO0_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO0_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO0_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO0_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO0_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO0_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO0_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO0_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO0_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO0_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO0_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO1
+// Description : Pad control register
+#define PADS_BANK0_GPIO1_OFFSET _u(0x00000008)
+#define PADS_BANK0_GPIO1_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO1_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO1_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO1_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO1_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO1_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO1_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO1_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO1_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO1_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO1_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO1_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO1_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO1_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO1_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO1_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO1_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO1_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO1_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO1_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO1_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO1_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO1_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO1_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO1_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO1_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO1_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO1_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO1_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO1_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO1_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO1_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO1_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO1_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO1_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO1_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO1_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO1_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO1_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO1_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO1_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO1_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO1_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO1_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO2
+// Description : Pad control register
+#define PADS_BANK0_GPIO2_OFFSET _u(0x0000000c)
+#define PADS_BANK0_GPIO2_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO2_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO2_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO2_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO2_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO2_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO2_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO2_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO2_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO2_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO2_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO2_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO2_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO2_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO2_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO2_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO2_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO2_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO2_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO2_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO2_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO2_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO2_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO2_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO2_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO2_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO2_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO2_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO2_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO2_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO2_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO2_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO2_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO2_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO2_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO2_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO2_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO2_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO2_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO2_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO2_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO2_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO2_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO2_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO3
+// Description : Pad control register
+#define PADS_BANK0_GPIO3_OFFSET _u(0x00000010)
+#define PADS_BANK0_GPIO3_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO3_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO3_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO3_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO3_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO3_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO3_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO3_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO3_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO3_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO3_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO3_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO3_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO3_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO3_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO3_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO3_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO3_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO3_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO3_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO3_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO3_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO3_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO3_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO3_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO3_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO3_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO3_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO3_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO3_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO3_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO3_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO3_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO3_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO3_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO3_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO3_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO3_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO3_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO3_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO3_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO3_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO3_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO3_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO4
+// Description : Pad control register
+#define PADS_BANK0_GPIO4_OFFSET _u(0x00000014)
+#define PADS_BANK0_GPIO4_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO4_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO4_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO4_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO4_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO4_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO4_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO4_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO4_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO4_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO4_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO4_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO4_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO4_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO4_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO4_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO4_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO4_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO4_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO4_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO4_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO4_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO4_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO4_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO4_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO4_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO4_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO4_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO4_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO4_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO4_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO4_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO4_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO4_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO4_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO4_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO4_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO4_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO4_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO4_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO4_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO4_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO4_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO4_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO5
+// Description : Pad control register
+#define PADS_BANK0_GPIO5_OFFSET _u(0x00000018)
+#define PADS_BANK0_GPIO5_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO5_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO5_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO5_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO5_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO5_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO5_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO5_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO5_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO5_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO5_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO5_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO5_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO5_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO5_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO5_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO5_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO5_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO5_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO5_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO5_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO5_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO5_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO5_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO5_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO5_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO5_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO5_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO5_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO5_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO5_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO5_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO5_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO5_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO5_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO5_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO5_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO5_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO5_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO5_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO5_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO5_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO5_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO5_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO6
+// Description : Pad control register
+#define PADS_BANK0_GPIO6_OFFSET _u(0x0000001c)
+#define PADS_BANK0_GPIO6_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO6_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO6_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO6_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO6_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO6_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO6_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO6_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO6_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO6_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO6_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO6_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO6_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO6_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO6_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO6_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO6_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO6_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO6_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO6_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO6_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO6_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO6_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO6_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO6_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO6_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO6_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO6_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO6_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO6_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO6_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO6_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO6_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO6_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO6_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO6_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO6_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO6_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO6_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO6_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO6_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO6_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO6_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO6_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO7
+// Description : Pad control register
+#define PADS_BANK0_GPIO7_OFFSET _u(0x00000020)
+#define PADS_BANK0_GPIO7_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO7_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO7_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO7_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO7_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO7_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO7_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO7_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO7_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO7_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO7_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO7_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO7_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO7_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO7_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO7_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO7_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO7_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO7_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO7_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO7_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO7_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO7_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO7_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO7_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO7_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO7_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO7_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO7_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO7_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO7_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO7_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO7_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO7_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO7_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO7_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO7_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO7_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO7_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO7_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO7_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO7_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO7_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO7_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO8
+// Description : Pad control register
+#define PADS_BANK0_GPIO8_OFFSET _u(0x00000024)
+#define PADS_BANK0_GPIO8_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO8_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO8_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO8_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO8_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO8_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO8_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO8_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO8_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO8_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO8_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO8_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO8_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO8_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO8_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO8_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO8_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO8_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO8_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO8_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO8_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO8_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO8_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO8_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO8_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO8_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO8_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO8_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO8_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO8_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO8_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO8_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO8_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO8_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO8_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO8_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO8_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO8_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO8_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO8_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO8_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO8_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO8_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO8_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO9
+// Description : Pad control register
+#define PADS_BANK0_GPIO9_OFFSET _u(0x00000028)
+#define PADS_BANK0_GPIO9_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO9_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO9_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO9_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO9_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO9_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO9_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO9_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO9_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO9_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO9_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO9_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO9_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO9_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO9_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO9_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO9_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO9_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO9_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO9_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO9_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO9_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO9_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO9_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO9_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO9_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO9_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO9_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO9_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO9_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO9_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO9_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO9_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO9_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO9_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO9_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO9_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO9_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO9_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO9_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO9_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO9_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO9_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO9_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO10
+// Description : Pad control register
+#define PADS_BANK0_GPIO10_OFFSET _u(0x0000002c)
+#define PADS_BANK0_GPIO10_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO10_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO10_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO10_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO10_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO10_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO10_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO10_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO10_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO10_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO10_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO10_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO10_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO10_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO10_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO10_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO10_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO10_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO10_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO10_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO10_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO10_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO10_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO10_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO10_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO10_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO10_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO10_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO10_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO10_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO10_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO10_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO10_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO10_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO10_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO10_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO10_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO10_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO10_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO10_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO10_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO10_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO10_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO10_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO11
+// Description : Pad control register
+#define PADS_BANK0_GPIO11_OFFSET _u(0x00000030)
+#define PADS_BANK0_GPIO11_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO11_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO11_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO11_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO11_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO11_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO11_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO11_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO11_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO11_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO11_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO11_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO11_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO11_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO11_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO11_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO11_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO11_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO11_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO11_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO11_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO11_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO11_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO11_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO11_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO11_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO11_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO11_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO11_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO11_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO11_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO11_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO11_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO11_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO11_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO11_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO11_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO11_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO11_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO11_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO11_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO11_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO11_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO11_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO12
+// Description : Pad control register
+#define PADS_BANK0_GPIO12_OFFSET _u(0x00000034)
+#define PADS_BANK0_GPIO12_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO12_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO12_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO12_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO12_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO12_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO12_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO12_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO12_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO12_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO12_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO12_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO12_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO12_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO12_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO12_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO12_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO12_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO12_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO12_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO12_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO12_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO12_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO12_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO12_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO12_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO12_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO12_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO12_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO12_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO12_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO12_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO12_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO12_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO12_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO12_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO12_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO12_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO12_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO12_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO12_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO12_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO12_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO12_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO13
+// Description : Pad control register
+#define PADS_BANK0_GPIO13_OFFSET _u(0x00000038)
+#define PADS_BANK0_GPIO13_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO13_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO13_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO13_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO13_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO13_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO13_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO13_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO13_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO13_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO13_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO13_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO13_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO13_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO13_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO13_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO13_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO13_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO13_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO13_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO13_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO13_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO13_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO13_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO13_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO13_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO13_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO13_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO13_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO13_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO13_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO13_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO13_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO13_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO13_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO13_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO13_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO13_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO13_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO13_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO13_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO13_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO13_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO13_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO14
+// Description : Pad control register
+#define PADS_BANK0_GPIO14_OFFSET _u(0x0000003c)
+#define PADS_BANK0_GPIO14_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO14_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO14_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO14_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO14_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO14_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO14_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO14_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO14_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO14_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO14_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO14_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO14_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO14_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO14_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO14_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO14_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO14_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO14_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO14_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO14_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO14_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO14_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO14_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO14_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO14_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO14_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO14_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO14_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO14_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO14_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO14_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO14_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO14_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO14_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO14_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO14_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO14_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO14_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO14_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO14_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO14_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO14_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO14_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO15
+// Description : Pad control register
+#define PADS_BANK0_GPIO15_OFFSET _u(0x00000040)
+#define PADS_BANK0_GPIO15_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO15_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO15_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO15_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO15_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO15_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO15_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO15_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO15_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO15_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO15_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO15_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO15_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO15_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO15_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO15_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO15_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO15_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO15_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO15_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO15_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO15_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO15_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO15_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO15_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO15_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO15_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO15_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO15_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO15_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO15_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO15_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO15_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO15_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO15_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO15_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO15_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO15_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO15_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO15_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO15_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO15_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO15_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO15_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO16
+// Description : Pad control register
+#define PADS_BANK0_GPIO16_OFFSET _u(0x00000044)
+#define PADS_BANK0_GPIO16_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO16_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO16_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO16_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO16_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO16_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO16_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO16_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO16_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO16_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO16_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO16_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO16_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO16_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO16_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO16_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO16_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO16_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO16_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO16_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO16_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO16_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO16_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO16_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO16_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO16_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO16_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO16_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO16_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO16_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO16_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO16_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO16_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO16_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO16_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO16_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO16_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO16_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO16_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO16_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO16_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO16_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO16_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO16_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO17
+// Description : Pad control register
+#define PADS_BANK0_GPIO17_OFFSET _u(0x00000048)
+#define PADS_BANK0_GPIO17_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO17_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO17_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO17_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO17_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO17_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO17_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO17_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO17_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO17_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO17_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO17_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO17_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO17_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO17_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO17_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO17_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO17_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO17_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO17_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO17_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO17_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO17_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO17_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO17_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO17_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO17_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO17_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO17_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO17_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO17_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO17_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO17_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO17_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO17_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO17_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO17_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO17_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO17_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO17_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO17_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO17_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO17_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO17_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO18
+// Description : Pad control register
+#define PADS_BANK0_GPIO18_OFFSET _u(0x0000004c)
+#define PADS_BANK0_GPIO18_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO18_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO18_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO18_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO18_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO18_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO18_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO18_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO18_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO18_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO18_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO18_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO18_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO18_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO18_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO18_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO18_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO18_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO18_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO18_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO18_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO18_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO18_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO18_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO18_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO18_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO18_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO18_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO18_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO18_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO18_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO18_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO18_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO18_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO18_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO18_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO18_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO18_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO18_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO18_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO18_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO18_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO18_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO18_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO19
+// Description : Pad control register
+#define PADS_BANK0_GPIO19_OFFSET _u(0x00000050)
+#define PADS_BANK0_GPIO19_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO19_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO19_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO19_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO19_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO19_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO19_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO19_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO19_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO19_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO19_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO19_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO19_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO19_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO19_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO19_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO19_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO19_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO19_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO19_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO19_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO19_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO19_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO19_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO19_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO19_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO19_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO19_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO19_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO19_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO19_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO19_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO19_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO19_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO19_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO19_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO19_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO19_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO19_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO19_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO19_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO19_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO19_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO19_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO20
+// Description : Pad control register
+#define PADS_BANK0_GPIO20_OFFSET _u(0x00000054)
+#define PADS_BANK0_GPIO20_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO20_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO20_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO20_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO20_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO20_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO20_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO20_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO20_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO20_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO20_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO20_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO20_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO20_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO20_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO20_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO20_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO20_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO20_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO20_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO20_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO20_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO20_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO20_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO20_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO20_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO20_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO20_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO20_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO20_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO20_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO20_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO20_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO20_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO20_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO20_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO20_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO20_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO20_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO20_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO20_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO20_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO20_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO20_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO21
+// Description : Pad control register
+#define PADS_BANK0_GPIO21_OFFSET _u(0x00000058)
+#define PADS_BANK0_GPIO21_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO21_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO21_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO21_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO21_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO21_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO21_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO21_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO21_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO21_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO21_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO21_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO21_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO21_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO21_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO21_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO21_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO21_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO21_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO21_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO21_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO21_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO21_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO21_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO21_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO21_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO21_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO21_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO21_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO21_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO21_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO21_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO21_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO21_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO21_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO21_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO21_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO21_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO21_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO21_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO21_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO21_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO21_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO21_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO22
+// Description : Pad control register
+#define PADS_BANK0_GPIO22_OFFSET _u(0x0000005c)
+#define PADS_BANK0_GPIO22_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO22_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO22_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO22_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO22_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO22_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO22_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO22_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO22_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO22_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO22_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO22_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO22_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO22_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO22_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO22_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO22_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO22_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO22_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO22_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO22_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO22_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO22_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO22_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO22_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO22_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO22_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO22_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO22_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO22_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO22_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO22_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO22_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO22_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO22_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO22_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO22_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO22_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO22_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO22_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO22_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO22_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO22_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO22_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO23
+// Description : Pad control register
+#define PADS_BANK0_GPIO23_OFFSET _u(0x00000060)
+#define PADS_BANK0_GPIO23_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO23_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO23_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO23_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO23_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO23_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO23_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO23_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO23_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO23_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO23_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO23_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO23_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO23_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO23_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO23_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO23_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO23_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO23_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO23_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO23_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO23_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO23_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO23_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO23_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO23_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO23_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO23_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO23_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO23_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO23_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO23_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO23_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO23_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO23_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO23_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO23_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO23_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO23_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO23_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO23_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO23_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO23_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO23_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO24
+// Description : Pad control register
+#define PADS_BANK0_GPIO24_OFFSET _u(0x00000064)
+#define PADS_BANK0_GPIO24_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO24_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO24_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO24_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO24_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO24_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO24_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO24_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO24_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO24_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO24_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO24_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO24_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO24_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO24_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO24_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO24_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO24_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO24_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO24_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO24_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO24_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO24_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO24_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO24_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO24_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO24_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO24_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO24_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO24_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO24_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO24_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO24_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO24_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO24_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO24_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO24_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO24_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO24_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO24_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO24_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO24_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO24_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO24_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO25
+// Description : Pad control register
+#define PADS_BANK0_GPIO25_OFFSET _u(0x00000068)
+#define PADS_BANK0_GPIO25_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO25_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO25_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO25_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO25_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO25_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO25_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO25_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO25_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO25_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO25_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO25_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO25_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO25_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO25_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO25_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO25_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO25_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO25_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO25_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO25_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO25_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO25_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO25_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO25_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO25_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO25_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO25_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO25_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO25_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO25_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO25_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO25_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO25_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO25_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO25_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO25_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO25_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO25_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO25_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO25_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO25_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO25_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO25_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO26
+// Description : Pad control register
+#define PADS_BANK0_GPIO26_OFFSET _u(0x0000006c)
+#define PADS_BANK0_GPIO26_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO26_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO26_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO26_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO26_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO26_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO26_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO26_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO26_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO26_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO26_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO26_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO26_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO26_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO26_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO26_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO26_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO26_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO26_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO26_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO26_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO26_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO26_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO26_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO26_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO26_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO26_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO26_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO26_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO26_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO26_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO26_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO26_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO26_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO26_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO26_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO26_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO26_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO26_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO26_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO26_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO26_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO26_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO26_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO27
+// Description : Pad control register
+#define PADS_BANK0_GPIO27_OFFSET _u(0x00000070)
+#define PADS_BANK0_GPIO27_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO27_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO27_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO27_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO27_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO27_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO27_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO27_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO27_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO27_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO27_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO27_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO27_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO27_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO27_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO27_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO27_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO27_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO27_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO27_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO27_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO27_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO27_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO27_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO27_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO27_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO27_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO27_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO27_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO27_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO27_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO27_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO27_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO27_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO27_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO27_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO27_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO27_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO27_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO27_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO27_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO27_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO27_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO27_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO28
+// Description : Pad control register
+#define PADS_BANK0_GPIO28_OFFSET _u(0x00000074)
+#define PADS_BANK0_GPIO28_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO28_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO28_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO28_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO28_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO28_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO28_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO28_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO28_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO28_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO28_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO28_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO28_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO28_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO28_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO28_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO28_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO28_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO28_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO28_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO28_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO28_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO28_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO28_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO28_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO28_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO28_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO28_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO28_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO28_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO28_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO28_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO28_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO28_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO28_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO28_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO28_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO28_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO28_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO28_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO28_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO28_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO28_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO28_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_GPIO29
+// Description : Pad control register
+#define PADS_BANK0_GPIO29_OFFSET _u(0x00000078)
+#define PADS_BANK0_GPIO29_BITS   _u(0x000000ff)
+#define PADS_BANK0_GPIO29_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO29_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_GPIO29_OD_RESET  _u(0x0)
+#define PADS_BANK0_GPIO29_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_GPIO29_OD_MSB    _u(7)
+#define PADS_BANK0_GPIO29_OD_LSB    _u(7)
+#define PADS_BANK0_GPIO29_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO29_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO29_IE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO29_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_GPIO29_IE_MSB    _u(6)
+#define PADS_BANK0_GPIO29_IE_LSB    _u(6)
+#define PADS_BANK0_GPIO29_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO29_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_GPIO29_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_GPIO29_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_GPIO29_DRIVE_MSB        _u(5)
+#define PADS_BANK0_GPIO29_DRIVE_LSB        _u(4)
+#define PADS_BANK0_GPIO29_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO29_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO29_PUE_RESET  _u(0x0)
+#define PADS_BANK0_GPIO29_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_GPIO29_PUE_MSB    _u(3)
+#define PADS_BANK0_GPIO29_PUE_LSB    _u(3)
+#define PADS_BANK0_GPIO29_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO29_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO29_PDE_RESET  _u(0x1)
+#define PADS_BANK0_GPIO29_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_GPIO29_PDE_MSB    _u(2)
+#define PADS_BANK0_GPIO29_PDE_LSB    _u(2)
+#define PADS_BANK0_GPIO29_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO29_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO29_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_GPIO29_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_GPIO29_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_GPIO29_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_GPIO29_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_GPIO29_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO29_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_GPIO29_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_GPIO29_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_GPIO29_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_GPIO29_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_SWCLK
+// Description : Pad control register
+#define PADS_BANK0_SWCLK_OFFSET _u(0x0000007c)
+#define PADS_BANK0_SWCLK_BITS   _u(0x000000ff)
+#define PADS_BANK0_SWCLK_RESET  _u(0x000000da)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_SWCLK_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_SWCLK_OD_RESET  _u(0x1)
+#define PADS_BANK0_SWCLK_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_SWCLK_OD_MSB    _u(7)
+#define PADS_BANK0_SWCLK_OD_LSB    _u(7)
+#define PADS_BANK0_SWCLK_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_SWCLK_IE
+// Description : Input enable
+#define PADS_BANK0_SWCLK_IE_RESET  _u(0x1)
+#define PADS_BANK0_SWCLK_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_SWCLK_IE_MSB    _u(6)
+#define PADS_BANK0_SWCLK_IE_LSB    _u(6)
+#define PADS_BANK0_SWCLK_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_SWCLK_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_SWCLK_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_SWCLK_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_SWCLK_DRIVE_MSB        _u(5)
+#define PADS_BANK0_SWCLK_DRIVE_LSB        _u(4)
+#define PADS_BANK0_SWCLK_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_SWCLK_PUE
+// Description : Pull up enable
+#define PADS_BANK0_SWCLK_PUE_RESET  _u(0x1)
+#define PADS_BANK0_SWCLK_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_SWCLK_PUE_MSB    _u(3)
+#define PADS_BANK0_SWCLK_PUE_LSB    _u(3)
+#define PADS_BANK0_SWCLK_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_SWCLK_PDE
+// Description : Pull down enable
+#define PADS_BANK0_SWCLK_PDE_RESET  _u(0x0)
+#define PADS_BANK0_SWCLK_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_SWCLK_PDE_MSB    _u(2)
+#define PADS_BANK0_SWCLK_PDE_LSB    _u(2)
+#define PADS_BANK0_SWCLK_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_SWCLK_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_SWCLK_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_SWCLK_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_SWCLK_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_SWCLK_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_SWCLK_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_SWCLK_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_SWCLK_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_SWCLK_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_SWCLK_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_SWCLK_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_SWCLK_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_BANK0_SWD
+// Description : Pad control register
+#define PADS_BANK0_SWD_OFFSET _u(0x00000080)
+#define PADS_BANK0_SWD_BITS   _u(0x000000ff)
+#define PADS_BANK0_SWD_RESET  _u(0x0000005a)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_SWD_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_BANK0_SWD_OD_RESET  _u(0x0)
+#define PADS_BANK0_SWD_OD_BITS   _u(0x00000080)
+#define PADS_BANK0_SWD_OD_MSB    _u(7)
+#define PADS_BANK0_SWD_OD_LSB    _u(7)
+#define PADS_BANK0_SWD_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_SWD_IE
+// Description : Input enable
+#define PADS_BANK0_SWD_IE_RESET  _u(0x1)
+#define PADS_BANK0_SWD_IE_BITS   _u(0x00000040)
+#define PADS_BANK0_SWD_IE_MSB    _u(6)
+#define PADS_BANK0_SWD_IE_LSB    _u(6)
+#define PADS_BANK0_SWD_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_SWD_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_BANK0_SWD_DRIVE_RESET      _u(0x1)
+#define PADS_BANK0_SWD_DRIVE_BITS       _u(0x00000030)
+#define PADS_BANK0_SWD_DRIVE_MSB        _u(5)
+#define PADS_BANK0_SWD_DRIVE_LSB        _u(4)
+#define PADS_BANK0_SWD_DRIVE_ACCESS     "RW"
+#define PADS_BANK0_SWD_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_BANK0_SWD_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_BANK0_SWD_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_BANK0_SWD_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_SWD_PUE
+// Description : Pull up enable
+#define PADS_BANK0_SWD_PUE_RESET  _u(0x1)
+#define PADS_BANK0_SWD_PUE_BITS   _u(0x00000008)
+#define PADS_BANK0_SWD_PUE_MSB    _u(3)
+#define PADS_BANK0_SWD_PUE_LSB    _u(3)
+#define PADS_BANK0_SWD_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_SWD_PDE
+// Description : Pull down enable
+#define PADS_BANK0_SWD_PDE_RESET  _u(0x0)
+#define PADS_BANK0_SWD_PDE_BITS   _u(0x00000004)
+#define PADS_BANK0_SWD_PDE_MSB    _u(2)
+#define PADS_BANK0_SWD_PDE_LSB    _u(2)
+#define PADS_BANK0_SWD_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_SWD_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_SWD_SCHMITT_RESET  _u(0x1)
+#define PADS_BANK0_SWD_SCHMITT_BITS   _u(0x00000002)
+#define PADS_BANK0_SWD_SCHMITT_MSB    _u(1)
+#define PADS_BANK0_SWD_SCHMITT_LSB    _u(1)
+#define PADS_BANK0_SWD_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_BANK0_SWD_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_SWD_SLEWFAST_RESET  _u(0x0)
+#define PADS_BANK0_SWD_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_BANK0_SWD_SLEWFAST_MSB    _u(0)
+#define PADS_BANK0_SWD_SLEWFAST_LSB    _u(0)
+#define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_PADS_BANK0_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h b/src/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h
new file mode 100644
index 0000000..b3a09e9
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h
@@ -0,0 +1,454 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : PADS_QSPI
+// Version        : 1
+// Bus type       : apb
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_PADS_QSPI_DEFINED
+#define HARDWARE_REGS_PADS_QSPI_DEFINED
+// =============================================================================
+// Register    : PADS_QSPI_VOLTAGE_SELECT
+// Description : Voltage select. Per bank control
+//               0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
+//               0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
+#define PADS_QSPI_VOLTAGE_SELECT_OFFSET    _u(0x00000000)
+#define PADS_QSPI_VOLTAGE_SELECT_BITS      _u(0x00000001)
+#define PADS_QSPI_VOLTAGE_SELECT_RESET     _u(0x00000000)
+#define PADS_QSPI_VOLTAGE_SELECT_MSB       _u(0)
+#define PADS_QSPI_VOLTAGE_SELECT_LSB       _u(0)
+#define PADS_QSPI_VOLTAGE_SELECT_ACCESS    "RW"
+#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)
+#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)
+// =============================================================================
+// Register    : PADS_QSPI_GPIO_QSPI_SCLK
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SCLK_BITS   _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SCLK_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SCLK_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS   _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SCLK_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS   _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET      _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS       _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB        _u(5)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB        _u(4)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS     "RW"
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SCLK_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS   _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SCLK_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS   _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS   _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_QSPI_GPIO_QSPI_SD0
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD0_BITS   _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD0_RESET  _u(0x00000052)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD0_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS   _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD0_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS   _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD0_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET      _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS       _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB        _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB        _u(4)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS     "RW"
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD0_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS   _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD0_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS   _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS   _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_QSPI_GPIO_QSPI_SD1
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c)
+#define PADS_QSPI_GPIO_QSPI_SD1_BITS   _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD1_RESET  _u(0x00000052)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD1_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS   _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD1_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS   _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD1_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET      _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS       _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB        _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB        _u(4)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS     "RW"
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD1_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS   _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD1_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS   _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS   _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_QSPI_GPIO_QSPI_SD2
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010)
+#define PADS_QSPI_GPIO_QSPI_SD2_BITS   _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD2_RESET  _u(0x00000052)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD2_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS   _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD2_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS   _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD2_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET      _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS       _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB        _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB        _u(4)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS     "RW"
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD2_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS   _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD2_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS   _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS   _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_QSPI_GPIO_QSPI_SD3
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014)
+#define PADS_QSPI_GPIO_QSPI_SD3_BITS   _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD3_RESET  _u(0x00000052)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD3_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS   _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD3_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS   _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD3_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET      _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS       _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB        _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB        _u(4)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS     "RW"
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD3_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS   _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD3_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS   _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS   _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_QSPI_GPIO_QSPI_SS
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018)
+#define PADS_QSPI_GPIO_QSPI_SS_BITS   _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SS_RESET  _u(0x0000005a)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SS_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS   _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SS_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS   _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SS_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET      _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS       _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB        _u(5)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB        _u(4)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS     "RW"
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SS_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS   _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SS_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS   _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SS_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS   _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_PADS_QSPI_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pio.h b/src/rp2040/hardware_regs/include/hardware/regs/pio.h
new file mode 100644
index 0000000..b231882
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/pio.h
@@ -0,0 +1,2764 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : PIO
+// Version        : 1
+// Bus type       : ahbl
+// Description    : Programmable IO block
+// =============================================================================
+#ifndef HARDWARE_REGS_PIO_DEFINED
+#define HARDWARE_REGS_PIO_DEFINED
+// =============================================================================
+// Register    : PIO_CTRL
+// Description : PIO control register
+#define PIO_CTRL_OFFSET _u(0x00000000)
+#define PIO_CTRL_BITS   _u(0x00000fff)
+#define PIO_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_CTRL_CLKDIV_RESTART
+// Description : Restart a state machine's clock divider from an initial phase
+//               of 0. Clock dividers are free-running, so once started, their
+//               output (including fractional jitter) is completely determined
+//               by the integer/fractional divisor configured in SMx_CLKDIV.
+//               This means that, if multiple clock dividers with the same
+//               divisor are restarted simultaneously, by writing multiple 1
+//               bits to this field, the execution clocks of those state
+//               machines will run in precise lockstep.
+//
+//               Note that setting/clearing SM_ENABLE does not stop the clock
+//               divider from running, so once multiple state machines' clocks
+//               are synchronised, it is safe to disable/reenable a state
+//               machine, whilst keeping the clock dividers in sync.
+//
+//               Note also that CLKDIV_RESTART can be written to whilst the
+//               state machine is running, and this is useful to resynchronise
+//               clock dividers after the divisors (SMx_CLKDIV) have been
+//               changed on-the-fly.
+#define PIO_CTRL_CLKDIV_RESTART_RESET  _u(0x0)
+#define PIO_CTRL_CLKDIV_RESTART_BITS   _u(0x00000f00)
+#define PIO_CTRL_CLKDIV_RESTART_MSB    _u(11)
+#define PIO_CTRL_CLKDIV_RESTART_LSB    _u(8)
+#define PIO_CTRL_CLKDIV_RESTART_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PIO_CTRL_SM_RESTART
+// Description : Write 1 to instantly clear internal SM state which may be
+//               otherwise difficult to access and will affect future execution.
+//
+//               Specifically, the following are cleared: input and output shift
+//               counters; the contents of the input shift register; the delay
+//               counter; the waiting-on-IRQ state; any stalled instruction
+//               written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left
+//               asserted due to OUT_STICKY.
+#define PIO_CTRL_SM_RESTART_RESET  _u(0x0)
+#define PIO_CTRL_SM_RESTART_BITS   _u(0x000000f0)
+#define PIO_CTRL_SM_RESTART_MSB    _u(7)
+#define PIO_CTRL_SM_RESTART_LSB    _u(4)
+#define PIO_CTRL_SM_RESTART_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PIO_CTRL_SM_ENABLE
+// Description : Enable/disable each of the four state machines by writing 1/0
+//               to each of these four bits. When disabled, a state machine will
+//               cease executing instructions, except those written directly to
+//               SMx_INSTR by the system. Multiple bits can be set/cleared at
+//               once to run/halt multiple state machines simultaneously.
+#define PIO_CTRL_SM_ENABLE_RESET  _u(0x0)
+#define PIO_CTRL_SM_ENABLE_BITS   _u(0x0000000f)
+#define PIO_CTRL_SM_ENABLE_MSB    _u(3)
+#define PIO_CTRL_SM_ENABLE_LSB    _u(0)
+#define PIO_CTRL_SM_ENABLE_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_FSTAT
+// Description : FIFO status register
+#define PIO_FSTAT_OFFSET _u(0x00000004)
+#define PIO_FSTAT_BITS   _u(0x0f0f0f0f)
+#define PIO_FSTAT_RESET  _u(0x0f000f00)
+// -----------------------------------------------------------------------------
+// Field       : PIO_FSTAT_TXEMPTY
+// Description : State machine TX FIFO is empty
+#define PIO_FSTAT_TXEMPTY_RESET  _u(0xf)
+#define PIO_FSTAT_TXEMPTY_BITS   _u(0x0f000000)
+#define PIO_FSTAT_TXEMPTY_MSB    _u(27)
+#define PIO_FSTAT_TXEMPTY_LSB    _u(24)
+#define PIO_FSTAT_TXEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_FSTAT_TXFULL
+// Description : State machine TX FIFO is full
+#define PIO_FSTAT_TXFULL_RESET  _u(0x0)
+#define PIO_FSTAT_TXFULL_BITS   _u(0x000f0000)
+#define PIO_FSTAT_TXFULL_MSB    _u(19)
+#define PIO_FSTAT_TXFULL_LSB    _u(16)
+#define PIO_FSTAT_TXFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_FSTAT_RXEMPTY
+// Description : State machine RX FIFO is empty
+#define PIO_FSTAT_RXEMPTY_RESET  _u(0xf)
+#define PIO_FSTAT_RXEMPTY_BITS   _u(0x00000f00)
+#define PIO_FSTAT_RXEMPTY_MSB    _u(11)
+#define PIO_FSTAT_RXEMPTY_LSB    _u(8)
+#define PIO_FSTAT_RXEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_FSTAT_RXFULL
+// Description : State machine RX FIFO is full
+#define PIO_FSTAT_RXFULL_RESET  _u(0x0)
+#define PIO_FSTAT_RXFULL_BITS   _u(0x0000000f)
+#define PIO_FSTAT_RXFULL_MSB    _u(3)
+#define PIO_FSTAT_RXFULL_LSB    _u(0)
+#define PIO_FSTAT_RXFULL_ACCESS "RO"
+// =============================================================================
+// Register    : PIO_FDEBUG
+// Description : FIFO debug register
+#define PIO_FDEBUG_OFFSET _u(0x00000008)
+#define PIO_FDEBUG_BITS   _u(0x0f0f0f0f)
+#define PIO_FDEBUG_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_FDEBUG_TXSTALL
+// Description : State machine has stalled on empty TX FIFO during a blocking
+//               PULL, or an OUT with autopull enabled. Write 1 to clear.
+#define PIO_FDEBUG_TXSTALL_RESET  _u(0x0)
+#define PIO_FDEBUG_TXSTALL_BITS   _u(0x0f000000)
+#define PIO_FDEBUG_TXSTALL_MSB    _u(27)
+#define PIO_FDEBUG_TXSTALL_LSB    _u(24)
+#define PIO_FDEBUG_TXSTALL_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : PIO_FDEBUG_TXOVER
+// Description : TX FIFO overflow (i.e. write-on-full by the system) has
+//               occurred. Write 1 to clear. Note that write-on-full does not
+//               alter the state or contents of the FIFO in any way, but the
+//               data that the system attempted to write is dropped, so if this
+//               flag is set, your software has quite likely dropped some data
+//               on the floor.
+#define PIO_FDEBUG_TXOVER_RESET  _u(0x0)
+#define PIO_FDEBUG_TXOVER_BITS   _u(0x000f0000)
+#define PIO_FDEBUG_TXOVER_MSB    _u(19)
+#define PIO_FDEBUG_TXOVER_LSB    _u(16)
+#define PIO_FDEBUG_TXOVER_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : PIO_FDEBUG_RXUNDER
+// Description : RX FIFO underflow (i.e. read-on-empty by the system) has
+//               occurred. Write 1 to clear. Note that read-on-empty does not
+//               perturb the state of the FIFO in any way, but the data returned
+//               by reading from an empty FIFO is undefined, so this flag
+//               generally only becomes set due to some kind of software error.
+#define PIO_FDEBUG_RXUNDER_RESET  _u(0x0)
+#define PIO_FDEBUG_RXUNDER_BITS   _u(0x00000f00)
+#define PIO_FDEBUG_RXUNDER_MSB    _u(11)
+#define PIO_FDEBUG_RXUNDER_LSB    _u(8)
+#define PIO_FDEBUG_RXUNDER_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : PIO_FDEBUG_RXSTALL
+// Description : State machine has stalled on full RX FIFO during a blocking
+//               PUSH, or an IN with autopush enabled. This flag is also set
+//               when a nonblocking PUSH to a full FIFO took place, in which
+//               case the state machine has dropped data. Write 1 to clear.
+#define PIO_FDEBUG_RXSTALL_RESET  _u(0x0)
+#define PIO_FDEBUG_RXSTALL_BITS   _u(0x0000000f)
+#define PIO_FDEBUG_RXSTALL_MSB    _u(3)
+#define PIO_FDEBUG_RXSTALL_LSB    _u(0)
+#define PIO_FDEBUG_RXSTALL_ACCESS "WC"
+// =============================================================================
+// Register    : PIO_FLEVEL
+// Description : FIFO levels
+#define PIO_FLEVEL_OFFSET _u(0x0000000c)
+#define PIO_FLEVEL_BITS   _u(0xffffffff)
+#define PIO_FLEVEL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_FLEVEL_RX3
+// Description : None
+#define PIO_FLEVEL_RX3_RESET  _u(0x0)
+#define PIO_FLEVEL_RX3_BITS   _u(0xf0000000)
+#define PIO_FLEVEL_RX3_MSB    _u(31)
+#define PIO_FLEVEL_RX3_LSB    _u(28)
+#define PIO_FLEVEL_RX3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_FLEVEL_TX3
+// Description : None
+#define PIO_FLEVEL_TX3_RESET  _u(0x0)
+#define PIO_FLEVEL_TX3_BITS   _u(0x0f000000)
+#define PIO_FLEVEL_TX3_MSB    _u(27)
+#define PIO_FLEVEL_TX3_LSB    _u(24)
+#define PIO_FLEVEL_TX3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_FLEVEL_RX2
+// Description : None
+#define PIO_FLEVEL_RX2_RESET  _u(0x0)
+#define PIO_FLEVEL_RX2_BITS   _u(0x00f00000)
+#define PIO_FLEVEL_RX2_MSB    _u(23)
+#define PIO_FLEVEL_RX2_LSB    _u(20)
+#define PIO_FLEVEL_RX2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_FLEVEL_TX2
+// Description : None
+#define PIO_FLEVEL_TX2_RESET  _u(0x0)
+#define PIO_FLEVEL_TX2_BITS   _u(0x000f0000)
+#define PIO_FLEVEL_TX2_MSB    _u(19)
+#define PIO_FLEVEL_TX2_LSB    _u(16)
+#define PIO_FLEVEL_TX2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_FLEVEL_RX1
+// Description : None
+#define PIO_FLEVEL_RX1_RESET  _u(0x0)
+#define PIO_FLEVEL_RX1_BITS   _u(0x0000f000)
+#define PIO_FLEVEL_RX1_MSB    _u(15)
+#define PIO_FLEVEL_RX1_LSB    _u(12)
+#define PIO_FLEVEL_RX1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_FLEVEL_TX1
+// Description : None
+#define PIO_FLEVEL_TX1_RESET  _u(0x0)
+#define PIO_FLEVEL_TX1_BITS   _u(0x00000f00)
+#define PIO_FLEVEL_TX1_MSB    _u(11)
+#define PIO_FLEVEL_TX1_LSB    _u(8)
+#define PIO_FLEVEL_TX1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_FLEVEL_RX0
+// Description : None
+#define PIO_FLEVEL_RX0_RESET  _u(0x0)
+#define PIO_FLEVEL_RX0_BITS   _u(0x000000f0)
+#define PIO_FLEVEL_RX0_MSB    _u(7)
+#define PIO_FLEVEL_RX0_LSB    _u(4)
+#define PIO_FLEVEL_RX0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_FLEVEL_TX0
+// Description : None
+#define PIO_FLEVEL_TX0_RESET  _u(0x0)
+#define PIO_FLEVEL_TX0_BITS   _u(0x0000000f)
+#define PIO_FLEVEL_TX0_MSB    _u(3)
+#define PIO_FLEVEL_TX0_LSB    _u(0)
+#define PIO_FLEVEL_TX0_ACCESS "RO"
+// =============================================================================
+// Register    : PIO_TXF0
+// Description : Direct write access to the TX FIFO for this state machine. Each
+//               write pushes one word to the FIFO. Attempting to write to a
+//               full FIFO has no effect on the FIFO state or contents, and sets
+//               the sticky FDEBUG_TXOVER error flag for this FIFO.
+#define PIO_TXF0_OFFSET _u(0x00000010)
+#define PIO_TXF0_BITS   _u(0xffffffff)
+#define PIO_TXF0_RESET  _u(0x00000000)
+#define PIO_TXF0_MSB    _u(31)
+#define PIO_TXF0_LSB    _u(0)
+#define PIO_TXF0_ACCESS "WF"
+// =============================================================================
+// Register    : PIO_TXF1
+// Description : Direct write access to the TX FIFO for this state machine. Each
+//               write pushes one word to the FIFO. Attempting to write to a
+//               full FIFO has no effect on the FIFO state or contents, and sets
+//               the sticky FDEBUG_TXOVER error flag for this FIFO.
+#define PIO_TXF1_OFFSET _u(0x00000014)
+#define PIO_TXF1_BITS   _u(0xffffffff)
+#define PIO_TXF1_RESET  _u(0x00000000)
+#define PIO_TXF1_MSB    _u(31)
+#define PIO_TXF1_LSB    _u(0)
+#define PIO_TXF1_ACCESS "WF"
+// =============================================================================
+// Register    : PIO_TXF2
+// Description : Direct write access to the TX FIFO for this state machine. Each
+//               write pushes one word to the FIFO. Attempting to write to a
+//               full FIFO has no effect on the FIFO state or contents, and sets
+//               the sticky FDEBUG_TXOVER error flag for this FIFO.
+#define PIO_TXF2_OFFSET _u(0x00000018)
+#define PIO_TXF2_BITS   _u(0xffffffff)
+#define PIO_TXF2_RESET  _u(0x00000000)
+#define PIO_TXF2_MSB    _u(31)
+#define PIO_TXF2_LSB    _u(0)
+#define PIO_TXF2_ACCESS "WF"
+// =============================================================================
+// Register    : PIO_TXF3
+// Description : Direct write access to the TX FIFO for this state machine. Each
+//               write pushes one word to the FIFO. Attempting to write to a
+//               full FIFO has no effect on the FIFO state or contents, and sets
+//               the sticky FDEBUG_TXOVER error flag for this FIFO.
+#define PIO_TXF3_OFFSET _u(0x0000001c)
+#define PIO_TXF3_BITS   _u(0xffffffff)
+#define PIO_TXF3_RESET  _u(0x00000000)
+#define PIO_TXF3_MSB    _u(31)
+#define PIO_TXF3_LSB    _u(0)
+#define PIO_TXF3_ACCESS "WF"
+// =============================================================================
+// Register    : PIO_RXF0
+// Description : Direct read access to the RX FIFO for this state machine. Each
+//               read pops one word from the FIFO. Attempting to read from an
+//               empty FIFO has no effect on the FIFO state, and sets the sticky
+//               FDEBUG_RXUNDER error flag for this FIFO. The data returned to
+//               the system on a read from an empty FIFO is undefined.
+#define PIO_RXF0_OFFSET _u(0x00000020)
+#define PIO_RXF0_BITS   _u(0xffffffff)
+#define PIO_RXF0_RESET  "-"
+#define PIO_RXF0_MSB    _u(31)
+#define PIO_RXF0_LSB    _u(0)
+#define PIO_RXF0_ACCESS "RF"
+// =============================================================================
+// Register    : PIO_RXF1
+// Description : Direct read access to the RX FIFO for this state machine. Each
+//               read pops one word from the FIFO. Attempting to read from an
+//               empty FIFO has no effect on the FIFO state, and sets the sticky
+//               FDEBUG_RXUNDER error flag for this FIFO. The data returned to
+//               the system on a read from an empty FIFO is undefined.
+#define PIO_RXF1_OFFSET _u(0x00000024)
+#define PIO_RXF1_BITS   _u(0xffffffff)
+#define PIO_RXF1_RESET  "-"
+#define PIO_RXF1_MSB    _u(31)
+#define PIO_RXF1_LSB    _u(0)
+#define PIO_RXF1_ACCESS "RF"
+// =============================================================================
+// Register    : PIO_RXF2
+// Description : Direct read access to the RX FIFO for this state machine. Each
+//               read pops one word from the FIFO. Attempting to read from an
+//               empty FIFO has no effect on the FIFO state, and sets the sticky
+//               FDEBUG_RXUNDER error flag for this FIFO. The data returned to
+//               the system on a read from an empty FIFO is undefined.
+#define PIO_RXF2_OFFSET _u(0x00000028)
+#define PIO_RXF2_BITS   _u(0xffffffff)
+#define PIO_RXF2_RESET  "-"
+#define PIO_RXF2_MSB    _u(31)
+#define PIO_RXF2_LSB    _u(0)
+#define PIO_RXF2_ACCESS "RF"
+// =============================================================================
+// Register    : PIO_RXF3
+// Description : Direct read access to the RX FIFO for this state machine. Each
+//               read pops one word from the FIFO. Attempting to read from an
+//               empty FIFO has no effect on the FIFO state, and sets the sticky
+//               FDEBUG_RXUNDER error flag for this FIFO. The data returned to
+//               the system on a read from an empty FIFO is undefined.
+#define PIO_RXF3_OFFSET _u(0x0000002c)
+#define PIO_RXF3_BITS   _u(0xffffffff)
+#define PIO_RXF3_RESET  "-"
+#define PIO_RXF3_MSB    _u(31)
+#define PIO_RXF3_LSB    _u(0)
+#define PIO_RXF3_ACCESS "RF"
+// =============================================================================
+// Register    : PIO_IRQ
+// Description : State machine IRQ flags register. Write 1 to clear. There are 8
+//               state machine IRQ flags, which can be set, cleared, and waited
+//               on by the state machines. There's no fixed association between
+//               flags and state machines -- any state machine can use any flag.
+//
+//               Any of the 8 flags can be used for timing synchronisation
+//               between state machines, using IRQ and WAIT instructions. The
+//               lower four of these flags are also routed out to system-level
+//               interrupt requests, alongside FIFO status interrupts -- see
+//               e.g. IRQ0_INTE.
+#define PIO_IRQ_OFFSET _u(0x00000030)
+#define PIO_IRQ_BITS   _u(0x000000ff)
+#define PIO_IRQ_RESET  _u(0x00000000)
+#define PIO_IRQ_MSB    _u(7)
+#define PIO_IRQ_LSB    _u(0)
+#define PIO_IRQ_ACCESS "WC"
+// =============================================================================
+// Register    : PIO_IRQ_FORCE
+// Description : Writing a 1 to each of these bits will forcibly assert the
+//               corresponding IRQ. Note this is different to the INTF register:
+//               writing here affects PIO internal state. INTF just asserts the
+//               processor-facing IRQ signal for testing ISRs, and is not
+//               visible to the state machines.
+#define PIO_IRQ_FORCE_OFFSET _u(0x00000034)
+#define PIO_IRQ_FORCE_BITS   _u(0x000000ff)
+#define PIO_IRQ_FORCE_RESET  _u(0x00000000)
+#define PIO_IRQ_FORCE_MSB    _u(7)
+#define PIO_IRQ_FORCE_LSB    _u(0)
+#define PIO_IRQ_FORCE_ACCESS "WF"
+// =============================================================================
+// Register    : PIO_INPUT_SYNC_BYPASS
+// Description : There is a 2-flipflop synchronizer on each GPIO input, which
+//               protects PIO logic from metastabilities. This increases input
+//               delay, and for fast synchronous IO (e.g. SPI) these
+//               synchronizers may need to be bypassed. Each bit in this
+//               register corresponds to one GPIO.
+//               0 -> input is synchronized (default)
+//               1 -> synchronizer is bypassed
+//               If in doubt, leave this register as all zeroes.
+#define PIO_INPUT_SYNC_BYPASS_OFFSET _u(0x00000038)
+#define PIO_INPUT_SYNC_BYPASS_BITS   _u(0xffffffff)
+#define PIO_INPUT_SYNC_BYPASS_RESET  _u(0x00000000)
+#define PIO_INPUT_SYNC_BYPASS_MSB    _u(31)
+#define PIO_INPUT_SYNC_BYPASS_LSB    _u(0)
+#define PIO_INPUT_SYNC_BYPASS_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_DBG_PADOUT
+// Description : Read to sample the pad output values PIO is currently driving
+//               to the GPIOs. On RP2040 there are 30 GPIOs, so the two most
+//               significant bits are hardwired to 0.
+#define PIO_DBG_PADOUT_OFFSET _u(0x0000003c)
+#define PIO_DBG_PADOUT_BITS   _u(0xffffffff)
+#define PIO_DBG_PADOUT_RESET  _u(0x00000000)
+#define PIO_DBG_PADOUT_MSB    _u(31)
+#define PIO_DBG_PADOUT_LSB    _u(0)
+#define PIO_DBG_PADOUT_ACCESS "RO"
+// =============================================================================
+// Register    : PIO_DBG_PADOE
+// Description : Read to sample the pad output enables (direction) PIO is
+//               currently driving to the GPIOs. On RP2040 there are 30 GPIOs,
+//               so the two most significant bits are hardwired to 0.
+#define PIO_DBG_PADOE_OFFSET _u(0x00000040)
+#define PIO_DBG_PADOE_BITS   _u(0xffffffff)
+#define PIO_DBG_PADOE_RESET  _u(0x00000000)
+#define PIO_DBG_PADOE_MSB    _u(31)
+#define PIO_DBG_PADOE_LSB    _u(0)
+#define PIO_DBG_PADOE_ACCESS "RO"
+// =============================================================================
+// Register    : PIO_DBG_CFGINFO
+// Description : The PIO hardware has some free parameters that may vary between
+//               chip products.
+//               These should be provided in the chip datasheet, but are also
+//               exposed here.
+#define PIO_DBG_CFGINFO_OFFSET _u(0x00000044)
+#define PIO_DBG_CFGINFO_BITS   _u(0x003f0f3f)
+#define PIO_DBG_CFGINFO_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_DBG_CFGINFO_IMEM_SIZE
+// Description : The size of the instruction memory, measured in units of one
+//               instruction
+#define PIO_DBG_CFGINFO_IMEM_SIZE_RESET  "-"
+#define PIO_DBG_CFGINFO_IMEM_SIZE_BITS   _u(0x003f0000)
+#define PIO_DBG_CFGINFO_IMEM_SIZE_MSB    _u(21)
+#define PIO_DBG_CFGINFO_IMEM_SIZE_LSB    _u(16)
+#define PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_DBG_CFGINFO_SM_COUNT
+// Description : The number of state machines this PIO instance is equipped
+//               with.
+#define PIO_DBG_CFGINFO_SM_COUNT_RESET  "-"
+#define PIO_DBG_CFGINFO_SM_COUNT_BITS   _u(0x00000f00)
+#define PIO_DBG_CFGINFO_SM_COUNT_MSB    _u(11)
+#define PIO_DBG_CFGINFO_SM_COUNT_LSB    _u(8)
+#define PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_DBG_CFGINFO_FIFO_DEPTH
+// Description : The depth of the state machine TX/RX FIFOs, measured in words.
+//               Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double
+//               this depth.
+#define PIO_DBG_CFGINFO_FIFO_DEPTH_RESET  "-"
+#define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS   _u(0x0000003f)
+#define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB    _u(5)
+#define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB    _u(0)
+#define PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM0
+// Description : Write-only access to instruction memory location 0
+#define PIO_INSTR_MEM0_OFFSET _u(0x00000048)
+#define PIO_INSTR_MEM0_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM0_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM0_MSB    _u(15)
+#define PIO_INSTR_MEM0_LSB    _u(0)
+#define PIO_INSTR_MEM0_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM1
+// Description : Write-only access to instruction memory location 1
+#define PIO_INSTR_MEM1_OFFSET _u(0x0000004c)
+#define PIO_INSTR_MEM1_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM1_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM1_MSB    _u(15)
+#define PIO_INSTR_MEM1_LSB    _u(0)
+#define PIO_INSTR_MEM1_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM2
+// Description : Write-only access to instruction memory location 2
+#define PIO_INSTR_MEM2_OFFSET _u(0x00000050)
+#define PIO_INSTR_MEM2_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM2_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM2_MSB    _u(15)
+#define PIO_INSTR_MEM2_LSB    _u(0)
+#define PIO_INSTR_MEM2_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM3
+// Description : Write-only access to instruction memory location 3
+#define PIO_INSTR_MEM3_OFFSET _u(0x00000054)
+#define PIO_INSTR_MEM3_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM3_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM3_MSB    _u(15)
+#define PIO_INSTR_MEM3_LSB    _u(0)
+#define PIO_INSTR_MEM3_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM4
+// Description : Write-only access to instruction memory location 4
+#define PIO_INSTR_MEM4_OFFSET _u(0x00000058)
+#define PIO_INSTR_MEM4_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM4_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM4_MSB    _u(15)
+#define PIO_INSTR_MEM4_LSB    _u(0)
+#define PIO_INSTR_MEM4_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM5
+// Description : Write-only access to instruction memory location 5
+#define PIO_INSTR_MEM5_OFFSET _u(0x0000005c)
+#define PIO_INSTR_MEM5_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM5_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM5_MSB    _u(15)
+#define PIO_INSTR_MEM5_LSB    _u(0)
+#define PIO_INSTR_MEM5_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM6
+// Description : Write-only access to instruction memory location 6
+#define PIO_INSTR_MEM6_OFFSET _u(0x00000060)
+#define PIO_INSTR_MEM6_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM6_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM6_MSB    _u(15)
+#define PIO_INSTR_MEM6_LSB    _u(0)
+#define PIO_INSTR_MEM6_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM7
+// Description : Write-only access to instruction memory location 7
+#define PIO_INSTR_MEM7_OFFSET _u(0x00000064)
+#define PIO_INSTR_MEM7_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM7_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM7_MSB    _u(15)
+#define PIO_INSTR_MEM7_LSB    _u(0)
+#define PIO_INSTR_MEM7_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM8
+// Description : Write-only access to instruction memory location 8
+#define PIO_INSTR_MEM8_OFFSET _u(0x00000068)
+#define PIO_INSTR_MEM8_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM8_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM8_MSB    _u(15)
+#define PIO_INSTR_MEM8_LSB    _u(0)
+#define PIO_INSTR_MEM8_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM9
+// Description : Write-only access to instruction memory location 9
+#define PIO_INSTR_MEM9_OFFSET _u(0x0000006c)
+#define PIO_INSTR_MEM9_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM9_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM9_MSB    _u(15)
+#define PIO_INSTR_MEM9_LSB    _u(0)
+#define PIO_INSTR_MEM9_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM10
+// Description : Write-only access to instruction memory location 10
+#define PIO_INSTR_MEM10_OFFSET _u(0x00000070)
+#define PIO_INSTR_MEM10_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM10_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM10_MSB    _u(15)
+#define PIO_INSTR_MEM10_LSB    _u(0)
+#define PIO_INSTR_MEM10_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM11
+// Description : Write-only access to instruction memory location 11
+#define PIO_INSTR_MEM11_OFFSET _u(0x00000074)
+#define PIO_INSTR_MEM11_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM11_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM11_MSB    _u(15)
+#define PIO_INSTR_MEM11_LSB    _u(0)
+#define PIO_INSTR_MEM11_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM12
+// Description : Write-only access to instruction memory location 12
+#define PIO_INSTR_MEM12_OFFSET _u(0x00000078)
+#define PIO_INSTR_MEM12_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM12_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM12_MSB    _u(15)
+#define PIO_INSTR_MEM12_LSB    _u(0)
+#define PIO_INSTR_MEM12_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM13
+// Description : Write-only access to instruction memory location 13
+#define PIO_INSTR_MEM13_OFFSET _u(0x0000007c)
+#define PIO_INSTR_MEM13_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM13_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM13_MSB    _u(15)
+#define PIO_INSTR_MEM13_LSB    _u(0)
+#define PIO_INSTR_MEM13_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM14
+// Description : Write-only access to instruction memory location 14
+#define PIO_INSTR_MEM14_OFFSET _u(0x00000080)
+#define PIO_INSTR_MEM14_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM14_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM14_MSB    _u(15)
+#define PIO_INSTR_MEM14_LSB    _u(0)
+#define PIO_INSTR_MEM14_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM15
+// Description : Write-only access to instruction memory location 15
+#define PIO_INSTR_MEM15_OFFSET _u(0x00000084)
+#define PIO_INSTR_MEM15_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM15_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM15_MSB    _u(15)
+#define PIO_INSTR_MEM15_LSB    _u(0)
+#define PIO_INSTR_MEM15_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM16
+// Description : Write-only access to instruction memory location 16
+#define PIO_INSTR_MEM16_OFFSET _u(0x00000088)
+#define PIO_INSTR_MEM16_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM16_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM16_MSB    _u(15)
+#define PIO_INSTR_MEM16_LSB    _u(0)
+#define PIO_INSTR_MEM16_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM17
+// Description : Write-only access to instruction memory location 17
+#define PIO_INSTR_MEM17_OFFSET _u(0x0000008c)
+#define PIO_INSTR_MEM17_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM17_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM17_MSB    _u(15)
+#define PIO_INSTR_MEM17_LSB    _u(0)
+#define PIO_INSTR_MEM17_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM18
+// Description : Write-only access to instruction memory location 18
+#define PIO_INSTR_MEM18_OFFSET _u(0x00000090)
+#define PIO_INSTR_MEM18_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM18_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM18_MSB    _u(15)
+#define PIO_INSTR_MEM18_LSB    _u(0)
+#define PIO_INSTR_MEM18_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM19
+// Description : Write-only access to instruction memory location 19
+#define PIO_INSTR_MEM19_OFFSET _u(0x00000094)
+#define PIO_INSTR_MEM19_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM19_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM19_MSB    _u(15)
+#define PIO_INSTR_MEM19_LSB    _u(0)
+#define PIO_INSTR_MEM19_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM20
+// Description : Write-only access to instruction memory location 20
+#define PIO_INSTR_MEM20_OFFSET _u(0x00000098)
+#define PIO_INSTR_MEM20_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM20_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM20_MSB    _u(15)
+#define PIO_INSTR_MEM20_LSB    _u(0)
+#define PIO_INSTR_MEM20_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM21
+// Description : Write-only access to instruction memory location 21
+#define PIO_INSTR_MEM21_OFFSET _u(0x0000009c)
+#define PIO_INSTR_MEM21_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM21_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM21_MSB    _u(15)
+#define PIO_INSTR_MEM21_LSB    _u(0)
+#define PIO_INSTR_MEM21_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM22
+// Description : Write-only access to instruction memory location 22
+#define PIO_INSTR_MEM22_OFFSET _u(0x000000a0)
+#define PIO_INSTR_MEM22_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM22_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM22_MSB    _u(15)
+#define PIO_INSTR_MEM22_LSB    _u(0)
+#define PIO_INSTR_MEM22_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM23
+// Description : Write-only access to instruction memory location 23
+#define PIO_INSTR_MEM23_OFFSET _u(0x000000a4)
+#define PIO_INSTR_MEM23_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM23_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM23_MSB    _u(15)
+#define PIO_INSTR_MEM23_LSB    _u(0)
+#define PIO_INSTR_MEM23_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM24
+// Description : Write-only access to instruction memory location 24
+#define PIO_INSTR_MEM24_OFFSET _u(0x000000a8)
+#define PIO_INSTR_MEM24_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM24_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM24_MSB    _u(15)
+#define PIO_INSTR_MEM24_LSB    _u(0)
+#define PIO_INSTR_MEM24_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM25
+// Description : Write-only access to instruction memory location 25
+#define PIO_INSTR_MEM25_OFFSET _u(0x000000ac)
+#define PIO_INSTR_MEM25_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM25_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM25_MSB    _u(15)
+#define PIO_INSTR_MEM25_LSB    _u(0)
+#define PIO_INSTR_MEM25_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM26
+// Description : Write-only access to instruction memory location 26
+#define PIO_INSTR_MEM26_OFFSET _u(0x000000b0)
+#define PIO_INSTR_MEM26_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM26_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM26_MSB    _u(15)
+#define PIO_INSTR_MEM26_LSB    _u(0)
+#define PIO_INSTR_MEM26_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM27
+// Description : Write-only access to instruction memory location 27
+#define PIO_INSTR_MEM27_OFFSET _u(0x000000b4)
+#define PIO_INSTR_MEM27_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM27_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM27_MSB    _u(15)
+#define PIO_INSTR_MEM27_LSB    _u(0)
+#define PIO_INSTR_MEM27_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM28
+// Description : Write-only access to instruction memory location 28
+#define PIO_INSTR_MEM28_OFFSET _u(0x000000b8)
+#define PIO_INSTR_MEM28_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM28_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM28_MSB    _u(15)
+#define PIO_INSTR_MEM28_LSB    _u(0)
+#define PIO_INSTR_MEM28_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM29
+// Description : Write-only access to instruction memory location 29
+#define PIO_INSTR_MEM29_OFFSET _u(0x000000bc)
+#define PIO_INSTR_MEM29_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM29_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM29_MSB    _u(15)
+#define PIO_INSTR_MEM29_LSB    _u(0)
+#define PIO_INSTR_MEM29_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM30
+// Description : Write-only access to instruction memory location 30
+#define PIO_INSTR_MEM30_OFFSET _u(0x000000c0)
+#define PIO_INSTR_MEM30_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM30_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM30_MSB    _u(15)
+#define PIO_INSTR_MEM30_LSB    _u(0)
+#define PIO_INSTR_MEM30_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_INSTR_MEM31
+// Description : Write-only access to instruction memory location 31
+#define PIO_INSTR_MEM31_OFFSET _u(0x000000c4)
+#define PIO_INSTR_MEM31_BITS   _u(0x0000ffff)
+#define PIO_INSTR_MEM31_RESET  _u(0x00000000)
+#define PIO_INSTR_MEM31_MSB    _u(15)
+#define PIO_INSTR_MEM31_LSB    _u(0)
+#define PIO_INSTR_MEM31_ACCESS "WO"
+// =============================================================================
+// Register    : PIO_SM0_CLKDIV
+// Description : Clock divisor register for state machine 0
+//               Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
+#define PIO_SM0_CLKDIV_OFFSET _u(0x000000c8)
+#define PIO_SM0_CLKDIV_BITS   _u(0xffffff00)
+#define PIO_SM0_CLKDIV_RESET  _u(0x00010000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_CLKDIV_INT
+// Description : Effective frequency is sysclk/(int + frac/256).
+//               Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
+//               be 0.
+#define PIO_SM0_CLKDIV_INT_RESET  _u(0x0001)
+#define PIO_SM0_CLKDIV_INT_BITS   _u(0xffff0000)
+#define PIO_SM0_CLKDIV_INT_MSB    _u(31)
+#define PIO_SM0_CLKDIV_INT_LSB    _u(16)
+#define PIO_SM0_CLKDIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_CLKDIV_FRAC
+// Description : Fractional part of clock divisor
+#define PIO_SM0_CLKDIV_FRAC_RESET  _u(0x00)
+#define PIO_SM0_CLKDIV_FRAC_BITS   _u(0x0000ff00)
+#define PIO_SM0_CLKDIV_FRAC_MSB    _u(15)
+#define PIO_SM0_CLKDIV_FRAC_LSB    _u(8)
+#define PIO_SM0_CLKDIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM0_EXECCTRL
+// Description : Execution/behavioural settings for state machine 0
+#define PIO_SM0_EXECCTRL_OFFSET _u(0x000000cc)
+#define PIO_SM0_EXECCTRL_BITS   _u(0xffffff9f)
+#define PIO_SM0_EXECCTRL_RESET  _u(0x0001f000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_EXECCTRL_EXEC_STALLED
+// Description : If 1, an instruction written to SMx_INSTR is stalled, and
+//               latched by the state machine. Will clear to 0 once this
+//               instruction completes.
+#define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET  _u(0x0)
+#define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS   _u(0x80000000)
+#define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB    _u(31)
+#define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB    _u(31)
+#define PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_EXECCTRL_SIDE_EN
+// Description : If 1, the MSB of the Delay/Side-set instruction field is used
+//               as side-set enable, rather than a side-set data bit. This
+//               allows instructions to perform side-set optionally, rather than
+//               on every instruction, but the maximum possible side-set width
+//               is reduced from 5 to 4. Note that the value of
+//               PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
+#define PIO_SM0_EXECCTRL_SIDE_EN_RESET  _u(0x0)
+#define PIO_SM0_EXECCTRL_SIDE_EN_BITS   _u(0x40000000)
+#define PIO_SM0_EXECCTRL_SIDE_EN_MSB    _u(30)
+#define PIO_SM0_EXECCTRL_SIDE_EN_LSB    _u(30)
+#define PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_EXECCTRL_SIDE_PINDIR
+// Description : If 1, side-set data is asserted to pin directions, instead of
+//               pin values
+#define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET  _u(0x0)
+#define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS   _u(0x20000000)
+#define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB    _u(29)
+#define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB    _u(29)
+#define PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_EXECCTRL_JMP_PIN
+// Description : The GPIO number to use as condition for JMP PIN. Unaffected by
+//               input mapping.
+#define PIO_SM0_EXECCTRL_JMP_PIN_RESET  _u(0x00)
+#define PIO_SM0_EXECCTRL_JMP_PIN_BITS   _u(0x1f000000)
+#define PIO_SM0_EXECCTRL_JMP_PIN_MSB    _u(28)
+#define PIO_SM0_EXECCTRL_JMP_PIN_LSB    _u(24)
+#define PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_EXECCTRL_OUT_EN_SEL
+// Description : Which data bit to use for inline OUT enable
+#define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET  _u(0x00)
+#define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS   _u(0x00f80000)
+#define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB    _u(23)
+#define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB    _u(19)
+#define PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_EXECCTRL_INLINE_OUT_EN
+// Description : If 1, use a bit of OUT data as an auxiliary write enable
+//               When used in conjunction with OUT_STICKY, writes with an enable
+//               of 0 will
+//               deassert the latest pin write. This can create useful
+//               masking/override behaviour
+//               due to the priority ordering of state machine pin writes (SM0 <
+//               SM1 < ...)
+#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET  _u(0x0)
+#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS   _u(0x00040000)
+#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB    _u(18)
+#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB    _u(18)
+#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_EXECCTRL_OUT_STICKY
+// Description : Continuously assert the most recent OUT/SET to the pins
+#define PIO_SM0_EXECCTRL_OUT_STICKY_RESET  _u(0x0)
+#define PIO_SM0_EXECCTRL_OUT_STICKY_BITS   _u(0x00020000)
+#define PIO_SM0_EXECCTRL_OUT_STICKY_MSB    _u(17)
+#define PIO_SM0_EXECCTRL_OUT_STICKY_LSB    _u(17)
+#define PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_EXECCTRL_WRAP_TOP
+// Description : After reaching this address, execution is wrapped to
+//               wrap_bottom.
+//               If the instruction is a jump, and the jump condition is true,
+//               the jump takes priority.
+#define PIO_SM0_EXECCTRL_WRAP_TOP_RESET  _u(0x1f)
+#define PIO_SM0_EXECCTRL_WRAP_TOP_BITS   _u(0x0001f000)
+#define PIO_SM0_EXECCTRL_WRAP_TOP_MSB    _u(16)
+#define PIO_SM0_EXECCTRL_WRAP_TOP_LSB    _u(12)
+#define PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_EXECCTRL_WRAP_BOTTOM
+// Description : After reaching wrap_top, execution is wrapped to this address.
+#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET  _u(0x00)
+#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS   _u(0x00000f80)
+#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB    _u(11)
+#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB    _u(7)
+#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_EXECCTRL_STATUS_SEL
+// Description : Comparison used for the MOV x, STATUS instruction.
+//               0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
+//               0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
+#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET         _u(0x0)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS          _u(0x00000010)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB           _u(4)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB           _u(4)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS        "RW"
+#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_EXECCTRL_STATUS_N
+// Description : Comparison level for the MOV x, STATUS instruction
+#define PIO_SM0_EXECCTRL_STATUS_N_RESET  _u(0x0)
+#define PIO_SM0_EXECCTRL_STATUS_N_BITS   _u(0x0000000f)
+#define PIO_SM0_EXECCTRL_STATUS_N_MSB    _u(3)
+#define PIO_SM0_EXECCTRL_STATUS_N_LSB    _u(0)
+#define PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM0_SHIFTCTRL
+// Description : Control behaviour of the input/output shift registers for state
+//               machine 0
+#define PIO_SM0_SHIFTCTRL_OFFSET _u(0x000000d0)
+#define PIO_SM0_SHIFTCTRL_BITS   _u(0xffff0000)
+#define PIO_SM0_SHIFTCTRL_RESET  _u(0x000c0000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_SHIFTCTRL_FJOIN_RX
+// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
+//               as deep.
+//               TX FIFO is disabled as a result (always reads as both full and
+//               empty).
+//               FIFOs are flushed when this bit is changed.
+#define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET  _u(0x0)
+#define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS   _u(0x80000000)
+#define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB    _u(31)
+#define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB    _u(31)
+#define PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_SHIFTCTRL_FJOIN_TX
+// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice
+//               as deep.
+//               RX FIFO is disabled as a result (always reads as both full and
+//               empty).
+//               FIFOs are flushed when this bit is changed.
+#define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET  _u(0x0)
+#define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS   _u(0x40000000)
+#define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB    _u(30)
+#define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB    _u(30)
+#define PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_SHIFTCTRL_PULL_THRESH
+// Description : Number of bits shifted out of OSR before autopull, or
+//               conditional pull (PULL IFEMPTY), will take place.
+//               Write 0 for value of 32.
+#define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET  _u(0x00)
+#define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS   _u(0x3e000000)
+#define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB    _u(29)
+#define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB    _u(25)
+#define PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_SHIFTCTRL_PUSH_THRESH
+// Description : Number of bits shifted into ISR before autopush, or conditional
+//               push (PUSH IFFULL), will take place.
+//               Write 0 for value of 32.
+#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET  _u(0x00)
+#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS   _u(0x01f00000)
+#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB    _u(24)
+#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB    _u(20)
+#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR
+// Description : 1 = shift out of output shift register to right. 0 = to left.
+#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET  _u(0x1)
+#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS   _u(0x00080000)
+#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB    _u(19)
+#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB    _u(19)
+#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_SHIFTCTRL_IN_SHIFTDIR
+// Description : 1 = shift input shift register to right (data enters from
+//               left). 0 = to left.
+#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET  _u(0x1)
+#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS   _u(0x00040000)
+#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB    _u(18)
+#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB    _u(18)
+#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_SHIFTCTRL_AUTOPULL
+// Description : Pull automatically when the output shift register is emptied,
+//               i.e. on or following an OUT instruction which causes the output
+//               shift counter to reach or exceed PULL_THRESH.
+#define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET  _u(0x0)
+#define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS   _u(0x00020000)
+#define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB    _u(17)
+#define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB    _u(17)
+#define PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_SHIFTCTRL_AUTOPUSH
+// Description : Push automatically when the input shift register is filled,
+//               i.e. on an IN instruction which causes the input shift counter
+//               to reach or exceed PUSH_THRESH.
+#define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET  _u(0x0)
+#define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS   _u(0x00010000)
+#define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB    _u(16)
+#define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB    _u(16)
+#define PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM0_ADDR
+// Description : Current instruction address of state machine 0
+#define PIO_SM0_ADDR_OFFSET _u(0x000000d4)
+#define PIO_SM0_ADDR_BITS   _u(0x0000001f)
+#define PIO_SM0_ADDR_RESET  _u(0x00000000)
+#define PIO_SM0_ADDR_MSB    _u(4)
+#define PIO_SM0_ADDR_LSB    _u(0)
+#define PIO_SM0_ADDR_ACCESS "RO"
+// =============================================================================
+// Register    : PIO_SM0_INSTR
+// Description : Read to see the instruction currently addressed by state
+//               machine 0's program counter
+//               Write to execute an instruction immediately (including jumps)
+//               and then resume execution.
+#define PIO_SM0_INSTR_OFFSET _u(0x000000d8)
+#define PIO_SM0_INSTR_BITS   _u(0x0000ffff)
+#define PIO_SM0_INSTR_RESET  "-"
+#define PIO_SM0_INSTR_MSB    _u(15)
+#define PIO_SM0_INSTR_LSB    _u(0)
+#define PIO_SM0_INSTR_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM0_PINCTRL
+// Description : State machine pin control
+#define PIO_SM0_PINCTRL_OFFSET _u(0x000000dc)
+#define PIO_SM0_PINCTRL_BITS   _u(0xffffffff)
+#define PIO_SM0_PINCTRL_RESET  _u(0x14000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_PINCTRL_SIDESET_COUNT
+// Description : The number of MSBs of the Delay/Side-set instruction field
+//               which are used for side-set. Inclusive of the enable bit, if
+//               present. Minimum of 0 (all delay bits, no side-set) and maximum
+//               of 5 (all side-set, no delay).
+#define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET  _u(0x0)
+#define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS   _u(0xe0000000)
+#define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB    _u(31)
+#define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB    _u(29)
+#define PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_PINCTRL_SET_COUNT
+// Description : The number of pins asserted by a SET. In the range 0 to 5
+//               inclusive.
+#define PIO_SM0_PINCTRL_SET_COUNT_RESET  _u(0x5)
+#define PIO_SM0_PINCTRL_SET_COUNT_BITS   _u(0x1c000000)
+#define PIO_SM0_PINCTRL_SET_COUNT_MSB    _u(28)
+#define PIO_SM0_PINCTRL_SET_COUNT_LSB    _u(26)
+#define PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_PINCTRL_OUT_COUNT
+// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
+//               PINS instruction. In the range 0 to 32 inclusive.
+#define PIO_SM0_PINCTRL_OUT_COUNT_RESET  _u(0x00)
+#define PIO_SM0_PINCTRL_OUT_COUNT_BITS   _u(0x03f00000)
+#define PIO_SM0_PINCTRL_OUT_COUNT_MSB    _u(25)
+#define PIO_SM0_PINCTRL_OUT_COUNT_LSB    _u(20)
+#define PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_PINCTRL_IN_BASE
+// Description : The pin which is mapped to the least-significant bit of a state
+//               machine's IN data bus. Higher-numbered pins are mapped to
+//               consecutively more-significant data bits, with a modulo of 32
+//               applied to pin number.
+#define PIO_SM0_PINCTRL_IN_BASE_RESET  _u(0x00)
+#define PIO_SM0_PINCTRL_IN_BASE_BITS   _u(0x000f8000)
+#define PIO_SM0_PINCTRL_IN_BASE_MSB    _u(19)
+#define PIO_SM0_PINCTRL_IN_BASE_LSB    _u(15)
+#define PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_PINCTRL_SIDESET_BASE
+// Description : The lowest-numbered pin that will be affected by a side-set
+//               operation. The MSBs of an instruction's side-set/delay field
+//               (up to 5, determined by SIDESET_COUNT) are used for side-set
+//               data, with the remaining LSBs used for delay. The
+//               least-significant bit of the side-set portion is the bit
+//               written to this pin, with more-significant bits written to
+//               higher-numbered pins.
+#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET  _u(0x00)
+#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS   _u(0x00007c00)
+#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB    _u(14)
+#define PIO_SM0_PINCTRL_SIDESET_BASE_LSB    _u(10)
+#define PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_PINCTRL_SET_BASE
+// Description : The lowest-numbered pin that will be affected by a SET PINS or
+//               SET PINDIRS instruction. The data written to this pin is the
+//               least-significant bit of the SET data.
+#define PIO_SM0_PINCTRL_SET_BASE_RESET  _u(0x00)
+#define PIO_SM0_PINCTRL_SET_BASE_BITS   _u(0x000003e0)
+#define PIO_SM0_PINCTRL_SET_BASE_MSB    _u(9)
+#define PIO_SM0_PINCTRL_SET_BASE_LSB    _u(5)
+#define PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM0_PINCTRL_OUT_BASE
+// Description : The lowest-numbered pin that will be affected by an OUT PINS,
+//               OUT PINDIRS or MOV PINS instruction. The data written to this
+//               pin will always be the least-significant bit of the OUT or MOV
+//               data.
+#define PIO_SM0_PINCTRL_OUT_BASE_RESET  _u(0x00)
+#define PIO_SM0_PINCTRL_OUT_BASE_BITS   _u(0x0000001f)
+#define PIO_SM0_PINCTRL_OUT_BASE_MSB    _u(4)
+#define PIO_SM0_PINCTRL_OUT_BASE_LSB    _u(0)
+#define PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM1_CLKDIV
+// Description : Clock divisor register for state machine 1
+//               Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
+#define PIO_SM1_CLKDIV_OFFSET _u(0x000000e0)
+#define PIO_SM1_CLKDIV_BITS   _u(0xffffff00)
+#define PIO_SM1_CLKDIV_RESET  _u(0x00010000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_CLKDIV_INT
+// Description : Effective frequency is sysclk/(int + frac/256).
+//               Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
+//               be 0.
+#define PIO_SM1_CLKDIV_INT_RESET  _u(0x0001)
+#define PIO_SM1_CLKDIV_INT_BITS   _u(0xffff0000)
+#define PIO_SM1_CLKDIV_INT_MSB    _u(31)
+#define PIO_SM1_CLKDIV_INT_LSB    _u(16)
+#define PIO_SM1_CLKDIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_CLKDIV_FRAC
+// Description : Fractional part of clock divisor
+#define PIO_SM1_CLKDIV_FRAC_RESET  _u(0x00)
+#define PIO_SM1_CLKDIV_FRAC_BITS   _u(0x0000ff00)
+#define PIO_SM1_CLKDIV_FRAC_MSB    _u(15)
+#define PIO_SM1_CLKDIV_FRAC_LSB    _u(8)
+#define PIO_SM1_CLKDIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM1_EXECCTRL
+// Description : Execution/behavioural settings for state machine 1
+#define PIO_SM1_EXECCTRL_OFFSET _u(0x000000e4)
+#define PIO_SM1_EXECCTRL_BITS   _u(0xffffff9f)
+#define PIO_SM1_EXECCTRL_RESET  _u(0x0001f000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_EXECCTRL_EXEC_STALLED
+// Description : If 1, an instruction written to SMx_INSTR is stalled, and
+//               latched by the state machine. Will clear to 0 once this
+//               instruction completes.
+#define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET  _u(0x0)
+#define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS   _u(0x80000000)
+#define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB    _u(31)
+#define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB    _u(31)
+#define PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_EXECCTRL_SIDE_EN
+// Description : If 1, the MSB of the Delay/Side-set instruction field is used
+//               as side-set enable, rather than a side-set data bit. This
+//               allows instructions to perform side-set optionally, rather than
+//               on every instruction, but the maximum possible side-set width
+//               is reduced from 5 to 4. Note that the value of
+//               PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
+#define PIO_SM1_EXECCTRL_SIDE_EN_RESET  _u(0x0)
+#define PIO_SM1_EXECCTRL_SIDE_EN_BITS   _u(0x40000000)
+#define PIO_SM1_EXECCTRL_SIDE_EN_MSB    _u(30)
+#define PIO_SM1_EXECCTRL_SIDE_EN_LSB    _u(30)
+#define PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_EXECCTRL_SIDE_PINDIR
+// Description : If 1, side-set data is asserted to pin directions, instead of
+//               pin values
+#define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET  _u(0x0)
+#define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS   _u(0x20000000)
+#define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB    _u(29)
+#define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB    _u(29)
+#define PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_EXECCTRL_JMP_PIN
+// Description : The GPIO number to use as condition for JMP PIN. Unaffected by
+//               input mapping.
+#define PIO_SM1_EXECCTRL_JMP_PIN_RESET  _u(0x00)
+#define PIO_SM1_EXECCTRL_JMP_PIN_BITS   _u(0x1f000000)
+#define PIO_SM1_EXECCTRL_JMP_PIN_MSB    _u(28)
+#define PIO_SM1_EXECCTRL_JMP_PIN_LSB    _u(24)
+#define PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_EXECCTRL_OUT_EN_SEL
+// Description : Which data bit to use for inline OUT enable
+#define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET  _u(0x00)
+#define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS   _u(0x00f80000)
+#define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB    _u(23)
+#define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB    _u(19)
+#define PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_EXECCTRL_INLINE_OUT_EN
+// Description : If 1, use a bit of OUT data as an auxiliary write enable
+//               When used in conjunction with OUT_STICKY, writes with an enable
+//               of 0 will
+//               deassert the latest pin write. This can create useful
+//               masking/override behaviour
+//               due to the priority ordering of state machine pin writes (SM0 <
+//               SM1 < ...)
+#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET  _u(0x0)
+#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS   _u(0x00040000)
+#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB    _u(18)
+#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB    _u(18)
+#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_EXECCTRL_OUT_STICKY
+// Description : Continuously assert the most recent OUT/SET to the pins
+#define PIO_SM1_EXECCTRL_OUT_STICKY_RESET  _u(0x0)
+#define PIO_SM1_EXECCTRL_OUT_STICKY_BITS   _u(0x00020000)
+#define PIO_SM1_EXECCTRL_OUT_STICKY_MSB    _u(17)
+#define PIO_SM1_EXECCTRL_OUT_STICKY_LSB    _u(17)
+#define PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_EXECCTRL_WRAP_TOP
+// Description : After reaching this address, execution is wrapped to
+//               wrap_bottom.
+//               If the instruction is a jump, and the jump condition is true,
+//               the jump takes priority.
+#define PIO_SM1_EXECCTRL_WRAP_TOP_RESET  _u(0x1f)
+#define PIO_SM1_EXECCTRL_WRAP_TOP_BITS   _u(0x0001f000)
+#define PIO_SM1_EXECCTRL_WRAP_TOP_MSB    _u(16)
+#define PIO_SM1_EXECCTRL_WRAP_TOP_LSB    _u(12)
+#define PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_EXECCTRL_WRAP_BOTTOM
+// Description : After reaching wrap_top, execution is wrapped to this address.
+#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET  _u(0x00)
+#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS   _u(0x00000f80)
+#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB    _u(11)
+#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB    _u(7)
+#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_EXECCTRL_STATUS_SEL
+// Description : Comparison used for the MOV x, STATUS instruction.
+//               0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
+//               0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
+#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET         _u(0x0)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS          _u(0x00000010)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB           _u(4)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB           _u(4)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS        "RW"
+#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_EXECCTRL_STATUS_N
+// Description : Comparison level for the MOV x, STATUS instruction
+#define PIO_SM1_EXECCTRL_STATUS_N_RESET  _u(0x0)
+#define PIO_SM1_EXECCTRL_STATUS_N_BITS   _u(0x0000000f)
+#define PIO_SM1_EXECCTRL_STATUS_N_MSB    _u(3)
+#define PIO_SM1_EXECCTRL_STATUS_N_LSB    _u(0)
+#define PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM1_SHIFTCTRL
+// Description : Control behaviour of the input/output shift registers for state
+//               machine 1
+#define PIO_SM1_SHIFTCTRL_OFFSET _u(0x000000e8)
+#define PIO_SM1_SHIFTCTRL_BITS   _u(0xffff0000)
+#define PIO_SM1_SHIFTCTRL_RESET  _u(0x000c0000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_SHIFTCTRL_FJOIN_RX
+// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
+//               as deep.
+//               TX FIFO is disabled as a result (always reads as both full and
+//               empty).
+//               FIFOs are flushed when this bit is changed.
+#define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET  _u(0x0)
+#define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS   _u(0x80000000)
+#define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB    _u(31)
+#define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB    _u(31)
+#define PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_SHIFTCTRL_FJOIN_TX
+// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice
+//               as deep.
+//               RX FIFO is disabled as a result (always reads as both full and
+//               empty).
+//               FIFOs are flushed when this bit is changed.
+#define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET  _u(0x0)
+#define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS   _u(0x40000000)
+#define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB    _u(30)
+#define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB    _u(30)
+#define PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_SHIFTCTRL_PULL_THRESH
+// Description : Number of bits shifted out of OSR before autopull, or
+//               conditional pull (PULL IFEMPTY), will take place.
+//               Write 0 for value of 32.
+#define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET  _u(0x00)
+#define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS   _u(0x3e000000)
+#define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB    _u(29)
+#define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB    _u(25)
+#define PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_SHIFTCTRL_PUSH_THRESH
+// Description : Number of bits shifted into ISR before autopush, or conditional
+//               push (PUSH IFFULL), will take place.
+//               Write 0 for value of 32.
+#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET  _u(0x00)
+#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS   _u(0x01f00000)
+#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB    _u(24)
+#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB    _u(20)
+#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR
+// Description : 1 = shift out of output shift register to right. 0 = to left.
+#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET  _u(0x1)
+#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS   _u(0x00080000)
+#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB    _u(19)
+#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB    _u(19)
+#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_SHIFTCTRL_IN_SHIFTDIR
+// Description : 1 = shift input shift register to right (data enters from
+//               left). 0 = to left.
+#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET  _u(0x1)
+#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS   _u(0x00040000)
+#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB    _u(18)
+#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB    _u(18)
+#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_SHIFTCTRL_AUTOPULL
+// Description : Pull automatically when the output shift register is emptied,
+//               i.e. on or following an OUT instruction which causes the output
+//               shift counter to reach or exceed PULL_THRESH.
+#define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET  _u(0x0)
+#define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS   _u(0x00020000)
+#define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB    _u(17)
+#define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB    _u(17)
+#define PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_SHIFTCTRL_AUTOPUSH
+// Description : Push automatically when the input shift register is filled,
+//               i.e. on an IN instruction which causes the input shift counter
+//               to reach or exceed PUSH_THRESH.
+#define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET  _u(0x0)
+#define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS   _u(0x00010000)
+#define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB    _u(16)
+#define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB    _u(16)
+#define PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM1_ADDR
+// Description : Current instruction address of state machine 1
+#define PIO_SM1_ADDR_OFFSET _u(0x000000ec)
+#define PIO_SM1_ADDR_BITS   _u(0x0000001f)
+#define PIO_SM1_ADDR_RESET  _u(0x00000000)
+#define PIO_SM1_ADDR_MSB    _u(4)
+#define PIO_SM1_ADDR_LSB    _u(0)
+#define PIO_SM1_ADDR_ACCESS "RO"
+// =============================================================================
+// Register    : PIO_SM1_INSTR
+// Description : Read to see the instruction currently addressed by state
+//               machine 1's program counter
+//               Write to execute an instruction immediately (including jumps)
+//               and then resume execution.
+#define PIO_SM1_INSTR_OFFSET _u(0x000000f0)
+#define PIO_SM1_INSTR_BITS   _u(0x0000ffff)
+#define PIO_SM1_INSTR_RESET  "-"
+#define PIO_SM1_INSTR_MSB    _u(15)
+#define PIO_SM1_INSTR_LSB    _u(0)
+#define PIO_SM1_INSTR_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM1_PINCTRL
+// Description : State machine pin control
+#define PIO_SM1_PINCTRL_OFFSET _u(0x000000f4)
+#define PIO_SM1_PINCTRL_BITS   _u(0xffffffff)
+#define PIO_SM1_PINCTRL_RESET  _u(0x14000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_PINCTRL_SIDESET_COUNT
+// Description : The number of MSBs of the Delay/Side-set instruction field
+//               which are used for side-set. Inclusive of the enable bit, if
+//               present. Minimum of 0 (all delay bits, no side-set) and maximum
+//               of 5 (all side-set, no delay).
+#define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET  _u(0x0)
+#define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS   _u(0xe0000000)
+#define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB    _u(31)
+#define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB    _u(29)
+#define PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_PINCTRL_SET_COUNT
+// Description : The number of pins asserted by a SET. In the range 0 to 5
+//               inclusive.
+#define PIO_SM1_PINCTRL_SET_COUNT_RESET  _u(0x5)
+#define PIO_SM1_PINCTRL_SET_COUNT_BITS   _u(0x1c000000)
+#define PIO_SM1_PINCTRL_SET_COUNT_MSB    _u(28)
+#define PIO_SM1_PINCTRL_SET_COUNT_LSB    _u(26)
+#define PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_PINCTRL_OUT_COUNT
+// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
+//               PINS instruction. In the range 0 to 32 inclusive.
+#define PIO_SM1_PINCTRL_OUT_COUNT_RESET  _u(0x00)
+#define PIO_SM1_PINCTRL_OUT_COUNT_BITS   _u(0x03f00000)
+#define PIO_SM1_PINCTRL_OUT_COUNT_MSB    _u(25)
+#define PIO_SM1_PINCTRL_OUT_COUNT_LSB    _u(20)
+#define PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_PINCTRL_IN_BASE
+// Description : The pin which is mapped to the least-significant bit of a state
+//               machine's IN data bus. Higher-numbered pins are mapped to
+//               consecutively more-significant data bits, with a modulo of 32
+//               applied to pin number.
+#define PIO_SM1_PINCTRL_IN_BASE_RESET  _u(0x00)
+#define PIO_SM1_PINCTRL_IN_BASE_BITS   _u(0x000f8000)
+#define PIO_SM1_PINCTRL_IN_BASE_MSB    _u(19)
+#define PIO_SM1_PINCTRL_IN_BASE_LSB    _u(15)
+#define PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_PINCTRL_SIDESET_BASE
+// Description : The lowest-numbered pin that will be affected by a side-set
+//               operation. The MSBs of an instruction's side-set/delay field
+//               (up to 5, determined by SIDESET_COUNT) are used for side-set
+//               data, with the remaining LSBs used for delay. The
+//               least-significant bit of the side-set portion is the bit
+//               written to this pin, with more-significant bits written to
+//               higher-numbered pins.
+#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET  _u(0x00)
+#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS   _u(0x00007c00)
+#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB    _u(14)
+#define PIO_SM1_PINCTRL_SIDESET_BASE_LSB    _u(10)
+#define PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_PINCTRL_SET_BASE
+// Description : The lowest-numbered pin that will be affected by a SET PINS or
+//               SET PINDIRS instruction. The data written to this pin is the
+//               least-significant bit of the SET data.
+#define PIO_SM1_PINCTRL_SET_BASE_RESET  _u(0x00)
+#define PIO_SM1_PINCTRL_SET_BASE_BITS   _u(0x000003e0)
+#define PIO_SM1_PINCTRL_SET_BASE_MSB    _u(9)
+#define PIO_SM1_PINCTRL_SET_BASE_LSB    _u(5)
+#define PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM1_PINCTRL_OUT_BASE
+// Description : The lowest-numbered pin that will be affected by an OUT PINS,
+//               OUT PINDIRS or MOV PINS instruction. The data written to this
+//               pin will always be the least-significant bit of the OUT or MOV
+//               data.
+#define PIO_SM1_PINCTRL_OUT_BASE_RESET  _u(0x00)
+#define PIO_SM1_PINCTRL_OUT_BASE_BITS   _u(0x0000001f)
+#define PIO_SM1_PINCTRL_OUT_BASE_MSB    _u(4)
+#define PIO_SM1_PINCTRL_OUT_BASE_LSB    _u(0)
+#define PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM2_CLKDIV
+// Description : Clock divisor register for state machine 2
+//               Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
+#define PIO_SM2_CLKDIV_OFFSET _u(0x000000f8)
+#define PIO_SM2_CLKDIV_BITS   _u(0xffffff00)
+#define PIO_SM2_CLKDIV_RESET  _u(0x00010000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_CLKDIV_INT
+// Description : Effective frequency is sysclk/(int + frac/256).
+//               Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
+//               be 0.
+#define PIO_SM2_CLKDIV_INT_RESET  _u(0x0001)
+#define PIO_SM2_CLKDIV_INT_BITS   _u(0xffff0000)
+#define PIO_SM2_CLKDIV_INT_MSB    _u(31)
+#define PIO_SM2_CLKDIV_INT_LSB    _u(16)
+#define PIO_SM2_CLKDIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_CLKDIV_FRAC
+// Description : Fractional part of clock divisor
+#define PIO_SM2_CLKDIV_FRAC_RESET  _u(0x00)
+#define PIO_SM2_CLKDIV_FRAC_BITS   _u(0x0000ff00)
+#define PIO_SM2_CLKDIV_FRAC_MSB    _u(15)
+#define PIO_SM2_CLKDIV_FRAC_LSB    _u(8)
+#define PIO_SM2_CLKDIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM2_EXECCTRL
+// Description : Execution/behavioural settings for state machine 2
+#define PIO_SM2_EXECCTRL_OFFSET _u(0x000000fc)
+#define PIO_SM2_EXECCTRL_BITS   _u(0xffffff9f)
+#define PIO_SM2_EXECCTRL_RESET  _u(0x0001f000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_EXECCTRL_EXEC_STALLED
+// Description : If 1, an instruction written to SMx_INSTR is stalled, and
+//               latched by the state machine. Will clear to 0 once this
+//               instruction completes.
+#define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET  _u(0x0)
+#define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS   _u(0x80000000)
+#define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB    _u(31)
+#define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB    _u(31)
+#define PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_EXECCTRL_SIDE_EN
+// Description : If 1, the MSB of the Delay/Side-set instruction field is used
+//               as side-set enable, rather than a side-set data bit. This
+//               allows instructions to perform side-set optionally, rather than
+//               on every instruction, but the maximum possible side-set width
+//               is reduced from 5 to 4. Note that the value of
+//               PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
+#define PIO_SM2_EXECCTRL_SIDE_EN_RESET  _u(0x0)
+#define PIO_SM2_EXECCTRL_SIDE_EN_BITS   _u(0x40000000)
+#define PIO_SM2_EXECCTRL_SIDE_EN_MSB    _u(30)
+#define PIO_SM2_EXECCTRL_SIDE_EN_LSB    _u(30)
+#define PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_EXECCTRL_SIDE_PINDIR
+// Description : If 1, side-set data is asserted to pin directions, instead of
+//               pin values
+#define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET  _u(0x0)
+#define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS   _u(0x20000000)
+#define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB    _u(29)
+#define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB    _u(29)
+#define PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_EXECCTRL_JMP_PIN
+// Description : The GPIO number to use as condition for JMP PIN. Unaffected by
+//               input mapping.
+#define PIO_SM2_EXECCTRL_JMP_PIN_RESET  _u(0x00)
+#define PIO_SM2_EXECCTRL_JMP_PIN_BITS   _u(0x1f000000)
+#define PIO_SM2_EXECCTRL_JMP_PIN_MSB    _u(28)
+#define PIO_SM2_EXECCTRL_JMP_PIN_LSB    _u(24)
+#define PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_EXECCTRL_OUT_EN_SEL
+// Description : Which data bit to use for inline OUT enable
+#define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET  _u(0x00)
+#define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS   _u(0x00f80000)
+#define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB    _u(23)
+#define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB    _u(19)
+#define PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_EXECCTRL_INLINE_OUT_EN
+// Description : If 1, use a bit of OUT data as an auxiliary write enable
+//               When used in conjunction with OUT_STICKY, writes with an enable
+//               of 0 will
+//               deassert the latest pin write. This can create useful
+//               masking/override behaviour
+//               due to the priority ordering of state machine pin writes (SM0 <
+//               SM1 < ...)
+#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET  _u(0x0)
+#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS   _u(0x00040000)
+#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB    _u(18)
+#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB    _u(18)
+#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_EXECCTRL_OUT_STICKY
+// Description : Continuously assert the most recent OUT/SET to the pins
+#define PIO_SM2_EXECCTRL_OUT_STICKY_RESET  _u(0x0)
+#define PIO_SM2_EXECCTRL_OUT_STICKY_BITS   _u(0x00020000)
+#define PIO_SM2_EXECCTRL_OUT_STICKY_MSB    _u(17)
+#define PIO_SM2_EXECCTRL_OUT_STICKY_LSB    _u(17)
+#define PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_EXECCTRL_WRAP_TOP
+// Description : After reaching this address, execution is wrapped to
+//               wrap_bottom.
+//               If the instruction is a jump, and the jump condition is true,
+//               the jump takes priority.
+#define PIO_SM2_EXECCTRL_WRAP_TOP_RESET  _u(0x1f)
+#define PIO_SM2_EXECCTRL_WRAP_TOP_BITS   _u(0x0001f000)
+#define PIO_SM2_EXECCTRL_WRAP_TOP_MSB    _u(16)
+#define PIO_SM2_EXECCTRL_WRAP_TOP_LSB    _u(12)
+#define PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_EXECCTRL_WRAP_BOTTOM
+// Description : After reaching wrap_top, execution is wrapped to this address.
+#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET  _u(0x00)
+#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS   _u(0x00000f80)
+#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB    _u(11)
+#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB    _u(7)
+#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_EXECCTRL_STATUS_SEL
+// Description : Comparison used for the MOV x, STATUS instruction.
+//               0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
+//               0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
+#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET         _u(0x0)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS          _u(0x00000010)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB           _u(4)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB           _u(4)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS        "RW"
+#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_EXECCTRL_STATUS_N
+// Description : Comparison level for the MOV x, STATUS instruction
+#define PIO_SM2_EXECCTRL_STATUS_N_RESET  _u(0x0)
+#define PIO_SM2_EXECCTRL_STATUS_N_BITS   _u(0x0000000f)
+#define PIO_SM2_EXECCTRL_STATUS_N_MSB    _u(3)
+#define PIO_SM2_EXECCTRL_STATUS_N_LSB    _u(0)
+#define PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM2_SHIFTCTRL
+// Description : Control behaviour of the input/output shift registers for state
+//               machine 2
+#define PIO_SM2_SHIFTCTRL_OFFSET _u(0x00000100)
+#define PIO_SM2_SHIFTCTRL_BITS   _u(0xffff0000)
+#define PIO_SM2_SHIFTCTRL_RESET  _u(0x000c0000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_SHIFTCTRL_FJOIN_RX
+// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
+//               as deep.
+//               TX FIFO is disabled as a result (always reads as both full and
+//               empty).
+//               FIFOs are flushed when this bit is changed.
+#define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET  _u(0x0)
+#define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS   _u(0x80000000)
+#define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB    _u(31)
+#define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB    _u(31)
+#define PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_SHIFTCTRL_FJOIN_TX
+// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice
+//               as deep.
+//               RX FIFO is disabled as a result (always reads as both full and
+//               empty).
+//               FIFOs are flushed when this bit is changed.
+#define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET  _u(0x0)
+#define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS   _u(0x40000000)
+#define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB    _u(30)
+#define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB    _u(30)
+#define PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_SHIFTCTRL_PULL_THRESH
+// Description : Number of bits shifted out of OSR before autopull, or
+//               conditional pull (PULL IFEMPTY), will take place.
+//               Write 0 for value of 32.
+#define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET  _u(0x00)
+#define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS   _u(0x3e000000)
+#define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB    _u(29)
+#define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB    _u(25)
+#define PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_SHIFTCTRL_PUSH_THRESH
+// Description : Number of bits shifted into ISR before autopush, or conditional
+//               push (PUSH IFFULL), will take place.
+//               Write 0 for value of 32.
+#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET  _u(0x00)
+#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS   _u(0x01f00000)
+#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB    _u(24)
+#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB    _u(20)
+#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR
+// Description : 1 = shift out of output shift register to right. 0 = to left.
+#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET  _u(0x1)
+#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS   _u(0x00080000)
+#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB    _u(19)
+#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB    _u(19)
+#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_SHIFTCTRL_IN_SHIFTDIR
+// Description : 1 = shift input shift register to right (data enters from
+//               left). 0 = to left.
+#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET  _u(0x1)
+#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS   _u(0x00040000)
+#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB    _u(18)
+#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB    _u(18)
+#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_SHIFTCTRL_AUTOPULL
+// Description : Pull automatically when the output shift register is emptied,
+//               i.e. on or following an OUT instruction which causes the output
+//               shift counter to reach or exceed PULL_THRESH.
+#define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET  _u(0x0)
+#define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS   _u(0x00020000)
+#define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB    _u(17)
+#define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB    _u(17)
+#define PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_SHIFTCTRL_AUTOPUSH
+// Description : Push automatically when the input shift register is filled,
+//               i.e. on an IN instruction which causes the input shift counter
+//               to reach or exceed PUSH_THRESH.
+#define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET  _u(0x0)
+#define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS   _u(0x00010000)
+#define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB    _u(16)
+#define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB    _u(16)
+#define PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM2_ADDR
+// Description : Current instruction address of state machine 2
+#define PIO_SM2_ADDR_OFFSET _u(0x00000104)
+#define PIO_SM2_ADDR_BITS   _u(0x0000001f)
+#define PIO_SM2_ADDR_RESET  _u(0x00000000)
+#define PIO_SM2_ADDR_MSB    _u(4)
+#define PIO_SM2_ADDR_LSB    _u(0)
+#define PIO_SM2_ADDR_ACCESS "RO"
+// =============================================================================
+// Register    : PIO_SM2_INSTR
+// Description : Read to see the instruction currently addressed by state
+//               machine 2's program counter
+//               Write to execute an instruction immediately (including jumps)
+//               and then resume execution.
+#define PIO_SM2_INSTR_OFFSET _u(0x00000108)
+#define PIO_SM2_INSTR_BITS   _u(0x0000ffff)
+#define PIO_SM2_INSTR_RESET  "-"
+#define PIO_SM2_INSTR_MSB    _u(15)
+#define PIO_SM2_INSTR_LSB    _u(0)
+#define PIO_SM2_INSTR_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM2_PINCTRL
+// Description : State machine pin control
+#define PIO_SM2_PINCTRL_OFFSET _u(0x0000010c)
+#define PIO_SM2_PINCTRL_BITS   _u(0xffffffff)
+#define PIO_SM2_PINCTRL_RESET  _u(0x14000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_PINCTRL_SIDESET_COUNT
+// Description : The number of MSBs of the Delay/Side-set instruction field
+//               which are used for side-set. Inclusive of the enable bit, if
+//               present. Minimum of 0 (all delay bits, no side-set) and maximum
+//               of 5 (all side-set, no delay).
+#define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET  _u(0x0)
+#define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS   _u(0xe0000000)
+#define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB    _u(31)
+#define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB    _u(29)
+#define PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_PINCTRL_SET_COUNT
+// Description : The number of pins asserted by a SET. In the range 0 to 5
+//               inclusive.
+#define PIO_SM2_PINCTRL_SET_COUNT_RESET  _u(0x5)
+#define PIO_SM2_PINCTRL_SET_COUNT_BITS   _u(0x1c000000)
+#define PIO_SM2_PINCTRL_SET_COUNT_MSB    _u(28)
+#define PIO_SM2_PINCTRL_SET_COUNT_LSB    _u(26)
+#define PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_PINCTRL_OUT_COUNT
+// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
+//               PINS instruction. In the range 0 to 32 inclusive.
+#define PIO_SM2_PINCTRL_OUT_COUNT_RESET  _u(0x00)
+#define PIO_SM2_PINCTRL_OUT_COUNT_BITS   _u(0x03f00000)
+#define PIO_SM2_PINCTRL_OUT_COUNT_MSB    _u(25)
+#define PIO_SM2_PINCTRL_OUT_COUNT_LSB    _u(20)
+#define PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_PINCTRL_IN_BASE
+// Description : The pin which is mapped to the least-significant bit of a state
+//               machine's IN data bus. Higher-numbered pins are mapped to
+//               consecutively more-significant data bits, with a modulo of 32
+//               applied to pin number.
+#define PIO_SM2_PINCTRL_IN_BASE_RESET  _u(0x00)
+#define PIO_SM2_PINCTRL_IN_BASE_BITS   _u(0x000f8000)
+#define PIO_SM2_PINCTRL_IN_BASE_MSB    _u(19)
+#define PIO_SM2_PINCTRL_IN_BASE_LSB    _u(15)
+#define PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_PINCTRL_SIDESET_BASE
+// Description : The lowest-numbered pin that will be affected by a side-set
+//               operation. The MSBs of an instruction's side-set/delay field
+//               (up to 5, determined by SIDESET_COUNT) are used for side-set
+//               data, with the remaining LSBs used for delay. The
+//               least-significant bit of the side-set portion is the bit
+//               written to this pin, with more-significant bits written to
+//               higher-numbered pins.
+#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET  _u(0x00)
+#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS   _u(0x00007c00)
+#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB    _u(14)
+#define PIO_SM2_PINCTRL_SIDESET_BASE_LSB    _u(10)
+#define PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_PINCTRL_SET_BASE
+// Description : The lowest-numbered pin that will be affected by a SET PINS or
+//               SET PINDIRS instruction. The data written to this pin is the
+//               least-significant bit of the SET data.
+#define PIO_SM2_PINCTRL_SET_BASE_RESET  _u(0x00)
+#define PIO_SM2_PINCTRL_SET_BASE_BITS   _u(0x000003e0)
+#define PIO_SM2_PINCTRL_SET_BASE_MSB    _u(9)
+#define PIO_SM2_PINCTRL_SET_BASE_LSB    _u(5)
+#define PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM2_PINCTRL_OUT_BASE
+// Description : The lowest-numbered pin that will be affected by an OUT PINS,
+//               OUT PINDIRS or MOV PINS instruction. The data written to this
+//               pin will always be the least-significant bit of the OUT or MOV
+//               data.
+#define PIO_SM2_PINCTRL_OUT_BASE_RESET  _u(0x00)
+#define PIO_SM2_PINCTRL_OUT_BASE_BITS   _u(0x0000001f)
+#define PIO_SM2_PINCTRL_OUT_BASE_MSB    _u(4)
+#define PIO_SM2_PINCTRL_OUT_BASE_LSB    _u(0)
+#define PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM3_CLKDIV
+// Description : Clock divisor register for state machine 3
+//               Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
+#define PIO_SM3_CLKDIV_OFFSET _u(0x00000110)
+#define PIO_SM3_CLKDIV_BITS   _u(0xffffff00)
+#define PIO_SM3_CLKDIV_RESET  _u(0x00010000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_CLKDIV_INT
+// Description : Effective frequency is sysclk/(int + frac/256).
+//               Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
+//               be 0.
+#define PIO_SM3_CLKDIV_INT_RESET  _u(0x0001)
+#define PIO_SM3_CLKDIV_INT_BITS   _u(0xffff0000)
+#define PIO_SM3_CLKDIV_INT_MSB    _u(31)
+#define PIO_SM3_CLKDIV_INT_LSB    _u(16)
+#define PIO_SM3_CLKDIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_CLKDIV_FRAC
+// Description : Fractional part of clock divisor
+#define PIO_SM3_CLKDIV_FRAC_RESET  _u(0x00)
+#define PIO_SM3_CLKDIV_FRAC_BITS   _u(0x0000ff00)
+#define PIO_SM3_CLKDIV_FRAC_MSB    _u(15)
+#define PIO_SM3_CLKDIV_FRAC_LSB    _u(8)
+#define PIO_SM3_CLKDIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM3_EXECCTRL
+// Description : Execution/behavioural settings for state machine 3
+#define PIO_SM3_EXECCTRL_OFFSET _u(0x00000114)
+#define PIO_SM3_EXECCTRL_BITS   _u(0xffffff9f)
+#define PIO_SM3_EXECCTRL_RESET  _u(0x0001f000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_EXECCTRL_EXEC_STALLED
+// Description : If 1, an instruction written to SMx_INSTR is stalled, and
+//               latched by the state machine. Will clear to 0 once this
+//               instruction completes.
+#define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET  _u(0x0)
+#define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS   _u(0x80000000)
+#define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB    _u(31)
+#define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB    _u(31)
+#define PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_EXECCTRL_SIDE_EN
+// Description : If 1, the MSB of the Delay/Side-set instruction field is used
+//               as side-set enable, rather than a side-set data bit. This
+//               allows instructions to perform side-set optionally, rather than
+//               on every instruction, but the maximum possible side-set width
+//               is reduced from 5 to 4. Note that the value of
+//               PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
+#define PIO_SM3_EXECCTRL_SIDE_EN_RESET  _u(0x0)
+#define PIO_SM3_EXECCTRL_SIDE_EN_BITS   _u(0x40000000)
+#define PIO_SM3_EXECCTRL_SIDE_EN_MSB    _u(30)
+#define PIO_SM3_EXECCTRL_SIDE_EN_LSB    _u(30)
+#define PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_EXECCTRL_SIDE_PINDIR
+// Description : If 1, side-set data is asserted to pin directions, instead of
+//               pin values
+#define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET  _u(0x0)
+#define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS   _u(0x20000000)
+#define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB    _u(29)
+#define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB    _u(29)
+#define PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_EXECCTRL_JMP_PIN
+// Description : The GPIO number to use as condition for JMP PIN. Unaffected by
+//               input mapping.
+#define PIO_SM3_EXECCTRL_JMP_PIN_RESET  _u(0x00)
+#define PIO_SM3_EXECCTRL_JMP_PIN_BITS   _u(0x1f000000)
+#define PIO_SM3_EXECCTRL_JMP_PIN_MSB    _u(28)
+#define PIO_SM3_EXECCTRL_JMP_PIN_LSB    _u(24)
+#define PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_EXECCTRL_OUT_EN_SEL
+// Description : Which data bit to use for inline OUT enable
+#define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET  _u(0x00)
+#define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS   _u(0x00f80000)
+#define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB    _u(23)
+#define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB    _u(19)
+#define PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_EXECCTRL_INLINE_OUT_EN
+// Description : If 1, use a bit of OUT data as an auxiliary write enable
+//               When used in conjunction with OUT_STICKY, writes with an enable
+//               of 0 will
+//               deassert the latest pin write. This can create useful
+//               masking/override behaviour
+//               due to the priority ordering of state machine pin writes (SM0 <
+//               SM1 < ...)
+#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET  _u(0x0)
+#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS   _u(0x00040000)
+#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB    _u(18)
+#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB    _u(18)
+#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_EXECCTRL_OUT_STICKY
+// Description : Continuously assert the most recent OUT/SET to the pins
+#define PIO_SM3_EXECCTRL_OUT_STICKY_RESET  _u(0x0)
+#define PIO_SM3_EXECCTRL_OUT_STICKY_BITS   _u(0x00020000)
+#define PIO_SM3_EXECCTRL_OUT_STICKY_MSB    _u(17)
+#define PIO_SM3_EXECCTRL_OUT_STICKY_LSB    _u(17)
+#define PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_EXECCTRL_WRAP_TOP
+// Description : After reaching this address, execution is wrapped to
+//               wrap_bottom.
+//               If the instruction is a jump, and the jump condition is true,
+//               the jump takes priority.
+#define PIO_SM3_EXECCTRL_WRAP_TOP_RESET  _u(0x1f)
+#define PIO_SM3_EXECCTRL_WRAP_TOP_BITS   _u(0x0001f000)
+#define PIO_SM3_EXECCTRL_WRAP_TOP_MSB    _u(16)
+#define PIO_SM3_EXECCTRL_WRAP_TOP_LSB    _u(12)
+#define PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_EXECCTRL_WRAP_BOTTOM
+// Description : After reaching wrap_top, execution is wrapped to this address.
+#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET  _u(0x00)
+#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS   _u(0x00000f80)
+#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB    _u(11)
+#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB    _u(7)
+#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_EXECCTRL_STATUS_SEL
+// Description : Comparison used for the MOV x, STATUS instruction.
+//               0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
+//               0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
+#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET         _u(0x0)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS          _u(0x00000010)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB           _u(4)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB           _u(4)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS        "RW"
+#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_EXECCTRL_STATUS_N
+// Description : Comparison level for the MOV x, STATUS instruction
+#define PIO_SM3_EXECCTRL_STATUS_N_RESET  _u(0x0)
+#define PIO_SM3_EXECCTRL_STATUS_N_BITS   _u(0x0000000f)
+#define PIO_SM3_EXECCTRL_STATUS_N_MSB    _u(3)
+#define PIO_SM3_EXECCTRL_STATUS_N_LSB    _u(0)
+#define PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM3_SHIFTCTRL
+// Description : Control behaviour of the input/output shift registers for state
+//               machine 3
+#define PIO_SM3_SHIFTCTRL_OFFSET _u(0x00000118)
+#define PIO_SM3_SHIFTCTRL_BITS   _u(0xffff0000)
+#define PIO_SM3_SHIFTCTRL_RESET  _u(0x000c0000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_SHIFTCTRL_FJOIN_RX
+// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
+//               as deep.
+//               TX FIFO is disabled as a result (always reads as both full and
+//               empty).
+//               FIFOs are flushed when this bit is changed.
+#define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET  _u(0x0)
+#define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS   _u(0x80000000)
+#define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB    _u(31)
+#define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB    _u(31)
+#define PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_SHIFTCTRL_FJOIN_TX
+// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice
+//               as deep.
+//               RX FIFO is disabled as a result (always reads as both full and
+//               empty).
+//               FIFOs are flushed when this bit is changed.
+#define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET  _u(0x0)
+#define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS   _u(0x40000000)
+#define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB    _u(30)
+#define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB    _u(30)
+#define PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_SHIFTCTRL_PULL_THRESH
+// Description : Number of bits shifted out of OSR before autopull, or
+//               conditional pull (PULL IFEMPTY), will take place.
+//               Write 0 for value of 32.
+#define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET  _u(0x00)
+#define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS   _u(0x3e000000)
+#define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB    _u(29)
+#define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB    _u(25)
+#define PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_SHIFTCTRL_PUSH_THRESH
+// Description : Number of bits shifted into ISR before autopush, or conditional
+//               push (PUSH IFFULL), will take place.
+//               Write 0 for value of 32.
+#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET  _u(0x00)
+#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS   _u(0x01f00000)
+#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB    _u(24)
+#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB    _u(20)
+#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR
+// Description : 1 = shift out of output shift register to right. 0 = to left.
+#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET  _u(0x1)
+#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS   _u(0x00080000)
+#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB    _u(19)
+#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB    _u(19)
+#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_SHIFTCTRL_IN_SHIFTDIR
+// Description : 1 = shift input shift register to right (data enters from
+//               left). 0 = to left.
+#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET  _u(0x1)
+#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS   _u(0x00040000)
+#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB    _u(18)
+#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB    _u(18)
+#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_SHIFTCTRL_AUTOPULL
+// Description : Pull automatically when the output shift register is emptied,
+//               i.e. on or following an OUT instruction which causes the output
+//               shift counter to reach or exceed PULL_THRESH.
+#define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET  _u(0x0)
+#define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS   _u(0x00020000)
+#define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB    _u(17)
+#define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB    _u(17)
+#define PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_SHIFTCTRL_AUTOPUSH
+// Description : Push automatically when the input shift register is filled,
+//               i.e. on an IN instruction which causes the input shift counter
+//               to reach or exceed PUSH_THRESH.
+#define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET  _u(0x0)
+#define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS   _u(0x00010000)
+#define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB    _u(16)
+#define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB    _u(16)
+#define PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM3_ADDR
+// Description : Current instruction address of state machine 3
+#define PIO_SM3_ADDR_OFFSET _u(0x0000011c)
+#define PIO_SM3_ADDR_BITS   _u(0x0000001f)
+#define PIO_SM3_ADDR_RESET  _u(0x00000000)
+#define PIO_SM3_ADDR_MSB    _u(4)
+#define PIO_SM3_ADDR_LSB    _u(0)
+#define PIO_SM3_ADDR_ACCESS "RO"
+// =============================================================================
+// Register    : PIO_SM3_INSTR
+// Description : Read to see the instruction currently addressed by state
+//               machine 3's program counter
+//               Write to execute an instruction immediately (including jumps)
+//               and then resume execution.
+#define PIO_SM3_INSTR_OFFSET _u(0x00000120)
+#define PIO_SM3_INSTR_BITS   _u(0x0000ffff)
+#define PIO_SM3_INSTR_RESET  "-"
+#define PIO_SM3_INSTR_MSB    _u(15)
+#define PIO_SM3_INSTR_LSB    _u(0)
+#define PIO_SM3_INSTR_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_SM3_PINCTRL
+// Description : State machine pin control
+#define PIO_SM3_PINCTRL_OFFSET _u(0x00000124)
+#define PIO_SM3_PINCTRL_BITS   _u(0xffffffff)
+#define PIO_SM3_PINCTRL_RESET  _u(0x14000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_PINCTRL_SIDESET_COUNT
+// Description : The number of MSBs of the Delay/Side-set instruction field
+//               which are used for side-set. Inclusive of the enable bit, if
+//               present. Minimum of 0 (all delay bits, no side-set) and maximum
+//               of 5 (all side-set, no delay).
+#define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET  _u(0x0)
+#define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS   _u(0xe0000000)
+#define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB    _u(31)
+#define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB    _u(29)
+#define PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_PINCTRL_SET_COUNT
+// Description : The number of pins asserted by a SET. In the range 0 to 5
+//               inclusive.
+#define PIO_SM3_PINCTRL_SET_COUNT_RESET  _u(0x5)
+#define PIO_SM3_PINCTRL_SET_COUNT_BITS   _u(0x1c000000)
+#define PIO_SM3_PINCTRL_SET_COUNT_MSB    _u(28)
+#define PIO_SM3_PINCTRL_SET_COUNT_LSB    _u(26)
+#define PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_PINCTRL_OUT_COUNT
+// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
+//               PINS instruction. In the range 0 to 32 inclusive.
+#define PIO_SM3_PINCTRL_OUT_COUNT_RESET  _u(0x00)
+#define PIO_SM3_PINCTRL_OUT_COUNT_BITS   _u(0x03f00000)
+#define PIO_SM3_PINCTRL_OUT_COUNT_MSB    _u(25)
+#define PIO_SM3_PINCTRL_OUT_COUNT_LSB    _u(20)
+#define PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_PINCTRL_IN_BASE
+// Description : The pin which is mapped to the least-significant bit of a state
+//               machine's IN data bus. Higher-numbered pins are mapped to
+//               consecutively more-significant data bits, with a modulo of 32
+//               applied to pin number.
+#define PIO_SM3_PINCTRL_IN_BASE_RESET  _u(0x00)
+#define PIO_SM3_PINCTRL_IN_BASE_BITS   _u(0x000f8000)
+#define PIO_SM3_PINCTRL_IN_BASE_MSB    _u(19)
+#define PIO_SM3_PINCTRL_IN_BASE_LSB    _u(15)
+#define PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_PINCTRL_SIDESET_BASE
+// Description : The lowest-numbered pin that will be affected by a side-set
+//               operation. The MSBs of an instruction's side-set/delay field
+//               (up to 5, determined by SIDESET_COUNT) are used for side-set
+//               data, with the remaining LSBs used for delay. The
+//               least-significant bit of the side-set portion is the bit
+//               written to this pin, with more-significant bits written to
+//               higher-numbered pins.
+#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET  _u(0x00)
+#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS   _u(0x00007c00)
+#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB    _u(14)
+#define PIO_SM3_PINCTRL_SIDESET_BASE_LSB    _u(10)
+#define PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_PINCTRL_SET_BASE
+// Description : The lowest-numbered pin that will be affected by a SET PINS or
+//               SET PINDIRS instruction. The data written to this pin is the
+//               least-significant bit of the SET data.
+#define PIO_SM3_PINCTRL_SET_BASE_RESET  _u(0x00)
+#define PIO_SM3_PINCTRL_SET_BASE_BITS   _u(0x000003e0)
+#define PIO_SM3_PINCTRL_SET_BASE_MSB    _u(9)
+#define PIO_SM3_PINCTRL_SET_BASE_LSB    _u(5)
+#define PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_SM3_PINCTRL_OUT_BASE
+// Description : The lowest-numbered pin that will be affected by an OUT PINS,
+//               OUT PINDIRS or MOV PINS instruction. The data written to this
+//               pin will always be the least-significant bit of the OUT or MOV
+//               data.
+#define PIO_SM3_PINCTRL_OUT_BASE_RESET  _u(0x00)
+#define PIO_SM3_PINCTRL_OUT_BASE_BITS   _u(0x0000001f)
+#define PIO_SM3_PINCTRL_OUT_BASE_MSB    _u(4)
+#define PIO_SM3_PINCTRL_OUT_BASE_LSB    _u(0)
+#define PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_INTR
+// Description : Raw Interrupts
+#define PIO_INTR_OFFSET _u(0x00000128)
+#define PIO_INTR_BITS   _u(0x00000fff)
+#define PIO_INTR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_INTR_SM3
+// Description : None
+#define PIO_INTR_SM3_RESET  _u(0x0)
+#define PIO_INTR_SM3_BITS   _u(0x00000800)
+#define PIO_INTR_SM3_MSB    _u(11)
+#define PIO_INTR_SM3_LSB    _u(11)
+#define PIO_INTR_SM3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_INTR_SM2
+// Description : None
+#define PIO_INTR_SM2_RESET  _u(0x0)
+#define PIO_INTR_SM2_BITS   _u(0x00000400)
+#define PIO_INTR_SM2_MSB    _u(10)
+#define PIO_INTR_SM2_LSB    _u(10)
+#define PIO_INTR_SM2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_INTR_SM1
+// Description : None
+#define PIO_INTR_SM1_RESET  _u(0x0)
+#define PIO_INTR_SM1_BITS   _u(0x00000200)
+#define PIO_INTR_SM1_MSB    _u(9)
+#define PIO_INTR_SM1_LSB    _u(9)
+#define PIO_INTR_SM1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_INTR_SM0
+// Description : None
+#define PIO_INTR_SM0_RESET  _u(0x0)
+#define PIO_INTR_SM0_BITS   _u(0x00000100)
+#define PIO_INTR_SM0_MSB    _u(8)
+#define PIO_INTR_SM0_LSB    _u(8)
+#define PIO_INTR_SM0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_INTR_SM3_TXNFULL
+// Description : None
+#define PIO_INTR_SM3_TXNFULL_RESET  _u(0x0)
+#define PIO_INTR_SM3_TXNFULL_BITS   _u(0x00000080)
+#define PIO_INTR_SM3_TXNFULL_MSB    _u(7)
+#define PIO_INTR_SM3_TXNFULL_LSB    _u(7)
+#define PIO_INTR_SM3_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_INTR_SM2_TXNFULL
+// Description : None
+#define PIO_INTR_SM2_TXNFULL_RESET  _u(0x0)
+#define PIO_INTR_SM2_TXNFULL_BITS   _u(0x00000040)
+#define PIO_INTR_SM2_TXNFULL_MSB    _u(6)
+#define PIO_INTR_SM2_TXNFULL_LSB    _u(6)
+#define PIO_INTR_SM2_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_INTR_SM1_TXNFULL
+// Description : None
+#define PIO_INTR_SM1_TXNFULL_RESET  _u(0x0)
+#define PIO_INTR_SM1_TXNFULL_BITS   _u(0x00000020)
+#define PIO_INTR_SM1_TXNFULL_MSB    _u(5)
+#define PIO_INTR_SM1_TXNFULL_LSB    _u(5)
+#define PIO_INTR_SM1_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_INTR_SM0_TXNFULL
+// Description : None
+#define PIO_INTR_SM0_TXNFULL_RESET  _u(0x0)
+#define PIO_INTR_SM0_TXNFULL_BITS   _u(0x00000010)
+#define PIO_INTR_SM0_TXNFULL_MSB    _u(4)
+#define PIO_INTR_SM0_TXNFULL_LSB    _u(4)
+#define PIO_INTR_SM0_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_INTR_SM3_RXNEMPTY
+// Description : None
+#define PIO_INTR_SM3_RXNEMPTY_RESET  _u(0x0)
+#define PIO_INTR_SM3_RXNEMPTY_BITS   _u(0x00000008)
+#define PIO_INTR_SM3_RXNEMPTY_MSB    _u(3)
+#define PIO_INTR_SM3_RXNEMPTY_LSB    _u(3)
+#define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_INTR_SM2_RXNEMPTY
+// Description : None
+#define PIO_INTR_SM2_RXNEMPTY_RESET  _u(0x0)
+#define PIO_INTR_SM2_RXNEMPTY_BITS   _u(0x00000004)
+#define PIO_INTR_SM2_RXNEMPTY_MSB    _u(2)
+#define PIO_INTR_SM2_RXNEMPTY_LSB    _u(2)
+#define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_INTR_SM1_RXNEMPTY
+// Description : None
+#define PIO_INTR_SM1_RXNEMPTY_RESET  _u(0x0)
+#define PIO_INTR_SM1_RXNEMPTY_BITS   _u(0x00000002)
+#define PIO_INTR_SM1_RXNEMPTY_MSB    _u(1)
+#define PIO_INTR_SM1_RXNEMPTY_LSB    _u(1)
+#define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_INTR_SM0_RXNEMPTY
+// Description : None
+#define PIO_INTR_SM0_RXNEMPTY_RESET  _u(0x0)
+#define PIO_INTR_SM0_RXNEMPTY_BITS   _u(0x00000001)
+#define PIO_INTR_SM0_RXNEMPTY_MSB    _u(0)
+#define PIO_INTR_SM0_RXNEMPTY_LSB    _u(0)
+#define PIO_INTR_SM0_RXNEMPTY_ACCESS "RO"
+// =============================================================================
+// Register    : PIO_IRQ0_INTE
+// Description : Interrupt Enable for irq0
+#define PIO_IRQ0_INTE_OFFSET _u(0x0000012c)
+#define PIO_IRQ0_INTE_BITS   _u(0x00000fff)
+#define PIO_IRQ0_INTE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTE_SM3
+// Description : None
+#define PIO_IRQ0_INTE_SM3_RESET  _u(0x0)
+#define PIO_IRQ0_INTE_SM3_BITS   _u(0x00000800)
+#define PIO_IRQ0_INTE_SM3_MSB    _u(11)
+#define PIO_IRQ0_INTE_SM3_LSB    _u(11)
+#define PIO_IRQ0_INTE_SM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTE_SM2
+// Description : None
+#define PIO_IRQ0_INTE_SM2_RESET  _u(0x0)
+#define PIO_IRQ0_INTE_SM2_BITS   _u(0x00000400)
+#define PIO_IRQ0_INTE_SM2_MSB    _u(10)
+#define PIO_IRQ0_INTE_SM2_LSB    _u(10)
+#define PIO_IRQ0_INTE_SM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTE_SM1
+// Description : None
+#define PIO_IRQ0_INTE_SM1_RESET  _u(0x0)
+#define PIO_IRQ0_INTE_SM1_BITS   _u(0x00000200)
+#define PIO_IRQ0_INTE_SM1_MSB    _u(9)
+#define PIO_IRQ0_INTE_SM1_LSB    _u(9)
+#define PIO_IRQ0_INTE_SM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTE_SM0
+// Description : None
+#define PIO_IRQ0_INTE_SM0_RESET  _u(0x0)
+#define PIO_IRQ0_INTE_SM0_BITS   _u(0x00000100)
+#define PIO_IRQ0_INTE_SM0_MSB    _u(8)
+#define PIO_IRQ0_INTE_SM0_LSB    _u(8)
+#define PIO_IRQ0_INTE_SM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTE_SM3_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS   _u(0x00000080)
+#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB    _u(7)
+#define PIO_IRQ0_INTE_SM3_TXNFULL_LSB    _u(7)
+#define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTE_SM2_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS   _u(0x00000040)
+#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB    _u(6)
+#define PIO_IRQ0_INTE_SM2_TXNFULL_LSB    _u(6)
+#define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTE_SM1_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS   _u(0x00000020)
+#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB    _u(5)
+#define PIO_IRQ0_INTE_SM1_TXNFULL_LSB    _u(5)
+#define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTE_SM0_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS   _u(0x00000010)
+#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB    _u(4)
+#define PIO_IRQ0_INTE_SM0_TXNFULL_LSB    _u(4)
+#define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTE_SM3_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS   _u(0x00000008)
+#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB    _u(3)
+#define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB    _u(3)
+#define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTE_SM2_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS   _u(0x00000004)
+#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB    _u(2)
+#define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB    _u(2)
+#define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTE_SM1_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS   _u(0x00000002)
+#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB    _u(1)
+#define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB    _u(1)
+#define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTE_SM0_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS   _u(0x00000001)
+#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB    _u(0)
+#define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB    _u(0)
+#define PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_IRQ0_INTF
+// Description : Interrupt Force for irq0
+#define PIO_IRQ0_INTF_OFFSET _u(0x00000130)
+#define PIO_IRQ0_INTF_BITS   _u(0x00000fff)
+#define PIO_IRQ0_INTF_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTF_SM3
+// Description : None
+#define PIO_IRQ0_INTF_SM3_RESET  _u(0x0)
+#define PIO_IRQ0_INTF_SM3_BITS   _u(0x00000800)
+#define PIO_IRQ0_INTF_SM3_MSB    _u(11)
+#define PIO_IRQ0_INTF_SM3_LSB    _u(11)
+#define PIO_IRQ0_INTF_SM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTF_SM2
+// Description : None
+#define PIO_IRQ0_INTF_SM2_RESET  _u(0x0)
+#define PIO_IRQ0_INTF_SM2_BITS   _u(0x00000400)
+#define PIO_IRQ0_INTF_SM2_MSB    _u(10)
+#define PIO_IRQ0_INTF_SM2_LSB    _u(10)
+#define PIO_IRQ0_INTF_SM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTF_SM1
+// Description : None
+#define PIO_IRQ0_INTF_SM1_RESET  _u(0x0)
+#define PIO_IRQ0_INTF_SM1_BITS   _u(0x00000200)
+#define PIO_IRQ0_INTF_SM1_MSB    _u(9)
+#define PIO_IRQ0_INTF_SM1_LSB    _u(9)
+#define PIO_IRQ0_INTF_SM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTF_SM0
+// Description : None
+#define PIO_IRQ0_INTF_SM0_RESET  _u(0x0)
+#define PIO_IRQ0_INTF_SM0_BITS   _u(0x00000100)
+#define PIO_IRQ0_INTF_SM0_MSB    _u(8)
+#define PIO_IRQ0_INTF_SM0_LSB    _u(8)
+#define PIO_IRQ0_INTF_SM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTF_SM3_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS   _u(0x00000080)
+#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB    _u(7)
+#define PIO_IRQ0_INTF_SM3_TXNFULL_LSB    _u(7)
+#define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTF_SM2_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS   _u(0x00000040)
+#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB    _u(6)
+#define PIO_IRQ0_INTF_SM2_TXNFULL_LSB    _u(6)
+#define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTF_SM1_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS   _u(0x00000020)
+#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB    _u(5)
+#define PIO_IRQ0_INTF_SM1_TXNFULL_LSB    _u(5)
+#define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTF_SM0_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS   _u(0x00000010)
+#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB    _u(4)
+#define PIO_IRQ0_INTF_SM0_TXNFULL_LSB    _u(4)
+#define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTF_SM3_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS   _u(0x00000008)
+#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB    _u(3)
+#define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB    _u(3)
+#define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTF_SM2_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS   _u(0x00000004)
+#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB    _u(2)
+#define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB    _u(2)
+#define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTF_SM1_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS   _u(0x00000002)
+#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB    _u(1)
+#define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB    _u(1)
+#define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTF_SM0_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS   _u(0x00000001)
+#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB    _u(0)
+#define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB    _u(0)
+#define PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_IRQ0_INTS
+// Description : Interrupt status after masking & forcing for irq0
+#define PIO_IRQ0_INTS_OFFSET _u(0x00000134)
+#define PIO_IRQ0_INTS_BITS   _u(0x00000fff)
+#define PIO_IRQ0_INTS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTS_SM3
+// Description : None
+#define PIO_IRQ0_INTS_SM3_RESET  _u(0x0)
+#define PIO_IRQ0_INTS_SM3_BITS   _u(0x00000800)
+#define PIO_IRQ0_INTS_SM3_MSB    _u(11)
+#define PIO_IRQ0_INTS_SM3_LSB    _u(11)
+#define PIO_IRQ0_INTS_SM3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTS_SM2
+// Description : None
+#define PIO_IRQ0_INTS_SM2_RESET  _u(0x0)
+#define PIO_IRQ0_INTS_SM2_BITS   _u(0x00000400)
+#define PIO_IRQ0_INTS_SM2_MSB    _u(10)
+#define PIO_IRQ0_INTS_SM2_LSB    _u(10)
+#define PIO_IRQ0_INTS_SM2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTS_SM1
+// Description : None
+#define PIO_IRQ0_INTS_SM1_RESET  _u(0x0)
+#define PIO_IRQ0_INTS_SM1_BITS   _u(0x00000200)
+#define PIO_IRQ0_INTS_SM1_MSB    _u(9)
+#define PIO_IRQ0_INTS_SM1_LSB    _u(9)
+#define PIO_IRQ0_INTS_SM1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTS_SM0
+// Description : None
+#define PIO_IRQ0_INTS_SM0_RESET  _u(0x0)
+#define PIO_IRQ0_INTS_SM0_BITS   _u(0x00000100)
+#define PIO_IRQ0_INTS_SM0_MSB    _u(8)
+#define PIO_IRQ0_INTS_SM0_LSB    _u(8)
+#define PIO_IRQ0_INTS_SM0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTS_SM3_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS   _u(0x00000080)
+#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB    _u(7)
+#define PIO_IRQ0_INTS_SM3_TXNFULL_LSB    _u(7)
+#define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTS_SM2_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS   _u(0x00000040)
+#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB    _u(6)
+#define PIO_IRQ0_INTS_SM2_TXNFULL_LSB    _u(6)
+#define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTS_SM1_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS   _u(0x00000020)
+#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB    _u(5)
+#define PIO_IRQ0_INTS_SM1_TXNFULL_LSB    _u(5)
+#define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTS_SM0_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS   _u(0x00000010)
+#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB    _u(4)
+#define PIO_IRQ0_INTS_SM0_TXNFULL_LSB    _u(4)
+#define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTS_SM3_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS   _u(0x00000008)
+#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB    _u(3)
+#define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB    _u(3)
+#define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTS_SM2_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS   _u(0x00000004)
+#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB    _u(2)
+#define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB    _u(2)
+#define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTS_SM1_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS   _u(0x00000002)
+#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB    _u(1)
+#define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB    _u(1)
+#define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ0_INTS_SM0_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS   _u(0x00000001)
+#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB    _u(0)
+#define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB    _u(0)
+#define PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO"
+// =============================================================================
+// Register    : PIO_IRQ1_INTE
+// Description : Interrupt Enable for irq1
+#define PIO_IRQ1_INTE_OFFSET _u(0x00000138)
+#define PIO_IRQ1_INTE_BITS   _u(0x00000fff)
+#define PIO_IRQ1_INTE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTE_SM3
+// Description : None
+#define PIO_IRQ1_INTE_SM3_RESET  _u(0x0)
+#define PIO_IRQ1_INTE_SM3_BITS   _u(0x00000800)
+#define PIO_IRQ1_INTE_SM3_MSB    _u(11)
+#define PIO_IRQ1_INTE_SM3_LSB    _u(11)
+#define PIO_IRQ1_INTE_SM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTE_SM2
+// Description : None
+#define PIO_IRQ1_INTE_SM2_RESET  _u(0x0)
+#define PIO_IRQ1_INTE_SM2_BITS   _u(0x00000400)
+#define PIO_IRQ1_INTE_SM2_MSB    _u(10)
+#define PIO_IRQ1_INTE_SM2_LSB    _u(10)
+#define PIO_IRQ1_INTE_SM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTE_SM1
+// Description : None
+#define PIO_IRQ1_INTE_SM1_RESET  _u(0x0)
+#define PIO_IRQ1_INTE_SM1_BITS   _u(0x00000200)
+#define PIO_IRQ1_INTE_SM1_MSB    _u(9)
+#define PIO_IRQ1_INTE_SM1_LSB    _u(9)
+#define PIO_IRQ1_INTE_SM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTE_SM0
+// Description : None
+#define PIO_IRQ1_INTE_SM0_RESET  _u(0x0)
+#define PIO_IRQ1_INTE_SM0_BITS   _u(0x00000100)
+#define PIO_IRQ1_INTE_SM0_MSB    _u(8)
+#define PIO_IRQ1_INTE_SM0_LSB    _u(8)
+#define PIO_IRQ1_INTE_SM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTE_SM3_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS   _u(0x00000080)
+#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB    _u(7)
+#define PIO_IRQ1_INTE_SM3_TXNFULL_LSB    _u(7)
+#define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTE_SM2_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS   _u(0x00000040)
+#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB    _u(6)
+#define PIO_IRQ1_INTE_SM2_TXNFULL_LSB    _u(6)
+#define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTE_SM1_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS   _u(0x00000020)
+#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB    _u(5)
+#define PIO_IRQ1_INTE_SM1_TXNFULL_LSB    _u(5)
+#define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTE_SM0_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS   _u(0x00000010)
+#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB    _u(4)
+#define PIO_IRQ1_INTE_SM0_TXNFULL_LSB    _u(4)
+#define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTE_SM3_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS   _u(0x00000008)
+#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB    _u(3)
+#define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB    _u(3)
+#define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTE_SM2_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS   _u(0x00000004)
+#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB    _u(2)
+#define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB    _u(2)
+#define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTE_SM1_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS   _u(0x00000002)
+#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB    _u(1)
+#define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB    _u(1)
+#define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTE_SM0_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS   _u(0x00000001)
+#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB    _u(0)
+#define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB    _u(0)
+#define PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_IRQ1_INTF
+// Description : Interrupt Force for irq1
+#define PIO_IRQ1_INTF_OFFSET _u(0x0000013c)
+#define PIO_IRQ1_INTF_BITS   _u(0x00000fff)
+#define PIO_IRQ1_INTF_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTF_SM3
+// Description : None
+#define PIO_IRQ1_INTF_SM3_RESET  _u(0x0)
+#define PIO_IRQ1_INTF_SM3_BITS   _u(0x00000800)
+#define PIO_IRQ1_INTF_SM3_MSB    _u(11)
+#define PIO_IRQ1_INTF_SM3_LSB    _u(11)
+#define PIO_IRQ1_INTF_SM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTF_SM2
+// Description : None
+#define PIO_IRQ1_INTF_SM2_RESET  _u(0x0)
+#define PIO_IRQ1_INTF_SM2_BITS   _u(0x00000400)
+#define PIO_IRQ1_INTF_SM2_MSB    _u(10)
+#define PIO_IRQ1_INTF_SM2_LSB    _u(10)
+#define PIO_IRQ1_INTF_SM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTF_SM1
+// Description : None
+#define PIO_IRQ1_INTF_SM1_RESET  _u(0x0)
+#define PIO_IRQ1_INTF_SM1_BITS   _u(0x00000200)
+#define PIO_IRQ1_INTF_SM1_MSB    _u(9)
+#define PIO_IRQ1_INTF_SM1_LSB    _u(9)
+#define PIO_IRQ1_INTF_SM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTF_SM0
+// Description : None
+#define PIO_IRQ1_INTF_SM0_RESET  _u(0x0)
+#define PIO_IRQ1_INTF_SM0_BITS   _u(0x00000100)
+#define PIO_IRQ1_INTF_SM0_MSB    _u(8)
+#define PIO_IRQ1_INTF_SM0_LSB    _u(8)
+#define PIO_IRQ1_INTF_SM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTF_SM3_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS   _u(0x00000080)
+#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB    _u(7)
+#define PIO_IRQ1_INTF_SM3_TXNFULL_LSB    _u(7)
+#define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTF_SM2_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS   _u(0x00000040)
+#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB    _u(6)
+#define PIO_IRQ1_INTF_SM2_TXNFULL_LSB    _u(6)
+#define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTF_SM1_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS   _u(0x00000020)
+#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB    _u(5)
+#define PIO_IRQ1_INTF_SM1_TXNFULL_LSB    _u(5)
+#define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTF_SM0_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS   _u(0x00000010)
+#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB    _u(4)
+#define PIO_IRQ1_INTF_SM0_TXNFULL_LSB    _u(4)
+#define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTF_SM3_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS   _u(0x00000008)
+#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB    _u(3)
+#define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB    _u(3)
+#define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTF_SM2_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS   _u(0x00000004)
+#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB    _u(2)
+#define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB    _u(2)
+#define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTF_SM1_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS   _u(0x00000002)
+#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB    _u(1)
+#define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB    _u(1)
+#define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTF_SM0_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS   _u(0x00000001)
+#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB    _u(0)
+#define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB    _u(0)
+#define PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW"
+// =============================================================================
+// Register    : PIO_IRQ1_INTS
+// Description : Interrupt status after masking & forcing for irq1
+#define PIO_IRQ1_INTS_OFFSET _u(0x00000140)
+#define PIO_IRQ1_INTS_BITS   _u(0x00000fff)
+#define PIO_IRQ1_INTS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTS_SM3
+// Description : None
+#define PIO_IRQ1_INTS_SM3_RESET  _u(0x0)
+#define PIO_IRQ1_INTS_SM3_BITS   _u(0x00000800)
+#define PIO_IRQ1_INTS_SM3_MSB    _u(11)
+#define PIO_IRQ1_INTS_SM3_LSB    _u(11)
+#define PIO_IRQ1_INTS_SM3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTS_SM2
+// Description : None
+#define PIO_IRQ1_INTS_SM2_RESET  _u(0x0)
+#define PIO_IRQ1_INTS_SM2_BITS   _u(0x00000400)
+#define PIO_IRQ1_INTS_SM2_MSB    _u(10)
+#define PIO_IRQ1_INTS_SM2_LSB    _u(10)
+#define PIO_IRQ1_INTS_SM2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTS_SM1
+// Description : None
+#define PIO_IRQ1_INTS_SM1_RESET  _u(0x0)
+#define PIO_IRQ1_INTS_SM1_BITS   _u(0x00000200)
+#define PIO_IRQ1_INTS_SM1_MSB    _u(9)
+#define PIO_IRQ1_INTS_SM1_LSB    _u(9)
+#define PIO_IRQ1_INTS_SM1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTS_SM0
+// Description : None
+#define PIO_IRQ1_INTS_SM0_RESET  _u(0x0)
+#define PIO_IRQ1_INTS_SM0_BITS   _u(0x00000100)
+#define PIO_IRQ1_INTS_SM0_MSB    _u(8)
+#define PIO_IRQ1_INTS_SM0_LSB    _u(8)
+#define PIO_IRQ1_INTS_SM0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTS_SM3_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS   _u(0x00000080)
+#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB    _u(7)
+#define PIO_IRQ1_INTS_SM3_TXNFULL_LSB    _u(7)
+#define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTS_SM2_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS   _u(0x00000040)
+#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB    _u(6)
+#define PIO_IRQ1_INTS_SM2_TXNFULL_LSB    _u(6)
+#define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTS_SM1_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS   _u(0x00000020)
+#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB    _u(5)
+#define PIO_IRQ1_INTS_SM1_TXNFULL_LSB    _u(5)
+#define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTS_SM0_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET  _u(0x0)
+#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS   _u(0x00000010)
+#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB    _u(4)
+#define PIO_IRQ1_INTS_SM0_TXNFULL_LSB    _u(4)
+#define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTS_SM3_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS   _u(0x00000008)
+#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB    _u(3)
+#define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB    _u(3)
+#define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTS_SM2_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS   _u(0x00000004)
+#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB    _u(2)
+#define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB    _u(2)
+#define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTS_SM1_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS   _u(0x00000002)
+#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB    _u(1)
+#define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB    _u(1)
+#define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PIO_IRQ1_INTS_SM0_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET  _u(0x0)
+#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS   _u(0x00000001)
+#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB    _u(0)
+#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB    _u(0)
+#define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_PIO_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pll.h b/src/rp2040/hardware_regs/include/hardware/regs/pll.h
new file mode 100644
index 0000000..a0f5ad0
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/pll.h
@@ -0,0 +1,135 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : PLL
+// Version        : 1
+// Bus type       : apb
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_PLL_DEFINED
+#define HARDWARE_REGS_PLL_DEFINED
+// =============================================================================
+// Register    : PLL_CS
+// Description : Control and Status
+//               GENERAL CONSTRAINTS:
+//               Reference clock frequency min=5MHz, max=800MHz
+//               Feedback divider min=16, max=320
+//               VCO frequency min=400MHz, max=1600MHz
+#define PLL_CS_OFFSET _u(0x00000000)
+#define PLL_CS_BITS   _u(0x8000013f)
+#define PLL_CS_RESET  _u(0x00000001)
+// -----------------------------------------------------------------------------
+// Field       : PLL_CS_LOCK
+// Description : PLL is locked
+#define PLL_CS_LOCK_RESET  _u(0x0)
+#define PLL_CS_LOCK_BITS   _u(0x80000000)
+#define PLL_CS_LOCK_MSB    _u(31)
+#define PLL_CS_LOCK_LSB    _u(31)
+#define PLL_CS_LOCK_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PLL_CS_BYPASS
+// Description : Passes the reference clock to the output instead of the divided
+//               VCO. The VCO continues to run so the user can switch between
+//               the reference clock and the divided VCO but the output will
+//               glitch when doing so.
+#define PLL_CS_BYPASS_RESET  _u(0x0)
+#define PLL_CS_BYPASS_BITS   _u(0x00000100)
+#define PLL_CS_BYPASS_MSB    _u(8)
+#define PLL_CS_BYPASS_LSB    _u(8)
+#define PLL_CS_BYPASS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PLL_CS_REFDIV
+// Description : Divides the PLL input reference clock.
+//               Behaviour is undefined for div=0.
+//               PLL output will be unpredictable during refdiv changes, wait
+//               for lock=1 before using it.
+#define PLL_CS_REFDIV_RESET  _u(0x01)
+#define PLL_CS_REFDIV_BITS   _u(0x0000003f)
+#define PLL_CS_REFDIV_MSB    _u(5)
+#define PLL_CS_REFDIV_LSB    _u(0)
+#define PLL_CS_REFDIV_ACCESS "RW"
+// =============================================================================
+// Register    : PLL_PWR
+// Description : Controls the PLL power modes.
+#define PLL_PWR_OFFSET _u(0x00000004)
+#define PLL_PWR_BITS   _u(0x0000002d)
+#define PLL_PWR_RESET  _u(0x0000002d)
+// -----------------------------------------------------------------------------
+// Field       : PLL_PWR_VCOPD
+// Description : PLL VCO powerdown
+//               To save power set high when PLL output not required or
+//               bypass=1.
+#define PLL_PWR_VCOPD_RESET  _u(0x1)
+#define PLL_PWR_VCOPD_BITS   _u(0x00000020)
+#define PLL_PWR_VCOPD_MSB    _u(5)
+#define PLL_PWR_VCOPD_LSB    _u(5)
+#define PLL_PWR_VCOPD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PLL_PWR_POSTDIVPD
+// Description : PLL post divider powerdown
+//               To save power set high when PLL output not required or
+//               bypass=1.
+#define PLL_PWR_POSTDIVPD_RESET  _u(0x1)
+#define PLL_PWR_POSTDIVPD_BITS   _u(0x00000008)
+#define PLL_PWR_POSTDIVPD_MSB    _u(3)
+#define PLL_PWR_POSTDIVPD_LSB    _u(3)
+#define PLL_PWR_POSTDIVPD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PLL_PWR_DSMPD
+// Description : PLL DSM powerdown
+//               Nothing is achieved by setting this low.
+#define PLL_PWR_DSMPD_RESET  _u(0x1)
+#define PLL_PWR_DSMPD_BITS   _u(0x00000004)
+#define PLL_PWR_DSMPD_MSB    _u(2)
+#define PLL_PWR_DSMPD_LSB    _u(2)
+#define PLL_PWR_DSMPD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PLL_PWR_PD
+// Description : PLL powerdown
+//               To save power set high when PLL output not required.
+#define PLL_PWR_PD_RESET  _u(0x1)
+#define PLL_PWR_PD_BITS   _u(0x00000001)
+#define PLL_PWR_PD_MSB    _u(0)
+#define PLL_PWR_PD_LSB    _u(0)
+#define PLL_PWR_PD_ACCESS "RW"
+// =============================================================================
+// Register    : PLL_FBDIV_INT
+// Description : Feedback divisor
+//               (note: this PLL does not support fractional division)
+//               see ctrl reg description for constraints
+#define PLL_FBDIV_INT_OFFSET _u(0x00000008)
+#define PLL_FBDIV_INT_BITS   _u(0x00000fff)
+#define PLL_FBDIV_INT_RESET  _u(0x00000000)
+#define PLL_FBDIV_INT_MSB    _u(11)
+#define PLL_FBDIV_INT_LSB    _u(0)
+#define PLL_FBDIV_INT_ACCESS "RW"
+// =============================================================================
+// Register    : PLL_PRIM
+// Description : Controls the PLL post dividers for the primary output
+//               (note: this PLL does not have a secondary output)
+//               the primary output is driven from VCO divided by
+//               postdiv1*postdiv2
+#define PLL_PRIM_OFFSET _u(0x0000000c)
+#define PLL_PRIM_BITS   _u(0x00077000)
+#define PLL_PRIM_RESET  _u(0x00077000)
+// -----------------------------------------------------------------------------
+// Field       : PLL_PRIM_POSTDIV1
+// Description : divide by 1-7
+#define PLL_PRIM_POSTDIV1_RESET  _u(0x7)
+#define PLL_PRIM_POSTDIV1_BITS   _u(0x00070000)
+#define PLL_PRIM_POSTDIV1_MSB    _u(18)
+#define PLL_PRIM_POSTDIV1_LSB    _u(16)
+#define PLL_PRIM_POSTDIV1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PLL_PRIM_POSTDIV2
+// Description : divide by 1-7
+#define PLL_PRIM_POSTDIV2_RESET  _u(0x7)
+#define PLL_PRIM_POSTDIV2_BITS   _u(0x00007000)
+#define PLL_PRIM_POSTDIV2_MSB    _u(14)
+#define PLL_PRIM_POSTDIV2_LSB    _u(12)
+#define PLL_PRIM_POSTDIV2_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_PLL_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/psm.h b/src/rp2040/hardware_regs/include/hardware/regs/psm.h
new file mode 100644
index 0000000..8810ae8
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/psm.h
@@ -0,0 +1,584 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : PSM
+// Version        : 1
+// Bus type       : apb
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_PSM_DEFINED
+#define HARDWARE_REGS_PSM_DEFINED
+// =============================================================================
+// Register    : PSM_FRCE_ON
+// Description : Force block out of reset (i.e. power it on)
+#define PSM_FRCE_ON_OFFSET _u(0x00000000)
+#define PSM_FRCE_ON_BITS   _u(0x0001ffff)
+#define PSM_FRCE_ON_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_PROC1
+// Description : None
+#define PSM_FRCE_ON_PROC1_RESET  _u(0x0)
+#define PSM_FRCE_ON_PROC1_BITS   _u(0x00010000)
+#define PSM_FRCE_ON_PROC1_MSB    _u(16)
+#define PSM_FRCE_ON_PROC1_LSB    _u(16)
+#define PSM_FRCE_ON_PROC1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_PROC0
+// Description : None
+#define PSM_FRCE_ON_PROC0_RESET  _u(0x0)
+#define PSM_FRCE_ON_PROC0_BITS   _u(0x00008000)
+#define PSM_FRCE_ON_PROC0_MSB    _u(15)
+#define PSM_FRCE_ON_PROC0_LSB    _u(15)
+#define PSM_FRCE_ON_PROC0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_SIO
+// Description : None
+#define PSM_FRCE_ON_SIO_RESET  _u(0x0)
+#define PSM_FRCE_ON_SIO_BITS   _u(0x00004000)
+#define PSM_FRCE_ON_SIO_MSB    _u(14)
+#define PSM_FRCE_ON_SIO_LSB    _u(14)
+#define PSM_FRCE_ON_SIO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_VREG_AND_CHIP_RESET
+// Description : None
+#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET  _u(0x0)
+#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS   _u(0x00002000)
+#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB    _u(13)
+#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB    _u(13)
+#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_XIP
+// Description : None
+#define PSM_FRCE_ON_XIP_RESET  _u(0x0)
+#define PSM_FRCE_ON_XIP_BITS   _u(0x00001000)
+#define PSM_FRCE_ON_XIP_MSB    _u(12)
+#define PSM_FRCE_ON_XIP_LSB    _u(12)
+#define PSM_FRCE_ON_XIP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_SRAM5
+// Description : None
+#define PSM_FRCE_ON_SRAM5_RESET  _u(0x0)
+#define PSM_FRCE_ON_SRAM5_BITS   _u(0x00000800)
+#define PSM_FRCE_ON_SRAM5_MSB    _u(11)
+#define PSM_FRCE_ON_SRAM5_LSB    _u(11)
+#define PSM_FRCE_ON_SRAM5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_SRAM4
+// Description : None
+#define PSM_FRCE_ON_SRAM4_RESET  _u(0x0)
+#define PSM_FRCE_ON_SRAM4_BITS   _u(0x00000400)
+#define PSM_FRCE_ON_SRAM4_MSB    _u(10)
+#define PSM_FRCE_ON_SRAM4_LSB    _u(10)
+#define PSM_FRCE_ON_SRAM4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_SRAM3
+// Description : None
+#define PSM_FRCE_ON_SRAM3_RESET  _u(0x0)
+#define PSM_FRCE_ON_SRAM3_BITS   _u(0x00000200)
+#define PSM_FRCE_ON_SRAM3_MSB    _u(9)
+#define PSM_FRCE_ON_SRAM3_LSB    _u(9)
+#define PSM_FRCE_ON_SRAM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_SRAM2
+// Description : None
+#define PSM_FRCE_ON_SRAM2_RESET  _u(0x0)
+#define PSM_FRCE_ON_SRAM2_BITS   _u(0x00000100)
+#define PSM_FRCE_ON_SRAM2_MSB    _u(8)
+#define PSM_FRCE_ON_SRAM2_LSB    _u(8)
+#define PSM_FRCE_ON_SRAM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_SRAM1
+// Description : None
+#define PSM_FRCE_ON_SRAM1_RESET  _u(0x0)
+#define PSM_FRCE_ON_SRAM1_BITS   _u(0x00000080)
+#define PSM_FRCE_ON_SRAM1_MSB    _u(7)
+#define PSM_FRCE_ON_SRAM1_LSB    _u(7)
+#define PSM_FRCE_ON_SRAM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_SRAM0
+// Description : None
+#define PSM_FRCE_ON_SRAM0_RESET  _u(0x0)
+#define PSM_FRCE_ON_SRAM0_BITS   _u(0x00000040)
+#define PSM_FRCE_ON_SRAM0_MSB    _u(6)
+#define PSM_FRCE_ON_SRAM0_LSB    _u(6)
+#define PSM_FRCE_ON_SRAM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_ROM
+// Description : None
+#define PSM_FRCE_ON_ROM_RESET  _u(0x0)
+#define PSM_FRCE_ON_ROM_BITS   _u(0x00000020)
+#define PSM_FRCE_ON_ROM_MSB    _u(5)
+#define PSM_FRCE_ON_ROM_LSB    _u(5)
+#define PSM_FRCE_ON_ROM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_BUSFABRIC
+// Description : None
+#define PSM_FRCE_ON_BUSFABRIC_RESET  _u(0x0)
+#define PSM_FRCE_ON_BUSFABRIC_BITS   _u(0x00000010)
+#define PSM_FRCE_ON_BUSFABRIC_MSB    _u(4)
+#define PSM_FRCE_ON_BUSFABRIC_LSB    _u(4)
+#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_RESETS
+// Description : None
+#define PSM_FRCE_ON_RESETS_RESET  _u(0x0)
+#define PSM_FRCE_ON_RESETS_BITS   _u(0x00000008)
+#define PSM_FRCE_ON_RESETS_MSB    _u(3)
+#define PSM_FRCE_ON_RESETS_LSB    _u(3)
+#define PSM_FRCE_ON_RESETS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_CLOCKS
+// Description : None
+#define PSM_FRCE_ON_CLOCKS_RESET  _u(0x0)
+#define PSM_FRCE_ON_CLOCKS_BITS   _u(0x00000004)
+#define PSM_FRCE_ON_CLOCKS_MSB    _u(2)
+#define PSM_FRCE_ON_CLOCKS_LSB    _u(2)
+#define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_XOSC
+// Description : None
+#define PSM_FRCE_ON_XOSC_RESET  _u(0x0)
+#define PSM_FRCE_ON_XOSC_BITS   _u(0x00000002)
+#define PSM_FRCE_ON_XOSC_MSB    _u(1)
+#define PSM_FRCE_ON_XOSC_LSB    _u(1)
+#define PSM_FRCE_ON_XOSC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_ON_ROSC
+// Description : None
+#define PSM_FRCE_ON_ROSC_RESET  _u(0x0)
+#define PSM_FRCE_ON_ROSC_BITS   _u(0x00000001)
+#define PSM_FRCE_ON_ROSC_MSB    _u(0)
+#define PSM_FRCE_ON_ROSC_LSB    _u(0)
+#define PSM_FRCE_ON_ROSC_ACCESS "RW"
+// =============================================================================
+// Register    : PSM_FRCE_OFF
+// Description : Force into reset (i.e. power it off)
+#define PSM_FRCE_OFF_OFFSET _u(0x00000004)
+#define PSM_FRCE_OFF_BITS   _u(0x0001ffff)
+#define PSM_FRCE_OFF_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_PROC1
+// Description : None
+#define PSM_FRCE_OFF_PROC1_RESET  _u(0x0)
+#define PSM_FRCE_OFF_PROC1_BITS   _u(0x00010000)
+#define PSM_FRCE_OFF_PROC1_MSB    _u(16)
+#define PSM_FRCE_OFF_PROC1_LSB    _u(16)
+#define PSM_FRCE_OFF_PROC1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_PROC0
+// Description : None
+#define PSM_FRCE_OFF_PROC0_RESET  _u(0x0)
+#define PSM_FRCE_OFF_PROC0_BITS   _u(0x00008000)
+#define PSM_FRCE_OFF_PROC0_MSB    _u(15)
+#define PSM_FRCE_OFF_PROC0_LSB    _u(15)
+#define PSM_FRCE_OFF_PROC0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_SIO
+// Description : None
+#define PSM_FRCE_OFF_SIO_RESET  _u(0x0)
+#define PSM_FRCE_OFF_SIO_BITS   _u(0x00004000)
+#define PSM_FRCE_OFF_SIO_MSB    _u(14)
+#define PSM_FRCE_OFF_SIO_LSB    _u(14)
+#define PSM_FRCE_OFF_SIO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_VREG_AND_CHIP_RESET
+// Description : None
+#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET  _u(0x0)
+#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS   _u(0x00002000)
+#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB    _u(13)
+#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB    _u(13)
+#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_XIP
+// Description : None
+#define PSM_FRCE_OFF_XIP_RESET  _u(0x0)
+#define PSM_FRCE_OFF_XIP_BITS   _u(0x00001000)
+#define PSM_FRCE_OFF_XIP_MSB    _u(12)
+#define PSM_FRCE_OFF_XIP_LSB    _u(12)
+#define PSM_FRCE_OFF_XIP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_SRAM5
+// Description : None
+#define PSM_FRCE_OFF_SRAM5_RESET  _u(0x0)
+#define PSM_FRCE_OFF_SRAM5_BITS   _u(0x00000800)
+#define PSM_FRCE_OFF_SRAM5_MSB    _u(11)
+#define PSM_FRCE_OFF_SRAM5_LSB    _u(11)
+#define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_SRAM4
+// Description : None
+#define PSM_FRCE_OFF_SRAM4_RESET  _u(0x0)
+#define PSM_FRCE_OFF_SRAM4_BITS   _u(0x00000400)
+#define PSM_FRCE_OFF_SRAM4_MSB    _u(10)
+#define PSM_FRCE_OFF_SRAM4_LSB    _u(10)
+#define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_SRAM3
+// Description : None
+#define PSM_FRCE_OFF_SRAM3_RESET  _u(0x0)
+#define PSM_FRCE_OFF_SRAM3_BITS   _u(0x00000200)
+#define PSM_FRCE_OFF_SRAM3_MSB    _u(9)
+#define PSM_FRCE_OFF_SRAM3_LSB    _u(9)
+#define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_SRAM2
+// Description : None
+#define PSM_FRCE_OFF_SRAM2_RESET  _u(0x0)
+#define PSM_FRCE_OFF_SRAM2_BITS   _u(0x00000100)
+#define PSM_FRCE_OFF_SRAM2_MSB    _u(8)
+#define PSM_FRCE_OFF_SRAM2_LSB    _u(8)
+#define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_SRAM1
+// Description : None
+#define PSM_FRCE_OFF_SRAM1_RESET  _u(0x0)
+#define PSM_FRCE_OFF_SRAM1_BITS   _u(0x00000080)
+#define PSM_FRCE_OFF_SRAM1_MSB    _u(7)
+#define PSM_FRCE_OFF_SRAM1_LSB    _u(7)
+#define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_SRAM0
+// Description : None
+#define PSM_FRCE_OFF_SRAM0_RESET  _u(0x0)
+#define PSM_FRCE_OFF_SRAM0_BITS   _u(0x00000040)
+#define PSM_FRCE_OFF_SRAM0_MSB    _u(6)
+#define PSM_FRCE_OFF_SRAM0_LSB    _u(6)
+#define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_ROM
+// Description : None
+#define PSM_FRCE_OFF_ROM_RESET  _u(0x0)
+#define PSM_FRCE_OFF_ROM_BITS   _u(0x00000020)
+#define PSM_FRCE_OFF_ROM_MSB    _u(5)
+#define PSM_FRCE_OFF_ROM_LSB    _u(5)
+#define PSM_FRCE_OFF_ROM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_BUSFABRIC
+// Description : None
+#define PSM_FRCE_OFF_BUSFABRIC_RESET  _u(0x0)
+#define PSM_FRCE_OFF_BUSFABRIC_BITS   _u(0x00000010)
+#define PSM_FRCE_OFF_BUSFABRIC_MSB    _u(4)
+#define PSM_FRCE_OFF_BUSFABRIC_LSB    _u(4)
+#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_RESETS
+// Description : None
+#define PSM_FRCE_OFF_RESETS_RESET  _u(0x0)
+#define PSM_FRCE_OFF_RESETS_BITS   _u(0x00000008)
+#define PSM_FRCE_OFF_RESETS_MSB    _u(3)
+#define PSM_FRCE_OFF_RESETS_LSB    _u(3)
+#define PSM_FRCE_OFF_RESETS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_CLOCKS
+// Description : None
+#define PSM_FRCE_OFF_CLOCKS_RESET  _u(0x0)
+#define PSM_FRCE_OFF_CLOCKS_BITS   _u(0x00000004)
+#define PSM_FRCE_OFF_CLOCKS_MSB    _u(2)
+#define PSM_FRCE_OFF_CLOCKS_LSB    _u(2)
+#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_XOSC
+// Description : None
+#define PSM_FRCE_OFF_XOSC_RESET  _u(0x0)
+#define PSM_FRCE_OFF_XOSC_BITS   _u(0x00000002)
+#define PSM_FRCE_OFF_XOSC_MSB    _u(1)
+#define PSM_FRCE_OFF_XOSC_LSB    _u(1)
+#define PSM_FRCE_OFF_XOSC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_FRCE_OFF_ROSC
+// Description : None
+#define PSM_FRCE_OFF_ROSC_RESET  _u(0x0)
+#define PSM_FRCE_OFF_ROSC_BITS   _u(0x00000001)
+#define PSM_FRCE_OFF_ROSC_MSB    _u(0)
+#define PSM_FRCE_OFF_ROSC_LSB    _u(0)
+#define PSM_FRCE_OFF_ROSC_ACCESS "RW"
+// =============================================================================
+// Register    : PSM_WDSEL
+// Description : Set to 1 if this peripheral should be reset when the watchdog
+//               fires.
+#define PSM_WDSEL_OFFSET _u(0x00000008)
+#define PSM_WDSEL_BITS   _u(0x0001ffff)
+#define PSM_WDSEL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_PROC1
+// Description : None
+#define PSM_WDSEL_PROC1_RESET  _u(0x0)
+#define PSM_WDSEL_PROC1_BITS   _u(0x00010000)
+#define PSM_WDSEL_PROC1_MSB    _u(16)
+#define PSM_WDSEL_PROC1_LSB    _u(16)
+#define PSM_WDSEL_PROC1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_PROC0
+// Description : None
+#define PSM_WDSEL_PROC0_RESET  _u(0x0)
+#define PSM_WDSEL_PROC0_BITS   _u(0x00008000)
+#define PSM_WDSEL_PROC0_MSB    _u(15)
+#define PSM_WDSEL_PROC0_LSB    _u(15)
+#define PSM_WDSEL_PROC0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_SIO
+// Description : None
+#define PSM_WDSEL_SIO_RESET  _u(0x0)
+#define PSM_WDSEL_SIO_BITS   _u(0x00004000)
+#define PSM_WDSEL_SIO_MSB    _u(14)
+#define PSM_WDSEL_SIO_LSB    _u(14)
+#define PSM_WDSEL_SIO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_VREG_AND_CHIP_RESET
+// Description : None
+#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET  _u(0x0)
+#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS   _u(0x00002000)
+#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB    _u(13)
+#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB    _u(13)
+#define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_XIP
+// Description : None
+#define PSM_WDSEL_XIP_RESET  _u(0x0)
+#define PSM_WDSEL_XIP_BITS   _u(0x00001000)
+#define PSM_WDSEL_XIP_MSB    _u(12)
+#define PSM_WDSEL_XIP_LSB    _u(12)
+#define PSM_WDSEL_XIP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_SRAM5
+// Description : None
+#define PSM_WDSEL_SRAM5_RESET  _u(0x0)
+#define PSM_WDSEL_SRAM5_BITS   _u(0x00000800)
+#define PSM_WDSEL_SRAM5_MSB    _u(11)
+#define PSM_WDSEL_SRAM5_LSB    _u(11)
+#define PSM_WDSEL_SRAM5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_SRAM4
+// Description : None
+#define PSM_WDSEL_SRAM4_RESET  _u(0x0)
+#define PSM_WDSEL_SRAM4_BITS   _u(0x00000400)
+#define PSM_WDSEL_SRAM4_MSB    _u(10)
+#define PSM_WDSEL_SRAM4_LSB    _u(10)
+#define PSM_WDSEL_SRAM4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_SRAM3
+// Description : None
+#define PSM_WDSEL_SRAM3_RESET  _u(0x0)
+#define PSM_WDSEL_SRAM3_BITS   _u(0x00000200)
+#define PSM_WDSEL_SRAM3_MSB    _u(9)
+#define PSM_WDSEL_SRAM3_LSB    _u(9)
+#define PSM_WDSEL_SRAM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_SRAM2
+// Description : None
+#define PSM_WDSEL_SRAM2_RESET  _u(0x0)
+#define PSM_WDSEL_SRAM2_BITS   _u(0x00000100)
+#define PSM_WDSEL_SRAM2_MSB    _u(8)
+#define PSM_WDSEL_SRAM2_LSB    _u(8)
+#define PSM_WDSEL_SRAM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_SRAM1
+// Description : None
+#define PSM_WDSEL_SRAM1_RESET  _u(0x0)
+#define PSM_WDSEL_SRAM1_BITS   _u(0x00000080)
+#define PSM_WDSEL_SRAM1_MSB    _u(7)
+#define PSM_WDSEL_SRAM1_LSB    _u(7)
+#define PSM_WDSEL_SRAM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_SRAM0
+// Description : None
+#define PSM_WDSEL_SRAM0_RESET  _u(0x0)
+#define PSM_WDSEL_SRAM0_BITS   _u(0x00000040)
+#define PSM_WDSEL_SRAM0_MSB    _u(6)
+#define PSM_WDSEL_SRAM0_LSB    _u(6)
+#define PSM_WDSEL_SRAM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_ROM
+// Description : None
+#define PSM_WDSEL_ROM_RESET  _u(0x0)
+#define PSM_WDSEL_ROM_BITS   _u(0x00000020)
+#define PSM_WDSEL_ROM_MSB    _u(5)
+#define PSM_WDSEL_ROM_LSB    _u(5)
+#define PSM_WDSEL_ROM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_BUSFABRIC
+// Description : None
+#define PSM_WDSEL_BUSFABRIC_RESET  _u(0x0)
+#define PSM_WDSEL_BUSFABRIC_BITS   _u(0x00000010)
+#define PSM_WDSEL_BUSFABRIC_MSB    _u(4)
+#define PSM_WDSEL_BUSFABRIC_LSB    _u(4)
+#define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_RESETS
+// Description : None
+#define PSM_WDSEL_RESETS_RESET  _u(0x0)
+#define PSM_WDSEL_RESETS_BITS   _u(0x00000008)
+#define PSM_WDSEL_RESETS_MSB    _u(3)
+#define PSM_WDSEL_RESETS_LSB    _u(3)
+#define PSM_WDSEL_RESETS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_CLOCKS
+// Description : None
+#define PSM_WDSEL_CLOCKS_RESET  _u(0x0)
+#define PSM_WDSEL_CLOCKS_BITS   _u(0x00000004)
+#define PSM_WDSEL_CLOCKS_MSB    _u(2)
+#define PSM_WDSEL_CLOCKS_LSB    _u(2)
+#define PSM_WDSEL_CLOCKS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_XOSC
+// Description : None
+#define PSM_WDSEL_XOSC_RESET  _u(0x0)
+#define PSM_WDSEL_XOSC_BITS   _u(0x00000002)
+#define PSM_WDSEL_XOSC_MSB    _u(1)
+#define PSM_WDSEL_XOSC_LSB    _u(1)
+#define PSM_WDSEL_XOSC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PSM_WDSEL_ROSC
+// Description : None
+#define PSM_WDSEL_ROSC_RESET  _u(0x0)
+#define PSM_WDSEL_ROSC_BITS   _u(0x00000001)
+#define PSM_WDSEL_ROSC_MSB    _u(0)
+#define PSM_WDSEL_ROSC_LSB    _u(0)
+#define PSM_WDSEL_ROSC_ACCESS "RW"
+// =============================================================================
+// Register    : PSM_DONE
+// Description : Indicates the peripheral's registers are ready to access.
+#define PSM_DONE_OFFSET _u(0x0000000c)
+#define PSM_DONE_BITS   _u(0x0001ffff)
+#define PSM_DONE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_PROC1
+// Description : None
+#define PSM_DONE_PROC1_RESET  _u(0x0)
+#define PSM_DONE_PROC1_BITS   _u(0x00010000)
+#define PSM_DONE_PROC1_MSB    _u(16)
+#define PSM_DONE_PROC1_LSB    _u(16)
+#define PSM_DONE_PROC1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_PROC0
+// Description : None
+#define PSM_DONE_PROC0_RESET  _u(0x0)
+#define PSM_DONE_PROC0_BITS   _u(0x00008000)
+#define PSM_DONE_PROC0_MSB    _u(15)
+#define PSM_DONE_PROC0_LSB    _u(15)
+#define PSM_DONE_PROC0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_SIO
+// Description : None
+#define PSM_DONE_SIO_RESET  _u(0x0)
+#define PSM_DONE_SIO_BITS   _u(0x00004000)
+#define PSM_DONE_SIO_MSB    _u(14)
+#define PSM_DONE_SIO_LSB    _u(14)
+#define PSM_DONE_SIO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_VREG_AND_CHIP_RESET
+// Description : None
+#define PSM_DONE_VREG_AND_CHIP_RESET_RESET  _u(0x0)
+#define PSM_DONE_VREG_AND_CHIP_RESET_BITS   _u(0x00002000)
+#define PSM_DONE_VREG_AND_CHIP_RESET_MSB    _u(13)
+#define PSM_DONE_VREG_AND_CHIP_RESET_LSB    _u(13)
+#define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_XIP
+// Description : None
+#define PSM_DONE_XIP_RESET  _u(0x0)
+#define PSM_DONE_XIP_BITS   _u(0x00001000)
+#define PSM_DONE_XIP_MSB    _u(12)
+#define PSM_DONE_XIP_LSB    _u(12)
+#define PSM_DONE_XIP_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_SRAM5
+// Description : None
+#define PSM_DONE_SRAM5_RESET  _u(0x0)
+#define PSM_DONE_SRAM5_BITS   _u(0x00000800)
+#define PSM_DONE_SRAM5_MSB    _u(11)
+#define PSM_DONE_SRAM5_LSB    _u(11)
+#define PSM_DONE_SRAM5_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_SRAM4
+// Description : None
+#define PSM_DONE_SRAM4_RESET  _u(0x0)
+#define PSM_DONE_SRAM4_BITS   _u(0x00000400)
+#define PSM_DONE_SRAM4_MSB    _u(10)
+#define PSM_DONE_SRAM4_LSB    _u(10)
+#define PSM_DONE_SRAM4_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_SRAM3
+// Description : None
+#define PSM_DONE_SRAM3_RESET  _u(0x0)
+#define PSM_DONE_SRAM3_BITS   _u(0x00000200)
+#define PSM_DONE_SRAM3_MSB    _u(9)
+#define PSM_DONE_SRAM3_LSB    _u(9)
+#define PSM_DONE_SRAM3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_SRAM2
+// Description : None
+#define PSM_DONE_SRAM2_RESET  _u(0x0)
+#define PSM_DONE_SRAM2_BITS   _u(0x00000100)
+#define PSM_DONE_SRAM2_MSB    _u(8)
+#define PSM_DONE_SRAM2_LSB    _u(8)
+#define PSM_DONE_SRAM2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_SRAM1
+// Description : None
+#define PSM_DONE_SRAM1_RESET  _u(0x0)
+#define PSM_DONE_SRAM1_BITS   _u(0x00000080)
+#define PSM_DONE_SRAM1_MSB    _u(7)
+#define PSM_DONE_SRAM1_LSB    _u(7)
+#define PSM_DONE_SRAM1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_SRAM0
+// Description : None
+#define PSM_DONE_SRAM0_RESET  _u(0x0)
+#define PSM_DONE_SRAM0_BITS   _u(0x00000040)
+#define PSM_DONE_SRAM0_MSB    _u(6)
+#define PSM_DONE_SRAM0_LSB    _u(6)
+#define PSM_DONE_SRAM0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_ROM
+// Description : None
+#define PSM_DONE_ROM_RESET  _u(0x0)
+#define PSM_DONE_ROM_BITS   _u(0x00000020)
+#define PSM_DONE_ROM_MSB    _u(5)
+#define PSM_DONE_ROM_LSB    _u(5)
+#define PSM_DONE_ROM_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_BUSFABRIC
+// Description : None
+#define PSM_DONE_BUSFABRIC_RESET  _u(0x0)
+#define PSM_DONE_BUSFABRIC_BITS   _u(0x00000010)
+#define PSM_DONE_BUSFABRIC_MSB    _u(4)
+#define PSM_DONE_BUSFABRIC_LSB    _u(4)
+#define PSM_DONE_BUSFABRIC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_RESETS
+// Description : None
+#define PSM_DONE_RESETS_RESET  _u(0x0)
+#define PSM_DONE_RESETS_BITS   _u(0x00000008)
+#define PSM_DONE_RESETS_MSB    _u(3)
+#define PSM_DONE_RESETS_LSB    _u(3)
+#define PSM_DONE_RESETS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_CLOCKS
+// Description : None
+#define PSM_DONE_CLOCKS_RESET  _u(0x0)
+#define PSM_DONE_CLOCKS_BITS   _u(0x00000004)
+#define PSM_DONE_CLOCKS_MSB    _u(2)
+#define PSM_DONE_CLOCKS_LSB    _u(2)
+#define PSM_DONE_CLOCKS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_XOSC
+// Description : None
+#define PSM_DONE_XOSC_RESET  _u(0x0)
+#define PSM_DONE_XOSC_BITS   _u(0x00000002)
+#define PSM_DONE_XOSC_MSB    _u(1)
+#define PSM_DONE_XOSC_LSB    _u(1)
+#define PSM_DONE_XOSC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PSM_DONE_ROSC
+// Description : None
+#define PSM_DONE_ROSC_RESET  _u(0x0)
+#define PSM_DONE_ROSC_BITS   _u(0x00000001)
+#define PSM_DONE_ROSC_MSB    _u(0)
+#define PSM_DONE_ROSC_LSB    _u(0)
+#define PSM_DONE_ROSC_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_PSM_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pwm.h b/src/rp2040/hardware_regs/include/hardware/regs/pwm.h
new file mode 100644
index 0000000..a853597
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/pwm.h
@@ -0,0 +1,1505 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : PWM
+// Version        : 1
+// Bus type       : apb
+// Description    : Simple PWM
+// =============================================================================
+#ifndef HARDWARE_REGS_PWM_DEFINED
+#define HARDWARE_REGS_PWM_DEFINED
+// =============================================================================
+// Register    : PWM_CH0_CSR
+// Description : Control and status register
+#define PWM_CH0_CSR_OFFSET _u(0x00000000)
+#define PWM_CH0_CSR_BITS   _u(0x000000ff)
+#define PWM_CH0_CSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH0_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running
+//               at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH0_CSR_PH_ADV_RESET  _u(0x0)
+#define PWM_CH0_CSR_PH_ADV_BITS   _u(0x00000080)
+#define PWM_CH0_CSR_PH_ADV_MSB    _u(7)
+#define PWM_CH0_CSR_PH_ADV_LSB    _u(7)
+#define PWM_CH0_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH0_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running.
+#define PWM_CH0_CSR_PH_RET_RESET  _u(0x0)
+#define PWM_CH0_CSR_PH_RET_BITS   _u(0x00000040)
+#define PWM_CH0_CSR_PH_RET_MSB    _u(6)
+#define PWM_CH0_CSR_PH_RET_LSB    _u(6)
+#define PWM_CH0_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH0_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+//               divider
+//               0x1 -> Fractional divider operation is gated by the PWM B pin.
+//               0x2 -> Counter advances with each rising edge of the PWM B pin.
+//               0x3 -> Counter advances with each falling edge of the PWM B
+//               pin.
+#define PWM_CH0_CSR_DIVMODE_RESET       _u(0x0)
+#define PWM_CH0_CSR_DIVMODE_BITS        _u(0x00000030)
+#define PWM_CH0_CSR_DIVMODE_MSB         _u(5)
+#define PWM_CH0_CSR_DIVMODE_LSB         _u(4)
+#define PWM_CH0_CSR_DIVMODE_ACCESS      "RW"
+#define PWM_CH0_CSR_DIVMODE_VALUE_DIV   _u(0x0)
+#define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH0_CSR_DIVMODE_VALUE_RISE  _u(0x2)
+#define PWM_CH0_CSR_DIVMODE_VALUE_FALL  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH0_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH0_CSR_B_INV_RESET  _u(0x0)
+#define PWM_CH0_CSR_B_INV_BITS   _u(0x00000008)
+#define PWM_CH0_CSR_B_INV_MSB    _u(3)
+#define PWM_CH0_CSR_B_INV_LSB    _u(3)
+#define PWM_CH0_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH0_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH0_CSR_A_INV_RESET  _u(0x0)
+#define PWM_CH0_CSR_A_INV_BITS   _u(0x00000004)
+#define PWM_CH0_CSR_A_INV_MSB    _u(2)
+#define PWM_CH0_CSR_A_INV_LSB    _u(2)
+#define PWM_CH0_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH0_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH0_CSR_PH_CORRECT_RESET  _u(0x0)
+#define PWM_CH0_CSR_PH_CORRECT_BITS   _u(0x00000002)
+#define PWM_CH0_CSR_PH_CORRECT_MSB    _u(1)
+#define PWM_CH0_CSR_PH_CORRECT_LSB    _u(1)
+#define PWM_CH0_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH0_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH0_CSR_EN_RESET  _u(0x0)
+#define PWM_CH0_CSR_EN_BITS   _u(0x00000001)
+#define PWM_CH0_CSR_EN_MSB    _u(0)
+#define PWM_CH0_CSR_EN_LSB    _u(0)
+#define PWM_CH0_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH0_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+//               Counting rate is system clock frequency divided by this number.
+//               Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH0_DIV_OFFSET _u(0x00000004)
+#define PWM_CH0_DIV_BITS   _u(0x00000fff)
+#define PWM_CH0_DIV_RESET  _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH0_DIV_INT
+// Description : None
+#define PWM_CH0_DIV_INT_RESET  _u(0x01)
+#define PWM_CH0_DIV_INT_BITS   _u(0x00000ff0)
+#define PWM_CH0_DIV_INT_MSB    _u(11)
+#define PWM_CH0_DIV_INT_LSB    _u(4)
+#define PWM_CH0_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH0_DIV_FRAC
+// Description : None
+#define PWM_CH0_DIV_FRAC_RESET  _u(0x0)
+#define PWM_CH0_DIV_FRAC_BITS   _u(0x0000000f)
+#define PWM_CH0_DIV_FRAC_MSB    _u(3)
+#define PWM_CH0_DIV_FRAC_LSB    _u(0)
+#define PWM_CH0_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH0_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH0_CTR_OFFSET _u(0x00000008)
+#define PWM_CH0_CTR_BITS   _u(0x0000ffff)
+#define PWM_CH0_CTR_RESET  _u(0x00000000)
+#define PWM_CH0_CTR_MSB    _u(15)
+#define PWM_CH0_CTR_LSB    _u(0)
+#define PWM_CH0_CTR_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH0_CC
+// Description : Counter compare values
+#define PWM_CH0_CC_OFFSET _u(0x0000000c)
+#define PWM_CH0_CC_BITS   _u(0xffffffff)
+#define PWM_CH0_CC_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH0_CC_B
+// Description : None
+#define PWM_CH0_CC_B_RESET  _u(0x0000)
+#define PWM_CH0_CC_B_BITS   _u(0xffff0000)
+#define PWM_CH0_CC_B_MSB    _u(31)
+#define PWM_CH0_CC_B_LSB    _u(16)
+#define PWM_CH0_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH0_CC_A
+// Description : None
+#define PWM_CH0_CC_A_RESET  _u(0x0000)
+#define PWM_CH0_CC_A_BITS   _u(0x0000ffff)
+#define PWM_CH0_CC_A_MSB    _u(15)
+#define PWM_CH0_CC_A_LSB    _u(0)
+#define PWM_CH0_CC_A_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH0_TOP
+// Description : Counter wrap value
+#define PWM_CH0_TOP_OFFSET _u(0x00000010)
+#define PWM_CH0_TOP_BITS   _u(0x0000ffff)
+#define PWM_CH0_TOP_RESET  _u(0x0000ffff)
+#define PWM_CH0_TOP_MSB    _u(15)
+#define PWM_CH0_TOP_LSB    _u(0)
+#define PWM_CH0_TOP_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH1_CSR
+// Description : Control and status register
+#define PWM_CH1_CSR_OFFSET _u(0x00000014)
+#define PWM_CH1_CSR_BITS   _u(0x000000ff)
+#define PWM_CH1_CSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH1_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running
+//               at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH1_CSR_PH_ADV_RESET  _u(0x0)
+#define PWM_CH1_CSR_PH_ADV_BITS   _u(0x00000080)
+#define PWM_CH1_CSR_PH_ADV_MSB    _u(7)
+#define PWM_CH1_CSR_PH_ADV_LSB    _u(7)
+#define PWM_CH1_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH1_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running.
+#define PWM_CH1_CSR_PH_RET_RESET  _u(0x0)
+#define PWM_CH1_CSR_PH_RET_BITS   _u(0x00000040)
+#define PWM_CH1_CSR_PH_RET_MSB    _u(6)
+#define PWM_CH1_CSR_PH_RET_LSB    _u(6)
+#define PWM_CH1_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH1_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+//               divider
+//               0x1 -> Fractional divider operation is gated by the PWM B pin.
+//               0x2 -> Counter advances with each rising edge of the PWM B pin.
+//               0x3 -> Counter advances with each falling edge of the PWM B
+//               pin.
+#define PWM_CH1_CSR_DIVMODE_RESET       _u(0x0)
+#define PWM_CH1_CSR_DIVMODE_BITS        _u(0x00000030)
+#define PWM_CH1_CSR_DIVMODE_MSB         _u(5)
+#define PWM_CH1_CSR_DIVMODE_LSB         _u(4)
+#define PWM_CH1_CSR_DIVMODE_ACCESS      "RW"
+#define PWM_CH1_CSR_DIVMODE_VALUE_DIV   _u(0x0)
+#define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH1_CSR_DIVMODE_VALUE_RISE  _u(0x2)
+#define PWM_CH1_CSR_DIVMODE_VALUE_FALL  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH1_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH1_CSR_B_INV_RESET  _u(0x0)
+#define PWM_CH1_CSR_B_INV_BITS   _u(0x00000008)
+#define PWM_CH1_CSR_B_INV_MSB    _u(3)
+#define PWM_CH1_CSR_B_INV_LSB    _u(3)
+#define PWM_CH1_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH1_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH1_CSR_A_INV_RESET  _u(0x0)
+#define PWM_CH1_CSR_A_INV_BITS   _u(0x00000004)
+#define PWM_CH1_CSR_A_INV_MSB    _u(2)
+#define PWM_CH1_CSR_A_INV_LSB    _u(2)
+#define PWM_CH1_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH1_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH1_CSR_PH_CORRECT_RESET  _u(0x0)
+#define PWM_CH1_CSR_PH_CORRECT_BITS   _u(0x00000002)
+#define PWM_CH1_CSR_PH_CORRECT_MSB    _u(1)
+#define PWM_CH1_CSR_PH_CORRECT_LSB    _u(1)
+#define PWM_CH1_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH1_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH1_CSR_EN_RESET  _u(0x0)
+#define PWM_CH1_CSR_EN_BITS   _u(0x00000001)
+#define PWM_CH1_CSR_EN_MSB    _u(0)
+#define PWM_CH1_CSR_EN_LSB    _u(0)
+#define PWM_CH1_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH1_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+//               Counting rate is system clock frequency divided by this number.
+//               Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH1_DIV_OFFSET _u(0x00000018)
+#define PWM_CH1_DIV_BITS   _u(0x00000fff)
+#define PWM_CH1_DIV_RESET  _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH1_DIV_INT
+// Description : None
+#define PWM_CH1_DIV_INT_RESET  _u(0x01)
+#define PWM_CH1_DIV_INT_BITS   _u(0x00000ff0)
+#define PWM_CH1_DIV_INT_MSB    _u(11)
+#define PWM_CH1_DIV_INT_LSB    _u(4)
+#define PWM_CH1_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH1_DIV_FRAC
+// Description : None
+#define PWM_CH1_DIV_FRAC_RESET  _u(0x0)
+#define PWM_CH1_DIV_FRAC_BITS   _u(0x0000000f)
+#define PWM_CH1_DIV_FRAC_MSB    _u(3)
+#define PWM_CH1_DIV_FRAC_LSB    _u(0)
+#define PWM_CH1_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH1_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH1_CTR_OFFSET _u(0x0000001c)
+#define PWM_CH1_CTR_BITS   _u(0x0000ffff)
+#define PWM_CH1_CTR_RESET  _u(0x00000000)
+#define PWM_CH1_CTR_MSB    _u(15)
+#define PWM_CH1_CTR_LSB    _u(0)
+#define PWM_CH1_CTR_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH1_CC
+// Description : Counter compare values
+#define PWM_CH1_CC_OFFSET _u(0x00000020)
+#define PWM_CH1_CC_BITS   _u(0xffffffff)
+#define PWM_CH1_CC_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH1_CC_B
+// Description : None
+#define PWM_CH1_CC_B_RESET  _u(0x0000)
+#define PWM_CH1_CC_B_BITS   _u(0xffff0000)
+#define PWM_CH1_CC_B_MSB    _u(31)
+#define PWM_CH1_CC_B_LSB    _u(16)
+#define PWM_CH1_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH1_CC_A
+// Description : None
+#define PWM_CH1_CC_A_RESET  _u(0x0000)
+#define PWM_CH1_CC_A_BITS   _u(0x0000ffff)
+#define PWM_CH1_CC_A_MSB    _u(15)
+#define PWM_CH1_CC_A_LSB    _u(0)
+#define PWM_CH1_CC_A_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH1_TOP
+// Description : Counter wrap value
+#define PWM_CH1_TOP_OFFSET _u(0x00000024)
+#define PWM_CH1_TOP_BITS   _u(0x0000ffff)
+#define PWM_CH1_TOP_RESET  _u(0x0000ffff)
+#define PWM_CH1_TOP_MSB    _u(15)
+#define PWM_CH1_TOP_LSB    _u(0)
+#define PWM_CH1_TOP_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH2_CSR
+// Description : Control and status register
+#define PWM_CH2_CSR_OFFSET _u(0x00000028)
+#define PWM_CH2_CSR_BITS   _u(0x000000ff)
+#define PWM_CH2_CSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH2_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running
+//               at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH2_CSR_PH_ADV_RESET  _u(0x0)
+#define PWM_CH2_CSR_PH_ADV_BITS   _u(0x00000080)
+#define PWM_CH2_CSR_PH_ADV_MSB    _u(7)
+#define PWM_CH2_CSR_PH_ADV_LSB    _u(7)
+#define PWM_CH2_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH2_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running.
+#define PWM_CH2_CSR_PH_RET_RESET  _u(0x0)
+#define PWM_CH2_CSR_PH_RET_BITS   _u(0x00000040)
+#define PWM_CH2_CSR_PH_RET_MSB    _u(6)
+#define PWM_CH2_CSR_PH_RET_LSB    _u(6)
+#define PWM_CH2_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH2_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+//               divider
+//               0x1 -> Fractional divider operation is gated by the PWM B pin.
+//               0x2 -> Counter advances with each rising edge of the PWM B pin.
+//               0x3 -> Counter advances with each falling edge of the PWM B
+//               pin.
+#define PWM_CH2_CSR_DIVMODE_RESET       _u(0x0)
+#define PWM_CH2_CSR_DIVMODE_BITS        _u(0x00000030)
+#define PWM_CH2_CSR_DIVMODE_MSB         _u(5)
+#define PWM_CH2_CSR_DIVMODE_LSB         _u(4)
+#define PWM_CH2_CSR_DIVMODE_ACCESS      "RW"
+#define PWM_CH2_CSR_DIVMODE_VALUE_DIV   _u(0x0)
+#define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH2_CSR_DIVMODE_VALUE_RISE  _u(0x2)
+#define PWM_CH2_CSR_DIVMODE_VALUE_FALL  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH2_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH2_CSR_B_INV_RESET  _u(0x0)
+#define PWM_CH2_CSR_B_INV_BITS   _u(0x00000008)
+#define PWM_CH2_CSR_B_INV_MSB    _u(3)
+#define PWM_CH2_CSR_B_INV_LSB    _u(3)
+#define PWM_CH2_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH2_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH2_CSR_A_INV_RESET  _u(0x0)
+#define PWM_CH2_CSR_A_INV_BITS   _u(0x00000004)
+#define PWM_CH2_CSR_A_INV_MSB    _u(2)
+#define PWM_CH2_CSR_A_INV_LSB    _u(2)
+#define PWM_CH2_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH2_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH2_CSR_PH_CORRECT_RESET  _u(0x0)
+#define PWM_CH2_CSR_PH_CORRECT_BITS   _u(0x00000002)
+#define PWM_CH2_CSR_PH_CORRECT_MSB    _u(1)
+#define PWM_CH2_CSR_PH_CORRECT_LSB    _u(1)
+#define PWM_CH2_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH2_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH2_CSR_EN_RESET  _u(0x0)
+#define PWM_CH2_CSR_EN_BITS   _u(0x00000001)
+#define PWM_CH2_CSR_EN_MSB    _u(0)
+#define PWM_CH2_CSR_EN_LSB    _u(0)
+#define PWM_CH2_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH2_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+//               Counting rate is system clock frequency divided by this number.
+//               Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH2_DIV_OFFSET _u(0x0000002c)
+#define PWM_CH2_DIV_BITS   _u(0x00000fff)
+#define PWM_CH2_DIV_RESET  _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH2_DIV_INT
+// Description : None
+#define PWM_CH2_DIV_INT_RESET  _u(0x01)
+#define PWM_CH2_DIV_INT_BITS   _u(0x00000ff0)
+#define PWM_CH2_DIV_INT_MSB    _u(11)
+#define PWM_CH2_DIV_INT_LSB    _u(4)
+#define PWM_CH2_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH2_DIV_FRAC
+// Description : None
+#define PWM_CH2_DIV_FRAC_RESET  _u(0x0)
+#define PWM_CH2_DIV_FRAC_BITS   _u(0x0000000f)
+#define PWM_CH2_DIV_FRAC_MSB    _u(3)
+#define PWM_CH2_DIV_FRAC_LSB    _u(0)
+#define PWM_CH2_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH2_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH2_CTR_OFFSET _u(0x00000030)
+#define PWM_CH2_CTR_BITS   _u(0x0000ffff)
+#define PWM_CH2_CTR_RESET  _u(0x00000000)
+#define PWM_CH2_CTR_MSB    _u(15)
+#define PWM_CH2_CTR_LSB    _u(0)
+#define PWM_CH2_CTR_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH2_CC
+// Description : Counter compare values
+#define PWM_CH2_CC_OFFSET _u(0x00000034)
+#define PWM_CH2_CC_BITS   _u(0xffffffff)
+#define PWM_CH2_CC_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH2_CC_B
+// Description : None
+#define PWM_CH2_CC_B_RESET  _u(0x0000)
+#define PWM_CH2_CC_B_BITS   _u(0xffff0000)
+#define PWM_CH2_CC_B_MSB    _u(31)
+#define PWM_CH2_CC_B_LSB    _u(16)
+#define PWM_CH2_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH2_CC_A
+// Description : None
+#define PWM_CH2_CC_A_RESET  _u(0x0000)
+#define PWM_CH2_CC_A_BITS   _u(0x0000ffff)
+#define PWM_CH2_CC_A_MSB    _u(15)
+#define PWM_CH2_CC_A_LSB    _u(0)
+#define PWM_CH2_CC_A_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH2_TOP
+// Description : Counter wrap value
+#define PWM_CH2_TOP_OFFSET _u(0x00000038)
+#define PWM_CH2_TOP_BITS   _u(0x0000ffff)
+#define PWM_CH2_TOP_RESET  _u(0x0000ffff)
+#define PWM_CH2_TOP_MSB    _u(15)
+#define PWM_CH2_TOP_LSB    _u(0)
+#define PWM_CH2_TOP_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH3_CSR
+// Description : Control and status register
+#define PWM_CH3_CSR_OFFSET _u(0x0000003c)
+#define PWM_CH3_CSR_BITS   _u(0x000000ff)
+#define PWM_CH3_CSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH3_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running
+//               at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH3_CSR_PH_ADV_RESET  _u(0x0)
+#define PWM_CH3_CSR_PH_ADV_BITS   _u(0x00000080)
+#define PWM_CH3_CSR_PH_ADV_MSB    _u(7)
+#define PWM_CH3_CSR_PH_ADV_LSB    _u(7)
+#define PWM_CH3_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH3_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running.
+#define PWM_CH3_CSR_PH_RET_RESET  _u(0x0)
+#define PWM_CH3_CSR_PH_RET_BITS   _u(0x00000040)
+#define PWM_CH3_CSR_PH_RET_MSB    _u(6)
+#define PWM_CH3_CSR_PH_RET_LSB    _u(6)
+#define PWM_CH3_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH3_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+//               divider
+//               0x1 -> Fractional divider operation is gated by the PWM B pin.
+//               0x2 -> Counter advances with each rising edge of the PWM B pin.
+//               0x3 -> Counter advances with each falling edge of the PWM B
+//               pin.
+#define PWM_CH3_CSR_DIVMODE_RESET       _u(0x0)
+#define PWM_CH3_CSR_DIVMODE_BITS        _u(0x00000030)
+#define PWM_CH3_CSR_DIVMODE_MSB         _u(5)
+#define PWM_CH3_CSR_DIVMODE_LSB         _u(4)
+#define PWM_CH3_CSR_DIVMODE_ACCESS      "RW"
+#define PWM_CH3_CSR_DIVMODE_VALUE_DIV   _u(0x0)
+#define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH3_CSR_DIVMODE_VALUE_RISE  _u(0x2)
+#define PWM_CH3_CSR_DIVMODE_VALUE_FALL  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH3_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH3_CSR_B_INV_RESET  _u(0x0)
+#define PWM_CH3_CSR_B_INV_BITS   _u(0x00000008)
+#define PWM_CH3_CSR_B_INV_MSB    _u(3)
+#define PWM_CH3_CSR_B_INV_LSB    _u(3)
+#define PWM_CH3_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH3_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH3_CSR_A_INV_RESET  _u(0x0)
+#define PWM_CH3_CSR_A_INV_BITS   _u(0x00000004)
+#define PWM_CH3_CSR_A_INV_MSB    _u(2)
+#define PWM_CH3_CSR_A_INV_LSB    _u(2)
+#define PWM_CH3_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH3_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH3_CSR_PH_CORRECT_RESET  _u(0x0)
+#define PWM_CH3_CSR_PH_CORRECT_BITS   _u(0x00000002)
+#define PWM_CH3_CSR_PH_CORRECT_MSB    _u(1)
+#define PWM_CH3_CSR_PH_CORRECT_LSB    _u(1)
+#define PWM_CH3_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH3_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH3_CSR_EN_RESET  _u(0x0)
+#define PWM_CH3_CSR_EN_BITS   _u(0x00000001)
+#define PWM_CH3_CSR_EN_MSB    _u(0)
+#define PWM_CH3_CSR_EN_LSB    _u(0)
+#define PWM_CH3_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH3_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+//               Counting rate is system clock frequency divided by this number.
+//               Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH3_DIV_OFFSET _u(0x00000040)
+#define PWM_CH3_DIV_BITS   _u(0x00000fff)
+#define PWM_CH3_DIV_RESET  _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH3_DIV_INT
+// Description : None
+#define PWM_CH3_DIV_INT_RESET  _u(0x01)
+#define PWM_CH3_DIV_INT_BITS   _u(0x00000ff0)
+#define PWM_CH3_DIV_INT_MSB    _u(11)
+#define PWM_CH3_DIV_INT_LSB    _u(4)
+#define PWM_CH3_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH3_DIV_FRAC
+// Description : None
+#define PWM_CH3_DIV_FRAC_RESET  _u(0x0)
+#define PWM_CH3_DIV_FRAC_BITS   _u(0x0000000f)
+#define PWM_CH3_DIV_FRAC_MSB    _u(3)
+#define PWM_CH3_DIV_FRAC_LSB    _u(0)
+#define PWM_CH3_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH3_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH3_CTR_OFFSET _u(0x00000044)
+#define PWM_CH3_CTR_BITS   _u(0x0000ffff)
+#define PWM_CH3_CTR_RESET  _u(0x00000000)
+#define PWM_CH3_CTR_MSB    _u(15)
+#define PWM_CH3_CTR_LSB    _u(0)
+#define PWM_CH3_CTR_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH3_CC
+// Description : Counter compare values
+#define PWM_CH3_CC_OFFSET _u(0x00000048)
+#define PWM_CH3_CC_BITS   _u(0xffffffff)
+#define PWM_CH3_CC_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH3_CC_B
+// Description : None
+#define PWM_CH3_CC_B_RESET  _u(0x0000)
+#define PWM_CH3_CC_B_BITS   _u(0xffff0000)
+#define PWM_CH3_CC_B_MSB    _u(31)
+#define PWM_CH3_CC_B_LSB    _u(16)
+#define PWM_CH3_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH3_CC_A
+// Description : None
+#define PWM_CH3_CC_A_RESET  _u(0x0000)
+#define PWM_CH3_CC_A_BITS   _u(0x0000ffff)
+#define PWM_CH3_CC_A_MSB    _u(15)
+#define PWM_CH3_CC_A_LSB    _u(0)
+#define PWM_CH3_CC_A_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH3_TOP
+// Description : Counter wrap value
+#define PWM_CH3_TOP_OFFSET _u(0x0000004c)
+#define PWM_CH3_TOP_BITS   _u(0x0000ffff)
+#define PWM_CH3_TOP_RESET  _u(0x0000ffff)
+#define PWM_CH3_TOP_MSB    _u(15)
+#define PWM_CH3_TOP_LSB    _u(0)
+#define PWM_CH3_TOP_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH4_CSR
+// Description : Control and status register
+#define PWM_CH4_CSR_OFFSET _u(0x00000050)
+#define PWM_CH4_CSR_BITS   _u(0x000000ff)
+#define PWM_CH4_CSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH4_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running
+//               at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH4_CSR_PH_ADV_RESET  _u(0x0)
+#define PWM_CH4_CSR_PH_ADV_BITS   _u(0x00000080)
+#define PWM_CH4_CSR_PH_ADV_MSB    _u(7)
+#define PWM_CH4_CSR_PH_ADV_LSB    _u(7)
+#define PWM_CH4_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH4_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running.
+#define PWM_CH4_CSR_PH_RET_RESET  _u(0x0)
+#define PWM_CH4_CSR_PH_RET_BITS   _u(0x00000040)
+#define PWM_CH4_CSR_PH_RET_MSB    _u(6)
+#define PWM_CH4_CSR_PH_RET_LSB    _u(6)
+#define PWM_CH4_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH4_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+//               divider
+//               0x1 -> Fractional divider operation is gated by the PWM B pin.
+//               0x2 -> Counter advances with each rising edge of the PWM B pin.
+//               0x3 -> Counter advances with each falling edge of the PWM B
+//               pin.
+#define PWM_CH4_CSR_DIVMODE_RESET       _u(0x0)
+#define PWM_CH4_CSR_DIVMODE_BITS        _u(0x00000030)
+#define PWM_CH4_CSR_DIVMODE_MSB         _u(5)
+#define PWM_CH4_CSR_DIVMODE_LSB         _u(4)
+#define PWM_CH4_CSR_DIVMODE_ACCESS      "RW"
+#define PWM_CH4_CSR_DIVMODE_VALUE_DIV   _u(0x0)
+#define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH4_CSR_DIVMODE_VALUE_RISE  _u(0x2)
+#define PWM_CH4_CSR_DIVMODE_VALUE_FALL  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH4_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH4_CSR_B_INV_RESET  _u(0x0)
+#define PWM_CH4_CSR_B_INV_BITS   _u(0x00000008)
+#define PWM_CH4_CSR_B_INV_MSB    _u(3)
+#define PWM_CH4_CSR_B_INV_LSB    _u(3)
+#define PWM_CH4_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH4_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH4_CSR_A_INV_RESET  _u(0x0)
+#define PWM_CH4_CSR_A_INV_BITS   _u(0x00000004)
+#define PWM_CH4_CSR_A_INV_MSB    _u(2)
+#define PWM_CH4_CSR_A_INV_LSB    _u(2)
+#define PWM_CH4_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH4_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH4_CSR_PH_CORRECT_RESET  _u(0x0)
+#define PWM_CH4_CSR_PH_CORRECT_BITS   _u(0x00000002)
+#define PWM_CH4_CSR_PH_CORRECT_MSB    _u(1)
+#define PWM_CH4_CSR_PH_CORRECT_LSB    _u(1)
+#define PWM_CH4_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH4_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH4_CSR_EN_RESET  _u(0x0)
+#define PWM_CH4_CSR_EN_BITS   _u(0x00000001)
+#define PWM_CH4_CSR_EN_MSB    _u(0)
+#define PWM_CH4_CSR_EN_LSB    _u(0)
+#define PWM_CH4_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH4_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+//               Counting rate is system clock frequency divided by this number.
+//               Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH4_DIV_OFFSET _u(0x00000054)
+#define PWM_CH4_DIV_BITS   _u(0x00000fff)
+#define PWM_CH4_DIV_RESET  _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH4_DIV_INT
+// Description : None
+#define PWM_CH4_DIV_INT_RESET  _u(0x01)
+#define PWM_CH4_DIV_INT_BITS   _u(0x00000ff0)
+#define PWM_CH4_DIV_INT_MSB    _u(11)
+#define PWM_CH4_DIV_INT_LSB    _u(4)
+#define PWM_CH4_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH4_DIV_FRAC
+// Description : None
+#define PWM_CH4_DIV_FRAC_RESET  _u(0x0)
+#define PWM_CH4_DIV_FRAC_BITS   _u(0x0000000f)
+#define PWM_CH4_DIV_FRAC_MSB    _u(3)
+#define PWM_CH4_DIV_FRAC_LSB    _u(0)
+#define PWM_CH4_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH4_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH4_CTR_OFFSET _u(0x00000058)
+#define PWM_CH4_CTR_BITS   _u(0x0000ffff)
+#define PWM_CH4_CTR_RESET  _u(0x00000000)
+#define PWM_CH4_CTR_MSB    _u(15)
+#define PWM_CH4_CTR_LSB    _u(0)
+#define PWM_CH4_CTR_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH4_CC
+// Description : Counter compare values
+#define PWM_CH4_CC_OFFSET _u(0x0000005c)
+#define PWM_CH4_CC_BITS   _u(0xffffffff)
+#define PWM_CH4_CC_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH4_CC_B
+// Description : None
+#define PWM_CH4_CC_B_RESET  _u(0x0000)
+#define PWM_CH4_CC_B_BITS   _u(0xffff0000)
+#define PWM_CH4_CC_B_MSB    _u(31)
+#define PWM_CH4_CC_B_LSB    _u(16)
+#define PWM_CH4_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH4_CC_A
+// Description : None
+#define PWM_CH4_CC_A_RESET  _u(0x0000)
+#define PWM_CH4_CC_A_BITS   _u(0x0000ffff)
+#define PWM_CH4_CC_A_MSB    _u(15)
+#define PWM_CH4_CC_A_LSB    _u(0)
+#define PWM_CH4_CC_A_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH4_TOP
+// Description : Counter wrap value
+#define PWM_CH4_TOP_OFFSET _u(0x00000060)
+#define PWM_CH4_TOP_BITS   _u(0x0000ffff)
+#define PWM_CH4_TOP_RESET  _u(0x0000ffff)
+#define PWM_CH4_TOP_MSB    _u(15)
+#define PWM_CH4_TOP_LSB    _u(0)
+#define PWM_CH4_TOP_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH5_CSR
+// Description : Control and status register
+#define PWM_CH5_CSR_OFFSET _u(0x00000064)
+#define PWM_CH5_CSR_BITS   _u(0x000000ff)
+#define PWM_CH5_CSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH5_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running
+//               at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH5_CSR_PH_ADV_RESET  _u(0x0)
+#define PWM_CH5_CSR_PH_ADV_BITS   _u(0x00000080)
+#define PWM_CH5_CSR_PH_ADV_MSB    _u(7)
+#define PWM_CH5_CSR_PH_ADV_LSB    _u(7)
+#define PWM_CH5_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH5_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running.
+#define PWM_CH5_CSR_PH_RET_RESET  _u(0x0)
+#define PWM_CH5_CSR_PH_RET_BITS   _u(0x00000040)
+#define PWM_CH5_CSR_PH_RET_MSB    _u(6)
+#define PWM_CH5_CSR_PH_RET_LSB    _u(6)
+#define PWM_CH5_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH5_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+//               divider
+//               0x1 -> Fractional divider operation is gated by the PWM B pin.
+//               0x2 -> Counter advances with each rising edge of the PWM B pin.
+//               0x3 -> Counter advances with each falling edge of the PWM B
+//               pin.
+#define PWM_CH5_CSR_DIVMODE_RESET       _u(0x0)
+#define PWM_CH5_CSR_DIVMODE_BITS        _u(0x00000030)
+#define PWM_CH5_CSR_DIVMODE_MSB         _u(5)
+#define PWM_CH5_CSR_DIVMODE_LSB         _u(4)
+#define PWM_CH5_CSR_DIVMODE_ACCESS      "RW"
+#define PWM_CH5_CSR_DIVMODE_VALUE_DIV   _u(0x0)
+#define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH5_CSR_DIVMODE_VALUE_RISE  _u(0x2)
+#define PWM_CH5_CSR_DIVMODE_VALUE_FALL  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH5_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH5_CSR_B_INV_RESET  _u(0x0)
+#define PWM_CH5_CSR_B_INV_BITS   _u(0x00000008)
+#define PWM_CH5_CSR_B_INV_MSB    _u(3)
+#define PWM_CH5_CSR_B_INV_LSB    _u(3)
+#define PWM_CH5_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH5_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH5_CSR_A_INV_RESET  _u(0x0)
+#define PWM_CH5_CSR_A_INV_BITS   _u(0x00000004)
+#define PWM_CH5_CSR_A_INV_MSB    _u(2)
+#define PWM_CH5_CSR_A_INV_LSB    _u(2)
+#define PWM_CH5_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH5_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH5_CSR_PH_CORRECT_RESET  _u(0x0)
+#define PWM_CH5_CSR_PH_CORRECT_BITS   _u(0x00000002)
+#define PWM_CH5_CSR_PH_CORRECT_MSB    _u(1)
+#define PWM_CH5_CSR_PH_CORRECT_LSB    _u(1)
+#define PWM_CH5_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH5_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH5_CSR_EN_RESET  _u(0x0)
+#define PWM_CH5_CSR_EN_BITS   _u(0x00000001)
+#define PWM_CH5_CSR_EN_MSB    _u(0)
+#define PWM_CH5_CSR_EN_LSB    _u(0)
+#define PWM_CH5_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH5_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+//               Counting rate is system clock frequency divided by this number.
+//               Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH5_DIV_OFFSET _u(0x00000068)
+#define PWM_CH5_DIV_BITS   _u(0x00000fff)
+#define PWM_CH5_DIV_RESET  _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH5_DIV_INT
+// Description : None
+#define PWM_CH5_DIV_INT_RESET  _u(0x01)
+#define PWM_CH5_DIV_INT_BITS   _u(0x00000ff0)
+#define PWM_CH5_DIV_INT_MSB    _u(11)
+#define PWM_CH5_DIV_INT_LSB    _u(4)
+#define PWM_CH5_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH5_DIV_FRAC
+// Description : None
+#define PWM_CH5_DIV_FRAC_RESET  _u(0x0)
+#define PWM_CH5_DIV_FRAC_BITS   _u(0x0000000f)
+#define PWM_CH5_DIV_FRAC_MSB    _u(3)
+#define PWM_CH5_DIV_FRAC_LSB    _u(0)
+#define PWM_CH5_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH5_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH5_CTR_OFFSET _u(0x0000006c)
+#define PWM_CH5_CTR_BITS   _u(0x0000ffff)
+#define PWM_CH5_CTR_RESET  _u(0x00000000)
+#define PWM_CH5_CTR_MSB    _u(15)
+#define PWM_CH5_CTR_LSB    _u(0)
+#define PWM_CH5_CTR_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH5_CC
+// Description : Counter compare values
+#define PWM_CH5_CC_OFFSET _u(0x00000070)
+#define PWM_CH5_CC_BITS   _u(0xffffffff)
+#define PWM_CH5_CC_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH5_CC_B
+// Description : None
+#define PWM_CH5_CC_B_RESET  _u(0x0000)
+#define PWM_CH5_CC_B_BITS   _u(0xffff0000)
+#define PWM_CH5_CC_B_MSB    _u(31)
+#define PWM_CH5_CC_B_LSB    _u(16)
+#define PWM_CH5_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH5_CC_A
+// Description : None
+#define PWM_CH5_CC_A_RESET  _u(0x0000)
+#define PWM_CH5_CC_A_BITS   _u(0x0000ffff)
+#define PWM_CH5_CC_A_MSB    _u(15)
+#define PWM_CH5_CC_A_LSB    _u(0)
+#define PWM_CH5_CC_A_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH5_TOP
+// Description : Counter wrap value
+#define PWM_CH5_TOP_OFFSET _u(0x00000074)
+#define PWM_CH5_TOP_BITS   _u(0x0000ffff)
+#define PWM_CH5_TOP_RESET  _u(0x0000ffff)
+#define PWM_CH5_TOP_MSB    _u(15)
+#define PWM_CH5_TOP_LSB    _u(0)
+#define PWM_CH5_TOP_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH6_CSR
+// Description : Control and status register
+#define PWM_CH6_CSR_OFFSET _u(0x00000078)
+#define PWM_CH6_CSR_BITS   _u(0x000000ff)
+#define PWM_CH6_CSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH6_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running
+//               at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH6_CSR_PH_ADV_RESET  _u(0x0)
+#define PWM_CH6_CSR_PH_ADV_BITS   _u(0x00000080)
+#define PWM_CH6_CSR_PH_ADV_MSB    _u(7)
+#define PWM_CH6_CSR_PH_ADV_LSB    _u(7)
+#define PWM_CH6_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH6_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running.
+#define PWM_CH6_CSR_PH_RET_RESET  _u(0x0)
+#define PWM_CH6_CSR_PH_RET_BITS   _u(0x00000040)
+#define PWM_CH6_CSR_PH_RET_MSB    _u(6)
+#define PWM_CH6_CSR_PH_RET_LSB    _u(6)
+#define PWM_CH6_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH6_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+//               divider
+//               0x1 -> Fractional divider operation is gated by the PWM B pin.
+//               0x2 -> Counter advances with each rising edge of the PWM B pin.
+//               0x3 -> Counter advances with each falling edge of the PWM B
+//               pin.
+#define PWM_CH6_CSR_DIVMODE_RESET       _u(0x0)
+#define PWM_CH6_CSR_DIVMODE_BITS        _u(0x00000030)
+#define PWM_CH6_CSR_DIVMODE_MSB         _u(5)
+#define PWM_CH6_CSR_DIVMODE_LSB         _u(4)
+#define PWM_CH6_CSR_DIVMODE_ACCESS      "RW"
+#define PWM_CH6_CSR_DIVMODE_VALUE_DIV   _u(0x0)
+#define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH6_CSR_DIVMODE_VALUE_RISE  _u(0x2)
+#define PWM_CH6_CSR_DIVMODE_VALUE_FALL  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH6_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH6_CSR_B_INV_RESET  _u(0x0)
+#define PWM_CH6_CSR_B_INV_BITS   _u(0x00000008)
+#define PWM_CH6_CSR_B_INV_MSB    _u(3)
+#define PWM_CH6_CSR_B_INV_LSB    _u(3)
+#define PWM_CH6_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH6_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH6_CSR_A_INV_RESET  _u(0x0)
+#define PWM_CH6_CSR_A_INV_BITS   _u(0x00000004)
+#define PWM_CH6_CSR_A_INV_MSB    _u(2)
+#define PWM_CH6_CSR_A_INV_LSB    _u(2)
+#define PWM_CH6_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH6_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH6_CSR_PH_CORRECT_RESET  _u(0x0)
+#define PWM_CH6_CSR_PH_CORRECT_BITS   _u(0x00000002)
+#define PWM_CH6_CSR_PH_CORRECT_MSB    _u(1)
+#define PWM_CH6_CSR_PH_CORRECT_LSB    _u(1)
+#define PWM_CH6_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH6_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH6_CSR_EN_RESET  _u(0x0)
+#define PWM_CH6_CSR_EN_BITS   _u(0x00000001)
+#define PWM_CH6_CSR_EN_MSB    _u(0)
+#define PWM_CH6_CSR_EN_LSB    _u(0)
+#define PWM_CH6_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH6_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+//               Counting rate is system clock frequency divided by this number.
+//               Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH6_DIV_OFFSET _u(0x0000007c)
+#define PWM_CH6_DIV_BITS   _u(0x00000fff)
+#define PWM_CH6_DIV_RESET  _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH6_DIV_INT
+// Description : None
+#define PWM_CH6_DIV_INT_RESET  _u(0x01)
+#define PWM_CH6_DIV_INT_BITS   _u(0x00000ff0)
+#define PWM_CH6_DIV_INT_MSB    _u(11)
+#define PWM_CH6_DIV_INT_LSB    _u(4)
+#define PWM_CH6_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH6_DIV_FRAC
+// Description : None
+#define PWM_CH6_DIV_FRAC_RESET  _u(0x0)
+#define PWM_CH6_DIV_FRAC_BITS   _u(0x0000000f)
+#define PWM_CH6_DIV_FRAC_MSB    _u(3)
+#define PWM_CH6_DIV_FRAC_LSB    _u(0)
+#define PWM_CH6_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH6_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH6_CTR_OFFSET _u(0x00000080)
+#define PWM_CH6_CTR_BITS   _u(0x0000ffff)
+#define PWM_CH6_CTR_RESET  _u(0x00000000)
+#define PWM_CH6_CTR_MSB    _u(15)
+#define PWM_CH6_CTR_LSB    _u(0)
+#define PWM_CH6_CTR_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH6_CC
+// Description : Counter compare values
+#define PWM_CH6_CC_OFFSET _u(0x00000084)
+#define PWM_CH6_CC_BITS   _u(0xffffffff)
+#define PWM_CH6_CC_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH6_CC_B
+// Description : None
+#define PWM_CH6_CC_B_RESET  _u(0x0000)
+#define PWM_CH6_CC_B_BITS   _u(0xffff0000)
+#define PWM_CH6_CC_B_MSB    _u(31)
+#define PWM_CH6_CC_B_LSB    _u(16)
+#define PWM_CH6_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH6_CC_A
+// Description : None
+#define PWM_CH6_CC_A_RESET  _u(0x0000)
+#define PWM_CH6_CC_A_BITS   _u(0x0000ffff)
+#define PWM_CH6_CC_A_MSB    _u(15)
+#define PWM_CH6_CC_A_LSB    _u(0)
+#define PWM_CH6_CC_A_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH6_TOP
+// Description : Counter wrap value
+#define PWM_CH6_TOP_OFFSET _u(0x00000088)
+#define PWM_CH6_TOP_BITS   _u(0x0000ffff)
+#define PWM_CH6_TOP_RESET  _u(0x0000ffff)
+#define PWM_CH6_TOP_MSB    _u(15)
+#define PWM_CH6_TOP_LSB    _u(0)
+#define PWM_CH6_TOP_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH7_CSR
+// Description : Control and status register
+#define PWM_CH7_CSR_OFFSET _u(0x0000008c)
+#define PWM_CH7_CSR_BITS   _u(0x000000ff)
+#define PWM_CH7_CSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH7_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running
+//               at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH7_CSR_PH_ADV_RESET  _u(0x0)
+#define PWM_CH7_CSR_PH_ADV_BITS   _u(0x00000080)
+#define PWM_CH7_CSR_PH_ADV_MSB    _u(7)
+#define PWM_CH7_CSR_PH_ADV_LSB    _u(7)
+#define PWM_CH7_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH7_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+//               running.
+//               Self-clearing. Write a 1, and poll until low. Counter must be
+//               running.
+#define PWM_CH7_CSR_PH_RET_RESET  _u(0x0)
+#define PWM_CH7_CSR_PH_RET_BITS   _u(0x00000040)
+#define PWM_CH7_CSR_PH_RET_MSB    _u(6)
+#define PWM_CH7_CSR_PH_RET_LSB    _u(6)
+#define PWM_CH7_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH7_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+//               divider
+//               0x1 -> Fractional divider operation is gated by the PWM B pin.
+//               0x2 -> Counter advances with each rising edge of the PWM B pin.
+//               0x3 -> Counter advances with each falling edge of the PWM B
+//               pin.
+#define PWM_CH7_CSR_DIVMODE_RESET       _u(0x0)
+#define PWM_CH7_CSR_DIVMODE_BITS        _u(0x00000030)
+#define PWM_CH7_CSR_DIVMODE_MSB         _u(5)
+#define PWM_CH7_CSR_DIVMODE_LSB         _u(4)
+#define PWM_CH7_CSR_DIVMODE_ACCESS      "RW"
+#define PWM_CH7_CSR_DIVMODE_VALUE_DIV   _u(0x0)
+#define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH7_CSR_DIVMODE_VALUE_RISE  _u(0x2)
+#define PWM_CH7_CSR_DIVMODE_VALUE_FALL  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH7_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH7_CSR_B_INV_RESET  _u(0x0)
+#define PWM_CH7_CSR_B_INV_BITS   _u(0x00000008)
+#define PWM_CH7_CSR_B_INV_MSB    _u(3)
+#define PWM_CH7_CSR_B_INV_LSB    _u(3)
+#define PWM_CH7_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH7_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH7_CSR_A_INV_RESET  _u(0x0)
+#define PWM_CH7_CSR_A_INV_BITS   _u(0x00000004)
+#define PWM_CH7_CSR_A_INV_MSB    _u(2)
+#define PWM_CH7_CSR_A_INV_LSB    _u(2)
+#define PWM_CH7_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH7_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH7_CSR_PH_CORRECT_RESET  _u(0x0)
+#define PWM_CH7_CSR_PH_CORRECT_BITS   _u(0x00000002)
+#define PWM_CH7_CSR_PH_CORRECT_MSB    _u(1)
+#define PWM_CH7_CSR_PH_CORRECT_LSB    _u(1)
+#define PWM_CH7_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH7_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH7_CSR_EN_RESET  _u(0x0)
+#define PWM_CH7_CSR_EN_BITS   _u(0x00000001)
+#define PWM_CH7_CSR_EN_MSB    _u(0)
+#define PWM_CH7_CSR_EN_LSB    _u(0)
+#define PWM_CH7_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH7_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+//               Counting rate is system clock frequency divided by this number.
+//               Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH7_DIV_OFFSET _u(0x00000090)
+#define PWM_CH7_DIV_BITS   _u(0x00000fff)
+#define PWM_CH7_DIV_RESET  _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH7_DIV_INT
+// Description : None
+#define PWM_CH7_DIV_INT_RESET  _u(0x01)
+#define PWM_CH7_DIV_INT_BITS   _u(0x00000ff0)
+#define PWM_CH7_DIV_INT_MSB    _u(11)
+#define PWM_CH7_DIV_INT_LSB    _u(4)
+#define PWM_CH7_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH7_DIV_FRAC
+// Description : None
+#define PWM_CH7_DIV_FRAC_RESET  _u(0x0)
+#define PWM_CH7_DIV_FRAC_BITS   _u(0x0000000f)
+#define PWM_CH7_DIV_FRAC_MSB    _u(3)
+#define PWM_CH7_DIV_FRAC_LSB    _u(0)
+#define PWM_CH7_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH7_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH7_CTR_OFFSET _u(0x00000094)
+#define PWM_CH7_CTR_BITS   _u(0x0000ffff)
+#define PWM_CH7_CTR_RESET  _u(0x00000000)
+#define PWM_CH7_CTR_MSB    _u(15)
+#define PWM_CH7_CTR_LSB    _u(0)
+#define PWM_CH7_CTR_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH7_CC
+// Description : Counter compare values
+#define PWM_CH7_CC_OFFSET _u(0x00000098)
+#define PWM_CH7_CC_BITS   _u(0xffffffff)
+#define PWM_CH7_CC_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH7_CC_B
+// Description : None
+#define PWM_CH7_CC_B_RESET  _u(0x0000)
+#define PWM_CH7_CC_B_BITS   _u(0xffff0000)
+#define PWM_CH7_CC_B_MSB    _u(31)
+#define PWM_CH7_CC_B_LSB    _u(16)
+#define PWM_CH7_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_CH7_CC_A
+// Description : None
+#define PWM_CH7_CC_A_RESET  _u(0x0000)
+#define PWM_CH7_CC_A_BITS   _u(0x0000ffff)
+#define PWM_CH7_CC_A_MSB    _u(15)
+#define PWM_CH7_CC_A_LSB    _u(0)
+#define PWM_CH7_CC_A_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_CH7_TOP
+// Description : Counter wrap value
+#define PWM_CH7_TOP_OFFSET _u(0x0000009c)
+#define PWM_CH7_TOP_BITS   _u(0x0000ffff)
+#define PWM_CH7_TOP_RESET  _u(0x0000ffff)
+#define PWM_CH7_TOP_MSB    _u(15)
+#define PWM_CH7_TOP_LSB    _u(0)
+#define PWM_CH7_TOP_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_EN
+// Description : This register aliases the CSR_EN bits for all channels.
+//               Writing to this register allows multiple channels to be enabled
+//               or disabled simultaneously, so they can run in perfect sync.
+//               For each channel, there is only one physical EN register bit,
+//               which can be accessed through here or CHx_CSR.
+#define PWM_EN_OFFSET _u(0x000000a0)
+#define PWM_EN_BITS   _u(0x000000ff)
+#define PWM_EN_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_EN_CH7
+// Description : None
+#define PWM_EN_CH7_RESET  _u(0x0)
+#define PWM_EN_CH7_BITS   _u(0x00000080)
+#define PWM_EN_CH7_MSB    _u(7)
+#define PWM_EN_CH7_LSB    _u(7)
+#define PWM_EN_CH7_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_EN_CH6
+// Description : None
+#define PWM_EN_CH6_RESET  _u(0x0)
+#define PWM_EN_CH6_BITS   _u(0x00000040)
+#define PWM_EN_CH6_MSB    _u(6)
+#define PWM_EN_CH6_LSB    _u(6)
+#define PWM_EN_CH6_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_EN_CH5
+// Description : None
+#define PWM_EN_CH5_RESET  _u(0x0)
+#define PWM_EN_CH5_BITS   _u(0x00000020)
+#define PWM_EN_CH5_MSB    _u(5)
+#define PWM_EN_CH5_LSB    _u(5)
+#define PWM_EN_CH5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_EN_CH4
+// Description : None
+#define PWM_EN_CH4_RESET  _u(0x0)
+#define PWM_EN_CH4_BITS   _u(0x00000010)
+#define PWM_EN_CH4_MSB    _u(4)
+#define PWM_EN_CH4_LSB    _u(4)
+#define PWM_EN_CH4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_EN_CH3
+// Description : None
+#define PWM_EN_CH3_RESET  _u(0x0)
+#define PWM_EN_CH3_BITS   _u(0x00000008)
+#define PWM_EN_CH3_MSB    _u(3)
+#define PWM_EN_CH3_LSB    _u(3)
+#define PWM_EN_CH3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_EN_CH2
+// Description : None
+#define PWM_EN_CH2_RESET  _u(0x0)
+#define PWM_EN_CH2_BITS   _u(0x00000004)
+#define PWM_EN_CH2_MSB    _u(2)
+#define PWM_EN_CH2_LSB    _u(2)
+#define PWM_EN_CH2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_EN_CH1
+// Description : None
+#define PWM_EN_CH1_RESET  _u(0x0)
+#define PWM_EN_CH1_BITS   _u(0x00000002)
+#define PWM_EN_CH1_MSB    _u(1)
+#define PWM_EN_CH1_LSB    _u(1)
+#define PWM_EN_CH1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_EN_CH0
+// Description : None
+#define PWM_EN_CH0_RESET  _u(0x0)
+#define PWM_EN_CH0_BITS   _u(0x00000001)
+#define PWM_EN_CH0_MSB    _u(0)
+#define PWM_EN_CH0_LSB    _u(0)
+#define PWM_EN_CH0_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_INTR
+// Description : Raw Interrupts
+#define PWM_INTR_OFFSET _u(0x000000a4)
+#define PWM_INTR_BITS   _u(0x000000ff)
+#define PWM_INTR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTR_CH7
+// Description : None
+#define PWM_INTR_CH7_RESET  _u(0x0)
+#define PWM_INTR_CH7_BITS   _u(0x00000080)
+#define PWM_INTR_CH7_MSB    _u(7)
+#define PWM_INTR_CH7_LSB    _u(7)
+#define PWM_INTR_CH7_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTR_CH6
+// Description : None
+#define PWM_INTR_CH6_RESET  _u(0x0)
+#define PWM_INTR_CH6_BITS   _u(0x00000040)
+#define PWM_INTR_CH6_MSB    _u(6)
+#define PWM_INTR_CH6_LSB    _u(6)
+#define PWM_INTR_CH6_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTR_CH5
+// Description : None
+#define PWM_INTR_CH5_RESET  _u(0x0)
+#define PWM_INTR_CH5_BITS   _u(0x00000020)
+#define PWM_INTR_CH5_MSB    _u(5)
+#define PWM_INTR_CH5_LSB    _u(5)
+#define PWM_INTR_CH5_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTR_CH4
+// Description : None
+#define PWM_INTR_CH4_RESET  _u(0x0)
+#define PWM_INTR_CH4_BITS   _u(0x00000010)
+#define PWM_INTR_CH4_MSB    _u(4)
+#define PWM_INTR_CH4_LSB    _u(4)
+#define PWM_INTR_CH4_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTR_CH3
+// Description : None
+#define PWM_INTR_CH3_RESET  _u(0x0)
+#define PWM_INTR_CH3_BITS   _u(0x00000008)
+#define PWM_INTR_CH3_MSB    _u(3)
+#define PWM_INTR_CH3_LSB    _u(3)
+#define PWM_INTR_CH3_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTR_CH2
+// Description : None
+#define PWM_INTR_CH2_RESET  _u(0x0)
+#define PWM_INTR_CH2_BITS   _u(0x00000004)
+#define PWM_INTR_CH2_MSB    _u(2)
+#define PWM_INTR_CH2_LSB    _u(2)
+#define PWM_INTR_CH2_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTR_CH1
+// Description : None
+#define PWM_INTR_CH1_RESET  _u(0x0)
+#define PWM_INTR_CH1_BITS   _u(0x00000002)
+#define PWM_INTR_CH1_MSB    _u(1)
+#define PWM_INTR_CH1_LSB    _u(1)
+#define PWM_INTR_CH1_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTR_CH0
+// Description : None
+#define PWM_INTR_CH0_RESET  _u(0x0)
+#define PWM_INTR_CH0_BITS   _u(0x00000001)
+#define PWM_INTR_CH0_MSB    _u(0)
+#define PWM_INTR_CH0_LSB    _u(0)
+#define PWM_INTR_CH0_ACCESS "WC"
+// =============================================================================
+// Register    : PWM_INTE
+// Description : Interrupt Enable
+#define PWM_INTE_OFFSET _u(0x000000a8)
+#define PWM_INTE_BITS   _u(0x000000ff)
+#define PWM_INTE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTE_CH7
+// Description : None
+#define PWM_INTE_CH7_RESET  _u(0x0)
+#define PWM_INTE_CH7_BITS   _u(0x00000080)
+#define PWM_INTE_CH7_MSB    _u(7)
+#define PWM_INTE_CH7_LSB    _u(7)
+#define PWM_INTE_CH7_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTE_CH6
+// Description : None
+#define PWM_INTE_CH6_RESET  _u(0x0)
+#define PWM_INTE_CH6_BITS   _u(0x00000040)
+#define PWM_INTE_CH6_MSB    _u(6)
+#define PWM_INTE_CH6_LSB    _u(6)
+#define PWM_INTE_CH6_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTE_CH5
+// Description : None
+#define PWM_INTE_CH5_RESET  _u(0x0)
+#define PWM_INTE_CH5_BITS   _u(0x00000020)
+#define PWM_INTE_CH5_MSB    _u(5)
+#define PWM_INTE_CH5_LSB    _u(5)
+#define PWM_INTE_CH5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTE_CH4
+// Description : None
+#define PWM_INTE_CH4_RESET  _u(0x0)
+#define PWM_INTE_CH4_BITS   _u(0x00000010)
+#define PWM_INTE_CH4_MSB    _u(4)
+#define PWM_INTE_CH4_LSB    _u(4)
+#define PWM_INTE_CH4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTE_CH3
+// Description : None
+#define PWM_INTE_CH3_RESET  _u(0x0)
+#define PWM_INTE_CH3_BITS   _u(0x00000008)
+#define PWM_INTE_CH3_MSB    _u(3)
+#define PWM_INTE_CH3_LSB    _u(3)
+#define PWM_INTE_CH3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTE_CH2
+// Description : None
+#define PWM_INTE_CH2_RESET  _u(0x0)
+#define PWM_INTE_CH2_BITS   _u(0x00000004)
+#define PWM_INTE_CH2_MSB    _u(2)
+#define PWM_INTE_CH2_LSB    _u(2)
+#define PWM_INTE_CH2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTE_CH1
+// Description : None
+#define PWM_INTE_CH1_RESET  _u(0x0)
+#define PWM_INTE_CH1_BITS   _u(0x00000002)
+#define PWM_INTE_CH1_MSB    _u(1)
+#define PWM_INTE_CH1_LSB    _u(1)
+#define PWM_INTE_CH1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTE_CH0
+// Description : None
+#define PWM_INTE_CH0_RESET  _u(0x0)
+#define PWM_INTE_CH0_BITS   _u(0x00000001)
+#define PWM_INTE_CH0_MSB    _u(0)
+#define PWM_INTE_CH0_LSB    _u(0)
+#define PWM_INTE_CH0_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_INTF
+// Description : Interrupt Force
+#define PWM_INTF_OFFSET _u(0x000000ac)
+#define PWM_INTF_BITS   _u(0x000000ff)
+#define PWM_INTF_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTF_CH7
+// Description : None
+#define PWM_INTF_CH7_RESET  _u(0x0)
+#define PWM_INTF_CH7_BITS   _u(0x00000080)
+#define PWM_INTF_CH7_MSB    _u(7)
+#define PWM_INTF_CH7_LSB    _u(7)
+#define PWM_INTF_CH7_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTF_CH6
+// Description : None
+#define PWM_INTF_CH6_RESET  _u(0x0)
+#define PWM_INTF_CH6_BITS   _u(0x00000040)
+#define PWM_INTF_CH6_MSB    _u(6)
+#define PWM_INTF_CH6_LSB    _u(6)
+#define PWM_INTF_CH6_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTF_CH5
+// Description : None
+#define PWM_INTF_CH5_RESET  _u(0x0)
+#define PWM_INTF_CH5_BITS   _u(0x00000020)
+#define PWM_INTF_CH5_MSB    _u(5)
+#define PWM_INTF_CH5_LSB    _u(5)
+#define PWM_INTF_CH5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTF_CH4
+// Description : None
+#define PWM_INTF_CH4_RESET  _u(0x0)
+#define PWM_INTF_CH4_BITS   _u(0x00000010)
+#define PWM_INTF_CH4_MSB    _u(4)
+#define PWM_INTF_CH4_LSB    _u(4)
+#define PWM_INTF_CH4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTF_CH3
+// Description : None
+#define PWM_INTF_CH3_RESET  _u(0x0)
+#define PWM_INTF_CH3_BITS   _u(0x00000008)
+#define PWM_INTF_CH3_MSB    _u(3)
+#define PWM_INTF_CH3_LSB    _u(3)
+#define PWM_INTF_CH3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTF_CH2
+// Description : None
+#define PWM_INTF_CH2_RESET  _u(0x0)
+#define PWM_INTF_CH2_BITS   _u(0x00000004)
+#define PWM_INTF_CH2_MSB    _u(2)
+#define PWM_INTF_CH2_LSB    _u(2)
+#define PWM_INTF_CH2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTF_CH1
+// Description : None
+#define PWM_INTF_CH1_RESET  _u(0x0)
+#define PWM_INTF_CH1_BITS   _u(0x00000002)
+#define PWM_INTF_CH1_MSB    _u(1)
+#define PWM_INTF_CH1_LSB    _u(1)
+#define PWM_INTF_CH1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTF_CH0
+// Description : None
+#define PWM_INTF_CH0_RESET  _u(0x0)
+#define PWM_INTF_CH0_BITS   _u(0x00000001)
+#define PWM_INTF_CH0_MSB    _u(0)
+#define PWM_INTF_CH0_LSB    _u(0)
+#define PWM_INTF_CH0_ACCESS "RW"
+// =============================================================================
+// Register    : PWM_INTS
+// Description : Interrupt status after masking & forcing
+#define PWM_INTS_OFFSET _u(0x000000b0)
+#define PWM_INTS_BITS   _u(0x000000ff)
+#define PWM_INTS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTS_CH7
+// Description : None
+#define PWM_INTS_CH7_RESET  _u(0x0)
+#define PWM_INTS_CH7_BITS   _u(0x00000080)
+#define PWM_INTS_CH7_MSB    _u(7)
+#define PWM_INTS_CH7_LSB    _u(7)
+#define PWM_INTS_CH7_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTS_CH6
+// Description : None
+#define PWM_INTS_CH6_RESET  _u(0x0)
+#define PWM_INTS_CH6_BITS   _u(0x00000040)
+#define PWM_INTS_CH6_MSB    _u(6)
+#define PWM_INTS_CH6_LSB    _u(6)
+#define PWM_INTS_CH6_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTS_CH5
+// Description : None
+#define PWM_INTS_CH5_RESET  _u(0x0)
+#define PWM_INTS_CH5_BITS   _u(0x00000020)
+#define PWM_INTS_CH5_MSB    _u(5)
+#define PWM_INTS_CH5_LSB    _u(5)
+#define PWM_INTS_CH5_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTS_CH4
+// Description : None
+#define PWM_INTS_CH4_RESET  _u(0x0)
+#define PWM_INTS_CH4_BITS   _u(0x00000010)
+#define PWM_INTS_CH4_MSB    _u(4)
+#define PWM_INTS_CH4_LSB    _u(4)
+#define PWM_INTS_CH4_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTS_CH3
+// Description : None
+#define PWM_INTS_CH3_RESET  _u(0x0)
+#define PWM_INTS_CH3_BITS   _u(0x00000008)
+#define PWM_INTS_CH3_MSB    _u(3)
+#define PWM_INTS_CH3_LSB    _u(3)
+#define PWM_INTS_CH3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTS_CH2
+// Description : None
+#define PWM_INTS_CH2_RESET  _u(0x0)
+#define PWM_INTS_CH2_BITS   _u(0x00000004)
+#define PWM_INTS_CH2_MSB    _u(2)
+#define PWM_INTS_CH2_LSB    _u(2)
+#define PWM_INTS_CH2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTS_CH1
+// Description : None
+#define PWM_INTS_CH1_RESET  _u(0x0)
+#define PWM_INTS_CH1_BITS   _u(0x00000002)
+#define PWM_INTS_CH1_MSB    _u(1)
+#define PWM_INTS_CH1_LSB    _u(1)
+#define PWM_INTS_CH1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : PWM_INTS_CH0
+// Description : None
+#define PWM_INTS_CH0_RESET  _u(0x0)
+#define PWM_INTS_CH0_BITS   _u(0x00000001)
+#define PWM_INTS_CH0_MSB    _u(0)
+#define PWM_INTS_CH0_LSB    _u(0)
+#define PWM_INTS_CH0_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_PWM_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/resets.h b/src/rp2040/hardware_regs/include/hardware/regs/resets.h
new file mode 100644
index 0000000..689a358
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/resets.h
@@ -0,0 +1,637 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : RESETS
+// Version        : 1
+// Bus type       : apb
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_RESETS_DEFINED
+#define HARDWARE_REGS_RESETS_DEFINED
+// =============================================================================
+// Register    : RESETS_RESET
+// Description : Reset control. If a bit is set it means the peripheral is in
+//               reset. 0 means the peripheral's reset is deasserted.
+#define RESETS_RESET_OFFSET _u(0x00000000)
+#define RESETS_RESET_BITS   _u(0x01ffffff)
+#define RESETS_RESET_RESET  _u(0x01ffffff)
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_USBCTRL
+// Description : None
+#define RESETS_RESET_USBCTRL_RESET  _u(0x1)
+#define RESETS_RESET_USBCTRL_BITS   _u(0x01000000)
+#define RESETS_RESET_USBCTRL_MSB    _u(24)
+#define RESETS_RESET_USBCTRL_LSB    _u(24)
+#define RESETS_RESET_USBCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_UART1
+// Description : None
+#define RESETS_RESET_UART1_RESET  _u(0x1)
+#define RESETS_RESET_UART1_BITS   _u(0x00800000)
+#define RESETS_RESET_UART1_MSB    _u(23)
+#define RESETS_RESET_UART1_LSB    _u(23)
+#define RESETS_RESET_UART1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_UART0
+// Description : None
+#define RESETS_RESET_UART0_RESET  _u(0x1)
+#define RESETS_RESET_UART0_BITS   _u(0x00400000)
+#define RESETS_RESET_UART0_MSB    _u(22)
+#define RESETS_RESET_UART0_LSB    _u(22)
+#define RESETS_RESET_UART0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_TIMER
+// Description : None
+#define RESETS_RESET_TIMER_RESET  _u(0x1)
+#define RESETS_RESET_TIMER_BITS   _u(0x00200000)
+#define RESETS_RESET_TIMER_MSB    _u(21)
+#define RESETS_RESET_TIMER_LSB    _u(21)
+#define RESETS_RESET_TIMER_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_TBMAN
+// Description : None
+#define RESETS_RESET_TBMAN_RESET  _u(0x1)
+#define RESETS_RESET_TBMAN_BITS   _u(0x00100000)
+#define RESETS_RESET_TBMAN_MSB    _u(20)
+#define RESETS_RESET_TBMAN_LSB    _u(20)
+#define RESETS_RESET_TBMAN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_SYSINFO
+// Description : None
+#define RESETS_RESET_SYSINFO_RESET  _u(0x1)
+#define RESETS_RESET_SYSINFO_BITS   _u(0x00080000)
+#define RESETS_RESET_SYSINFO_MSB    _u(19)
+#define RESETS_RESET_SYSINFO_LSB    _u(19)
+#define RESETS_RESET_SYSINFO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_SYSCFG
+// Description : None
+#define RESETS_RESET_SYSCFG_RESET  _u(0x1)
+#define RESETS_RESET_SYSCFG_BITS   _u(0x00040000)
+#define RESETS_RESET_SYSCFG_MSB    _u(18)
+#define RESETS_RESET_SYSCFG_LSB    _u(18)
+#define RESETS_RESET_SYSCFG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_SPI1
+// Description : None
+#define RESETS_RESET_SPI1_RESET  _u(0x1)
+#define RESETS_RESET_SPI1_BITS   _u(0x00020000)
+#define RESETS_RESET_SPI1_MSB    _u(17)
+#define RESETS_RESET_SPI1_LSB    _u(17)
+#define RESETS_RESET_SPI1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_SPI0
+// Description : None
+#define RESETS_RESET_SPI0_RESET  _u(0x1)
+#define RESETS_RESET_SPI0_BITS   _u(0x00010000)
+#define RESETS_RESET_SPI0_MSB    _u(16)
+#define RESETS_RESET_SPI0_LSB    _u(16)
+#define RESETS_RESET_SPI0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_RTC
+// Description : None
+#define RESETS_RESET_RTC_RESET  _u(0x1)
+#define RESETS_RESET_RTC_BITS   _u(0x00008000)
+#define RESETS_RESET_RTC_MSB    _u(15)
+#define RESETS_RESET_RTC_LSB    _u(15)
+#define RESETS_RESET_RTC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_PWM
+// Description : None
+#define RESETS_RESET_PWM_RESET  _u(0x1)
+#define RESETS_RESET_PWM_BITS   _u(0x00004000)
+#define RESETS_RESET_PWM_MSB    _u(14)
+#define RESETS_RESET_PWM_LSB    _u(14)
+#define RESETS_RESET_PWM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_PLL_USB
+// Description : None
+#define RESETS_RESET_PLL_USB_RESET  _u(0x1)
+#define RESETS_RESET_PLL_USB_BITS   _u(0x00002000)
+#define RESETS_RESET_PLL_USB_MSB    _u(13)
+#define RESETS_RESET_PLL_USB_LSB    _u(13)
+#define RESETS_RESET_PLL_USB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_PLL_SYS
+// Description : None
+#define RESETS_RESET_PLL_SYS_RESET  _u(0x1)
+#define RESETS_RESET_PLL_SYS_BITS   _u(0x00001000)
+#define RESETS_RESET_PLL_SYS_MSB    _u(12)
+#define RESETS_RESET_PLL_SYS_LSB    _u(12)
+#define RESETS_RESET_PLL_SYS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_PIO1
+// Description : None
+#define RESETS_RESET_PIO1_RESET  _u(0x1)
+#define RESETS_RESET_PIO1_BITS   _u(0x00000800)
+#define RESETS_RESET_PIO1_MSB    _u(11)
+#define RESETS_RESET_PIO1_LSB    _u(11)
+#define RESETS_RESET_PIO1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_PIO0
+// Description : None
+#define RESETS_RESET_PIO0_RESET  _u(0x1)
+#define RESETS_RESET_PIO0_BITS   _u(0x00000400)
+#define RESETS_RESET_PIO0_MSB    _u(10)
+#define RESETS_RESET_PIO0_LSB    _u(10)
+#define RESETS_RESET_PIO0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_PADS_QSPI
+// Description : None
+#define RESETS_RESET_PADS_QSPI_RESET  _u(0x1)
+#define RESETS_RESET_PADS_QSPI_BITS   _u(0x00000200)
+#define RESETS_RESET_PADS_QSPI_MSB    _u(9)
+#define RESETS_RESET_PADS_QSPI_LSB    _u(9)
+#define RESETS_RESET_PADS_QSPI_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_PADS_BANK0
+// Description : None
+#define RESETS_RESET_PADS_BANK0_RESET  _u(0x1)
+#define RESETS_RESET_PADS_BANK0_BITS   _u(0x00000100)
+#define RESETS_RESET_PADS_BANK0_MSB    _u(8)
+#define RESETS_RESET_PADS_BANK0_LSB    _u(8)
+#define RESETS_RESET_PADS_BANK0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_JTAG
+// Description : None
+#define RESETS_RESET_JTAG_RESET  _u(0x1)
+#define RESETS_RESET_JTAG_BITS   _u(0x00000080)
+#define RESETS_RESET_JTAG_MSB    _u(7)
+#define RESETS_RESET_JTAG_LSB    _u(7)
+#define RESETS_RESET_JTAG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_IO_QSPI
+// Description : None
+#define RESETS_RESET_IO_QSPI_RESET  _u(0x1)
+#define RESETS_RESET_IO_QSPI_BITS   _u(0x00000040)
+#define RESETS_RESET_IO_QSPI_MSB    _u(6)
+#define RESETS_RESET_IO_QSPI_LSB    _u(6)
+#define RESETS_RESET_IO_QSPI_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_IO_BANK0
+// Description : None
+#define RESETS_RESET_IO_BANK0_RESET  _u(0x1)
+#define RESETS_RESET_IO_BANK0_BITS   _u(0x00000020)
+#define RESETS_RESET_IO_BANK0_MSB    _u(5)
+#define RESETS_RESET_IO_BANK0_LSB    _u(5)
+#define RESETS_RESET_IO_BANK0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_I2C1
+// Description : None
+#define RESETS_RESET_I2C1_RESET  _u(0x1)
+#define RESETS_RESET_I2C1_BITS   _u(0x00000010)
+#define RESETS_RESET_I2C1_MSB    _u(4)
+#define RESETS_RESET_I2C1_LSB    _u(4)
+#define RESETS_RESET_I2C1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_I2C0
+// Description : None
+#define RESETS_RESET_I2C0_RESET  _u(0x1)
+#define RESETS_RESET_I2C0_BITS   _u(0x00000008)
+#define RESETS_RESET_I2C0_MSB    _u(3)
+#define RESETS_RESET_I2C0_LSB    _u(3)
+#define RESETS_RESET_I2C0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DMA
+// Description : None
+#define RESETS_RESET_DMA_RESET  _u(0x1)
+#define RESETS_RESET_DMA_BITS   _u(0x00000004)
+#define RESETS_RESET_DMA_MSB    _u(2)
+#define RESETS_RESET_DMA_LSB    _u(2)
+#define RESETS_RESET_DMA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_BUSCTRL
+// Description : None
+#define RESETS_RESET_BUSCTRL_RESET  _u(0x1)
+#define RESETS_RESET_BUSCTRL_BITS   _u(0x00000002)
+#define RESETS_RESET_BUSCTRL_MSB    _u(1)
+#define RESETS_RESET_BUSCTRL_LSB    _u(1)
+#define RESETS_RESET_BUSCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_ADC
+// Description : None
+#define RESETS_RESET_ADC_RESET  _u(0x1)
+#define RESETS_RESET_ADC_BITS   _u(0x00000001)
+#define RESETS_RESET_ADC_MSB    _u(0)
+#define RESETS_RESET_ADC_LSB    _u(0)
+#define RESETS_RESET_ADC_ACCESS "RW"
+// =============================================================================
+// Register    : RESETS_WDSEL
+// Description : Watchdog select. If a bit is set then the watchdog will reset
+//               this peripheral when the watchdog fires.
+#define RESETS_WDSEL_OFFSET _u(0x00000004)
+#define RESETS_WDSEL_BITS   _u(0x01ffffff)
+#define RESETS_WDSEL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_USBCTRL
+// Description : None
+#define RESETS_WDSEL_USBCTRL_RESET  _u(0x0)
+#define RESETS_WDSEL_USBCTRL_BITS   _u(0x01000000)
+#define RESETS_WDSEL_USBCTRL_MSB    _u(24)
+#define RESETS_WDSEL_USBCTRL_LSB    _u(24)
+#define RESETS_WDSEL_USBCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_UART1
+// Description : None
+#define RESETS_WDSEL_UART1_RESET  _u(0x0)
+#define RESETS_WDSEL_UART1_BITS   _u(0x00800000)
+#define RESETS_WDSEL_UART1_MSB    _u(23)
+#define RESETS_WDSEL_UART1_LSB    _u(23)
+#define RESETS_WDSEL_UART1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_UART0
+// Description : None
+#define RESETS_WDSEL_UART0_RESET  _u(0x0)
+#define RESETS_WDSEL_UART0_BITS   _u(0x00400000)
+#define RESETS_WDSEL_UART0_MSB    _u(22)
+#define RESETS_WDSEL_UART0_LSB    _u(22)
+#define RESETS_WDSEL_UART0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_TIMER
+// Description : None
+#define RESETS_WDSEL_TIMER_RESET  _u(0x0)
+#define RESETS_WDSEL_TIMER_BITS   _u(0x00200000)
+#define RESETS_WDSEL_TIMER_MSB    _u(21)
+#define RESETS_WDSEL_TIMER_LSB    _u(21)
+#define RESETS_WDSEL_TIMER_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_TBMAN
+// Description : None
+#define RESETS_WDSEL_TBMAN_RESET  _u(0x0)
+#define RESETS_WDSEL_TBMAN_BITS   _u(0x00100000)
+#define RESETS_WDSEL_TBMAN_MSB    _u(20)
+#define RESETS_WDSEL_TBMAN_LSB    _u(20)
+#define RESETS_WDSEL_TBMAN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_SYSINFO
+// Description : None
+#define RESETS_WDSEL_SYSINFO_RESET  _u(0x0)
+#define RESETS_WDSEL_SYSINFO_BITS   _u(0x00080000)
+#define RESETS_WDSEL_SYSINFO_MSB    _u(19)
+#define RESETS_WDSEL_SYSINFO_LSB    _u(19)
+#define RESETS_WDSEL_SYSINFO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_SYSCFG
+// Description : None
+#define RESETS_WDSEL_SYSCFG_RESET  _u(0x0)
+#define RESETS_WDSEL_SYSCFG_BITS   _u(0x00040000)
+#define RESETS_WDSEL_SYSCFG_MSB    _u(18)
+#define RESETS_WDSEL_SYSCFG_LSB    _u(18)
+#define RESETS_WDSEL_SYSCFG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_SPI1
+// Description : None
+#define RESETS_WDSEL_SPI1_RESET  _u(0x0)
+#define RESETS_WDSEL_SPI1_BITS   _u(0x00020000)
+#define RESETS_WDSEL_SPI1_MSB    _u(17)
+#define RESETS_WDSEL_SPI1_LSB    _u(17)
+#define RESETS_WDSEL_SPI1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_SPI0
+// Description : None
+#define RESETS_WDSEL_SPI0_RESET  _u(0x0)
+#define RESETS_WDSEL_SPI0_BITS   _u(0x00010000)
+#define RESETS_WDSEL_SPI0_MSB    _u(16)
+#define RESETS_WDSEL_SPI0_LSB    _u(16)
+#define RESETS_WDSEL_SPI0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_RTC
+// Description : None
+#define RESETS_WDSEL_RTC_RESET  _u(0x0)
+#define RESETS_WDSEL_RTC_BITS   _u(0x00008000)
+#define RESETS_WDSEL_RTC_MSB    _u(15)
+#define RESETS_WDSEL_RTC_LSB    _u(15)
+#define RESETS_WDSEL_RTC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_PWM
+// Description : None
+#define RESETS_WDSEL_PWM_RESET  _u(0x0)
+#define RESETS_WDSEL_PWM_BITS   _u(0x00004000)
+#define RESETS_WDSEL_PWM_MSB    _u(14)
+#define RESETS_WDSEL_PWM_LSB    _u(14)
+#define RESETS_WDSEL_PWM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_PLL_USB
+// Description : None
+#define RESETS_WDSEL_PLL_USB_RESET  _u(0x0)
+#define RESETS_WDSEL_PLL_USB_BITS   _u(0x00002000)
+#define RESETS_WDSEL_PLL_USB_MSB    _u(13)
+#define RESETS_WDSEL_PLL_USB_LSB    _u(13)
+#define RESETS_WDSEL_PLL_USB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_PLL_SYS
+// Description : None
+#define RESETS_WDSEL_PLL_SYS_RESET  _u(0x0)
+#define RESETS_WDSEL_PLL_SYS_BITS   _u(0x00001000)
+#define RESETS_WDSEL_PLL_SYS_MSB    _u(12)
+#define RESETS_WDSEL_PLL_SYS_LSB    _u(12)
+#define RESETS_WDSEL_PLL_SYS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_PIO1
+// Description : None
+#define RESETS_WDSEL_PIO1_RESET  _u(0x0)
+#define RESETS_WDSEL_PIO1_BITS   _u(0x00000800)
+#define RESETS_WDSEL_PIO1_MSB    _u(11)
+#define RESETS_WDSEL_PIO1_LSB    _u(11)
+#define RESETS_WDSEL_PIO1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_PIO0
+// Description : None
+#define RESETS_WDSEL_PIO0_RESET  _u(0x0)
+#define RESETS_WDSEL_PIO0_BITS   _u(0x00000400)
+#define RESETS_WDSEL_PIO0_MSB    _u(10)
+#define RESETS_WDSEL_PIO0_LSB    _u(10)
+#define RESETS_WDSEL_PIO0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_PADS_QSPI
+// Description : None
+#define RESETS_WDSEL_PADS_QSPI_RESET  _u(0x0)
+#define RESETS_WDSEL_PADS_QSPI_BITS   _u(0x00000200)
+#define RESETS_WDSEL_PADS_QSPI_MSB    _u(9)
+#define RESETS_WDSEL_PADS_QSPI_LSB    _u(9)
+#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_PADS_BANK0
+// Description : None
+#define RESETS_WDSEL_PADS_BANK0_RESET  _u(0x0)
+#define RESETS_WDSEL_PADS_BANK0_BITS   _u(0x00000100)
+#define RESETS_WDSEL_PADS_BANK0_MSB    _u(8)
+#define RESETS_WDSEL_PADS_BANK0_LSB    _u(8)
+#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_JTAG
+// Description : None
+#define RESETS_WDSEL_JTAG_RESET  _u(0x0)
+#define RESETS_WDSEL_JTAG_BITS   _u(0x00000080)
+#define RESETS_WDSEL_JTAG_MSB    _u(7)
+#define RESETS_WDSEL_JTAG_LSB    _u(7)
+#define RESETS_WDSEL_JTAG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_IO_QSPI
+// Description : None
+#define RESETS_WDSEL_IO_QSPI_RESET  _u(0x0)
+#define RESETS_WDSEL_IO_QSPI_BITS   _u(0x00000040)
+#define RESETS_WDSEL_IO_QSPI_MSB    _u(6)
+#define RESETS_WDSEL_IO_QSPI_LSB    _u(6)
+#define RESETS_WDSEL_IO_QSPI_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_IO_BANK0
+// Description : None
+#define RESETS_WDSEL_IO_BANK0_RESET  _u(0x0)
+#define RESETS_WDSEL_IO_BANK0_BITS   _u(0x00000020)
+#define RESETS_WDSEL_IO_BANK0_MSB    _u(5)
+#define RESETS_WDSEL_IO_BANK0_LSB    _u(5)
+#define RESETS_WDSEL_IO_BANK0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_I2C1
+// Description : None
+#define RESETS_WDSEL_I2C1_RESET  _u(0x0)
+#define RESETS_WDSEL_I2C1_BITS   _u(0x00000010)
+#define RESETS_WDSEL_I2C1_MSB    _u(4)
+#define RESETS_WDSEL_I2C1_LSB    _u(4)
+#define RESETS_WDSEL_I2C1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_I2C0
+// Description : None
+#define RESETS_WDSEL_I2C0_RESET  _u(0x0)
+#define RESETS_WDSEL_I2C0_BITS   _u(0x00000008)
+#define RESETS_WDSEL_I2C0_MSB    _u(3)
+#define RESETS_WDSEL_I2C0_LSB    _u(3)
+#define RESETS_WDSEL_I2C0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_DMA
+// Description : None
+#define RESETS_WDSEL_DMA_RESET  _u(0x0)
+#define RESETS_WDSEL_DMA_BITS   _u(0x00000004)
+#define RESETS_WDSEL_DMA_MSB    _u(2)
+#define RESETS_WDSEL_DMA_LSB    _u(2)
+#define RESETS_WDSEL_DMA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_BUSCTRL
+// Description : None
+#define RESETS_WDSEL_BUSCTRL_RESET  _u(0x0)
+#define RESETS_WDSEL_BUSCTRL_BITS   _u(0x00000002)
+#define RESETS_WDSEL_BUSCTRL_MSB    _u(1)
+#define RESETS_WDSEL_BUSCTRL_LSB    _u(1)
+#define RESETS_WDSEL_BUSCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_WDSEL_ADC
+// Description : None
+#define RESETS_WDSEL_ADC_RESET  _u(0x0)
+#define RESETS_WDSEL_ADC_BITS   _u(0x00000001)
+#define RESETS_WDSEL_ADC_MSB    _u(0)
+#define RESETS_WDSEL_ADC_LSB    _u(0)
+#define RESETS_WDSEL_ADC_ACCESS "RW"
+// =============================================================================
+// Register    : RESETS_RESET_DONE
+// Description : Reset done. If a bit is set then a reset done signal has been
+//               returned by the peripheral. This indicates that the
+//               peripheral's registers are ready to be accessed.
+#define RESETS_RESET_DONE_OFFSET _u(0x00000008)
+#define RESETS_RESET_DONE_BITS   _u(0x01ffffff)
+#define RESETS_RESET_DONE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_USBCTRL
+// Description : None
+#define RESETS_RESET_DONE_USBCTRL_RESET  _u(0x0)
+#define RESETS_RESET_DONE_USBCTRL_BITS   _u(0x01000000)
+#define RESETS_RESET_DONE_USBCTRL_MSB    _u(24)
+#define RESETS_RESET_DONE_USBCTRL_LSB    _u(24)
+#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_UART1
+// Description : None
+#define RESETS_RESET_DONE_UART1_RESET  _u(0x0)
+#define RESETS_RESET_DONE_UART1_BITS   _u(0x00800000)
+#define RESETS_RESET_DONE_UART1_MSB    _u(23)
+#define RESETS_RESET_DONE_UART1_LSB    _u(23)
+#define RESETS_RESET_DONE_UART1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_UART0
+// Description : None
+#define RESETS_RESET_DONE_UART0_RESET  _u(0x0)
+#define RESETS_RESET_DONE_UART0_BITS   _u(0x00400000)
+#define RESETS_RESET_DONE_UART0_MSB    _u(22)
+#define RESETS_RESET_DONE_UART0_LSB    _u(22)
+#define RESETS_RESET_DONE_UART0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_TIMER
+// Description : None
+#define RESETS_RESET_DONE_TIMER_RESET  _u(0x0)
+#define RESETS_RESET_DONE_TIMER_BITS   _u(0x00200000)
+#define RESETS_RESET_DONE_TIMER_MSB    _u(21)
+#define RESETS_RESET_DONE_TIMER_LSB    _u(21)
+#define RESETS_RESET_DONE_TIMER_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_TBMAN
+// Description : None
+#define RESETS_RESET_DONE_TBMAN_RESET  _u(0x0)
+#define RESETS_RESET_DONE_TBMAN_BITS   _u(0x00100000)
+#define RESETS_RESET_DONE_TBMAN_MSB    _u(20)
+#define RESETS_RESET_DONE_TBMAN_LSB    _u(20)
+#define RESETS_RESET_DONE_TBMAN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_SYSINFO
+// Description : None
+#define RESETS_RESET_DONE_SYSINFO_RESET  _u(0x0)
+#define RESETS_RESET_DONE_SYSINFO_BITS   _u(0x00080000)
+#define RESETS_RESET_DONE_SYSINFO_MSB    _u(19)
+#define RESETS_RESET_DONE_SYSINFO_LSB    _u(19)
+#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_SYSCFG
+// Description : None
+#define RESETS_RESET_DONE_SYSCFG_RESET  _u(0x0)
+#define RESETS_RESET_DONE_SYSCFG_BITS   _u(0x00040000)
+#define RESETS_RESET_DONE_SYSCFG_MSB    _u(18)
+#define RESETS_RESET_DONE_SYSCFG_LSB    _u(18)
+#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_SPI1
+// Description : None
+#define RESETS_RESET_DONE_SPI1_RESET  _u(0x0)
+#define RESETS_RESET_DONE_SPI1_BITS   _u(0x00020000)
+#define RESETS_RESET_DONE_SPI1_MSB    _u(17)
+#define RESETS_RESET_DONE_SPI1_LSB    _u(17)
+#define RESETS_RESET_DONE_SPI1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_SPI0
+// Description : None
+#define RESETS_RESET_DONE_SPI0_RESET  _u(0x0)
+#define RESETS_RESET_DONE_SPI0_BITS   _u(0x00010000)
+#define RESETS_RESET_DONE_SPI0_MSB    _u(16)
+#define RESETS_RESET_DONE_SPI0_LSB    _u(16)
+#define RESETS_RESET_DONE_SPI0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_RTC
+// Description : None
+#define RESETS_RESET_DONE_RTC_RESET  _u(0x0)
+#define RESETS_RESET_DONE_RTC_BITS   _u(0x00008000)
+#define RESETS_RESET_DONE_RTC_MSB    _u(15)
+#define RESETS_RESET_DONE_RTC_LSB    _u(15)
+#define RESETS_RESET_DONE_RTC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_PWM
+// Description : None
+#define RESETS_RESET_DONE_PWM_RESET  _u(0x0)
+#define RESETS_RESET_DONE_PWM_BITS   _u(0x00004000)
+#define RESETS_RESET_DONE_PWM_MSB    _u(14)
+#define RESETS_RESET_DONE_PWM_LSB    _u(14)
+#define RESETS_RESET_DONE_PWM_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_PLL_USB
+// Description : None
+#define RESETS_RESET_DONE_PLL_USB_RESET  _u(0x0)
+#define RESETS_RESET_DONE_PLL_USB_BITS   _u(0x00002000)
+#define RESETS_RESET_DONE_PLL_USB_MSB    _u(13)
+#define RESETS_RESET_DONE_PLL_USB_LSB    _u(13)
+#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_PLL_SYS
+// Description : None
+#define RESETS_RESET_DONE_PLL_SYS_RESET  _u(0x0)
+#define RESETS_RESET_DONE_PLL_SYS_BITS   _u(0x00001000)
+#define RESETS_RESET_DONE_PLL_SYS_MSB    _u(12)
+#define RESETS_RESET_DONE_PLL_SYS_LSB    _u(12)
+#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_PIO1
+// Description : None
+#define RESETS_RESET_DONE_PIO1_RESET  _u(0x0)
+#define RESETS_RESET_DONE_PIO1_BITS   _u(0x00000800)
+#define RESETS_RESET_DONE_PIO1_MSB    _u(11)
+#define RESETS_RESET_DONE_PIO1_LSB    _u(11)
+#define RESETS_RESET_DONE_PIO1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_PIO0
+// Description : None
+#define RESETS_RESET_DONE_PIO0_RESET  _u(0x0)
+#define RESETS_RESET_DONE_PIO0_BITS   _u(0x00000400)
+#define RESETS_RESET_DONE_PIO0_MSB    _u(10)
+#define RESETS_RESET_DONE_PIO0_LSB    _u(10)
+#define RESETS_RESET_DONE_PIO0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_PADS_QSPI
+// Description : None
+#define RESETS_RESET_DONE_PADS_QSPI_RESET  _u(0x0)
+#define RESETS_RESET_DONE_PADS_QSPI_BITS   _u(0x00000200)
+#define RESETS_RESET_DONE_PADS_QSPI_MSB    _u(9)
+#define RESETS_RESET_DONE_PADS_QSPI_LSB    _u(9)
+#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_PADS_BANK0
+// Description : None
+#define RESETS_RESET_DONE_PADS_BANK0_RESET  _u(0x0)
+#define RESETS_RESET_DONE_PADS_BANK0_BITS   _u(0x00000100)
+#define RESETS_RESET_DONE_PADS_BANK0_MSB    _u(8)
+#define RESETS_RESET_DONE_PADS_BANK0_LSB    _u(8)
+#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_JTAG
+// Description : None
+#define RESETS_RESET_DONE_JTAG_RESET  _u(0x0)
+#define RESETS_RESET_DONE_JTAG_BITS   _u(0x00000080)
+#define RESETS_RESET_DONE_JTAG_MSB    _u(7)
+#define RESETS_RESET_DONE_JTAG_LSB    _u(7)
+#define RESETS_RESET_DONE_JTAG_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_IO_QSPI
+// Description : None
+#define RESETS_RESET_DONE_IO_QSPI_RESET  _u(0x0)
+#define RESETS_RESET_DONE_IO_QSPI_BITS   _u(0x00000040)
+#define RESETS_RESET_DONE_IO_QSPI_MSB    _u(6)
+#define RESETS_RESET_DONE_IO_QSPI_LSB    _u(6)
+#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_IO_BANK0
+// Description : None
+#define RESETS_RESET_DONE_IO_BANK0_RESET  _u(0x0)
+#define RESETS_RESET_DONE_IO_BANK0_BITS   _u(0x00000020)
+#define RESETS_RESET_DONE_IO_BANK0_MSB    _u(5)
+#define RESETS_RESET_DONE_IO_BANK0_LSB    _u(5)
+#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_I2C1
+// Description : None
+#define RESETS_RESET_DONE_I2C1_RESET  _u(0x0)
+#define RESETS_RESET_DONE_I2C1_BITS   _u(0x00000010)
+#define RESETS_RESET_DONE_I2C1_MSB    _u(4)
+#define RESETS_RESET_DONE_I2C1_LSB    _u(4)
+#define RESETS_RESET_DONE_I2C1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_I2C0
+// Description : None
+#define RESETS_RESET_DONE_I2C0_RESET  _u(0x0)
+#define RESETS_RESET_DONE_I2C0_BITS   _u(0x00000008)
+#define RESETS_RESET_DONE_I2C0_MSB    _u(3)
+#define RESETS_RESET_DONE_I2C0_LSB    _u(3)
+#define RESETS_RESET_DONE_I2C0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_DMA
+// Description : None
+#define RESETS_RESET_DONE_DMA_RESET  _u(0x0)
+#define RESETS_RESET_DONE_DMA_BITS   _u(0x00000004)
+#define RESETS_RESET_DONE_DMA_MSB    _u(2)
+#define RESETS_RESET_DONE_DMA_LSB    _u(2)
+#define RESETS_RESET_DONE_DMA_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_BUSCTRL
+// Description : None
+#define RESETS_RESET_DONE_BUSCTRL_RESET  _u(0x0)
+#define RESETS_RESET_DONE_BUSCTRL_BITS   _u(0x00000002)
+#define RESETS_RESET_DONE_BUSCTRL_MSB    _u(1)
+#define RESETS_RESET_DONE_BUSCTRL_LSB    _u(1)
+#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RESETS_RESET_DONE_ADC
+// Description : None
+#define RESETS_RESET_DONE_ADC_RESET  _u(0x0)
+#define RESETS_RESET_DONE_ADC_BITS   _u(0x00000001)
+#define RESETS_RESET_DONE_ADC_MSB    _u(0)
+#define RESETS_RESET_DONE_ADC_LSB    _u(0)
+#define RESETS_RESET_DONE_ADC_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_RESETS_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/rosc.h b/src/rp2040/hardware_regs/include/hardware/regs/rosc.h
new file mode 100644
index 0000000..5501e7e
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/rosc.h
@@ -0,0 +1,312 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : ROSC
+// Version        : 1
+// Bus type       : apb
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_ROSC_DEFINED
+#define HARDWARE_REGS_ROSC_DEFINED
+// =============================================================================
+// Register    : ROSC_CTRL
+// Description : Ring Oscillator control
+#define ROSC_CTRL_OFFSET _u(0x00000000)
+#define ROSC_CTRL_BITS   _u(0x00ffffff)
+#define ROSC_CTRL_RESET  _u(0x00000aa0)
+// -----------------------------------------------------------------------------
+// Field       : ROSC_CTRL_ENABLE
+// Description : On power-up this field is initialised to ENABLE
+//               The system clock must be switched to another source before
+//               setting this field to DISABLE otherwise the chip will lock up
+//               The 12-bit code is intended to give some protection against
+//               accidental writes. An invalid setting will enable the
+//               oscillator.
+//               0xd1e -> DISABLE
+//               0xfab -> ENABLE
+#define ROSC_CTRL_ENABLE_RESET         "-"
+#define ROSC_CTRL_ENABLE_BITS          _u(0x00fff000)
+#define ROSC_CTRL_ENABLE_MSB           _u(23)
+#define ROSC_CTRL_ENABLE_LSB           _u(12)
+#define ROSC_CTRL_ENABLE_ACCESS        "RW"
+#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
+#define ROSC_CTRL_ENABLE_VALUE_ENABLE  _u(0xfab)
+// -----------------------------------------------------------------------------
+// Field       : ROSC_CTRL_FREQ_RANGE
+// Description : Controls the number of delay stages in the ROSC ring
+//               LOW uses stages 0 to 7
+//               MEDIUM uses stages 0 to 5
+//               HIGH uses stages 0 to 3
+//               TOOHIGH uses stages 0 to 1 and should not be used because its
+//               frequency exceeds design specifications
+//               The clock output will not glitch when changing the range up one
+//               step at a time
+//               The clock output will glitch when changing the range down
+//               Note: the values here are gray coded which is why HIGH comes
+//               before TOOHIGH
+//               0xfa4 -> LOW
+//               0xfa5 -> MEDIUM
+//               0xfa7 -> HIGH
+//               0xfa6 -> TOOHIGH
+#define ROSC_CTRL_FREQ_RANGE_RESET         _u(0xaa0)
+#define ROSC_CTRL_FREQ_RANGE_BITS          _u(0x00000fff)
+#define ROSC_CTRL_FREQ_RANGE_MSB           _u(11)
+#define ROSC_CTRL_FREQ_RANGE_LSB           _u(0)
+#define ROSC_CTRL_FREQ_RANGE_ACCESS        "RW"
+#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW     _u(0xfa4)
+#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM  _u(0xfa5)
+#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH    _u(0xfa7)
+#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6)
+// =============================================================================
+// Register    : ROSC_FREQA
+// Description : The FREQA & FREQB registers control the frequency by
+//               controlling the drive strength of each stage
+//               The drive strength has 4 levels determined by the number of
+//               bits set
+//               Increasing the number of bits set increases the drive strength
+//               and increases the oscillation frequency
+//               0 bits set is the default drive strength
+//               1 bit set doubles the drive strength
+//               2 bits set triples drive strength
+//               3 bits set quadruples drive strength
+#define ROSC_FREQA_OFFSET _u(0x00000004)
+#define ROSC_FREQA_BITS   _u(0xffff7777)
+#define ROSC_FREQA_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : ROSC_FREQA_PASSWD
+// Description : Set to 0x9696 to apply the settings
+//               Any other value in this field will set all drive strengths to 0
+//               0x9696 -> PASS
+#define ROSC_FREQA_PASSWD_RESET      _u(0x0000)
+#define ROSC_FREQA_PASSWD_BITS       _u(0xffff0000)
+#define ROSC_FREQA_PASSWD_MSB        _u(31)
+#define ROSC_FREQA_PASSWD_LSB        _u(16)
+#define ROSC_FREQA_PASSWD_ACCESS     "RW"
+#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696)
+// -----------------------------------------------------------------------------
+// Field       : ROSC_FREQA_DS3
+// Description : Stage 3 drive strength
+#define ROSC_FREQA_DS3_RESET  _u(0x0)
+#define ROSC_FREQA_DS3_BITS   _u(0x00007000)
+#define ROSC_FREQA_DS3_MSB    _u(14)
+#define ROSC_FREQA_DS3_LSB    _u(12)
+#define ROSC_FREQA_DS3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ROSC_FREQA_DS2
+// Description : Stage 2 drive strength
+#define ROSC_FREQA_DS2_RESET  _u(0x0)
+#define ROSC_FREQA_DS2_BITS   _u(0x00000700)
+#define ROSC_FREQA_DS2_MSB    _u(10)
+#define ROSC_FREQA_DS2_LSB    _u(8)
+#define ROSC_FREQA_DS2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ROSC_FREQA_DS1
+// Description : Stage 1 drive strength
+#define ROSC_FREQA_DS1_RESET  _u(0x0)
+#define ROSC_FREQA_DS1_BITS   _u(0x00000070)
+#define ROSC_FREQA_DS1_MSB    _u(6)
+#define ROSC_FREQA_DS1_LSB    _u(4)
+#define ROSC_FREQA_DS1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ROSC_FREQA_DS0
+// Description : Stage 0 drive strength
+#define ROSC_FREQA_DS0_RESET  _u(0x0)
+#define ROSC_FREQA_DS0_BITS   _u(0x00000007)
+#define ROSC_FREQA_DS0_MSB    _u(2)
+#define ROSC_FREQA_DS0_LSB    _u(0)
+#define ROSC_FREQA_DS0_ACCESS "RW"
+// =============================================================================
+// Register    : ROSC_FREQB
+// Description : For a detailed description see freqa register
+#define ROSC_FREQB_OFFSET _u(0x00000008)
+#define ROSC_FREQB_BITS   _u(0xffff7777)
+#define ROSC_FREQB_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : ROSC_FREQB_PASSWD
+// Description : Set to 0x9696 to apply the settings
+//               Any other value in this field will set all drive strengths to 0
+//               0x9696 -> PASS
+#define ROSC_FREQB_PASSWD_RESET      _u(0x0000)
+#define ROSC_FREQB_PASSWD_BITS       _u(0xffff0000)
+#define ROSC_FREQB_PASSWD_MSB        _u(31)
+#define ROSC_FREQB_PASSWD_LSB        _u(16)
+#define ROSC_FREQB_PASSWD_ACCESS     "RW"
+#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696)
+// -----------------------------------------------------------------------------
+// Field       : ROSC_FREQB_DS7
+// Description : Stage 7 drive strength
+#define ROSC_FREQB_DS7_RESET  _u(0x0)
+#define ROSC_FREQB_DS7_BITS   _u(0x00007000)
+#define ROSC_FREQB_DS7_MSB    _u(14)
+#define ROSC_FREQB_DS7_LSB    _u(12)
+#define ROSC_FREQB_DS7_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ROSC_FREQB_DS6
+// Description : Stage 6 drive strength
+#define ROSC_FREQB_DS6_RESET  _u(0x0)
+#define ROSC_FREQB_DS6_BITS   _u(0x00000700)
+#define ROSC_FREQB_DS6_MSB    _u(10)
+#define ROSC_FREQB_DS6_LSB    _u(8)
+#define ROSC_FREQB_DS6_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ROSC_FREQB_DS5
+// Description : Stage 5 drive strength
+#define ROSC_FREQB_DS5_RESET  _u(0x0)
+#define ROSC_FREQB_DS5_BITS   _u(0x00000070)
+#define ROSC_FREQB_DS5_MSB    _u(6)
+#define ROSC_FREQB_DS5_LSB    _u(4)
+#define ROSC_FREQB_DS5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ROSC_FREQB_DS4
+// Description : Stage 4 drive strength
+#define ROSC_FREQB_DS4_RESET  _u(0x0)
+#define ROSC_FREQB_DS4_BITS   _u(0x00000007)
+#define ROSC_FREQB_DS4_MSB    _u(2)
+#define ROSC_FREQB_DS4_LSB    _u(0)
+#define ROSC_FREQB_DS4_ACCESS "RW"
+// =============================================================================
+// Register    : ROSC_DORMANT
+// Description : Ring Oscillator pause control
+//               This is used to save power by pausing the ROSC
+//               On power-up this field is initialised to WAKE
+//               An invalid write will also select WAKE
+//               Warning: setup the irq before selecting dormant mode
+//               0x636f6d61 -> DORMANT
+//               0x77616b65 -> WAKE
+#define ROSC_DORMANT_OFFSET        _u(0x0000000c)
+#define ROSC_DORMANT_BITS          _u(0xffffffff)
+#define ROSC_DORMANT_RESET         "-"
+#define ROSC_DORMANT_MSB           _u(31)
+#define ROSC_DORMANT_LSB           _u(0)
+#define ROSC_DORMANT_ACCESS        "RW"
+#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
+#define ROSC_DORMANT_VALUE_WAKE    _u(0x77616b65)
+// =============================================================================
+// Register    : ROSC_DIV
+// Description : Controls the output divider
+//               set to 0xaa0 + div where
+//               div = 0 divides by 32
+//               div = 1-31 divides by div
+//               any other value sets div=31
+//               this register resets to div=16
+//               0xaa0 -> PASS
+#define ROSC_DIV_OFFSET     _u(0x00000010)
+#define ROSC_DIV_BITS       _u(0x00000fff)
+#define ROSC_DIV_RESET      "-"
+#define ROSC_DIV_MSB        _u(11)
+#define ROSC_DIV_LSB        _u(0)
+#define ROSC_DIV_ACCESS     "RW"
+#define ROSC_DIV_VALUE_PASS _u(0xaa0)
+// =============================================================================
+// Register    : ROSC_PHASE
+// Description : Controls the phase shifted output
+#define ROSC_PHASE_OFFSET _u(0x00000014)
+#define ROSC_PHASE_BITS   _u(0x00000fff)
+#define ROSC_PHASE_RESET  _u(0x00000008)
+// -----------------------------------------------------------------------------
+// Field       : ROSC_PHASE_PASSWD
+// Description : set to 0xaa
+//               any other value enables the output with shift=0
+#define ROSC_PHASE_PASSWD_RESET  _u(0x00)
+#define ROSC_PHASE_PASSWD_BITS   _u(0x00000ff0)
+#define ROSC_PHASE_PASSWD_MSB    _u(11)
+#define ROSC_PHASE_PASSWD_LSB    _u(4)
+#define ROSC_PHASE_PASSWD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ROSC_PHASE_ENABLE
+// Description : enable the phase-shifted output
+//               this can be changed on-the-fly
+#define ROSC_PHASE_ENABLE_RESET  _u(0x1)
+#define ROSC_PHASE_ENABLE_BITS   _u(0x00000008)
+#define ROSC_PHASE_ENABLE_MSB    _u(3)
+#define ROSC_PHASE_ENABLE_LSB    _u(3)
+#define ROSC_PHASE_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ROSC_PHASE_FLIP
+// Description : invert the phase-shifted output
+//               this is ignored when div=1
+#define ROSC_PHASE_FLIP_RESET  _u(0x0)
+#define ROSC_PHASE_FLIP_BITS   _u(0x00000004)
+#define ROSC_PHASE_FLIP_MSB    _u(2)
+#define ROSC_PHASE_FLIP_LSB    _u(2)
+#define ROSC_PHASE_FLIP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : ROSC_PHASE_SHIFT
+// Description : phase shift the phase-shifted output by SHIFT input clocks
+//               this can be changed on-the-fly
+//               must be set to 0 before setting div=1
+#define ROSC_PHASE_SHIFT_RESET  _u(0x0)
+#define ROSC_PHASE_SHIFT_BITS   _u(0x00000003)
+#define ROSC_PHASE_SHIFT_MSB    _u(1)
+#define ROSC_PHASE_SHIFT_LSB    _u(0)
+#define ROSC_PHASE_SHIFT_ACCESS "RW"
+// =============================================================================
+// Register    : ROSC_STATUS
+// Description : Ring Oscillator Status
+#define ROSC_STATUS_OFFSET _u(0x00000018)
+#define ROSC_STATUS_BITS   _u(0x81011000)
+#define ROSC_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : ROSC_STATUS_STABLE
+// Description : Oscillator is running and stable
+#define ROSC_STATUS_STABLE_RESET  _u(0x0)
+#define ROSC_STATUS_STABLE_BITS   _u(0x80000000)
+#define ROSC_STATUS_STABLE_MSB    _u(31)
+#define ROSC_STATUS_STABLE_LSB    _u(31)
+#define ROSC_STATUS_STABLE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : ROSC_STATUS_BADWRITE
+// Description : An invalid value has been written to CTRL_ENABLE or
+//               CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT
+#define ROSC_STATUS_BADWRITE_RESET  _u(0x0)
+#define ROSC_STATUS_BADWRITE_BITS   _u(0x01000000)
+#define ROSC_STATUS_BADWRITE_MSB    _u(24)
+#define ROSC_STATUS_BADWRITE_LSB    _u(24)
+#define ROSC_STATUS_BADWRITE_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : ROSC_STATUS_DIV_RUNNING
+// Description : post-divider is running
+//               this resets to 0 but transitions to 1 during chip startup
+#define ROSC_STATUS_DIV_RUNNING_RESET  "-"
+#define ROSC_STATUS_DIV_RUNNING_BITS   _u(0x00010000)
+#define ROSC_STATUS_DIV_RUNNING_MSB    _u(16)
+#define ROSC_STATUS_DIV_RUNNING_LSB    _u(16)
+#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : ROSC_STATUS_ENABLED
+// Description : Oscillator is enabled but not necessarily running and stable
+//               this resets to 0 but transitions to 1 during chip startup
+#define ROSC_STATUS_ENABLED_RESET  "-"
+#define ROSC_STATUS_ENABLED_BITS   _u(0x00001000)
+#define ROSC_STATUS_ENABLED_MSB    _u(12)
+#define ROSC_STATUS_ENABLED_LSB    _u(12)
+#define ROSC_STATUS_ENABLED_ACCESS "RO"
+// =============================================================================
+// Register    : ROSC_RANDOMBIT
+// Description : This just reads the state of the oscillator output so
+//               randomness is compromised if the ring oscillator is stopped or
+//               run at a harmonic of the bus frequency
+#define ROSC_RANDOMBIT_OFFSET _u(0x0000001c)
+#define ROSC_RANDOMBIT_BITS   _u(0x00000001)
+#define ROSC_RANDOMBIT_RESET  _u(0x00000001)
+#define ROSC_RANDOMBIT_MSB    _u(0)
+#define ROSC_RANDOMBIT_LSB    _u(0)
+#define ROSC_RANDOMBIT_ACCESS "RO"
+// =============================================================================
+// Register    : ROSC_COUNT
+// Description : A down counter running at the ROSC frequency which counts to
+//               zero and stops.
+//               To start the counter write a non-zero value.
+//               Can be used for short software pauses when setting up time
+//               sensitive hardware.
+#define ROSC_COUNT_OFFSET _u(0x00000020)
+#define ROSC_COUNT_BITS   _u(0x000000ff)
+#define ROSC_COUNT_RESET  _u(0x00000000)
+#define ROSC_COUNT_MSB    _u(7)
+#define ROSC_COUNT_LSB    _u(0)
+#define ROSC_COUNT_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_ROSC_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/rtc.h b/src/rp2040/hardware_regs/include/hardware/regs/rtc.h
new file mode 100644
index 0000000..7d62c9d
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/rtc.h
@@ -0,0 +1,398 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : RTC
+// Version        : 1
+// Bus type       : apb
+// Description    : Register block to control RTC
+// =============================================================================
+#ifndef HARDWARE_REGS_RTC_DEFINED
+#define HARDWARE_REGS_RTC_DEFINED
+// =============================================================================
+// Register    : RTC_CLKDIV_M1
+// Description : Divider minus 1 for the 1 second counter. Safe to change the
+//               value when RTC is not enabled.
+#define RTC_CLKDIV_M1_OFFSET _u(0x00000000)
+#define RTC_CLKDIV_M1_BITS   _u(0x0000ffff)
+#define RTC_CLKDIV_M1_RESET  _u(0x00000000)
+#define RTC_CLKDIV_M1_MSB    _u(15)
+#define RTC_CLKDIV_M1_LSB    _u(0)
+#define RTC_CLKDIV_M1_ACCESS "RW"
+// =============================================================================
+// Register    : RTC_SETUP_0
+// Description : RTC setup register 0
+#define RTC_SETUP_0_OFFSET _u(0x00000004)
+#define RTC_SETUP_0_BITS   _u(0x00ffff1f)
+#define RTC_SETUP_0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : RTC_SETUP_0_YEAR
+// Description : Year
+#define RTC_SETUP_0_YEAR_RESET  _u(0x000)
+#define RTC_SETUP_0_YEAR_BITS   _u(0x00fff000)
+#define RTC_SETUP_0_YEAR_MSB    _u(23)
+#define RTC_SETUP_0_YEAR_LSB    _u(12)
+#define RTC_SETUP_0_YEAR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_SETUP_0_MONTH
+// Description : Month (1..12)
+#define RTC_SETUP_0_MONTH_RESET  _u(0x0)
+#define RTC_SETUP_0_MONTH_BITS   _u(0x00000f00)
+#define RTC_SETUP_0_MONTH_MSB    _u(11)
+#define RTC_SETUP_0_MONTH_LSB    _u(8)
+#define RTC_SETUP_0_MONTH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_SETUP_0_DAY
+// Description : Day of the month (1..31)
+#define RTC_SETUP_0_DAY_RESET  _u(0x00)
+#define RTC_SETUP_0_DAY_BITS   _u(0x0000001f)
+#define RTC_SETUP_0_DAY_MSB    _u(4)
+#define RTC_SETUP_0_DAY_LSB    _u(0)
+#define RTC_SETUP_0_DAY_ACCESS "RW"
+// =============================================================================
+// Register    : RTC_SETUP_1
+// Description : RTC setup register 1
+#define RTC_SETUP_1_OFFSET _u(0x00000008)
+#define RTC_SETUP_1_BITS   _u(0x071f3f3f)
+#define RTC_SETUP_1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : RTC_SETUP_1_DOTW
+// Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7
+#define RTC_SETUP_1_DOTW_RESET  _u(0x0)
+#define RTC_SETUP_1_DOTW_BITS   _u(0x07000000)
+#define RTC_SETUP_1_DOTW_MSB    _u(26)
+#define RTC_SETUP_1_DOTW_LSB    _u(24)
+#define RTC_SETUP_1_DOTW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_SETUP_1_HOUR
+// Description : Hours
+#define RTC_SETUP_1_HOUR_RESET  _u(0x00)
+#define RTC_SETUP_1_HOUR_BITS   _u(0x001f0000)
+#define RTC_SETUP_1_HOUR_MSB    _u(20)
+#define RTC_SETUP_1_HOUR_LSB    _u(16)
+#define RTC_SETUP_1_HOUR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_SETUP_1_MIN
+// Description : Minutes
+#define RTC_SETUP_1_MIN_RESET  _u(0x00)
+#define RTC_SETUP_1_MIN_BITS   _u(0x00003f00)
+#define RTC_SETUP_1_MIN_MSB    _u(13)
+#define RTC_SETUP_1_MIN_LSB    _u(8)
+#define RTC_SETUP_1_MIN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_SETUP_1_SEC
+// Description : Seconds
+#define RTC_SETUP_1_SEC_RESET  _u(0x00)
+#define RTC_SETUP_1_SEC_BITS   _u(0x0000003f)
+#define RTC_SETUP_1_SEC_MSB    _u(5)
+#define RTC_SETUP_1_SEC_LSB    _u(0)
+#define RTC_SETUP_1_SEC_ACCESS "RW"
+// =============================================================================
+// Register    : RTC_CTRL
+// Description : RTC Control and status
+#define RTC_CTRL_OFFSET _u(0x0000000c)
+#define RTC_CTRL_BITS   _u(0x00000113)
+#define RTC_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : RTC_CTRL_FORCE_NOTLEAPYEAR
+// Description : If set, leapyear is forced off.
+//               Useful for years divisible by 100 but not by 400
+#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET  _u(0x0)
+#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS   _u(0x00000100)
+#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB    _u(8)
+#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB    _u(8)
+#define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_CTRL_LOAD
+// Description : Load RTC
+#define RTC_CTRL_LOAD_RESET  _u(0x0)
+#define RTC_CTRL_LOAD_BITS   _u(0x00000010)
+#define RTC_CTRL_LOAD_MSB    _u(4)
+#define RTC_CTRL_LOAD_LSB    _u(4)
+#define RTC_CTRL_LOAD_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : RTC_CTRL_RTC_ACTIVE
+// Description : RTC enabled (running)
+#define RTC_CTRL_RTC_ACTIVE_RESET  "-"
+#define RTC_CTRL_RTC_ACTIVE_BITS   _u(0x00000002)
+#define RTC_CTRL_RTC_ACTIVE_MSB    _u(1)
+#define RTC_CTRL_RTC_ACTIVE_LSB    _u(1)
+#define RTC_CTRL_RTC_ACTIVE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RTC_CTRL_RTC_ENABLE
+// Description : Enable RTC
+#define RTC_CTRL_RTC_ENABLE_RESET  _u(0x0)
+#define RTC_CTRL_RTC_ENABLE_BITS   _u(0x00000001)
+#define RTC_CTRL_RTC_ENABLE_MSB    _u(0)
+#define RTC_CTRL_RTC_ENABLE_LSB    _u(0)
+#define RTC_CTRL_RTC_ENABLE_ACCESS "RW"
+// =============================================================================
+// Register    : RTC_IRQ_SETUP_0
+// Description : Interrupt setup register 0
+#define RTC_IRQ_SETUP_0_OFFSET _u(0x00000010)
+#define RTC_IRQ_SETUP_0_BITS   _u(0x37ffff1f)
+#define RTC_IRQ_SETUP_0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_0_MATCH_ACTIVE
+// Description : None
+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET  "-"
+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS   _u(0x20000000)
+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB    _u(29)
+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB    _u(29)
+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_0_MATCH_ENA
+// Description : Global match enable. Don't change any other value while this
+//               one is enabled
+#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET  _u(0x0)
+#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS   _u(0x10000000)
+#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB    _u(28)
+#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB    _u(28)
+#define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_0_YEAR_ENA
+// Description : Enable year matching
+#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET  _u(0x0)
+#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS   _u(0x04000000)
+#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB    _u(26)
+#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB    _u(26)
+#define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_0_MONTH_ENA
+// Description : Enable month matching
+#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET  _u(0x0)
+#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS   _u(0x02000000)
+#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB    _u(25)
+#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB    _u(25)
+#define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_0_DAY_ENA
+// Description : Enable day matching
+#define RTC_IRQ_SETUP_0_DAY_ENA_RESET  _u(0x0)
+#define RTC_IRQ_SETUP_0_DAY_ENA_BITS   _u(0x01000000)
+#define RTC_IRQ_SETUP_0_DAY_ENA_MSB    _u(24)
+#define RTC_IRQ_SETUP_0_DAY_ENA_LSB    _u(24)
+#define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_0_YEAR
+// Description : Year
+#define RTC_IRQ_SETUP_0_YEAR_RESET  _u(0x000)
+#define RTC_IRQ_SETUP_0_YEAR_BITS   _u(0x00fff000)
+#define RTC_IRQ_SETUP_0_YEAR_MSB    _u(23)
+#define RTC_IRQ_SETUP_0_YEAR_LSB    _u(12)
+#define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_0_MONTH
+// Description : Month (1..12)
+#define RTC_IRQ_SETUP_0_MONTH_RESET  _u(0x0)
+#define RTC_IRQ_SETUP_0_MONTH_BITS   _u(0x00000f00)
+#define RTC_IRQ_SETUP_0_MONTH_MSB    _u(11)
+#define RTC_IRQ_SETUP_0_MONTH_LSB    _u(8)
+#define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_0_DAY
+// Description : Day of the month (1..31)
+#define RTC_IRQ_SETUP_0_DAY_RESET  _u(0x00)
+#define RTC_IRQ_SETUP_0_DAY_BITS   _u(0x0000001f)
+#define RTC_IRQ_SETUP_0_DAY_MSB    _u(4)
+#define RTC_IRQ_SETUP_0_DAY_LSB    _u(0)
+#define RTC_IRQ_SETUP_0_DAY_ACCESS "RW"
+// =============================================================================
+// Register    : RTC_IRQ_SETUP_1
+// Description : Interrupt setup register 1
+#define RTC_IRQ_SETUP_1_OFFSET _u(0x00000014)
+#define RTC_IRQ_SETUP_1_BITS   _u(0xf71f3f3f)
+#define RTC_IRQ_SETUP_1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_1_DOTW_ENA
+// Description : Enable day of the week matching
+#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET  _u(0x0)
+#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS   _u(0x80000000)
+#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB    _u(31)
+#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB    _u(31)
+#define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_1_HOUR_ENA
+// Description : Enable hour matching
+#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET  _u(0x0)
+#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS   _u(0x40000000)
+#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB    _u(30)
+#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB    _u(30)
+#define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_1_MIN_ENA
+// Description : Enable minute matching
+#define RTC_IRQ_SETUP_1_MIN_ENA_RESET  _u(0x0)
+#define RTC_IRQ_SETUP_1_MIN_ENA_BITS   _u(0x20000000)
+#define RTC_IRQ_SETUP_1_MIN_ENA_MSB    _u(29)
+#define RTC_IRQ_SETUP_1_MIN_ENA_LSB    _u(29)
+#define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_1_SEC_ENA
+// Description : Enable second matching
+#define RTC_IRQ_SETUP_1_SEC_ENA_RESET  _u(0x0)
+#define RTC_IRQ_SETUP_1_SEC_ENA_BITS   _u(0x10000000)
+#define RTC_IRQ_SETUP_1_SEC_ENA_MSB    _u(28)
+#define RTC_IRQ_SETUP_1_SEC_ENA_LSB    _u(28)
+#define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_1_DOTW
+// Description : Day of the week
+#define RTC_IRQ_SETUP_1_DOTW_RESET  _u(0x0)
+#define RTC_IRQ_SETUP_1_DOTW_BITS   _u(0x07000000)
+#define RTC_IRQ_SETUP_1_DOTW_MSB    _u(26)
+#define RTC_IRQ_SETUP_1_DOTW_LSB    _u(24)
+#define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_1_HOUR
+// Description : Hours
+#define RTC_IRQ_SETUP_1_HOUR_RESET  _u(0x00)
+#define RTC_IRQ_SETUP_1_HOUR_BITS   _u(0x001f0000)
+#define RTC_IRQ_SETUP_1_HOUR_MSB    _u(20)
+#define RTC_IRQ_SETUP_1_HOUR_LSB    _u(16)
+#define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_1_MIN
+// Description : Minutes
+#define RTC_IRQ_SETUP_1_MIN_RESET  _u(0x00)
+#define RTC_IRQ_SETUP_1_MIN_BITS   _u(0x00003f00)
+#define RTC_IRQ_SETUP_1_MIN_MSB    _u(13)
+#define RTC_IRQ_SETUP_1_MIN_LSB    _u(8)
+#define RTC_IRQ_SETUP_1_MIN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : RTC_IRQ_SETUP_1_SEC
+// Description : Seconds
+#define RTC_IRQ_SETUP_1_SEC_RESET  _u(0x00)
+#define RTC_IRQ_SETUP_1_SEC_BITS   _u(0x0000003f)
+#define RTC_IRQ_SETUP_1_SEC_MSB    _u(5)
+#define RTC_IRQ_SETUP_1_SEC_LSB    _u(0)
+#define RTC_IRQ_SETUP_1_SEC_ACCESS "RW"
+// =============================================================================
+// Register    : RTC_RTC_1
+// Description : RTC register 1.
+#define RTC_RTC_1_OFFSET _u(0x00000018)
+#define RTC_RTC_1_BITS   _u(0x00ffff1f)
+#define RTC_RTC_1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : RTC_RTC_1_YEAR
+// Description : Year
+#define RTC_RTC_1_YEAR_RESET  "-"
+#define RTC_RTC_1_YEAR_BITS   _u(0x00fff000)
+#define RTC_RTC_1_YEAR_MSB    _u(23)
+#define RTC_RTC_1_YEAR_LSB    _u(12)
+#define RTC_RTC_1_YEAR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RTC_RTC_1_MONTH
+// Description : Month (1..12)
+#define RTC_RTC_1_MONTH_RESET  "-"
+#define RTC_RTC_1_MONTH_BITS   _u(0x00000f00)
+#define RTC_RTC_1_MONTH_MSB    _u(11)
+#define RTC_RTC_1_MONTH_LSB    _u(8)
+#define RTC_RTC_1_MONTH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : RTC_RTC_1_DAY
+// Description : Day of the month (1..31)
+#define RTC_RTC_1_DAY_RESET  "-"
+#define RTC_RTC_1_DAY_BITS   _u(0x0000001f)
+#define RTC_RTC_1_DAY_MSB    _u(4)
+#define RTC_RTC_1_DAY_LSB    _u(0)
+#define RTC_RTC_1_DAY_ACCESS "RO"
+// =============================================================================
+// Register    : RTC_RTC_0
+// Description : RTC register 0
+//               Read this before RTC 1!
+#define RTC_RTC_0_OFFSET _u(0x0000001c)
+#define RTC_RTC_0_BITS   _u(0x071f3f3f)
+#define RTC_RTC_0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : RTC_RTC_0_DOTW
+// Description : Day of the week
+#define RTC_RTC_0_DOTW_RESET  "-"
+#define RTC_RTC_0_DOTW_BITS   _u(0x07000000)
+#define RTC_RTC_0_DOTW_MSB    _u(26)
+#define RTC_RTC_0_DOTW_LSB    _u(24)
+#define RTC_RTC_0_DOTW_ACCESS "RF"
+// -----------------------------------------------------------------------------
+// Field       : RTC_RTC_0_HOUR
+// Description : Hours
+#define RTC_RTC_0_HOUR_RESET  "-"
+#define RTC_RTC_0_HOUR_BITS   _u(0x001f0000)
+#define RTC_RTC_0_HOUR_MSB    _u(20)
+#define RTC_RTC_0_HOUR_LSB    _u(16)
+#define RTC_RTC_0_HOUR_ACCESS "RF"
+// -----------------------------------------------------------------------------
+// Field       : RTC_RTC_0_MIN
+// Description : Minutes
+#define RTC_RTC_0_MIN_RESET  "-"
+#define RTC_RTC_0_MIN_BITS   _u(0x00003f00)
+#define RTC_RTC_0_MIN_MSB    _u(13)
+#define RTC_RTC_0_MIN_LSB    _u(8)
+#define RTC_RTC_0_MIN_ACCESS "RF"
+// -----------------------------------------------------------------------------
+// Field       : RTC_RTC_0_SEC
+// Description : Seconds
+#define RTC_RTC_0_SEC_RESET  "-"
+#define RTC_RTC_0_SEC_BITS   _u(0x0000003f)
+#define RTC_RTC_0_SEC_MSB    _u(5)
+#define RTC_RTC_0_SEC_LSB    _u(0)
+#define RTC_RTC_0_SEC_ACCESS "RF"
+// =============================================================================
+// Register    : RTC_INTR
+// Description : Raw Interrupts
+#define RTC_INTR_OFFSET _u(0x00000020)
+#define RTC_INTR_BITS   _u(0x00000001)
+#define RTC_INTR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : RTC_INTR_RTC
+// Description : None
+#define RTC_INTR_RTC_RESET  _u(0x0)
+#define RTC_INTR_RTC_BITS   _u(0x00000001)
+#define RTC_INTR_RTC_MSB    _u(0)
+#define RTC_INTR_RTC_LSB    _u(0)
+#define RTC_INTR_RTC_ACCESS "RO"
+// =============================================================================
+// Register    : RTC_INTE
+// Description : Interrupt Enable
+#define RTC_INTE_OFFSET _u(0x00000024)
+#define RTC_INTE_BITS   _u(0x00000001)
+#define RTC_INTE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : RTC_INTE_RTC
+// Description : None
+#define RTC_INTE_RTC_RESET  _u(0x0)
+#define RTC_INTE_RTC_BITS   _u(0x00000001)
+#define RTC_INTE_RTC_MSB    _u(0)
+#define RTC_INTE_RTC_LSB    _u(0)
+#define RTC_INTE_RTC_ACCESS "RW"
+// =============================================================================
+// Register    : RTC_INTF
+// Description : Interrupt Force
+#define RTC_INTF_OFFSET _u(0x00000028)
+#define RTC_INTF_BITS   _u(0x00000001)
+#define RTC_INTF_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : RTC_INTF_RTC
+// Description : None
+#define RTC_INTF_RTC_RESET  _u(0x0)
+#define RTC_INTF_RTC_BITS   _u(0x00000001)
+#define RTC_INTF_RTC_MSB    _u(0)
+#define RTC_INTF_RTC_LSB    _u(0)
+#define RTC_INTF_RTC_ACCESS "RW"
+// =============================================================================
+// Register    : RTC_INTS
+// Description : Interrupt status after masking & forcing
+#define RTC_INTS_OFFSET _u(0x0000002c)
+#define RTC_INTS_BITS   _u(0x00000001)
+#define RTC_INTS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : RTC_INTS_RTC
+// Description : None
+#define RTC_INTS_RTC_RESET  _u(0x0)
+#define RTC_INTS_RTC_BITS   _u(0x00000001)
+#define RTC_INTS_RTC_MSB    _u(0)
+#define RTC_INTS_RTC_LSB    _u(0)
+#define RTC_INTS_RTC_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_RTC_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/sio.h b/src/rp2040/hardware_regs/include/hardware/regs/sio.h
new file mode 100644
index 0000000..f641533
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/sio.h
@@ -0,0 +1,1656 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : SIO
+// Version        : 1
+// Bus type       : apb
+// Description    : Single-cycle IO block
+//                  Provides core-local and inter-core hardware for the two
+//                  processors, with single-cycle access.
+// =============================================================================
+#ifndef HARDWARE_REGS_SIO_DEFINED
+#define HARDWARE_REGS_SIO_DEFINED
+// =============================================================================
+// Register    : SIO_CPUID
+// Description : Processor core identifier
+//               Value is 0 when read from processor core 0, and 1 when read
+//               from processor core 1.
+#define SIO_CPUID_OFFSET _u(0x00000000)
+#define SIO_CPUID_BITS   _u(0xffffffff)
+#define SIO_CPUID_RESET  "-"
+#define SIO_CPUID_MSB    _u(31)
+#define SIO_CPUID_LSB    _u(0)
+#define SIO_CPUID_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_GPIO_IN
+// Description : Input value for GPIO pins
+//               Input value for GPIO0...29
+#define SIO_GPIO_IN_OFFSET _u(0x00000004)
+#define SIO_GPIO_IN_BITS   _u(0x3fffffff)
+#define SIO_GPIO_IN_RESET  _u(0x00000000)
+#define SIO_GPIO_IN_MSB    _u(29)
+#define SIO_GPIO_IN_LSB    _u(0)
+#define SIO_GPIO_IN_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_GPIO_HI_IN
+// Description : Input value for QSPI pins
+//               Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2,
+//               SD3
+#define SIO_GPIO_HI_IN_OFFSET _u(0x00000008)
+#define SIO_GPIO_HI_IN_BITS   _u(0x0000003f)
+#define SIO_GPIO_HI_IN_RESET  _u(0x00000000)
+#define SIO_GPIO_HI_IN_MSB    _u(5)
+#define SIO_GPIO_HI_IN_LSB    _u(0)
+#define SIO_GPIO_HI_IN_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_GPIO_OUT
+// Description : GPIO output value
+//               Set output level (1/0 -> high/low) for GPIO0...29.
+//               Reading back gives the last value written, NOT the input value
+//               from the pins.
+//               If core 0 and core 1 both write to GPIO_OUT simultaneously (or
+//               to a SET/CLR/XOR alias),
+//               the result is as though the write from core 0 took place first,
+//               and the write from core 1 was then applied to that intermediate
+//               result.
+#define SIO_GPIO_OUT_OFFSET _u(0x00000010)
+#define SIO_GPIO_OUT_BITS   _u(0x3fffffff)
+#define SIO_GPIO_OUT_RESET  _u(0x00000000)
+#define SIO_GPIO_OUT_MSB    _u(29)
+#define SIO_GPIO_OUT_LSB    _u(0)
+#define SIO_GPIO_OUT_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_GPIO_OUT_SET
+// Description : GPIO output value set
+//               Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`
+#define SIO_GPIO_OUT_SET_OFFSET _u(0x00000014)
+#define SIO_GPIO_OUT_SET_BITS   _u(0x3fffffff)
+#define SIO_GPIO_OUT_SET_RESET  _u(0x00000000)
+#define SIO_GPIO_OUT_SET_MSB    _u(29)
+#define SIO_GPIO_OUT_SET_LSB    _u(0)
+#define SIO_GPIO_OUT_SET_ACCESS "WO"
+// =============================================================================
+// Register    : SIO_GPIO_OUT_CLR
+// Description : GPIO output value clear
+//               Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &=
+//               ~wdata`
+#define SIO_GPIO_OUT_CLR_OFFSET _u(0x00000018)
+#define SIO_GPIO_OUT_CLR_BITS   _u(0x3fffffff)
+#define SIO_GPIO_OUT_CLR_RESET  _u(0x00000000)
+#define SIO_GPIO_OUT_CLR_MSB    _u(29)
+#define SIO_GPIO_OUT_CLR_LSB    _u(0)
+#define SIO_GPIO_OUT_CLR_ACCESS "WO"
+// =============================================================================
+// Register    : SIO_GPIO_OUT_XOR
+// Description : GPIO output value XOR
+//               Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^=
+//               wdata`
+#define SIO_GPIO_OUT_XOR_OFFSET _u(0x0000001c)
+#define SIO_GPIO_OUT_XOR_BITS   _u(0x3fffffff)
+#define SIO_GPIO_OUT_XOR_RESET  _u(0x00000000)
+#define SIO_GPIO_OUT_XOR_MSB    _u(29)
+#define SIO_GPIO_OUT_XOR_LSB    _u(0)
+#define SIO_GPIO_OUT_XOR_ACCESS "WO"
+// =============================================================================
+// Register    : SIO_GPIO_OE
+// Description : GPIO output enable
+//               Set output enable (1/0 -> output/input) for GPIO0...29.
+//               Reading back gives the last value written.
+//               If core 0 and core 1 both write to GPIO_OE simultaneously (or
+//               to a SET/CLR/XOR alias),
+//               the result is as though the write from core 0 took place first,
+//               and the write from core 1 was then applied to that intermediate
+//               result.
+#define SIO_GPIO_OE_OFFSET _u(0x00000020)
+#define SIO_GPIO_OE_BITS   _u(0x3fffffff)
+#define SIO_GPIO_OE_RESET  _u(0x00000000)
+#define SIO_GPIO_OE_MSB    _u(29)
+#define SIO_GPIO_OE_LSB    _u(0)
+#define SIO_GPIO_OE_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_GPIO_OE_SET
+// Description : GPIO output enable set
+//               Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`
+#define SIO_GPIO_OE_SET_OFFSET _u(0x00000024)
+#define SIO_GPIO_OE_SET_BITS   _u(0x3fffffff)
+#define SIO_GPIO_OE_SET_RESET  _u(0x00000000)
+#define SIO_GPIO_OE_SET_MSB    _u(29)
+#define SIO_GPIO_OE_SET_LSB    _u(0)
+#define SIO_GPIO_OE_SET_ACCESS "WO"
+// =============================================================================
+// Register    : SIO_GPIO_OE_CLR
+// Description : GPIO output enable clear
+//               Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &=
+//               ~wdata`
+#define SIO_GPIO_OE_CLR_OFFSET _u(0x00000028)
+#define SIO_GPIO_OE_CLR_BITS   _u(0x3fffffff)
+#define SIO_GPIO_OE_CLR_RESET  _u(0x00000000)
+#define SIO_GPIO_OE_CLR_MSB    _u(29)
+#define SIO_GPIO_OE_CLR_LSB    _u(0)
+#define SIO_GPIO_OE_CLR_ACCESS "WO"
+// =============================================================================
+// Register    : SIO_GPIO_OE_XOR
+// Description : GPIO output enable XOR
+//               Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^=
+//               wdata`
+#define SIO_GPIO_OE_XOR_OFFSET _u(0x0000002c)
+#define SIO_GPIO_OE_XOR_BITS   _u(0x3fffffff)
+#define SIO_GPIO_OE_XOR_RESET  _u(0x00000000)
+#define SIO_GPIO_OE_XOR_MSB    _u(29)
+#define SIO_GPIO_OE_XOR_LSB    _u(0)
+#define SIO_GPIO_OE_XOR_ACCESS "WO"
+// =============================================================================
+// Register    : SIO_GPIO_HI_OUT
+// Description : QSPI output value
+//               Set output level (1/0 -> high/low) for QSPI IO0...5.
+//               Reading back gives the last value written, NOT the input value
+//               from the pins.
+//               If core 0 and core 1 both write to GPIO_HI_OUT simultaneously
+//               (or to a SET/CLR/XOR alias),
+//               the result is as though the write from core 0 took place first,
+//               and the write from core 1 was then applied to that intermediate
+//               result.
+#define SIO_GPIO_HI_OUT_OFFSET _u(0x00000030)
+#define SIO_GPIO_HI_OUT_BITS   _u(0x0000003f)
+#define SIO_GPIO_HI_OUT_RESET  _u(0x00000000)
+#define SIO_GPIO_HI_OUT_MSB    _u(5)
+#define SIO_GPIO_HI_OUT_LSB    _u(0)
+#define SIO_GPIO_HI_OUT_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_GPIO_HI_OUT_SET
+// Description : QSPI output value set
+//               Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |=
+//               wdata`
+#define SIO_GPIO_HI_OUT_SET_OFFSET _u(0x00000034)
+#define SIO_GPIO_HI_OUT_SET_BITS   _u(0x0000003f)
+#define SIO_GPIO_HI_OUT_SET_RESET  _u(0x00000000)
+#define SIO_GPIO_HI_OUT_SET_MSB    _u(5)
+#define SIO_GPIO_HI_OUT_SET_LSB    _u(0)
+#define SIO_GPIO_HI_OUT_SET_ACCESS "WO"
+// =============================================================================
+// Register    : SIO_GPIO_HI_OUT_CLR
+// Description : QSPI output value clear
+//               Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT
+//               &= ~wdata`
+#define SIO_GPIO_HI_OUT_CLR_OFFSET _u(0x00000038)
+#define SIO_GPIO_HI_OUT_CLR_BITS   _u(0x0000003f)
+#define SIO_GPIO_HI_OUT_CLR_RESET  _u(0x00000000)
+#define SIO_GPIO_HI_OUT_CLR_MSB    _u(5)
+#define SIO_GPIO_HI_OUT_CLR_LSB    _u(0)
+#define SIO_GPIO_HI_OUT_CLR_ACCESS "WO"
+// =============================================================================
+// Register    : SIO_GPIO_HI_OUT_XOR
+// Description : QSPI output value XOR
+//               Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT
+//               ^= wdata`
+#define SIO_GPIO_HI_OUT_XOR_OFFSET _u(0x0000003c)
+#define SIO_GPIO_HI_OUT_XOR_BITS   _u(0x0000003f)
+#define SIO_GPIO_HI_OUT_XOR_RESET  _u(0x00000000)
+#define SIO_GPIO_HI_OUT_XOR_MSB    _u(5)
+#define SIO_GPIO_HI_OUT_XOR_LSB    _u(0)
+#define SIO_GPIO_HI_OUT_XOR_ACCESS "WO"
+// =============================================================================
+// Register    : SIO_GPIO_HI_OE
+// Description : QSPI output enable
+//               Set output enable (1/0 -> output/input) for QSPI IO0...5.
+//               Reading back gives the last value written.
+//               If core 0 and core 1 both write to GPIO_HI_OE simultaneously
+//               (or to a SET/CLR/XOR alias),
+//               the result is as though the write from core 0 took place first,
+//               and the write from core 1 was then applied to that intermediate
+//               result.
+#define SIO_GPIO_HI_OE_OFFSET _u(0x00000040)
+#define SIO_GPIO_HI_OE_BITS   _u(0x0000003f)
+#define SIO_GPIO_HI_OE_RESET  _u(0x00000000)
+#define SIO_GPIO_HI_OE_MSB    _u(5)
+#define SIO_GPIO_HI_OE_LSB    _u(0)
+#define SIO_GPIO_HI_OE_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_GPIO_HI_OE_SET
+// Description : QSPI output enable set
+//               Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |=
+//               wdata`
+#define SIO_GPIO_HI_OE_SET_OFFSET _u(0x00000044)
+#define SIO_GPIO_HI_OE_SET_BITS   _u(0x0000003f)
+#define SIO_GPIO_HI_OE_SET_RESET  _u(0x00000000)
+#define SIO_GPIO_HI_OE_SET_MSB    _u(5)
+#define SIO_GPIO_HI_OE_SET_LSB    _u(0)
+#define SIO_GPIO_HI_OE_SET_ACCESS "WO"
+// =============================================================================
+// Register    : SIO_GPIO_HI_OE_CLR
+// Description : QSPI output enable clear
+//               Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &=
+//               ~wdata`
+#define SIO_GPIO_HI_OE_CLR_OFFSET _u(0x00000048)
+#define SIO_GPIO_HI_OE_CLR_BITS   _u(0x0000003f)
+#define SIO_GPIO_HI_OE_CLR_RESET  _u(0x00000000)
+#define SIO_GPIO_HI_OE_CLR_MSB    _u(5)
+#define SIO_GPIO_HI_OE_CLR_LSB    _u(0)
+#define SIO_GPIO_HI_OE_CLR_ACCESS "WO"
+// =============================================================================
+// Register    : SIO_GPIO_HI_OE_XOR
+// Description : QSPI output enable XOR
+//               Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE
+//               ^= wdata`
+#define SIO_GPIO_HI_OE_XOR_OFFSET _u(0x0000004c)
+#define SIO_GPIO_HI_OE_XOR_BITS   _u(0x0000003f)
+#define SIO_GPIO_HI_OE_XOR_RESET  _u(0x00000000)
+#define SIO_GPIO_HI_OE_XOR_MSB    _u(5)
+#define SIO_GPIO_HI_OE_XOR_LSB    _u(0)
+#define SIO_GPIO_HI_OE_XOR_ACCESS "WO"
+// =============================================================================
+// Register    : SIO_FIFO_ST
+// Description : Status register for inter-core FIFOs (mailboxes).
+//               There is one FIFO in the core 0 -> core 1 direction, and one
+//               core 1 -> core 0. Both are 32 bits wide and 8 words deep.
+//               Core 0 can see the read side of the 1->0 FIFO (RX), and the
+//               write side of 0->1 FIFO (TX).
+//               Core 1 can see the read side of the 0->1 FIFO (RX), and the
+//               write side of 1->0 FIFO (TX).
+//               The SIO IRQ for each core is the logical OR of the VLD, WOF and
+//               ROE fields of its FIFO_ST register.
+#define SIO_FIFO_ST_OFFSET _u(0x00000050)
+#define SIO_FIFO_ST_BITS   _u(0x0000000f)
+#define SIO_FIFO_ST_RESET  _u(0x00000002)
+// -----------------------------------------------------------------------------
+// Field       : SIO_FIFO_ST_ROE
+// Description : Sticky flag indicating the RX FIFO was read when empty. This
+//               read was ignored by the FIFO.
+#define SIO_FIFO_ST_ROE_RESET  _u(0x0)
+#define SIO_FIFO_ST_ROE_BITS   _u(0x00000008)
+#define SIO_FIFO_ST_ROE_MSB    _u(3)
+#define SIO_FIFO_ST_ROE_LSB    _u(3)
+#define SIO_FIFO_ST_ROE_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : SIO_FIFO_ST_WOF
+// Description : Sticky flag indicating the TX FIFO was written when full. This
+//               write was ignored by the FIFO.
+#define SIO_FIFO_ST_WOF_RESET  _u(0x0)
+#define SIO_FIFO_ST_WOF_BITS   _u(0x00000004)
+#define SIO_FIFO_ST_WOF_MSB    _u(2)
+#define SIO_FIFO_ST_WOF_LSB    _u(2)
+#define SIO_FIFO_ST_WOF_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : SIO_FIFO_ST_RDY
+// Description : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR
+//               is ready for more data)
+#define SIO_FIFO_ST_RDY_RESET  _u(0x1)
+#define SIO_FIFO_ST_RDY_BITS   _u(0x00000002)
+#define SIO_FIFO_ST_RDY_MSB    _u(1)
+#define SIO_FIFO_ST_RDY_LSB    _u(1)
+#define SIO_FIFO_ST_RDY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SIO_FIFO_ST_VLD
+// Description : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD
+//               is valid)
+#define SIO_FIFO_ST_VLD_RESET  _u(0x0)
+#define SIO_FIFO_ST_VLD_BITS   _u(0x00000001)
+#define SIO_FIFO_ST_VLD_MSB    _u(0)
+#define SIO_FIFO_ST_VLD_LSB    _u(0)
+#define SIO_FIFO_ST_VLD_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_FIFO_WR
+// Description : Write access to this core's TX FIFO
+#define SIO_FIFO_WR_OFFSET _u(0x00000054)
+#define SIO_FIFO_WR_BITS   _u(0xffffffff)
+#define SIO_FIFO_WR_RESET  _u(0x00000000)
+#define SIO_FIFO_WR_MSB    _u(31)
+#define SIO_FIFO_WR_LSB    _u(0)
+#define SIO_FIFO_WR_ACCESS "WF"
+// =============================================================================
+// Register    : SIO_FIFO_RD
+// Description : Read access to this core's RX FIFO
+#define SIO_FIFO_RD_OFFSET _u(0x00000058)
+#define SIO_FIFO_RD_BITS   _u(0xffffffff)
+#define SIO_FIFO_RD_RESET  "-"
+#define SIO_FIFO_RD_MSB    _u(31)
+#define SIO_FIFO_RD_LSB    _u(0)
+#define SIO_FIFO_RD_ACCESS "RF"
+// =============================================================================
+// Register    : SIO_SPINLOCK_ST
+// Description : Spinlock state
+//               A bitmap containing the state of all 32 spinlocks (1=locked).
+//               Mainly intended for debugging.
+#define SIO_SPINLOCK_ST_OFFSET _u(0x0000005c)
+#define SIO_SPINLOCK_ST_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK_ST_RESET  _u(0x00000000)
+#define SIO_SPINLOCK_ST_MSB    _u(31)
+#define SIO_SPINLOCK_ST_LSB    _u(0)
+#define SIO_SPINLOCK_ST_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_DIV_UDIVIDEND
+// Description : Divider unsigned dividend
+//               Write to the DIVIDEND operand of the divider, i.e. the p in `p
+//               / q`.
+//               Any operand write starts a new calculation. The results appear
+//               in QUOTIENT, REMAINDER.
+//               UDIVIDEND/SDIVIDEND are aliases of the same internal register.
+//               The U alias starts an
+//               unsigned calculation, and the S alias starts a signed
+//               calculation.
+#define SIO_DIV_UDIVIDEND_OFFSET _u(0x00000060)
+#define SIO_DIV_UDIVIDEND_BITS   _u(0xffffffff)
+#define SIO_DIV_UDIVIDEND_RESET  _u(0x00000000)
+#define SIO_DIV_UDIVIDEND_MSB    _u(31)
+#define SIO_DIV_UDIVIDEND_LSB    _u(0)
+#define SIO_DIV_UDIVIDEND_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_DIV_UDIVISOR
+// Description : Divider unsigned divisor
+//               Write to the DIVISOR operand of the divider, i.e. the q in `p /
+//               q`.
+//               Any operand write starts a new calculation. The results appear
+//               in QUOTIENT, REMAINDER.
+//               UDIVIDEND/SDIVIDEND are aliases of the same internal register.
+//               The U alias starts an
+//               unsigned calculation, and the S alias starts a signed
+//               calculation.
+#define SIO_DIV_UDIVISOR_OFFSET _u(0x00000064)
+#define SIO_DIV_UDIVISOR_BITS   _u(0xffffffff)
+#define SIO_DIV_UDIVISOR_RESET  _u(0x00000000)
+#define SIO_DIV_UDIVISOR_MSB    _u(31)
+#define SIO_DIV_UDIVISOR_LSB    _u(0)
+#define SIO_DIV_UDIVISOR_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_DIV_SDIVIDEND
+// Description : Divider signed dividend
+//               The same as UDIVIDEND, but starts a signed calculation, rather
+//               than unsigned.
+#define SIO_DIV_SDIVIDEND_OFFSET _u(0x00000068)
+#define SIO_DIV_SDIVIDEND_BITS   _u(0xffffffff)
+#define SIO_DIV_SDIVIDEND_RESET  _u(0x00000000)
+#define SIO_DIV_SDIVIDEND_MSB    _u(31)
+#define SIO_DIV_SDIVIDEND_LSB    _u(0)
+#define SIO_DIV_SDIVIDEND_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_DIV_SDIVISOR
+// Description : Divider signed divisor
+//               The same as UDIVISOR, but starts a signed calculation, rather
+//               than unsigned.
+#define SIO_DIV_SDIVISOR_OFFSET _u(0x0000006c)
+#define SIO_DIV_SDIVISOR_BITS   _u(0xffffffff)
+#define SIO_DIV_SDIVISOR_RESET  _u(0x00000000)
+#define SIO_DIV_SDIVISOR_MSB    _u(31)
+#define SIO_DIV_SDIVISOR_LSB    _u(0)
+#define SIO_DIV_SDIVISOR_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_DIV_QUOTIENT
+// Description : Divider result quotient
+//               The result of `DIVIDEND / DIVISOR` (division). Contents
+//               undefined while CSR_READY is low.
+//               For signed calculations, QUOTIENT is negative when the signs of
+//               DIVIDEND and DIVISOR differ.
+//               This register can be written to directly, for context
+//               save/restore purposes. This halts any
+//               in-progress calculation and sets the CSR_READY and CSR_DIRTY
+//               flags.
+//               Reading from QUOTIENT clears the CSR_DIRTY flag, so should read
+//               results in the order
+//               REMAINDER, QUOTIENT if CSR_DIRTY is used.
+#define SIO_DIV_QUOTIENT_OFFSET _u(0x00000070)
+#define SIO_DIV_QUOTIENT_BITS   _u(0xffffffff)
+#define SIO_DIV_QUOTIENT_RESET  _u(0x00000000)
+#define SIO_DIV_QUOTIENT_MSB    _u(31)
+#define SIO_DIV_QUOTIENT_LSB    _u(0)
+#define SIO_DIV_QUOTIENT_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_DIV_REMAINDER
+// Description : Divider result remainder
+//               The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined
+//               while CSR_READY is low.
+//               For signed calculations, REMAINDER is negative only when
+//               DIVIDEND is negative.
+//               This register can be written to directly, for context
+//               save/restore purposes. This halts any
+//               in-progress calculation and sets the CSR_READY and CSR_DIRTY
+//               flags.
+#define SIO_DIV_REMAINDER_OFFSET _u(0x00000074)
+#define SIO_DIV_REMAINDER_BITS   _u(0xffffffff)
+#define SIO_DIV_REMAINDER_RESET  _u(0x00000000)
+#define SIO_DIV_REMAINDER_MSB    _u(31)
+#define SIO_DIV_REMAINDER_LSB    _u(0)
+#define SIO_DIV_REMAINDER_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_DIV_CSR
+// Description : Control and status register for divider.
+#define SIO_DIV_CSR_OFFSET _u(0x00000078)
+#define SIO_DIV_CSR_BITS   _u(0x00000003)
+#define SIO_DIV_CSR_RESET  _u(0x00000001)
+// -----------------------------------------------------------------------------
+// Field       : SIO_DIV_CSR_DIRTY
+// Description : Changes to 1 when any register is written, and back to 0 when
+//               QUOTIENT is read.
+//               Software can use this flag to make save/restore more efficient
+//               (skip if not DIRTY).
+//               If the flag is used in this way, it's recommended to either
+//               read QUOTIENT only,
+//               or REMAINDER and then QUOTIENT, to prevent data loss on context
+//               switch.
+#define SIO_DIV_CSR_DIRTY_RESET  _u(0x0)
+#define SIO_DIV_CSR_DIRTY_BITS   _u(0x00000002)
+#define SIO_DIV_CSR_DIRTY_MSB    _u(1)
+#define SIO_DIV_CSR_DIRTY_LSB    _u(1)
+#define SIO_DIV_CSR_DIRTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SIO_DIV_CSR_READY
+// Description : Reads as 0 when a calculation is in progress, 1 otherwise.
+//               Writing an operand (xDIVIDEND, xDIVISOR) will immediately start
+//               a new calculation, no
+//               matter if one is already in progress.
+//               Writing to a result register will immediately terminate any
+//               in-progress calculation
+//               and set the READY and DIRTY flags.
+#define SIO_DIV_CSR_READY_RESET  _u(0x1)
+#define SIO_DIV_CSR_READY_BITS   _u(0x00000001)
+#define SIO_DIV_CSR_READY_MSB    _u(0)
+#define SIO_DIV_CSR_READY_LSB    _u(0)
+#define SIO_DIV_CSR_READY_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_INTERP0_ACCUM0
+// Description : Read/write access to accumulator 0
+#define SIO_INTERP0_ACCUM0_OFFSET _u(0x00000080)
+#define SIO_INTERP0_ACCUM0_BITS   _u(0xffffffff)
+#define SIO_INTERP0_ACCUM0_RESET  _u(0x00000000)
+#define SIO_INTERP0_ACCUM0_MSB    _u(31)
+#define SIO_INTERP0_ACCUM0_LSB    _u(0)
+#define SIO_INTERP0_ACCUM0_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP0_ACCUM1
+// Description : Read/write access to accumulator 1
+#define SIO_INTERP0_ACCUM1_OFFSET _u(0x00000084)
+#define SIO_INTERP0_ACCUM1_BITS   _u(0xffffffff)
+#define SIO_INTERP0_ACCUM1_RESET  _u(0x00000000)
+#define SIO_INTERP0_ACCUM1_MSB    _u(31)
+#define SIO_INTERP0_ACCUM1_LSB    _u(0)
+#define SIO_INTERP0_ACCUM1_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP0_BASE0
+// Description : Read/write access to BASE0 register.
+#define SIO_INTERP0_BASE0_OFFSET _u(0x00000088)
+#define SIO_INTERP0_BASE0_BITS   _u(0xffffffff)
+#define SIO_INTERP0_BASE0_RESET  _u(0x00000000)
+#define SIO_INTERP0_BASE0_MSB    _u(31)
+#define SIO_INTERP0_BASE0_LSB    _u(0)
+#define SIO_INTERP0_BASE0_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP0_BASE1
+// Description : Read/write access to BASE1 register.
+#define SIO_INTERP0_BASE1_OFFSET _u(0x0000008c)
+#define SIO_INTERP0_BASE1_BITS   _u(0xffffffff)
+#define SIO_INTERP0_BASE1_RESET  _u(0x00000000)
+#define SIO_INTERP0_BASE1_MSB    _u(31)
+#define SIO_INTERP0_BASE1_LSB    _u(0)
+#define SIO_INTERP0_BASE1_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP0_BASE2
+// Description : Read/write access to BASE2 register.
+#define SIO_INTERP0_BASE2_OFFSET _u(0x00000090)
+#define SIO_INTERP0_BASE2_BITS   _u(0xffffffff)
+#define SIO_INTERP0_BASE2_RESET  _u(0x00000000)
+#define SIO_INTERP0_BASE2_MSB    _u(31)
+#define SIO_INTERP0_BASE2_LSB    _u(0)
+#define SIO_INTERP0_BASE2_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP0_POP_LANE0
+// Description : Read LANE0 result, and simultaneously write lane results to
+//               both accumulators (POP).
+#define SIO_INTERP0_POP_LANE0_OFFSET _u(0x00000094)
+#define SIO_INTERP0_POP_LANE0_BITS   _u(0xffffffff)
+#define SIO_INTERP0_POP_LANE0_RESET  _u(0x00000000)
+#define SIO_INTERP0_POP_LANE0_MSB    _u(31)
+#define SIO_INTERP0_POP_LANE0_LSB    _u(0)
+#define SIO_INTERP0_POP_LANE0_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_INTERP0_POP_LANE1
+// Description : Read LANE1 result, and simultaneously write lane results to
+//               both accumulators (POP).
+#define SIO_INTERP0_POP_LANE1_OFFSET _u(0x00000098)
+#define SIO_INTERP0_POP_LANE1_BITS   _u(0xffffffff)
+#define SIO_INTERP0_POP_LANE1_RESET  _u(0x00000000)
+#define SIO_INTERP0_POP_LANE1_MSB    _u(31)
+#define SIO_INTERP0_POP_LANE1_LSB    _u(0)
+#define SIO_INTERP0_POP_LANE1_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_INTERP0_POP_FULL
+// Description : Read FULL result, and simultaneously write lane results to both
+//               accumulators (POP).
+#define SIO_INTERP0_POP_FULL_OFFSET _u(0x0000009c)
+#define SIO_INTERP0_POP_FULL_BITS   _u(0xffffffff)
+#define SIO_INTERP0_POP_FULL_RESET  _u(0x00000000)
+#define SIO_INTERP0_POP_FULL_MSB    _u(31)
+#define SIO_INTERP0_POP_FULL_LSB    _u(0)
+#define SIO_INTERP0_POP_FULL_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_INTERP0_PEEK_LANE0
+// Description : Read LANE0 result, without altering any internal state (PEEK).
+#define SIO_INTERP0_PEEK_LANE0_OFFSET _u(0x000000a0)
+#define SIO_INTERP0_PEEK_LANE0_BITS   _u(0xffffffff)
+#define SIO_INTERP0_PEEK_LANE0_RESET  _u(0x00000000)
+#define SIO_INTERP0_PEEK_LANE0_MSB    _u(31)
+#define SIO_INTERP0_PEEK_LANE0_LSB    _u(0)
+#define SIO_INTERP0_PEEK_LANE0_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_INTERP0_PEEK_LANE1
+// Description : Read LANE1 result, without altering any internal state (PEEK).
+#define SIO_INTERP0_PEEK_LANE1_OFFSET _u(0x000000a4)
+#define SIO_INTERP0_PEEK_LANE1_BITS   _u(0xffffffff)
+#define SIO_INTERP0_PEEK_LANE1_RESET  _u(0x00000000)
+#define SIO_INTERP0_PEEK_LANE1_MSB    _u(31)
+#define SIO_INTERP0_PEEK_LANE1_LSB    _u(0)
+#define SIO_INTERP0_PEEK_LANE1_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_INTERP0_PEEK_FULL
+// Description : Read FULL result, without altering any internal state (PEEK).
+#define SIO_INTERP0_PEEK_FULL_OFFSET _u(0x000000a8)
+#define SIO_INTERP0_PEEK_FULL_BITS   _u(0xffffffff)
+#define SIO_INTERP0_PEEK_FULL_RESET  _u(0x00000000)
+#define SIO_INTERP0_PEEK_FULL_MSB    _u(31)
+#define SIO_INTERP0_PEEK_FULL_LSB    _u(0)
+#define SIO_INTERP0_PEEK_FULL_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_INTERP0_CTRL_LANE0
+// Description : Control register for lane 0
+#define SIO_INTERP0_CTRL_LANE0_OFFSET _u(0x000000ac)
+#define SIO_INTERP0_CTRL_LANE0_BITS   _u(0x03bfffff)
+#define SIO_INTERP0_CTRL_LANE0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE0_OVERF
+// Description : Set if either OVERF0 or OVERF1 is set.
+#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET  _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS   _u(0x02000000)
+#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB    _u(25)
+#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB    _u(25)
+#define SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE0_OVERF1
+// Description : Indicates if any masked-off MSBs in ACCUM1 are set.
+#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET  _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS   _u(0x01000000)
+#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB    _u(24)
+#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB    _u(24)
+#define SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE0_OVERF0
+// Description : Indicates if any masked-off MSBs in ACCUM0 are set.
+#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET  _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS   _u(0x00800000)
+#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB    _u(23)
+#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB    _u(23)
+#define SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE0_BLEND
+// Description : Only present on INTERP0 on each core. If BLEND mode is enabled:
+//               - LANE1 result is a linear interpolation between BASE0 and
+//               BASE1, controlled
+//               by the 8 LSBs of lane 1 shift and mask value (a fractional
+//               number between
+//               0 and 255/256ths)
+//               - LANE0 result does not have BASE0 added (yields only the 8
+//               LSBs of lane 1 shift+mask value)
+//               - FULL result does not have lane 1 shift+mask value added
+//               (BASE2 + lane 0 shift+mask)
+//               LANE1 SIGNED flag controls whether the interpolation is signed
+//               or unsigned.
+#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET  _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS   _u(0x00200000)
+#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB    _u(21)
+#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB    _u(21)
+#define SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE0_FORCE_MSB
+// Description : ORed into bits 29:28 of the lane result presented to the
+//               processor on the bus.
+//               No effect on the internal 32-bit datapath. Handy for using a
+//               lane to generate sequence
+//               of pointers into flash or SRAM.
+#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET  _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS   _u(0x00180000)
+#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB    _u(20)
+#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB    _u(19)
+#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE0_ADD_RAW
+// Description : If 1, mask + shift is bypassed for LANE0 result. This does not
+//               affect FULL result.
+#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET  _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS   _u(0x00040000)
+#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB    _u(18)
+#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB    _u(18)
+#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE0_CROSS_RESULT
+// Description : If 1, feed the opposite lane's result into this lane's
+//               accumulator on POP.
+#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET  _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS   _u(0x00020000)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB    _u(17)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB    _u(17)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE0_CROSS_INPUT
+// Description : If 1, feed the opposite lane's accumulator into this lane's
+//               shift + mask hardware.
+//               Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is
+//               before the shift+mask bypass)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET  _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS   _u(0x00010000)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB    _u(16)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB    _u(16)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE0_SIGNED
+// Description : If SIGNED is set, the shifted and masked accumulator value is
+//               sign-extended to 32 bits
+//               before adding to BASE0, and LANE0 PEEK/POP appear extended to
+//               32 bits when read by processor.
+#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET  _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS   _u(0x00008000)
+#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB    _u(15)
+#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB    _u(15)
+#define SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE0_MASK_MSB
+// Description : The most-significant bit allowed to pass by the mask
+//               (inclusive)
+//               Setting MSB < LSB may cause chip to turn inside-out
+#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET  _u(0x00)
+#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS   _u(0x00007c00)
+#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB    _u(14)
+#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB    _u(10)
+#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE0_MASK_LSB
+// Description : The least-significant bit allowed to pass by the mask
+//               (inclusive)
+#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET  _u(0x00)
+#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS   _u(0x000003e0)
+#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB    _u(9)
+#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB    _u(5)
+#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE0_SHIFT
+// Description : Logical right-shift applied to accumulator before masking
+#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET  _u(0x00)
+#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS   _u(0x0000001f)
+#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB    _u(4)
+#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB    _u(0)
+#define SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP0_CTRL_LANE1
+// Description : Control register for lane 1
+#define SIO_INTERP0_CTRL_LANE1_OFFSET _u(0x000000b0)
+#define SIO_INTERP0_CTRL_LANE1_BITS   _u(0x001fffff)
+#define SIO_INTERP0_CTRL_LANE1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE1_FORCE_MSB
+// Description : ORed into bits 29:28 of the lane result presented to the
+//               processor on the bus.
+//               No effect on the internal 32-bit datapath. Handy for using a
+//               lane to generate sequence
+//               of pointers into flash or SRAM.
+#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET  _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS   _u(0x00180000)
+#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB    _u(20)
+#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB    _u(19)
+#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE1_ADD_RAW
+// Description : If 1, mask + shift is bypassed for LANE1 result. This does not
+//               affect FULL result.
+#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET  _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS   _u(0x00040000)
+#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB    _u(18)
+#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB    _u(18)
+#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE1_CROSS_RESULT
+// Description : If 1, feed the opposite lane's result into this lane's
+//               accumulator on POP.
+#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET  _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS   _u(0x00020000)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB    _u(17)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB    _u(17)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE1_CROSS_INPUT
+// Description : If 1, feed the opposite lane's accumulator into this lane's
+//               shift + mask hardware.
+//               Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is
+//               before the shift+mask bypass)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET  _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS   _u(0x00010000)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB    _u(16)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB    _u(16)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE1_SIGNED
+// Description : If SIGNED is set, the shifted and masked accumulator value is
+//               sign-extended to 32 bits
+//               before adding to BASE1, and LANE1 PEEK/POP appear extended to
+//               32 bits when read by processor.
+#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET  _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS   _u(0x00008000)
+#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB    _u(15)
+#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB    _u(15)
+#define SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE1_MASK_MSB
+// Description : The most-significant bit allowed to pass by the mask
+//               (inclusive)
+//               Setting MSB < LSB may cause chip to turn inside-out
+#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET  _u(0x00)
+#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS   _u(0x00007c00)
+#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB    _u(14)
+#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB    _u(10)
+#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE1_MASK_LSB
+// Description : The least-significant bit allowed to pass by the mask
+//               (inclusive)
+#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET  _u(0x00)
+#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS   _u(0x000003e0)
+#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB    _u(9)
+#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB    _u(5)
+#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP0_CTRL_LANE1_SHIFT
+// Description : Logical right-shift applied to accumulator before masking
+#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET  _u(0x00)
+#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS   _u(0x0000001f)
+#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB    _u(4)
+#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB    _u(0)
+#define SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP0_ACCUM0_ADD
+// Description : Values written here are atomically added to ACCUM0
+//               Reading yields lane 0's raw shift and mask value (BASE0 not
+//               added).
+#define SIO_INTERP0_ACCUM0_ADD_OFFSET _u(0x000000b4)
+#define SIO_INTERP0_ACCUM0_ADD_BITS   _u(0x00ffffff)
+#define SIO_INTERP0_ACCUM0_ADD_RESET  _u(0x00000000)
+#define SIO_INTERP0_ACCUM0_ADD_MSB    _u(23)
+#define SIO_INTERP0_ACCUM0_ADD_LSB    _u(0)
+#define SIO_INTERP0_ACCUM0_ADD_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP0_ACCUM1_ADD
+// Description : Values written here are atomically added to ACCUM1
+//               Reading yields lane 1's raw shift and mask value (BASE1 not
+//               added).
+#define SIO_INTERP0_ACCUM1_ADD_OFFSET _u(0x000000b8)
+#define SIO_INTERP0_ACCUM1_ADD_BITS   _u(0x00ffffff)
+#define SIO_INTERP0_ACCUM1_ADD_RESET  _u(0x00000000)
+#define SIO_INTERP0_ACCUM1_ADD_MSB    _u(23)
+#define SIO_INTERP0_ACCUM1_ADD_LSB    _u(0)
+#define SIO_INTERP0_ACCUM1_ADD_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP0_BASE_1AND0
+// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1
+//               simultaneously.
+//               Each half is sign-extended to 32 bits if that lane's SIGNED
+//               flag is set.
+#define SIO_INTERP0_BASE_1AND0_OFFSET _u(0x000000bc)
+#define SIO_INTERP0_BASE_1AND0_BITS   _u(0xffffffff)
+#define SIO_INTERP0_BASE_1AND0_RESET  _u(0x00000000)
+#define SIO_INTERP0_BASE_1AND0_MSB    _u(31)
+#define SIO_INTERP0_BASE_1AND0_LSB    _u(0)
+#define SIO_INTERP0_BASE_1AND0_ACCESS "WO"
+// =============================================================================
+// Register    : SIO_INTERP1_ACCUM0
+// Description : Read/write access to accumulator 0
+#define SIO_INTERP1_ACCUM0_OFFSET _u(0x000000c0)
+#define SIO_INTERP1_ACCUM0_BITS   _u(0xffffffff)
+#define SIO_INTERP1_ACCUM0_RESET  _u(0x00000000)
+#define SIO_INTERP1_ACCUM0_MSB    _u(31)
+#define SIO_INTERP1_ACCUM0_LSB    _u(0)
+#define SIO_INTERP1_ACCUM0_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP1_ACCUM1
+// Description : Read/write access to accumulator 1
+#define SIO_INTERP1_ACCUM1_OFFSET _u(0x000000c4)
+#define SIO_INTERP1_ACCUM1_BITS   _u(0xffffffff)
+#define SIO_INTERP1_ACCUM1_RESET  _u(0x00000000)
+#define SIO_INTERP1_ACCUM1_MSB    _u(31)
+#define SIO_INTERP1_ACCUM1_LSB    _u(0)
+#define SIO_INTERP1_ACCUM1_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP1_BASE0
+// Description : Read/write access to BASE0 register.
+#define SIO_INTERP1_BASE0_OFFSET _u(0x000000c8)
+#define SIO_INTERP1_BASE0_BITS   _u(0xffffffff)
+#define SIO_INTERP1_BASE0_RESET  _u(0x00000000)
+#define SIO_INTERP1_BASE0_MSB    _u(31)
+#define SIO_INTERP1_BASE0_LSB    _u(0)
+#define SIO_INTERP1_BASE0_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP1_BASE1
+// Description : Read/write access to BASE1 register.
+#define SIO_INTERP1_BASE1_OFFSET _u(0x000000cc)
+#define SIO_INTERP1_BASE1_BITS   _u(0xffffffff)
+#define SIO_INTERP1_BASE1_RESET  _u(0x00000000)
+#define SIO_INTERP1_BASE1_MSB    _u(31)
+#define SIO_INTERP1_BASE1_LSB    _u(0)
+#define SIO_INTERP1_BASE1_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP1_BASE2
+// Description : Read/write access to BASE2 register.
+#define SIO_INTERP1_BASE2_OFFSET _u(0x000000d0)
+#define SIO_INTERP1_BASE2_BITS   _u(0xffffffff)
+#define SIO_INTERP1_BASE2_RESET  _u(0x00000000)
+#define SIO_INTERP1_BASE2_MSB    _u(31)
+#define SIO_INTERP1_BASE2_LSB    _u(0)
+#define SIO_INTERP1_BASE2_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP1_POP_LANE0
+// Description : Read LANE0 result, and simultaneously write lane results to
+//               both accumulators (POP).
+#define SIO_INTERP1_POP_LANE0_OFFSET _u(0x000000d4)
+#define SIO_INTERP1_POP_LANE0_BITS   _u(0xffffffff)
+#define SIO_INTERP1_POP_LANE0_RESET  _u(0x00000000)
+#define SIO_INTERP1_POP_LANE0_MSB    _u(31)
+#define SIO_INTERP1_POP_LANE0_LSB    _u(0)
+#define SIO_INTERP1_POP_LANE0_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_INTERP1_POP_LANE1
+// Description : Read LANE1 result, and simultaneously write lane results to
+//               both accumulators (POP).
+#define SIO_INTERP1_POP_LANE1_OFFSET _u(0x000000d8)
+#define SIO_INTERP1_POP_LANE1_BITS   _u(0xffffffff)
+#define SIO_INTERP1_POP_LANE1_RESET  _u(0x00000000)
+#define SIO_INTERP1_POP_LANE1_MSB    _u(31)
+#define SIO_INTERP1_POP_LANE1_LSB    _u(0)
+#define SIO_INTERP1_POP_LANE1_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_INTERP1_POP_FULL
+// Description : Read FULL result, and simultaneously write lane results to both
+//               accumulators (POP).
+#define SIO_INTERP1_POP_FULL_OFFSET _u(0x000000dc)
+#define SIO_INTERP1_POP_FULL_BITS   _u(0xffffffff)
+#define SIO_INTERP1_POP_FULL_RESET  _u(0x00000000)
+#define SIO_INTERP1_POP_FULL_MSB    _u(31)
+#define SIO_INTERP1_POP_FULL_LSB    _u(0)
+#define SIO_INTERP1_POP_FULL_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_INTERP1_PEEK_LANE0
+// Description : Read LANE0 result, without altering any internal state (PEEK).
+#define SIO_INTERP1_PEEK_LANE0_OFFSET _u(0x000000e0)
+#define SIO_INTERP1_PEEK_LANE0_BITS   _u(0xffffffff)
+#define SIO_INTERP1_PEEK_LANE0_RESET  _u(0x00000000)
+#define SIO_INTERP1_PEEK_LANE0_MSB    _u(31)
+#define SIO_INTERP1_PEEK_LANE0_LSB    _u(0)
+#define SIO_INTERP1_PEEK_LANE0_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_INTERP1_PEEK_LANE1
+// Description : Read LANE1 result, without altering any internal state (PEEK).
+#define SIO_INTERP1_PEEK_LANE1_OFFSET _u(0x000000e4)
+#define SIO_INTERP1_PEEK_LANE1_BITS   _u(0xffffffff)
+#define SIO_INTERP1_PEEK_LANE1_RESET  _u(0x00000000)
+#define SIO_INTERP1_PEEK_LANE1_MSB    _u(31)
+#define SIO_INTERP1_PEEK_LANE1_LSB    _u(0)
+#define SIO_INTERP1_PEEK_LANE1_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_INTERP1_PEEK_FULL
+// Description : Read FULL result, without altering any internal state (PEEK).
+#define SIO_INTERP1_PEEK_FULL_OFFSET _u(0x000000e8)
+#define SIO_INTERP1_PEEK_FULL_BITS   _u(0xffffffff)
+#define SIO_INTERP1_PEEK_FULL_RESET  _u(0x00000000)
+#define SIO_INTERP1_PEEK_FULL_MSB    _u(31)
+#define SIO_INTERP1_PEEK_FULL_LSB    _u(0)
+#define SIO_INTERP1_PEEK_FULL_ACCESS "RO"
+// =============================================================================
+// Register    : SIO_INTERP1_CTRL_LANE0
+// Description : Control register for lane 0
+#define SIO_INTERP1_CTRL_LANE0_OFFSET _u(0x000000ec)
+#define SIO_INTERP1_CTRL_LANE0_BITS   _u(0x03dfffff)
+#define SIO_INTERP1_CTRL_LANE0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE0_OVERF
+// Description : Set if either OVERF0 or OVERF1 is set.
+#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET  _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS   _u(0x02000000)
+#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB    _u(25)
+#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB    _u(25)
+#define SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE0_OVERF1
+// Description : Indicates if any masked-off MSBs in ACCUM1 are set.
+#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET  _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS   _u(0x01000000)
+#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB    _u(24)
+#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB    _u(24)
+#define SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE0_OVERF0
+// Description : Indicates if any masked-off MSBs in ACCUM0 are set.
+#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET  _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS   _u(0x00800000)
+#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB    _u(23)
+#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB    _u(23)
+#define SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE0_CLAMP
+// Description : Only present on INTERP1 on each core. If CLAMP mode is enabled:
+//               - LANE0 result is shifted and masked ACCUM0, clamped by a lower
+//               bound of
+//               BASE0 and an upper bound of BASE1.
+//               - Signedness of these comparisons is determined by
+//               LANE0_CTRL_SIGNED
+#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET  _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS   _u(0x00400000)
+#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB    _u(22)
+#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB    _u(22)
+#define SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE0_FORCE_MSB
+// Description : ORed into bits 29:28 of the lane result presented to the
+//               processor on the bus.
+//               No effect on the internal 32-bit datapath. Handy for using a
+//               lane to generate sequence
+//               of pointers into flash or SRAM.
+#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET  _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS   _u(0x00180000)
+#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB    _u(20)
+#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB    _u(19)
+#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE0_ADD_RAW
+// Description : If 1, mask + shift is bypassed for LANE0 result. This does not
+//               affect FULL result.
+#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET  _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS   _u(0x00040000)
+#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB    _u(18)
+#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB    _u(18)
+#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE0_CROSS_RESULT
+// Description : If 1, feed the opposite lane's result into this lane's
+//               accumulator on POP.
+#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET  _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS   _u(0x00020000)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB    _u(17)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB    _u(17)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE0_CROSS_INPUT
+// Description : If 1, feed the opposite lane's accumulator into this lane's
+//               shift + mask hardware.
+//               Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is
+//               before the shift+mask bypass)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET  _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS   _u(0x00010000)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB    _u(16)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB    _u(16)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE0_SIGNED
+// Description : If SIGNED is set, the shifted and masked accumulator value is
+//               sign-extended to 32 bits
+//               before adding to BASE0, and LANE0 PEEK/POP appear extended to
+//               32 bits when read by processor.
+#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET  _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS   _u(0x00008000)
+#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB    _u(15)
+#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB    _u(15)
+#define SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE0_MASK_MSB
+// Description : The most-significant bit allowed to pass by the mask
+//               (inclusive)
+//               Setting MSB < LSB may cause chip to turn inside-out
+#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET  _u(0x00)
+#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS   _u(0x00007c00)
+#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB    _u(14)
+#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB    _u(10)
+#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE0_MASK_LSB
+// Description : The least-significant bit allowed to pass by the mask
+//               (inclusive)
+#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET  _u(0x00)
+#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS   _u(0x000003e0)
+#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB    _u(9)
+#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB    _u(5)
+#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE0_SHIFT
+// Description : Logical right-shift applied to accumulator before masking
+#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET  _u(0x00)
+#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS   _u(0x0000001f)
+#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB    _u(4)
+#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB    _u(0)
+#define SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP1_CTRL_LANE1
+// Description : Control register for lane 1
+#define SIO_INTERP1_CTRL_LANE1_OFFSET _u(0x000000f0)
+#define SIO_INTERP1_CTRL_LANE1_BITS   _u(0x001fffff)
+#define SIO_INTERP1_CTRL_LANE1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE1_FORCE_MSB
+// Description : ORed into bits 29:28 of the lane result presented to the
+//               processor on the bus.
+//               No effect on the internal 32-bit datapath. Handy for using a
+//               lane to generate sequence
+//               of pointers into flash or SRAM.
+#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET  _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS   _u(0x00180000)
+#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB    _u(20)
+#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB    _u(19)
+#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE1_ADD_RAW
+// Description : If 1, mask + shift is bypassed for LANE1 result. This does not
+//               affect FULL result.
+#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET  _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS   _u(0x00040000)
+#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB    _u(18)
+#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB    _u(18)
+#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE1_CROSS_RESULT
+// Description : If 1, feed the opposite lane's result into this lane's
+//               accumulator on POP.
+#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET  _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS   _u(0x00020000)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB    _u(17)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB    _u(17)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE1_CROSS_INPUT
+// Description : If 1, feed the opposite lane's accumulator into this lane's
+//               shift + mask hardware.
+//               Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is
+//               before the shift+mask bypass)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET  _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS   _u(0x00010000)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB    _u(16)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB    _u(16)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE1_SIGNED
+// Description : If SIGNED is set, the shifted and masked accumulator value is
+//               sign-extended to 32 bits
+//               before adding to BASE1, and LANE1 PEEK/POP appear extended to
+//               32 bits when read by processor.
+#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET  _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS   _u(0x00008000)
+#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB    _u(15)
+#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB    _u(15)
+#define SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE1_MASK_MSB
+// Description : The most-significant bit allowed to pass by the mask
+//               (inclusive)
+//               Setting MSB < LSB may cause chip to turn inside-out
+#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET  _u(0x00)
+#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS   _u(0x00007c00)
+#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB    _u(14)
+#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB    _u(10)
+#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE1_MASK_LSB
+// Description : The least-significant bit allowed to pass by the mask
+//               (inclusive)
+#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET  _u(0x00)
+#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS   _u(0x000003e0)
+#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB    _u(9)
+#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB    _u(5)
+#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SIO_INTERP1_CTRL_LANE1_SHIFT
+// Description : Logical right-shift applied to accumulator before masking
+#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET  _u(0x00)
+#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS   _u(0x0000001f)
+#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB    _u(4)
+#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB    _u(0)
+#define SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP1_ACCUM0_ADD
+// Description : Values written here are atomically added to ACCUM0
+//               Reading yields lane 0's raw shift and mask value (BASE0 not
+//               added).
+#define SIO_INTERP1_ACCUM0_ADD_OFFSET _u(0x000000f4)
+#define SIO_INTERP1_ACCUM0_ADD_BITS   _u(0x00ffffff)
+#define SIO_INTERP1_ACCUM0_ADD_RESET  _u(0x00000000)
+#define SIO_INTERP1_ACCUM0_ADD_MSB    _u(23)
+#define SIO_INTERP1_ACCUM0_ADD_LSB    _u(0)
+#define SIO_INTERP1_ACCUM0_ADD_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP1_ACCUM1_ADD
+// Description : Values written here are atomically added to ACCUM1
+//               Reading yields lane 1's raw shift and mask value (BASE1 not
+//               added).
+#define SIO_INTERP1_ACCUM1_ADD_OFFSET _u(0x000000f8)
+#define SIO_INTERP1_ACCUM1_ADD_BITS   _u(0x00ffffff)
+#define SIO_INTERP1_ACCUM1_ADD_RESET  _u(0x00000000)
+#define SIO_INTERP1_ACCUM1_ADD_MSB    _u(23)
+#define SIO_INTERP1_ACCUM1_ADD_LSB    _u(0)
+#define SIO_INTERP1_ACCUM1_ADD_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_INTERP1_BASE_1AND0
+// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1
+//               simultaneously.
+//               Each half is sign-extended to 32 bits if that lane's SIGNED
+//               flag is set.
+#define SIO_INTERP1_BASE_1AND0_OFFSET _u(0x000000fc)
+#define SIO_INTERP1_BASE_1AND0_BITS   _u(0xffffffff)
+#define SIO_INTERP1_BASE_1AND0_RESET  _u(0x00000000)
+#define SIO_INTERP1_BASE_1AND0_MSB    _u(31)
+#define SIO_INTERP1_BASE_1AND0_LSB    _u(0)
+#define SIO_INTERP1_BASE_1AND0_ACCESS "WO"
+// =============================================================================
+// Register    : SIO_SPINLOCK0
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK0_OFFSET _u(0x00000100)
+#define SIO_SPINLOCK0_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK0_RESET  _u(0x00000000)
+#define SIO_SPINLOCK0_MSB    _u(31)
+#define SIO_SPINLOCK0_LSB    _u(0)
+#define SIO_SPINLOCK0_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK1
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK1_OFFSET _u(0x00000104)
+#define SIO_SPINLOCK1_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK1_RESET  _u(0x00000000)
+#define SIO_SPINLOCK1_MSB    _u(31)
+#define SIO_SPINLOCK1_LSB    _u(0)
+#define SIO_SPINLOCK1_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK2
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK2_OFFSET _u(0x00000108)
+#define SIO_SPINLOCK2_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK2_RESET  _u(0x00000000)
+#define SIO_SPINLOCK2_MSB    _u(31)
+#define SIO_SPINLOCK2_LSB    _u(0)
+#define SIO_SPINLOCK2_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK3
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK3_OFFSET _u(0x0000010c)
+#define SIO_SPINLOCK3_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK3_RESET  _u(0x00000000)
+#define SIO_SPINLOCK3_MSB    _u(31)
+#define SIO_SPINLOCK3_LSB    _u(0)
+#define SIO_SPINLOCK3_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK4
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK4_OFFSET _u(0x00000110)
+#define SIO_SPINLOCK4_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK4_RESET  _u(0x00000000)
+#define SIO_SPINLOCK4_MSB    _u(31)
+#define SIO_SPINLOCK4_LSB    _u(0)
+#define SIO_SPINLOCK4_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK5
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK5_OFFSET _u(0x00000114)
+#define SIO_SPINLOCK5_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK5_RESET  _u(0x00000000)
+#define SIO_SPINLOCK5_MSB    _u(31)
+#define SIO_SPINLOCK5_LSB    _u(0)
+#define SIO_SPINLOCK5_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK6
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK6_OFFSET _u(0x00000118)
+#define SIO_SPINLOCK6_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK6_RESET  _u(0x00000000)
+#define SIO_SPINLOCK6_MSB    _u(31)
+#define SIO_SPINLOCK6_LSB    _u(0)
+#define SIO_SPINLOCK6_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK7
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK7_OFFSET _u(0x0000011c)
+#define SIO_SPINLOCK7_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK7_RESET  _u(0x00000000)
+#define SIO_SPINLOCK7_MSB    _u(31)
+#define SIO_SPINLOCK7_LSB    _u(0)
+#define SIO_SPINLOCK7_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK8
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK8_OFFSET _u(0x00000120)
+#define SIO_SPINLOCK8_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK8_RESET  _u(0x00000000)
+#define SIO_SPINLOCK8_MSB    _u(31)
+#define SIO_SPINLOCK8_LSB    _u(0)
+#define SIO_SPINLOCK8_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK9
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK9_OFFSET _u(0x00000124)
+#define SIO_SPINLOCK9_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK9_RESET  _u(0x00000000)
+#define SIO_SPINLOCK9_MSB    _u(31)
+#define SIO_SPINLOCK9_LSB    _u(0)
+#define SIO_SPINLOCK9_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK10
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK10_OFFSET _u(0x00000128)
+#define SIO_SPINLOCK10_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK10_RESET  _u(0x00000000)
+#define SIO_SPINLOCK10_MSB    _u(31)
+#define SIO_SPINLOCK10_LSB    _u(0)
+#define SIO_SPINLOCK10_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK11
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK11_OFFSET _u(0x0000012c)
+#define SIO_SPINLOCK11_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK11_RESET  _u(0x00000000)
+#define SIO_SPINLOCK11_MSB    _u(31)
+#define SIO_SPINLOCK11_LSB    _u(0)
+#define SIO_SPINLOCK11_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK12
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK12_OFFSET _u(0x00000130)
+#define SIO_SPINLOCK12_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK12_RESET  _u(0x00000000)
+#define SIO_SPINLOCK12_MSB    _u(31)
+#define SIO_SPINLOCK12_LSB    _u(0)
+#define SIO_SPINLOCK12_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK13
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK13_OFFSET _u(0x00000134)
+#define SIO_SPINLOCK13_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK13_RESET  _u(0x00000000)
+#define SIO_SPINLOCK13_MSB    _u(31)
+#define SIO_SPINLOCK13_LSB    _u(0)
+#define SIO_SPINLOCK13_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK14
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK14_OFFSET _u(0x00000138)
+#define SIO_SPINLOCK14_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK14_RESET  _u(0x00000000)
+#define SIO_SPINLOCK14_MSB    _u(31)
+#define SIO_SPINLOCK14_LSB    _u(0)
+#define SIO_SPINLOCK14_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK15
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK15_OFFSET _u(0x0000013c)
+#define SIO_SPINLOCK15_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK15_RESET  _u(0x00000000)
+#define SIO_SPINLOCK15_MSB    _u(31)
+#define SIO_SPINLOCK15_LSB    _u(0)
+#define SIO_SPINLOCK15_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK16
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK16_OFFSET _u(0x00000140)
+#define SIO_SPINLOCK16_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK16_RESET  _u(0x00000000)
+#define SIO_SPINLOCK16_MSB    _u(31)
+#define SIO_SPINLOCK16_LSB    _u(0)
+#define SIO_SPINLOCK16_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK17
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK17_OFFSET _u(0x00000144)
+#define SIO_SPINLOCK17_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK17_RESET  _u(0x00000000)
+#define SIO_SPINLOCK17_MSB    _u(31)
+#define SIO_SPINLOCK17_LSB    _u(0)
+#define SIO_SPINLOCK17_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK18
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK18_OFFSET _u(0x00000148)
+#define SIO_SPINLOCK18_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK18_RESET  _u(0x00000000)
+#define SIO_SPINLOCK18_MSB    _u(31)
+#define SIO_SPINLOCK18_LSB    _u(0)
+#define SIO_SPINLOCK18_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK19
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK19_OFFSET _u(0x0000014c)
+#define SIO_SPINLOCK19_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK19_RESET  _u(0x00000000)
+#define SIO_SPINLOCK19_MSB    _u(31)
+#define SIO_SPINLOCK19_LSB    _u(0)
+#define SIO_SPINLOCK19_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK20
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK20_OFFSET _u(0x00000150)
+#define SIO_SPINLOCK20_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK20_RESET  _u(0x00000000)
+#define SIO_SPINLOCK20_MSB    _u(31)
+#define SIO_SPINLOCK20_LSB    _u(0)
+#define SIO_SPINLOCK20_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK21
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK21_OFFSET _u(0x00000154)
+#define SIO_SPINLOCK21_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK21_RESET  _u(0x00000000)
+#define SIO_SPINLOCK21_MSB    _u(31)
+#define SIO_SPINLOCK21_LSB    _u(0)
+#define SIO_SPINLOCK21_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK22
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK22_OFFSET _u(0x00000158)
+#define SIO_SPINLOCK22_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK22_RESET  _u(0x00000000)
+#define SIO_SPINLOCK22_MSB    _u(31)
+#define SIO_SPINLOCK22_LSB    _u(0)
+#define SIO_SPINLOCK22_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK23
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK23_OFFSET _u(0x0000015c)
+#define SIO_SPINLOCK23_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK23_RESET  _u(0x00000000)
+#define SIO_SPINLOCK23_MSB    _u(31)
+#define SIO_SPINLOCK23_LSB    _u(0)
+#define SIO_SPINLOCK23_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK24
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK24_OFFSET _u(0x00000160)
+#define SIO_SPINLOCK24_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK24_RESET  _u(0x00000000)
+#define SIO_SPINLOCK24_MSB    _u(31)
+#define SIO_SPINLOCK24_LSB    _u(0)
+#define SIO_SPINLOCK24_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK25
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK25_OFFSET _u(0x00000164)
+#define SIO_SPINLOCK25_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK25_RESET  _u(0x00000000)
+#define SIO_SPINLOCK25_MSB    _u(31)
+#define SIO_SPINLOCK25_LSB    _u(0)
+#define SIO_SPINLOCK25_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK26
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK26_OFFSET _u(0x00000168)
+#define SIO_SPINLOCK26_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK26_RESET  _u(0x00000000)
+#define SIO_SPINLOCK26_MSB    _u(31)
+#define SIO_SPINLOCK26_LSB    _u(0)
+#define SIO_SPINLOCK26_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK27
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK27_OFFSET _u(0x0000016c)
+#define SIO_SPINLOCK27_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK27_RESET  _u(0x00000000)
+#define SIO_SPINLOCK27_MSB    _u(31)
+#define SIO_SPINLOCK27_LSB    _u(0)
+#define SIO_SPINLOCK27_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK28
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK28_OFFSET _u(0x00000170)
+#define SIO_SPINLOCK28_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK28_RESET  _u(0x00000000)
+#define SIO_SPINLOCK28_MSB    _u(31)
+#define SIO_SPINLOCK28_LSB    _u(0)
+#define SIO_SPINLOCK28_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK29
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK29_OFFSET _u(0x00000174)
+#define SIO_SPINLOCK29_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK29_RESET  _u(0x00000000)
+#define SIO_SPINLOCK29_MSB    _u(31)
+#define SIO_SPINLOCK29_LSB    _u(0)
+#define SIO_SPINLOCK29_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK30
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK30_OFFSET _u(0x00000178)
+#define SIO_SPINLOCK30_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK30_RESET  _u(0x00000000)
+#define SIO_SPINLOCK30_MSB    _u(31)
+#define SIO_SPINLOCK30_LSB    _u(0)
+#define SIO_SPINLOCK30_ACCESS "RW"
+// =============================================================================
+// Register    : SIO_SPINLOCK31
+// Description : Reading from a spinlock address will:
+//               - Return 0 if lock is already locked
+//               - Otherwise return nonzero, and simultaneously claim the lock
+//
+//               Writing (any value) releases the lock.
+//               If core 0 and core 1 attempt to claim the same lock
+//               simultaneously, core 0 wins.
+//               The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK31_OFFSET _u(0x0000017c)
+#define SIO_SPINLOCK31_BITS   _u(0xffffffff)
+#define SIO_SPINLOCK31_RESET  _u(0x00000000)
+#define SIO_SPINLOCK31_MSB    _u(31)
+#define SIO_SPINLOCK31_LSB    _u(0)
+#define SIO_SPINLOCK31_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_SIO_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/spi.h b/src/rp2040/hardware_regs/include/hardware/regs/spi.h
new file mode 100644
index 0000000..816e150
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/spi.h
@@ -0,0 +1,521 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : SPI
+// Version        : 1
+// Bus type       : apb
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_SPI_DEFINED
+#define HARDWARE_REGS_SPI_DEFINED
+// =============================================================================
+// Register    : SPI_SSPCR0
+// Description : Control register 0, SSPCR0 on page 3-4
+#define SPI_SSPCR0_OFFSET _u(0x00000000)
+#define SPI_SSPCR0_BITS   _u(0x0000ffff)
+#define SPI_SSPCR0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPCR0_SCR
+// Description : Serial clock rate. The value SCR is used to generate the
+//               transmit and receive bit rate of the PrimeCell SSP. The bit
+//               rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even
+//               value from 2-254, programmed through the SSPCPSR register and
+//               SCR is a value from 0-255.
+#define SPI_SSPCR0_SCR_RESET  _u(0x00)
+#define SPI_SSPCR0_SCR_BITS   _u(0x0000ff00)
+#define SPI_SSPCR0_SCR_MSB    _u(15)
+#define SPI_SSPCR0_SCR_LSB    _u(8)
+#define SPI_SSPCR0_SCR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPCR0_SPH
+// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only.
+//               See Motorola SPI frame format on page 2-10.
+#define SPI_SSPCR0_SPH_RESET  _u(0x0)
+#define SPI_SSPCR0_SPH_BITS   _u(0x00000080)
+#define SPI_SSPCR0_SPH_MSB    _u(7)
+#define SPI_SSPCR0_SPH_LSB    _u(7)
+#define SPI_SSPCR0_SPH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPCR0_SPO
+// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format
+//               only. See Motorola SPI frame format on page 2-10.
+#define SPI_SSPCR0_SPO_RESET  _u(0x0)
+#define SPI_SSPCR0_SPO_BITS   _u(0x00000040)
+#define SPI_SSPCR0_SPO_MSB    _u(6)
+#define SPI_SSPCR0_SPO_LSB    _u(6)
+#define SPI_SSPCR0_SPO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPCR0_FRF
+// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous
+//               serial frame format. 10 National Microwire frame format. 11
+//               Reserved, undefined operation.
+#define SPI_SSPCR0_FRF_RESET  _u(0x0)
+#define SPI_SSPCR0_FRF_BITS   _u(0x00000030)
+#define SPI_SSPCR0_FRF_MSB    _u(5)
+#define SPI_SSPCR0_FRF_LSB    _u(4)
+#define SPI_SSPCR0_FRF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPCR0_DSS
+// Description : Data Size Select: 0000 Reserved, undefined operation. 0001
+//               Reserved, undefined operation. 0010 Reserved, undefined
+//               operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data.
+//               0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit
+//               data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data.
+//               1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
+#define SPI_SSPCR0_DSS_RESET  _u(0x0)
+#define SPI_SSPCR0_DSS_BITS   _u(0x0000000f)
+#define SPI_SSPCR0_DSS_MSB    _u(3)
+#define SPI_SSPCR0_DSS_LSB    _u(0)
+#define SPI_SSPCR0_DSS_ACCESS "RW"
+// =============================================================================
+// Register    : SPI_SSPCR1
+// Description : Control register 1, SSPCR1 on page 3-5
+#define SPI_SSPCR1_OFFSET _u(0x00000004)
+#define SPI_SSPCR1_BITS   _u(0x0000000f)
+#define SPI_SSPCR1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPCR1_SOD
+// Description : Slave-mode output disable. This bit is relevant only in the
+//               slave mode, MS=1. In multiple-slave systems, it is possible for
+//               an PrimeCell SSP master to broadcast a message to all slaves in
+//               the system while ensuring that only one slave drives data onto
+//               its serial output line. In such systems the RXD lines from
+//               multiple slaves could be tied together. To operate in such
+//               systems, the SOD bit can be set if the PrimeCell SSP slave is
+//               not supposed to drive the SSPTXD line: 0 SSP can drive the
+//               SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD
+//               output in slave mode.
+#define SPI_SSPCR1_SOD_RESET  _u(0x0)
+#define SPI_SSPCR1_SOD_BITS   _u(0x00000008)
+#define SPI_SSPCR1_SOD_MSB    _u(3)
+#define SPI_SSPCR1_SOD_LSB    _u(3)
+#define SPI_SSPCR1_SOD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPCR1_MS
+// Description : Master or slave mode select. This bit can be modified only when
+//               the PrimeCell SSP is disabled, SSE=0: 0 Device configured as
+//               master, default. 1 Device configured as slave.
+#define SPI_SSPCR1_MS_RESET  _u(0x0)
+#define SPI_SSPCR1_MS_BITS   _u(0x00000004)
+#define SPI_SSPCR1_MS_MSB    _u(2)
+#define SPI_SSPCR1_MS_LSB    _u(2)
+#define SPI_SSPCR1_MS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPCR1_SSE
+// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP
+//               operation enabled.
+#define SPI_SSPCR1_SSE_RESET  _u(0x0)
+#define SPI_SSPCR1_SSE_BITS   _u(0x00000002)
+#define SPI_SSPCR1_SSE_MSB    _u(1)
+#define SPI_SSPCR1_SSE_LSB    _u(1)
+#define SPI_SSPCR1_SSE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPCR1_LBM
+// Description : Loop back mode: 0 Normal serial port operation enabled. 1
+//               Output of transmit serial shifter is connected to input of
+//               receive serial shifter internally.
+#define SPI_SSPCR1_LBM_RESET  _u(0x0)
+#define SPI_SSPCR1_LBM_BITS   _u(0x00000001)
+#define SPI_SSPCR1_LBM_MSB    _u(0)
+#define SPI_SSPCR1_LBM_LSB    _u(0)
+#define SPI_SSPCR1_LBM_ACCESS "RW"
+// =============================================================================
+// Register    : SPI_SSPDR
+// Description : Data register, SSPDR on page 3-6
+#define SPI_SSPDR_OFFSET _u(0x00000008)
+#define SPI_SSPDR_BITS   _u(0x0000ffff)
+#define SPI_SSPDR_RESET  "-"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPDR_DATA
+// Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO.
+//               You must right-justify data when the PrimeCell SSP is
+//               programmed for a data size that is less than 16 bits. Unused
+//               bits at the top are ignored by transmit logic. The receive
+//               logic automatically right-justifies.
+#define SPI_SSPDR_DATA_RESET  "-"
+#define SPI_SSPDR_DATA_BITS   _u(0x0000ffff)
+#define SPI_SSPDR_DATA_MSB    _u(15)
+#define SPI_SSPDR_DATA_LSB    _u(0)
+#define SPI_SSPDR_DATA_ACCESS "RWF"
+// =============================================================================
+// Register    : SPI_SSPSR
+// Description : Status register, SSPSR on page 3-7
+#define SPI_SSPSR_OFFSET _u(0x0000000c)
+#define SPI_SSPSR_BITS   _u(0x0000001f)
+#define SPI_SSPSR_RESET  _u(0x00000003)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPSR_BSY
+// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently
+//               transmitting and/or receiving a frame or the transmit FIFO is
+//               not empty.
+#define SPI_SSPSR_BSY_RESET  _u(0x0)
+#define SPI_SSPSR_BSY_BITS   _u(0x00000010)
+#define SPI_SSPSR_BSY_MSB    _u(4)
+#define SPI_SSPSR_BSY_LSB    _u(4)
+#define SPI_SSPSR_BSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPSR_RFF
+// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive
+//               FIFO is full.
+#define SPI_SSPSR_RFF_RESET  _u(0x0)
+#define SPI_SSPSR_RFF_BITS   _u(0x00000008)
+#define SPI_SSPSR_RFF_MSB    _u(3)
+#define SPI_SSPSR_RFF_LSB    _u(3)
+#define SPI_SSPSR_RFF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPSR_RNE
+// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive
+//               FIFO is not empty.
+#define SPI_SSPSR_RNE_RESET  _u(0x0)
+#define SPI_SSPSR_RNE_BITS   _u(0x00000004)
+#define SPI_SSPSR_RNE_MSB    _u(2)
+#define SPI_SSPSR_RNE_LSB    _u(2)
+#define SPI_SSPSR_RNE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPSR_TNF
+// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit
+//               FIFO is not full.
+#define SPI_SSPSR_TNF_RESET  _u(0x1)
+#define SPI_SSPSR_TNF_BITS   _u(0x00000002)
+#define SPI_SSPSR_TNF_MSB    _u(1)
+#define SPI_SSPSR_TNF_LSB    _u(1)
+#define SPI_SSPSR_TNF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPSR_TFE
+// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1
+//               Transmit FIFO is empty.
+#define SPI_SSPSR_TFE_RESET  _u(0x1)
+#define SPI_SSPSR_TFE_BITS   _u(0x00000001)
+#define SPI_SSPSR_TFE_MSB    _u(0)
+#define SPI_SSPSR_TFE_LSB    _u(0)
+#define SPI_SSPSR_TFE_ACCESS "RO"
+// =============================================================================
+// Register    : SPI_SSPCPSR
+// Description : Clock prescale register, SSPCPSR on page 3-8
+#define SPI_SSPCPSR_OFFSET _u(0x00000010)
+#define SPI_SSPCPSR_BITS   _u(0x000000ff)
+#define SPI_SSPCPSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPCPSR_CPSDVSR
+// Description : Clock prescale divisor. Must be an even number from 2-254,
+//               depending on the frequency of SSPCLK. The least significant bit
+//               always returns zero on reads.
+#define SPI_SSPCPSR_CPSDVSR_RESET  _u(0x00)
+#define SPI_SSPCPSR_CPSDVSR_BITS   _u(0x000000ff)
+#define SPI_SSPCPSR_CPSDVSR_MSB    _u(7)
+#define SPI_SSPCPSR_CPSDVSR_LSB    _u(0)
+#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW"
+// =============================================================================
+// Register    : SPI_SSPIMSC
+// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9
+#define SPI_SSPIMSC_OFFSET _u(0x00000014)
+#define SPI_SSPIMSC_BITS   _u(0x0000000f)
+#define SPI_SSPIMSC_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPIMSC_TXIM
+// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or
+//               less condition interrupt is masked. 1 Transmit FIFO half empty
+//               or less condition interrupt is not masked.
+#define SPI_SSPIMSC_TXIM_RESET  _u(0x0)
+#define SPI_SSPIMSC_TXIM_BITS   _u(0x00000008)
+#define SPI_SSPIMSC_TXIM_MSB    _u(3)
+#define SPI_SSPIMSC_TXIM_LSB    _u(3)
+#define SPI_SSPIMSC_TXIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPIMSC_RXIM
+// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less
+//               condition interrupt is masked. 1 Receive FIFO half full or less
+//               condition interrupt is not masked.
+#define SPI_SSPIMSC_RXIM_RESET  _u(0x0)
+#define SPI_SSPIMSC_RXIM_BITS   _u(0x00000004)
+#define SPI_SSPIMSC_RXIM_MSB    _u(2)
+#define SPI_SSPIMSC_RXIM_LSB    _u(2)
+#define SPI_SSPIMSC_RXIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPIMSC_RTIM
+// Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no
+//               read prior to timeout period interrupt is masked. 1 Receive
+//               FIFO not empty and no read prior to timeout period interrupt is
+//               not masked.
+#define SPI_SSPIMSC_RTIM_RESET  _u(0x0)
+#define SPI_SSPIMSC_RTIM_BITS   _u(0x00000002)
+#define SPI_SSPIMSC_RTIM_MSB    _u(1)
+#define SPI_SSPIMSC_RTIM_LSB    _u(1)
+#define SPI_SSPIMSC_RTIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPIMSC_RORIM
+// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while
+//               full condition interrupt is masked. 1 Receive FIFO written to
+//               while full condition interrupt is not masked.
+#define SPI_SSPIMSC_RORIM_RESET  _u(0x0)
+#define SPI_SSPIMSC_RORIM_BITS   _u(0x00000001)
+#define SPI_SSPIMSC_RORIM_MSB    _u(0)
+#define SPI_SSPIMSC_RORIM_LSB    _u(0)
+#define SPI_SSPIMSC_RORIM_ACCESS "RW"
+// =============================================================================
+// Register    : SPI_SSPRIS
+// Description : Raw interrupt status register, SSPRIS on page 3-10
+#define SPI_SSPRIS_OFFSET _u(0x00000018)
+#define SPI_SSPRIS_BITS   _u(0x0000000f)
+#define SPI_SSPRIS_RESET  _u(0x00000008)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPRIS_TXRIS
+// Description : Gives the raw interrupt state, prior to masking, of the
+//               SSPTXINTR interrupt
+#define SPI_SSPRIS_TXRIS_RESET  _u(0x1)
+#define SPI_SSPRIS_TXRIS_BITS   _u(0x00000008)
+#define SPI_SSPRIS_TXRIS_MSB    _u(3)
+#define SPI_SSPRIS_TXRIS_LSB    _u(3)
+#define SPI_SSPRIS_TXRIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPRIS_RXRIS
+// Description : Gives the raw interrupt state, prior to masking, of the
+//               SSPRXINTR interrupt
+#define SPI_SSPRIS_RXRIS_RESET  _u(0x0)
+#define SPI_SSPRIS_RXRIS_BITS   _u(0x00000004)
+#define SPI_SSPRIS_RXRIS_MSB    _u(2)
+#define SPI_SSPRIS_RXRIS_LSB    _u(2)
+#define SPI_SSPRIS_RXRIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPRIS_RTRIS
+// Description : Gives the raw interrupt state, prior to masking, of the
+//               SSPRTINTR interrupt
+#define SPI_SSPRIS_RTRIS_RESET  _u(0x0)
+#define SPI_SSPRIS_RTRIS_BITS   _u(0x00000002)
+#define SPI_SSPRIS_RTRIS_MSB    _u(1)
+#define SPI_SSPRIS_RTRIS_LSB    _u(1)
+#define SPI_SSPRIS_RTRIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPRIS_RORRIS
+// Description : Gives the raw interrupt state, prior to masking, of the
+//               SSPRORINTR interrupt
+#define SPI_SSPRIS_RORRIS_RESET  _u(0x0)
+#define SPI_SSPRIS_RORRIS_BITS   _u(0x00000001)
+#define SPI_SSPRIS_RORRIS_MSB    _u(0)
+#define SPI_SSPRIS_RORRIS_LSB    _u(0)
+#define SPI_SSPRIS_RORRIS_ACCESS "RO"
+// =============================================================================
+// Register    : SPI_SSPMIS
+// Description : Masked interrupt status register, SSPMIS on page 3-11
+#define SPI_SSPMIS_OFFSET _u(0x0000001c)
+#define SPI_SSPMIS_BITS   _u(0x0000000f)
+#define SPI_SSPMIS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPMIS_TXMIS
+// Description : Gives the transmit FIFO masked interrupt state, after masking,
+//               of the SSPTXINTR interrupt
+#define SPI_SSPMIS_TXMIS_RESET  _u(0x0)
+#define SPI_SSPMIS_TXMIS_BITS   _u(0x00000008)
+#define SPI_SSPMIS_TXMIS_MSB    _u(3)
+#define SPI_SSPMIS_TXMIS_LSB    _u(3)
+#define SPI_SSPMIS_TXMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPMIS_RXMIS
+// Description : Gives the receive FIFO masked interrupt state, after masking,
+//               of the SSPRXINTR interrupt
+#define SPI_SSPMIS_RXMIS_RESET  _u(0x0)
+#define SPI_SSPMIS_RXMIS_BITS   _u(0x00000004)
+#define SPI_SSPMIS_RXMIS_MSB    _u(2)
+#define SPI_SSPMIS_RXMIS_LSB    _u(2)
+#define SPI_SSPMIS_RXMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPMIS_RTMIS
+// Description : Gives the receive timeout masked interrupt state, after
+//               masking, of the SSPRTINTR interrupt
+#define SPI_SSPMIS_RTMIS_RESET  _u(0x0)
+#define SPI_SSPMIS_RTMIS_BITS   _u(0x00000002)
+#define SPI_SSPMIS_RTMIS_MSB    _u(1)
+#define SPI_SSPMIS_RTMIS_LSB    _u(1)
+#define SPI_SSPMIS_RTMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPMIS_RORMIS
+// Description : Gives the receive over run masked interrupt status, after
+//               masking, of the SSPRORINTR interrupt
+#define SPI_SSPMIS_RORMIS_RESET  _u(0x0)
+#define SPI_SSPMIS_RORMIS_BITS   _u(0x00000001)
+#define SPI_SSPMIS_RORMIS_MSB    _u(0)
+#define SPI_SSPMIS_RORMIS_LSB    _u(0)
+#define SPI_SSPMIS_RORMIS_ACCESS "RO"
+// =============================================================================
+// Register    : SPI_SSPICR
+// Description : Interrupt clear register, SSPICR on page 3-11
+#define SPI_SSPICR_OFFSET _u(0x00000020)
+#define SPI_SSPICR_BITS   _u(0x00000003)
+#define SPI_SSPICR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPICR_RTIC
+// Description : Clears the SSPRTINTR interrupt
+#define SPI_SSPICR_RTIC_RESET  _u(0x0)
+#define SPI_SSPICR_RTIC_BITS   _u(0x00000002)
+#define SPI_SSPICR_RTIC_MSB    _u(1)
+#define SPI_SSPICR_RTIC_LSB    _u(1)
+#define SPI_SSPICR_RTIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPICR_RORIC
+// Description : Clears the SSPRORINTR interrupt
+#define SPI_SSPICR_RORIC_RESET  _u(0x0)
+#define SPI_SSPICR_RORIC_BITS   _u(0x00000001)
+#define SPI_SSPICR_RORIC_MSB    _u(0)
+#define SPI_SSPICR_RORIC_LSB    _u(0)
+#define SPI_SSPICR_RORIC_ACCESS "WC"
+// =============================================================================
+// Register    : SPI_SSPDMACR
+// Description : DMA control register, SSPDMACR on page 3-12
+#define SPI_SSPDMACR_OFFSET _u(0x00000024)
+#define SPI_SSPDMACR_BITS   _u(0x00000003)
+#define SPI_SSPDMACR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPDMACR_TXDMAE
+// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the
+//               transmit FIFO is enabled.
+#define SPI_SSPDMACR_TXDMAE_RESET  _u(0x0)
+#define SPI_SSPDMACR_TXDMAE_BITS   _u(0x00000002)
+#define SPI_SSPDMACR_TXDMAE_MSB    _u(1)
+#define SPI_SSPDMACR_TXDMAE_LSB    _u(1)
+#define SPI_SSPDMACR_TXDMAE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPDMACR_RXDMAE
+// Description : Receive DMA Enable. If this bit is set to 1, DMA for the
+//               receive FIFO is enabled.
+#define SPI_SSPDMACR_RXDMAE_RESET  _u(0x0)
+#define SPI_SSPDMACR_RXDMAE_BITS   _u(0x00000001)
+#define SPI_SSPDMACR_RXDMAE_MSB    _u(0)
+#define SPI_SSPDMACR_RXDMAE_LSB    _u(0)
+#define SPI_SSPDMACR_RXDMAE_ACCESS "RW"
+// =============================================================================
+// Register    : SPI_SSPPERIPHID0
+// Description : Peripheral identification registers, SSPPeriphID0-3 on page
+//               3-13
+#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0)
+#define SPI_SSPPERIPHID0_BITS   _u(0x000000ff)
+#define SPI_SSPPERIPHID0_RESET  _u(0x00000022)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPPERIPHID0_PARTNUMBER0
+// Description : These bits read back as 0x22
+#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET  _u(0x22)
+#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS   _u(0x000000ff)
+#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB    _u(7)
+#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB    _u(0)
+#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO"
+// =============================================================================
+// Register    : SPI_SSPPERIPHID1
+// Description : Peripheral identification registers, SSPPeriphID0-3 on page
+//               3-13
+#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4)
+#define SPI_SSPPERIPHID1_BITS   _u(0x000000ff)
+#define SPI_SSPPERIPHID1_RESET  _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPPERIPHID1_DESIGNER0
+// Description : These bits read back as 0x1
+#define SPI_SSPPERIPHID1_DESIGNER0_RESET  _u(0x1)
+#define SPI_SSPPERIPHID1_DESIGNER0_BITS   _u(0x000000f0)
+#define SPI_SSPPERIPHID1_DESIGNER0_MSB    _u(7)
+#define SPI_SSPPERIPHID1_DESIGNER0_LSB    _u(4)
+#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPPERIPHID1_PARTNUMBER1
+// Description : These bits read back as 0x0
+#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET  _u(0x0)
+#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS   _u(0x0000000f)
+#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB    _u(3)
+#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB    _u(0)
+#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO"
+// =============================================================================
+// Register    : SPI_SSPPERIPHID2
+// Description : Peripheral identification registers, SSPPeriphID0-3 on page
+//               3-13
+#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8)
+#define SPI_SSPPERIPHID2_BITS   _u(0x000000ff)
+#define SPI_SSPPERIPHID2_RESET  _u(0x00000034)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPPERIPHID2_REVISION
+// Description : These bits return the peripheral revision
+#define SPI_SSPPERIPHID2_REVISION_RESET  _u(0x3)
+#define SPI_SSPPERIPHID2_REVISION_BITS   _u(0x000000f0)
+#define SPI_SSPPERIPHID2_REVISION_MSB    _u(7)
+#define SPI_SSPPERIPHID2_REVISION_LSB    _u(4)
+#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPPERIPHID2_DESIGNER1
+// Description : These bits read back as 0x4
+#define SPI_SSPPERIPHID2_DESIGNER1_RESET  _u(0x4)
+#define SPI_SSPPERIPHID2_DESIGNER1_BITS   _u(0x0000000f)
+#define SPI_SSPPERIPHID2_DESIGNER1_MSB    _u(3)
+#define SPI_SSPPERIPHID2_DESIGNER1_LSB    _u(0)
+#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO"
+// =============================================================================
+// Register    : SPI_SSPPERIPHID3
+// Description : Peripheral identification registers, SSPPeriphID0-3 on page
+//               3-13
+#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec)
+#define SPI_SSPPERIPHID3_BITS   _u(0x000000ff)
+#define SPI_SSPPERIPHID3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPPERIPHID3_CONFIGURATION
+// Description : These bits read back as 0x00
+#define SPI_SSPPERIPHID3_CONFIGURATION_RESET  _u(0x00)
+#define SPI_SSPPERIPHID3_CONFIGURATION_BITS   _u(0x000000ff)
+#define SPI_SSPPERIPHID3_CONFIGURATION_MSB    _u(7)
+#define SPI_SSPPERIPHID3_CONFIGURATION_LSB    _u(0)
+#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO"
+// =============================================================================
+// Register    : SPI_SSPPCELLID0
+// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0)
+#define SPI_SSPPCELLID0_BITS   _u(0x000000ff)
+#define SPI_SSPPCELLID0_RESET  _u(0x0000000d)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPPCELLID0_SSPPCELLID0
+// Description : These bits read back as 0x0D
+#define SPI_SSPPCELLID0_SSPPCELLID0_RESET  _u(0x0d)
+#define SPI_SSPPCELLID0_SSPPCELLID0_BITS   _u(0x000000ff)
+#define SPI_SSPPCELLID0_SSPPCELLID0_MSB    _u(7)
+#define SPI_SSPPCELLID0_SSPPCELLID0_LSB    _u(0)
+#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO"
+// =============================================================================
+// Register    : SPI_SSPPCELLID1
+// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4)
+#define SPI_SSPPCELLID1_BITS   _u(0x000000ff)
+#define SPI_SSPPCELLID1_RESET  _u(0x000000f0)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPPCELLID1_SSPPCELLID1
+// Description : These bits read back as 0xF0
+#define SPI_SSPPCELLID1_SSPPCELLID1_RESET  _u(0xf0)
+#define SPI_SSPPCELLID1_SSPPCELLID1_BITS   _u(0x000000ff)
+#define SPI_SSPPCELLID1_SSPPCELLID1_MSB    _u(7)
+#define SPI_SSPPCELLID1_SSPPCELLID1_LSB    _u(0)
+#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO"
+// =============================================================================
+// Register    : SPI_SSPPCELLID2
+// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8)
+#define SPI_SSPPCELLID2_BITS   _u(0x000000ff)
+#define SPI_SSPPCELLID2_RESET  _u(0x00000005)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPPCELLID2_SSPPCELLID2
+// Description : These bits read back as 0x05
+#define SPI_SSPPCELLID2_SSPPCELLID2_RESET  _u(0x05)
+#define SPI_SSPPCELLID2_SSPPCELLID2_BITS   _u(0x000000ff)
+#define SPI_SSPPCELLID2_SSPPCELLID2_MSB    _u(7)
+#define SPI_SSPPCELLID2_SSPPCELLID2_LSB    _u(0)
+#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO"
+// =============================================================================
+// Register    : SPI_SSPPCELLID3
+// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc)
+#define SPI_SSPPCELLID3_BITS   _u(0x000000ff)
+#define SPI_SSPPCELLID3_RESET  _u(0x000000b1)
+// -----------------------------------------------------------------------------
+// Field       : SPI_SSPPCELLID3_SSPPCELLID3
+// Description : These bits read back as 0xB1
+#define SPI_SSPPCELLID3_SSPPCELLID3_RESET  _u(0xb1)
+#define SPI_SSPPCELLID3_SSPPCELLID3_BITS   _u(0x000000ff)
+#define SPI_SSPPCELLID3_SSPPCELLID3_MSB    _u(7)
+#define SPI_SSPPCELLID3_SSPPCELLID3_LSB    _u(0)
+#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_SPI_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/ssi.h b/src/rp2040/hardware_regs/include/hardware/regs/ssi.h
new file mode 100644
index 0000000..67fddc0
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/ssi.h
@@ -0,0 +1,809 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : SSI
+// Version        : 1
+// Bus type       : apb
+// Description    : DW_apb_ssi has the following features:
+//                  * APB interface – Allows for easy integration into a
+//                  DesignWare Synthesizable Components for AMBA 2
+//                  implementation.
+//                  * APB3 and APB4 protocol support.
+//                  * Scalable APB data bus width – Supports APB data bus widths
+//                  of 8, 16, and 32 bits.
+//                  * Serial-master or serial-slave operation – Enables serial
+//                  communication with serial-master or serial-slave peripheral
+//                  devices.
+//                  * Programmable Dual/Quad/Octal SPI support in Master Mode.
+//                  * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support -
+//                  Enables the DW_apb_ssi master to perform operations with the
+//                  device in DDR and RDS modes when working in Dual/Quad/Octal
+//                  mode of operation.
+//                  * Data Mask Support - Enables the DW_apb_ssi to selectively
+//                  update the bytes in the device. This feature is applicable
+//                  only in enhanced SPI modes.
+//                  * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi
+//                  master to behave as a memory mapped I/O and fetches the data
+//                  from the device based on the APB read request. This feature
+//                  is applicable only in enhanced SPI modes.
+//                  * DMA Controller Interface – Enables the DW_apb_ssi to
+//                  interface to a DMA controller over the bus using a
+//                  handshaking interface for transfer requests.
+//                  * Independent masking of interrupts – Master collision,
+//                  transmit FIFO overflow, transmit FIFO empty, receive FIFO
+//                  full, receive FIFO underflow, and receive FIFO overflow
+//                  interrupts can all be masked independently.
+//                  * Multi-master contention detection – Informs the processor
+//                  of multiple serial-master accesses on the serial bus.
+//                  * Bypass of meta-stability flip-flops for synchronous clocks
+//                  – When the APB clock (pclk) and the DW_apb_ssi serial clock
+//                  (ssi_clk) are synchronous, meta-stable flip-flops are not
+//                  used when transferring control signals across these clock
+//                  domains.
+//                  * Programmable delay on the sample time of the received
+//                  serial data bit (rxd); enables programmable control of
+//                  routing delays resulting in higher serial data-bit rates.
+//                  * Programmable features:
+//                  - Serial interface operation – Choice of Motorola SPI, Texas
+//                  Instruments Synchronous Serial Protocol or National
+//                  Semiconductor Microwire.
+//                  - Clock bit-rate – Dynamic control of the serial bit rate of
+//                  the data transfer; used in only serial-master mode of
+//                  operation.
+//                  - Data Item size (4 to 32 bits) – Item size of each data
+//                  transfer under the control of the programmer.
+//                  * Configured features:
+//                  - FIFO depth – 16 words deep. The FIFO width is fixed at 32
+//                  bits.
+//                  - 1 slave select output.
+//                  - Hardware slave-select – Dedicated hardware slave-select
+//                  line.
+//                  - Combined interrupt line - one combined interrupt line from
+//                  the DW_apb_ssi to the interrupt controller.
+//                  - Interrupt polarity – active high interrupt lines.
+//                  - Serial clock polarity – low serial-clock polarity directly
+//                  after reset.
+//                  - Serial clock phase – capture on first edge of serial-clock
+//                  directly after reset.
+// =============================================================================
+#ifndef HARDWARE_REGS_SSI_DEFINED
+#define HARDWARE_REGS_SSI_DEFINED
+// =============================================================================
+// Register    : SSI_CTRLR0
+// Description : Control register 0
+#define SSI_CTRLR0_OFFSET _u(0x00000000)
+#define SSI_CTRLR0_BITS   _u(0x017fffff)
+#define SSI_CTRLR0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_SSTE
+// Description : Slave select toggle enable
+#define SSI_CTRLR0_SSTE_RESET  _u(0x0)
+#define SSI_CTRLR0_SSTE_BITS   _u(0x01000000)
+#define SSI_CTRLR0_SSTE_MSB    _u(24)
+#define SSI_CTRLR0_SSTE_LSB    _u(24)
+#define SSI_CTRLR0_SSTE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_SPI_FRF
+// Description : SPI frame format
+//               0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK,
+//               full-duplex
+//               0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex
+//               0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex
+#define SSI_CTRLR0_SPI_FRF_RESET      _u(0x0)
+#define SSI_CTRLR0_SPI_FRF_BITS       _u(0x00600000)
+#define SSI_CTRLR0_SPI_FRF_MSB        _u(22)
+#define SSI_CTRLR0_SPI_FRF_LSB        _u(21)
+#define SSI_CTRLR0_SPI_FRF_ACCESS     "RW"
+#define SSI_CTRLR0_SPI_FRF_VALUE_STD  _u(0x0)
+#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL _u(0x1)
+#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_DFS_32
+// Description : Data frame size in 32b transfer mode
+//               Value of n -> n+1 clocks per frame.
+#define SSI_CTRLR0_DFS_32_RESET  _u(0x00)
+#define SSI_CTRLR0_DFS_32_BITS   _u(0x001f0000)
+#define SSI_CTRLR0_DFS_32_MSB    _u(20)
+#define SSI_CTRLR0_DFS_32_LSB    _u(16)
+#define SSI_CTRLR0_DFS_32_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_CFS
+// Description : Control frame size
+//               Value of n -> n+1 clocks per frame.
+#define SSI_CTRLR0_CFS_RESET  _u(0x0)
+#define SSI_CTRLR0_CFS_BITS   _u(0x0000f000)
+#define SSI_CTRLR0_CFS_MSB    _u(15)
+#define SSI_CTRLR0_CFS_LSB    _u(12)
+#define SSI_CTRLR0_CFS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_SRL
+// Description : Shift register loop (test mode)
+#define SSI_CTRLR0_SRL_RESET  _u(0x0)
+#define SSI_CTRLR0_SRL_BITS   _u(0x00000800)
+#define SSI_CTRLR0_SRL_MSB    _u(11)
+#define SSI_CTRLR0_SRL_LSB    _u(11)
+#define SSI_CTRLR0_SRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_SLV_OE
+// Description : Slave output enable
+#define SSI_CTRLR0_SLV_OE_RESET  _u(0x0)
+#define SSI_CTRLR0_SLV_OE_BITS   _u(0x00000400)
+#define SSI_CTRLR0_SLV_OE_MSB    _u(10)
+#define SSI_CTRLR0_SLV_OE_LSB    _u(10)
+#define SSI_CTRLR0_SLV_OE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_TMOD
+// Description : Transfer mode
+//               0x0 -> Both transmit and receive
+//               0x1 -> Transmit only (not for FRF == 0, standard SPI mode)
+//               0x2 -> Receive only (not for FRF == 0, standard SPI mode)
+//               0x3 -> EEPROM read mode (TX then RX; RX starts after control
+//               data TX'd)
+#define SSI_CTRLR0_TMOD_RESET             _u(0x0)
+#define SSI_CTRLR0_TMOD_BITS              _u(0x00000300)
+#define SSI_CTRLR0_TMOD_MSB               _u(9)
+#define SSI_CTRLR0_TMOD_LSB               _u(8)
+#define SSI_CTRLR0_TMOD_ACCESS            "RW"
+#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX   _u(0x0)
+#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY     _u(0x1)
+#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY     _u(0x2)
+#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_SCPOL
+// Description : Serial clock polarity
+#define SSI_CTRLR0_SCPOL_RESET  _u(0x0)
+#define SSI_CTRLR0_SCPOL_BITS   _u(0x00000080)
+#define SSI_CTRLR0_SCPOL_MSB    _u(7)
+#define SSI_CTRLR0_SCPOL_LSB    _u(7)
+#define SSI_CTRLR0_SCPOL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_SCPH
+// Description : Serial clock phase
+#define SSI_CTRLR0_SCPH_RESET  _u(0x0)
+#define SSI_CTRLR0_SCPH_BITS   _u(0x00000040)
+#define SSI_CTRLR0_SCPH_MSB    _u(6)
+#define SSI_CTRLR0_SCPH_LSB    _u(6)
+#define SSI_CTRLR0_SCPH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_FRF
+// Description : Frame format
+#define SSI_CTRLR0_FRF_RESET  _u(0x0)
+#define SSI_CTRLR0_FRF_BITS   _u(0x00000030)
+#define SSI_CTRLR0_FRF_MSB    _u(5)
+#define SSI_CTRLR0_FRF_LSB    _u(4)
+#define SSI_CTRLR0_FRF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_DFS
+// Description : Data frame size
+#define SSI_CTRLR0_DFS_RESET  _u(0x0)
+#define SSI_CTRLR0_DFS_BITS   _u(0x0000000f)
+#define SSI_CTRLR0_DFS_MSB    _u(3)
+#define SSI_CTRLR0_DFS_LSB    _u(0)
+#define SSI_CTRLR0_DFS_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_CTRLR1
+// Description : Master Control register 1
+#define SSI_CTRLR1_OFFSET _u(0x00000004)
+#define SSI_CTRLR1_BITS   _u(0x0000ffff)
+#define SSI_CTRLR1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR1_NDF
+// Description : Number of data frames
+#define SSI_CTRLR1_NDF_RESET  _u(0x0000)
+#define SSI_CTRLR1_NDF_BITS   _u(0x0000ffff)
+#define SSI_CTRLR1_NDF_MSB    _u(15)
+#define SSI_CTRLR1_NDF_LSB    _u(0)
+#define SSI_CTRLR1_NDF_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_SSIENR
+// Description : SSI Enable
+#define SSI_SSIENR_OFFSET _u(0x00000008)
+#define SSI_SSIENR_BITS   _u(0x00000001)
+#define SSI_SSIENR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_SSIENR_SSI_EN
+// Description : SSI enable
+#define SSI_SSIENR_SSI_EN_RESET  _u(0x0)
+#define SSI_SSIENR_SSI_EN_BITS   _u(0x00000001)
+#define SSI_SSIENR_SSI_EN_MSB    _u(0)
+#define SSI_SSIENR_SSI_EN_LSB    _u(0)
+#define SSI_SSIENR_SSI_EN_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_MWCR
+// Description : Microwire Control
+#define SSI_MWCR_OFFSET _u(0x0000000c)
+#define SSI_MWCR_BITS   _u(0x00000007)
+#define SSI_MWCR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_MWCR_MHS
+// Description : Microwire handshaking
+#define SSI_MWCR_MHS_RESET  _u(0x0)
+#define SSI_MWCR_MHS_BITS   _u(0x00000004)
+#define SSI_MWCR_MHS_MSB    _u(2)
+#define SSI_MWCR_MHS_LSB    _u(2)
+#define SSI_MWCR_MHS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_MWCR_MDD
+// Description : Microwire control
+#define SSI_MWCR_MDD_RESET  _u(0x0)
+#define SSI_MWCR_MDD_BITS   _u(0x00000002)
+#define SSI_MWCR_MDD_MSB    _u(1)
+#define SSI_MWCR_MDD_LSB    _u(1)
+#define SSI_MWCR_MDD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_MWCR_MWMOD
+// Description : Microwire transfer mode
+#define SSI_MWCR_MWMOD_RESET  _u(0x0)
+#define SSI_MWCR_MWMOD_BITS   _u(0x00000001)
+#define SSI_MWCR_MWMOD_MSB    _u(0)
+#define SSI_MWCR_MWMOD_LSB    _u(0)
+#define SSI_MWCR_MWMOD_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_SER
+// Description : Slave enable
+//               For each bit:
+//               0 -> slave not selected
+//               1 -> slave selected
+#define SSI_SER_OFFSET _u(0x00000010)
+#define SSI_SER_BITS   _u(0x00000001)
+#define SSI_SER_RESET  _u(0x00000000)
+#define SSI_SER_MSB    _u(0)
+#define SSI_SER_LSB    _u(0)
+#define SSI_SER_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_BAUDR
+// Description : Baud rate
+#define SSI_BAUDR_OFFSET _u(0x00000014)
+#define SSI_BAUDR_BITS   _u(0x0000ffff)
+#define SSI_BAUDR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_BAUDR_SCKDV
+// Description : SSI clock divider
+#define SSI_BAUDR_SCKDV_RESET  _u(0x0000)
+#define SSI_BAUDR_SCKDV_BITS   _u(0x0000ffff)
+#define SSI_BAUDR_SCKDV_MSB    _u(15)
+#define SSI_BAUDR_SCKDV_LSB    _u(0)
+#define SSI_BAUDR_SCKDV_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_TXFTLR
+// Description : TX FIFO threshold level
+#define SSI_TXFTLR_OFFSET _u(0x00000018)
+#define SSI_TXFTLR_BITS   _u(0x000000ff)
+#define SSI_TXFTLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_TXFTLR_TFT
+// Description : Transmit FIFO threshold
+#define SSI_TXFTLR_TFT_RESET  _u(0x00)
+#define SSI_TXFTLR_TFT_BITS   _u(0x000000ff)
+#define SSI_TXFTLR_TFT_MSB    _u(7)
+#define SSI_TXFTLR_TFT_LSB    _u(0)
+#define SSI_TXFTLR_TFT_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_RXFTLR
+// Description : RX FIFO threshold level
+#define SSI_RXFTLR_OFFSET _u(0x0000001c)
+#define SSI_RXFTLR_BITS   _u(0x000000ff)
+#define SSI_RXFTLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_RXFTLR_RFT
+// Description : Receive FIFO threshold
+#define SSI_RXFTLR_RFT_RESET  _u(0x00)
+#define SSI_RXFTLR_RFT_BITS   _u(0x000000ff)
+#define SSI_RXFTLR_RFT_MSB    _u(7)
+#define SSI_RXFTLR_RFT_LSB    _u(0)
+#define SSI_RXFTLR_RFT_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_TXFLR
+// Description : TX FIFO level
+#define SSI_TXFLR_OFFSET _u(0x00000020)
+#define SSI_TXFLR_BITS   _u(0x000000ff)
+#define SSI_TXFLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_TXFLR_TFTFL
+// Description : Transmit FIFO level
+#define SSI_TXFLR_TFTFL_RESET  _u(0x00)
+#define SSI_TXFLR_TFTFL_BITS   _u(0x000000ff)
+#define SSI_TXFLR_TFTFL_MSB    _u(7)
+#define SSI_TXFLR_TFTFL_LSB    _u(0)
+#define SSI_TXFLR_TFTFL_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_RXFLR
+// Description : RX FIFO level
+#define SSI_RXFLR_OFFSET _u(0x00000024)
+#define SSI_RXFLR_BITS   _u(0x000000ff)
+#define SSI_RXFLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_RXFLR_RXTFL
+// Description : Receive FIFO level
+#define SSI_RXFLR_RXTFL_RESET  _u(0x00)
+#define SSI_RXFLR_RXTFL_BITS   _u(0x000000ff)
+#define SSI_RXFLR_RXTFL_MSB    _u(7)
+#define SSI_RXFLR_RXTFL_LSB    _u(0)
+#define SSI_RXFLR_RXTFL_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_SR
+// Description : Status register
+#define SSI_SR_OFFSET _u(0x00000028)
+#define SSI_SR_BITS   _u(0x0000007f)
+#define SSI_SR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_SR_DCOL
+// Description : Data collision error
+#define SSI_SR_DCOL_RESET  _u(0x0)
+#define SSI_SR_DCOL_BITS   _u(0x00000040)
+#define SSI_SR_DCOL_MSB    _u(6)
+#define SSI_SR_DCOL_LSB    _u(6)
+#define SSI_SR_DCOL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SR_TXE
+// Description : Transmission error
+#define SSI_SR_TXE_RESET  _u(0x0)
+#define SSI_SR_TXE_BITS   _u(0x00000020)
+#define SSI_SR_TXE_MSB    _u(5)
+#define SSI_SR_TXE_LSB    _u(5)
+#define SSI_SR_TXE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SR_RFF
+// Description : Receive FIFO full
+#define SSI_SR_RFF_RESET  _u(0x0)
+#define SSI_SR_RFF_BITS   _u(0x00000010)
+#define SSI_SR_RFF_MSB    _u(4)
+#define SSI_SR_RFF_LSB    _u(4)
+#define SSI_SR_RFF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SR_RFNE
+// Description : Receive FIFO not empty
+#define SSI_SR_RFNE_RESET  _u(0x0)
+#define SSI_SR_RFNE_BITS   _u(0x00000008)
+#define SSI_SR_RFNE_MSB    _u(3)
+#define SSI_SR_RFNE_LSB    _u(3)
+#define SSI_SR_RFNE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SR_TFE
+// Description : Transmit FIFO empty
+#define SSI_SR_TFE_RESET  _u(0x0)
+#define SSI_SR_TFE_BITS   _u(0x00000004)
+#define SSI_SR_TFE_MSB    _u(2)
+#define SSI_SR_TFE_LSB    _u(2)
+#define SSI_SR_TFE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SR_TFNF
+// Description : Transmit FIFO not full
+#define SSI_SR_TFNF_RESET  _u(0x0)
+#define SSI_SR_TFNF_BITS   _u(0x00000002)
+#define SSI_SR_TFNF_MSB    _u(1)
+#define SSI_SR_TFNF_LSB    _u(1)
+#define SSI_SR_TFNF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SR_BUSY
+// Description : SSI busy flag
+#define SSI_SR_BUSY_RESET  _u(0x0)
+#define SSI_SR_BUSY_BITS   _u(0x00000001)
+#define SSI_SR_BUSY_MSB    _u(0)
+#define SSI_SR_BUSY_LSB    _u(0)
+#define SSI_SR_BUSY_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_IMR
+// Description : Interrupt mask
+#define SSI_IMR_OFFSET _u(0x0000002c)
+#define SSI_IMR_BITS   _u(0x0000003f)
+#define SSI_IMR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_IMR_MSTIM
+// Description : Multi-master contention interrupt mask
+#define SSI_IMR_MSTIM_RESET  _u(0x0)
+#define SSI_IMR_MSTIM_BITS   _u(0x00000020)
+#define SSI_IMR_MSTIM_MSB    _u(5)
+#define SSI_IMR_MSTIM_LSB    _u(5)
+#define SSI_IMR_MSTIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_IMR_RXFIM
+// Description : Receive FIFO full interrupt mask
+#define SSI_IMR_RXFIM_RESET  _u(0x0)
+#define SSI_IMR_RXFIM_BITS   _u(0x00000010)
+#define SSI_IMR_RXFIM_MSB    _u(4)
+#define SSI_IMR_RXFIM_LSB    _u(4)
+#define SSI_IMR_RXFIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_IMR_RXOIM
+// Description : Receive FIFO overflow interrupt mask
+#define SSI_IMR_RXOIM_RESET  _u(0x0)
+#define SSI_IMR_RXOIM_BITS   _u(0x00000008)
+#define SSI_IMR_RXOIM_MSB    _u(3)
+#define SSI_IMR_RXOIM_LSB    _u(3)
+#define SSI_IMR_RXOIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_IMR_RXUIM
+// Description : Receive FIFO underflow interrupt mask
+#define SSI_IMR_RXUIM_RESET  _u(0x0)
+#define SSI_IMR_RXUIM_BITS   _u(0x00000004)
+#define SSI_IMR_RXUIM_MSB    _u(2)
+#define SSI_IMR_RXUIM_LSB    _u(2)
+#define SSI_IMR_RXUIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_IMR_TXOIM
+// Description : Transmit FIFO overflow interrupt mask
+#define SSI_IMR_TXOIM_RESET  _u(0x0)
+#define SSI_IMR_TXOIM_BITS   _u(0x00000002)
+#define SSI_IMR_TXOIM_MSB    _u(1)
+#define SSI_IMR_TXOIM_LSB    _u(1)
+#define SSI_IMR_TXOIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_IMR_TXEIM
+// Description : Transmit FIFO empty interrupt mask
+#define SSI_IMR_TXEIM_RESET  _u(0x0)
+#define SSI_IMR_TXEIM_BITS   _u(0x00000001)
+#define SSI_IMR_TXEIM_MSB    _u(0)
+#define SSI_IMR_TXEIM_LSB    _u(0)
+#define SSI_IMR_TXEIM_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_ISR
+// Description : Interrupt status
+#define SSI_ISR_OFFSET _u(0x00000030)
+#define SSI_ISR_BITS   _u(0x0000003f)
+#define SSI_ISR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_ISR_MSTIS
+// Description : Multi-master contention interrupt status
+#define SSI_ISR_MSTIS_RESET  _u(0x0)
+#define SSI_ISR_MSTIS_BITS   _u(0x00000020)
+#define SSI_ISR_MSTIS_MSB    _u(5)
+#define SSI_ISR_MSTIS_LSB    _u(5)
+#define SSI_ISR_MSTIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_ISR_RXFIS
+// Description : Receive FIFO full interrupt status
+#define SSI_ISR_RXFIS_RESET  _u(0x0)
+#define SSI_ISR_RXFIS_BITS   _u(0x00000010)
+#define SSI_ISR_RXFIS_MSB    _u(4)
+#define SSI_ISR_RXFIS_LSB    _u(4)
+#define SSI_ISR_RXFIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_ISR_RXOIS
+// Description : Receive FIFO overflow interrupt status
+#define SSI_ISR_RXOIS_RESET  _u(0x0)
+#define SSI_ISR_RXOIS_BITS   _u(0x00000008)
+#define SSI_ISR_RXOIS_MSB    _u(3)
+#define SSI_ISR_RXOIS_LSB    _u(3)
+#define SSI_ISR_RXOIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_ISR_RXUIS
+// Description : Receive FIFO underflow interrupt status
+#define SSI_ISR_RXUIS_RESET  _u(0x0)
+#define SSI_ISR_RXUIS_BITS   _u(0x00000004)
+#define SSI_ISR_RXUIS_MSB    _u(2)
+#define SSI_ISR_RXUIS_LSB    _u(2)
+#define SSI_ISR_RXUIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_ISR_TXOIS
+// Description : Transmit FIFO overflow interrupt status
+#define SSI_ISR_TXOIS_RESET  _u(0x0)
+#define SSI_ISR_TXOIS_BITS   _u(0x00000002)
+#define SSI_ISR_TXOIS_MSB    _u(1)
+#define SSI_ISR_TXOIS_LSB    _u(1)
+#define SSI_ISR_TXOIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_ISR_TXEIS
+// Description : Transmit FIFO empty interrupt status
+#define SSI_ISR_TXEIS_RESET  _u(0x0)
+#define SSI_ISR_TXEIS_BITS   _u(0x00000001)
+#define SSI_ISR_TXEIS_MSB    _u(0)
+#define SSI_ISR_TXEIS_LSB    _u(0)
+#define SSI_ISR_TXEIS_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_RISR
+// Description : Raw interrupt status
+#define SSI_RISR_OFFSET _u(0x00000034)
+#define SSI_RISR_BITS   _u(0x0000003f)
+#define SSI_RISR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_RISR_MSTIR
+// Description : Multi-master contention raw interrupt status
+#define SSI_RISR_MSTIR_RESET  _u(0x0)
+#define SSI_RISR_MSTIR_BITS   _u(0x00000020)
+#define SSI_RISR_MSTIR_MSB    _u(5)
+#define SSI_RISR_MSTIR_LSB    _u(5)
+#define SSI_RISR_MSTIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_RISR_RXFIR
+// Description : Receive FIFO full raw interrupt status
+#define SSI_RISR_RXFIR_RESET  _u(0x0)
+#define SSI_RISR_RXFIR_BITS   _u(0x00000010)
+#define SSI_RISR_RXFIR_MSB    _u(4)
+#define SSI_RISR_RXFIR_LSB    _u(4)
+#define SSI_RISR_RXFIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_RISR_RXOIR
+// Description : Receive FIFO overflow raw interrupt status
+#define SSI_RISR_RXOIR_RESET  _u(0x0)
+#define SSI_RISR_RXOIR_BITS   _u(0x00000008)
+#define SSI_RISR_RXOIR_MSB    _u(3)
+#define SSI_RISR_RXOIR_LSB    _u(3)
+#define SSI_RISR_RXOIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_RISR_RXUIR
+// Description : Receive FIFO underflow raw interrupt status
+#define SSI_RISR_RXUIR_RESET  _u(0x0)
+#define SSI_RISR_RXUIR_BITS   _u(0x00000004)
+#define SSI_RISR_RXUIR_MSB    _u(2)
+#define SSI_RISR_RXUIR_LSB    _u(2)
+#define SSI_RISR_RXUIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_RISR_TXOIR
+// Description : Transmit FIFO overflow raw interrupt status
+#define SSI_RISR_TXOIR_RESET  _u(0x0)
+#define SSI_RISR_TXOIR_BITS   _u(0x00000002)
+#define SSI_RISR_TXOIR_MSB    _u(1)
+#define SSI_RISR_TXOIR_LSB    _u(1)
+#define SSI_RISR_TXOIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_RISR_TXEIR
+// Description : Transmit FIFO empty raw interrupt status
+#define SSI_RISR_TXEIR_RESET  _u(0x0)
+#define SSI_RISR_TXEIR_BITS   _u(0x00000001)
+#define SSI_RISR_TXEIR_MSB    _u(0)
+#define SSI_RISR_TXEIR_LSB    _u(0)
+#define SSI_RISR_TXEIR_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_TXOICR
+// Description : TX FIFO overflow interrupt clear
+//               Clear-on-read transmit FIFO overflow interrupt
+#define SSI_TXOICR_OFFSET _u(0x00000038)
+#define SSI_TXOICR_BITS   _u(0x00000001)
+#define SSI_TXOICR_RESET  _u(0x00000000)
+#define SSI_TXOICR_MSB    _u(0)
+#define SSI_TXOICR_LSB    _u(0)
+#define SSI_TXOICR_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_RXOICR
+// Description : RX FIFO overflow interrupt clear
+//               Clear-on-read receive FIFO overflow interrupt
+#define SSI_RXOICR_OFFSET _u(0x0000003c)
+#define SSI_RXOICR_BITS   _u(0x00000001)
+#define SSI_RXOICR_RESET  _u(0x00000000)
+#define SSI_RXOICR_MSB    _u(0)
+#define SSI_RXOICR_LSB    _u(0)
+#define SSI_RXOICR_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_RXUICR
+// Description : RX FIFO underflow interrupt clear
+//               Clear-on-read receive FIFO underflow interrupt
+#define SSI_RXUICR_OFFSET _u(0x00000040)
+#define SSI_RXUICR_BITS   _u(0x00000001)
+#define SSI_RXUICR_RESET  _u(0x00000000)
+#define SSI_RXUICR_MSB    _u(0)
+#define SSI_RXUICR_LSB    _u(0)
+#define SSI_RXUICR_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_MSTICR
+// Description : Multi-master interrupt clear
+//               Clear-on-read multi-master contention interrupt
+#define SSI_MSTICR_OFFSET _u(0x00000044)
+#define SSI_MSTICR_BITS   _u(0x00000001)
+#define SSI_MSTICR_RESET  _u(0x00000000)
+#define SSI_MSTICR_MSB    _u(0)
+#define SSI_MSTICR_LSB    _u(0)
+#define SSI_MSTICR_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_ICR
+// Description : Interrupt clear
+//               Clear-on-read all active interrupts
+#define SSI_ICR_OFFSET _u(0x00000048)
+#define SSI_ICR_BITS   _u(0x00000001)
+#define SSI_ICR_RESET  _u(0x00000000)
+#define SSI_ICR_MSB    _u(0)
+#define SSI_ICR_LSB    _u(0)
+#define SSI_ICR_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_DMACR
+// Description : DMA control
+#define SSI_DMACR_OFFSET _u(0x0000004c)
+#define SSI_DMACR_BITS   _u(0x00000003)
+#define SSI_DMACR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_DMACR_TDMAE
+// Description : Transmit DMA enable
+#define SSI_DMACR_TDMAE_RESET  _u(0x0)
+#define SSI_DMACR_TDMAE_BITS   _u(0x00000002)
+#define SSI_DMACR_TDMAE_MSB    _u(1)
+#define SSI_DMACR_TDMAE_LSB    _u(1)
+#define SSI_DMACR_TDMAE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_DMACR_RDMAE
+// Description : Receive DMA enable
+#define SSI_DMACR_RDMAE_RESET  _u(0x0)
+#define SSI_DMACR_RDMAE_BITS   _u(0x00000001)
+#define SSI_DMACR_RDMAE_MSB    _u(0)
+#define SSI_DMACR_RDMAE_LSB    _u(0)
+#define SSI_DMACR_RDMAE_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_DMATDLR
+// Description : DMA TX data level
+#define SSI_DMATDLR_OFFSET _u(0x00000050)
+#define SSI_DMATDLR_BITS   _u(0x000000ff)
+#define SSI_DMATDLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_DMATDLR_DMATDL
+// Description : Transmit data watermark level
+#define SSI_DMATDLR_DMATDL_RESET  _u(0x00)
+#define SSI_DMATDLR_DMATDL_BITS   _u(0x000000ff)
+#define SSI_DMATDLR_DMATDL_MSB    _u(7)
+#define SSI_DMATDLR_DMATDL_LSB    _u(0)
+#define SSI_DMATDLR_DMATDL_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_DMARDLR
+// Description : DMA RX data level
+#define SSI_DMARDLR_OFFSET _u(0x00000054)
+#define SSI_DMARDLR_BITS   _u(0x000000ff)
+#define SSI_DMARDLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_DMARDLR_DMARDL
+// Description : Receive data watermark level (DMARDLR+1)
+#define SSI_DMARDLR_DMARDL_RESET  _u(0x00)
+#define SSI_DMARDLR_DMARDL_BITS   _u(0x000000ff)
+#define SSI_DMARDLR_DMARDL_MSB    _u(7)
+#define SSI_DMARDLR_DMARDL_LSB    _u(0)
+#define SSI_DMARDLR_DMARDL_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_IDR
+// Description : Identification register
+#define SSI_IDR_OFFSET _u(0x00000058)
+#define SSI_IDR_BITS   _u(0xffffffff)
+#define SSI_IDR_RESET  _u(0x51535049)
+// -----------------------------------------------------------------------------
+// Field       : SSI_IDR_IDCODE
+// Description : Peripheral dentification code
+#define SSI_IDR_IDCODE_RESET  _u(0x51535049)
+#define SSI_IDR_IDCODE_BITS   _u(0xffffffff)
+#define SSI_IDR_IDCODE_MSB    _u(31)
+#define SSI_IDR_IDCODE_LSB    _u(0)
+#define SSI_IDR_IDCODE_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_SSI_VERSION_ID
+// Description : Version ID
+#define SSI_SSI_VERSION_ID_OFFSET _u(0x0000005c)
+#define SSI_SSI_VERSION_ID_BITS   _u(0xffffffff)
+#define SSI_SSI_VERSION_ID_RESET  _u(0x3430312a)
+// -----------------------------------------------------------------------------
+// Field       : SSI_SSI_VERSION_ID_SSI_COMP_VERSION
+// Description : SNPS component version (format X.YY)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET  _u(0x3430312a)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS   _u(0xffffffff)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB    _u(31)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB    _u(0)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_DR0
+// Description : Data Register 0 (of 36)
+#define SSI_DR0_OFFSET _u(0x00000060)
+#define SSI_DR0_BITS   _u(0xffffffff)
+#define SSI_DR0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_DR0_DR
+// Description : First data register of 36
+#define SSI_DR0_DR_RESET  _u(0x00000000)
+#define SSI_DR0_DR_BITS   _u(0xffffffff)
+#define SSI_DR0_DR_MSB    _u(31)
+#define SSI_DR0_DR_LSB    _u(0)
+#define SSI_DR0_DR_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_RX_SAMPLE_DLY
+// Description : RX sample delay
+#define SSI_RX_SAMPLE_DLY_OFFSET _u(0x000000f0)
+#define SSI_RX_SAMPLE_DLY_BITS   _u(0x000000ff)
+#define SSI_RX_SAMPLE_DLY_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_RX_SAMPLE_DLY_RSD
+// Description : RXD sample delay (in SCLK cycles)
+#define SSI_RX_SAMPLE_DLY_RSD_RESET  _u(0x00)
+#define SSI_RX_SAMPLE_DLY_RSD_BITS   _u(0x000000ff)
+#define SSI_RX_SAMPLE_DLY_RSD_MSB    _u(7)
+#define SSI_RX_SAMPLE_DLY_RSD_LSB    _u(0)
+#define SSI_RX_SAMPLE_DLY_RSD_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_SPI_CTRLR0
+// Description : SPI control
+#define SSI_SPI_CTRLR0_OFFSET _u(0x000000f4)
+#define SSI_SPI_CTRLR0_BITS   _u(0xff07fb3f)
+#define SSI_SPI_CTRLR0_RESET  _u(0x03000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_XIP_CMD
+// Description : SPI Command to send in XIP mode (INST_L = 8-bit) or to append
+//               to Address (INST_L = 0-bit)
+#define SSI_SPI_CTRLR0_XIP_CMD_RESET  _u(0x03)
+#define SSI_SPI_CTRLR0_XIP_CMD_BITS   _u(0xff000000)
+#define SSI_SPI_CTRLR0_XIP_CMD_MSB    _u(31)
+#define SSI_SPI_CTRLR0_XIP_CMD_LSB    _u(24)
+#define SSI_SPI_CTRLR0_XIP_CMD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_SPI_RXDS_EN
+// Description : Read data strobe enable
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET  _u(0x0)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS   _u(0x00040000)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB    _u(18)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB    _u(18)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_INST_DDR_EN
+// Description : Instruction DDR transfer enable
+#define SSI_SPI_CTRLR0_INST_DDR_EN_RESET  _u(0x0)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_BITS   _u(0x00020000)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_MSB    _u(17)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_LSB    _u(17)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_SPI_DDR_EN
+// Description : SPI DDR transfer enable
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET  _u(0x0)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS   _u(0x00010000)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB    _u(16)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB    _u(16)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_WAIT_CYCLES
+// Description : Wait cycles between control frame transmit and data reception
+//               (in SCLK cycles)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET  _u(0x00)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS   _u(0x0000f800)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB    _u(15)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB    _u(11)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_INST_L
+// Description : Instruction length (0/4/8/16b)
+//               0x0 -> No instruction
+//               0x1 -> 4-bit instruction
+//               0x2 -> 8-bit instruction
+//               0x3 -> 16-bit instruction
+#define SSI_SPI_CTRLR0_INST_L_RESET      _u(0x0)
+#define SSI_SPI_CTRLR0_INST_L_BITS       _u(0x00000300)
+#define SSI_SPI_CTRLR0_INST_L_MSB        _u(9)
+#define SSI_SPI_CTRLR0_INST_L_LSB        _u(8)
+#define SSI_SPI_CTRLR0_INST_L_ACCESS     "RW"
+#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE _u(0x0)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_4B   _u(0x1)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_8B   _u(0x2)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_16B  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_ADDR_L
+// Description : Address length (0b-60b in 4b increments)
+#define SSI_SPI_CTRLR0_ADDR_L_RESET  _u(0x0)
+#define SSI_SPI_CTRLR0_ADDR_L_BITS   _u(0x0000003c)
+#define SSI_SPI_CTRLR0_ADDR_L_MSB    _u(5)
+#define SSI_SPI_CTRLR0_ADDR_L_LSB    _u(2)
+#define SSI_SPI_CTRLR0_ADDR_L_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_TRANS_TYPE
+// Description : Address and instruction transfer format
+//               0x0 -> Command and address both in standard SPI frame format
+//               0x1 -> Command in standard SPI format, address in format
+//               specified by FRF
+//               0x2 -> Command and address both in format specified by FRF
+//               (e.g. Dual-SPI)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET      _u(0x0)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS       _u(0x00000003)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB        _u(1)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB        _u(0)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS     "RW"
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A _u(0x0)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A _u(0x1)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A _u(0x2)
+// =============================================================================
+// Register    : SSI_TXD_DRIVE_EDGE
+// Description : TX drive edge
+#define SSI_TXD_DRIVE_EDGE_OFFSET _u(0x000000f8)
+#define SSI_TXD_DRIVE_EDGE_BITS   _u(0x000000ff)
+#define SSI_TXD_DRIVE_EDGE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_TXD_DRIVE_EDGE_TDE
+// Description : TXD drive edge
+#define SSI_TXD_DRIVE_EDGE_TDE_RESET  _u(0x00)
+#define SSI_TXD_DRIVE_EDGE_TDE_BITS   _u(0x000000ff)
+#define SSI_TXD_DRIVE_EDGE_TDE_MSB    _u(7)
+#define SSI_TXD_DRIVE_EDGE_TDE_LSB    _u(0)
+#define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_SSI_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/syscfg.h b/src/rp2040/hardware_regs/include/hardware/regs/syscfg.h
new file mode 100644
index 0000000..2bf09e2
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/syscfg.h
@@ -0,0 +1,257 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : SYSCFG
+// Version        : 1
+// Bus type       : apb
+// Description    : Register block for various chip control signals
+// =============================================================================
+#ifndef HARDWARE_REGS_SYSCFG_DEFINED
+#define HARDWARE_REGS_SYSCFG_DEFINED
+// =============================================================================
+// Register    : SYSCFG_PROC0_NMI_MASK
+// Description : Processor core 0 NMI source mask
+//               Set a bit high to enable NMI from that IRQ
+#define SYSCFG_PROC0_NMI_MASK_OFFSET _u(0x00000000)
+#define SYSCFG_PROC0_NMI_MASK_BITS   _u(0xffffffff)
+#define SYSCFG_PROC0_NMI_MASK_RESET  _u(0x00000000)
+#define SYSCFG_PROC0_NMI_MASK_MSB    _u(31)
+#define SYSCFG_PROC0_NMI_MASK_LSB    _u(0)
+#define SYSCFG_PROC0_NMI_MASK_ACCESS "RW"
+// =============================================================================
+// Register    : SYSCFG_PROC1_NMI_MASK
+// Description : Processor core 1 NMI source mask
+//               Set a bit high to enable NMI from that IRQ
+#define SYSCFG_PROC1_NMI_MASK_OFFSET _u(0x00000004)
+#define SYSCFG_PROC1_NMI_MASK_BITS   _u(0xffffffff)
+#define SYSCFG_PROC1_NMI_MASK_RESET  _u(0x00000000)
+#define SYSCFG_PROC1_NMI_MASK_MSB    _u(31)
+#define SYSCFG_PROC1_NMI_MASK_LSB    _u(0)
+#define SYSCFG_PROC1_NMI_MASK_ACCESS "RW"
+// =============================================================================
+// Register    : SYSCFG_PROC_CONFIG
+// Description : Configuration for processors
+#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000008)
+#define SYSCFG_PROC_CONFIG_BITS   _u(0xff000003)
+#define SYSCFG_PROC_CONFIG_RESET  _u(0x10000000)
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID
+// Description : Configure proc1 DAP instance ID.
+//               Recommend that this is NOT changed until you require debug
+//               access in multi-chip environment
+//               WARNING: do not set to 15 as this is reserved for RescueDP
+#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET  _u(0x1)
+#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS   _u(0xf0000000)
+#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB    _u(31)
+#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB    _u(28)
+#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID
+// Description : Configure proc0 DAP instance ID.
+//               Recommend that this is NOT changed until you require debug
+//               access in multi-chip environment
+//               WARNING: do not set to 15 as this is reserved for RescueDP
+#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET  _u(0x0)
+#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS   _u(0x0f000000)
+#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB    _u(27)
+#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB    _u(24)
+#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_PROC_CONFIG_PROC1_HALTED
+// Description : Indication that proc1 has halted
+#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET  _u(0x0)
+#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS   _u(0x00000002)
+#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB    _u(1)
+#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB    _u(1)
+#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_PROC_CONFIG_PROC0_HALTED
+// Description : Indication that proc0 has halted
+#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET  _u(0x0)
+#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS   _u(0x00000001)
+#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB    _u(0)
+#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB    _u(0)
+#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO"
+// =============================================================================
+// Register    : SYSCFG_PROC_IN_SYNC_BYPASS
+// Description : For each bit, if 1, bypass the input synchronizer between that
+//               GPIO
+//               and the GPIO input register in the SIO. The input synchronizers
+//               should
+//               generally be unbypassed, to avoid injecting metastabilities
+//               into processors.
+//               If you're feeling brave, you can bypass to save two cycles of
+//               input
+//               latency. This register applies to GPIO 0...29.
+#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x0000000c)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS   _u(0x3fffffff)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET  _u(0x00000000)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB    _u(29)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB    _u(0)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW"
+// =============================================================================
+// Register    : SYSCFG_PROC_IN_SYNC_BYPASS_HI
+// Description : For each bit, if 1, bypass the input synchronizer between that
+//               GPIO
+//               and the GPIO input register in the SIO. The input synchronizers
+//               should
+//               generally be unbypassed, to avoid injecting metastabilities
+//               into processors.
+//               If you're feeling brave, you can bypass to save two cycles of
+//               input
+//               latency. This register applies to GPIO 30...35 (the QSPI IOs).
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000010)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS   _u(0x0000003f)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET  _u(0x00000000)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB    _u(5)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB    _u(0)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW"
+// =============================================================================
+// Register    : SYSCFG_DBGFORCE
+// Description : Directly control the SWD debug port of either processor
+#define SYSCFG_DBGFORCE_OFFSET _u(0x00000014)
+#define SYSCFG_DBGFORCE_BITS   _u(0x000000ff)
+#define SYSCFG_DBGFORCE_RESET  _u(0x00000066)
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_DBGFORCE_PROC1_ATTACH
+// Description : Attach processor 1 debug port to syscfg controls, and
+//               disconnect it from external SWD pads.
+#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET  _u(0x0)
+#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS   _u(0x00000080)
+#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB    _u(7)
+#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB    _u(7)
+#define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_DBGFORCE_PROC1_SWCLK
+// Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
+#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET  _u(0x1)
+#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS   _u(0x00000040)
+#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB    _u(6)
+#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB    _u(6)
+#define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_DBGFORCE_PROC1_SWDI
+// Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
+#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET  _u(0x1)
+#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS   _u(0x00000020)
+#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB    _u(5)
+#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB    _u(5)
+#define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_DBGFORCE_PROC1_SWDO
+// Description : Observe the value of processor 1 SWDIO output.
+#define SYSCFG_DBGFORCE_PROC1_SWDO_RESET  "-"
+#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS   _u(0x00000010)
+#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB    _u(4)
+#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB    _u(4)
+#define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_DBGFORCE_PROC0_ATTACH
+// Description : Attach processor 0 debug port to syscfg controls, and
+//               disconnect it from external SWD pads.
+#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET  _u(0x0)
+#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS   _u(0x00000008)
+#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB    _u(3)
+#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB    _u(3)
+#define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_DBGFORCE_PROC0_SWCLK
+// Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
+#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET  _u(0x1)
+#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS   _u(0x00000004)
+#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB    _u(2)
+#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB    _u(2)
+#define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_DBGFORCE_PROC0_SWDI
+// Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
+#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET  _u(0x1)
+#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS   _u(0x00000002)
+#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB    _u(1)
+#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB    _u(1)
+#define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_DBGFORCE_PROC0_SWDO
+// Description : Observe the value of processor 0 SWDIO output.
+#define SYSCFG_DBGFORCE_PROC0_SWDO_RESET  "-"
+#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS   _u(0x00000001)
+#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB    _u(0)
+#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB    _u(0)
+#define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO"
+// =============================================================================
+// Register    : SYSCFG_MEMPOWERDOWN
+// Description : Control power downs to memories. Set high to power down
+//               memories.
+//               Use with extreme caution
+#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000018)
+#define SYSCFG_MEMPOWERDOWN_BITS   _u(0x000000ff)
+#define SYSCFG_MEMPOWERDOWN_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_MEMPOWERDOWN_ROM
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_ROM_RESET  _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_ROM_BITS   _u(0x00000080)
+#define SYSCFG_MEMPOWERDOWN_ROM_MSB    _u(7)
+#define SYSCFG_MEMPOWERDOWN_ROM_LSB    _u(7)
+#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_MEMPOWERDOWN_USB
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_USB_RESET  _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_USB_BITS   _u(0x00000040)
+#define SYSCFG_MEMPOWERDOWN_USB_MSB    _u(6)
+#define SYSCFG_MEMPOWERDOWN_USB_LSB    _u(6)
+#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_MEMPOWERDOWN_SRAM5
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET  _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS   _u(0x00000020)
+#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB    _u(5)
+#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB    _u(5)
+#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_MEMPOWERDOWN_SRAM4
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET  _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS   _u(0x00000010)
+#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB    _u(4)
+#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB    _u(4)
+#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_MEMPOWERDOWN_SRAM3
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET  _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS   _u(0x00000008)
+#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB    _u(3)
+#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB    _u(3)
+#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_MEMPOWERDOWN_SRAM2
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET  _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS   _u(0x00000004)
+#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB    _u(2)
+#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB    _u(2)
+#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_MEMPOWERDOWN_SRAM1
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET  _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS   _u(0x00000002)
+#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB    _u(1)
+#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB    _u(1)
+#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SYSCFG_MEMPOWERDOWN_SRAM0
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET  _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS   _u(0x00000001)
+#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB    _u(0)
+#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB    _u(0)
+#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_SYSCFG_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h b/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h
new file mode 100644
index 0000000..2a46658
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h
@@ -0,0 +1,77 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : SYSINFO
+// Version        : 1
+// Bus type       : apb
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_SYSINFO_DEFINED
+#define HARDWARE_REGS_SYSINFO_DEFINED
+// =============================================================================
+// Register    : SYSINFO_CHIP_ID
+// Description : JEDEC JEP-106 compliant chip identifier.
+#define SYSINFO_CHIP_ID_OFFSET _u(0x00000000)
+#define SYSINFO_CHIP_ID_BITS   _u(0xffffffff)
+#define SYSINFO_CHIP_ID_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SYSINFO_CHIP_ID_REVISION
+// Description : None
+#define SYSINFO_CHIP_ID_REVISION_RESET  "-"
+#define SYSINFO_CHIP_ID_REVISION_BITS   _u(0xf0000000)
+#define SYSINFO_CHIP_ID_REVISION_MSB    _u(31)
+#define SYSINFO_CHIP_ID_REVISION_LSB    _u(28)
+#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SYSINFO_CHIP_ID_PART
+// Description : None
+#define SYSINFO_CHIP_ID_PART_RESET  "-"
+#define SYSINFO_CHIP_ID_PART_BITS   _u(0x0ffff000)
+#define SYSINFO_CHIP_ID_PART_MSB    _u(27)
+#define SYSINFO_CHIP_ID_PART_LSB    _u(12)
+#define SYSINFO_CHIP_ID_PART_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SYSINFO_CHIP_ID_MANUFACTURER
+// Description : None
+#define SYSINFO_CHIP_ID_MANUFACTURER_RESET  "-"
+#define SYSINFO_CHIP_ID_MANUFACTURER_BITS   _u(0x00000fff)
+#define SYSINFO_CHIP_ID_MANUFACTURER_MSB    _u(11)
+#define SYSINFO_CHIP_ID_MANUFACTURER_LSB    _u(0)
+#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO"
+// =============================================================================
+// Register    : SYSINFO_PLATFORM
+// Description : Platform register. Allows software to know what environment it
+//               is running in.
+#define SYSINFO_PLATFORM_OFFSET _u(0x00000004)
+#define SYSINFO_PLATFORM_BITS   _u(0x00000003)
+#define SYSINFO_PLATFORM_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SYSINFO_PLATFORM_ASIC
+// Description : None
+#define SYSINFO_PLATFORM_ASIC_RESET  _u(0x0)
+#define SYSINFO_PLATFORM_ASIC_BITS   _u(0x00000002)
+#define SYSINFO_PLATFORM_ASIC_MSB    _u(1)
+#define SYSINFO_PLATFORM_ASIC_LSB    _u(1)
+#define SYSINFO_PLATFORM_ASIC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SYSINFO_PLATFORM_FPGA
+// Description : None
+#define SYSINFO_PLATFORM_FPGA_RESET  _u(0x0)
+#define SYSINFO_PLATFORM_FPGA_BITS   _u(0x00000001)
+#define SYSINFO_PLATFORM_FPGA_MSB    _u(0)
+#define SYSINFO_PLATFORM_FPGA_LSB    _u(0)
+#define SYSINFO_PLATFORM_FPGA_ACCESS "RO"
+// =============================================================================
+// Register    : SYSINFO_GITREF_RP2040
+// Description : Git hash of the chip source. Used to identify chip version.
+#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000040)
+#define SYSINFO_GITREF_RP2040_BITS   _u(0xffffffff)
+#define SYSINFO_GITREF_RP2040_RESET  "-"
+#define SYSINFO_GITREF_RP2040_MSB    _u(31)
+#define SYSINFO_GITREF_RP2040_LSB    _u(0)
+#define SYSINFO_GITREF_RP2040_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_SYSINFO_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/tbman.h b/src/rp2040/hardware_regs/include/hardware/regs/tbman.h
new file mode 100644
index 0000000..4f8f641
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/tbman.h
@@ -0,0 +1,38 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : TBMAN
+// Version        : 1
+// Bus type       : apb
+// Description    : Testbench manager. Allows the programmer to know what
+//                  platform their software is running on.
+// =============================================================================
+#ifndef HARDWARE_REGS_TBMAN_DEFINED
+#define HARDWARE_REGS_TBMAN_DEFINED
+// =============================================================================
+// Register    : TBMAN_PLATFORM
+// Description : Indicates the type of platform in use
+#define TBMAN_PLATFORM_OFFSET _u(0x00000000)
+#define TBMAN_PLATFORM_BITS   _u(0x00000003)
+#define TBMAN_PLATFORM_RESET  _u(0x00000005)
+// -----------------------------------------------------------------------------
+// Field       : TBMAN_PLATFORM_FPGA
+// Description : Indicates the platform is an FPGA
+#define TBMAN_PLATFORM_FPGA_RESET  _u(0x0)
+#define TBMAN_PLATFORM_FPGA_BITS   _u(0x00000002)
+#define TBMAN_PLATFORM_FPGA_MSB    _u(1)
+#define TBMAN_PLATFORM_FPGA_LSB    _u(1)
+#define TBMAN_PLATFORM_FPGA_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : TBMAN_PLATFORM_ASIC
+// Description : Indicates the platform is an ASIC
+#define TBMAN_PLATFORM_ASIC_RESET  _u(0x1)
+#define TBMAN_PLATFORM_ASIC_BITS   _u(0x00000001)
+#define TBMAN_PLATFORM_ASIC_MSB    _u(0)
+#define TBMAN_PLATFORM_ASIC_LSB    _u(0)
+#define TBMAN_PLATFORM_ASIC_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_TBMAN_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/timer.h b/src/rp2040/hardware_regs/include/hardware/regs/timer.h
new file mode 100644
index 0000000..c3ef0c5
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/timer.h
@@ -0,0 +1,332 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : TIMER
+// Version        : 1
+// Bus type       : apb
+// Description    : Controls time and alarms
+//                  time is a 64 bit value indicating the time in usec since
+//                  power-on
+//                  timeh is the top 32 bits of time & timel is the bottom 32
+//                  bits
+//                  to change time write to timelw before timehw
+//                  to read time read from timelr before timehr
+//                  An alarm is set by setting alarm_enable and writing to the
+//                  corresponding alarm register
+//                  When an alarm is pending, the corresponding alarm_running
+//                  signal will be high
+//                  An alarm can be cancelled before it has finished by clearing
+//                  the alarm_enable
+//                  When an alarm fires, the corresponding alarm_irq is set and
+//                  alarm_running is cleared
+//                  To clear the interrupt write a 1 to the corresponding
+//                  alarm_irq
+// =============================================================================
+#ifndef HARDWARE_REGS_TIMER_DEFINED
+#define HARDWARE_REGS_TIMER_DEFINED
+// =============================================================================
+// Register    : TIMER_TIMEHW
+// Description : Write to bits 63:32 of time
+//               always write timelw before timehw
+#define TIMER_TIMEHW_OFFSET _u(0x00000000)
+#define TIMER_TIMEHW_BITS   _u(0xffffffff)
+#define TIMER_TIMEHW_RESET  _u(0x00000000)
+#define TIMER_TIMEHW_MSB    _u(31)
+#define TIMER_TIMEHW_LSB    _u(0)
+#define TIMER_TIMEHW_ACCESS "WF"
+// =============================================================================
+// Register    : TIMER_TIMELW
+// Description : Write to bits 31:0 of time
+//               writes do not get copied to time until timehw is written
+#define TIMER_TIMELW_OFFSET _u(0x00000004)
+#define TIMER_TIMELW_BITS   _u(0xffffffff)
+#define TIMER_TIMELW_RESET  _u(0x00000000)
+#define TIMER_TIMELW_MSB    _u(31)
+#define TIMER_TIMELW_LSB    _u(0)
+#define TIMER_TIMELW_ACCESS "WF"
+// =============================================================================
+// Register    : TIMER_TIMEHR
+// Description : Read from bits 63:32 of time
+//               always read timelr before timehr
+#define TIMER_TIMEHR_OFFSET _u(0x00000008)
+#define TIMER_TIMEHR_BITS   _u(0xffffffff)
+#define TIMER_TIMEHR_RESET  _u(0x00000000)
+#define TIMER_TIMEHR_MSB    _u(31)
+#define TIMER_TIMEHR_LSB    _u(0)
+#define TIMER_TIMEHR_ACCESS "RO"
+// =============================================================================
+// Register    : TIMER_TIMELR
+// Description : Read from bits 31:0 of time
+#define TIMER_TIMELR_OFFSET _u(0x0000000c)
+#define TIMER_TIMELR_BITS   _u(0xffffffff)
+#define TIMER_TIMELR_RESET  _u(0x00000000)
+#define TIMER_TIMELR_MSB    _u(31)
+#define TIMER_TIMELR_LSB    _u(0)
+#define TIMER_TIMELR_ACCESS "RO"
+// =============================================================================
+// Register    : TIMER_ALARM0
+// Description : Arm alarm 0, and configure the time it will fire.
+//               Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.
+//               The alarm will disarm itself once it fires, and can
+//               be disarmed early using the ARMED status register.
+#define TIMER_ALARM0_OFFSET _u(0x00000010)
+#define TIMER_ALARM0_BITS   _u(0xffffffff)
+#define TIMER_ALARM0_RESET  _u(0x00000000)
+#define TIMER_ALARM0_MSB    _u(31)
+#define TIMER_ALARM0_LSB    _u(0)
+#define TIMER_ALARM0_ACCESS "RW"
+// =============================================================================
+// Register    : TIMER_ALARM1
+// Description : Arm alarm 1, and configure the time it will fire.
+//               Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
+//               The alarm will disarm itself once it fires, and can
+//               be disarmed early using the ARMED status register.
+#define TIMER_ALARM1_OFFSET _u(0x00000014)
+#define TIMER_ALARM1_BITS   _u(0xffffffff)
+#define TIMER_ALARM1_RESET  _u(0x00000000)
+#define TIMER_ALARM1_MSB    _u(31)
+#define TIMER_ALARM1_LSB    _u(0)
+#define TIMER_ALARM1_ACCESS "RW"
+// =============================================================================
+// Register    : TIMER_ALARM2
+// Description : Arm alarm 2, and configure the time it will fire.
+//               Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.
+//               The alarm will disarm itself once it fires, and can
+//               be disarmed early using the ARMED status register.
+#define TIMER_ALARM2_OFFSET _u(0x00000018)
+#define TIMER_ALARM2_BITS   _u(0xffffffff)
+#define TIMER_ALARM2_RESET  _u(0x00000000)
+#define TIMER_ALARM2_MSB    _u(31)
+#define TIMER_ALARM2_LSB    _u(0)
+#define TIMER_ALARM2_ACCESS "RW"
+// =============================================================================
+// Register    : TIMER_ALARM3
+// Description : Arm alarm 3, and configure the time it will fire.
+//               Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.
+//               The alarm will disarm itself once it fires, and can
+//               be disarmed early using the ARMED status register.
+#define TIMER_ALARM3_OFFSET _u(0x0000001c)
+#define TIMER_ALARM3_BITS   _u(0xffffffff)
+#define TIMER_ALARM3_RESET  _u(0x00000000)
+#define TIMER_ALARM3_MSB    _u(31)
+#define TIMER_ALARM3_LSB    _u(0)
+#define TIMER_ALARM3_ACCESS "RW"
+// =============================================================================
+// Register    : TIMER_ARMED
+// Description : Indicates the armed/disarmed status of each alarm.
+//               A write to the corresponding ALARMx register arms the alarm.
+//               Alarms automatically disarm upon firing, but writing ones here
+//               will disarm immediately without waiting to fire.
+#define TIMER_ARMED_OFFSET _u(0x00000020)
+#define TIMER_ARMED_BITS   _u(0x0000000f)
+#define TIMER_ARMED_RESET  _u(0x00000000)
+#define TIMER_ARMED_MSB    _u(3)
+#define TIMER_ARMED_LSB    _u(0)
+#define TIMER_ARMED_ACCESS "WC"
+// =============================================================================
+// Register    : TIMER_TIMERAWH
+// Description : Raw read from bits 63:32 of time (no side effects)
+#define TIMER_TIMERAWH_OFFSET _u(0x00000024)
+#define TIMER_TIMERAWH_BITS   _u(0xffffffff)
+#define TIMER_TIMERAWH_RESET  _u(0x00000000)
+#define TIMER_TIMERAWH_MSB    _u(31)
+#define TIMER_TIMERAWH_LSB    _u(0)
+#define TIMER_TIMERAWH_ACCESS "RO"
+// =============================================================================
+// Register    : TIMER_TIMERAWL
+// Description : Raw read from bits 31:0 of time (no side effects)
+#define TIMER_TIMERAWL_OFFSET _u(0x00000028)
+#define TIMER_TIMERAWL_BITS   _u(0xffffffff)
+#define TIMER_TIMERAWL_RESET  _u(0x00000000)
+#define TIMER_TIMERAWL_MSB    _u(31)
+#define TIMER_TIMERAWL_LSB    _u(0)
+#define TIMER_TIMERAWL_ACCESS "RO"
+// =============================================================================
+// Register    : TIMER_DBGPAUSE
+// Description : Set bits high to enable pause when the corresponding debug
+//               ports are active
+#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c)
+#define TIMER_DBGPAUSE_BITS   _u(0x00000006)
+#define TIMER_DBGPAUSE_RESET  _u(0x00000007)
+// -----------------------------------------------------------------------------
+// Field       : TIMER_DBGPAUSE_DBG1
+// Description : Pause when processor 1 is in debug mode
+#define TIMER_DBGPAUSE_DBG1_RESET  _u(0x1)
+#define TIMER_DBGPAUSE_DBG1_BITS   _u(0x00000004)
+#define TIMER_DBGPAUSE_DBG1_MSB    _u(2)
+#define TIMER_DBGPAUSE_DBG1_LSB    _u(2)
+#define TIMER_DBGPAUSE_DBG1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : TIMER_DBGPAUSE_DBG0
+// Description : Pause when processor 0 is in debug mode
+#define TIMER_DBGPAUSE_DBG0_RESET  _u(0x1)
+#define TIMER_DBGPAUSE_DBG0_BITS   _u(0x00000002)
+#define TIMER_DBGPAUSE_DBG0_MSB    _u(1)
+#define TIMER_DBGPAUSE_DBG0_LSB    _u(1)
+#define TIMER_DBGPAUSE_DBG0_ACCESS "RW"
+// =============================================================================
+// Register    : TIMER_PAUSE
+// Description : Set high to pause the timer
+#define TIMER_PAUSE_OFFSET _u(0x00000030)
+#define TIMER_PAUSE_BITS   _u(0x00000001)
+#define TIMER_PAUSE_RESET  _u(0x00000000)
+#define TIMER_PAUSE_MSB    _u(0)
+#define TIMER_PAUSE_LSB    _u(0)
+#define TIMER_PAUSE_ACCESS "RW"
+// =============================================================================
+// Register    : TIMER_INTR
+// Description : Raw Interrupts
+#define TIMER_INTR_OFFSET _u(0x00000034)
+#define TIMER_INTR_BITS   _u(0x0000000f)
+#define TIMER_INTR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTR_ALARM_3
+// Description : None
+#define TIMER_INTR_ALARM_3_RESET  _u(0x0)
+#define TIMER_INTR_ALARM_3_BITS   _u(0x00000008)
+#define TIMER_INTR_ALARM_3_MSB    _u(3)
+#define TIMER_INTR_ALARM_3_LSB    _u(3)
+#define TIMER_INTR_ALARM_3_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTR_ALARM_2
+// Description : None
+#define TIMER_INTR_ALARM_2_RESET  _u(0x0)
+#define TIMER_INTR_ALARM_2_BITS   _u(0x00000004)
+#define TIMER_INTR_ALARM_2_MSB    _u(2)
+#define TIMER_INTR_ALARM_2_LSB    _u(2)
+#define TIMER_INTR_ALARM_2_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTR_ALARM_1
+// Description : None
+#define TIMER_INTR_ALARM_1_RESET  _u(0x0)
+#define TIMER_INTR_ALARM_1_BITS   _u(0x00000002)
+#define TIMER_INTR_ALARM_1_MSB    _u(1)
+#define TIMER_INTR_ALARM_1_LSB    _u(1)
+#define TIMER_INTR_ALARM_1_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTR_ALARM_0
+// Description : None
+#define TIMER_INTR_ALARM_0_RESET  _u(0x0)
+#define TIMER_INTR_ALARM_0_BITS   _u(0x00000001)
+#define TIMER_INTR_ALARM_0_MSB    _u(0)
+#define TIMER_INTR_ALARM_0_LSB    _u(0)
+#define TIMER_INTR_ALARM_0_ACCESS "WC"
+// =============================================================================
+// Register    : TIMER_INTE
+// Description : Interrupt Enable
+#define TIMER_INTE_OFFSET _u(0x00000038)
+#define TIMER_INTE_BITS   _u(0x0000000f)
+#define TIMER_INTE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTE_ALARM_3
+// Description : None
+#define TIMER_INTE_ALARM_3_RESET  _u(0x0)
+#define TIMER_INTE_ALARM_3_BITS   _u(0x00000008)
+#define TIMER_INTE_ALARM_3_MSB    _u(3)
+#define TIMER_INTE_ALARM_3_LSB    _u(3)
+#define TIMER_INTE_ALARM_3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTE_ALARM_2
+// Description : None
+#define TIMER_INTE_ALARM_2_RESET  _u(0x0)
+#define TIMER_INTE_ALARM_2_BITS   _u(0x00000004)
+#define TIMER_INTE_ALARM_2_MSB    _u(2)
+#define TIMER_INTE_ALARM_2_LSB    _u(2)
+#define TIMER_INTE_ALARM_2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTE_ALARM_1
+// Description : None
+#define TIMER_INTE_ALARM_1_RESET  _u(0x0)
+#define TIMER_INTE_ALARM_1_BITS   _u(0x00000002)
+#define TIMER_INTE_ALARM_1_MSB    _u(1)
+#define TIMER_INTE_ALARM_1_LSB    _u(1)
+#define TIMER_INTE_ALARM_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTE_ALARM_0
+// Description : None
+#define TIMER_INTE_ALARM_0_RESET  _u(0x0)
+#define TIMER_INTE_ALARM_0_BITS   _u(0x00000001)
+#define TIMER_INTE_ALARM_0_MSB    _u(0)
+#define TIMER_INTE_ALARM_0_LSB    _u(0)
+#define TIMER_INTE_ALARM_0_ACCESS "RW"
+// =============================================================================
+// Register    : TIMER_INTF
+// Description : Interrupt Force
+#define TIMER_INTF_OFFSET _u(0x0000003c)
+#define TIMER_INTF_BITS   _u(0x0000000f)
+#define TIMER_INTF_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTF_ALARM_3
+// Description : None
+#define TIMER_INTF_ALARM_3_RESET  _u(0x0)
+#define TIMER_INTF_ALARM_3_BITS   _u(0x00000008)
+#define TIMER_INTF_ALARM_3_MSB    _u(3)
+#define TIMER_INTF_ALARM_3_LSB    _u(3)
+#define TIMER_INTF_ALARM_3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTF_ALARM_2
+// Description : None
+#define TIMER_INTF_ALARM_2_RESET  _u(0x0)
+#define TIMER_INTF_ALARM_2_BITS   _u(0x00000004)
+#define TIMER_INTF_ALARM_2_MSB    _u(2)
+#define TIMER_INTF_ALARM_2_LSB    _u(2)
+#define TIMER_INTF_ALARM_2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTF_ALARM_1
+// Description : None
+#define TIMER_INTF_ALARM_1_RESET  _u(0x0)
+#define TIMER_INTF_ALARM_1_BITS   _u(0x00000002)
+#define TIMER_INTF_ALARM_1_MSB    _u(1)
+#define TIMER_INTF_ALARM_1_LSB    _u(1)
+#define TIMER_INTF_ALARM_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTF_ALARM_0
+// Description : None
+#define TIMER_INTF_ALARM_0_RESET  _u(0x0)
+#define TIMER_INTF_ALARM_0_BITS   _u(0x00000001)
+#define TIMER_INTF_ALARM_0_MSB    _u(0)
+#define TIMER_INTF_ALARM_0_LSB    _u(0)
+#define TIMER_INTF_ALARM_0_ACCESS "RW"
+// =============================================================================
+// Register    : TIMER_INTS
+// Description : Interrupt status after masking & forcing
+#define TIMER_INTS_OFFSET _u(0x00000040)
+#define TIMER_INTS_BITS   _u(0x0000000f)
+#define TIMER_INTS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTS_ALARM_3
+// Description : None
+#define TIMER_INTS_ALARM_3_RESET  _u(0x0)
+#define TIMER_INTS_ALARM_3_BITS   _u(0x00000008)
+#define TIMER_INTS_ALARM_3_MSB    _u(3)
+#define TIMER_INTS_ALARM_3_LSB    _u(3)
+#define TIMER_INTS_ALARM_3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTS_ALARM_2
+// Description : None
+#define TIMER_INTS_ALARM_2_RESET  _u(0x0)
+#define TIMER_INTS_ALARM_2_BITS   _u(0x00000004)
+#define TIMER_INTS_ALARM_2_MSB    _u(2)
+#define TIMER_INTS_ALARM_2_LSB    _u(2)
+#define TIMER_INTS_ALARM_2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTS_ALARM_1
+// Description : None
+#define TIMER_INTS_ALARM_1_RESET  _u(0x0)
+#define TIMER_INTS_ALARM_1_BITS   _u(0x00000002)
+#define TIMER_INTS_ALARM_1_MSB    _u(1)
+#define TIMER_INTS_ALARM_1_LSB    _u(1)
+#define TIMER_INTS_ALARM_1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : TIMER_INTS_ALARM_0
+// Description : None
+#define TIMER_INTS_ALARM_0_RESET  _u(0x0)
+#define TIMER_INTS_ALARM_0_BITS   _u(0x00000001)
+#define TIMER_INTS_ALARM_0_MSB    _u(0)
+#define TIMER_INTS_ALARM_0_LSB    _u(0)
+#define TIMER_INTS_ALARM_0_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_TIMER_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/uart.h b/src/rp2040/hardware_regs/include/hardware/regs/uart.h
new file mode 100644
index 0000000..409f598
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/uart.h
@@ -0,0 +1,1148 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : UART
+// Version        : 1
+// Bus type       : apb
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_UART_DEFINED
+#define HARDWARE_REGS_UART_DEFINED
+// =============================================================================
+// Register    : UART_UARTDR
+// Description : Data Register, UARTDR
+#define UART_UARTDR_OFFSET _u(0x00000000)
+#define UART_UARTDR_BITS   _u(0x00000fff)
+#define UART_UARTDR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTDR_OE
+// Description : Overrun error. This bit is set to 1 if data is received and the
+//               receive FIFO is already full. This is cleared to 0 once there
+//               is an empty space in the FIFO and a new character can be
+//               written to it.
+#define UART_UARTDR_OE_RESET  "-"
+#define UART_UARTDR_OE_BITS   _u(0x00000800)
+#define UART_UARTDR_OE_MSB    _u(11)
+#define UART_UARTDR_OE_LSB    _u(11)
+#define UART_UARTDR_OE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTDR_BE
+// Description : Break error. This bit is set to 1 if a break condition was
+//               detected, indicating that the received data input was held LOW
+//               for longer than a full-word transmission time (defined as
+//               start, data, parity and stop bits). In FIFO mode, this error is
+//               associated with the character at the top of the FIFO. When a
+//               break occurs, only one 0 character is loaded into the FIFO. The
+//               next character is only enabled after the receive data input
+//               goes to a 1 (marking state), and the next valid start bit is
+//               received.
+#define UART_UARTDR_BE_RESET  "-"
+#define UART_UARTDR_BE_BITS   _u(0x00000400)
+#define UART_UARTDR_BE_MSB    _u(10)
+#define UART_UARTDR_BE_LSB    _u(10)
+#define UART_UARTDR_BE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTDR_PE
+// Description : Parity error. When set to 1, it indicates that the parity of
+//               the received data character does not match the parity that the
+//               EPS and SPS bits in the Line Control Register, UARTLCR_H. In
+//               FIFO mode, this error is associated with the character at the
+//               top of the FIFO.
+#define UART_UARTDR_PE_RESET  "-"
+#define UART_UARTDR_PE_BITS   _u(0x00000200)
+#define UART_UARTDR_PE_MSB    _u(9)
+#define UART_UARTDR_PE_LSB    _u(9)
+#define UART_UARTDR_PE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTDR_FE
+// Description : Framing error. When set to 1, it indicates that the received
+//               character did not have a valid stop bit (a valid stop bit is
+//               1). In FIFO mode, this error is associated with the character
+//               at the top of the FIFO.
+#define UART_UARTDR_FE_RESET  "-"
+#define UART_UARTDR_FE_BITS   _u(0x00000100)
+#define UART_UARTDR_FE_MSB    _u(8)
+#define UART_UARTDR_FE_LSB    _u(8)
+#define UART_UARTDR_FE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTDR_DATA
+// Description : Receive (read) data character. Transmit (write) data character.
+#define UART_UARTDR_DATA_RESET  "-"
+#define UART_UARTDR_DATA_BITS   _u(0x000000ff)
+#define UART_UARTDR_DATA_MSB    _u(7)
+#define UART_UARTDR_DATA_LSB    _u(0)
+#define UART_UARTDR_DATA_ACCESS "RWF"
+// =============================================================================
+// Register    : UART_UARTRSR
+// Description : Receive Status Register/Error Clear Register, UARTRSR/UARTECR
+#define UART_UARTRSR_OFFSET _u(0x00000004)
+#define UART_UARTRSR_BITS   _u(0x0000000f)
+#define UART_UARTRSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRSR_OE
+// Description : Overrun error. This bit is set to 1 if data is received and the
+//               FIFO is already full. This bit is cleared to 0 by a write to
+//               UARTECR. The FIFO contents remain valid because no more data is
+//               written when the FIFO is full, only the contents of the shift
+//               register are overwritten. The CPU must now read the data, to
+//               empty the FIFO.
+#define UART_UARTRSR_OE_RESET  _u(0x0)
+#define UART_UARTRSR_OE_BITS   _u(0x00000008)
+#define UART_UARTRSR_OE_MSB    _u(3)
+#define UART_UARTRSR_OE_LSB    _u(3)
+#define UART_UARTRSR_OE_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRSR_BE
+// Description : Break error. This bit is set to 1 if a break condition was
+//               detected, indicating that the received data input was held LOW
+//               for longer than a full-word transmission time (defined as
+//               start, data, parity, and stop bits). This bit is cleared to 0
+//               after a write to UARTECR. In FIFO mode, this error is
+//               associated with the character at the top of the FIFO. When a
+//               break occurs, only one 0 character is loaded into the FIFO. The
+//               next character is only enabled after the receive data input
+//               goes to a 1 (marking state) and the next valid start bit is
+//               received.
+#define UART_UARTRSR_BE_RESET  _u(0x0)
+#define UART_UARTRSR_BE_BITS   _u(0x00000004)
+#define UART_UARTRSR_BE_MSB    _u(2)
+#define UART_UARTRSR_BE_LSB    _u(2)
+#define UART_UARTRSR_BE_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRSR_PE
+// Description : Parity error. When set to 1, it indicates that the parity of
+//               the received data character does not match the parity that the
+//               EPS and SPS bits in the Line Control Register, UARTLCR_H. This
+//               bit is cleared to 0 by a write to UARTECR. In FIFO mode, this
+//               error is associated with the character at the top of the FIFO.
+#define UART_UARTRSR_PE_RESET  _u(0x0)
+#define UART_UARTRSR_PE_BITS   _u(0x00000002)
+#define UART_UARTRSR_PE_MSB    _u(1)
+#define UART_UARTRSR_PE_LSB    _u(1)
+#define UART_UARTRSR_PE_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRSR_FE
+// Description : Framing error. When set to 1, it indicates that the received
+//               character did not have a valid stop bit (a valid stop bit is
+//               1). This bit is cleared to 0 by a write to UARTECR. In FIFO
+//               mode, this error is associated with the character at the top of
+//               the FIFO.
+#define UART_UARTRSR_FE_RESET  _u(0x0)
+#define UART_UARTRSR_FE_BITS   _u(0x00000001)
+#define UART_UARTRSR_FE_MSB    _u(0)
+#define UART_UARTRSR_FE_LSB    _u(0)
+#define UART_UARTRSR_FE_ACCESS "WC"
+// =============================================================================
+// Register    : UART_UARTFR
+// Description : Flag Register, UARTFR
+#define UART_UARTFR_OFFSET _u(0x00000018)
+#define UART_UARTFR_BITS   _u(0x000001ff)
+#define UART_UARTFR_RESET  _u(0x00000090)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTFR_RI
+// Description : Ring indicator. This bit is the complement of the UART ring
+//               indicator, nUARTRI, modem status input. That is, the bit is 1
+//               when nUARTRI is LOW.
+#define UART_UARTFR_RI_RESET  "-"
+#define UART_UARTFR_RI_BITS   _u(0x00000100)
+#define UART_UARTFR_RI_MSB    _u(8)
+#define UART_UARTFR_RI_LSB    _u(8)
+#define UART_UARTFR_RI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTFR_TXFE
+// Description : Transmit FIFO empty. The meaning of this bit depends on the
+//               state of the FEN bit in the Line Control Register, UARTLCR_H.
+//               If the FIFO is disabled, this bit is set when the transmit
+//               holding register is empty. If the FIFO is enabled, the TXFE bit
+//               is set when the transmit FIFO is empty. This bit does not
+//               indicate if there is data in the transmit shift register.
+#define UART_UARTFR_TXFE_RESET  _u(0x1)
+#define UART_UARTFR_TXFE_BITS   _u(0x00000080)
+#define UART_UARTFR_TXFE_MSB    _u(7)
+#define UART_UARTFR_TXFE_LSB    _u(7)
+#define UART_UARTFR_TXFE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTFR_RXFF
+// Description : Receive FIFO full. The meaning of this bit depends on the state
+//               of the FEN bit in the UARTLCR_H Register. If the FIFO is
+//               disabled, this bit is set when the receive holding register is
+//               full. If the FIFO is enabled, the RXFF bit is set when the
+//               receive FIFO is full.
+#define UART_UARTFR_RXFF_RESET  _u(0x0)
+#define UART_UARTFR_RXFF_BITS   _u(0x00000040)
+#define UART_UARTFR_RXFF_MSB    _u(6)
+#define UART_UARTFR_RXFF_LSB    _u(6)
+#define UART_UARTFR_RXFF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTFR_TXFF
+// Description : Transmit FIFO full. The meaning of this bit depends on the
+//               state of the FEN bit in the UARTLCR_H Register. If the FIFO is
+//               disabled, this bit is set when the transmit holding register is
+//               full. If the FIFO is enabled, the TXFF bit is set when the
+//               transmit FIFO is full.
+#define UART_UARTFR_TXFF_RESET  _u(0x0)
+#define UART_UARTFR_TXFF_BITS   _u(0x00000020)
+#define UART_UARTFR_TXFF_MSB    _u(5)
+#define UART_UARTFR_TXFF_LSB    _u(5)
+#define UART_UARTFR_TXFF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTFR_RXFE
+// Description : Receive FIFO empty. The meaning of this bit depends on the
+//               state of the FEN bit in the UARTLCR_H Register. If the FIFO is
+//               disabled, this bit is set when the receive holding register is
+//               empty. If the FIFO is enabled, the RXFE bit is set when the
+//               receive FIFO is empty.
+#define UART_UARTFR_RXFE_RESET  _u(0x1)
+#define UART_UARTFR_RXFE_BITS   _u(0x00000010)
+#define UART_UARTFR_RXFE_MSB    _u(4)
+#define UART_UARTFR_RXFE_LSB    _u(4)
+#define UART_UARTFR_RXFE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTFR_BUSY
+// Description : UART busy. If this bit is set to 1, the UART is busy
+//               transmitting data. This bit remains set until the complete
+//               byte, including all the stop bits, has been sent from the shift
+//               register. This bit is set as soon as the transmit FIFO becomes
+//               non-empty, regardless of whether the UART is enabled or not.
+#define UART_UARTFR_BUSY_RESET  _u(0x0)
+#define UART_UARTFR_BUSY_BITS   _u(0x00000008)
+#define UART_UARTFR_BUSY_MSB    _u(3)
+#define UART_UARTFR_BUSY_LSB    _u(3)
+#define UART_UARTFR_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTFR_DCD
+// Description : Data carrier detect. This bit is the complement of the UART
+//               data carrier detect, nUARTDCD, modem status input. That is, the
+//               bit is 1 when nUARTDCD is LOW.
+#define UART_UARTFR_DCD_RESET  "-"
+#define UART_UARTFR_DCD_BITS   _u(0x00000004)
+#define UART_UARTFR_DCD_MSB    _u(2)
+#define UART_UARTFR_DCD_LSB    _u(2)
+#define UART_UARTFR_DCD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTFR_DSR
+// Description : Data set ready. This bit is the complement of the UART data set
+//               ready, nUARTDSR, modem status input. That is, the bit is 1 when
+//               nUARTDSR is LOW.
+#define UART_UARTFR_DSR_RESET  "-"
+#define UART_UARTFR_DSR_BITS   _u(0x00000002)
+#define UART_UARTFR_DSR_MSB    _u(1)
+#define UART_UARTFR_DSR_LSB    _u(1)
+#define UART_UARTFR_DSR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTFR_CTS
+// Description : Clear to send. This bit is the complement of the UART clear to
+//               send, nUARTCTS, modem status input. That is, the bit is 1 when
+//               nUARTCTS is LOW.
+#define UART_UARTFR_CTS_RESET  "-"
+#define UART_UARTFR_CTS_BITS   _u(0x00000001)
+#define UART_UARTFR_CTS_MSB    _u(0)
+#define UART_UARTFR_CTS_LSB    _u(0)
+#define UART_UARTFR_CTS_ACCESS "RO"
+// =============================================================================
+// Register    : UART_UARTILPR
+// Description : IrDA Low-Power Counter Register, UARTILPR
+#define UART_UARTILPR_OFFSET _u(0x00000020)
+#define UART_UARTILPR_BITS   _u(0x000000ff)
+#define UART_UARTILPR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTILPR_ILPDVSR
+// Description : 8-bit low-power divisor value. These bits are cleared to 0 at
+//               reset.
+#define UART_UARTILPR_ILPDVSR_RESET  _u(0x00)
+#define UART_UARTILPR_ILPDVSR_BITS   _u(0x000000ff)
+#define UART_UARTILPR_ILPDVSR_MSB    _u(7)
+#define UART_UARTILPR_ILPDVSR_LSB    _u(0)
+#define UART_UARTILPR_ILPDVSR_ACCESS "RW"
+// =============================================================================
+// Register    : UART_UARTIBRD
+// Description : Integer Baud Rate Register, UARTIBRD
+#define UART_UARTIBRD_OFFSET _u(0x00000024)
+#define UART_UARTIBRD_BITS   _u(0x0000ffff)
+#define UART_UARTIBRD_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTIBRD_BAUD_DIVINT
+// Description : The integer baud rate divisor. These bits are cleared to 0 on
+//               reset.
+#define UART_UARTIBRD_BAUD_DIVINT_RESET  _u(0x0000)
+#define UART_UARTIBRD_BAUD_DIVINT_BITS   _u(0x0000ffff)
+#define UART_UARTIBRD_BAUD_DIVINT_MSB    _u(15)
+#define UART_UARTIBRD_BAUD_DIVINT_LSB    _u(0)
+#define UART_UARTIBRD_BAUD_DIVINT_ACCESS "RW"
+// =============================================================================
+// Register    : UART_UARTFBRD
+// Description : Fractional Baud Rate Register, UARTFBRD
+#define UART_UARTFBRD_OFFSET _u(0x00000028)
+#define UART_UARTFBRD_BITS   _u(0x0000003f)
+#define UART_UARTFBRD_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTFBRD_BAUD_DIVFRAC
+// Description : The fractional baud rate divisor. These bits are cleared to 0
+//               on reset.
+#define UART_UARTFBRD_BAUD_DIVFRAC_RESET  _u(0x00)
+#define UART_UARTFBRD_BAUD_DIVFRAC_BITS   _u(0x0000003f)
+#define UART_UARTFBRD_BAUD_DIVFRAC_MSB    _u(5)
+#define UART_UARTFBRD_BAUD_DIVFRAC_LSB    _u(0)
+#define UART_UARTFBRD_BAUD_DIVFRAC_ACCESS "RW"
+// =============================================================================
+// Register    : UART_UARTLCR_H
+// Description : Line Control Register, UARTLCR_H
+#define UART_UARTLCR_H_OFFSET _u(0x0000002c)
+#define UART_UARTLCR_H_BITS   _u(0x000000ff)
+#define UART_UARTLCR_H_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTLCR_H_SPS
+// Description : Stick parity select. 0 = stick parity is disabled 1 = either: *
+//               if the EPS bit is 0 then the parity bit is transmitted and
+//               checked as a 1 * if the EPS bit is 1 then the parity bit is
+//               transmitted and checked as a 0. This bit has no effect when the
+//               PEN bit disables parity checking and generation.
+#define UART_UARTLCR_H_SPS_RESET  _u(0x0)
+#define UART_UARTLCR_H_SPS_BITS   _u(0x00000080)
+#define UART_UARTLCR_H_SPS_MSB    _u(7)
+#define UART_UARTLCR_H_SPS_LSB    _u(7)
+#define UART_UARTLCR_H_SPS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTLCR_H_WLEN
+// Description : Word length. These bits indicate the number of data bits
+//               transmitted or received in a frame as follows: b11 = 8 bits b10
+//               = 7 bits b01 = 6 bits b00 = 5 bits.
+#define UART_UARTLCR_H_WLEN_RESET  _u(0x0)
+#define UART_UARTLCR_H_WLEN_BITS   _u(0x00000060)
+#define UART_UARTLCR_H_WLEN_MSB    _u(6)
+#define UART_UARTLCR_H_WLEN_LSB    _u(5)
+#define UART_UARTLCR_H_WLEN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTLCR_H_FEN
+// Description : Enable FIFOs: 0 = FIFOs are disabled (character mode) that is,
+//               the FIFOs become 1-byte-deep holding registers 1 = transmit and
+//               receive FIFO buffers are enabled (FIFO mode).
+#define UART_UARTLCR_H_FEN_RESET  _u(0x0)
+#define UART_UARTLCR_H_FEN_BITS   _u(0x00000010)
+#define UART_UARTLCR_H_FEN_MSB    _u(4)
+#define UART_UARTLCR_H_FEN_LSB    _u(4)
+#define UART_UARTLCR_H_FEN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTLCR_H_STP2
+// Description : Two stop bits select. If this bit is set to 1, two stop bits
+//               are transmitted at the end of the frame. The receive logic does
+//               not check for two stop bits being received.
+#define UART_UARTLCR_H_STP2_RESET  _u(0x0)
+#define UART_UARTLCR_H_STP2_BITS   _u(0x00000008)
+#define UART_UARTLCR_H_STP2_MSB    _u(3)
+#define UART_UARTLCR_H_STP2_LSB    _u(3)
+#define UART_UARTLCR_H_STP2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTLCR_H_EPS
+// Description : Even parity select. Controls the type of parity the UART uses
+//               during transmission and reception: 0 = odd parity. The UART
+//               generates or checks for an odd number of 1s in the data and
+//               parity bits. 1 = even parity. The UART generates or checks for
+//               an even number of 1s in the data and parity bits. This bit has
+//               no effect when the PEN bit disables parity checking and
+//               generation.
+#define UART_UARTLCR_H_EPS_RESET  _u(0x0)
+#define UART_UARTLCR_H_EPS_BITS   _u(0x00000004)
+#define UART_UARTLCR_H_EPS_MSB    _u(2)
+#define UART_UARTLCR_H_EPS_LSB    _u(2)
+#define UART_UARTLCR_H_EPS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTLCR_H_PEN
+// Description : Parity enable: 0 = parity is disabled and no parity bit added
+//               to the data frame 1 = parity checking and generation is
+//               enabled.
+#define UART_UARTLCR_H_PEN_RESET  _u(0x0)
+#define UART_UARTLCR_H_PEN_BITS   _u(0x00000002)
+#define UART_UARTLCR_H_PEN_MSB    _u(1)
+#define UART_UARTLCR_H_PEN_LSB    _u(1)
+#define UART_UARTLCR_H_PEN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTLCR_H_BRK
+// Description : Send break. If this bit is set to 1, a low-level is continually
+//               output on the UARTTXD output, after completing transmission of
+//               the current character. For the proper execution of the break
+//               command, the software must set this bit for at least two
+//               complete frames. For normal use, this bit must be cleared to 0.
+#define UART_UARTLCR_H_BRK_RESET  _u(0x0)
+#define UART_UARTLCR_H_BRK_BITS   _u(0x00000001)
+#define UART_UARTLCR_H_BRK_MSB    _u(0)
+#define UART_UARTLCR_H_BRK_LSB    _u(0)
+#define UART_UARTLCR_H_BRK_ACCESS "RW"
+// =============================================================================
+// Register    : UART_UARTCR
+// Description : Control Register, UARTCR
+#define UART_UARTCR_OFFSET _u(0x00000030)
+#define UART_UARTCR_BITS   _u(0x0000ff87)
+#define UART_UARTCR_RESET  _u(0x00000300)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTCR_CTSEN
+// Description : CTS hardware flow control enable. If this bit is set to 1, CTS
+//               hardware flow control is enabled. Data is only transmitted when
+//               the nUARTCTS signal is asserted.
+#define UART_UARTCR_CTSEN_RESET  _u(0x0)
+#define UART_UARTCR_CTSEN_BITS   _u(0x00008000)
+#define UART_UARTCR_CTSEN_MSB    _u(15)
+#define UART_UARTCR_CTSEN_LSB    _u(15)
+#define UART_UARTCR_CTSEN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTCR_RTSEN
+// Description : RTS hardware flow control enable. If this bit is set to 1, RTS
+//               hardware flow control is enabled. Data is only requested when
+//               there is space in the receive FIFO for it to be received.
+#define UART_UARTCR_RTSEN_RESET  _u(0x0)
+#define UART_UARTCR_RTSEN_BITS   _u(0x00004000)
+#define UART_UARTCR_RTSEN_MSB    _u(14)
+#define UART_UARTCR_RTSEN_LSB    _u(14)
+#define UART_UARTCR_RTSEN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTCR_OUT2
+// Description : This bit is the complement of the UART Out2 (nUARTOut2) modem
+//               status output. That is, when the bit is programmed to a 1, the
+//               output is 0. For DTE this can be used as Ring Indicator (RI).
+#define UART_UARTCR_OUT2_RESET  _u(0x0)
+#define UART_UARTCR_OUT2_BITS   _u(0x00002000)
+#define UART_UARTCR_OUT2_MSB    _u(13)
+#define UART_UARTCR_OUT2_LSB    _u(13)
+#define UART_UARTCR_OUT2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTCR_OUT1
+// Description : This bit is the complement of the UART Out1 (nUARTOut1) modem
+//               status output. That is, when the bit is programmed to a 1 the
+//               output is 0. For DTE this can be used as Data Carrier Detect
+//               (DCD).
+#define UART_UARTCR_OUT1_RESET  _u(0x0)
+#define UART_UARTCR_OUT1_BITS   _u(0x00001000)
+#define UART_UARTCR_OUT1_MSB    _u(12)
+#define UART_UARTCR_OUT1_LSB    _u(12)
+#define UART_UARTCR_OUT1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTCR_RTS
+// Description : Request to send. This bit is the complement of the UART request
+//               to send, nUARTRTS, modem status output. That is, when the bit
+//               is programmed to a 1 then nUARTRTS is LOW.
+#define UART_UARTCR_RTS_RESET  _u(0x0)
+#define UART_UARTCR_RTS_BITS   _u(0x00000800)
+#define UART_UARTCR_RTS_MSB    _u(11)
+#define UART_UARTCR_RTS_LSB    _u(11)
+#define UART_UARTCR_RTS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTCR_DTR
+// Description : Data transmit ready. This bit is the complement of the UART
+//               data transmit ready, nUARTDTR, modem status output. That is,
+//               when the bit is programmed to a 1 then nUARTDTR is LOW.
+#define UART_UARTCR_DTR_RESET  _u(0x0)
+#define UART_UARTCR_DTR_BITS   _u(0x00000400)
+#define UART_UARTCR_DTR_MSB    _u(10)
+#define UART_UARTCR_DTR_LSB    _u(10)
+#define UART_UARTCR_DTR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTCR_RXE
+// Description : Receive enable. If this bit is set to 1, the receive section of
+//               the UART is enabled. Data reception occurs for either UART
+//               signals or SIR signals depending on the setting of the SIREN
+//               bit. When the UART is disabled in the middle of reception, it
+//               completes the current character before stopping.
+#define UART_UARTCR_RXE_RESET  _u(0x1)
+#define UART_UARTCR_RXE_BITS   _u(0x00000200)
+#define UART_UARTCR_RXE_MSB    _u(9)
+#define UART_UARTCR_RXE_LSB    _u(9)
+#define UART_UARTCR_RXE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTCR_TXE
+// Description : Transmit enable. If this bit is set to 1, the transmit section
+//               of the UART is enabled. Data transmission occurs for either
+//               UART signals, or SIR signals depending on the setting of the
+//               SIREN bit. When the UART is disabled in the middle of
+//               transmission, it completes the current character before
+//               stopping.
+#define UART_UARTCR_TXE_RESET  _u(0x1)
+#define UART_UARTCR_TXE_BITS   _u(0x00000100)
+#define UART_UARTCR_TXE_MSB    _u(8)
+#define UART_UARTCR_TXE_LSB    _u(8)
+#define UART_UARTCR_TXE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTCR_LBE
+// Description : Loopback enable. If this bit is set to 1 and the SIREN bit is
+//               set to 1 and the SIRTEST bit in the Test Control Register,
+//               UARTTCR is set to 1, then the nSIROUT path is inverted, and fed
+//               through to the SIRIN path. The SIRTEST bit in the test register
+//               must be set to 1 to override the normal half-duplex SIR
+//               operation. This must be the requirement for accessing the test
+//               registers during normal operation, and SIRTEST must be cleared
+//               to 0 when loopback testing is finished. This feature reduces
+//               the amount of external coupling required during system test. If
+//               this bit is set to 1, and the SIRTEST bit is set to 0, the
+//               UARTTXD path is fed through to the UARTRXD path. In either SIR
+//               mode or UART mode, when this bit is set, the modem outputs are
+//               also fed through to the modem inputs. This bit is cleared to 0
+//               on reset, to disable loopback.
+#define UART_UARTCR_LBE_RESET  _u(0x0)
+#define UART_UARTCR_LBE_BITS   _u(0x00000080)
+#define UART_UARTCR_LBE_MSB    _u(7)
+#define UART_UARTCR_LBE_LSB    _u(7)
+#define UART_UARTCR_LBE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTCR_SIRLP
+// Description : SIR low-power IrDA mode. This bit selects the IrDA encoding
+//               mode. If this bit is cleared to 0, low-level bits are
+//               transmitted as an active high pulse with a width of 3 / 16th of
+//               the bit period. If this bit is set to 1, low-level bits are
+//               transmitted with a pulse width that is 3 times the period of
+//               the IrLPBaud16 input signal, regardless of the selected bit
+//               rate. Setting this bit uses less power, but might reduce
+//               transmission distances.
+#define UART_UARTCR_SIRLP_RESET  _u(0x0)
+#define UART_UARTCR_SIRLP_BITS   _u(0x00000004)
+#define UART_UARTCR_SIRLP_MSB    _u(2)
+#define UART_UARTCR_SIRLP_LSB    _u(2)
+#define UART_UARTCR_SIRLP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTCR_SIREN
+// Description : SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW
+//               (no light pulse generated), and signal transitions on SIRIN
+//               have no effect. 1 = IrDA SIR ENDEC is enabled. Data is
+//               transmitted and received on nSIROUT and SIRIN. UARTTXD remains
+//               HIGH, in the marking state. Signal transitions on UARTRXD or
+//               modem status inputs have no effect. This bit has no effect if
+//               the UARTEN bit disables the UART.
+#define UART_UARTCR_SIREN_RESET  _u(0x0)
+#define UART_UARTCR_SIREN_BITS   _u(0x00000002)
+#define UART_UARTCR_SIREN_MSB    _u(1)
+#define UART_UARTCR_SIREN_LSB    _u(1)
+#define UART_UARTCR_SIREN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTCR_UARTEN
+// Description : UART enable: 0 = UART is disabled. If the UART is disabled in
+//               the middle of transmission or reception, it completes the
+//               current character before stopping. 1 = the UART is enabled.
+//               Data transmission and reception occurs for either UART signals
+//               or SIR signals depending on the setting of the SIREN bit.
+#define UART_UARTCR_UARTEN_RESET  _u(0x0)
+#define UART_UARTCR_UARTEN_BITS   _u(0x00000001)
+#define UART_UARTCR_UARTEN_MSB    _u(0)
+#define UART_UARTCR_UARTEN_LSB    _u(0)
+#define UART_UARTCR_UARTEN_ACCESS "RW"
+// =============================================================================
+// Register    : UART_UARTIFLS
+// Description : Interrupt FIFO Level Select Register, UARTIFLS
+#define UART_UARTIFLS_OFFSET _u(0x00000034)
+#define UART_UARTIFLS_BITS   _u(0x0000003f)
+#define UART_UARTIFLS_RESET  _u(0x00000012)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTIFLS_RXIFLSEL
+// Description : Receive interrupt FIFO level select. The trigger points for the
+//               receive interrupt are as follows: b000 = Receive FIFO becomes
+//               >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 =
+//               Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes
+//               >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full
+//               b101-b111 = reserved.
+#define UART_UARTIFLS_RXIFLSEL_RESET  _u(0x2)
+#define UART_UARTIFLS_RXIFLSEL_BITS   _u(0x00000038)
+#define UART_UARTIFLS_RXIFLSEL_MSB    _u(5)
+#define UART_UARTIFLS_RXIFLSEL_LSB    _u(3)
+#define UART_UARTIFLS_RXIFLSEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTIFLS_TXIFLSEL
+// Description : Transmit interrupt FIFO level select. The trigger points for
+//               the transmit interrupt are as follows: b000 = Transmit FIFO
+//               becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4
+//               full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit
+//               FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 /
+//               8 full b101-b111 = reserved.
+#define UART_UARTIFLS_TXIFLSEL_RESET  _u(0x2)
+#define UART_UARTIFLS_TXIFLSEL_BITS   _u(0x00000007)
+#define UART_UARTIFLS_TXIFLSEL_MSB    _u(2)
+#define UART_UARTIFLS_TXIFLSEL_LSB    _u(0)
+#define UART_UARTIFLS_TXIFLSEL_ACCESS "RW"
+// =============================================================================
+// Register    : UART_UARTIMSC
+// Description : Interrupt Mask Set/Clear Register, UARTIMSC
+#define UART_UARTIMSC_OFFSET _u(0x00000038)
+#define UART_UARTIMSC_BITS   _u(0x000007ff)
+#define UART_UARTIMSC_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTIMSC_OEIM
+// Description : Overrun error interrupt mask. A read returns the current mask
+//               for the UARTOEINTR interrupt. On a write of 1, the mask of the
+//               UARTOEINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_OEIM_RESET  _u(0x0)
+#define UART_UARTIMSC_OEIM_BITS   _u(0x00000400)
+#define UART_UARTIMSC_OEIM_MSB    _u(10)
+#define UART_UARTIMSC_OEIM_LSB    _u(10)
+#define UART_UARTIMSC_OEIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTIMSC_BEIM
+// Description : Break error interrupt mask. A read returns the current mask for
+//               the UARTBEINTR interrupt. On a write of 1, the mask of the
+//               UARTBEINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_BEIM_RESET  _u(0x0)
+#define UART_UARTIMSC_BEIM_BITS   _u(0x00000200)
+#define UART_UARTIMSC_BEIM_MSB    _u(9)
+#define UART_UARTIMSC_BEIM_LSB    _u(9)
+#define UART_UARTIMSC_BEIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTIMSC_PEIM
+// Description : Parity error interrupt mask. A read returns the current mask
+//               for the UARTPEINTR interrupt. On a write of 1, the mask of the
+//               UARTPEINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_PEIM_RESET  _u(0x0)
+#define UART_UARTIMSC_PEIM_BITS   _u(0x00000100)
+#define UART_UARTIMSC_PEIM_MSB    _u(8)
+#define UART_UARTIMSC_PEIM_LSB    _u(8)
+#define UART_UARTIMSC_PEIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTIMSC_FEIM
+// Description : Framing error interrupt mask. A read returns the current mask
+//               for the UARTFEINTR interrupt. On a write of 1, the mask of the
+//               UARTFEINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_FEIM_RESET  _u(0x0)
+#define UART_UARTIMSC_FEIM_BITS   _u(0x00000080)
+#define UART_UARTIMSC_FEIM_MSB    _u(7)
+#define UART_UARTIMSC_FEIM_LSB    _u(7)
+#define UART_UARTIMSC_FEIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTIMSC_RTIM
+// Description : Receive timeout interrupt mask. A read returns the current mask
+//               for the UARTRTINTR interrupt. On a write of 1, the mask of the
+//               UARTRTINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_RTIM_RESET  _u(0x0)
+#define UART_UARTIMSC_RTIM_BITS   _u(0x00000040)
+#define UART_UARTIMSC_RTIM_MSB    _u(6)
+#define UART_UARTIMSC_RTIM_LSB    _u(6)
+#define UART_UARTIMSC_RTIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTIMSC_TXIM
+// Description : Transmit interrupt mask. A read returns the current mask for
+//               the UARTTXINTR interrupt. On a write of 1, the mask of the
+//               UARTTXINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_TXIM_RESET  _u(0x0)
+#define UART_UARTIMSC_TXIM_BITS   _u(0x00000020)
+#define UART_UARTIMSC_TXIM_MSB    _u(5)
+#define UART_UARTIMSC_TXIM_LSB    _u(5)
+#define UART_UARTIMSC_TXIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTIMSC_RXIM
+// Description : Receive interrupt mask. A read returns the current mask for the
+//               UARTRXINTR interrupt. On a write of 1, the mask of the
+//               UARTRXINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_RXIM_RESET  _u(0x0)
+#define UART_UARTIMSC_RXIM_BITS   _u(0x00000010)
+#define UART_UARTIMSC_RXIM_MSB    _u(4)
+#define UART_UARTIMSC_RXIM_LSB    _u(4)
+#define UART_UARTIMSC_RXIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTIMSC_DSRMIM
+// Description : nUARTDSR modem interrupt mask. A read returns the current mask
+//               for the UARTDSRINTR interrupt. On a write of 1, the mask of the
+//               UARTDSRINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_DSRMIM_RESET  _u(0x0)
+#define UART_UARTIMSC_DSRMIM_BITS   _u(0x00000008)
+#define UART_UARTIMSC_DSRMIM_MSB    _u(3)
+#define UART_UARTIMSC_DSRMIM_LSB    _u(3)
+#define UART_UARTIMSC_DSRMIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTIMSC_DCDMIM
+// Description : nUARTDCD modem interrupt mask. A read returns the current mask
+//               for the UARTDCDINTR interrupt. On a write of 1, the mask of the
+//               UARTDCDINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_DCDMIM_RESET  _u(0x0)
+#define UART_UARTIMSC_DCDMIM_BITS   _u(0x00000004)
+#define UART_UARTIMSC_DCDMIM_MSB    _u(2)
+#define UART_UARTIMSC_DCDMIM_LSB    _u(2)
+#define UART_UARTIMSC_DCDMIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTIMSC_CTSMIM
+// Description : nUARTCTS modem interrupt mask. A read returns the current mask
+//               for the UARTCTSINTR interrupt. On a write of 1, the mask of the
+//               UARTCTSINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_CTSMIM_RESET  _u(0x0)
+#define UART_UARTIMSC_CTSMIM_BITS   _u(0x00000002)
+#define UART_UARTIMSC_CTSMIM_MSB    _u(1)
+#define UART_UARTIMSC_CTSMIM_LSB    _u(1)
+#define UART_UARTIMSC_CTSMIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTIMSC_RIMIM
+// Description : nUARTRI modem interrupt mask. A read returns the current mask
+//               for the UARTRIINTR interrupt. On a write of 1, the mask of the
+//               UARTRIINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_RIMIM_RESET  _u(0x0)
+#define UART_UARTIMSC_RIMIM_BITS   _u(0x00000001)
+#define UART_UARTIMSC_RIMIM_MSB    _u(0)
+#define UART_UARTIMSC_RIMIM_LSB    _u(0)
+#define UART_UARTIMSC_RIMIM_ACCESS "RW"
+// =============================================================================
+// Register    : UART_UARTRIS
+// Description : Raw Interrupt Status Register, UARTRIS
+#define UART_UARTRIS_OFFSET _u(0x0000003c)
+#define UART_UARTRIS_BITS   _u(0x000007ff)
+#define UART_UARTRIS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRIS_OERIS
+// Description : Overrun error interrupt status. Returns the raw interrupt state
+//               of the UARTOEINTR interrupt.
+#define UART_UARTRIS_OERIS_RESET  _u(0x0)
+#define UART_UARTRIS_OERIS_BITS   _u(0x00000400)
+#define UART_UARTRIS_OERIS_MSB    _u(10)
+#define UART_UARTRIS_OERIS_LSB    _u(10)
+#define UART_UARTRIS_OERIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRIS_BERIS
+// Description : Break error interrupt status. Returns the raw interrupt state
+//               of the UARTBEINTR interrupt.
+#define UART_UARTRIS_BERIS_RESET  _u(0x0)
+#define UART_UARTRIS_BERIS_BITS   _u(0x00000200)
+#define UART_UARTRIS_BERIS_MSB    _u(9)
+#define UART_UARTRIS_BERIS_LSB    _u(9)
+#define UART_UARTRIS_BERIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRIS_PERIS
+// Description : Parity error interrupt status. Returns the raw interrupt state
+//               of the UARTPEINTR interrupt.
+#define UART_UARTRIS_PERIS_RESET  _u(0x0)
+#define UART_UARTRIS_PERIS_BITS   _u(0x00000100)
+#define UART_UARTRIS_PERIS_MSB    _u(8)
+#define UART_UARTRIS_PERIS_LSB    _u(8)
+#define UART_UARTRIS_PERIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRIS_FERIS
+// Description : Framing error interrupt status. Returns the raw interrupt state
+//               of the UARTFEINTR interrupt.
+#define UART_UARTRIS_FERIS_RESET  _u(0x0)
+#define UART_UARTRIS_FERIS_BITS   _u(0x00000080)
+#define UART_UARTRIS_FERIS_MSB    _u(7)
+#define UART_UARTRIS_FERIS_LSB    _u(7)
+#define UART_UARTRIS_FERIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRIS_RTRIS
+// Description : Receive timeout interrupt status. Returns the raw interrupt
+//               state of the UARTRTINTR interrupt. a
+#define UART_UARTRIS_RTRIS_RESET  _u(0x0)
+#define UART_UARTRIS_RTRIS_BITS   _u(0x00000040)
+#define UART_UARTRIS_RTRIS_MSB    _u(6)
+#define UART_UARTRIS_RTRIS_LSB    _u(6)
+#define UART_UARTRIS_RTRIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRIS_TXRIS
+// Description : Transmit interrupt status. Returns the raw interrupt state of
+//               the UARTTXINTR interrupt.
+#define UART_UARTRIS_TXRIS_RESET  _u(0x0)
+#define UART_UARTRIS_TXRIS_BITS   _u(0x00000020)
+#define UART_UARTRIS_TXRIS_MSB    _u(5)
+#define UART_UARTRIS_TXRIS_LSB    _u(5)
+#define UART_UARTRIS_TXRIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRIS_RXRIS
+// Description : Receive interrupt status. Returns the raw interrupt state of
+//               the UARTRXINTR interrupt.
+#define UART_UARTRIS_RXRIS_RESET  _u(0x0)
+#define UART_UARTRIS_RXRIS_BITS   _u(0x00000010)
+#define UART_UARTRIS_RXRIS_MSB    _u(4)
+#define UART_UARTRIS_RXRIS_LSB    _u(4)
+#define UART_UARTRIS_RXRIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRIS_DSRRMIS
+// Description : nUARTDSR modem interrupt status. Returns the raw interrupt
+//               state of the UARTDSRINTR interrupt.
+#define UART_UARTRIS_DSRRMIS_RESET  "-"
+#define UART_UARTRIS_DSRRMIS_BITS   _u(0x00000008)
+#define UART_UARTRIS_DSRRMIS_MSB    _u(3)
+#define UART_UARTRIS_DSRRMIS_LSB    _u(3)
+#define UART_UARTRIS_DSRRMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRIS_DCDRMIS
+// Description : nUARTDCD modem interrupt status. Returns the raw interrupt
+//               state of the UARTDCDINTR interrupt.
+#define UART_UARTRIS_DCDRMIS_RESET  "-"
+#define UART_UARTRIS_DCDRMIS_BITS   _u(0x00000004)
+#define UART_UARTRIS_DCDRMIS_MSB    _u(2)
+#define UART_UARTRIS_DCDRMIS_LSB    _u(2)
+#define UART_UARTRIS_DCDRMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRIS_CTSRMIS
+// Description : nUARTCTS modem interrupt status. Returns the raw interrupt
+//               state of the UARTCTSINTR interrupt.
+#define UART_UARTRIS_CTSRMIS_RESET  "-"
+#define UART_UARTRIS_CTSRMIS_BITS   _u(0x00000002)
+#define UART_UARTRIS_CTSRMIS_MSB    _u(1)
+#define UART_UARTRIS_CTSRMIS_LSB    _u(1)
+#define UART_UARTRIS_CTSRMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTRIS_RIRMIS
+// Description : nUARTRI modem interrupt status. Returns the raw interrupt state
+//               of the UARTRIINTR interrupt.
+#define UART_UARTRIS_RIRMIS_RESET  "-"
+#define UART_UARTRIS_RIRMIS_BITS   _u(0x00000001)
+#define UART_UARTRIS_RIRMIS_MSB    _u(0)
+#define UART_UARTRIS_RIRMIS_LSB    _u(0)
+#define UART_UARTRIS_RIRMIS_ACCESS "RO"
+// =============================================================================
+// Register    : UART_UARTMIS
+// Description : Masked Interrupt Status Register, UARTMIS
+#define UART_UARTMIS_OFFSET _u(0x00000040)
+#define UART_UARTMIS_BITS   _u(0x000007ff)
+#define UART_UARTMIS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTMIS_OEMIS
+// Description : Overrun error masked interrupt status. Returns the masked
+//               interrupt state of the UARTOEINTR interrupt.
+#define UART_UARTMIS_OEMIS_RESET  _u(0x0)
+#define UART_UARTMIS_OEMIS_BITS   _u(0x00000400)
+#define UART_UARTMIS_OEMIS_MSB    _u(10)
+#define UART_UARTMIS_OEMIS_LSB    _u(10)
+#define UART_UARTMIS_OEMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTMIS_BEMIS
+// Description : Break error masked interrupt status. Returns the masked
+//               interrupt state of the UARTBEINTR interrupt.
+#define UART_UARTMIS_BEMIS_RESET  _u(0x0)
+#define UART_UARTMIS_BEMIS_BITS   _u(0x00000200)
+#define UART_UARTMIS_BEMIS_MSB    _u(9)
+#define UART_UARTMIS_BEMIS_LSB    _u(9)
+#define UART_UARTMIS_BEMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTMIS_PEMIS
+// Description : Parity error masked interrupt status. Returns the masked
+//               interrupt state of the UARTPEINTR interrupt.
+#define UART_UARTMIS_PEMIS_RESET  _u(0x0)
+#define UART_UARTMIS_PEMIS_BITS   _u(0x00000100)
+#define UART_UARTMIS_PEMIS_MSB    _u(8)
+#define UART_UARTMIS_PEMIS_LSB    _u(8)
+#define UART_UARTMIS_PEMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTMIS_FEMIS
+// Description : Framing error masked interrupt status. Returns the masked
+//               interrupt state of the UARTFEINTR interrupt.
+#define UART_UARTMIS_FEMIS_RESET  _u(0x0)
+#define UART_UARTMIS_FEMIS_BITS   _u(0x00000080)
+#define UART_UARTMIS_FEMIS_MSB    _u(7)
+#define UART_UARTMIS_FEMIS_LSB    _u(7)
+#define UART_UARTMIS_FEMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTMIS_RTMIS
+// Description : Receive timeout masked interrupt status. Returns the masked
+//               interrupt state of the UARTRTINTR interrupt.
+#define UART_UARTMIS_RTMIS_RESET  _u(0x0)
+#define UART_UARTMIS_RTMIS_BITS   _u(0x00000040)
+#define UART_UARTMIS_RTMIS_MSB    _u(6)
+#define UART_UARTMIS_RTMIS_LSB    _u(6)
+#define UART_UARTMIS_RTMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTMIS_TXMIS
+// Description : Transmit masked interrupt status. Returns the masked interrupt
+//               state of the UARTTXINTR interrupt.
+#define UART_UARTMIS_TXMIS_RESET  _u(0x0)
+#define UART_UARTMIS_TXMIS_BITS   _u(0x00000020)
+#define UART_UARTMIS_TXMIS_MSB    _u(5)
+#define UART_UARTMIS_TXMIS_LSB    _u(5)
+#define UART_UARTMIS_TXMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTMIS_RXMIS
+// Description : Receive masked interrupt status. Returns the masked interrupt
+//               state of the UARTRXINTR interrupt.
+#define UART_UARTMIS_RXMIS_RESET  _u(0x0)
+#define UART_UARTMIS_RXMIS_BITS   _u(0x00000010)
+#define UART_UARTMIS_RXMIS_MSB    _u(4)
+#define UART_UARTMIS_RXMIS_LSB    _u(4)
+#define UART_UARTMIS_RXMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTMIS_DSRMMIS
+// Description : nUARTDSR modem masked interrupt status. Returns the masked
+//               interrupt state of the UARTDSRINTR interrupt.
+#define UART_UARTMIS_DSRMMIS_RESET  "-"
+#define UART_UARTMIS_DSRMMIS_BITS   _u(0x00000008)
+#define UART_UARTMIS_DSRMMIS_MSB    _u(3)
+#define UART_UARTMIS_DSRMMIS_LSB    _u(3)
+#define UART_UARTMIS_DSRMMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTMIS_DCDMMIS
+// Description : nUARTDCD modem masked interrupt status. Returns the masked
+//               interrupt state of the UARTDCDINTR interrupt.
+#define UART_UARTMIS_DCDMMIS_RESET  "-"
+#define UART_UARTMIS_DCDMMIS_BITS   _u(0x00000004)
+#define UART_UARTMIS_DCDMMIS_MSB    _u(2)
+#define UART_UARTMIS_DCDMMIS_LSB    _u(2)
+#define UART_UARTMIS_DCDMMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTMIS_CTSMMIS
+// Description : nUARTCTS modem masked interrupt status. Returns the masked
+//               interrupt state of the UARTCTSINTR interrupt.
+#define UART_UARTMIS_CTSMMIS_RESET  "-"
+#define UART_UARTMIS_CTSMMIS_BITS   _u(0x00000002)
+#define UART_UARTMIS_CTSMMIS_MSB    _u(1)
+#define UART_UARTMIS_CTSMMIS_LSB    _u(1)
+#define UART_UARTMIS_CTSMMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTMIS_RIMMIS
+// Description : nUARTRI modem masked interrupt status. Returns the masked
+//               interrupt state of the UARTRIINTR interrupt.
+#define UART_UARTMIS_RIMMIS_RESET  "-"
+#define UART_UARTMIS_RIMMIS_BITS   _u(0x00000001)
+#define UART_UARTMIS_RIMMIS_MSB    _u(0)
+#define UART_UARTMIS_RIMMIS_LSB    _u(0)
+#define UART_UARTMIS_RIMMIS_ACCESS "RO"
+// =============================================================================
+// Register    : UART_UARTICR
+// Description : Interrupt Clear Register, UARTICR
+#define UART_UARTICR_OFFSET _u(0x00000044)
+#define UART_UARTICR_BITS   _u(0x000007ff)
+#define UART_UARTICR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTICR_OEIC
+// Description : Overrun error interrupt clear. Clears the UARTOEINTR interrupt.
+#define UART_UARTICR_OEIC_RESET  "-"
+#define UART_UARTICR_OEIC_BITS   _u(0x00000400)
+#define UART_UARTICR_OEIC_MSB    _u(10)
+#define UART_UARTICR_OEIC_LSB    _u(10)
+#define UART_UARTICR_OEIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTICR_BEIC
+// Description : Break error interrupt clear. Clears the UARTBEINTR interrupt.
+#define UART_UARTICR_BEIC_RESET  "-"
+#define UART_UARTICR_BEIC_BITS   _u(0x00000200)
+#define UART_UARTICR_BEIC_MSB    _u(9)
+#define UART_UARTICR_BEIC_LSB    _u(9)
+#define UART_UARTICR_BEIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTICR_PEIC
+// Description : Parity error interrupt clear. Clears the UARTPEINTR interrupt.
+#define UART_UARTICR_PEIC_RESET  "-"
+#define UART_UARTICR_PEIC_BITS   _u(0x00000100)
+#define UART_UARTICR_PEIC_MSB    _u(8)
+#define UART_UARTICR_PEIC_LSB    _u(8)
+#define UART_UARTICR_PEIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTICR_FEIC
+// Description : Framing error interrupt clear. Clears the UARTFEINTR interrupt.
+#define UART_UARTICR_FEIC_RESET  "-"
+#define UART_UARTICR_FEIC_BITS   _u(0x00000080)
+#define UART_UARTICR_FEIC_MSB    _u(7)
+#define UART_UARTICR_FEIC_LSB    _u(7)
+#define UART_UARTICR_FEIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTICR_RTIC
+// Description : Receive timeout interrupt clear. Clears the UARTRTINTR
+//               interrupt.
+#define UART_UARTICR_RTIC_RESET  "-"
+#define UART_UARTICR_RTIC_BITS   _u(0x00000040)
+#define UART_UARTICR_RTIC_MSB    _u(6)
+#define UART_UARTICR_RTIC_LSB    _u(6)
+#define UART_UARTICR_RTIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTICR_TXIC
+// Description : Transmit interrupt clear. Clears the UARTTXINTR interrupt.
+#define UART_UARTICR_TXIC_RESET  "-"
+#define UART_UARTICR_TXIC_BITS   _u(0x00000020)
+#define UART_UARTICR_TXIC_MSB    _u(5)
+#define UART_UARTICR_TXIC_LSB    _u(5)
+#define UART_UARTICR_TXIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTICR_RXIC
+// Description : Receive interrupt clear. Clears the UARTRXINTR interrupt.
+#define UART_UARTICR_RXIC_RESET  "-"
+#define UART_UARTICR_RXIC_BITS   _u(0x00000010)
+#define UART_UARTICR_RXIC_MSB    _u(4)
+#define UART_UARTICR_RXIC_LSB    _u(4)
+#define UART_UARTICR_RXIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTICR_DSRMIC
+// Description : nUARTDSR modem interrupt clear. Clears the UARTDSRINTR
+//               interrupt.
+#define UART_UARTICR_DSRMIC_RESET  "-"
+#define UART_UARTICR_DSRMIC_BITS   _u(0x00000008)
+#define UART_UARTICR_DSRMIC_MSB    _u(3)
+#define UART_UARTICR_DSRMIC_LSB    _u(3)
+#define UART_UARTICR_DSRMIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTICR_DCDMIC
+// Description : nUARTDCD modem interrupt clear. Clears the UARTDCDINTR
+//               interrupt.
+#define UART_UARTICR_DCDMIC_RESET  "-"
+#define UART_UARTICR_DCDMIC_BITS   _u(0x00000004)
+#define UART_UARTICR_DCDMIC_MSB    _u(2)
+#define UART_UARTICR_DCDMIC_LSB    _u(2)
+#define UART_UARTICR_DCDMIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTICR_CTSMIC
+// Description : nUARTCTS modem interrupt clear. Clears the UARTCTSINTR
+//               interrupt.
+#define UART_UARTICR_CTSMIC_RESET  "-"
+#define UART_UARTICR_CTSMIC_BITS   _u(0x00000002)
+#define UART_UARTICR_CTSMIC_MSB    _u(1)
+#define UART_UARTICR_CTSMIC_LSB    _u(1)
+#define UART_UARTICR_CTSMIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTICR_RIMIC
+// Description : nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.
+#define UART_UARTICR_RIMIC_RESET  "-"
+#define UART_UARTICR_RIMIC_BITS   _u(0x00000001)
+#define UART_UARTICR_RIMIC_MSB    _u(0)
+#define UART_UARTICR_RIMIC_LSB    _u(0)
+#define UART_UARTICR_RIMIC_ACCESS "WC"
+// =============================================================================
+// Register    : UART_UARTDMACR
+// Description : DMA Control Register, UARTDMACR
+#define UART_UARTDMACR_OFFSET _u(0x00000048)
+#define UART_UARTDMACR_BITS   _u(0x00000007)
+#define UART_UARTDMACR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTDMACR_DMAONERR
+// Description : DMA on error. If this bit is set to 1, the DMA receive request
+//               outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the
+//               UART error interrupt is asserted.
+#define UART_UARTDMACR_DMAONERR_RESET  _u(0x0)
+#define UART_UARTDMACR_DMAONERR_BITS   _u(0x00000004)
+#define UART_UARTDMACR_DMAONERR_MSB    _u(2)
+#define UART_UARTDMACR_DMAONERR_LSB    _u(2)
+#define UART_UARTDMACR_DMAONERR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTDMACR_TXDMAE
+// Description : Transmit DMA enable. If this bit is set to 1, DMA for the
+//               transmit FIFO is enabled.
+#define UART_UARTDMACR_TXDMAE_RESET  _u(0x0)
+#define UART_UARTDMACR_TXDMAE_BITS   _u(0x00000002)
+#define UART_UARTDMACR_TXDMAE_MSB    _u(1)
+#define UART_UARTDMACR_TXDMAE_LSB    _u(1)
+#define UART_UARTDMACR_TXDMAE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTDMACR_RXDMAE
+// Description : Receive DMA enable. If this bit is set to 1, DMA for the
+//               receive FIFO is enabled.
+#define UART_UARTDMACR_RXDMAE_RESET  _u(0x0)
+#define UART_UARTDMACR_RXDMAE_BITS   _u(0x00000001)
+#define UART_UARTDMACR_RXDMAE_MSB    _u(0)
+#define UART_UARTDMACR_RXDMAE_LSB    _u(0)
+#define UART_UARTDMACR_RXDMAE_ACCESS "RW"
+// =============================================================================
+// Register    : UART_UARTPERIPHID0
+// Description : UARTPeriphID0 Register
+#define UART_UARTPERIPHID0_OFFSET _u(0x00000fe0)
+#define UART_UARTPERIPHID0_BITS   _u(0x000000ff)
+#define UART_UARTPERIPHID0_RESET  _u(0x00000011)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTPERIPHID0_PARTNUMBER0
+// Description : These bits read back as 0x11
+#define UART_UARTPERIPHID0_PARTNUMBER0_RESET  _u(0x11)
+#define UART_UARTPERIPHID0_PARTNUMBER0_BITS   _u(0x000000ff)
+#define UART_UARTPERIPHID0_PARTNUMBER0_MSB    _u(7)
+#define UART_UARTPERIPHID0_PARTNUMBER0_LSB    _u(0)
+#define UART_UARTPERIPHID0_PARTNUMBER0_ACCESS "RO"
+// =============================================================================
+// Register    : UART_UARTPERIPHID1
+// Description : UARTPeriphID1 Register
+#define UART_UARTPERIPHID1_OFFSET _u(0x00000fe4)
+#define UART_UARTPERIPHID1_BITS   _u(0x000000ff)
+#define UART_UARTPERIPHID1_RESET  _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTPERIPHID1_DESIGNER0
+// Description : These bits read back as 0x1
+#define UART_UARTPERIPHID1_DESIGNER0_RESET  _u(0x1)
+#define UART_UARTPERIPHID1_DESIGNER0_BITS   _u(0x000000f0)
+#define UART_UARTPERIPHID1_DESIGNER0_MSB    _u(7)
+#define UART_UARTPERIPHID1_DESIGNER0_LSB    _u(4)
+#define UART_UARTPERIPHID1_DESIGNER0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTPERIPHID1_PARTNUMBER1
+// Description : These bits read back as 0x0
+#define UART_UARTPERIPHID1_PARTNUMBER1_RESET  _u(0x0)
+#define UART_UARTPERIPHID1_PARTNUMBER1_BITS   _u(0x0000000f)
+#define UART_UARTPERIPHID1_PARTNUMBER1_MSB    _u(3)
+#define UART_UARTPERIPHID1_PARTNUMBER1_LSB    _u(0)
+#define UART_UARTPERIPHID1_PARTNUMBER1_ACCESS "RO"
+// =============================================================================
+// Register    : UART_UARTPERIPHID2
+// Description : UARTPeriphID2 Register
+#define UART_UARTPERIPHID2_OFFSET _u(0x00000fe8)
+#define UART_UARTPERIPHID2_BITS   _u(0x000000ff)
+#define UART_UARTPERIPHID2_RESET  _u(0x00000034)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTPERIPHID2_REVISION
+// Description : This field depends on the revision of the UART: r1p0 0x0 r1p1
+//               0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3
+#define UART_UARTPERIPHID2_REVISION_RESET  _u(0x3)
+#define UART_UARTPERIPHID2_REVISION_BITS   _u(0x000000f0)
+#define UART_UARTPERIPHID2_REVISION_MSB    _u(7)
+#define UART_UARTPERIPHID2_REVISION_LSB    _u(4)
+#define UART_UARTPERIPHID2_REVISION_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTPERIPHID2_DESIGNER1
+// Description : These bits read back as 0x4
+#define UART_UARTPERIPHID2_DESIGNER1_RESET  _u(0x4)
+#define UART_UARTPERIPHID2_DESIGNER1_BITS   _u(0x0000000f)
+#define UART_UARTPERIPHID2_DESIGNER1_MSB    _u(3)
+#define UART_UARTPERIPHID2_DESIGNER1_LSB    _u(0)
+#define UART_UARTPERIPHID2_DESIGNER1_ACCESS "RO"
+// =============================================================================
+// Register    : UART_UARTPERIPHID3
+// Description : UARTPeriphID3 Register
+#define UART_UARTPERIPHID3_OFFSET _u(0x00000fec)
+#define UART_UARTPERIPHID3_BITS   _u(0x000000ff)
+#define UART_UARTPERIPHID3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTPERIPHID3_CONFIGURATION
+// Description : These bits read back as 0x00
+#define UART_UARTPERIPHID3_CONFIGURATION_RESET  _u(0x00)
+#define UART_UARTPERIPHID3_CONFIGURATION_BITS   _u(0x000000ff)
+#define UART_UARTPERIPHID3_CONFIGURATION_MSB    _u(7)
+#define UART_UARTPERIPHID3_CONFIGURATION_LSB    _u(0)
+#define UART_UARTPERIPHID3_CONFIGURATION_ACCESS "RO"
+// =============================================================================
+// Register    : UART_UARTPCELLID0
+// Description : UARTPCellID0 Register
+#define UART_UARTPCELLID0_OFFSET _u(0x00000ff0)
+#define UART_UARTPCELLID0_BITS   _u(0x000000ff)
+#define UART_UARTPCELLID0_RESET  _u(0x0000000d)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTPCELLID0_UARTPCELLID0
+// Description : These bits read back as 0x0D
+#define UART_UARTPCELLID0_UARTPCELLID0_RESET  _u(0x0d)
+#define UART_UARTPCELLID0_UARTPCELLID0_BITS   _u(0x000000ff)
+#define UART_UARTPCELLID0_UARTPCELLID0_MSB    _u(7)
+#define UART_UARTPCELLID0_UARTPCELLID0_LSB    _u(0)
+#define UART_UARTPCELLID0_UARTPCELLID0_ACCESS "RO"
+// =============================================================================
+// Register    : UART_UARTPCELLID1
+// Description : UARTPCellID1 Register
+#define UART_UARTPCELLID1_OFFSET _u(0x00000ff4)
+#define UART_UARTPCELLID1_BITS   _u(0x000000ff)
+#define UART_UARTPCELLID1_RESET  _u(0x000000f0)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTPCELLID1_UARTPCELLID1
+// Description : These bits read back as 0xF0
+#define UART_UARTPCELLID1_UARTPCELLID1_RESET  _u(0xf0)
+#define UART_UARTPCELLID1_UARTPCELLID1_BITS   _u(0x000000ff)
+#define UART_UARTPCELLID1_UARTPCELLID1_MSB    _u(7)
+#define UART_UARTPCELLID1_UARTPCELLID1_LSB    _u(0)
+#define UART_UARTPCELLID1_UARTPCELLID1_ACCESS "RO"
+// =============================================================================
+// Register    : UART_UARTPCELLID2
+// Description : UARTPCellID2 Register
+#define UART_UARTPCELLID2_OFFSET _u(0x00000ff8)
+#define UART_UARTPCELLID2_BITS   _u(0x000000ff)
+#define UART_UARTPCELLID2_RESET  _u(0x00000005)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTPCELLID2_UARTPCELLID2
+// Description : These bits read back as 0x05
+#define UART_UARTPCELLID2_UARTPCELLID2_RESET  _u(0x05)
+#define UART_UARTPCELLID2_UARTPCELLID2_BITS   _u(0x000000ff)
+#define UART_UARTPCELLID2_UARTPCELLID2_MSB    _u(7)
+#define UART_UARTPCELLID2_UARTPCELLID2_LSB    _u(0)
+#define UART_UARTPCELLID2_UARTPCELLID2_ACCESS "RO"
+// =============================================================================
+// Register    : UART_UARTPCELLID3
+// Description : UARTPCellID3 Register
+#define UART_UARTPCELLID3_OFFSET _u(0x00000ffc)
+#define UART_UARTPCELLID3_BITS   _u(0x000000ff)
+#define UART_UARTPCELLID3_RESET  _u(0x000000b1)
+// -----------------------------------------------------------------------------
+// Field       : UART_UARTPCELLID3_UARTPCELLID3
+// Description : These bits read back as 0xB1
+#define UART_UARTPCELLID3_UARTPCELLID3_RESET  _u(0xb1)
+#define UART_UARTPCELLID3_UARTPCELLID3_BITS   _u(0x000000ff)
+#define UART_UARTPCELLID3_UARTPCELLID3_MSB    _u(7)
+#define UART_UARTPCELLID3_UARTPCELLID3_LSB    _u(0)
+#define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_UART_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/usb.h b/src/rp2040/hardware_regs/include/hardware/regs/usb.h
new file mode 100644
index 0000000..552cd11
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/usb.h
@@ -0,0 +1,3603 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : USB
+// Version        : 1
+// Bus type       : ahbl
+// Description    : USB FS/LS controller device registers
+// =============================================================================
+#ifndef HARDWARE_REGS_USB_DEFINED
+#define HARDWARE_REGS_USB_DEFINED
+// =============================================================================
+// Register    : USB_ADDR_ENDP
+// Description : Device address and endpoint control
+#define USB_ADDR_ENDP_OFFSET _u(0x00000000)
+#define USB_ADDR_ENDP_BITS   _u(0x000f007f)
+#define USB_ADDR_ENDP_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP_ENDPOINT
+// Description : Device endpoint to send data to. Only valid for HOST mode.
+#define USB_ADDR_ENDP_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP_ADDRESS
+// Description : In device mode, the address that the device should respond to.
+//               Set in response to a SET_ADDR setup packet from the host. In
+//               host mode set to the address of the device to communicate with.
+#define USB_ADDR_ENDP_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP1
+// Description : Interrupt endpoint 1. Only valid for HOST mode.
+#define USB_ADDR_ENDP1_OFFSET _u(0x00000004)
+#define USB_ADDR_ENDP1_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP1_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP1_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP1_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP1_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP1_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP1_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP1_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP1_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP1_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP1_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP1_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP1_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP1_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP1_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP1_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP1_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP1_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP1_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP1_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP1_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP2
+// Description : Interrupt endpoint 2. Only valid for HOST mode.
+#define USB_ADDR_ENDP2_OFFSET _u(0x00000008)
+#define USB_ADDR_ENDP2_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP2_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP2_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP2_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP2_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP2_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP2_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP2_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP2_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP2_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP2_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP2_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP2_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP2_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP2_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP2_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP2_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP2_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP2_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP2_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP2_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP3
+// Description : Interrupt endpoint 3. Only valid for HOST mode.
+#define USB_ADDR_ENDP3_OFFSET _u(0x0000000c)
+#define USB_ADDR_ENDP3_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP3_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP3_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP3_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP3_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP3_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP3_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP3_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP3_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP3_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP3_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP3_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP3_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP3_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP3_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP3_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP3_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP3_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP3_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP3_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP3_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP4
+// Description : Interrupt endpoint 4. Only valid for HOST mode.
+#define USB_ADDR_ENDP4_OFFSET _u(0x00000010)
+#define USB_ADDR_ENDP4_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP4_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP4_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP4_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP4_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP4_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP4_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP4_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP4_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP4_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP4_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP4_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP4_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP4_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP4_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP4_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP4_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP4_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP4_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP4_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP4_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP4_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP5
+// Description : Interrupt endpoint 5. Only valid for HOST mode.
+#define USB_ADDR_ENDP5_OFFSET _u(0x00000014)
+#define USB_ADDR_ENDP5_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP5_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP5_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP5_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP5_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP5_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP5_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP5_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP5_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP5_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP5_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP5_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP5_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP5_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP5_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP5_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP5_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP5_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP5_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP5_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP5_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP5_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP6
+// Description : Interrupt endpoint 6. Only valid for HOST mode.
+#define USB_ADDR_ENDP6_OFFSET _u(0x00000018)
+#define USB_ADDR_ENDP6_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP6_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP6_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP6_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP6_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP6_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP6_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP6_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP6_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP6_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP6_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP6_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP6_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP6_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP6_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP6_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP6_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP6_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP6_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP6_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP6_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP6_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP7
+// Description : Interrupt endpoint 7. Only valid for HOST mode.
+#define USB_ADDR_ENDP7_OFFSET _u(0x0000001c)
+#define USB_ADDR_ENDP7_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP7_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP7_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP7_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP7_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP7_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP7_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP7_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP7_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP7_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP7_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP7_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP7_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP7_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP7_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP7_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP7_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP7_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP7_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP7_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP7_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP7_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP8
+// Description : Interrupt endpoint 8. Only valid for HOST mode.
+#define USB_ADDR_ENDP8_OFFSET _u(0x00000020)
+#define USB_ADDR_ENDP8_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP8_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP8_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP8_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP8_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP8_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP8_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP8_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP8_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP8_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP8_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP8_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP8_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP8_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP8_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP8_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP8_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP8_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP8_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP8_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP8_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP8_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP9
+// Description : Interrupt endpoint 9. Only valid for HOST mode.
+#define USB_ADDR_ENDP9_OFFSET _u(0x00000024)
+#define USB_ADDR_ENDP9_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP9_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP9_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP9_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP9_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP9_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP9_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP9_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP9_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP9_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP9_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP9_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP9_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP9_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP9_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP9_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP9_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP9_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP9_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP9_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP9_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP9_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP10
+// Description : Interrupt endpoint 10. Only valid for HOST mode.
+#define USB_ADDR_ENDP10_OFFSET _u(0x00000028)
+#define USB_ADDR_ENDP10_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP10_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP10_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP10_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP10_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP10_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP10_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP10_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP10_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP10_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP10_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP10_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP10_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP10_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP10_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP10_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP10_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP10_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP10_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP10_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP10_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP10_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP11
+// Description : Interrupt endpoint 11. Only valid for HOST mode.
+#define USB_ADDR_ENDP11_OFFSET _u(0x0000002c)
+#define USB_ADDR_ENDP11_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP11_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP11_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP11_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP11_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP11_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP11_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP11_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP11_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP11_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP11_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP11_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP11_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP11_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP11_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP11_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP11_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP11_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP11_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP11_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP11_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP11_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP12
+// Description : Interrupt endpoint 12. Only valid for HOST mode.
+#define USB_ADDR_ENDP12_OFFSET _u(0x00000030)
+#define USB_ADDR_ENDP12_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP12_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP12_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP12_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP12_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP12_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP12_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP12_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP12_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP12_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP12_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP12_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP12_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP12_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP12_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP12_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP12_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP12_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP12_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP12_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP12_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP12_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP13
+// Description : Interrupt endpoint 13. Only valid for HOST mode.
+#define USB_ADDR_ENDP13_OFFSET _u(0x00000034)
+#define USB_ADDR_ENDP13_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP13_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP13_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP13_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP13_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP13_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP13_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP13_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP13_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP13_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP13_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP13_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP13_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP13_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP13_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP13_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP13_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP13_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP13_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP13_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP13_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP13_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP14
+// Description : Interrupt endpoint 14. Only valid for HOST mode.
+#define USB_ADDR_ENDP14_OFFSET _u(0x00000038)
+#define USB_ADDR_ENDP14_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP14_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP14_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP14_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP14_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP14_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP14_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP14_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP14_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP14_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP14_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP14_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP14_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP14_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP14_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP14_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP14_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP14_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP14_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP14_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP14_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP14_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_ADDR_ENDP15
+// Description : Interrupt endpoint 15. Only valid for HOST mode.
+#define USB_ADDR_ENDP15_OFFSET _u(0x0000003c)
+#define USB_ADDR_ENDP15_BITS   _u(0x060f007f)
+#define USB_ADDR_ENDP15_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP15_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+//               speed hub)
+#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET  _u(0x0)
+#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS   _u(0x04000000)
+#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB    _u(26)
+#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB    _u(26)
+#define USB_ADDR_ENDP15_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP15_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP15_INTEP_DIR_RESET  _u(0x0)
+#define USB_ADDR_ENDP15_INTEP_DIR_BITS   _u(0x02000000)
+#define USB_ADDR_ENDP15_INTEP_DIR_MSB    _u(25)
+#define USB_ADDR_ENDP15_INTEP_DIR_LSB    _u(25)
+#define USB_ADDR_ENDP15_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP15_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP15_ENDPOINT_RESET  _u(0x0)
+#define USB_ADDR_ENDP15_ENDPOINT_BITS   _u(0x000f0000)
+#define USB_ADDR_ENDP15_ENDPOINT_MSB    _u(19)
+#define USB_ADDR_ENDP15_ENDPOINT_LSB    _u(16)
+#define USB_ADDR_ENDP15_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_ADDR_ENDP15_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP15_ADDRESS_RESET  _u(0x00)
+#define USB_ADDR_ENDP15_ADDRESS_BITS   _u(0x0000007f)
+#define USB_ADDR_ENDP15_ADDRESS_MSB    _u(6)
+#define USB_ADDR_ENDP15_ADDRESS_LSB    _u(0)
+#define USB_ADDR_ENDP15_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_MAIN_CTRL
+// Description : Main control register
+#define USB_MAIN_CTRL_OFFSET _u(0x00000040)
+#define USB_MAIN_CTRL_BITS   _u(0x80000003)
+#define USB_MAIN_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_MAIN_CTRL_SIM_TIMING
+// Description : Reduced timings for simulation
+#define USB_MAIN_CTRL_SIM_TIMING_RESET  _u(0x0)
+#define USB_MAIN_CTRL_SIM_TIMING_BITS   _u(0x80000000)
+#define USB_MAIN_CTRL_SIM_TIMING_MSB    _u(31)
+#define USB_MAIN_CTRL_SIM_TIMING_LSB    _u(31)
+#define USB_MAIN_CTRL_SIM_TIMING_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_MAIN_CTRL_HOST_NDEVICE
+// Description : Device mode = 0, Host mode = 1
+#define USB_MAIN_CTRL_HOST_NDEVICE_RESET  _u(0x0)
+#define USB_MAIN_CTRL_HOST_NDEVICE_BITS   _u(0x00000002)
+#define USB_MAIN_CTRL_HOST_NDEVICE_MSB    _u(1)
+#define USB_MAIN_CTRL_HOST_NDEVICE_LSB    _u(1)
+#define USB_MAIN_CTRL_HOST_NDEVICE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_MAIN_CTRL_CONTROLLER_EN
+// Description : Enable controller
+#define USB_MAIN_CTRL_CONTROLLER_EN_RESET  _u(0x0)
+#define USB_MAIN_CTRL_CONTROLLER_EN_BITS   _u(0x00000001)
+#define USB_MAIN_CTRL_CONTROLLER_EN_MSB    _u(0)
+#define USB_MAIN_CTRL_CONTROLLER_EN_LSB    _u(0)
+#define USB_MAIN_CTRL_CONTROLLER_EN_ACCESS "RW"
+// =============================================================================
+// Register    : USB_SOF_WR
+// Description : Set the SOF (Start of Frame) frame number in the host
+//               controller. The SOF packet is sent every 1ms and the host will
+//               increment the frame number by 1 each time.
+#define USB_SOF_WR_OFFSET _u(0x00000044)
+#define USB_SOF_WR_BITS   _u(0x000007ff)
+#define USB_SOF_WR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_SOF_WR_COUNT
+// Description : None
+#define USB_SOF_WR_COUNT_RESET  _u(0x000)
+#define USB_SOF_WR_COUNT_BITS   _u(0x000007ff)
+#define USB_SOF_WR_COUNT_MSB    _u(10)
+#define USB_SOF_WR_COUNT_LSB    _u(0)
+#define USB_SOF_WR_COUNT_ACCESS "WF"
+// =============================================================================
+// Register    : USB_SOF_RD
+// Description : Read the last SOF (Start of Frame) frame number seen. In device
+//               mode the last SOF received from the host. In host mode the last
+//               SOF sent by the host.
+#define USB_SOF_RD_OFFSET _u(0x00000048)
+#define USB_SOF_RD_BITS   _u(0x000007ff)
+#define USB_SOF_RD_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_SOF_RD_COUNT
+// Description : None
+#define USB_SOF_RD_COUNT_RESET  _u(0x000)
+#define USB_SOF_RD_COUNT_BITS   _u(0x000007ff)
+#define USB_SOF_RD_COUNT_MSB    _u(10)
+#define USB_SOF_RD_COUNT_LSB    _u(0)
+#define USB_SOF_RD_COUNT_ACCESS "RO"
+// =============================================================================
+// Register    : USB_SIE_CTRL
+// Description : SIE control register
+#define USB_SIE_CTRL_OFFSET _u(0x0000004c)
+#define USB_SIE_CTRL_BITS   _u(0xff07bf5f)
+#define USB_SIE_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_EP0_INT_STALL
+// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
+#define USB_SIE_CTRL_EP0_INT_STALL_RESET  _u(0x0)
+#define USB_SIE_CTRL_EP0_INT_STALL_BITS   _u(0x80000000)
+#define USB_SIE_CTRL_EP0_INT_STALL_MSB    _u(31)
+#define USB_SIE_CTRL_EP0_INT_STALL_LSB    _u(31)
+#define USB_SIE_CTRL_EP0_INT_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_EP0_DOUBLE_BUF
+// Description : Device: EP0 single buffered = 0, double buffered = 1
+#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET  _u(0x0)
+#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS   _u(0x40000000)
+#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB    _u(30)
+#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB    _u(30)
+#define USB_SIE_CTRL_EP0_DOUBLE_BUF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_EP0_INT_1BUF
+// Description : Device: Set bit in BUFF_STATUS for every buffer completed on
+//               EP0
+#define USB_SIE_CTRL_EP0_INT_1BUF_RESET  _u(0x0)
+#define USB_SIE_CTRL_EP0_INT_1BUF_BITS   _u(0x20000000)
+#define USB_SIE_CTRL_EP0_INT_1BUF_MSB    _u(29)
+#define USB_SIE_CTRL_EP0_INT_1BUF_LSB    _u(29)
+#define USB_SIE_CTRL_EP0_INT_1BUF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_EP0_INT_2BUF
+// Description : Device: Set bit in BUFF_STATUS for every 2 buffers completed on
+//               EP0
+#define USB_SIE_CTRL_EP0_INT_2BUF_RESET  _u(0x0)
+#define USB_SIE_CTRL_EP0_INT_2BUF_BITS   _u(0x10000000)
+#define USB_SIE_CTRL_EP0_INT_2BUF_MSB    _u(28)
+#define USB_SIE_CTRL_EP0_INT_2BUF_LSB    _u(28)
+#define USB_SIE_CTRL_EP0_INT_2BUF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_EP0_INT_NAK
+// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
+#define USB_SIE_CTRL_EP0_INT_NAK_RESET  _u(0x0)
+#define USB_SIE_CTRL_EP0_INT_NAK_BITS   _u(0x08000000)
+#define USB_SIE_CTRL_EP0_INT_NAK_MSB    _u(27)
+#define USB_SIE_CTRL_EP0_INT_NAK_LSB    _u(27)
+#define USB_SIE_CTRL_EP0_INT_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_DIRECT_EN
+// Description : Direct bus drive enable
+#define USB_SIE_CTRL_DIRECT_EN_RESET  _u(0x0)
+#define USB_SIE_CTRL_DIRECT_EN_BITS   _u(0x04000000)
+#define USB_SIE_CTRL_DIRECT_EN_MSB    _u(26)
+#define USB_SIE_CTRL_DIRECT_EN_LSB    _u(26)
+#define USB_SIE_CTRL_DIRECT_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_DIRECT_DP
+// Description : Direct control of DP
+#define USB_SIE_CTRL_DIRECT_DP_RESET  _u(0x0)
+#define USB_SIE_CTRL_DIRECT_DP_BITS   _u(0x02000000)
+#define USB_SIE_CTRL_DIRECT_DP_MSB    _u(25)
+#define USB_SIE_CTRL_DIRECT_DP_LSB    _u(25)
+#define USB_SIE_CTRL_DIRECT_DP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_DIRECT_DM
+// Description : Direct control of DM
+#define USB_SIE_CTRL_DIRECT_DM_RESET  _u(0x0)
+#define USB_SIE_CTRL_DIRECT_DM_BITS   _u(0x01000000)
+#define USB_SIE_CTRL_DIRECT_DM_MSB    _u(24)
+#define USB_SIE_CTRL_DIRECT_DM_LSB    _u(24)
+#define USB_SIE_CTRL_DIRECT_DM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_TRANSCEIVER_PD
+// Description : Power down bus transceiver
+#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET  _u(0x0)
+#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS   _u(0x00040000)
+#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB    _u(18)
+#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB    _u(18)
+#define USB_SIE_CTRL_TRANSCEIVER_PD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_RPU_OPT
+// Description : Device: Pull-up strength (0=1K2, 1=2k3)
+#define USB_SIE_CTRL_RPU_OPT_RESET  _u(0x0)
+#define USB_SIE_CTRL_RPU_OPT_BITS   _u(0x00020000)
+#define USB_SIE_CTRL_RPU_OPT_MSB    _u(17)
+#define USB_SIE_CTRL_RPU_OPT_LSB    _u(17)
+#define USB_SIE_CTRL_RPU_OPT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_PULLUP_EN
+// Description : Device: Enable pull up resistor
+#define USB_SIE_CTRL_PULLUP_EN_RESET  _u(0x0)
+#define USB_SIE_CTRL_PULLUP_EN_BITS   _u(0x00010000)
+#define USB_SIE_CTRL_PULLUP_EN_MSB    _u(16)
+#define USB_SIE_CTRL_PULLUP_EN_LSB    _u(16)
+#define USB_SIE_CTRL_PULLUP_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_PULLDOWN_EN
+// Description : Host: Enable pull down resistors
+#define USB_SIE_CTRL_PULLDOWN_EN_RESET  _u(0x0)
+#define USB_SIE_CTRL_PULLDOWN_EN_BITS   _u(0x00008000)
+#define USB_SIE_CTRL_PULLDOWN_EN_MSB    _u(15)
+#define USB_SIE_CTRL_PULLDOWN_EN_LSB    _u(15)
+#define USB_SIE_CTRL_PULLDOWN_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_RESET_BUS
+// Description : Host: Reset bus
+#define USB_SIE_CTRL_RESET_BUS_RESET  _u(0x0)
+#define USB_SIE_CTRL_RESET_BUS_BITS   _u(0x00002000)
+#define USB_SIE_CTRL_RESET_BUS_MSB    _u(13)
+#define USB_SIE_CTRL_RESET_BUS_LSB    _u(13)
+#define USB_SIE_CTRL_RESET_BUS_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_RESUME
+// Description : Device: Remote wakeup. Device can initiate its own resume after
+//               suspend.
+#define USB_SIE_CTRL_RESUME_RESET  _u(0x0)
+#define USB_SIE_CTRL_RESUME_BITS   _u(0x00001000)
+#define USB_SIE_CTRL_RESUME_MSB    _u(12)
+#define USB_SIE_CTRL_RESUME_LSB    _u(12)
+#define USB_SIE_CTRL_RESUME_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_VBUS_EN
+// Description : Host: Enable VBUS
+#define USB_SIE_CTRL_VBUS_EN_RESET  _u(0x0)
+#define USB_SIE_CTRL_VBUS_EN_BITS   _u(0x00000800)
+#define USB_SIE_CTRL_VBUS_EN_MSB    _u(11)
+#define USB_SIE_CTRL_VBUS_EN_LSB    _u(11)
+#define USB_SIE_CTRL_VBUS_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_KEEP_ALIVE_EN
+// Description : Host: Enable keep alive packet (for low speed bus)
+#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET  _u(0x0)
+#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS   _u(0x00000400)
+#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB    _u(10)
+#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB    _u(10)
+#define USB_SIE_CTRL_KEEP_ALIVE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_SOF_EN
+// Description : Host: Enable SOF generation (for full speed bus)
+#define USB_SIE_CTRL_SOF_EN_RESET  _u(0x0)
+#define USB_SIE_CTRL_SOF_EN_BITS   _u(0x00000200)
+#define USB_SIE_CTRL_SOF_EN_MSB    _u(9)
+#define USB_SIE_CTRL_SOF_EN_LSB    _u(9)
+#define USB_SIE_CTRL_SOF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_SOF_SYNC
+// Description : Host: Delay packet(s) until after SOF
+#define USB_SIE_CTRL_SOF_SYNC_RESET  _u(0x0)
+#define USB_SIE_CTRL_SOF_SYNC_BITS   _u(0x00000100)
+#define USB_SIE_CTRL_SOF_SYNC_MSB    _u(8)
+#define USB_SIE_CTRL_SOF_SYNC_LSB    _u(8)
+#define USB_SIE_CTRL_SOF_SYNC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_PREAMBLE_EN
+// Description : Host: Preable enable for LS device on FS hub
+#define USB_SIE_CTRL_PREAMBLE_EN_RESET  _u(0x0)
+#define USB_SIE_CTRL_PREAMBLE_EN_BITS   _u(0x00000040)
+#define USB_SIE_CTRL_PREAMBLE_EN_MSB    _u(6)
+#define USB_SIE_CTRL_PREAMBLE_EN_LSB    _u(6)
+#define USB_SIE_CTRL_PREAMBLE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_STOP_TRANS
+// Description : Host: Stop transaction
+#define USB_SIE_CTRL_STOP_TRANS_RESET  _u(0x0)
+#define USB_SIE_CTRL_STOP_TRANS_BITS   _u(0x00000010)
+#define USB_SIE_CTRL_STOP_TRANS_MSB    _u(4)
+#define USB_SIE_CTRL_STOP_TRANS_LSB    _u(4)
+#define USB_SIE_CTRL_STOP_TRANS_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_RECEIVE_DATA
+// Description : Host: Receive transaction (IN to host)
+#define USB_SIE_CTRL_RECEIVE_DATA_RESET  _u(0x0)
+#define USB_SIE_CTRL_RECEIVE_DATA_BITS   _u(0x00000008)
+#define USB_SIE_CTRL_RECEIVE_DATA_MSB    _u(3)
+#define USB_SIE_CTRL_RECEIVE_DATA_LSB    _u(3)
+#define USB_SIE_CTRL_RECEIVE_DATA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_SEND_DATA
+// Description : Host: Send transaction (OUT from host)
+#define USB_SIE_CTRL_SEND_DATA_RESET  _u(0x0)
+#define USB_SIE_CTRL_SEND_DATA_BITS   _u(0x00000004)
+#define USB_SIE_CTRL_SEND_DATA_MSB    _u(2)
+#define USB_SIE_CTRL_SEND_DATA_LSB    _u(2)
+#define USB_SIE_CTRL_SEND_DATA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_SEND_SETUP
+// Description : Host: Send Setup packet
+#define USB_SIE_CTRL_SEND_SETUP_RESET  _u(0x0)
+#define USB_SIE_CTRL_SEND_SETUP_BITS   _u(0x00000002)
+#define USB_SIE_CTRL_SEND_SETUP_MSB    _u(1)
+#define USB_SIE_CTRL_SEND_SETUP_LSB    _u(1)
+#define USB_SIE_CTRL_SEND_SETUP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_CTRL_START_TRANS
+// Description : Host: Start transaction
+#define USB_SIE_CTRL_START_TRANS_RESET  _u(0x0)
+#define USB_SIE_CTRL_START_TRANS_BITS   _u(0x00000001)
+#define USB_SIE_CTRL_START_TRANS_MSB    _u(0)
+#define USB_SIE_CTRL_START_TRANS_LSB    _u(0)
+#define USB_SIE_CTRL_START_TRANS_ACCESS "SC"
+// =============================================================================
+// Register    : USB_SIE_STATUS
+// Description : SIE status register
+#define USB_SIE_STATUS_OFFSET _u(0x00000050)
+#define USB_SIE_STATUS_BITS   _u(0xff0f0f1d)
+#define USB_SIE_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_DATA_SEQ_ERROR
+// Description : Data Sequence Error.
+//
+//               The device can raise a sequence error in the following
+//               conditions:
+//
+//               * A SETUP packet is received followed by a DATA1 packet (data
+//               phase should always be DATA0) * An OUT packet is received from
+//               the host but doesn't match the data pid in the buffer control
+//               register read from DPSRAM
+//
+//               The host can raise a data sequence error in the following
+//               conditions:
+//
+//               * An IN packet from the device has the wrong data PID
+#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET  _u(0x0)
+#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS   _u(0x80000000)
+#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB    _u(31)
+#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB    _u(31)
+#define USB_SIE_STATUS_DATA_SEQ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_ACK_REC
+// Description : ACK received. Raised by both host and device.
+#define USB_SIE_STATUS_ACK_REC_RESET  _u(0x0)
+#define USB_SIE_STATUS_ACK_REC_BITS   _u(0x40000000)
+#define USB_SIE_STATUS_ACK_REC_MSB    _u(30)
+#define USB_SIE_STATUS_ACK_REC_LSB    _u(30)
+#define USB_SIE_STATUS_ACK_REC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_STALL_REC
+// Description : Host: STALL received
+#define USB_SIE_STATUS_STALL_REC_RESET  _u(0x0)
+#define USB_SIE_STATUS_STALL_REC_BITS   _u(0x20000000)
+#define USB_SIE_STATUS_STALL_REC_MSB    _u(29)
+#define USB_SIE_STATUS_STALL_REC_LSB    _u(29)
+#define USB_SIE_STATUS_STALL_REC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_NAK_REC
+// Description : Host: NAK received
+#define USB_SIE_STATUS_NAK_REC_RESET  _u(0x0)
+#define USB_SIE_STATUS_NAK_REC_BITS   _u(0x10000000)
+#define USB_SIE_STATUS_NAK_REC_MSB    _u(28)
+#define USB_SIE_STATUS_NAK_REC_LSB    _u(28)
+#define USB_SIE_STATUS_NAK_REC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_RX_TIMEOUT
+// Description : RX timeout is raised by both the host and device if an ACK is
+//               not received in the maximum time specified by the USB spec.
+#define USB_SIE_STATUS_RX_TIMEOUT_RESET  _u(0x0)
+#define USB_SIE_STATUS_RX_TIMEOUT_BITS   _u(0x08000000)
+#define USB_SIE_STATUS_RX_TIMEOUT_MSB    _u(27)
+#define USB_SIE_STATUS_RX_TIMEOUT_LSB    _u(27)
+#define USB_SIE_STATUS_RX_TIMEOUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_RX_OVERFLOW
+// Description : RX overflow is raised by the Serial RX engine if the incoming
+//               data is too fast.
+#define USB_SIE_STATUS_RX_OVERFLOW_RESET  _u(0x0)
+#define USB_SIE_STATUS_RX_OVERFLOW_BITS   _u(0x04000000)
+#define USB_SIE_STATUS_RX_OVERFLOW_MSB    _u(26)
+#define USB_SIE_STATUS_RX_OVERFLOW_LSB    _u(26)
+#define USB_SIE_STATUS_RX_OVERFLOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_BIT_STUFF_ERROR
+// Description : Bit Stuff Error. Raised by the Serial RX engine.
+#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET  _u(0x0)
+#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS   _u(0x02000000)
+#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB    _u(25)
+#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB    _u(25)
+#define USB_SIE_STATUS_BIT_STUFF_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_CRC_ERROR
+// Description : CRC Error. Raised by the Serial RX engine.
+#define USB_SIE_STATUS_CRC_ERROR_RESET  _u(0x0)
+#define USB_SIE_STATUS_CRC_ERROR_BITS   _u(0x01000000)
+#define USB_SIE_STATUS_CRC_ERROR_MSB    _u(24)
+#define USB_SIE_STATUS_CRC_ERROR_LSB    _u(24)
+#define USB_SIE_STATUS_CRC_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_BUS_RESET
+// Description : Device: bus reset received
+#define USB_SIE_STATUS_BUS_RESET_RESET  _u(0x0)
+#define USB_SIE_STATUS_BUS_RESET_BITS   _u(0x00080000)
+#define USB_SIE_STATUS_BUS_RESET_MSB    _u(19)
+#define USB_SIE_STATUS_BUS_RESET_LSB    _u(19)
+#define USB_SIE_STATUS_BUS_RESET_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_TRANS_COMPLETE
+// Description : Transaction complete.
+//
+//               Raised by device if:
+//
+//               * An IN or OUT packet is sent with the `LAST_BUFF` bit set in
+//               the buffer control register
+//
+//               Raised by host if:
+//
+//               * A setup packet is sent when no data in or data out
+//               transaction follows * An IN packet is received and the
+//               `LAST_BUFF` bit is set in the buffer control register * An IN
+//               packet is received with zero length * An OUT packet is sent and
+//               the `LAST_BUFF` bit is set
+#define USB_SIE_STATUS_TRANS_COMPLETE_RESET  _u(0x0)
+#define USB_SIE_STATUS_TRANS_COMPLETE_BITS   _u(0x00040000)
+#define USB_SIE_STATUS_TRANS_COMPLETE_MSB    _u(18)
+#define USB_SIE_STATUS_TRANS_COMPLETE_LSB    _u(18)
+#define USB_SIE_STATUS_TRANS_COMPLETE_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_SETUP_REC
+// Description : Device: Setup packet received
+#define USB_SIE_STATUS_SETUP_REC_RESET  _u(0x0)
+#define USB_SIE_STATUS_SETUP_REC_BITS   _u(0x00020000)
+#define USB_SIE_STATUS_SETUP_REC_MSB    _u(17)
+#define USB_SIE_STATUS_SETUP_REC_LSB    _u(17)
+#define USB_SIE_STATUS_SETUP_REC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_CONNECTED
+// Description : Device: connected
+#define USB_SIE_STATUS_CONNECTED_RESET  _u(0x0)
+#define USB_SIE_STATUS_CONNECTED_BITS   _u(0x00010000)
+#define USB_SIE_STATUS_CONNECTED_MSB    _u(16)
+#define USB_SIE_STATUS_CONNECTED_LSB    _u(16)
+#define USB_SIE_STATUS_CONNECTED_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_RESUME
+// Description : Host: Device has initiated a remote resume. Device: host has
+//               initiated a resume.
+#define USB_SIE_STATUS_RESUME_RESET  _u(0x0)
+#define USB_SIE_STATUS_RESUME_BITS   _u(0x00000800)
+#define USB_SIE_STATUS_RESUME_MSB    _u(11)
+#define USB_SIE_STATUS_RESUME_LSB    _u(11)
+#define USB_SIE_STATUS_RESUME_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_VBUS_OVER_CURR
+// Description : VBUS over current detected
+#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET  _u(0x0)
+#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS   _u(0x00000400)
+#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB    _u(10)
+#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB    _u(10)
+#define USB_SIE_STATUS_VBUS_OVER_CURR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_SPEED
+// Description : Host: device speed. Disconnected = 00, LS = 01, FS = 10
+#define USB_SIE_STATUS_SPEED_RESET  _u(0x0)
+#define USB_SIE_STATUS_SPEED_BITS   _u(0x00000300)
+#define USB_SIE_STATUS_SPEED_MSB    _u(9)
+#define USB_SIE_STATUS_SPEED_LSB    _u(8)
+#define USB_SIE_STATUS_SPEED_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_SUSPENDED
+// Description : Bus in suspended state. Valid for device and host. Host and
+//               device will go into suspend if neither Keep Alive / SOF frames
+//               are enabled.
+#define USB_SIE_STATUS_SUSPENDED_RESET  _u(0x0)
+#define USB_SIE_STATUS_SUSPENDED_BITS   _u(0x00000010)
+#define USB_SIE_STATUS_SUSPENDED_MSB    _u(4)
+#define USB_SIE_STATUS_SUSPENDED_LSB    _u(4)
+#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_LINE_STATE
+// Description : USB bus line state
+#define USB_SIE_STATUS_LINE_STATE_RESET  _u(0x0)
+#define USB_SIE_STATUS_LINE_STATE_BITS   _u(0x0000000c)
+#define USB_SIE_STATUS_LINE_STATE_MSB    _u(3)
+#define USB_SIE_STATUS_LINE_STATE_LSB    _u(2)
+#define USB_SIE_STATUS_LINE_STATE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_SIE_STATUS_VBUS_DETECTED
+// Description : Device: VBUS Detected
+#define USB_SIE_STATUS_VBUS_DETECTED_RESET  _u(0x0)
+#define USB_SIE_STATUS_VBUS_DETECTED_BITS   _u(0x00000001)
+#define USB_SIE_STATUS_VBUS_DETECTED_MSB    _u(0)
+#define USB_SIE_STATUS_VBUS_DETECTED_LSB    _u(0)
+#define USB_SIE_STATUS_VBUS_DETECTED_ACCESS "RO"
+// =============================================================================
+// Register    : USB_INT_EP_CTRL
+// Description : interrupt endpoint control register
+#define USB_INT_EP_CTRL_OFFSET _u(0x00000054)
+#define USB_INT_EP_CTRL_BITS   _u(0x0000fffe)
+#define USB_INT_EP_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_INT_EP_CTRL_INT_EP_ACTIVE
+// Description : Host: Enable interrupt endpoint 1 -> 15
+#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET  _u(0x0000)
+#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS   _u(0x0000fffe)
+#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB    _u(15)
+#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB    _u(1)
+#define USB_INT_EP_CTRL_INT_EP_ACTIVE_ACCESS "RW"
+// =============================================================================
+// Register    : USB_BUFF_STATUS
+// Description : Buffer status register. A bit set here indicates that a buffer
+//               has completed on the endpoint (if the buffer interrupt is
+//               enabled). It is possible for 2 buffers to be completed, so
+//               clearing the buffer status bit may instantly re set it on the
+//               next clock cycle.
+#define USB_BUFF_STATUS_OFFSET _u(0x00000058)
+#define USB_BUFF_STATUS_BITS   _u(0xffffffff)
+#define USB_BUFF_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP15_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP15_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP15_OUT_BITS   _u(0x80000000)
+#define USB_BUFF_STATUS_EP15_OUT_MSB    _u(31)
+#define USB_BUFF_STATUS_EP15_OUT_LSB    _u(31)
+#define USB_BUFF_STATUS_EP15_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP15_IN
+// Description : None
+#define USB_BUFF_STATUS_EP15_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP15_IN_BITS   _u(0x40000000)
+#define USB_BUFF_STATUS_EP15_IN_MSB    _u(30)
+#define USB_BUFF_STATUS_EP15_IN_LSB    _u(30)
+#define USB_BUFF_STATUS_EP15_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP14_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP14_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP14_OUT_BITS   _u(0x20000000)
+#define USB_BUFF_STATUS_EP14_OUT_MSB    _u(29)
+#define USB_BUFF_STATUS_EP14_OUT_LSB    _u(29)
+#define USB_BUFF_STATUS_EP14_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP14_IN
+// Description : None
+#define USB_BUFF_STATUS_EP14_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP14_IN_BITS   _u(0x10000000)
+#define USB_BUFF_STATUS_EP14_IN_MSB    _u(28)
+#define USB_BUFF_STATUS_EP14_IN_LSB    _u(28)
+#define USB_BUFF_STATUS_EP14_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP13_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP13_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP13_OUT_BITS   _u(0x08000000)
+#define USB_BUFF_STATUS_EP13_OUT_MSB    _u(27)
+#define USB_BUFF_STATUS_EP13_OUT_LSB    _u(27)
+#define USB_BUFF_STATUS_EP13_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP13_IN
+// Description : None
+#define USB_BUFF_STATUS_EP13_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP13_IN_BITS   _u(0x04000000)
+#define USB_BUFF_STATUS_EP13_IN_MSB    _u(26)
+#define USB_BUFF_STATUS_EP13_IN_LSB    _u(26)
+#define USB_BUFF_STATUS_EP13_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP12_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP12_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP12_OUT_BITS   _u(0x02000000)
+#define USB_BUFF_STATUS_EP12_OUT_MSB    _u(25)
+#define USB_BUFF_STATUS_EP12_OUT_LSB    _u(25)
+#define USB_BUFF_STATUS_EP12_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP12_IN
+// Description : None
+#define USB_BUFF_STATUS_EP12_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP12_IN_BITS   _u(0x01000000)
+#define USB_BUFF_STATUS_EP12_IN_MSB    _u(24)
+#define USB_BUFF_STATUS_EP12_IN_LSB    _u(24)
+#define USB_BUFF_STATUS_EP12_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP11_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP11_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP11_OUT_BITS   _u(0x00800000)
+#define USB_BUFF_STATUS_EP11_OUT_MSB    _u(23)
+#define USB_BUFF_STATUS_EP11_OUT_LSB    _u(23)
+#define USB_BUFF_STATUS_EP11_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP11_IN
+// Description : None
+#define USB_BUFF_STATUS_EP11_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP11_IN_BITS   _u(0x00400000)
+#define USB_BUFF_STATUS_EP11_IN_MSB    _u(22)
+#define USB_BUFF_STATUS_EP11_IN_LSB    _u(22)
+#define USB_BUFF_STATUS_EP11_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP10_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP10_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP10_OUT_BITS   _u(0x00200000)
+#define USB_BUFF_STATUS_EP10_OUT_MSB    _u(21)
+#define USB_BUFF_STATUS_EP10_OUT_LSB    _u(21)
+#define USB_BUFF_STATUS_EP10_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP10_IN
+// Description : None
+#define USB_BUFF_STATUS_EP10_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP10_IN_BITS   _u(0x00100000)
+#define USB_BUFF_STATUS_EP10_IN_MSB    _u(20)
+#define USB_BUFF_STATUS_EP10_IN_LSB    _u(20)
+#define USB_BUFF_STATUS_EP10_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP9_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP9_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP9_OUT_BITS   _u(0x00080000)
+#define USB_BUFF_STATUS_EP9_OUT_MSB    _u(19)
+#define USB_BUFF_STATUS_EP9_OUT_LSB    _u(19)
+#define USB_BUFF_STATUS_EP9_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP9_IN
+// Description : None
+#define USB_BUFF_STATUS_EP9_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP9_IN_BITS   _u(0x00040000)
+#define USB_BUFF_STATUS_EP9_IN_MSB    _u(18)
+#define USB_BUFF_STATUS_EP9_IN_LSB    _u(18)
+#define USB_BUFF_STATUS_EP9_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP8_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP8_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP8_OUT_BITS   _u(0x00020000)
+#define USB_BUFF_STATUS_EP8_OUT_MSB    _u(17)
+#define USB_BUFF_STATUS_EP8_OUT_LSB    _u(17)
+#define USB_BUFF_STATUS_EP8_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP8_IN
+// Description : None
+#define USB_BUFF_STATUS_EP8_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP8_IN_BITS   _u(0x00010000)
+#define USB_BUFF_STATUS_EP8_IN_MSB    _u(16)
+#define USB_BUFF_STATUS_EP8_IN_LSB    _u(16)
+#define USB_BUFF_STATUS_EP8_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP7_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP7_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP7_OUT_BITS   _u(0x00008000)
+#define USB_BUFF_STATUS_EP7_OUT_MSB    _u(15)
+#define USB_BUFF_STATUS_EP7_OUT_LSB    _u(15)
+#define USB_BUFF_STATUS_EP7_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP7_IN
+// Description : None
+#define USB_BUFF_STATUS_EP7_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP7_IN_BITS   _u(0x00004000)
+#define USB_BUFF_STATUS_EP7_IN_MSB    _u(14)
+#define USB_BUFF_STATUS_EP7_IN_LSB    _u(14)
+#define USB_BUFF_STATUS_EP7_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP6_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP6_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP6_OUT_BITS   _u(0x00002000)
+#define USB_BUFF_STATUS_EP6_OUT_MSB    _u(13)
+#define USB_BUFF_STATUS_EP6_OUT_LSB    _u(13)
+#define USB_BUFF_STATUS_EP6_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP6_IN
+// Description : None
+#define USB_BUFF_STATUS_EP6_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP6_IN_BITS   _u(0x00001000)
+#define USB_BUFF_STATUS_EP6_IN_MSB    _u(12)
+#define USB_BUFF_STATUS_EP6_IN_LSB    _u(12)
+#define USB_BUFF_STATUS_EP6_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP5_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP5_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP5_OUT_BITS   _u(0x00000800)
+#define USB_BUFF_STATUS_EP5_OUT_MSB    _u(11)
+#define USB_BUFF_STATUS_EP5_OUT_LSB    _u(11)
+#define USB_BUFF_STATUS_EP5_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP5_IN
+// Description : None
+#define USB_BUFF_STATUS_EP5_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP5_IN_BITS   _u(0x00000400)
+#define USB_BUFF_STATUS_EP5_IN_MSB    _u(10)
+#define USB_BUFF_STATUS_EP5_IN_LSB    _u(10)
+#define USB_BUFF_STATUS_EP5_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP4_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP4_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP4_OUT_BITS   _u(0x00000200)
+#define USB_BUFF_STATUS_EP4_OUT_MSB    _u(9)
+#define USB_BUFF_STATUS_EP4_OUT_LSB    _u(9)
+#define USB_BUFF_STATUS_EP4_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP4_IN
+// Description : None
+#define USB_BUFF_STATUS_EP4_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP4_IN_BITS   _u(0x00000100)
+#define USB_BUFF_STATUS_EP4_IN_MSB    _u(8)
+#define USB_BUFF_STATUS_EP4_IN_LSB    _u(8)
+#define USB_BUFF_STATUS_EP4_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP3_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP3_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP3_OUT_BITS   _u(0x00000080)
+#define USB_BUFF_STATUS_EP3_OUT_MSB    _u(7)
+#define USB_BUFF_STATUS_EP3_OUT_LSB    _u(7)
+#define USB_BUFF_STATUS_EP3_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP3_IN
+// Description : None
+#define USB_BUFF_STATUS_EP3_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP3_IN_BITS   _u(0x00000040)
+#define USB_BUFF_STATUS_EP3_IN_MSB    _u(6)
+#define USB_BUFF_STATUS_EP3_IN_LSB    _u(6)
+#define USB_BUFF_STATUS_EP3_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP2_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP2_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP2_OUT_BITS   _u(0x00000020)
+#define USB_BUFF_STATUS_EP2_OUT_MSB    _u(5)
+#define USB_BUFF_STATUS_EP2_OUT_LSB    _u(5)
+#define USB_BUFF_STATUS_EP2_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP2_IN
+// Description : None
+#define USB_BUFF_STATUS_EP2_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP2_IN_BITS   _u(0x00000010)
+#define USB_BUFF_STATUS_EP2_IN_MSB    _u(4)
+#define USB_BUFF_STATUS_EP2_IN_LSB    _u(4)
+#define USB_BUFF_STATUS_EP2_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP1_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP1_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP1_OUT_BITS   _u(0x00000008)
+#define USB_BUFF_STATUS_EP1_OUT_MSB    _u(3)
+#define USB_BUFF_STATUS_EP1_OUT_LSB    _u(3)
+#define USB_BUFF_STATUS_EP1_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP1_IN
+// Description : None
+#define USB_BUFF_STATUS_EP1_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP1_IN_BITS   _u(0x00000004)
+#define USB_BUFF_STATUS_EP1_IN_MSB    _u(2)
+#define USB_BUFF_STATUS_EP1_IN_LSB    _u(2)
+#define USB_BUFF_STATUS_EP1_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP0_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP0_OUT_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP0_OUT_BITS   _u(0x00000002)
+#define USB_BUFF_STATUS_EP0_OUT_MSB    _u(1)
+#define USB_BUFF_STATUS_EP0_OUT_LSB    _u(1)
+#define USB_BUFF_STATUS_EP0_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_STATUS_EP0_IN
+// Description : None
+#define USB_BUFF_STATUS_EP0_IN_RESET  _u(0x0)
+#define USB_BUFF_STATUS_EP0_IN_BITS   _u(0x00000001)
+#define USB_BUFF_STATUS_EP0_IN_MSB    _u(0)
+#define USB_BUFF_STATUS_EP0_IN_LSB    _u(0)
+#define USB_BUFF_STATUS_EP0_IN_ACCESS "WC"
+// =============================================================================
+// Register    : USB_BUFF_CPU_SHOULD_HANDLE
+// Description : Which of the double buffers should be handled. Only valid if
+//               using an interrupt per buffer (i.e. not per 2 buffers). Not
+//               valid for host interrupt endpoint polling because they are only
+//               single buffered.
+#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET _u(0x0000005c)
+#define USB_BUFF_CPU_SHOULD_HANDLE_BITS   _u(0xffffffff)
+#define USB_BUFF_CPU_SHOULD_HANDLE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS   _u(0x80000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB    _u(31)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB    _u(31)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS   _u(0x40000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB    _u(30)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB    _u(30)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS   _u(0x20000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB    _u(29)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB    _u(29)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS   _u(0x10000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB    _u(28)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB    _u(28)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS   _u(0x08000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB    _u(27)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB    _u(27)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS   _u(0x04000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB    _u(26)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB    _u(26)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS   _u(0x02000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB    _u(25)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB    _u(25)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS   _u(0x01000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB    _u(24)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB    _u(24)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS   _u(0x00800000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB    _u(23)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB    _u(23)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS   _u(0x00400000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB    _u(22)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB    _u(22)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS   _u(0x00200000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB    _u(21)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB    _u(21)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS   _u(0x00100000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB    _u(20)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB    _u(20)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS   _u(0x00080000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB    _u(19)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB    _u(19)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS   _u(0x00040000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB    _u(18)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB    _u(18)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS   _u(0x00020000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB    _u(17)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB    _u(17)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS   _u(0x00010000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB    _u(16)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB    _u(16)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS   _u(0x00008000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB    _u(15)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB    _u(15)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS   _u(0x00004000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB    _u(14)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB    _u(14)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS   _u(0x00002000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB    _u(13)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB    _u(13)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS   _u(0x00001000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB    _u(12)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB    _u(12)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS   _u(0x00000800)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB    _u(11)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB    _u(11)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS   _u(0x00000400)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB    _u(10)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB    _u(10)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS   _u(0x00000200)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB    _u(9)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB    _u(9)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS   _u(0x00000100)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB    _u(8)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB    _u(8)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS   _u(0x00000080)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB    _u(7)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB    _u(7)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS   _u(0x00000040)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB    _u(6)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB    _u(6)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS   _u(0x00000020)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB    _u(5)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB    _u(5)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS   _u(0x00000010)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB    _u(4)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB    _u(4)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS   _u(0x00000008)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB    _u(3)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB    _u(3)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS   _u(0x00000004)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB    _u(2)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB    _u(2)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS   _u(0x00000002)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB    _u(1)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB    _u(1)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET  _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS   _u(0x00000001)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB    _u(0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB    _u(0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_ACCESS "RO"
+// =============================================================================
+// Register    : USB_EP_ABORT
+// Description : Device only: Can be set to ignore the buffer control register
+//               for this endpoint in case you would like to revoke a buffer. A
+//               NAK will be sent for every access to the endpoint until this
+//               bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set
+//               when it is safe to modify the buffer control register.
+#define USB_EP_ABORT_OFFSET _u(0x00000060)
+#define USB_EP_ABORT_BITS   _u(0xffffffff)
+#define USB_EP_ABORT_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP15_OUT
+// Description : None
+#define USB_EP_ABORT_EP15_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP15_OUT_BITS   _u(0x80000000)
+#define USB_EP_ABORT_EP15_OUT_MSB    _u(31)
+#define USB_EP_ABORT_EP15_OUT_LSB    _u(31)
+#define USB_EP_ABORT_EP15_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP15_IN
+// Description : None
+#define USB_EP_ABORT_EP15_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP15_IN_BITS   _u(0x40000000)
+#define USB_EP_ABORT_EP15_IN_MSB    _u(30)
+#define USB_EP_ABORT_EP15_IN_LSB    _u(30)
+#define USB_EP_ABORT_EP15_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP14_OUT
+// Description : None
+#define USB_EP_ABORT_EP14_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP14_OUT_BITS   _u(0x20000000)
+#define USB_EP_ABORT_EP14_OUT_MSB    _u(29)
+#define USB_EP_ABORT_EP14_OUT_LSB    _u(29)
+#define USB_EP_ABORT_EP14_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP14_IN
+// Description : None
+#define USB_EP_ABORT_EP14_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP14_IN_BITS   _u(0x10000000)
+#define USB_EP_ABORT_EP14_IN_MSB    _u(28)
+#define USB_EP_ABORT_EP14_IN_LSB    _u(28)
+#define USB_EP_ABORT_EP14_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP13_OUT
+// Description : None
+#define USB_EP_ABORT_EP13_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP13_OUT_BITS   _u(0x08000000)
+#define USB_EP_ABORT_EP13_OUT_MSB    _u(27)
+#define USB_EP_ABORT_EP13_OUT_LSB    _u(27)
+#define USB_EP_ABORT_EP13_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP13_IN
+// Description : None
+#define USB_EP_ABORT_EP13_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP13_IN_BITS   _u(0x04000000)
+#define USB_EP_ABORT_EP13_IN_MSB    _u(26)
+#define USB_EP_ABORT_EP13_IN_LSB    _u(26)
+#define USB_EP_ABORT_EP13_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP12_OUT
+// Description : None
+#define USB_EP_ABORT_EP12_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP12_OUT_BITS   _u(0x02000000)
+#define USB_EP_ABORT_EP12_OUT_MSB    _u(25)
+#define USB_EP_ABORT_EP12_OUT_LSB    _u(25)
+#define USB_EP_ABORT_EP12_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP12_IN
+// Description : None
+#define USB_EP_ABORT_EP12_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP12_IN_BITS   _u(0x01000000)
+#define USB_EP_ABORT_EP12_IN_MSB    _u(24)
+#define USB_EP_ABORT_EP12_IN_LSB    _u(24)
+#define USB_EP_ABORT_EP12_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP11_OUT
+// Description : None
+#define USB_EP_ABORT_EP11_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP11_OUT_BITS   _u(0x00800000)
+#define USB_EP_ABORT_EP11_OUT_MSB    _u(23)
+#define USB_EP_ABORT_EP11_OUT_LSB    _u(23)
+#define USB_EP_ABORT_EP11_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP11_IN
+// Description : None
+#define USB_EP_ABORT_EP11_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP11_IN_BITS   _u(0x00400000)
+#define USB_EP_ABORT_EP11_IN_MSB    _u(22)
+#define USB_EP_ABORT_EP11_IN_LSB    _u(22)
+#define USB_EP_ABORT_EP11_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP10_OUT
+// Description : None
+#define USB_EP_ABORT_EP10_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP10_OUT_BITS   _u(0x00200000)
+#define USB_EP_ABORT_EP10_OUT_MSB    _u(21)
+#define USB_EP_ABORT_EP10_OUT_LSB    _u(21)
+#define USB_EP_ABORT_EP10_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP10_IN
+// Description : None
+#define USB_EP_ABORT_EP10_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP10_IN_BITS   _u(0x00100000)
+#define USB_EP_ABORT_EP10_IN_MSB    _u(20)
+#define USB_EP_ABORT_EP10_IN_LSB    _u(20)
+#define USB_EP_ABORT_EP10_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP9_OUT
+// Description : None
+#define USB_EP_ABORT_EP9_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP9_OUT_BITS   _u(0x00080000)
+#define USB_EP_ABORT_EP9_OUT_MSB    _u(19)
+#define USB_EP_ABORT_EP9_OUT_LSB    _u(19)
+#define USB_EP_ABORT_EP9_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP9_IN
+// Description : None
+#define USB_EP_ABORT_EP9_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP9_IN_BITS   _u(0x00040000)
+#define USB_EP_ABORT_EP9_IN_MSB    _u(18)
+#define USB_EP_ABORT_EP9_IN_LSB    _u(18)
+#define USB_EP_ABORT_EP9_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP8_OUT
+// Description : None
+#define USB_EP_ABORT_EP8_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP8_OUT_BITS   _u(0x00020000)
+#define USB_EP_ABORT_EP8_OUT_MSB    _u(17)
+#define USB_EP_ABORT_EP8_OUT_LSB    _u(17)
+#define USB_EP_ABORT_EP8_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP8_IN
+// Description : None
+#define USB_EP_ABORT_EP8_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP8_IN_BITS   _u(0x00010000)
+#define USB_EP_ABORT_EP8_IN_MSB    _u(16)
+#define USB_EP_ABORT_EP8_IN_LSB    _u(16)
+#define USB_EP_ABORT_EP8_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP7_OUT
+// Description : None
+#define USB_EP_ABORT_EP7_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP7_OUT_BITS   _u(0x00008000)
+#define USB_EP_ABORT_EP7_OUT_MSB    _u(15)
+#define USB_EP_ABORT_EP7_OUT_LSB    _u(15)
+#define USB_EP_ABORT_EP7_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP7_IN
+// Description : None
+#define USB_EP_ABORT_EP7_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP7_IN_BITS   _u(0x00004000)
+#define USB_EP_ABORT_EP7_IN_MSB    _u(14)
+#define USB_EP_ABORT_EP7_IN_LSB    _u(14)
+#define USB_EP_ABORT_EP7_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP6_OUT
+// Description : None
+#define USB_EP_ABORT_EP6_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP6_OUT_BITS   _u(0x00002000)
+#define USB_EP_ABORT_EP6_OUT_MSB    _u(13)
+#define USB_EP_ABORT_EP6_OUT_LSB    _u(13)
+#define USB_EP_ABORT_EP6_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP6_IN
+// Description : None
+#define USB_EP_ABORT_EP6_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP6_IN_BITS   _u(0x00001000)
+#define USB_EP_ABORT_EP6_IN_MSB    _u(12)
+#define USB_EP_ABORT_EP6_IN_LSB    _u(12)
+#define USB_EP_ABORT_EP6_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP5_OUT
+// Description : None
+#define USB_EP_ABORT_EP5_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP5_OUT_BITS   _u(0x00000800)
+#define USB_EP_ABORT_EP5_OUT_MSB    _u(11)
+#define USB_EP_ABORT_EP5_OUT_LSB    _u(11)
+#define USB_EP_ABORT_EP5_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP5_IN
+// Description : None
+#define USB_EP_ABORT_EP5_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP5_IN_BITS   _u(0x00000400)
+#define USB_EP_ABORT_EP5_IN_MSB    _u(10)
+#define USB_EP_ABORT_EP5_IN_LSB    _u(10)
+#define USB_EP_ABORT_EP5_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP4_OUT
+// Description : None
+#define USB_EP_ABORT_EP4_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP4_OUT_BITS   _u(0x00000200)
+#define USB_EP_ABORT_EP4_OUT_MSB    _u(9)
+#define USB_EP_ABORT_EP4_OUT_LSB    _u(9)
+#define USB_EP_ABORT_EP4_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP4_IN
+// Description : None
+#define USB_EP_ABORT_EP4_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP4_IN_BITS   _u(0x00000100)
+#define USB_EP_ABORT_EP4_IN_MSB    _u(8)
+#define USB_EP_ABORT_EP4_IN_LSB    _u(8)
+#define USB_EP_ABORT_EP4_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP3_OUT
+// Description : None
+#define USB_EP_ABORT_EP3_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP3_OUT_BITS   _u(0x00000080)
+#define USB_EP_ABORT_EP3_OUT_MSB    _u(7)
+#define USB_EP_ABORT_EP3_OUT_LSB    _u(7)
+#define USB_EP_ABORT_EP3_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP3_IN
+// Description : None
+#define USB_EP_ABORT_EP3_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP3_IN_BITS   _u(0x00000040)
+#define USB_EP_ABORT_EP3_IN_MSB    _u(6)
+#define USB_EP_ABORT_EP3_IN_LSB    _u(6)
+#define USB_EP_ABORT_EP3_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP2_OUT
+// Description : None
+#define USB_EP_ABORT_EP2_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP2_OUT_BITS   _u(0x00000020)
+#define USB_EP_ABORT_EP2_OUT_MSB    _u(5)
+#define USB_EP_ABORT_EP2_OUT_LSB    _u(5)
+#define USB_EP_ABORT_EP2_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP2_IN
+// Description : None
+#define USB_EP_ABORT_EP2_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP2_IN_BITS   _u(0x00000010)
+#define USB_EP_ABORT_EP2_IN_MSB    _u(4)
+#define USB_EP_ABORT_EP2_IN_LSB    _u(4)
+#define USB_EP_ABORT_EP2_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP1_OUT
+// Description : None
+#define USB_EP_ABORT_EP1_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP1_OUT_BITS   _u(0x00000008)
+#define USB_EP_ABORT_EP1_OUT_MSB    _u(3)
+#define USB_EP_ABORT_EP1_OUT_LSB    _u(3)
+#define USB_EP_ABORT_EP1_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP1_IN
+// Description : None
+#define USB_EP_ABORT_EP1_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP1_IN_BITS   _u(0x00000004)
+#define USB_EP_ABORT_EP1_IN_MSB    _u(2)
+#define USB_EP_ABORT_EP1_IN_LSB    _u(2)
+#define USB_EP_ABORT_EP1_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP0_OUT
+// Description : None
+#define USB_EP_ABORT_EP0_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_EP0_OUT_BITS   _u(0x00000002)
+#define USB_EP_ABORT_EP0_OUT_MSB    _u(1)
+#define USB_EP_ABORT_EP0_OUT_LSB    _u(1)
+#define USB_EP_ABORT_EP0_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_EP0_IN
+// Description : None
+#define USB_EP_ABORT_EP0_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_EP0_IN_BITS   _u(0x00000001)
+#define USB_EP_ABORT_EP0_IN_MSB    _u(0)
+#define USB_EP_ABORT_EP0_IN_LSB    _u(0)
+#define USB_EP_ABORT_EP0_IN_ACCESS "RW"
+// =============================================================================
+// Register    : USB_EP_ABORT_DONE
+// Description : Device only: Used in conjunction with `EP_ABORT`. Set once an
+//               endpoint is idle so the programmer knows it is safe to modify
+//               the buffer control register.
+#define USB_EP_ABORT_DONE_OFFSET _u(0x00000064)
+#define USB_EP_ABORT_DONE_BITS   _u(0xffffffff)
+#define USB_EP_ABORT_DONE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP15_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP15_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP15_OUT_BITS   _u(0x80000000)
+#define USB_EP_ABORT_DONE_EP15_OUT_MSB    _u(31)
+#define USB_EP_ABORT_DONE_EP15_OUT_LSB    _u(31)
+#define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP15_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP15_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP15_IN_BITS   _u(0x40000000)
+#define USB_EP_ABORT_DONE_EP15_IN_MSB    _u(30)
+#define USB_EP_ABORT_DONE_EP15_IN_LSB    _u(30)
+#define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP14_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP14_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP14_OUT_BITS   _u(0x20000000)
+#define USB_EP_ABORT_DONE_EP14_OUT_MSB    _u(29)
+#define USB_EP_ABORT_DONE_EP14_OUT_LSB    _u(29)
+#define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP14_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP14_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP14_IN_BITS   _u(0x10000000)
+#define USB_EP_ABORT_DONE_EP14_IN_MSB    _u(28)
+#define USB_EP_ABORT_DONE_EP14_IN_LSB    _u(28)
+#define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP13_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP13_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP13_OUT_BITS   _u(0x08000000)
+#define USB_EP_ABORT_DONE_EP13_OUT_MSB    _u(27)
+#define USB_EP_ABORT_DONE_EP13_OUT_LSB    _u(27)
+#define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP13_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP13_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP13_IN_BITS   _u(0x04000000)
+#define USB_EP_ABORT_DONE_EP13_IN_MSB    _u(26)
+#define USB_EP_ABORT_DONE_EP13_IN_LSB    _u(26)
+#define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP12_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP12_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP12_OUT_BITS   _u(0x02000000)
+#define USB_EP_ABORT_DONE_EP12_OUT_MSB    _u(25)
+#define USB_EP_ABORT_DONE_EP12_OUT_LSB    _u(25)
+#define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP12_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP12_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP12_IN_BITS   _u(0x01000000)
+#define USB_EP_ABORT_DONE_EP12_IN_MSB    _u(24)
+#define USB_EP_ABORT_DONE_EP12_IN_LSB    _u(24)
+#define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP11_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP11_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP11_OUT_BITS   _u(0x00800000)
+#define USB_EP_ABORT_DONE_EP11_OUT_MSB    _u(23)
+#define USB_EP_ABORT_DONE_EP11_OUT_LSB    _u(23)
+#define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP11_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP11_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP11_IN_BITS   _u(0x00400000)
+#define USB_EP_ABORT_DONE_EP11_IN_MSB    _u(22)
+#define USB_EP_ABORT_DONE_EP11_IN_LSB    _u(22)
+#define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP10_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP10_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP10_OUT_BITS   _u(0x00200000)
+#define USB_EP_ABORT_DONE_EP10_OUT_MSB    _u(21)
+#define USB_EP_ABORT_DONE_EP10_OUT_LSB    _u(21)
+#define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP10_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP10_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP10_IN_BITS   _u(0x00100000)
+#define USB_EP_ABORT_DONE_EP10_IN_MSB    _u(20)
+#define USB_EP_ABORT_DONE_EP10_IN_LSB    _u(20)
+#define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP9_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP9_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP9_OUT_BITS   _u(0x00080000)
+#define USB_EP_ABORT_DONE_EP9_OUT_MSB    _u(19)
+#define USB_EP_ABORT_DONE_EP9_OUT_LSB    _u(19)
+#define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP9_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP9_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP9_IN_BITS   _u(0x00040000)
+#define USB_EP_ABORT_DONE_EP9_IN_MSB    _u(18)
+#define USB_EP_ABORT_DONE_EP9_IN_LSB    _u(18)
+#define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP8_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP8_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP8_OUT_BITS   _u(0x00020000)
+#define USB_EP_ABORT_DONE_EP8_OUT_MSB    _u(17)
+#define USB_EP_ABORT_DONE_EP8_OUT_LSB    _u(17)
+#define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP8_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP8_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP8_IN_BITS   _u(0x00010000)
+#define USB_EP_ABORT_DONE_EP8_IN_MSB    _u(16)
+#define USB_EP_ABORT_DONE_EP8_IN_LSB    _u(16)
+#define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP7_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP7_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP7_OUT_BITS   _u(0x00008000)
+#define USB_EP_ABORT_DONE_EP7_OUT_MSB    _u(15)
+#define USB_EP_ABORT_DONE_EP7_OUT_LSB    _u(15)
+#define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP7_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP7_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP7_IN_BITS   _u(0x00004000)
+#define USB_EP_ABORT_DONE_EP7_IN_MSB    _u(14)
+#define USB_EP_ABORT_DONE_EP7_IN_LSB    _u(14)
+#define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP6_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP6_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP6_OUT_BITS   _u(0x00002000)
+#define USB_EP_ABORT_DONE_EP6_OUT_MSB    _u(13)
+#define USB_EP_ABORT_DONE_EP6_OUT_LSB    _u(13)
+#define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP6_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP6_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP6_IN_BITS   _u(0x00001000)
+#define USB_EP_ABORT_DONE_EP6_IN_MSB    _u(12)
+#define USB_EP_ABORT_DONE_EP6_IN_LSB    _u(12)
+#define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP5_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP5_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP5_OUT_BITS   _u(0x00000800)
+#define USB_EP_ABORT_DONE_EP5_OUT_MSB    _u(11)
+#define USB_EP_ABORT_DONE_EP5_OUT_LSB    _u(11)
+#define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP5_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP5_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP5_IN_BITS   _u(0x00000400)
+#define USB_EP_ABORT_DONE_EP5_IN_MSB    _u(10)
+#define USB_EP_ABORT_DONE_EP5_IN_LSB    _u(10)
+#define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP4_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP4_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP4_OUT_BITS   _u(0x00000200)
+#define USB_EP_ABORT_DONE_EP4_OUT_MSB    _u(9)
+#define USB_EP_ABORT_DONE_EP4_OUT_LSB    _u(9)
+#define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP4_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP4_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP4_IN_BITS   _u(0x00000100)
+#define USB_EP_ABORT_DONE_EP4_IN_MSB    _u(8)
+#define USB_EP_ABORT_DONE_EP4_IN_LSB    _u(8)
+#define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP3_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP3_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP3_OUT_BITS   _u(0x00000080)
+#define USB_EP_ABORT_DONE_EP3_OUT_MSB    _u(7)
+#define USB_EP_ABORT_DONE_EP3_OUT_LSB    _u(7)
+#define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP3_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP3_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP3_IN_BITS   _u(0x00000040)
+#define USB_EP_ABORT_DONE_EP3_IN_MSB    _u(6)
+#define USB_EP_ABORT_DONE_EP3_IN_LSB    _u(6)
+#define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP2_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP2_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP2_OUT_BITS   _u(0x00000020)
+#define USB_EP_ABORT_DONE_EP2_OUT_MSB    _u(5)
+#define USB_EP_ABORT_DONE_EP2_OUT_LSB    _u(5)
+#define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP2_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP2_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP2_IN_BITS   _u(0x00000010)
+#define USB_EP_ABORT_DONE_EP2_IN_MSB    _u(4)
+#define USB_EP_ABORT_DONE_EP2_IN_LSB    _u(4)
+#define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP1_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP1_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP1_OUT_BITS   _u(0x00000008)
+#define USB_EP_ABORT_DONE_EP1_OUT_MSB    _u(3)
+#define USB_EP_ABORT_DONE_EP1_OUT_LSB    _u(3)
+#define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP1_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP1_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP1_IN_BITS   _u(0x00000004)
+#define USB_EP_ABORT_DONE_EP1_IN_MSB    _u(2)
+#define USB_EP_ABORT_DONE_EP1_IN_LSB    _u(2)
+#define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP0_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP0_OUT_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP0_OUT_BITS   _u(0x00000002)
+#define USB_EP_ABORT_DONE_EP0_OUT_MSB    _u(1)
+#define USB_EP_ABORT_DONE_EP0_OUT_LSB    _u(1)
+#define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_ABORT_DONE_EP0_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP0_IN_RESET  _u(0x0)
+#define USB_EP_ABORT_DONE_EP0_IN_BITS   _u(0x00000001)
+#define USB_EP_ABORT_DONE_EP0_IN_MSB    _u(0)
+#define USB_EP_ABORT_DONE_EP0_IN_LSB    _u(0)
+#define USB_EP_ABORT_DONE_EP0_IN_ACCESS "WC"
+// =============================================================================
+// Register    : USB_EP_STALL_ARM
+// Description : Device: this bit must be set in conjunction with the `STALL`
+//               bit in the buffer control register to send a STALL on EP0. The
+//               device controller clears these bits when a SETUP packet is
+//               received because the USB spec requires that a STALL condition
+//               is cleared when a SETUP packet is received.
+#define USB_EP_STALL_ARM_OFFSET _u(0x00000068)
+#define USB_EP_STALL_ARM_BITS   _u(0x00000003)
+#define USB_EP_STALL_ARM_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STALL_ARM_EP0_OUT
+// Description : None
+#define USB_EP_STALL_ARM_EP0_OUT_RESET  _u(0x0)
+#define USB_EP_STALL_ARM_EP0_OUT_BITS   _u(0x00000002)
+#define USB_EP_STALL_ARM_EP0_OUT_MSB    _u(1)
+#define USB_EP_STALL_ARM_EP0_OUT_LSB    _u(1)
+#define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STALL_ARM_EP0_IN
+// Description : None
+#define USB_EP_STALL_ARM_EP0_IN_RESET  _u(0x0)
+#define USB_EP_STALL_ARM_EP0_IN_BITS   _u(0x00000001)
+#define USB_EP_STALL_ARM_EP0_IN_MSB    _u(0)
+#define USB_EP_STALL_ARM_EP0_IN_LSB    _u(0)
+#define USB_EP_STALL_ARM_EP0_IN_ACCESS "RW"
+// =============================================================================
+// Register    : USB_NAK_POLL
+// Description : Used by the host controller. Sets the wait time in microseconds
+//               before trying again if the device replies with a NAK.
+#define USB_NAK_POLL_OFFSET _u(0x0000006c)
+#define USB_NAK_POLL_BITS   _u(0x03ff03ff)
+#define USB_NAK_POLL_RESET  _u(0x00100010)
+// -----------------------------------------------------------------------------
+// Field       : USB_NAK_POLL_DELAY_FS
+// Description : NAK polling interval for a full speed device
+#define USB_NAK_POLL_DELAY_FS_RESET  _u(0x010)
+#define USB_NAK_POLL_DELAY_FS_BITS   _u(0x03ff0000)
+#define USB_NAK_POLL_DELAY_FS_MSB    _u(25)
+#define USB_NAK_POLL_DELAY_FS_LSB    _u(16)
+#define USB_NAK_POLL_DELAY_FS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_NAK_POLL_DELAY_LS
+// Description : NAK polling interval for a low speed device
+#define USB_NAK_POLL_DELAY_LS_RESET  _u(0x010)
+#define USB_NAK_POLL_DELAY_LS_BITS   _u(0x000003ff)
+#define USB_NAK_POLL_DELAY_LS_MSB    _u(9)
+#define USB_NAK_POLL_DELAY_LS_LSB    _u(0)
+#define USB_NAK_POLL_DELAY_LS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_EP_STATUS_STALL_NAK
+// Description : Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL`
+//               bits are set. For EP0 this comes from `SIE_CTRL`. For all other
+//               endpoints it comes from the endpoint control register.
+#define USB_EP_STATUS_STALL_NAK_OFFSET _u(0x00000070)
+#define USB_EP_STATUS_STALL_NAK_BITS   _u(0xffffffff)
+#define USB_EP_STATUS_STALL_NAK_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP15_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS   _u(0x80000000)
+#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB    _u(31)
+#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB    _u(31)
+#define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP15_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS   _u(0x40000000)
+#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB    _u(30)
+#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB    _u(30)
+#define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP14_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS   _u(0x20000000)
+#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB    _u(29)
+#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB    _u(29)
+#define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP14_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS   _u(0x10000000)
+#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB    _u(28)
+#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB    _u(28)
+#define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP13_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS   _u(0x08000000)
+#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB    _u(27)
+#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB    _u(27)
+#define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP13_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS   _u(0x04000000)
+#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB    _u(26)
+#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB    _u(26)
+#define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP12_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS   _u(0x02000000)
+#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB    _u(25)
+#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB    _u(25)
+#define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP12_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS   _u(0x01000000)
+#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB    _u(24)
+#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB    _u(24)
+#define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP11_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS   _u(0x00800000)
+#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB    _u(23)
+#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB    _u(23)
+#define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP11_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS   _u(0x00400000)
+#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB    _u(22)
+#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB    _u(22)
+#define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP10_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS   _u(0x00200000)
+#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB    _u(21)
+#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB    _u(21)
+#define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP10_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS   _u(0x00100000)
+#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB    _u(20)
+#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB    _u(20)
+#define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP9_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS   _u(0x00080000)
+#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB    _u(19)
+#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB    _u(19)
+#define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP9_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS   _u(0x00040000)
+#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB    _u(18)
+#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB    _u(18)
+#define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP8_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS   _u(0x00020000)
+#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB    _u(17)
+#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB    _u(17)
+#define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP8_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS   _u(0x00010000)
+#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB    _u(16)
+#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB    _u(16)
+#define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP7_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS   _u(0x00008000)
+#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB    _u(15)
+#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB    _u(15)
+#define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP7_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS   _u(0x00004000)
+#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB    _u(14)
+#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB    _u(14)
+#define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP6_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS   _u(0x00002000)
+#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB    _u(13)
+#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB    _u(13)
+#define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP6_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS   _u(0x00001000)
+#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB    _u(12)
+#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB    _u(12)
+#define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP5_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS   _u(0x00000800)
+#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB    _u(11)
+#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB    _u(11)
+#define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP5_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS   _u(0x00000400)
+#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB    _u(10)
+#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB    _u(10)
+#define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP4_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS   _u(0x00000200)
+#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB    _u(9)
+#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB    _u(9)
+#define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP4_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS   _u(0x00000100)
+#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB    _u(8)
+#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB    _u(8)
+#define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP3_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS   _u(0x00000080)
+#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB    _u(7)
+#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB    _u(7)
+#define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP3_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS   _u(0x00000040)
+#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB    _u(6)
+#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB    _u(6)
+#define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP2_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS   _u(0x00000020)
+#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB    _u(5)
+#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB    _u(5)
+#define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP2_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS   _u(0x00000010)
+#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB    _u(4)
+#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB    _u(4)
+#define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP1_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS   _u(0x00000008)
+#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB    _u(3)
+#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB    _u(3)
+#define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP1_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS   _u(0x00000004)
+#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB    _u(2)
+#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB    _u(2)
+#define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP0_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS   _u(0x00000002)
+#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB    _u(1)
+#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB    _u(1)
+#define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : USB_EP_STATUS_STALL_NAK_EP0_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET  _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS   _u(0x00000001)
+#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB    _u(0)
+#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB    _u(0)
+#define USB_EP_STATUS_STALL_NAK_EP0_IN_ACCESS "WC"
+// =============================================================================
+// Register    : USB_USB_MUXING
+// Description : Where to connect the USB controller. Should be to_phy by
+//               default.
+#define USB_USB_MUXING_OFFSET _u(0x00000074)
+#define USB_USB_MUXING_BITS   _u(0x0000000f)
+#define USB_USB_MUXING_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_USB_MUXING_SOFTCON
+// Description : None
+#define USB_USB_MUXING_SOFTCON_RESET  _u(0x0)
+#define USB_USB_MUXING_SOFTCON_BITS   _u(0x00000008)
+#define USB_USB_MUXING_SOFTCON_MSB    _u(3)
+#define USB_USB_MUXING_SOFTCON_LSB    _u(3)
+#define USB_USB_MUXING_SOFTCON_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USB_MUXING_TO_DIGITAL_PAD
+// Description : None
+#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET  _u(0x0)
+#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS   _u(0x00000004)
+#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB    _u(2)
+#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB    _u(2)
+#define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USB_MUXING_TO_EXTPHY
+// Description : None
+#define USB_USB_MUXING_TO_EXTPHY_RESET  _u(0x0)
+#define USB_USB_MUXING_TO_EXTPHY_BITS   _u(0x00000002)
+#define USB_USB_MUXING_TO_EXTPHY_MSB    _u(1)
+#define USB_USB_MUXING_TO_EXTPHY_LSB    _u(1)
+#define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USB_MUXING_TO_PHY
+// Description : None
+#define USB_USB_MUXING_TO_PHY_RESET  _u(0x0)
+#define USB_USB_MUXING_TO_PHY_BITS   _u(0x00000001)
+#define USB_USB_MUXING_TO_PHY_MSB    _u(0)
+#define USB_USB_MUXING_TO_PHY_LSB    _u(0)
+#define USB_USB_MUXING_TO_PHY_ACCESS "RW"
+// =============================================================================
+// Register    : USB_USB_PWR
+// Description : Overrides for the power signals in the event that the VBUS
+//               signals are not hooked up to GPIO. Set the value of the
+//               override and then the override enable to switch over to the
+//               override value.
+#define USB_USB_PWR_OFFSET _u(0x00000078)
+#define USB_USB_PWR_BITS   _u(0x0000003f)
+#define USB_USB_PWR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_USB_PWR_OVERCURR_DETECT_EN
+// Description : None
+#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET  _u(0x0)
+#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS   _u(0x00000020)
+#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB    _u(5)
+#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB    _u(5)
+#define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USB_PWR_OVERCURR_DETECT
+// Description : None
+#define USB_USB_PWR_OVERCURR_DETECT_RESET  _u(0x0)
+#define USB_USB_PWR_OVERCURR_DETECT_BITS   _u(0x00000010)
+#define USB_USB_PWR_OVERCURR_DETECT_MSB    _u(4)
+#define USB_USB_PWR_OVERCURR_DETECT_LSB    _u(4)
+#define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN
+// Description : None
+#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS   _u(0x00000008)
+#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB    _u(3)
+#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB    _u(3)
+#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USB_PWR_VBUS_DETECT
+// Description : None
+#define USB_USB_PWR_VBUS_DETECT_RESET  _u(0x0)
+#define USB_USB_PWR_VBUS_DETECT_BITS   _u(0x00000004)
+#define USB_USB_PWR_VBUS_DETECT_MSB    _u(2)
+#define USB_USB_PWR_VBUS_DETECT_LSB    _u(2)
+#define USB_USB_PWR_VBUS_DETECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USB_PWR_VBUS_EN_OVERRIDE_EN
+// Description : None
+#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS   _u(0x00000002)
+#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB    _u(1)
+#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB    _u(1)
+#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USB_PWR_VBUS_EN
+// Description : None
+#define USB_USB_PWR_VBUS_EN_RESET  _u(0x0)
+#define USB_USB_PWR_VBUS_EN_BITS   _u(0x00000001)
+#define USB_USB_PWR_VBUS_EN_MSB    _u(0)
+#define USB_USB_PWR_VBUS_EN_LSB    _u(0)
+#define USB_USB_PWR_VBUS_EN_ACCESS "RW"
+// =============================================================================
+// Register    : USB_USBPHY_DIRECT
+// Description : This register allows for direct control of the USB phy. Use in
+//               conjunction with usbphy_direct_override register to enable each
+//               override bit.
+#define USB_USBPHY_DIRECT_OFFSET _u(0x0000007c)
+#define USB_USBPHY_DIRECT_BITS   _u(0x007fff77)
+#define USB_USBPHY_DIRECT_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_DM_OVV
+// Description : DM over voltage
+#define USB_USBPHY_DIRECT_DM_OVV_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_DM_OVV_BITS   _u(0x00400000)
+#define USB_USBPHY_DIRECT_DM_OVV_MSB    _u(22)
+#define USB_USBPHY_DIRECT_DM_OVV_LSB    _u(22)
+#define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_DP_OVV
+// Description : DP over voltage
+#define USB_USBPHY_DIRECT_DP_OVV_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_DP_OVV_BITS   _u(0x00200000)
+#define USB_USBPHY_DIRECT_DP_OVV_MSB    _u(21)
+#define USB_USBPHY_DIRECT_DP_OVV_LSB    _u(21)
+#define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_DM_OVCN
+// Description : DM overcurrent
+#define USB_USBPHY_DIRECT_DM_OVCN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_DM_OVCN_BITS   _u(0x00100000)
+#define USB_USBPHY_DIRECT_DM_OVCN_MSB    _u(20)
+#define USB_USBPHY_DIRECT_DM_OVCN_LSB    _u(20)
+#define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_DP_OVCN
+// Description : DP overcurrent
+#define USB_USBPHY_DIRECT_DP_OVCN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_DP_OVCN_BITS   _u(0x00080000)
+#define USB_USBPHY_DIRECT_DP_OVCN_MSB    _u(19)
+#define USB_USBPHY_DIRECT_DP_OVCN_LSB    _u(19)
+#define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_RX_DM
+// Description : DPM pin state
+#define USB_USBPHY_DIRECT_RX_DM_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_RX_DM_BITS   _u(0x00040000)
+#define USB_USBPHY_DIRECT_RX_DM_MSB    _u(18)
+#define USB_USBPHY_DIRECT_RX_DM_LSB    _u(18)
+#define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_RX_DP
+// Description : DPP pin state
+#define USB_USBPHY_DIRECT_RX_DP_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_RX_DP_BITS   _u(0x00020000)
+#define USB_USBPHY_DIRECT_RX_DP_MSB    _u(17)
+#define USB_USBPHY_DIRECT_RX_DP_LSB    _u(17)
+#define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_RX_DD
+// Description : Differential RX
+#define USB_USBPHY_DIRECT_RX_DD_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_RX_DD_BITS   _u(0x00010000)
+#define USB_USBPHY_DIRECT_RX_DD_MSB    _u(16)
+#define USB_USBPHY_DIRECT_RX_DD_LSB    _u(16)
+#define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_TX_DIFFMODE
+// Description : TX_DIFFMODE=0: Single ended mode
+//               TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE
+//               ignored)
+#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS   _u(0x00008000)
+#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB    _u(15)
+#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB    _u(15)
+#define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_TX_FSSLEW
+// Description : TX_FSSLEW=0: Low speed slew rate
+//               TX_FSSLEW=1: Full speed slew rate
+#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS   _u(0x00004000)
+#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB    _u(14)
+#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB    _u(14)
+#define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_TX_PD
+// Description : TX power down override (if override enable is set). 1 = powered
+//               down.
+#define USB_USBPHY_DIRECT_TX_PD_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_TX_PD_BITS   _u(0x00002000)
+#define USB_USBPHY_DIRECT_TX_PD_MSB    _u(13)
+#define USB_USBPHY_DIRECT_TX_PD_LSB    _u(13)
+#define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_RX_PD
+// Description : RX power down override (if override enable is set). 1 = powered
+//               down.
+#define USB_USBPHY_DIRECT_RX_PD_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_RX_PD_BITS   _u(0x00001000)
+#define USB_USBPHY_DIRECT_RX_PD_MSB    _u(12)
+#define USB_USBPHY_DIRECT_RX_PD_LSB    _u(12)
+#define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_TX_DM
+// Description : Output data. TX_DIFFMODE=1, Ignored
+//               TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive.
+//               DPM=TX_DM
+#define USB_USBPHY_DIRECT_TX_DM_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DM_BITS   _u(0x00000800)
+#define USB_USBPHY_DIRECT_TX_DM_MSB    _u(11)
+#define USB_USBPHY_DIRECT_TX_DM_LSB    _u(11)
+#define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_TX_DP
+// Description : Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair.
+//               TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP
+//               If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive.
+//               DPP=TX_DP
+#define USB_USBPHY_DIRECT_TX_DP_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DP_BITS   _u(0x00000400)
+#define USB_USBPHY_DIRECT_TX_DP_MSB    _u(10)
+#define USB_USBPHY_DIRECT_TX_DP_LSB    _u(10)
+#define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_TX_DM_OE
+// Description : Output enable. If TX_DIFFMODE=1, Ignored.
+//               If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 -
+//               DPM driving
+#define USB_USBPHY_DIRECT_TX_DM_OE_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DM_OE_BITS   _u(0x00000200)
+#define USB_USBPHY_DIRECT_TX_DM_OE_MSB    _u(9)
+#define USB_USBPHY_DIRECT_TX_DM_OE_LSB    _u(9)
+#define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_TX_DP_OE
+// Description : Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 -
+//               DPP/DPM in Hi-Z state; 1 - DPP/DPM driving
+//               If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 -
+//               DPP driving
+#define USB_USBPHY_DIRECT_TX_DP_OE_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DP_OE_BITS   _u(0x00000100)
+#define USB_USBPHY_DIRECT_TX_DP_OE_MSB    _u(8)
+#define USB_USBPHY_DIRECT_TX_DP_OE_LSB    _u(8)
+#define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_DM_PULLDN_EN
+// Description : DM pull down enable
+#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS   _u(0x00000040)
+#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB    _u(6)
+#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB    _u(6)
+#define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_DM_PULLUP_EN
+// Description : DM pull up enable
+#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS   _u(0x00000020)
+#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB    _u(5)
+#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB    _u(5)
+#define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_DM_PULLUP_HISEL
+// Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 -
+//               Pull = Rpu1 + Rpu2
+#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS   _u(0x00000010)
+#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB    _u(4)
+#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB    _u(4)
+#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_DP_PULLDN_EN
+// Description : DP pull down enable
+#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS   _u(0x00000004)
+#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB    _u(2)
+#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB    _u(2)
+#define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_DP_PULLUP_EN
+// Description : DP pull up enable
+#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS   _u(0x00000002)
+#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB    _u(1)
+#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB    _u(1)
+#define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_DP_PULLUP_HISEL
+// Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 -
+//               Pull = Rpu1 + Rpu2
+#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS   _u(0x00000001)
+#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB    _u(0)
+#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB    _u(0)
+#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW"
+// =============================================================================
+// Register    : USB_USBPHY_DIRECT_OVERRIDE
+// Description : Override enable for each control in usbphy_direct
+#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _u(0x00000080)
+#define USB_USBPHY_DIRECT_OVERRIDE_BITS   _u(0x00009fff)
+#define USB_USBPHY_DIRECT_OVERRIDE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS   _u(0x00008000)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB    _u(15)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB    _u(15)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS   _u(0x00001000)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB    _u(12)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB    _u(12)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS   _u(0x00000800)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB    _u(11)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB    _u(11)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS   _u(0x00000400)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB    _u(10)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB    _u(10)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS   _u(0x00000200)
+#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB    _u(9)
+#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB    _u(9)
+#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS   _u(0x00000100)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB    _u(8)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB    _u(8)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS   _u(0x00000080)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB    _u(7)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB    _u(7)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS   _u(0x00000040)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB    _u(6)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB    _u(6)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS   _u(0x00000020)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB    _u(5)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB    _u(5)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS   _u(0x00000010)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB    _u(4)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB    _u(4)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS   _u(0x00000008)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB    _u(3)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB    _u(3)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS   _u(0x00000004)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB    _u(2)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB    _u(2)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS   _u(0x00000002)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB    _u(1)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB    _u(1)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET  _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS   _u(0x00000001)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB    _u(0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB    _u(0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW"
+// =============================================================================
+// Register    : USB_USBPHY_TRIM
+// Description : Used to adjust trim values of USB phy pull down resistors.
+#define USB_USBPHY_TRIM_OFFSET _u(0x00000084)
+#define USB_USBPHY_TRIM_BITS   _u(0x00001f1f)
+#define USB_USBPHY_TRIM_RESET  _u(0x00001f1f)
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_TRIM_DM_PULLDN_TRIM
+// Description : Value to drive to USB PHY
+//               DM pulldown resistor trim control
+//               Experimental data suggests that the reset value will work, but
+//               this register allows adjustment if required
+#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET  _u(0x1f)
+#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS   _u(0x00001f00)
+#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB    _u(12)
+#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB    _u(8)
+#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_USBPHY_TRIM_DP_PULLDN_TRIM
+// Description : Value to drive to USB PHY
+//               DP pulldown resistor trim control
+//               Experimental data suggests that the reset value will work, but
+//               this register allows adjustment if required
+#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET  _u(0x1f)
+#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS   _u(0x0000001f)
+#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB    _u(4)
+#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB    _u(0)
+#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_ACCESS "RW"
+// =============================================================================
+// Register    : USB_INTR
+// Description : Raw Interrupts
+#define USB_INTR_OFFSET _u(0x0000008c)
+#define USB_INTR_BITS   _u(0x000fffff)
+#define USB_INTR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_EP_STALL_NAK
+// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
+//               clearing all bits in EP_STATUS_STALL_NAK.
+#define USB_INTR_EP_STALL_NAK_RESET  _u(0x0)
+#define USB_INTR_EP_STALL_NAK_BITS   _u(0x00080000)
+#define USB_INTR_EP_STALL_NAK_MSB    _u(19)
+#define USB_INTR_EP_STALL_NAK_LSB    _u(19)
+#define USB_INTR_EP_STALL_NAK_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_ABORT_DONE
+// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
+//               bits in ABORT_DONE.
+#define USB_INTR_ABORT_DONE_RESET  _u(0x0)
+#define USB_INTR_ABORT_DONE_BITS   _u(0x00040000)
+#define USB_INTR_ABORT_DONE_MSB    _u(18)
+#define USB_INTR_ABORT_DONE_LSB    _u(18)
+#define USB_INTR_ABORT_DONE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_DEV_SOF
+// Description : Set every time the device receives a SOF (Start of Frame)
+//               packet. Cleared by reading SOF_RD
+#define USB_INTR_DEV_SOF_RESET  _u(0x0)
+#define USB_INTR_DEV_SOF_BITS   _u(0x00020000)
+#define USB_INTR_DEV_SOF_MSB    _u(17)
+#define USB_INTR_DEV_SOF_LSB    _u(17)
+#define USB_INTR_DEV_SOF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_SETUP_REQ
+// Description : Device. Source: SIE_STATUS.SETUP_REC
+#define USB_INTR_SETUP_REQ_RESET  _u(0x0)
+#define USB_INTR_SETUP_REQ_BITS   _u(0x00010000)
+#define USB_INTR_SETUP_REQ_MSB    _u(16)
+#define USB_INTR_SETUP_REQ_LSB    _u(16)
+#define USB_INTR_SETUP_REQ_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_DEV_RESUME_FROM_HOST
+// Description : Set when the device receives a resume from the host. Cleared by
+//               writing to SIE_STATUS.RESUME
+#define USB_INTR_DEV_RESUME_FROM_HOST_RESET  _u(0x0)
+#define USB_INTR_DEV_RESUME_FROM_HOST_BITS   _u(0x00008000)
+#define USB_INTR_DEV_RESUME_FROM_HOST_MSB    _u(15)
+#define USB_INTR_DEV_RESUME_FROM_HOST_LSB    _u(15)
+#define USB_INTR_DEV_RESUME_FROM_HOST_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_DEV_SUSPEND
+// Description : Set when the device suspend state changes. Cleared by writing
+//               to SIE_STATUS.SUSPENDED
+#define USB_INTR_DEV_SUSPEND_RESET  _u(0x0)
+#define USB_INTR_DEV_SUSPEND_BITS   _u(0x00004000)
+#define USB_INTR_DEV_SUSPEND_MSB    _u(14)
+#define USB_INTR_DEV_SUSPEND_LSB    _u(14)
+#define USB_INTR_DEV_SUSPEND_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_DEV_CONN_DIS
+// Description : Set when the device connection state changes. Cleared by
+//               writing to SIE_STATUS.CONNECTED
+#define USB_INTR_DEV_CONN_DIS_RESET  _u(0x0)
+#define USB_INTR_DEV_CONN_DIS_BITS   _u(0x00002000)
+#define USB_INTR_DEV_CONN_DIS_MSB    _u(13)
+#define USB_INTR_DEV_CONN_DIS_LSB    _u(13)
+#define USB_INTR_DEV_CONN_DIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_BUS_RESET
+// Description : Source: SIE_STATUS.BUS_RESET
+#define USB_INTR_BUS_RESET_RESET  _u(0x0)
+#define USB_INTR_BUS_RESET_BITS   _u(0x00001000)
+#define USB_INTR_BUS_RESET_MSB    _u(12)
+#define USB_INTR_BUS_RESET_LSB    _u(12)
+#define USB_INTR_BUS_RESET_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
+#define USB_INTR_VBUS_DETECT_RESET  _u(0x0)
+#define USB_INTR_VBUS_DETECT_BITS   _u(0x00000800)
+#define USB_INTR_VBUS_DETECT_MSB    _u(11)
+#define USB_INTR_VBUS_DETECT_LSB    _u(11)
+#define USB_INTR_VBUS_DETECT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_STALL
+// Description : Source: SIE_STATUS.STALL_REC
+#define USB_INTR_STALL_RESET  _u(0x0)
+#define USB_INTR_STALL_BITS   _u(0x00000400)
+#define USB_INTR_STALL_MSB    _u(10)
+#define USB_INTR_STALL_LSB    _u(10)
+#define USB_INTR_STALL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_ERROR_CRC
+// Description : Source: SIE_STATUS.CRC_ERROR
+#define USB_INTR_ERROR_CRC_RESET  _u(0x0)
+#define USB_INTR_ERROR_CRC_BITS   _u(0x00000200)
+#define USB_INTR_ERROR_CRC_MSB    _u(9)
+#define USB_INTR_ERROR_CRC_LSB    _u(9)
+#define USB_INTR_ERROR_CRC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_ERROR_BIT_STUFF
+// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
+#define USB_INTR_ERROR_BIT_STUFF_RESET  _u(0x0)
+#define USB_INTR_ERROR_BIT_STUFF_BITS   _u(0x00000100)
+#define USB_INTR_ERROR_BIT_STUFF_MSB    _u(8)
+#define USB_INTR_ERROR_BIT_STUFF_LSB    _u(8)
+#define USB_INTR_ERROR_BIT_STUFF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_ERROR_RX_OVERFLOW
+// Description : Source: SIE_STATUS.RX_OVERFLOW
+#define USB_INTR_ERROR_RX_OVERFLOW_RESET  _u(0x0)
+#define USB_INTR_ERROR_RX_OVERFLOW_BITS   _u(0x00000080)
+#define USB_INTR_ERROR_RX_OVERFLOW_MSB    _u(7)
+#define USB_INTR_ERROR_RX_OVERFLOW_LSB    _u(7)
+#define USB_INTR_ERROR_RX_OVERFLOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_ERROR_RX_TIMEOUT
+// Description : Source: SIE_STATUS.RX_TIMEOUT
+#define USB_INTR_ERROR_RX_TIMEOUT_RESET  _u(0x0)
+#define USB_INTR_ERROR_RX_TIMEOUT_BITS   _u(0x00000040)
+#define USB_INTR_ERROR_RX_TIMEOUT_MSB    _u(6)
+#define USB_INTR_ERROR_RX_TIMEOUT_LSB    _u(6)
+#define USB_INTR_ERROR_RX_TIMEOUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_ERROR_DATA_SEQ
+// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
+#define USB_INTR_ERROR_DATA_SEQ_RESET  _u(0x0)
+#define USB_INTR_ERROR_DATA_SEQ_BITS   _u(0x00000020)
+#define USB_INTR_ERROR_DATA_SEQ_MSB    _u(5)
+#define USB_INTR_ERROR_DATA_SEQ_LSB    _u(5)
+#define USB_INTR_ERROR_DATA_SEQ_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_BUFF_STATUS
+// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
+//               all bits in BUFF_STATUS.
+#define USB_INTR_BUFF_STATUS_RESET  _u(0x0)
+#define USB_INTR_BUFF_STATUS_BITS   _u(0x00000010)
+#define USB_INTR_BUFF_STATUS_MSB    _u(4)
+#define USB_INTR_BUFF_STATUS_LSB    _u(4)
+#define USB_INTR_BUFF_STATUS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_TRANS_COMPLETE
+// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
+//               writing to this bit.
+#define USB_INTR_TRANS_COMPLETE_RESET  _u(0x0)
+#define USB_INTR_TRANS_COMPLETE_BITS   _u(0x00000008)
+#define USB_INTR_TRANS_COMPLETE_MSB    _u(3)
+#define USB_INTR_TRANS_COMPLETE_LSB    _u(3)
+#define USB_INTR_TRANS_COMPLETE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_HOST_SOF
+// Description : Host: raised every time the host sends a SOF (Start of Frame).
+//               Cleared by reading SOF_RD
+#define USB_INTR_HOST_SOF_RESET  _u(0x0)
+#define USB_INTR_HOST_SOF_BITS   _u(0x00000004)
+#define USB_INTR_HOST_SOF_MSB    _u(2)
+#define USB_INTR_HOST_SOF_LSB    _u(2)
+#define USB_INTR_HOST_SOF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_HOST_RESUME
+// Description : Host: raised when a device wakes up the host. Cleared by
+//               writing to SIE_STATUS.RESUME
+#define USB_INTR_HOST_RESUME_RESET  _u(0x0)
+#define USB_INTR_HOST_RESUME_BITS   _u(0x00000002)
+#define USB_INTR_HOST_RESUME_MSB    _u(1)
+#define USB_INTR_HOST_RESUME_LSB    _u(1)
+#define USB_INTR_HOST_RESUME_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTR_HOST_CONN_DIS
+// Description : Host: raised when a device is connected or disconnected (i.e.
+//               when SIE_STATUS.SPEED changes). Cleared by writing to
+//               SIE_STATUS.SPEED
+#define USB_INTR_HOST_CONN_DIS_RESET  _u(0x0)
+#define USB_INTR_HOST_CONN_DIS_BITS   _u(0x00000001)
+#define USB_INTR_HOST_CONN_DIS_MSB    _u(0)
+#define USB_INTR_HOST_CONN_DIS_LSB    _u(0)
+#define USB_INTR_HOST_CONN_DIS_ACCESS "RO"
+// =============================================================================
+// Register    : USB_INTE
+// Description : Interrupt Enable
+#define USB_INTE_OFFSET _u(0x00000090)
+#define USB_INTE_BITS   _u(0x000fffff)
+#define USB_INTE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_EP_STALL_NAK
+// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
+//               clearing all bits in EP_STATUS_STALL_NAK.
+#define USB_INTE_EP_STALL_NAK_RESET  _u(0x0)
+#define USB_INTE_EP_STALL_NAK_BITS   _u(0x00080000)
+#define USB_INTE_EP_STALL_NAK_MSB    _u(19)
+#define USB_INTE_EP_STALL_NAK_LSB    _u(19)
+#define USB_INTE_EP_STALL_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_ABORT_DONE
+// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
+//               bits in ABORT_DONE.
+#define USB_INTE_ABORT_DONE_RESET  _u(0x0)
+#define USB_INTE_ABORT_DONE_BITS   _u(0x00040000)
+#define USB_INTE_ABORT_DONE_MSB    _u(18)
+#define USB_INTE_ABORT_DONE_LSB    _u(18)
+#define USB_INTE_ABORT_DONE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_DEV_SOF
+// Description : Set every time the device receives a SOF (Start of Frame)
+//               packet. Cleared by reading SOF_RD
+#define USB_INTE_DEV_SOF_RESET  _u(0x0)
+#define USB_INTE_DEV_SOF_BITS   _u(0x00020000)
+#define USB_INTE_DEV_SOF_MSB    _u(17)
+#define USB_INTE_DEV_SOF_LSB    _u(17)
+#define USB_INTE_DEV_SOF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_SETUP_REQ
+// Description : Device. Source: SIE_STATUS.SETUP_REC
+#define USB_INTE_SETUP_REQ_RESET  _u(0x0)
+#define USB_INTE_SETUP_REQ_BITS   _u(0x00010000)
+#define USB_INTE_SETUP_REQ_MSB    _u(16)
+#define USB_INTE_SETUP_REQ_LSB    _u(16)
+#define USB_INTE_SETUP_REQ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_DEV_RESUME_FROM_HOST
+// Description : Set when the device receives a resume from the host. Cleared by
+//               writing to SIE_STATUS.RESUME
+#define USB_INTE_DEV_RESUME_FROM_HOST_RESET  _u(0x0)
+#define USB_INTE_DEV_RESUME_FROM_HOST_BITS   _u(0x00008000)
+#define USB_INTE_DEV_RESUME_FROM_HOST_MSB    _u(15)
+#define USB_INTE_DEV_RESUME_FROM_HOST_LSB    _u(15)
+#define USB_INTE_DEV_RESUME_FROM_HOST_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_DEV_SUSPEND
+// Description : Set when the device suspend state changes. Cleared by writing
+//               to SIE_STATUS.SUSPENDED
+#define USB_INTE_DEV_SUSPEND_RESET  _u(0x0)
+#define USB_INTE_DEV_SUSPEND_BITS   _u(0x00004000)
+#define USB_INTE_DEV_SUSPEND_MSB    _u(14)
+#define USB_INTE_DEV_SUSPEND_LSB    _u(14)
+#define USB_INTE_DEV_SUSPEND_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_DEV_CONN_DIS
+// Description : Set when the device connection state changes. Cleared by
+//               writing to SIE_STATUS.CONNECTED
+#define USB_INTE_DEV_CONN_DIS_RESET  _u(0x0)
+#define USB_INTE_DEV_CONN_DIS_BITS   _u(0x00002000)
+#define USB_INTE_DEV_CONN_DIS_MSB    _u(13)
+#define USB_INTE_DEV_CONN_DIS_LSB    _u(13)
+#define USB_INTE_DEV_CONN_DIS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_BUS_RESET
+// Description : Source: SIE_STATUS.BUS_RESET
+#define USB_INTE_BUS_RESET_RESET  _u(0x0)
+#define USB_INTE_BUS_RESET_BITS   _u(0x00001000)
+#define USB_INTE_BUS_RESET_MSB    _u(12)
+#define USB_INTE_BUS_RESET_LSB    _u(12)
+#define USB_INTE_BUS_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
+#define USB_INTE_VBUS_DETECT_RESET  _u(0x0)
+#define USB_INTE_VBUS_DETECT_BITS   _u(0x00000800)
+#define USB_INTE_VBUS_DETECT_MSB    _u(11)
+#define USB_INTE_VBUS_DETECT_LSB    _u(11)
+#define USB_INTE_VBUS_DETECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_STALL
+// Description : Source: SIE_STATUS.STALL_REC
+#define USB_INTE_STALL_RESET  _u(0x0)
+#define USB_INTE_STALL_BITS   _u(0x00000400)
+#define USB_INTE_STALL_MSB    _u(10)
+#define USB_INTE_STALL_LSB    _u(10)
+#define USB_INTE_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_ERROR_CRC
+// Description : Source: SIE_STATUS.CRC_ERROR
+#define USB_INTE_ERROR_CRC_RESET  _u(0x0)
+#define USB_INTE_ERROR_CRC_BITS   _u(0x00000200)
+#define USB_INTE_ERROR_CRC_MSB    _u(9)
+#define USB_INTE_ERROR_CRC_LSB    _u(9)
+#define USB_INTE_ERROR_CRC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_ERROR_BIT_STUFF
+// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
+#define USB_INTE_ERROR_BIT_STUFF_RESET  _u(0x0)
+#define USB_INTE_ERROR_BIT_STUFF_BITS   _u(0x00000100)
+#define USB_INTE_ERROR_BIT_STUFF_MSB    _u(8)
+#define USB_INTE_ERROR_BIT_STUFF_LSB    _u(8)
+#define USB_INTE_ERROR_BIT_STUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_ERROR_RX_OVERFLOW
+// Description : Source: SIE_STATUS.RX_OVERFLOW
+#define USB_INTE_ERROR_RX_OVERFLOW_RESET  _u(0x0)
+#define USB_INTE_ERROR_RX_OVERFLOW_BITS   _u(0x00000080)
+#define USB_INTE_ERROR_RX_OVERFLOW_MSB    _u(7)
+#define USB_INTE_ERROR_RX_OVERFLOW_LSB    _u(7)
+#define USB_INTE_ERROR_RX_OVERFLOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_ERROR_RX_TIMEOUT
+// Description : Source: SIE_STATUS.RX_TIMEOUT
+#define USB_INTE_ERROR_RX_TIMEOUT_RESET  _u(0x0)
+#define USB_INTE_ERROR_RX_TIMEOUT_BITS   _u(0x00000040)
+#define USB_INTE_ERROR_RX_TIMEOUT_MSB    _u(6)
+#define USB_INTE_ERROR_RX_TIMEOUT_LSB    _u(6)
+#define USB_INTE_ERROR_RX_TIMEOUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_ERROR_DATA_SEQ
+// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
+#define USB_INTE_ERROR_DATA_SEQ_RESET  _u(0x0)
+#define USB_INTE_ERROR_DATA_SEQ_BITS   _u(0x00000020)
+#define USB_INTE_ERROR_DATA_SEQ_MSB    _u(5)
+#define USB_INTE_ERROR_DATA_SEQ_LSB    _u(5)
+#define USB_INTE_ERROR_DATA_SEQ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_BUFF_STATUS
+// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
+//               all bits in BUFF_STATUS.
+#define USB_INTE_BUFF_STATUS_RESET  _u(0x0)
+#define USB_INTE_BUFF_STATUS_BITS   _u(0x00000010)
+#define USB_INTE_BUFF_STATUS_MSB    _u(4)
+#define USB_INTE_BUFF_STATUS_LSB    _u(4)
+#define USB_INTE_BUFF_STATUS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_TRANS_COMPLETE
+// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
+//               writing to this bit.
+#define USB_INTE_TRANS_COMPLETE_RESET  _u(0x0)
+#define USB_INTE_TRANS_COMPLETE_BITS   _u(0x00000008)
+#define USB_INTE_TRANS_COMPLETE_MSB    _u(3)
+#define USB_INTE_TRANS_COMPLETE_LSB    _u(3)
+#define USB_INTE_TRANS_COMPLETE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_HOST_SOF
+// Description : Host: raised every time the host sends a SOF (Start of Frame).
+//               Cleared by reading SOF_RD
+#define USB_INTE_HOST_SOF_RESET  _u(0x0)
+#define USB_INTE_HOST_SOF_BITS   _u(0x00000004)
+#define USB_INTE_HOST_SOF_MSB    _u(2)
+#define USB_INTE_HOST_SOF_LSB    _u(2)
+#define USB_INTE_HOST_SOF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_HOST_RESUME
+// Description : Host: raised when a device wakes up the host. Cleared by
+//               writing to SIE_STATUS.RESUME
+#define USB_INTE_HOST_RESUME_RESET  _u(0x0)
+#define USB_INTE_HOST_RESUME_BITS   _u(0x00000002)
+#define USB_INTE_HOST_RESUME_MSB    _u(1)
+#define USB_INTE_HOST_RESUME_LSB    _u(1)
+#define USB_INTE_HOST_RESUME_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTE_HOST_CONN_DIS
+// Description : Host: raised when a device is connected or disconnected (i.e.
+//               when SIE_STATUS.SPEED changes). Cleared by writing to
+//               SIE_STATUS.SPEED
+#define USB_INTE_HOST_CONN_DIS_RESET  _u(0x0)
+#define USB_INTE_HOST_CONN_DIS_BITS   _u(0x00000001)
+#define USB_INTE_HOST_CONN_DIS_MSB    _u(0)
+#define USB_INTE_HOST_CONN_DIS_LSB    _u(0)
+#define USB_INTE_HOST_CONN_DIS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_INTF
+// Description : Interrupt Force
+#define USB_INTF_OFFSET _u(0x00000094)
+#define USB_INTF_BITS   _u(0x000fffff)
+#define USB_INTF_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_EP_STALL_NAK
+// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
+//               clearing all bits in EP_STATUS_STALL_NAK.
+#define USB_INTF_EP_STALL_NAK_RESET  _u(0x0)
+#define USB_INTF_EP_STALL_NAK_BITS   _u(0x00080000)
+#define USB_INTF_EP_STALL_NAK_MSB    _u(19)
+#define USB_INTF_EP_STALL_NAK_LSB    _u(19)
+#define USB_INTF_EP_STALL_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_ABORT_DONE
+// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
+//               bits in ABORT_DONE.
+#define USB_INTF_ABORT_DONE_RESET  _u(0x0)
+#define USB_INTF_ABORT_DONE_BITS   _u(0x00040000)
+#define USB_INTF_ABORT_DONE_MSB    _u(18)
+#define USB_INTF_ABORT_DONE_LSB    _u(18)
+#define USB_INTF_ABORT_DONE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_DEV_SOF
+// Description : Set every time the device receives a SOF (Start of Frame)
+//               packet. Cleared by reading SOF_RD
+#define USB_INTF_DEV_SOF_RESET  _u(0x0)
+#define USB_INTF_DEV_SOF_BITS   _u(0x00020000)
+#define USB_INTF_DEV_SOF_MSB    _u(17)
+#define USB_INTF_DEV_SOF_LSB    _u(17)
+#define USB_INTF_DEV_SOF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_SETUP_REQ
+// Description : Device. Source: SIE_STATUS.SETUP_REC
+#define USB_INTF_SETUP_REQ_RESET  _u(0x0)
+#define USB_INTF_SETUP_REQ_BITS   _u(0x00010000)
+#define USB_INTF_SETUP_REQ_MSB    _u(16)
+#define USB_INTF_SETUP_REQ_LSB    _u(16)
+#define USB_INTF_SETUP_REQ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_DEV_RESUME_FROM_HOST
+// Description : Set when the device receives a resume from the host. Cleared by
+//               writing to SIE_STATUS.RESUME
+#define USB_INTF_DEV_RESUME_FROM_HOST_RESET  _u(0x0)
+#define USB_INTF_DEV_RESUME_FROM_HOST_BITS   _u(0x00008000)
+#define USB_INTF_DEV_RESUME_FROM_HOST_MSB    _u(15)
+#define USB_INTF_DEV_RESUME_FROM_HOST_LSB    _u(15)
+#define USB_INTF_DEV_RESUME_FROM_HOST_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_DEV_SUSPEND
+// Description : Set when the device suspend state changes. Cleared by writing
+//               to SIE_STATUS.SUSPENDED
+#define USB_INTF_DEV_SUSPEND_RESET  _u(0x0)
+#define USB_INTF_DEV_SUSPEND_BITS   _u(0x00004000)
+#define USB_INTF_DEV_SUSPEND_MSB    _u(14)
+#define USB_INTF_DEV_SUSPEND_LSB    _u(14)
+#define USB_INTF_DEV_SUSPEND_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_DEV_CONN_DIS
+// Description : Set when the device connection state changes. Cleared by
+//               writing to SIE_STATUS.CONNECTED
+#define USB_INTF_DEV_CONN_DIS_RESET  _u(0x0)
+#define USB_INTF_DEV_CONN_DIS_BITS   _u(0x00002000)
+#define USB_INTF_DEV_CONN_DIS_MSB    _u(13)
+#define USB_INTF_DEV_CONN_DIS_LSB    _u(13)
+#define USB_INTF_DEV_CONN_DIS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_BUS_RESET
+// Description : Source: SIE_STATUS.BUS_RESET
+#define USB_INTF_BUS_RESET_RESET  _u(0x0)
+#define USB_INTF_BUS_RESET_BITS   _u(0x00001000)
+#define USB_INTF_BUS_RESET_MSB    _u(12)
+#define USB_INTF_BUS_RESET_LSB    _u(12)
+#define USB_INTF_BUS_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
+#define USB_INTF_VBUS_DETECT_RESET  _u(0x0)
+#define USB_INTF_VBUS_DETECT_BITS   _u(0x00000800)
+#define USB_INTF_VBUS_DETECT_MSB    _u(11)
+#define USB_INTF_VBUS_DETECT_LSB    _u(11)
+#define USB_INTF_VBUS_DETECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_STALL
+// Description : Source: SIE_STATUS.STALL_REC
+#define USB_INTF_STALL_RESET  _u(0x0)
+#define USB_INTF_STALL_BITS   _u(0x00000400)
+#define USB_INTF_STALL_MSB    _u(10)
+#define USB_INTF_STALL_LSB    _u(10)
+#define USB_INTF_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_ERROR_CRC
+// Description : Source: SIE_STATUS.CRC_ERROR
+#define USB_INTF_ERROR_CRC_RESET  _u(0x0)
+#define USB_INTF_ERROR_CRC_BITS   _u(0x00000200)
+#define USB_INTF_ERROR_CRC_MSB    _u(9)
+#define USB_INTF_ERROR_CRC_LSB    _u(9)
+#define USB_INTF_ERROR_CRC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_ERROR_BIT_STUFF
+// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
+#define USB_INTF_ERROR_BIT_STUFF_RESET  _u(0x0)
+#define USB_INTF_ERROR_BIT_STUFF_BITS   _u(0x00000100)
+#define USB_INTF_ERROR_BIT_STUFF_MSB    _u(8)
+#define USB_INTF_ERROR_BIT_STUFF_LSB    _u(8)
+#define USB_INTF_ERROR_BIT_STUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_ERROR_RX_OVERFLOW
+// Description : Source: SIE_STATUS.RX_OVERFLOW
+#define USB_INTF_ERROR_RX_OVERFLOW_RESET  _u(0x0)
+#define USB_INTF_ERROR_RX_OVERFLOW_BITS   _u(0x00000080)
+#define USB_INTF_ERROR_RX_OVERFLOW_MSB    _u(7)
+#define USB_INTF_ERROR_RX_OVERFLOW_LSB    _u(7)
+#define USB_INTF_ERROR_RX_OVERFLOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_ERROR_RX_TIMEOUT
+// Description : Source: SIE_STATUS.RX_TIMEOUT
+#define USB_INTF_ERROR_RX_TIMEOUT_RESET  _u(0x0)
+#define USB_INTF_ERROR_RX_TIMEOUT_BITS   _u(0x00000040)
+#define USB_INTF_ERROR_RX_TIMEOUT_MSB    _u(6)
+#define USB_INTF_ERROR_RX_TIMEOUT_LSB    _u(6)
+#define USB_INTF_ERROR_RX_TIMEOUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_ERROR_DATA_SEQ
+// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
+#define USB_INTF_ERROR_DATA_SEQ_RESET  _u(0x0)
+#define USB_INTF_ERROR_DATA_SEQ_BITS   _u(0x00000020)
+#define USB_INTF_ERROR_DATA_SEQ_MSB    _u(5)
+#define USB_INTF_ERROR_DATA_SEQ_LSB    _u(5)
+#define USB_INTF_ERROR_DATA_SEQ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_BUFF_STATUS
+// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
+//               all bits in BUFF_STATUS.
+#define USB_INTF_BUFF_STATUS_RESET  _u(0x0)
+#define USB_INTF_BUFF_STATUS_BITS   _u(0x00000010)
+#define USB_INTF_BUFF_STATUS_MSB    _u(4)
+#define USB_INTF_BUFF_STATUS_LSB    _u(4)
+#define USB_INTF_BUFF_STATUS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_TRANS_COMPLETE
+// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
+//               writing to this bit.
+#define USB_INTF_TRANS_COMPLETE_RESET  _u(0x0)
+#define USB_INTF_TRANS_COMPLETE_BITS   _u(0x00000008)
+#define USB_INTF_TRANS_COMPLETE_MSB    _u(3)
+#define USB_INTF_TRANS_COMPLETE_LSB    _u(3)
+#define USB_INTF_TRANS_COMPLETE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_HOST_SOF
+// Description : Host: raised every time the host sends a SOF (Start of Frame).
+//               Cleared by reading SOF_RD
+#define USB_INTF_HOST_SOF_RESET  _u(0x0)
+#define USB_INTF_HOST_SOF_BITS   _u(0x00000004)
+#define USB_INTF_HOST_SOF_MSB    _u(2)
+#define USB_INTF_HOST_SOF_LSB    _u(2)
+#define USB_INTF_HOST_SOF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_HOST_RESUME
+// Description : Host: raised when a device wakes up the host. Cleared by
+//               writing to SIE_STATUS.RESUME
+#define USB_INTF_HOST_RESUME_RESET  _u(0x0)
+#define USB_INTF_HOST_RESUME_BITS   _u(0x00000002)
+#define USB_INTF_HOST_RESUME_MSB    _u(1)
+#define USB_INTF_HOST_RESUME_LSB    _u(1)
+#define USB_INTF_HOST_RESUME_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTF_HOST_CONN_DIS
+// Description : Host: raised when a device is connected or disconnected (i.e.
+//               when SIE_STATUS.SPEED changes). Cleared by writing to
+//               SIE_STATUS.SPEED
+#define USB_INTF_HOST_CONN_DIS_RESET  _u(0x0)
+#define USB_INTF_HOST_CONN_DIS_BITS   _u(0x00000001)
+#define USB_INTF_HOST_CONN_DIS_MSB    _u(0)
+#define USB_INTF_HOST_CONN_DIS_LSB    _u(0)
+#define USB_INTF_HOST_CONN_DIS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_INTS
+// Description : Interrupt status after masking & forcing
+#define USB_INTS_OFFSET _u(0x00000098)
+#define USB_INTS_BITS   _u(0x000fffff)
+#define USB_INTS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_EP_STALL_NAK
+// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
+//               clearing all bits in EP_STATUS_STALL_NAK.
+#define USB_INTS_EP_STALL_NAK_RESET  _u(0x0)
+#define USB_INTS_EP_STALL_NAK_BITS   _u(0x00080000)
+#define USB_INTS_EP_STALL_NAK_MSB    _u(19)
+#define USB_INTS_EP_STALL_NAK_LSB    _u(19)
+#define USB_INTS_EP_STALL_NAK_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_ABORT_DONE
+// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
+//               bits in ABORT_DONE.
+#define USB_INTS_ABORT_DONE_RESET  _u(0x0)
+#define USB_INTS_ABORT_DONE_BITS   _u(0x00040000)
+#define USB_INTS_ABORT_DONE_MSB    _u(18)
+#define USB_INTS_ABORT_DONE_LSB    _u(18)
+#define USB_INTS_ABORT_DONE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_DEV_SOF
+// Description : Set every time the device receives a SOF (Start of Frame)
+//               packet. Cleared by reading SOF_RD
+#define USB_INTS_DEV_SOF_RESET  _u(0x0)
+#define USB_INTS_DEV_SOF_BITS   _u(0x00020000)
+#define USB_INTS_DEV_SOF_MSB    _u(17)
+#define USB_INTS_DEV_SOF_LSB    _u(17)
+#define USB_INTS_DEV_SOF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_SETUP_REQ
+// Description : Device. Source: SIE_STATUS.SETUP_REC
+#define USB_INTS_SETUP_REQ_RESET  _u(0x0)
+#define USB_INTS_SETUP_REQ_BITS   _u(0x00010000)
+#define USB_INTS_SETUP_REQ_MSB    _u(16)
+#define USB_INTS_SETUP_REQ_LSB    _u(16)
+#define USB_INTS_SETUP_REQ_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_DEV_RESUME_FROM_HOST
+// Description : Set when the device receives a resume from the host. Cleared by
+//               writing to SIE_STATUS.RESUME
+#define USB_INTS_DEV_RESUME_FROM_HOST_RESET  _u(0x0)
+#define USB_INTS_DEV_RESUME_FROM_HOST_BITS   _u(0x00008000)
+#define USB_INTS_DEV_RESUME_FROM_HOST_MSB    _u(15)
+#define USB_INTS_DEV_RESUME_FROM_HOST_LSB    _u(15)
+#define USB_INTS_DEV_RESUME_FROM_HOST_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_DEV_SUSPEND
+// Description : Set when the device suspend state changes. Cleared by writing
+//               to SIE_STATUS.SUSPENDED
+#define USB_INTS_DEV_SUSPEND_RESET  _u(0x0)
+#define USB_INTS_DEV_SUSPEND_BITS   _u(0x00004000)
+#define USB_INTS_DEV_SUSPEND_MSB    _u(14)
+#define USB_INTS_DEV_SUSPEND_LSB    _u(14)
+#define USB_INTS_DEV_SUSPEND_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_DEV_CONN_DIS
+// Description : Set when the device connection state changes. Cleared by
+//               writing to SIE_STATUS.CONNECTED
+#define USB_INTS_DEV_CONN_DIS_RESET  _u(0x0)
+#define USB_INTS_DEV_CONN_DIS_BITS   _u(0x00002000)
+#define USB_INTS_DEV_CONN_DIS_MSB    _u(13)
+#define USB_INTS_DEV_CONN_DIS_LSB    _u(13)
+#define USB_INTS_DEV_CONN_DIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_BUS_RESET
+// Description : Source: SIE_STATUS.BUS_RESET
+#define USB_INTS_BUS_RESET_RESET  _u(0x0)
+#define USB_INTS_BUS_RESET_BITS   _u(0x00001000)
+#define USB_INTS_BUS_RESET_MSB    _u(12)
+#define USB_INTS_BUS_RESET_LSB    _u(12)
+#define USB_INTS_BUS_RESET_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
+#define USB_INTS_VBUS_DETECT_RESET  _u(0x0)
+#define USB_INTS_VBUS_DETECT_BITS   _u(0x00000800)
+#define USB_INTS_VBUS_DETECT_MSB    _u(11)
+#define USB_INTS_VBUS_DETECT_LSB    _u(11)
+#define USB_INTS_VBUS_DETECT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_STALL
+// Description : Source: SIE_STATUS.STALL_REC
+#define USB_INTS_STALL_RESET  _u(0x0)
+#define USB_INTS_STALL_BITS   _u(0x00000400)
+#define USB_INTS_STALL_MSB    _u(10)
+#define USB_INTS_STALL_LSB    _u(10)
+#define USB_INTS_STALL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_ERROR_CRC
+// Description : Source: SIE_STATUS.CRC_ERROR
+#define USB_INTS_ERROR_CRC_RESET  _u(0x0)
+#define USB_INTS_ERROR_CRC_BITS   _u(0x00000200)
+#define USB_INTS_ERROR_CRC_MSB    _u(9)
+#define USB_INTS_ERROR_CRC_LSB    _u(9)
+#define USB_INTS_ERROR_CRC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_ERROR_BIT_STUFF
+// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
+#define USB_INTS_ERROR_BIT_STUFF_RESET  _u(0x0)
+#define USB_INTS_ERROR_BIT_STUFF_BITS   _u(0x00000100)
+#define USB_INTS_ERROR_BIT_STUFF_MSB    _u(8)
+#define USB_INTS_ERROR_BIT_STUFF_LSB    _u(8)
+#define USB_INTS_ERROR_BIT_STUFF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_ERROR_RX_OVERFLOW
+// Description : Source: SIE_STATUS.RX_OVERFLOW
+#define USB_INTS_ERROR_RX_OVERFLOW_RESET  _u(0x0)
+#define USB_INTS_ERROR_RX_OVERFLOW_BITS   _u(0x00000080)
+#define USB_INTS_ERROR_RX_OVERFLOW_MSB    _u(7)
+#define USB_INTS_ERROR_RX_OVERFLOW_LSB    _u(7)
+#define USB_INTS_ERROR_RX_OVERFLOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_ERROR_RX_TIMEOUT
+// Description : Source: SIE_STATUS.RX_TIMEOUT
+#define USB_INTS_ERROR_RX_TIMEOUT_RESET  _u(0x0)
+#define USB_INTS_ERROR_RX_TIMEOUT_BITS   _u(0x00000040)
+#define USB_INTS_ERROR_RX_TIMEOUT_MSB    _u(6)
+#define USB_INTS_ERROR_RX_TIMEOUT_LSB    _u(6)
+#define USB_INTS_ERROR_RX_TIMEOUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_ERROR_DATA_SEQ
+// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
+#define USB_INTS_ERROR_DATA_SEQ_RESET  _u(0x0)
+#define USB_INTS_ERROR_DATA_SEQ_BITS   _u(0x00000020)
+#define USB_INTS_ERROR_DATA_SEQ_MSB    _u(5)
+#define USB_INTS_ERROR_DATA_SEQ_LSB    _u(5)
+#define USB_INTS_ERROR_DATA_SEQ_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_BUFF_STATUS
+// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
+//               all bits in BUFF_STATUS.
+#define USB_INTS_BUFF_STATUS_RESET  _u(0x0)
+#define USB_INTS_BUFF_STATUS_BITS   _u(0x00000010)
+#define USB_INTS_BUFF_STATUS_MSB    _u(4)
+#define USB_INTS_BUFF_STATUS_LSB    _u(4)
+#define USB_INTS_BUFF_STATUS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_TRANS_COMPLETE
+// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
+//               writing to this bit.
+#define USB_INTS_TRANS_COMPLETE_RESET  _u(0x0)
+#define USB_INTS_TRANS_COMPLETE_BITS   _u(0x00000008)
+#define USB_INTS_TRANS_COMPLETE_MSB    _u(3)
+#define USB_INTS_TRANS_COMPLETE_LSB    _u(3)
+#define USB_INTS_TRANS_COMPLETE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_HOST_SOF
+// Description : Host: raised every time the host sends a SOF (Start of Frame).
+//               Cleared by reading SOF_RD
+#define USB_INTS_HOST_SOF_RESET  _u(0x0)
+#define USB_INTS_HOST_SOF_BITS   _u(0x00000004)
+#define USB_INTS_HOST_SOF_MSB    _u(2)
+#define USB_INTS_HOST_SOF_LSB    _u(2)
+#define USB_INTS_HOST_SOF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_HOST_RESUME
+// Description : Host: raised when a device wakes up the host. Cleared by
+//               writing to SIE_STATUS.RESUME
+#define USB_INTS_HOST_RESUME_RESET  _u(0x0)
+#define USB_INTS_HOST_RESUME_BITS   _u(0x00000002)
+#define USB_INTS_HOST_RESUME_MSB    _u(1)
+#define USB_INTS_HOST_RESUME_LSB    _u(1)
+#define USB_INTS_HOST_RESUME_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : USB_INTS_HOST_CONN_DIS
+// Description : Host: raised when a device is connected or disconnected (i.e.
+//               when SIE_STATUS.SPEED changes). Cleared by writing to
+//               SIE_STATUS.SPEED
+#define USB_INTS_HOST_CONN_DIS_RESET  _u(0x0)
+#define USB_INTS_HOST_CONN_DIS_BITS   _u(0x00000001)
+#define USB_INTS_HOST_CONN_DIS_MSB    _u(0)
+#define USB_INTS_HOST_CONN_DIS_LSB    _u(0)
+#define USB_INTS_HOST_CONN_DIS_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_USB_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h b/src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h
new file mode 100644
index 0000000..fe65ffb
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h
@@ -0,0 +1,6807 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : USB_DEVICE_DPRAM
+// Version        : 1
+// Bus type       : ahbl
+// Description    : DPRAM layout for USB device.
+// =============================================================================
+#ifndef HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED
+#define HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_SETUP_PACKET_LOW
+// Description : Bytes 0-3 of the SETUP packet from the host.
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_OFFSET _u(0x00000000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_BITS   _u(0xffff0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_LSB    _u(16)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_RESET  _u(0x00)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_BITS   _u(0x0000ff00)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_MSB    _u(15)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_LSB    _u(8)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_RESET  _u(0x00)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_BITS   _u(0x000000ff)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_MSB    _u(7)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_LSB    _u(0)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH
+// Description : Bytes 4-7 of the setup packet from the host.
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_OFFSET _u(0x00000004)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_BITS   _u(0xffff0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_MSB    _u(31)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_LSB    _u(16)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_MSB    _u(15)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_LSB    _u(0)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP1_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_OFFSET _u(0x00000008)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP1_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_OFFSET _u(0x0000000c)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP2_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_OFFSET _u(0x00000010)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP2_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_OFFSET _u(0x00000014)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP3_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_OFFSET _u(0x00000018)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP3_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_OFFSET _u(0x0000001c)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP4_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_OFFSET _u(0x00000020)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP4_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_OFFSET _u(0x00000024)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP5_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_OFFSET _u(0x00000028)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP5_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_OFFSET _u(0x0000002c)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP6_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_OFFSET _u(0x00000030)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP6_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_OFFSET _u(0x00000034)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP7_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_OFFSET _u(0x00000038)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP7_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_OFFSET _u(0x0000003c)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP8_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_OFFSET _u(0x00000040)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP8_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_OFFSET _u(0x00000044)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP9_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_OFFSET _u(0x00000048)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP9_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_OFFSET _u(0x0000004c)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP10_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_OFFSET _u(0x00000050)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP10_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_OFFSET _u(0x00000054)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP11_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_OFFSET _u(0x00000058)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP11_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_OFFSET _u(0x0000005c)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP12_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_OFFSET _u(0x00000060)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP12_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_OFFSET _u(0x00000064)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP13_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_OFFSET _u(0x00000068)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP13_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_OFFSET _u(0x0000006c)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP14_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_OFFSET _u(0x00000070)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP14_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_OFFSET _u(0x00000074)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP15_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_OFFSET _u(0x00000078)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP15_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_OFFSET _u(0x0000007c)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BITS   _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+//               for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+//               valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS   _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB    _u(28)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB    _u(28)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+//               0x1 -> Isochronous
+//               0x2 -> Bulk
+//               0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_RESET             _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_BITS              _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_MSB               _u(27)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_LSB               _u(26)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_ACCESS            "RW"
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL     _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK        _u(0x2)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT   _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+//               only.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_BITS   _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_MSB    _u(17)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_LSB    _u(17)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_BITS   _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_MSB    _u(16)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+//               ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_RESET  _u(0x0000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_BITS   _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_OFFSET _u(0x00000080)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_OFFSET _u(0x00000084)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_OFFSET _u(0x00000088)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_OFFSET _u(0x0000008c)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_OFFSET _u(0x00000090)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_OFFSET _u(0x00000094)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_OFFSET _u(0x00000098)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_OFFSET _u(0x0000009c)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_OFFSET _u(0x000000a0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_OFFSET _u(0x000000a4)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_OFFSET _u(0x000000a8)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ac)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_OFFSET _u(0x000000b0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_OFFSET _u(0x000000b4)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_OFFSET _u(0x000000b8)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_OFFSET _u(0x000000bc)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_OFFSET _u(0x000000c0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_OFFSET _u(0x000000c4)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_OFFSET _u(0x000000c8)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_OFFSET _u(0x000000cc)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_OFFSET _u(0x000000d0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_OFFSET _u(0x000000d4)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+//               ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_OFFSET _u(0x000000d8)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_OFFSET _u(0x000000dc)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+//               ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_OFFSET _u(0x000000e0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_OFFSET _u(0x000000e4)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+//               ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_OFFSET _u(0x000000e8)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ec)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+//               ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_OFFSET _u(0x000000f0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_OFFSET _u(0x000000f4)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+//               ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_OFFSET _u(0x000000f8)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+//               T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register    : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+//               in a _1 are for buffer 1.
+//               Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+//               only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_OFFSET _u(0x000000fc)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_BITS   _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_BITS   _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_MSB    _u(31)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_LSB    _u(31)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_BITS   _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_MSB    _u(30)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_LSB    _u(30)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_BITS   _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_MSB    _u(29)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_LSB    _u(29)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+//               ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+//               Isochronous mode. Only valid in double buffered mode for an
+//               Isochronous endpoint.
+//               For a non Isochronous endpoint the offset is always 64 bytes.
+//               0x0 -> 128
+//               0x1 -> 256
+//               0x2 -> 512
+//               0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET      _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS       _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB        _u(28)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB        _u(27)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS     "RW"
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256  _u(0x1)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512  _u(0x2)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS   _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB    _u(26)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB    _u(26)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_BITS   _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_MSB    _u(25)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_LSB    _u(16)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+//               is set to indicate the data is valid. For an OUT transfer (RX
+//               from the host) this bit should be left as a 0. The host will
+//               set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_BITS   _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_MSB    _u(15)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_LSB    _u(15)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_BITS   _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_MSB    _u(14)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_LSB    _u(14)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_BITS   _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_MSB    _u(13)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_LSB    _u(13)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_BITS   _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_MSB    _u(12)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_LSB    _u(12)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_BITS   _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_MSB    _u(11)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_LSB    _u(11)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+//               can be used by the controller. The controller clears the
+//               available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET  _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS   _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB    _u(10)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB    _u(10)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_RESET  _u(0x000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_BITS   _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_MSB    _u(9)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_LSB    _u(0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h b/src/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h
new file mode 100644
index 0000000..356ff56
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h
@@ -0,0 +1,151 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : VREG_AND_CHIP_RESET
+// Version        : 1
+// Bus type       : apb
+// Description    : control and status for on-chip voltage regulator and chip
+//                  level reset subsystem
+// =============================================================================
+#ifndef HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
+#define HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
+// =============================================================================
+// Register    : VREG_AND_CHIP_RESET_VREG
+// Description : Voltage regulator control and status
+#define VREG_AND_CHIP_RESET_VREG_OFFSET _u(0x00000000)
+#define VREG_AND_CHIP_RESET_VREG_BITS   _u(0x000010f3)
+#define VREG_AND_CHIP_RESET_VREG_RESET  _u(0x000000b1)
+// -----------------------------------------------------------------------------
+// Field       : VREG_AND_CHIP_RESET_VREG_ROK
+// Description : regulation status
+//               0=not in regulation, 1=in regulation
+#define VREG_AND_CHIP_RESET_VREG_ROK_RESET  _u(0x0)
+#define VREG_AND_CHIP_RESET_VREG_ROK_BITS   _u(0x00001000)
+#define VREG_AND_CHIP_RESET_VREG_ROK_MSB    _u(12)
+#define VREG_AND_CHIP_RESET_VREG_ROK_LSB    _u(12)
+#define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : VREG_AND_CHIP_RESET_VREG_VSEL
+// Description : output voltage select
+//               0000 to 0101 - 0.80V
+//               0110         - 0.85V
+//               0111         - 0.90V
+//               1000         - 0.95V
+//               1001         - 1.00V
+//               1010         - 1.05V
+//               1011         - 1.10V (default)
+//               1100         - 1.15V
+//               1101         - 1.20V
+//               1110         - 1.25V
+//               1111         - 1.30V
+#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET  _u(0xb)
+#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS   _u(0x000000f0)
+#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB    _u(7)
+#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB    _u(4)
+#define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : VREG_AND_CHIP_RESET_VREG_HIZ
+// Description : high impedance mode select
+//               0=not in high impedance mode, 1=in high impedance mode
+#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET  _u(0x0)
+#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS   _u(0x00000002)
+#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB    _u(1)
+#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB    _u(1)
+#define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : VREG_AND_CHIP_RESET_VREG_EN
+// Description : enable
+//               0=not enabled, 1=enabled
+#define VREG_AND_CHIP_RESET_VREG_EN_RESET  _u(0x1)
+#define VREG_AND_CHIP_RESET_VREG_EN_BITS   _u(0x00000001)
+#define VREG_AND_CHIP_RESET_VREG_EN_MSB    _u(0)
+#define VREG_AND_CHIP_RESET_VREG_EN_LSB    _u(0)
+#define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW"
+// =============================================================================
+// Register    : VREG_AND_CHIP_RESET_BOD
+// Description : brown-out detection control
+#define VREG_AND_CHIP_RESET_BOD_OFFSET _u(0x00000004)
+#define VREG_AND_CHIP_RESET_BOD_BITS   _u(0x000000f1)
+#define VREG_AND_CHIP_RESET_BOD_RESET  _u(0x00000091)
+// -----------------------------------------------------------------------------
+// Field       : VREG_AND_CHIP_RESET_BOD_VSEL
+// Description : threshold select
+//               0000 - 0.473V
+//               0001 - 0.516V
+//               0010 - 0.559V
+//               0011 - 0.602V
+//               0100 - 0.645V
+//               0101 - 0.688V
+//               0110 - 0.731V
+//               0111 - 0.774V
+//               1000 - 0.817V
+//               1001 - 0.860V (default)
+//               1010 - 0.903V
+//               1011 - 0.946V
+//               1100 - 0.989V
+//               1101 - 1.032V
+//               1110 - 1.075V
+//               1111 - 1.118V
+#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET  _u(0x9)
+#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS   _u(0x000000f0)
+#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB    _u(7)
+#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB    _u(4)
+#define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : VREG_AND_CHIP_RESET_BOD_EN
+// Description : enable
+//               0=not enabled, 1=enabled
+#define VREG_AND_CHIP_RESET_BOD_EN_RESET  _u(0x1)
+#define VREG_AND_CHIP_RESET_BOD_EN_BITS   _u(0x00000001)
+#define VREG_AND_CHIP_RESET_BOD_EN_MSB    _u(0)
+#define VREG_AND_CHIP_RESET_BOD_EN_LSB    _u(0)
+#define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW"
+// =============================================================================
+// Register    : VREG_AND_CHIP_RESET_CHIP_RESET
+// Description : Chip reset control and status
+#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET _u(0x00000008)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS   _u(0x01110100)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG
+// Description : This is set by psm_restart from the debugger.
+//               Its purpose is to branch bootcode to a safe mode when the
+//               debugger has issued a psm_restart in order to recover from a
+//               boot lock-up.
+//               In the safe mode the debugger can repair the boot code, clear
+//               this flag then reboot the processor.
+#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET  _u(0x0)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS   _u(0x01000000)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB    _u(24)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB    _u(24)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART
+// Description : Last reset was from the debug port
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET  _u(0x0)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS   _u(0x00100000)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB    _u(20)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB    _u(20)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN
+// Description : Last reset was from the RUN pin
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET  _u(0x0)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS   _u(0x00010000)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB    _u(16)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB    _u(16)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR
+// Description : Last reset was from the power-on reset or brown-out detection
+//               blocks
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET  _u(0x0)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS   _u(0x00000100)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB    _u(8)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB    _u(8)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/watchdog.h b/src/rp2040/hardware_regs/include/hardware/regs/watchdog.h
new file mode 100644
index 0000000..6a9853d
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/watchdog.h
@@ -0,0 +1,226 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : WATCHDOG
+// Version        : 1
+// Bus type       : apb
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_WATCHDOG_DEFINED
+#define HARDWARE_REGS_WATCHDOG_DEFINED
+// =============================================================================
+// Register    : WATCHDOG_CTRL
+// Description : Watchdog control
+//               The rst_wdsel register determines which subsystems are reset
+//               when the watchdog is triggered.
+//               The watchdog can be triggered in software.
+#define WATCHDOG_CTRL_OFFSET _u(0x00000000)
+#define WATCHDOG_CTRL_BITS   _u(0xc7ffffff)
+#define WATCHDOG_CTRL_RESET  _u(0x07000000)
+// -----------------------------------------------------------------------------
+// Field       : WATCHDOG_CTRL_TRIGGER
+// Description : Trigger a watchdog reset
+#define WATCHDOG_CTRL_TRIGGER_RESET  _u(0x0)
+#define WATCHDOG_CTRL_TRIGGER_BITS   _u(0x80000000)
+#define WATCHDOG_CTRL_TRIGGER_MSB    _u(31)
+#define WATCHDOG_CTRL_TRIGGER_LSB    _u(31)
+#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field       : WATCHDOG_CTRL_ENABLE
+// Description : When not enabled the watchdog timer is paused
+#define WATCHDOG_CTRL_ENABLE_RESET  _u(0x0)
+#define WATCHDOG_CTRL_ENABLE_BITS   _u(0x40000000)
+#define WATCHDOG_CTRL_ENABLE_MSB    _u(30)
+#define WATCHDOG_CTRL_ENABLE_LSB    _u(30)
+#define WATCHDOG_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : WATCHDOG_CTRL_PAUSE_DBG1
+// Description : Pause the watchdog timer when processor 1 is in debug mode
+#define WATCHDOG_CTRL_PAUSE_DBG1_RESET  _u(0x1)
+#define WATCHDOG_CTRL_PAUSE_DBG1_BITS   _u(0x04000000)
+#define WATCHDOG_CTRL_PAUSE_DBG1_MSB    _u(26)
+#define WATCHDOG_CTRL_PAUSE_DBG1_LSB    _u(26)
+#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : WATCHDOG_CTRL_PAUSE_DBG0
+// Description : Pause the watchdog timer when processor 0 is in debug mode
+#define WATCHDOG_CTRL_PAUSE_DBG0_RESET  _u(0x1)
+#define WATCHDOG_CTRL_PAUSE_DBG0_BITS   _u(0x02000000)
+#define WATCHDOG_CTRL_PAUSE_DBG0_MSB    _u(25)
+#define WATCHDOG_CTRL_PAUSE_DBG0_LSB    _u(25)
+#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : WATCHDOG_CTRL_PAUSE_JTAG
+// Description : Pause the watchdog timer when JTAG is accessing the bus fabric
+#define WATCHDOG_CTRL_PAUSE_JTAG_RESET  _u(0x1)
+#define WATCHDOG_CTRL_PAUSE_JTAG_BITS   _u(0x01000000)
+#define WATCHDOG_CTRL_PAUSE_JTAG_MSB    _u(24)
+#define WATCHDOG_CTRL_PAUSE_JTAG_LSB    _u(24)
+#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : WATCHDOG_CTRL_TIME
+// Description : Indicates the number of ticks / 2 (see errata RP2040-E1) before
+//               a watchdog reset will be triggered
+#define WATCHDOG_CTRL_TIME_RESET  _u(0x000000)
+#define WATCHDOG_CTRL_TIME_BITS   _u(0x00ffffff)
+#define WATCHDOG_CTRL_TIME_MSB    _u(23)
+#define WATCHDOG_CTRL_TIME_LSB    _u(0)
+#define WATCHDOG_CTRL_TIME_ACCESS "RO"
+// =============================================================================
+// Register    : WATCHDOG_LOAD
+// Description : Load the watchdog timer. The maximum setting is 0xffffff which
+//               corresponds to 0xffffff / 2 ticks before triggering a watchdog
+//               reset (see errata RP2040-E1).
+#define WATCHDOG_LOAD_OFFSET _u(0x00000004)
+#define WATCHDOG_LOAD_BITS   _u(0x00ffffff)
+#define WATCHDOG_LOAD_RESET  _u(0x00000000)
+#define WATCHDOG_LOAD_MSB    _u(23)
+#define WATCHDOG_LOAD_LSB    _u(0)
+#define WATCHDOG_LOAD_ACCESS "WF"
+// =============================================================================
+// Register    : WATCHDOG_REASON
+// Description : Logs the reason for the last reset. Both bits are zero for the
+//               case of a hardware reset.
+#define WATCHDOG_REASON_OFFSET _u(0x00000008)
+#define WATCHDOG_REASON_BITS   _u(0x00000003)
+#define WATCHDOG_REASON_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : WATCHDOG_REASON_FORCE
+// Description : None
+#define WATCHDOG_REASON_FORCE_RESET  _u(0x0)
+#define WATCHDOG_REASON_FORCE_BITS   _u(0x00000002)
+#define WATCHDOG_REASON_FORCE_MSB    _u(1)
+#define WATCHDOG_REASON_FORCE_LSB    _u(1)
+#define WATCHDOG_REASON_FORCE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : WATCHDOG_REASON_TIMER
+// Description : None
+#define WATCHDOG_REASON_TIMER_RESET  _u(0x0)
+#define WATCHDOG_REASON_TIMER_BITS   _u(0x00000001)
+#define WATCHDOG_REASON_TIMER_MSB    _u(0)
+#define WATCHDOG_REASON_TIMER_LSB    _u(0)
+#define WATCHDOG_REASON_TIMER_ACCESS "RO"
+// =============================================================================
+// Register    : WATCHDOG_SCRATCH0
+// Description : Scratch register. Information persists through soft reset of
+//               the chip.
+#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c)
+#define WATCHDOG_SCRATCH0_BITS   _u(0xffffffff)
+#define WATCHDOG_SCRATCH0_RESET  _u(0x00000000)
+#define WATCHDOG_SCRATCH0_MSB    _u(31)
+#define WATCHDOG_SCRATCH0_LSB    _u(0)
+#define WATCHDOG_SCRATCH0_ACCESS "RW"
+// =============================================================================
+// Register    : WATCHDOG_SCRATCH1
+// Description : Scratch register. Information persists through soft reset of
+//               the chip.
+#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010)
+#define WATCHDOG_SCRATCH1_BITS   _u(0xffffffff)
+#define WATCHDOG_SCRATCH1_RESET  _u(0x00000000)
+#define WATCHDOG_SCRATCH1_MSB    _u(31)
+#define WATCHDOG_SCRATCH1_LSB    _u(0)
+#define WATCHDOG_SCRATCH1_ACCESS "RW"
+// =============================================================================
+// Register    : WATCHDOG_SCRATCH2
+// Description : Scratch register. Information persists through soft reset of
+//               the chip.
+#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014)
+#define WATCHDOG_SCRATCH2_BITS   _u(0xffffffff)
+#define WATCHDOG_SCRATCH2_RESET  _u(0x00000000)
+#define WATCHDOG_SCRATCH2_MSB    _u(31)
+#define WATCHDOG_SCRATCH2_LSB    _u(0)
+#define WATCHDOG_SCRATCH2_ACCESS "RW"
+// =============================================================================
+// Register    : WATCHDOG_SCRATCH3
+// Description : Scratch register. Information persists through soft reset of
+//               the chip.
+#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018)
+#define WATCHDOG_SCRATCH3_BITS   _u(0xffffffff)
+#define WATCHDOG_SCRATCH3_RESET  _u(0x00000000)
+#define WATCHDOG_SCRATCH3_MSB    _u(31)
+#define WATCHDOG_SCRATCH3_LSB    _u(0)
+#define WATCHDOG_SCRATCH3_ACCESS "RW"
+// =============================================================================
+// Register    : WATCHDOG_SCRATCH4
+// Description : Scratch register. Information persists through soft reset of
+//               the chip.
+#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c)
+#define WATCHDOG_SCRATCH4_BITS   _u(0xffffffff)
+#define WATCHDOG_SCRATCH4_RESET  _u(0x00000000)
+#define WATCHDOG_SCRATCH4_MSB    _u(31)
+#define WATCHDOG_SCRATCH4_LSB    _u(0)
+#define WATCHDOG_SCRATCH4_ACCESS "RW"
+// =============================================================================
+// Register    : WATCHDOG_SCRATCH5
+// Description : Scratch register. Information persists through soft reset of
+//               the chip.
+#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020)
+#define WATCHDOG_SCRATCH5_BITS   _u(0xffffffff)
+#define WATCHDOG_SCRATCH5_RESET  _u(0x00000000)
+#define WATCHDOG_SCRATCH5_MSB    _u(31)
+#define WATCHDOG_SCRATCH5_LSB    _u(0)
+#define WATCHDOG_SCRATCH5_ACCESS "RW"
+// =============================================================================
+// Register    : WATCHDOG_SCRATCH6
+// Description : Scratch register. Information persists through soft reset of
+//               the chip.
+#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024)
+#define WATCHDOG_SCRATCH6_BITS   _u(0xffffffff)
+#define WATCHDOG_SCRATCH6_RESET  _u(0x00000000)
+#define WATCHDOG_SCRATCH6_MSB    _u(31)
+#define WATCHDOG_SCRATCH6_LSB    _u(0)
+#define WATCHDOG_SCRATCH6_ACCESS "RW"
+// =============================================================================
+// Register    : WATCHDOG_SCRATCH7
+// Description : Scratch register. Information persists through soft reset of
+//               the chip.
+#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028)
+#define WATCHDOG_SCRATCH7_BITS   _u(0xffffffff)
+#define WATCHDOG_SCRATCH7_RESET  _u(0x00000000)
+#define WATCHDOG_SCRATCH7_MSB    _u(31)
+#define WATCHDOG_SCRATCH7_LSB    _u(0)
+#define WATCHDOG_SCRATCH7_ACCESS "RW"
+// =============================================================================
+// Register    : WATCHDOG_TICK
+// Description : Controls the tick generator
+#define WATCHDOG_TICK_OFFSET _u(0x0000002c)
+#define WATCHDOG_TICK_BITS   _u(0x000fffff)
+#define WATCHDOG_TICK_RESET  _u(0x00000200)
+// -----------------------------------------------------------------------------
+// Field       : WATCHDOG_TICK_COUNT
+// Description : Count down timer: the remaining number clk_tick cycles before
+//               the next tick is generated.
+#define WATCHDOG_TICK_COUNT_RESET  "-"
+#define WATCHDOG_TICK_COUNT_BITS   _u(0x000ff800)
+#define WATCHDOG_TICK_COUNT_MSB    _u(19)
+#define WATCHDOG_TICK_COUNT_LSB    _u(11)
+#define WATCHDOG_TICK_COUNT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : WATCHDOG_TICK_RUNNING
+// Description : Is the tick generator running?
+#define WATCHDOG_TICK_RUNNING_RESET  "-"
+#define WATCHDOG_TICK_RUNNING_BITS   _u(0x00000400)
+#define WATCHDOG_TICK_RUNNING_MSB    _u(10)
+#define WATCHDOG_TICK_RUNNING_LSB    _u(10)
+#define WATCHDOG_TICK_RUNNING_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : WATCHDOG_TICK_ENABLE
+// Description : start / stop tick generation
+#define WATCHDOG_TICK_ENABLE_RESET  _u(0x1)
+#define WATCHDOG_TICK_ENABLE_BITS   _u(0x00000200)
+#define WATCHDOG_TICK_ENABLE_MSB    _u(9)
+#define WATCHDOG_TICK_ENABLE_LSB    _u(9)
+#define WATCHDOG_TICK_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : WATCHDOG_TICK_CYCLES
+// Description : Total number of clk_tick cycles before the next tick.
+#define WATCHDOG_TICK_CYCLES_RESET  _u(0x000)
+#define WATCHDOG_TICK_CYCLES_BITS   _u(0x000001ff)
+#define WATCHDOG_TICK_CYCLES_MSB    _u(8)
+#define WATCHDOG_TICK_CYCLES_LSB    _u(0)
+#define WATCHDOG_TICK_CYCLES_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_WATCHDOG_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/xip.h b/src/rp2040/hardware_regs/include/hardware/regs/xip.h
new file mode 100644
index 0000000..3964f67
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/xip.h
@@ -0,0 +1,187 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : XIP
+// Version        : 1
+// Bus type       : ahb
+// Description    : QSPI flash execute-in-place block
+// =============================================================================
+#ifndef HARDWARE_REGS_XIP_DEFINED
+#define HARDWARE_REGS_XIP_DEFINED
+// =============================================================================
+// Register    : XIP_CTRL
+// Description : Cache control
+#define XIP_CTRL_OFFSET _u(0x00000000)
+#define XIP_CTRL_BITS   _u(0x0000000b)
+#define XIP_CTRL_RESET  _u(0x00000003)
+// -----------------------------------------------------------------------------
+// Field       : XIP_CTRL_POWER_DOWN
+// Description : When 1, the cache memories are powered down. They retain state,
+//               but can not be accessed. This reduces static power dissipation.
+//               Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache
+//               cannot
+//               be enabled when powered down.
+//               Cache-as-SRAM accesses will produce a bus error response when
+//               the cache is powered down.
+#define XIP_CTRL_POWER_DOWN_RESET  _u(0x0)
+#define XIP_CTRL_POWER_DOWN_BITS   _u(0x00000008)
+#define XIP_CTRL_POWER_DOWN_MSB    _u(3)
+#define XIP_CTRL_POWER_DOWN_LSB    _u(3)
+#define XIP_CTRL_POWER_DOWN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : XIP_CTRL_ERR_BADWRITE
+// Description : When 1, writes to any alias other than 0x0 (caching,
+//               allocating)
+//               will produce a bus fault. When 0, these writes are silently
+//               ignored.
+//               In either case, writes to the 0x0 alias will deallocate on tag
+//               match,
+//               as usual.
+#define XIP_CTRL_ERR_BADWRITE_RESET  _u(0x1)
+#define XIP_CTRL_ERR_BADWRITE_BITS   _u(0x00000002)
+#define XIP_CTRL_ERR_BADWRITE_MSB    _u(1)
+#define XIP_CTRL_ERR_BADWRITE_LSB    _u(1)
+#define XIP_CTRL_ERR_BADWRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : XIP_CTRL_EN
+// Description : When 1, enable the cache. When the cache is disabled, all XIP
+//               accesses
+//               will go straight to the flash, without querying the cache. When
+//               enabled,
+//               cacheable XIP accesses will query the cache, and the flash will
+//               not be accessed if the tag matches and the valid bit is set.
+//
+//               If the cache is enabled, cache-as-SRAM accesses have no effect
+//               on the
+//               cache data RAM, and will produce a bus error response.
+#define XIP_CTRL_EN_RESET  _u(0x1)
+#define XIP_CTRL_EN_BITS   _u(0x00000001)
+#define XIP_CTRL_EN_MSB    _u(0)
+#define XIP_CTRL_EN_LSB    _u(0)
+#define XIP_CTRL_EN_ACCESS "RW"
+// =============================================================================
+// Register    : XIP_FLUSH
+// Description : Cache Flush control
+//               Write 1 to flush the cache. This clears the tag memory, but
+//               the data memory retains its contents. (This means cache-as-SRAM
+//               contents is not affected by flush or reset.)
+//               Reading will hold the bus (stall the processor) until the flush
+//               completes. Alternatively STAT can be polled until completion.
+#define XIP_FLUSH_OFFSET _u(0x00000004)
+#define XIP_FLUSH_BITS   _u(0x00000001)
+#define XIP_FLUSH_RESET  _u(0x00000000)
+#define XIP_FLUSH_MSB    _u(0)
+#define XIP_FLUSH_LSB    _u(0)
+#define XIP_FLUSH_ACCESS "SC"
+// =============================================================================
+// Register    : XIP_STAT
+// Description : Cache Status
+#define XIP_STAT_OFFSET _u(0x00000008)
+#define XIP_STAT_BITS   _u(0x00000007)
+#define XIP_STAT_RESET  _u(0x00000002)
+// -----------------------------------------------------------------------------
+// Field       : XIP_STAT_FIFO_FULL
+// Description : When 1, indicates the XIP streaming FIFO is completely full.
+//               The streaming FIFO is 2 entries deep, so the full and empty
+//               flag allow its level to be ascertained.
+#define XIP_STAT_FIFO_FULL_RESET  _u(0x0)
+#define XIP_STAT_FIFO_FULL_BITS   _u(0x00000004)
+#define XIP_STAT_FIFO_FULL_MSB    _u(2)
+#define XIP_STAT_FIFO_FULL_LSB    _u(2)
+#define XIP_STAT_FIFO_FULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : XIP_STAT_FIFO_EMPTY
+// Description : When 1, indicates the XIP streaming FIFO is completely empty.
+#define XIP_STAT_FIFO_EMPTY_RESET  _u(0x1)
+#define XIP_STAT_FIFO_EMPTY_BITS   _u(0x00000002)
+#define XIP_STAT_FIFO_EMPTY_MSB    _u(1)
+#define XIP_STAT_FIFO_EMPTY_LSB    _u(1)
+#define XIP_STAT_FIFO_EMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : XIP_STAT_FLUSH_READY
+// Description : Reads as 0 while a cache flush is in progress, and 1 otherwise.
+//               The cache is flushed whenever the XIP block is reset, and also
+//               when requested via the FLUSH register.
+#define XIP_STAT_FLUSH_READY_RESET  _u(0x0)
+#define XIP_STAT_FLUSH_READY_BITS   _u(0x00000001)
+#define XIP_STAT_FLUSH_READY_MSB    _u(0)
+#define XIP_STAT_FLUSH_READY_LSB    _u(0)
+#define XIP_STAT_FLUSH_READY_ACCESS "RO"
+// =============================================================================
+// Register    : XIP_CTR_HIT
+// Description : Cache Hit counter
+//               A 32 bit saturating counter that increments upon each cache
+//               hit,
+//               i.e. when an XIP access is serviced directly from cached data.
+//               Write any value to clear.
+#define XIP_CTR_HIT_OFFSET _u(0x0000000c)
+#define XIP_CTR_HIT_BITS   _u(0xffffffff)
+#define XIP_CTR_HIT_RESET  _u(0x00000000)
+#define XIP_CTR_HIT_MSB    _u(31)
+#define XIP_CTR_HIT_LSB    _u(0)
+#define XIP_CTR_HIT_ACCESS "WC"
+// =============================================================================
+// Register    : XIP_CTR_ACC
+// Description : Cache Access counter
+//               A 32 bit saturating counter that increments upon each XIP
+//               access,
+//               whether the cache is hit or not. This includes noncacheable
+//               accesses.
+//               Write any value to clear.
+#define XIP_CTR_ACC_OFFSET _u(0x00000010)
+#define XIP_CTR_ACC_BITS   _u(0xffffffff)
+#define XIP_CTR_ACC_RESET  _u(0x00000000)
+#define XIP_CTR_ACC_MSB    _u(31)
+#define XIP_CTR_ACC_LSB    _u(0)
+#define XIP_CTR_ACC_ACCESS "WC"
+// =============================================================================
+// Register    : XIP_STREAM_ADDR
+// Description : FIFO stream address
+//               The address of the next word to be streamed from flash to the
+//               streaming FIFO.
+//               Increments automatically after each flash access.
+//               Write the initial access address here before starting a
+//               streaming read.
+#define XIP_STREAM_ADDR_OFFSET _u(0x00000014)
+#define XIP_STREAM_ADDR_BITS   _u(0xfffffffc)
+#define XIP_STREAM_ADDR_RESET  _u(0x00000000)
+#define XIP_STREAM_ADDR_MSB    _u(31)
+#define XIP_STREAM_ADDR_LSB    _u(2)
+#define XIP_STREAM_ADDR_ACCESS "RW"
+// =============================================================================
+// Register    : XIP_STREAM_CTR
+// Description : FIFO stream control
+//               Write a nonzero value to start a streaming read. This will then
+//               progress in the background, using flash idle cycles to transfer
+//               a linear data block from flash to the streaming FIFO.
+//               Decrements automatically (1 at a time) as the stream
+//               progresses, and halts on reaching 0.
+//               Write 0 to halt an in-progress stream, and discard any
+//               in-flight
+//               read, so that a new stream can immediately be started (after
+//               draining the FIFO and reinitialising STREAM_ADDR)
+#define XIP_STREAM_CTR_OFFSET _u(0x00000018)
+#define XIP_STREAM_CTR_BITS   _u(0x003fffff)
+#define XIP_STREAM_CTR_RESET  _u(0x00000000)
+#define XIP_STREAM_CTR_MSB    _u(21)
+#define XIP_STREAM_CTR_LSB    _u(0)
+#define XIP_STREAM_CTR_ACCESS "RW"
+// =============================================================================
+// Register    : XIP_STREAM_FIFO
+// Description : FIFO stream data
+//               Streamed data is buffered here, for retrieval by the system
+//               DMA.
+//               This FIFO can also be accessed via the XIP_AUX slave, to avoid
+//               exposing
+//               the DMA to bus stalls caused by other XIP traffic.
+#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c)
+#define XIP_STREAM_FIFO_BITS   _u(0xffffffff)
+#define XIP_STREAM_FIFO_RESET  _u(0x00000000)
+#define XIP_STREAM_FIFO_MSB    _u(31)
+#define XIP_STREAM_FIFO_LSB    _u(0)
+#define XIP_STREAM_FIFO_ACCESS "RF"
+// =============================================================================
+#endif // HARDWARE_REGS_XIP_DEFINED
diff --git a/src/rp2040/hardware_regs/include/hardware/regs/xosc.h b/src/rp2040/hardware_regs/include/hardware/regs/xosc.h
new file mode 100644
index 0000000..ec84d3d
--- /dev/null
+++ b/src/rp2040/hardware_regs/include/hardware/regs/xosc.h
@@ -0,0 +1,160 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : XOSC
+// Version        : 1
+// Bus type       : apb
+// Description    : Controls the crystal oscillator
+// =============================================================================
+#ifndef HARDWARE_REGS_XOSC_DEFINED
+#define HARDWARE_REGS_XOSC_DEFINED
+// =============================================================================
+// Register    : XOSC_CTRL
+// Description : Crystal Oscillator Control
+#define XOSC_CTRL_OFFSET _u(0x00000000)
+#define XOSC_CTRL_BITS   _u(0x00ffffff)
+#define XOSC_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : XOSC_CTRL_ENABLE
+// Description : On power-up this field is initialised to DISABLE and the chip
+//               runs from the ROSC.
+//               If the chip has subsequently been programmed to run from the
+//               XOSC then setting this field to DISABLE may lock-up the chip.
+//               If this is a concern then run the clk_ref from the ROSC and
+//               enable the clk_sys RESUS feature.
+//               The 12-bit code is intended to give some protection against
+//               accidental writes. An invalid setting will enable the
+//               oscillator.
+//               0xd1e -> DISABLE
+//               0xfab -> ENABLE
+#define XOSC_CTRL_ENABLE_RESET         "-"
+#define XOSC_CTRL_ENABLE_BITS          _u(0x00fff000)
+#define XOSC_CTRL_ENABLE_MSB           _u(23)
+#define XOSC_CTRL_ENABLE_LSB           _u(12)
+#define XOSC_CTRL_ENABLE_ACCESS        "RW"
+#define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
+#define XOSC_CTRL_ENABLE_VALUE_ENABLE  _u(0xfab)
+// -----------------------------------------------------------------------------
+// Field       : XOSC_CTRL_FREQ_RANGE
+// Description : Frequency range. This resets to 0xAA0 and cannot be changed.
+//               0xaa0 -> 1_15MHZ
+//               0xaa1 -> RESERVED_1
+//               0xaa2 -> RESERVED_2
+//               0xaa3 -> RESERVED_3
+#define XOSC_CTRL_FREQ_RANGE_RESET            "-"
+#define XOSC_CTRL_FREQ_RANGE_BITS             _u(0x00000fff)
+#define XOSC_CTRL_FREQ_RANGE_MSB              _u(11)
+#define XOSC_CTRL_FREQ_RANGE_LSB              _u(0)
+#define XOSC_CTRL_FREQ_RANGE_ACCESS           "RW"
+#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ    _u(0xaa0)
+#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 _u(0xaa1)
+#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 _u(0xaa2)
+#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 _u(0xaa3)
+// =============================================================================
+// Register    : XOSC_STATUS
+// Description : Crystal Oscillator Status
+#define XOSC_STATUS_OFFSET _u(0x00000004)
+#define XOSC_STATUS_BITS   _u(0x81001003)
+#define XOSC_STATUS_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : XOSC_STATUS_STABLE
+// Description : Oscillator is running and stable
+#define XOSC_STATUS_STABLE_RESET  _u(0x0)
+#define XOSC_STATUS_STABLE_BITS   _u(0x80000000)
+#define XOSC_STATUS_STABLE_MSB    _u(31)
+#define XOSC_STATUS_STABLE_LSB    _u(31)
+#define XOSC_STATUS_STABLE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : XOSC_STATUS_BADWRITE
+// Description : An invalid value has been written to CTRL_ENABLE or
+//               CTRL_FREQ_RANGE or DORMANT
+#define XOSC_STATUS_BADWRITE_RESET  _u(0x0)
+#define XOSC_STATUS_BADWRITE_BITS   _u(0x01000000)
+#define XOSC_STATUS_BADWRITE_MSB    _u(24)
+#define XOSC_STATUS_BADWRITE_LSB    _u(24)
+#define XOSC_STATUS_BADWRITE_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field       : XOSC_STATUS_ENABLED
+// Description : Oscillator is enabled but not necessarily running and stable,
+//               resets to 0
+#define XOSC_STATUS_ENABLED_RESET  "-"
+#define XOSC_STATUS_ENABLED_BITS   _u(0x00001000)
+#define XOSC_STATUS_ENABLED_MSB    _u(12)
+#define XOSC_STATUS_ENABLED_LSB    _u(12)
+#define XOSC_STATUS_ENABLED_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : XOSC_STATUS_FREQ_RANGE
+// Description : The current frequency range setting, always reads 0
+//               0x0 -> 1_15MHZ
+//               0x1 -> RESERVED_1
+//               0x2 -> RESERVED_2
+//               0x3 -> RESERVED_3
+#define XOSC_STATUS_FREQ_RANGE_RESET            "-"
+#define XOSC_STATUS_FREQ_RANGE_BITS             _u(0x00000003)
+#define XOSC_STATUS_FREQ_RANGE_MSB              _u(1)
+#define XOSC_STATUS_FREQ_RANGE_LSB              _u(0)
+#define XOSC_STATUS_FREQ_RANGE_ACCESS           "RO"
+#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ    _u(0x0)
+#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 _u(0x1)
+#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 _u(0x2)
+#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 _u(0x3)
+// =============================================================================
+// Register    : XOSC_DORMANT
+// Description : Crystal Oscillator pause control
+//               This is used to save power by pausing the XOSC
+//               On power-up this field is initialised to WAKE
+//               An invalid write will also select WAKE
+//               WARNING: stop the PLLs before selecting dormant mode
+//               WARNING: setup the irq before selecting dormant mode
+//               0x636f6d61 -> DORMANT
+//               0x77616b65 -> WAKE
+#define XOSC_DORMANT_OFFSET        _u(0x00000008)
+#define XOSC_DORMANT_BITS          _u(0xffffffff)
+#define XOSC_DORMANT_RESET         "-"
+#define XOSC_DORMANT_MSB           _u(31)
+#define XOSC_DORMANT_LSB           _u(0)
+#define XOSC_DORMANT_ACCESS        "RW"
+#define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
+#define XOSC_DORMANT_VALUE_WAKE    _u(0x77616b65)
+// =============================================================================
+// Register    : XOSC_STARTUP
+// Description : Controls the startup delay
+#define XOSC_STARTUP_OFFSET _u(0x0000000c)
+#define XOSC_STARTUP_BITS   _u(0x00103fff)
+#define XOSC_STARTUP_RESET  _u(0x000000c4)
+// -----------------------------------------------------------------------------
+// Field       : XOSC_STARTUP_X4
+// Description : Multiplies the startup_delay by 4. This is of little value to
+//               the user given that the delay can be programmed directly.
+#define XOSC_STARTUP_X4_RESET  _u(0x0)
+#define XOSC_STARTUP_X4_BITS   _u(0x00100000)
+#define XOSC_STARTUP_X4_MSB    _u(20)
+#define XOSC_STARTUP_X4_LSB    _u(20)
+#define XOSC_STARTUP_X4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : XOSC_STARTUP_DELAY
+// Description : in multiples of 256*xtal_period. The reset value of 0xc4
+//               corresponds to approx 50 000 cycles.
+#define XOSC_STARTUP_DELAY_RESET  _u(0x00c4)
+#define XOSC_STARTUP_DELAY_BITS   _u(0x00003fff)
+#define XOSC_STARTUP_DELAY_MSB    _u(13)
+#define XOSC_STARTUP_DELAY_LSB    _u(0)
+#define XOSC_STARTUP_DELAY_ACCESS "RW"
+// =============================================================================
+// Register    : XOSC_COUNT
+// Description : A down counter running at the xosc frequency which counts to
+//               zero and stops.
+//               To start the counter write a non-zero value.
+//               Can be used for short software pauses when setting up time
+//               sensitive hardware.
+#define XOSC_COUNT_OFFSET _u(0x0000001c)
+#define XOSC_COUNT_BITS   _u(0x000000ff)
+#define XOSC_COUNT_RESET  _u(0x00000000)
+#define XOSC_COUNT_MSB    _u(7)
+#define XOSC_COUNT_LSB    _u(0)
+#define XOSC_COUNT_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_XOSC_DEFINED
diff --git a/src/rp2040/hardware_regs/rp2040.svd b/src/rp2040/hardware_regs/rp2040.svd
new file mode 100644
index 0000000..52da2c0
--- /dev/null
+++ b/src/rp2040/hardware_regs/rp2040.svd
@@ -0,0 +1,46397 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--
+  Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+
+  SPDX-License-Identifier: BSD-3-Clause
+-->
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+  <addressUnitBits>8</addressUnitBits>
+  <vendor>Raspberry Pi</vendor>
+  <name>RP2040</name>
+  <licenseText>
+    Copyright (c) 2020 Raspberry Pi (Trading) Ltd. \n
+    \n
+    SPDX-License-Identifier: BSD-3-Clause
+  </licenseText>
+  <version>0.1</version>
+  <width>32</width>
+  <cpu>
+    <name>CM0PLUS</name>
+    <revision>r0p1</revision>
+    <endian>little</endian>
+    <mpuPresent>true</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <nvicPrioBits>2</nvicPrioBits>
+    <vtorPresent>1</vtorPresent>
+    <vendorSystickConfig>false</vendorSystickConfig>
+    <deviceNumInterrupts>26</deviceNumInterrupts>
+  </cpu>
+  <peripherals>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x0020</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x14000000</baseAddress>
+      <description>QSPI flash execute-in-place block</description>
+      <interrupt>
+        <name>XIP_IRQ</name>
+        <value>6</value>
+      </interrupt>
+      <name>XIP_CTRL</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Cache control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>When 1, the cache memories are powered down. They retain state,\n
+                but can not be accessed. This reduces static power dissipation.\n
+                Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n
+                be enabled when powered down.\n
+                Cache-as-SRAM accesses will produce a bus error response when\n
+                the cache is powered down.</description>
+              <name>POWER_DOWN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>When 1, writes to any alias other than 0x0 (caching, allocating)\n
+                will produce a bus fault. When 0, these writes are silently ignored.\n
+                In either case, writes to the 0x0 alias will deallocate on tag match,\n
+                as usual.</description>
+              <name>ERR_BADWRITE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>When 1, enable the cache. When the cache is disabled, all XIP accesses\n
+                will go straight to the flash, without querying the cache. When enabled,\n
+                cacheable XIP accesses will query the cache, and the flash will\n
+                not be accessed if the tag matches and the valid bit is set.\n\n
+                If the cache is enabled, cache-as-SRAM accesses have no effect on the\n
+                cache data RAM, and will produce a bus error response.</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CTRL</name>
+          <resetValue>0x00000003</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Cache Flush control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Write 1 to flush the cache. This clears the tag memory, but\n
+                the data memory retains its contents. (This means cache-as-SRAM\n
+                contents is not affected by flush or reset.)\n
+                Reading will hold the bus (stall the processor) until the flush\n
+                completes. Alternatively STAT can be polled until completion.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>FLUSH</name>
+            </field>
+          </fields>
+          <name>FLUSH</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>Cache Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>When 1, indicates the XIP streaming FIFO is completely full.\n
+                The streaming FIFO is 2 entries deep, so the full and empty\n
+                flag allow its level to be ascertained.</description>
+              <name>FIFO_FULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>When 1, indicates the XIP streaming FIFO is completely empty.</description>
+              <name>FIFO_EMPTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Reads as 0 while a cache flush is in progress, and 1 otherwise.\n
+                The cache is flushed whenever the XIP block is reset, and also\n
+                when requested via the FLUSH register.</description>
+              <name>FLUSH_READY</name>
+            </field>
+          </fields>
+          <name>STAT</name>
+          <resetValue>0x00000002</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x000c</addressOffset>
+          <description>Cache Hit counter\n
+            A 32 bit saturating counter that increments upon each cache hit,\n
+            i.e. when an XIP access is serviced directly from cached data.\n
+            Write any value to clear.</description>
+          <modifiedWriteValues>oneToClear</modifiedWriteValues>
+          <name>CTR_HIT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0010</addressOffset>
+          <description>Cache Access counter\n
+            A 32 bit saturating counter that increments upon each XIP access,\n
+            whether the cache is hit or not. This includes noncacheable accesses.\n
+            Write any value to clear.</description>
+          <modifiedWriteValues>oneToClear</modifiedWriteValues>
+          <name>CTR_ACC</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>FIFO stream address</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:2]</bitRange>
+              <description>The address of the next word to be streamed from flash to the streaming FIFO.\n
+                Increments automatically after each flash access.\n
+                Write the initial access address here before starting a streaming read.</description>
+              <name>STREAM_ADDR</name>
+            </field>
+          </fields>
+          <name>STREAM_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>FIFO stream control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:0]</bitRange>
+              <description>Write a nonzero value to start a streaming read. This will then\n
+                progress in the background, using flash idle cycles to transfer\n
+                a linear data block from flash to the streaming FIFO.\n
+                Decrements automatically (1 at a time) as the stream\n
+                progresses, and halts on reaching 0.\n
+                Write 0 to halt an in-progress stream, and discard any in-flight\n
+                read, so that a new stream can immediately be started (after\n
+                draining the FIFO and reinitialising STREAM_ADDR)</description>
+              <name>STREAM_CTR</name>
+            </field>
+          </fields>
+          <name>STREAM_CTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x001c</addressOffset>
+          <description>FIFO stream data\n
+            Streamed data is buffered here, for retrieval by the system DMA.\n
+            This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n
+            the DMA to bus stalls caused by other XIP traffic.</description>
+          <name>STREAM_FIFO</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x0100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x18000000</baseAddress>
+      <description>DW_apb_ssi has the following features:\n
+        * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n
+        * APB3 and APB4 protocol support.\n
+        * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.\n
+        * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.\n
+        * Programmable Dual/Quad/Octal SPI support in Master Mode.\n
+        * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n
+        * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n
+        * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n
+        * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n
+        * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n
+        * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.\n
+        * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n
+        * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n
+        * Programmable features:\n
+        - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n
+        - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n
+        - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.\n
+        * Configured features:\n
+        - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\n
+        - 1 slave select output.\n
+        - Hardware slave-select – Dedicated hardware slave-select line.\n
+        - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n
+        - Interrupt polarity – active high interrupt lines.\n
+        - Serial clock polarity – low serial-clock polarity directly after reset.\n
+        - Serial clock phase – capture on first edge of serial-clock directly after reset.</description>
+      <name>XIP_SSI</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Control register 0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <description>Slave select toggle enable</description>
+              <name>SSTE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:21]</bitRange>
+              <description>SPI frame format</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex</description>
+                  <name>STD</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Dual-SPI frame format; two bits per SCK, half-duplex</description>
+                  <name>DUAL</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Quad-SPI frame format; four bits per SCK, half-duplex</description>
+                  <name>QUAD</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>SPI_FRF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:16]</bitRange>
+              <description>Data frame size in 32b transfer mode\n
+                Value of n -&gt; n+1 clocks per frame.</description>
+              <name>DFS_32</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:12]</bitRange>
+              <description>Control frame size\n
+                Value of n -&gt; n+1 clocks per frame.</description>
+              <name>CFS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Shift register loop (test mode)</description>
+              <name>SRL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Slave output enable</description>
+              <name>SLV_OE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <description>Transfer mode</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Both transmit and receive</description>
+                  <name>TX_AND_RX</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Transmit only (not for FRF == 0, standard SPI mode)</description>
+                  <name>TX_ONLY</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Receive only (not for FRF == 0, standard SPI mode)</description>
+                  <name>RX_ONLY</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>EEPROM read mode (TX then RX; RX starts after control data TX'd)</description>
+                  <name>EEPROM_READ</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TMOD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Serial clock polarity</description>
+              <name>SCPOL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Serial clock phase</description>
+              <name>SCPH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Frame format</description>
+              <name>FRF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <description>Data frame size</description>
+              <name>DFS</name>
+            </field>
+          </fields>
+          <name>CTRLR0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Master Control register 1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Number of data frames</description>
+              <name>NDF</name>
+            </field>
+          </fields>
+          <name>CTRLR1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>SSI Enable</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>SSI enable</description>
+              <name>SSI_EN</name>
+            </field>
+          </fields>
+          <name>SSIENR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>Microwire Control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Microwire handshaking</description>
+              <name>MHS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Microwire control</description>
+              <name>MDD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Microwire transfer mode</description>
+              <name>MWMOD</name>
+            </field>
+          </fields>
+          <name>MWCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>Slave enable</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>For each bit:\n
+                0 -&gt; slave not selected\n
+                1 -&gt; slave selected</description>
+              <name>SER</name>
+            </field>
+          </fields>
+          <name>SER</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>Baud rate</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>SSI clock divider</description>
+              <name>SCKDV</name>
+            </field>
+          </fields>
+          <name>BAUDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>TX FIFO threshold level</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Transmit FIFO threshold</description>
+              <name>TFT</name>
+            </field>
+          </fields>
+          <name>TXFTLR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>RX FIFO threshold level</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Receive FIFO threshold</description>
+              <name>RFT</name>
+            </field>
+          </fields>
+          <name>RXFTLR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>TX FIFO level</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Transmit FIFO level</description>
+              <name>TFTFL</name>
+            </field>
+          </fields>
+          <name>TXFLR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0024</addressOffset>
+          <description>RX FIFO level</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Receive FIFO level</description>
+              <name>RXTFL</name>
+            </field>
+          </fields>
+          <name>RXFLR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0028</addressOffset>
+          <description>Status register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Data collision error</description>
+              <name>DCOL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Transmission error</description>
+              <name>TXE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Receive FIFO full</description>
+              <name>RFF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Receive FIFO not empty</description>
+              <name>RFNE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Transmit FIFO empty</description>
+              <name>TFE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Transmit FIFO not full</description>
+              <name>TFNF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>SSI busy flag</description>
+              <name>BUSY</name>
+            </field>
+          </fields>
+          <name>SR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x002c</addressOffset>
+          <description>Interrupt mask</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Multi-master contention interrupt mask</description>
+              <name>MSTIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Receive FIFO full interrupt mask</description>
+              <name>RXFIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Receive FIFO overflow interrupt mask</description>
+              <name>RXOIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Receive FIFO underflow interrupt mask</description>
+              <name>RXUIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Transmit FIFO overflow interrupt mask</description>
+              <name>TXOIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Transmit FIFO empty interrupt mask</description>
+              <name>TXEIM</name>
+            </field>
+          </fields>
+          <name>IMR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0030</addressOffset>
+          <description>Interrupt status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Multi-master contention interrupt status</description>
+              <name>MSTIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Receive FIFO full interrupt status</description>
+              <name>RXFIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Receive FIFO overflow interrupt status</description>
+              <name>RXOIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Receive FIFO underflow interrupt status</description>
+              <name>RXUIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Transmit FIFO overflow interrupt status</description>
+              <name>TXOIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Transmit FIFO empty interrupt status</description>
+              <name>TXEIS</name>
+            </field>
+          </fields>
+          <name>ISR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0034</addressOffset>
+          <description>Raw interrupt status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Multi-master contention raw interrupt status</description>
+              <name>MSTIR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Receive FIFO full raw interrupt status</description>
+              <name>RXFIR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Receive FIFO overflow raw interrupt status</description>
+              <name>RXOIR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Receive FIFO underflow raw interrupt status</description>
+              <name>RXUIR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Transmit FIFO overflow raw interrupt status</description>
+              <name>TXOIR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Transmit FIFO empty raw interrupt status</description>
+              <name>TXEIR</name>
+            </field>
+          </fields>
+          <name>RISR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0038</addressOffset>
+          <description>TX FIFO overflow interrupt clear</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Clear-on-read transmit FIFO overflow interrupt</description>
+              <name>TXOICR</name>
+            </field>
+          </fields>
+          <name>TXOICR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x003c</addressOffset>
+          <description>RX FIFO overflow interrupt clear</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Clear-on-read receive FIFO overflow interrupt</description>
+              <name>RXOICR</name>
+            </field>
+          </fields>
+          <name>RXOICR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0040</addressOffset>
+          <description>RX FIFO underflow interrupt clear</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Clear-on-read receive FIFO underflow interrupt</description>
+              <name>RXUICR</name>
+            </field>
+          </fields>
+          <name>RXUICR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0044</addressOffset>
+          <description>Multi-master interrupt clear</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Clear-on-read multi-master contention interrupt</description>
+              <name>MSTICR</name>
+            </field>
+          </fields>
+          <name>MSTICR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0048</addressOffset>
+          <description>Interrupt clear</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Clear-on-read all active interrupts</description>
+              <name>ICR</name>
+            </field>
+          </fields>
+          <name>ICR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x004c</addressOffset>
+          <description>DMA control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Transmit DMA enable</description>
+              <name>TDMAE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Receive DMA enable</description>
+              <name>RDMAE</name>
+            </field>
+          </fields>
+          <name>DMACR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0050</addressOffset>
+          <description>DMA TX data level</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Transmit data watermark level</description>
+              <name>DMATDL</name>
+            </field>
+          </fields>
+          <name>DMATDLR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0054</addressOffset>
+          <description>DMA RX data level</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Receive data watermark level (DMARDLR+1)</description>
+              <name>DMARDL</name>
+            </field>
+          </fields>
+          <name>DMARDLR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0058</addressOffset>
+          <description>Identification register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:0]</bitRange>
+              <description>Peripheral dentification code</description>
+              <name>IDCODE</name>
+            </field>
+          </fields>
+          <name>IDR</name>
+          <resetValue>0x51535049</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x005c</addressOffset>
+          <description>Version ID</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:0]</bitRange>
+              <description>SNPS component version (format X.YY)</description>
+              <name>SSI_COMP_VERSION</name>
+            </field>
+          </fields>
+          <name>SSI_VERSION_ID</name>
+          <resetValue>0x3430312a</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0060</addressOffset>
+          <description>Data Register 0 (of 36)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:0]</bitRange>
+              <description>First data register of 36</description>
+              <name>DR</name>
+            </field>
+          </fields>
+          <name>DR0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f0</addressOffset>
+          <description>RX sample delay</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>RXD sample delay (in SCLK cycles)</description>
+              <name>RSD</name>
+            </field>
+          </fields>
+          <name>RX_SAMPLE_DLY</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f4</addressOffset>
+          <description>SPI control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:24]</bitRange>
+              <description>SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)</description>
+              <name>XIP_CMD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>Read data strobe enable</description>
+              <name>SPI_RXDS_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Instruction DDR transfer enable</description>
+              <name>INST_DDR_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>SPI DDR transfer enable</description>
+              <name>SPI_DDR_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:11]</bitRange>
+              <description>Wait cycles between control frame transmit and data reception (in SCLK cycles)</description>
+              <name>WAIT_CYCLES</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <description>Instruction length (0/4/8/16b)</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>No instruction</description>
+                  <name>NONE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>4-bit instruction</description>
+                  <name>4B</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>8-bit instruction</description>
+                  <name>8B</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>16-bit instruction</description>
+                  <name>16B</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INST_L</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:2]</bitRange>
+              <description>Address length (0b-60b in 4b increments)</description>
+              <name>ADDR_L</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:0]</bitRange>
+              <description>Address and instruction transfer format</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Command and address both in standard SPI frame format</description>
+                  <name>1C1A</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Command in standard SPI format, address in format specified by FRF</description>
+                  <name>1C2A</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Command and address both in format specified by FRF (e.g. Dual-SPI)</description>
+                  <name>2C2A</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TRANS_TYPE</name>
+            </field>
+          </fields>
+          <name>SPI_CTRLR0</name>
+          <resetValue>0x03000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f8</addressOffset>
+          <description>TX drive edge</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>TXD drive edge</description>
+              <name>TDE</name>
+            </field>
+          </fields>
+          <name>TXD_DRIVE_EDGE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40000000</baseAddress>
+      <name>SYSINFO</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>JEDEC JEP-106 compliant chip identifier.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:28]</bitRange>
+              <name>REVISION</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[27:12]</bitRange>
+              <name>PART</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:0]</bitRange>
+              <name>MANUFACTURER</name>
+            </field>
+          </fields>
+          <name>CHIP_ID</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Platform register. Allows software to know what environment it is running in.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>ASIC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>FPGA</name>
+            </field>
+          </fields>
+          <name>PLATFORM</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0040</addressOffset>
+          <description>Git hash of the chip source. Used to identify chip version.</description>
+          <name>GITREF_RP2040</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40004000</baseAddress>
+      <description>Register block for various chip control signals</description>
+      <name>SYSCFG</name>
+      <registers>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0000</addressOffset>
+          <description>Processor core 0 NMI source mask\n
+            Set a bit high to enable NMI from that IRQ</description>
+          <name>PROC0_NMI_MASK</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0004</addressOffset>
+          <description>Processor core 1 NMI source mask\n
+            Set a bit high to enable NMI from that IRQ</description>
+          <name>PROC1_NMI_MASK</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>Configuration for processors</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:28]</bitRange>
+              <description>Configure proc1 DAP instance ID.\n
+                Recommend that this is NOT changed until you require debug access in multi-chip environment\n
+                WARNING: do not set to 15 as this is reserved for RescueDP</description>
+              <name>PROC1_DAP_INSTID</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:24]</bitRange>
+              <description>Configure proc0 DAP instance ID.\n
+                Recommend that this is NOT changed until you require debug access in multi-chip environment\n
+                WARNING: do not set to 15 as this is reserved for RescueDP</description>
+              <name>PROC0_DAP_INSTID</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Indication that proc1 has halted</description>
+              <name>PROC1_HALTED</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Indication that proc0 has halted</description>
+              <name>PROC0_HALTED</name>
+            </field>
+          </fields>
+          <name>PROC_CONFIG</name>
+          <resetValue>0x10000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>For each bit, if 1, bypass the input synchronizer between that GPIO\n
+            and the GPIO input register in the SIO. The input synchronizers should\n
+            generally be unbypassed, to avoid injecting metastabilities into processors.\n
+            If you're feeling brave, you can bypass to save two cycles of input\n
+            latency. This register applies to GPIO 0...29.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:0]</bitRange>
+              <name>PROC_IN_SYNC_BYPASS</name>
+            </field>
+          </fields>
+          <name>PROC_IN_SYNC_BYPASS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>For each bit, if 1, bypass the input synchronizer between that GPIO\n
+            and the GPIO input register in the SIO. The input synchronizers should\n
+            generally be unbypassed, to avoid injecting metastabilities into processors.\n
+            If you're feeling brave, you can bypass to save two cycles of input\n
+            latency. This register applies to GPIO 30...35 (the QSPI IOs).</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <name>PROC_IN_SYNC_BYPASS_HI</name>
+            </field>
+          </fields>
+          <name>PROC_IN_SYNC_BYPASS_HI</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>Directly control the SWD debug port of either processor</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads.</description>
+              <name>PROC1_ATTACH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Directly drive processor 1 SWCLK, if PROC1_ATTACH is set</description>
+              <name>PROC1_SWCLK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set</description>
+              <name>PROC1_SWDI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Observe the value of processor 1 SWDIO output.</description>
+              <name>PROC1_SWDO</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads.</description>
+              <name>PROC0_ATTACH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Directly drive processor 0 SWCLK, if PROC0_ATTACH is set</description>
+              <name>PROC0_SWCLK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set</description>
+              <name>PROC0_SWDI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Observe the value of processor 0 SWDIO output.</description>
+              <name>PROC0_SWDO</name>
+            </field>
+          </fields>
+          <name>DBGFORCE</name>
+          <resetValue>0x00000066</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>Control power downs to memories. Set high to power down memories.\n
+            Use with extreme caution</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>ROM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>USB</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>SRAM5</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>SRAM4</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>SRAM3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>SRAM2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>SRAM1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>SRAM0</name>
+            </field>
+          </fields>
+          <name>MEMPOWERDOWN</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40008000</baseAddress>
+      <interrupt>
+        <name>CLOCKS_IRQ</name>
+        <value>17</value>
+      </interrupt>
+      <name>CLOCKS</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
+                This can be done at any time</description>
+              <name>NUDGE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <description>This delays the enable signal by up to 3 cycles of the input clock\n
+                This must be set before the clock is enabled to have any effect</description>
+              <name>PHASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Enables duty cycle correction for odd divisors</description>
+              <name>DC50</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Starts and stops the clock generator cleanly</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Asynchronously kills the clock generator</description>
+              <name>KILL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:5]</bitRange>
+              <description>Selects the auxiliary clock source, will glitch when switching</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>clksrc_pll_sys</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin0</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin1</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_pll_usb</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rosc_clksrc</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xosc_clksrc</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_sys</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_usb</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_adc</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_rtc</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_ref</name>
+                  <value>10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>AUXSRC</name>
+            </field>
+          </fields>
+          <name>CLK_GPOUT0_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Clock divisor, can be changed on-the-fly</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:8]</bitRange>
+              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Fractional component of the divisor</description>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>CLK_GPOUT0_DIV</name>
+          <resetValue>0x00000100</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0008</addressOffset>
+          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
+            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+          <name>CLK_GPOUT0_SELECTED</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
+                This can be done at any time</description>
+              <name>NUDGE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <description>This delays the enable signal by up to 3 cycles of the input clock\n
+                This must be set before the clock is enabled to have any effect</description>
+              <name>PHASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Enables duty cycle correction for odd divisors</description>
+              <name>DC50</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Starts and stops the clock generator cleanly</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Asynchronously kills the clock generator</description>
+              <name>KILL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:5]</bitRange>
+              <description>Selects the auxiliary clock source, will glitch when switching</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>clksrc_pll_sys</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin0</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin1</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_pll_usb</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rosc_clksrc</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xosc_clksrc</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_sys</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_usb</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_adc</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_rtc</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_ref</name>
+                  <value>10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>AUXSRC</name>
+            </field>
+          </fields>
+          <name>CLK_GPOUT1_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>Clock divisor, can be changed on-the-fly</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:8]</bitRange>
+              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Fractional component of the divisor</description>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>CLK_GPOUT1_DIV</name>
+          <resetValue>0x00000100</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0014</addressOffset>
+          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
+            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+          <name>CLK_GPOUT1_SELECTED</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
+                This can be done at any time</description>
+              <name>NUDGE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <description>This delays the enable signal by up to 3 cycles of the input clock\n
+                This must be set before the clock is enabled to have any effect</description>
+              <name>PHASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Enables duty cycle correction for odd divisors</description>
+              <name>DC50</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Starts and stops the clock generator cleanly</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Asynchronously kills the clock generator</description>
+              <name>KILL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:5]</bitRange>
+              <description>Selects the auxiliary clock source, will glitch when switching</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>clksrc_pll_sys</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin0</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin1</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_pll_usb</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rosc_clksrc_ph</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xosc_clksrc</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_sys</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_usb</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_adc</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_rtc</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_ref</name>
+                  <value>10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>AUXSRC</name>
+            </field>
+          </fields>
+          <name>CLK_GPOUT2_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>Clock divisor, can be changed on-the-fly</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:8]</bitRange>
+              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Fractional component of the divisor</description>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>CLK_GPOUT2_DIV</name>
+          <resetValue>0x00000100</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0020</addressOffset>
+          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
+            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+          <name>CLK_GPOUT2_SELECTED</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0024</addressOffset>
+          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
+                This can be done at any time</description>
+              <name>NUDGE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <description>This delays the enable signal by up to 3 cycles of the input clock\n
+                This must be set before the clock is enabled to have any effect</description>
+              <name>PHASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Enables duty cycle correction for odd divisors</description>
+              <name>DC50</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Starts and stops the clock generator cleanly</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Asynchronously kills the clock generator</description>
+              <name>KILL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:5]</bitRange>
+              <description>Selects the auxiliary clock source, will glitch when switching</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>clksrc_pll_sys</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin0</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin1</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_pll_usb</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rosc_clksrc_ph</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xosc_clksrc</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_sys</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_usb</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_adc</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_rtc</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_ref</name>
+                  <value>10</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>AUXSRC</name>
+            </field>
+          </fields>
+          <name>CLK_GPOUT3_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0028</addressOffset>
+          <description>Clock divisor, can be changed on-the-fly</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:8]</bitRange>
+              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Fractional component of the divisor</description>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>CLK_GPOUT3_DIV</name>
+          <resetValue>0x00000100</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x002c</addressOffset>
+          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
+            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+          <name>CLK_GPOUT3_SELECTED</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0030</addressOffset>
+          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:5]</bitRange>
+              <description>Selects the auxiliary clock source, will glitch when switching</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>clksrc_pll_usb</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin0</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin1</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>AUXSRC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:0]</bitRange>
+              <description>Selects the clock source glitchlessly, can be changed on-the-fly</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>rosc_clksrc_ph</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_clk_ref_aux</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xosc_clksrc</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>SRC</name>
+            </field>
+          </fields>
+          <name>CLK_REF_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0034</addressOffset>
+          <description>Clock divisor, can be changed on-the-fly</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+              <name>INT</name>
+            </field>
+          </fields>
+          <name>CLK_REF_DIV</name>
+          <resetValue>0x00000100</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0038</addressOffset>
+          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
+            The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</description>
+          <name>CLK_REF_SELECTED</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x003c</addressOffset>
+          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:5]</bitRange>
+              <description>Selects the auxiliary clock source, will glitch when switching</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>clksrc_pll_sys</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_pll_usb</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rosc_clksrc</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xosc_clksrc</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin0</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin1</name>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>AUXSRC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Selects the clock source glitchlessly, can be changed on-the-fly</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>clk_ref</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_clk_sys_aux</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>SRC</name>
+            </field>
+          </fields>
+          <name>CLK_SYS_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0040</addressOffset>
+          <description>Clock divisor, can be changed on-the-fly</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:8]</bitRange>
+              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Fractional component of the divisor</description>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>CLK_SYS_DIV</name>
+          <resetValue>0x00000100</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0044</addressOffset>
+          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
+            The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</description>
+          <name>CLK_SYS_SELECTED</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0048</addressOffset>
+          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Starts and stops the clock generator cleanly</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Asynchronously kills the clock generator</description>
+              <name>KILL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:5]</bitRange>
+              <description>Selects the auxiliary clock source, will glitch when switching</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>clk_sys</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_pll_sys</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_pll_usb</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rosc_clksrc_ph</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xosc_clksrc</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin0</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin1</name>
+                  <value>6</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>AUXSRC</name>
+            </field>
+          </fields>
+          <name>CLK_PERI_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0050</addressOffset>
+          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
+            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+          <name>CLK_PERI_SELECTED</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0054</addressOffset>
+          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
+                This can be done at any time</description>
+              <name>NUDGE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <description>This delays the enable signal by up to 3 cycles of the input clock\n
+                This must be set before the clock is enabled to have any effect</description>
+              <name>PHASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Starts and stops the clock generator cleanly</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Asynchronously kills the clock generator</description>
+              <name>KILL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:5]</bitRange>
+              <description>Selects the auxiliary clock source, will glitch when switching</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>clksrc_pll_usb</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_pll_sys</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rosc_clksrc_ph</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xosc_clksrc</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin0</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin1</name>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>AUXSRC</name>
+            </field>
+          </fields>
+          <name>CLK_USB_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0058</addressOffset>
+          <description>Clock divisor, can be changed on-the-fly</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+              <name>INT</name>
+            </field>
+          </fields>
+          <name>CLK_USB_DIV</name>
+          <resetValue>0x00000100</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x005c</addressOffset>
+          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
+            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+          <name>CLK_USB_SELECTED</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0060</addressOffset>
+          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
+                This can be done at any time</description>
+              <name>NUDGE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <description>This delays the enable signal by up to 3 cycles of the input clock\n
+                This must be set before the clock is enabled to have any effect</description>
+              <name>PHASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Starts and stops the clock generator cleanly</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Asynchronously kills the clock generator</description>
+              <name>KILL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:5]</bitRange>
+              <description>Selects the auxiliary clock source, will glitch when switching</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>clksrc_pll_usb</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_pll_sys</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rosc_clksrc_ph</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xosc_clksrc</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin0</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin1</name>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>AUXSRC</name>
+            </field>
+          </fields>
+          <name>CLK_ADC_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0064</addressOffset>
+          <description>Clock divisor, can be changed on-the-fly</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+              <name>INT</name>
+            </field>
+          </fields>
+          <name>CLK_ADC_DIV</name>
+          <resetValue>0x00000100</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0068</addressOffset>
+          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
+            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+          <name>CLK_ADC_SELECTED</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x006c</addressOffset>
+          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
+                This can be done at any time</description>
+              <name>NUDGE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <description>This delays the enable signal by up to 3 cycles of the input clock\n
+                This must be set before the clock is enabled to have any effect</description>
+              <name>PHASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Starts and stops the clock generator cleanly</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Asynchronously kills the clock generator</description>
+              <name>KILL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:5]</bitRange>
+              <description>Selects the auxiliary clock source, will glitch when switching</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>clksrc_pll_usb</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_pll_sys</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rosc_clksrc_ph</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xosc_clksrc</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin0</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin1</name>
+                  <value>5</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>AUXSRC</name>
+            </field>
+          </fields>
+          <name>CLK_RTC_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0070</addressOffset>
+          <description>Clock divisor, can be changed on-the-fly</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:8]</bitRange>
+              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Fractional component of the divisor</description>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>CLK_RTC_DIV</name>
+          <resetValue>0x00000100</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0074</addressOffset>
+          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
+            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
+          <name>CLK_RTC_SELECTED</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0078</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>For clearing the resus after the fault that triggered it has been corrected</description>
+              <name>CLEAR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Force a resus, for test purposes only</description>
+              <name>FRCE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Enable resus</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>This is expressed as a number of clk_ref cycles\n
+                and must be &gt;= 2x clk_ref_freq/min_clk_tst_freq</description>
+              <name>TIMEOUT</name>
+            </field>
+          </fields>
+          <name>CLK_SYS_RESUS_CTRL</name>
+          <resetValue>0x000000ff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x007c</addressOffset>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Clock has been resuscitated, correct the error then send ctrl_clear=1</description>
+              <name>RESUSSED</name>
+            </field>
+          </fields>
+          <name>CLK_SYS_RESUS_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0080</addressOffset>
+          <description>Reference clock frequency in kHz</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:0]</bitRange>
+              <name>FC0_REF_KHZ</name>
+            </field>
+          </fields>
+          <name>FC0_REF_KHZ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0084</addressOffset>
+          <description>Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:0]</bitRange>
+              <name>FC0_MIN_KHZ</name>
+            </field>
+          </fields>
+          <name>FC0_MIN_KHZ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0088</addressOffset>
+          <description>Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:0]</bitRange>
+              <name>FC0_MAX_KHZ</name>
+            </field>
+          </fields>
+          <name>FC0_MAX_KHZ</name>
+          <resetValue>0x01ffffff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x008c</addressOffset>
+          <description>Delays the start of frequency counting to allow the mux to settle\n
+            Delay is measured in multiples of the reference clock period</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:0]</bitRange>
+              <name>FC0_DELAY</name>
+            </field>
+          </fields>
+          <name>FC0_DELAY</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0090</addressOffset>
+          <description>The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\n
+            The default gives a test interval of 250us</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <name>FC0_INTERVAL</name>
+            </field>
+          </fields>
+          <name>FC0_INTERVAL</name>
+          <resetValue>0x00000008</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0094</addressOffset>
+          <description>Clock sent to frequency counter, set to 0 when not required\n
+            Writing to this register initiates the frequency count</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NULL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pll_sys_clksrc_primary</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pll_usb_clksrc_primary</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rosc_clksrc</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rosc_clksrc_ph</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xosc_clksrc</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin0</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clksrc_gpin1</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_ref</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_sys</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_peri</name>
+                  <value>10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_usb</name>
+                  <value>11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_adc</name>
+                  <value>12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clk_rtc</name>
+                  <value>13</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FC0_SRC</name>
+            </field>
+          </fields>
+          <name>FC0_SRC</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0098</addressOffset>
+          <description>Frequency counter status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Test clock stopped during test</description>
+              <name>DIED</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>Test clock faster than expected, only valid when status_done=1</description>
+              <name>FAST</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <description>Test clock slower than expected, only valid when status_done=1</description>
+              <name>SLOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Test failed</description>
+              <name>FAIL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Waiting for test clock to start</description>
+              <name>WAITING</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Test running</description>
+              <name>RUNNING</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Test complete</description>
+              <name>DONE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Test passed</description>
+              <name>PASS</name>
+            </field>
+          </fields>
+          <name>FC0_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x009c</addressOffset>
+          <description>Result of frequency measurement, only valid when status_done=1</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:5]</bitRange>
+              <name>KHZ</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:0]</bitRange>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>FC0_RESULT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a0</addressOffset>
+          <description>enable clock in wake mode</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>clk_sys_sram3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>clk_sys_sram2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>clk_sys_sram1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>clk_sys_sram0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>clk_sys_spi1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>clk_peri_spi1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>clk_sys_spi0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>clk_peri_spi0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>clk_sys_sio</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>clk_sys_rtc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>clk_rtc_rtc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>clk_sys_rosc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>clk_sys_rom</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>clk_sys_resets</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>clk_sys_pwm</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>clk_sys_psm</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>clk_sys_pll_usb</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>clk_sys_pll_sys</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>clk_sys_pio1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>clk_sys_pio0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>clk_sys_pads</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>clk_sys_vreg_and_chip_reset</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>clk_sys_jtag</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>clk_sys_io</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>clk_sys_i2c1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>clk_sys_i2c0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>clk_sys_dma</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>clk_sys_busfabric</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>clk_sys_busctrl</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>clk_sys_adc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>clk_adc_adc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>clk_sys_clocks</name>
+            </field>
+          </fields>
+          <name>WAKE_EN0</name>
+          <resetValue>0xffffffff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a4</addressOffset>
+          <description>enable clock in wake mode</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>clk_sys_xosc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>clk_sys_xip</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>clk_sys_watchdog</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>clk_usb_usbctrl</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>clk_sys_usbctrl</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>clk_sys_uart1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>clk_peri_uart1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>clk_sys_uart0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>clk_peri_uart0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>clk_sys_timer</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>clk_sys_tbman</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>clk_sys_sysinfo</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>clk_sys_syscfg</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>clk_sys_sram5</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>clk_sys_sram4</name>
+            </field>
+          </fields>
+          <name>WAKE_EN1</name>
+          <resetValue>0x00007fff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a8</addressOffset>
+          <description>enable clock in sleep mode</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>clk_sys_sram3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>clk_sys_sram2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>clk_sys_sram1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>clk_sys_sram0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>clk_sys_spi1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>clk_peri_spi1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>clk_sys_spi0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>clk_peri_spi0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>clk_sys_sio</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>clk_sys_rtc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>clk_rtc_rtc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>clk_sys_rosc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>clk_sys_rom</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>clk_sys_resets</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>clk_sys_pwm</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>clk_sys_psm</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>clk_sys_pll_usb</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>clk_sys_pll_sys</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>clk_sys_pio1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>clk_sys_pio0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>clk_sys_pads</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>clk_sys_vreg_and_chip_reset</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>clk_sys_jtag</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>clk_sys_io</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>clk_sys_i2c1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>clk_sys_i2c0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>clk_sys_dma</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>clk_sys_busfabric</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>clk_sys_busctrl</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>clk_sys_adc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>clk_adc_adc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>clk_sys_clocks</name>
+            </field>
+          </fields>
+          <name>SLEEP_EN0</name>
+          <resetValue>0xffffffff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00ac</addressOffset>
+          <description>enable clock in sleep mode</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>clk_sys_xosc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>clk_sys_xip</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>clk_sys_watchdog</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>clk_usb_usbctrl</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>clk_sys_usbctrl</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>clk_sys_uart1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>clk_peri_uart1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>clk_sys_uart0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>clk_peri_uart0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>clk_sys_timer</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>clk_sys_tbman</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>clk_sys_sysinfo</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>clk_sys_syscfg</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>clk_sys_sram5</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>clk_sys_sram4</name>
+            </field>
+          </fields>
+          <name>SLEEP_EN1</name>
+          <resetValue>0x00007fff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b0</addressOffset>
+          <description>indicates the state of the clock enable</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <name>clk_sys_sram3</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[30:30]</bitRange>
+              <name>clk_sys_sram2</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>clk_sys_sram1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <name>clk_sys_sram0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[27:27]</bitRange>
+              <name>clk_sys_spi1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <name>clk_peri_spi1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <name>clk_sys_spi0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>clk_peri_spi0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>clk_sys_sio</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>clk_sys_rtc</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>clk_rtc_rtc</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>clk_sys_rosc</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>clk_sys_rom</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>clk_sys_resets</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>clk_sys_pwm</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>clk_sys_psm</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>clk_sys_pll_usb</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>clk_sys_pll_sys</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>clk_sys_pio1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>clk_sys_pio0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>clk_sys_pads</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>clk_sys_vreg_and_chip_reset</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>clk_sys_jtag</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>clk_sys_io</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>clk_sys_i2c1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>clk_sys_i2c0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>clk_sys_dma</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>clk_sys_busfabric</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>clk_sys_busctrl</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>clk_sys_adc</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>clk_adc_adc</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>clk_sys_clocks</name>
+            </field>
+          </fields>
+          <name>ENABLED0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b4</addressOffset>
+          <description>indicates the state of the clock enable</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>clk_sys_xosc</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>clk_sys_xip</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>clk_sys_watchdog</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>clk_usb_usbctrl</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>clk_sys_usbctrl</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>clk_sys_uart1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>clk_peri_uart1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>clk_sys_uart0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>clk_peri_uart0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>clk_sys_timer</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>clk_sys_tbman</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>clk_sys_sysinfo</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>clk_sys_syscfg</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>clk_sys_sram5</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>clk_sys_sram4</name>
+            </field>
+          </fields>
+          <name>ENABLED1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b8</addressOffset>
+          <description>Raw Interrupts</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>CLK_SYS_RESUS</name>
+            </field>
+          </fields>
+          <name>INTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00bc</addressOffset>
+          <description>Interrupt Enable</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>CLK_SYS_RESUS</name>
+            </field>
+          </fields>
+          <name>INTE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00c0</addressOffset>
+          <description>Interrupt Force</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>CLK_SYS_RESUS</name>
+            </field>
+          </fields>
+          <name>INTF</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00c4</addressOffset>
+          <description>Interrupt status after masking &amp; forcing</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>CLK_SYS_RESUS</name>
+            </field>
+          </fields>
+          <name>INTS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x4000c000</baseAddress>
+      <name>RESETS</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>usbctrl</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>uart1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>uart0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>timer</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>tbman</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>sysinfo</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>syscfg</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>spi1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>spi0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>rtc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>pwm</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>pll_usb</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>pll_sys</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>pio1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>pio0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>pads_qspi</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>pads_bank0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>jtag</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>io_qspi</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>io_bank0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>i2c1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>i2c0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>dma</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>busctrl</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>adc</name>
+            </field>
+          </fields>
+          <name>RESET</name>
+          <resetValue>0x01ffffff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>usbctrl</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>uart1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>uart0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>timer</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>tbman</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>sysinfo</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>syscfg</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>spi1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>spi0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>rtc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>pwm</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>pll_usb</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>pll_sys</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>pio1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>pio0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>pads_qspi</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>pads_bank0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>jtag</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>io_qspi</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>io_bank0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>i2c1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>i2c0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>dma</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>busctrl</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>adc</name>
+            </field>
+          </fields>
+          <name>WDSEL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>usbctrl</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>uart1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>uart0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>timer</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>tbman</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>sysinfo</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>syscfg</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>spi1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>spi0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>rtc</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>pwm</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>pll_usb</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>pll_sys</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>pio1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>pio0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>pads_qspi</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>pads_bank0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>jtag</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>io_qspi</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>io_bank0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>i2c1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>i2c0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>dma</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>busctrl</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>adc</name>
+            </field>
+          </fields>
+          <name>RESET_DONE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40010000</baseAddress>
+      <name>PSM</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Force block out of reset (i.e. power it on)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>proc1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>proc0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>sio</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>vreg_and_chip_reset</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>xip</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>sram5</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>sram4</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>sram3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>sram2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>sram1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>sram0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>rom</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>busfabric</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>resets</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>clocks</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>xosc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>rosc</name>
+            </field>
+          </fields>
+          <name>FRCE_ON</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Force into reset (i.e. power it off)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>proc1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>proc0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>sio</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>vreg_and_chip_reset</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>xip</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>sram5</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>sram4</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>sram3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>sram2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>sram1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>sram0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>rom</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>busfabric</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>resets</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>clocks</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>xosc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>rosc</name>
+            </field>
+          </fields>
+          <name>FRCE_OFF</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>Set to 1 if this peripheral should be reset when the watchdog fires.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>proc1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>proc0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>sio</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>vreg_and_chip_reset</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>xip</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>sram5</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>sram4</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>sram3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>sram2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>sram1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>sram0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>rom</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>busfabric</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>resets</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>clocks</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>xosc</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>rosc</name>
+            </field>
+          </fields>
+          <name>WDSEL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>Indicates the peripheral's registers are ready to access.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>proc1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>proc0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>sio</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>vreg_and_chip_reset</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>xip</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>sram5</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>sram4</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>sram3</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>sram2</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>sram1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>sram0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>rom</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>busfabric</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>resets</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>clocks</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>xosc</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>rosc</name>
+            </field>
+          </fields>
+          <name>DONE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40014000</baseAddress>
+      <interrupt>
+        <name>IO_IRQ_BANK0</name>
+        <value>13</value>
+      </interrupt>
+      <name>IO_BANK0</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO0_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>jtag_tck</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>spi0_rx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart0_tx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_0</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_0</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_0</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_0</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_overcurr_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO0_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO1_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>jtag_tms</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>spi0_ss_n</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart0_rx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_0</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_1</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_1</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_1</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO1_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO2_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>jtag_tdi</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>spi0_sclk</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart0_cts</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c1_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_1</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_2</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_2</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_2</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_en</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO2_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO3_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>jtag_tdo</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>spi0_tx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart0_rts</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c1_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_1</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_3</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_3</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_3</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_overcurr_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO3_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO4_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0024</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi0_rx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_tx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_2</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_4</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_4</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_4</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO4_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0028</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO5_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x002c</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi0_ss_n</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_rx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_2</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_5</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_5</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_5</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_en</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO5_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0030</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO6_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0034</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi0_sclk</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_cts</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c1_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_3</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_6</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_6</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_6</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_extphy_softcon</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_overcurr_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO6_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0038</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO7_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x003c</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi0_tx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_rts</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c1_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_3</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_7</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_7</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_7</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_extphy_oe_n</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO7_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0040</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO8_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0044</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi1_rx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_tx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_4</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_8</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_8</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_8</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_extphy_rcv</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_en</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO8_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0048</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO9_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x004c</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi1_ss_n</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_rx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_4</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_9</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_9</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_9</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_extphy_vp</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_overcurr_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO9_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0050</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO10_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0054</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi1_sclk</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_cts</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c1_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_5</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_10</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_10</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_10</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_extphy_vm</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO10_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0058</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO11_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x005c</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi1_tx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_rts</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c1_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_5</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_11</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_11</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_11</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_extphy_suspnd</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_en</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO11_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0060</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO12_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0064</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi1_rx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart0_tx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_6</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_12</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_12</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_12</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_extphy_speed</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_overcurr_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO12_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0068</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO13_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x006c</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi1_ss_n</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart0_rx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_6</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_13</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_13</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_13</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_extphy_vpo</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO13_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0070</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO14_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0074</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi1_sclk</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart0_cts</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c1_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_7</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_14</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_14</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_14</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_extphy_vmo</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_en</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO14_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0078</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO15_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x007c</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi1_tx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart0_rts</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c1_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_7</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_15</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_15</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_15</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_digital_dp</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_overcurr_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO15_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0080</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO16_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0084</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi0_rx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart0_tx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_0</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_16</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_16</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_16</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_digital_dm</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO16_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0088</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO17_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x008c</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi0_ss_n</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart0_rx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_0</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_17</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_17</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_17</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_en</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO17_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0090</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO18_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0094</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi0_sclk</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart0_cts</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c1_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_1</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_18</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_18</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_18</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_overcurr_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO18_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0098</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO19_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x009c</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi0_tx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart0_rts</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c1_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_1</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_19</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_19</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_19</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO19_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a0</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO20_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a4</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi0_rx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_tx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_2</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_20</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_20</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_20</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clocks_gpin_0</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_en</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO20_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a8</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO21_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00ac</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi0_ss_n</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_rx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_2</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_21</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_21</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_21</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clocks_gpout_0</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_overcurr_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO21_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b0</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO22_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b4</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi0_sclk</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_cts</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c1_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_3</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_22</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_22</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_22</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clocks_gpin_1</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO22_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b8</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO23_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00bc</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi0_tx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_rts</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c1_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_3</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_23</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_23</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_23</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clocks_gpout_1</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_en</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO23_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00c0</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO24_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00c4</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi1_rx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_tx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_4</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_24</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_24</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_24</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clocks_gpout_2</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_overcurr_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO24_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00c8</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO25_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00cc</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi1_ss_n</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_rx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_4</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_25</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_25</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_25</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>clocks_gpout_3</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO25_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00d0</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO26_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00d4</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi1_sclk</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_cts</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c1_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_5</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_26</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_26</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_26</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_en</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO26_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00d8</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO27_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00dc</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi1_tx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart1_rts</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c1_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_5</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_27</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_27</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_27</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_overcurr_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO27_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00e0</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO28_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00e4</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi1_rx</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart0_tx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_sda</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_a_6</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_28</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_28</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_28</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_detect</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO28_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00e8</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO29_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00ec</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>spi1_ss_n</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>uart0_rx</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>i2c0_scl</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pwm_b_6</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_29</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio0_29</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>pio1_29</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>usb_muxing_vbus_en</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO29_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f0</addressOffset>
+          <description>Raw Interrupts</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO7_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO7_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO7_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO7_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO6_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO6_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO6_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO6_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO5_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO5_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO5_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO5_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO4_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO4_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO4_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO4_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO0_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>INTR0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f4</addressOffset>
+          <description>Raw Interrupts</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO15_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO15_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO15_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO15_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO14_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO14_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO14_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO14_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO13_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO13_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO13_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO13_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO12_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO12_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO12_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO12_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO11_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO11_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO11_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO11_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO10_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO10_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO10_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO10_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO9_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO9_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO9_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO9_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO8_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO8_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO8_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO8_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>INTR1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f8</addressOffset>
+          <description>Raw Interrupts</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO23_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO23_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO23_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO23_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO22_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO22_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO22_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO22_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO21_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO21_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO21_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO21_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO20_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO20_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO20_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO20_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO19_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO19_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO19_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO19_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO18_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO18_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO18_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO18_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO17_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO17_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO17_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO17_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO16_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO16_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO16_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO16_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>INTR2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00fc</addressOffset>
+          <description>Raw Interrupts</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO29_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO29_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO29_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO29_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO28_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO28_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO28_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO28_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO27_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO27_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO27_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO27_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO26_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO26_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO26_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO26_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO25_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO25_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO25_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO25_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO24_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO24_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO24_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO24_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>INTR3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0100</addressOffset>
+          <description>Interrupt Enable for proc0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO7_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO7_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO7_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO7_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO6_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO6_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO6_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO6_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO5_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO5_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO5_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO5_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO4_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO4_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO4_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO4_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO0_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTE0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0104</addressOffset>
+          <description>Interrupt Enable for proc0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO15_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO15_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO15_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO15_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO14_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO14_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO14_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO14_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO13_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO13_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO13_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO13_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO12_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO12_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO12_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO12_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO11_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO11_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO11_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO11_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO10_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO10_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO10_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO10_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO9_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO9_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO9_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO9_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO8_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO8_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO8_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO8_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTE1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0108</addressOffset>
+          <description>Interrupt Enable for proc0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO23_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO23_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO23_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO23_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO22_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO22_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO22_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO22_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO21_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO21_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO21_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO21_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO20_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO20_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO20_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO20_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO19_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO19_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO19_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO19_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO18_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO18_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO18_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO18_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO17_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO17_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO17_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO17_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO16_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO16_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO16_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO16_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTE2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x010c</addressOffset>
+          <description>Interrupt Enable for proc0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO29_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO29_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO29_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO29_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO28_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO28_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO28_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO28_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO27_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO27_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO27_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO27_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO26_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO26_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO26_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO26_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO25_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO25_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO25_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO25_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO24_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO24_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO24_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO24_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTE3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0110</addressOffset>
+          <description>Interrupt Force for proc0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO7_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO7_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO7_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO7_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO6_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO6_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO6_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO6_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO5_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO5_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO5_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO5_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO4_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO4_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO4_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO4_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO0_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTF0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0114</addressOffset>
+          <description>Interrupt Force for proc0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO15_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO15_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO15_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO15_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO14_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO14_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO14_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO14_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO13_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO13_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO13_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO13_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO12_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO12_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO12_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO12_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO11_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO11_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO11_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO11_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO10_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO10_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO10_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO10_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO9_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO9_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO9_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO9_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO8_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO8_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO8_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO8_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTF1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0118</addressOffset>
+          <description>Interrupt Force for proc0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO23_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO23_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO23_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO23_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO22_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO22_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO22_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO22_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO21_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO21_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO21_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO21_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO20_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO20_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO20_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO20_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO19_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO19_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO19_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO19_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO18_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO18_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO18_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO18_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO17_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO17_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO17_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO17_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO16_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO16_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO16_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO16_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTF2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x011c</addressOffset>
+          <description>Interrupt Force for proc0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO29_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO29_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO29_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO29_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO28_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO28_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO28_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO28_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO27_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO27_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO27_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO27_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO26_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO26_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO26_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO26_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO25_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO25_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO25_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO25_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO24_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO24_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO24_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO24_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTF3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0120</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for proc0</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO7_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO7_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO7_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO7_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO6_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO6_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO6_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO6_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO5_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO5_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO5_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO5_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO4_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO4_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO4_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO4_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO0_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTS0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0124</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for proc0</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO15_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO15_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO15_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO15_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO14_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO14_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO14_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO14_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO13_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO13_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO13_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO13_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO12_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO12_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO12_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO12_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO11_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO11_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO11_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO11_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO10_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO10_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO10_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO10_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO9_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO9_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO9_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO9_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO8_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO8_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO8_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO8_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTS1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0128</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for proc0</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO23_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO23_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO23_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO23_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO22_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO22_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO22_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO22_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO21_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO21_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO21_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO21_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO20_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO20_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO20_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO20_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO19_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO19_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO19_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO19_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO18_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO18_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO18_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO18_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO17_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO17_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO17_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO17_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO16_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO16_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO16_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO16_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTS2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x012c</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for proc0</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO29_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO29_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO29_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO29_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO28_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO28_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO28_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO28_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO27_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO27_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO27_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO27_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO26_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO26_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO26_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO26_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO25_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO25_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO25_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO25_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO24_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO24_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO24_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO24_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTS3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0130</addressOffset>
+          <description>Interrupt Enable for proc1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO7_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO7_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO7_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO7_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO6_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO6_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO6_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO6_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO5_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO5_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO5_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO5_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO4_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO4_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO4_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO4_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO0_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTE0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0134</addressOffset>
+          <description>Interrupt Enable for proc1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO15_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO15_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO15_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO15_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO14_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO14_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO14_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO14_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO13_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO13_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO13_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO13_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO12_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO12_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO12_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO12_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO11_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO11_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO11_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO11_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO10_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO10_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO10_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO10_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO9_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO9_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO9_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO9_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO8_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO8_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO8_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO8_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTE1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0138</addressOffset>
+          <description>Interrupt Enable for proc1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO23_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO23_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO23_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO23_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO22_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO22_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO22_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO22_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO21_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO21_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO21_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO21_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO20_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO20_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO20_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO20_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO19_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO19_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO19_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO19_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO18_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO18_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO18_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO18_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO17_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO17_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO17_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO17_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO16_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO16_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO16_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO16_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTE2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x013c</addressOffset>
+          <description>Interrupt Enable for proc1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO29_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO29_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO29_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO29_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO28_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO28_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO28_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO28_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO27_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO27_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO27_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO27_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO26_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO26_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO26_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO26_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO25_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO25_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO25_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO25_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO24_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO24_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO24_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO24_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTE3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0140</addressOffset>
+          <description>Interrupt Force for proc1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO7_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO7_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO7_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO7_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO6_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO6_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO6_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO6_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO5_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO5_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO5_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO5_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO4_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO4_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO4_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO4_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO0_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTF0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0144</addressOffset>
+          <description>Interrupt Force for proc1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO15_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO15_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO15_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO15_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO14_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO14_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO14_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO14_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO13_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO13_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO13_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO13_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO12_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO12_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO12_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO12_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO11_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO11_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO11_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO11_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO10_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO10_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO10_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO10_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO9_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO9_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO9_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO9_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO8_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO8_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO8_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO8_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTF1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0148</addressOffset>
+          <description>Interrupt Force for proc1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO23_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO23_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO23_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO23_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO22_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO22_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO22_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO22_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO21_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO21_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO21_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO21_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO20_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO20_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO20_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO20_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO19_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO19_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO19_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO19_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO18_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO18_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO18_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO18_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO17_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO17_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO17_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO17_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO16_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO16_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO16_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO16_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTF2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x014c</addressOffset>
+          <description>Interrupt Force for proc1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO29_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO29_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO29_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO29_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO28_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO28_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO28_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO28_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO27_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO27_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO27_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO27_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO26_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO26_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO26_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO26_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO25_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO25_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO25_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO25_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO24_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO24_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO24_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO24_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTF3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0150</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for proc1</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO7_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO7_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO7_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO7_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO6_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO6_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO6_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO6_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO5_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO5_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO5_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO5_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO4_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO4_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO4_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO4_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO0_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTS0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0154</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for proc1</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO15_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO15_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO15_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO15_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO14_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO14_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO14_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO14_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO13_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO13_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO13_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO13_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO12_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO12_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO12_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO12_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO11_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO11_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO11_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO11_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO10_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO10_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO10_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO10_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO9_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO9_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO9_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO9_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO8_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO8_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO8_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO8_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTS1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0158</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for proc1</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO23_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO23_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO23_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO23_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO22_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO22_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO22_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO22_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO21_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO21_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO21_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO21_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO20_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO20_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO20_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO20_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO19_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO19_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO19_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO19_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO18_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO18_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO18_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO18_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO17_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO17_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO17_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO17_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO16_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO16_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO16_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO16_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTS2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x015c</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for proc1</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO29_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO29_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO29_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO29_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO28_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO28_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO28_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO28_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO27_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO27_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO27_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO27_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO26_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO26_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO26_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO26_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO25_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO25_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO25_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO25_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO24_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO24_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO24_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO24_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTS3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0160</addressOffset>
+          <description>Interrupt Enable for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO7_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO7_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO7_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO7_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO6_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO6_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO6_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO6_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO5_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO5_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO5_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO5_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO4_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO4_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO4_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO4_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO0_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTE0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0164</addressOffset>
+          <description>Interrupt Enable for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO15_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO15_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO15_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO15_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO14_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO14_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO14_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO14_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO13_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO13_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO13_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO13_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO12_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO12_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO12_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO12_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO11_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO11_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO11_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO11_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO10_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO10_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO10_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO10_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO9_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO9_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO9_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO9_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO8_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO8_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO8_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO8_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTE1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0168</addressOffset>
+          <description>Interrupt Enable for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO23_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO23_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO23_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO23_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO22_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO22_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO22_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO22_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO21_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO21_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO21_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO21_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO20_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO20_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO20_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO20_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO19_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO19_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO19_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO19_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO18_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO18_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO18_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO18_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO17_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO17_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO17_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO17_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO16_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO16_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO16_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO16_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTE2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x016c</addressOffset>
+          <description>Interrupt Enable for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO29_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO29_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO29_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO29_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO28_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO28_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO28_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO28_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO27_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO27_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO27_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO27_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO26_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO26_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO26_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO26_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO25_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO25_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO25_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO25_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO24_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO24_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO24_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO24_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTE3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0170</addressOffset>
+          <description>Interrupt Force for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO7_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO7_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO7_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO7_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO6_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO6_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO6_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO6_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO5_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO5_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO5_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO5_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO4_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO4_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO4_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO4_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO0_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTF0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0174</addressOffset>
+          <description>Interrupt Force for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO15_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO15_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO15_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO15_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO14_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO14_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO14_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO14_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO13_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO13_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO13_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO13_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO12_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO12_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO12_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO12_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO11_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO11_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO11_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO11_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO10_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO10_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO10_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO10_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO9_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO9_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO9_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO9_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO8_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO8_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO8_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO8_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTF1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0178</addressOffset>
+          <description>Interrupt Force for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO23_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO23_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO23_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO23_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO22_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO22_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO22_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO22_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO21_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO21_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO21_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO21_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO20_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO20_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO20_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO20_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO19_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO19_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO19_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO19_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO18_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO18_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO18_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO18_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO17_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO17_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO17_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO17_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO16_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO16_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO16_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO16_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTF2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x017c</addressOffset>
+          <description>Interrupt Force for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO29_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO29_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO29_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO29_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO28_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO28_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO28_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO28_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO27_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO27_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO27_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO27_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO26_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO26_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO26_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO26_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO25_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO25_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO25_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO25_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO24_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO24_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO24_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO24_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTF3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0180</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO7_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO7_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO7_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO7_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO6_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO6_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO6_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO6_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO5_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO5_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO5_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO5_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO4_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO4_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO4_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO4_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO0_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTS0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0184</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO15_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO15_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO15_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO15_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO14_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO14_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO14_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO14_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO13_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO13_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO13_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO13_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO12_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO12_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO12_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO12_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO11_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO11_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO11_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO11_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO10_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO10_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO10_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO10_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO9_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO9_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO9_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO9_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO8_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO8_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO8_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO8_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTS1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0188</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <name>GPIO23_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[30:30]</bitRange>
+              <name>GPIO23_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>GPIO23_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <name>GPIO23_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[27:27]</bitRange>
+              <name>GPIO22_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <name>GPIO22_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <name>GPIO22_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>GPIO22_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO21_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO21_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO21_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO21_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO20_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO20_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO20_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO20_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO19_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO19_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO19_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO19_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO18_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO18_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO18_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO18_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO17_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO17_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO17_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO17_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO16_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO16_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO16_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO16_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTS2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x018c</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO29_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO29_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO29_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO29_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO28_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO28_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO28_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO28_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO27_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO27_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO27_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO27_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO26_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO26_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO26_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO26_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO25_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO25_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO25_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO25_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO24_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO24_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO24_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO24_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTS3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40018000</baseAddress>
+      <interrupt>
+        <name>IO_IRQ_QSPI</name>
+        <value>14</value>
+      </interrupt>
+      <name>IO_QSPI</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SCLK_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>xip_sclk</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_30</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SCLK_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SS_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>xip_ss_n</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_31</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SS_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SD0_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>xip_sd0</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_32</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SD0_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SD1_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>xip_sd1</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_33</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SD1_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SD2_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0024</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>xip_sd2</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_34</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SD2_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0028</addressOffset>
+          <description>GPIO status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <description>interrupt to processors, after override is applied</description>
+              <name>IRQTOPROC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>interrupt from pad before override is applied</description>
+              <name>IRQFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>input signal to peripheral, after override is applied</description>
+              <name>INTOPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>input signal from pad, before override is applied</description>
+              <name>INFROMPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>output enable to pad after register override is applied</description>
+              <name>OETOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>output enable from selected peripheral, before register override is applied</description>
+              <name>OEFROMPERI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>output signal to pad after register override is applied</description>
+              <name>OUTTOPAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>output signal from selected peripheral, before register override is applied</description>
+              <name>OUTFROMPERI</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SD3_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x002c</addressOffset>
+          <description>GPIO control including function select and overrides.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:28]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the interrupt</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the interrupt</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive interrupt high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IRQOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:16]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>don't invert the peri input</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>invert the peri input</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive peri input high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>INOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:12]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output enable from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output enable from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>disable output</description>
+                  <name>DISABLE</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>enable output</description>
+                  <name>ENABLE</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OEOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>drive output from peripheral signal selected by funcsel</description>
+                  <name>NORMAL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output from inverse of peripheral signal selected by funcsel</description>
+                  <name>INVERT</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output low</description>
+                  <name>LOW</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>drive output high</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>OUTOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>0-31 -&gt; selects pin function according to the gpio table\n
+                31 == NULL</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>xip_sd3</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sio_35</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>null</name>
+                  <value>31</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FUNCSEL</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SD3_CTRL</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0030</addressOffset>
+          <description>Raw Interrupts</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO_QSPI_SS_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>INTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0034</addressOffset>
+          <description>Interrupt Enable for proc0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0038</addressOffset>
+          <description>Interrupt Force for proc0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTF</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x003c</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for proc0</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC0_INTS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0040</addressOffset>
+          <description>Interrupt Enable for proc1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0044</addressOffset>
+          <description>Interrupt Force for proc1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTF</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0048</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for proc1</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>PROC1_INTS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x004c</addressOffset>
+          <description>Interrupt Enable for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0050</addressOffset>
+          <description>Interrupt Force for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTF</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0054</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for dormant_wake</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>GPIO_QSPI_SD3_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>GPIO_QSPI_SD3_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>GPIO_QSPI_SD2_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>GPIO_QSPI_SD2_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>GPIO_QSPI_SD1_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>GPIO_QSPI_SD1_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>GPIO_QSPI_SD0_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>GPIO_QSPI_SD0_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>GPIO_QSPI_SS_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>GPIO_QSPI_SS_LEVEL_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>GPIO_QSPI_SCLK_EDGE_LOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_HIGH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>GPIO_QSPI_SCLK_LEVEL_LOW</name>
+            </field>
+          </fields>
+          <name>DORMANT_WAKE_INTS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x4001c000</baseAddress>
+      <name>PADS_BANK0</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Voltage select. Per bank control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Set voltage to 3.3V (DVDD &gt;= 2V5)</description>
+                  <name>3v3</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Set voltage to 1.8V (DVDD &lt;= 1V8)</description>
+                  <name>1v8</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>VOLTAGE_SELECT</name>
+            </field>
+          </fields>
+          <name>VOLTAGE_SELECT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO0</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO1</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO2</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO3</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO4</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO5</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO6</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO7</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0024</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO8</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0028</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO9</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x002c</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO10</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0030</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO11</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0034</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO12</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0038</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO13</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x003c</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO14</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0040</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO15</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0044</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO16</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0048</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO17</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x004c</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO18</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0050</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO19</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0054</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO20</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0058</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO21</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x005c</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO22</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0060</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO23</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0064</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO24</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0068</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO25</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x006c</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO26</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0070</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO27</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0074</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO28</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0078</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO29</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x007c</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>SWCLK</name>
+          <resetValue>0x000000da</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0080</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>SWD</name>
+          <resetValue>0x0000005a</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40020000</baseAddress>
+      <name>PADS_QSPI</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Voltage select. Per bank control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Set voltage to 3.3V (DVDD &gt;= 2V5)</description>
+                  <name>3v3</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Set voltage to 1.8V (DVDD &lt;= 1V8)</description>
+                  <name>1v8</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>VOLTAGE_SELECT</name>
+            </field>
+          </fields>
+          <name>VOLTAGE_SELECT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SCLK</name>
+          <resetValue>0x00000056</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SD0</name>
+          <resetValue>0x00000052</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SD1</name>
+          <resetValue>0x00000052</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SD2</name>
+          <resetValue>0x00000052</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SD3</name>
+          <resetValue>0x00000052</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>Pad control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Output disable. Has priority over output enable from peripherals</description>
+              <name>OD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Input enable</description>
+              <name>IE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Drive strength.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>2mA</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>4mA</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>8mA</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>12mA</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DRIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Pull up enable</description>
+              <name>PUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pull down enable</description>
+              <name>PDE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enable schmitt trigger</description>
+              <name>SCHMITT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Slew rate control. 1 = Fast, 0 = Slow</description>
+              <name>SLEWFAST</name>
+            </field>
+          </fields>
+          <name>GPIO_QSPI_SS</name>
+          <resetValue>0x0000005a</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40024000</baseAddress>
+      <description>Controls the crystal oscillator</description>
+      <name>XOSC</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Crystal Oscillator Control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:12]</bitRange>
+              <description>On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\n
+                If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.\n
+                The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <value>3358</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <value>4011</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:0]</bitRange>
+              <description>Frequency range. This resets to 0xAA0 and cannot be changed.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>1_15MHZ</name>
+                  <value>2720</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESERVED_1</name>
+                  <value>2721</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESERVED_2</name>
+                  <value>2722</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESERVED_3</name>
+                  <value>2723</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FREQ_RANGE</name>
+            </field>
+          </fields>
+          <name>CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Crystal Oscillator Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Oscillator is running and stable</description>
+              <name>STABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>BADWRITE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Oscillator is enabled but not necessarily running and stable, resets to 0</description>
+              <name>ENABLED</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:0]</bitRange>
+              <description>The current frequency range setting, always reads 0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>1_15MHZ</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESERVED_1</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESERVED_2</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESERVED_3</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FREQ_RANGE</name>
+            </field>
+          </fields>
+          <name>STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0008</addressOffset>
+          <description>Crystal Oscillator pause control\n
+            This is used to save power by pausing the XOSC\n
+            On power-up this field is initialised to WAKE\n
+            An invalid write will also select WAKE\n
+            WARNING: stop the PLLs before selecting dormant mode\n
+            WARNING: setup the irq before selecting dormant mode</description>
+          <name>DORMANT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>Controls the startup delay</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <description>Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly.</description>
+              <name>X4</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:0]</bitRange>
+              <description>in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles.</description>
+              <name>DELAY</name>
+            </field>
+          </fields>
+          <name>STARTUP</name>
+          <resetValue>0x000000c4</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>A down counter running at the xosc frequency which counts to zero and stops.\n
+            To start the counter write a non-zero value.\n
+            Can be used for short software pauses when setting up time sensitive hardware.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <name>COUNT</name>
+            </field>
+          </fields>
+          <name>COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40028000</baseAddress>
+      <name>PLL_SYS</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Control and Status\n
+            GENERAL CONSTRAINTS:\n
+            Reference clock frequency min=5MHz, max=800MHz\n
+            Feedback divider min=16, max=320\n
+            VCO frequency min=400MHz, max=1600MHz</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>PLL is locked</description>
+              <name>LOCK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.</description>
+              <name>BYPASS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <description>Divides the PLL input reference clock.\n
+                Behaviour is undefined for div=0.\n
+                PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.</description>
+              <name>REFDIV</name>
+            </field>
+          </fields>
+          <name>CS</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Controls the PLL power modes.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>PLL VCO powerdown\n
+                To save power set high when PLL output not required or bypass=1.</description>
+              <name>VCOPD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>PLL post divider powerdown\n
+                To save power set high when PLL output not required or bypass=1.</description>
+              <name>POSTDIVPD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>PLL DSM powerdown\n
+                Nothing is achieved by setting this low.</description>
+              <name>DSMPD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>PLL powerdown\n
+                To save power set high when PLL output not required.</description>
+              <name>PD</name>
+            </field>
+          </fields>
+          <name>PWR</name>
+          <resetValue>0x0000002d</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>Feedback divisor\n
+            (note: this PLL does not support fractional division)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:0]</bitRange>
+              <description>see ctrl reg description for constraints</description>
+              <name>FBDIV_INT</name>
+            </field>
+          </fields>
+          <name>FBDIV_INT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>Controls the PLL post dividers for the primary output\n
+            (note: this PLL does not have a secondary output)\n
+            the primary output is driven from VCO divided by postdiv1*postdiv2</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:16]</bitRange>
+              <description>divide by 1-7</description>
+              <name>POSTDIV1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:12]</bitRange>
+              <description>divide by 1-7</description>
+              <name>POSTDIV2</name>
+            </field>
+          </fields>
+          <name>PRIM</name>
+          <resetValue>0x00077000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral derivedFrom="PLL_SYS">
+      <baseAddress>0x4002c000</baseAddress>
+      <name>PLL_USB</name>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40030000</baseAddress>
+      <description>Register block for busfabric control signals and performance counters</description>
+      <name>BUSCTRL</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Set the priority of each master for bus arbitration.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>0 - low priority, 1 - high priority</description>
+              <name>DMA_W</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <description>0 - low priority, 1 - high priority</description>
+              <name>DMA_R</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>0 - low priority, 1 - high priority</description>
+              <name>PROC1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>0 - low priority, 1 - high priority</description>
+              <name>PROC0</name>
+            </field>
+          </fields>
+          <name>BUS_PRIORITY</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Bus priority acknowledge</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Goes to 1 once all arbiters have registered the new global priority levels.\n
+                Arbiters update their local priority when servicing a new nonsequential access.\n
+                In normal circumstances this will happen almost immediately.</description>
+              <name>BUS_PRIORITY_ACK</name>
+            </field>
+          </fields>
+          <name>BUS_PRIORITY_ACK</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>Bus fabric performance counter 0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:0]</bitRange>
+              <description>Busfabric saturating performance counter 0\n
+                Count some event signal from the busfabric arbiters.\n
+                Write any value to clear. Select an event to count using PERFSEL0</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>PERFCTR0</name>
+            </field>
+          </fields>
+          <name>PERFCTR0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>Bus fabric performance event select for PERFCTR0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>apb_contested</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>apb</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fastperi_contested</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fastperi</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram5_contested</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram5</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram4_contested</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram4</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram3_contested</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram3</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram2_contested</name>
+                  <value>10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram2</name>
+                  <value>11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram1_contested</name>
+                  <value>12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram1</name>
+                  <value>13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram0_contested</name>
+                  <value>14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram0</name>
+                  <value>15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xip_main_contested</name>
+                  <value>16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xip_main</name>
+                  <value>17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rom_contested</name>
+                  <value>18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rom</name>
+                  <value>19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>PERFSEL0</name>
+            </field>
+          </fields>
+          <name>PERFSEL0</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>Bus fabric performance counter 1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:0]</bitRange>
+              <description>Busfabric saturating performance counter 1\n
+                Count some event signal from the busfabric arbiters.\n
+                Write any value to clear. Select an event to count using PERFSEL1</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>PERFCTR1</name>
+            </field>
+          </fields>
+          <name>PERFCTR1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>Bus fabric performance event select for PERFCTR1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>apb_contested</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>apb</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fastperi_contested</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fastperi</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram5_contested</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram5</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram4_contested</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram4</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram3_contested</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram3</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram2_contested</name>
+                  <value>10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram2</name>
+                  <value>11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram1_contested</name>
+                  <value>12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram1</name>
+                  <value>13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram0_contested</name>
+                  <value>14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram0</name>
+                  <value>15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xip_main_contested</name>
+                  <value>16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xip_main</name>
+                  <value>17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rom_contested</name>
+                  <value>18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rom</name>
+                  <value>19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>PERFSEL1</name>
+            </field>
+          </fields>
+          <name>PERFSEL1</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>Bus fabric performance counter 2</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:0]</bitRange>
+              <description>Busfabric saturating performance counter 2\n
+                Count some event signal from the busfabric arbiters.\n
+                Write any value to clear. Select an event to count using PERFSEL2</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>PERFCTR2</name>
+            </field>
+          </fields>
+          <name>PERFCTR2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>Bus fabric performance event select for PERFCTR2</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>apb_contested</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>apb</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fastperi_contested</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fastperi</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram5_contested</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram5</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram4_contested</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram4</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram3_contested</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram3</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram2_contested</name>
+                  <value>10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram2</name>
+                  <value>11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram1_contested</name>
+                  <value>12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram1</name>
+                  <value>13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram0_contested</name>
+                  <value>14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram0</name>
+                  <value>15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xip_main_contested</name>
+                  <value>16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xip_main</name>
+                  <value>17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rom_contested</name>
+                  <value>18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rom</name>
+                  <value>19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>PERFSEL2</name>
+            </field>
+          </fields>
+          <name>PERFSEL2</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>Bus fabric performance counter 3</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:0]</bitRange>
+              <description>Busfabric saturating performance counter 3\n
+                Count some event signal from the busfabric arbiters.\n
+                Write any value to clear. Select an event to count using PERFSEL3</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>PERFCTR3</name>
+            </field>
+          </fields>
+          <name>PERFCTR3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0024</addressOffset>
+          <description>Bus fabric performance event select for PERFCTR3</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>apb_contested</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>apb</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fastperi_contested</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>fastperi</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram5_contested</name>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram5</name>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram4_contested</name>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram4</name>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram3_contested</name>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram3</name>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram2_contested</name>
+                  <value>10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram2</name>
+                  <value>11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram1_contested</name>
+                  <value>12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram1</name>
+                  <value>13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram0_contested</name>
+                  <value>14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>sram0</name>
+                  <value>15</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xip_main_contested</name>
+                  <value>16</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>xip_main</name>
+                  <value>17</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rom_contested</name>
+                  <value>18</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>rom</name>
+                  <value>19</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>PERFSEL3</name>
+            </field>
+          </fields>
+          <name>PERFSEL3</name>
+          <resetValue>0x0000001f</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40034000</baseAddress>
+      <interrupt>
+        <name>UART0_IRQ</name>
+        <value>20</value>
+      </interrupt>
+      <name>UART0</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Data Register, UARTDR</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.</description>
+              <name>OE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.</description>
+              <name>BE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
+              <name>PE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
+              <name>FE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Receive (read) data character. Transmit (write) data character.</description>
+              <name>DATA</name>
+            </field>
+          </fields>
+          <name>UARTDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Receive Status Register/Error Clear Register, UARTRSR/UARTECR</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>OE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>BE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>PE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>FE</name>
+            </field>
+          </fields>
+          <name>UARTRSR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>Flag Register, UARTFR</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW.</description>
+              <name>RI</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.</description>
+              <name>TXFE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.</description>
+              <name>RXFF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.</description>
+              <name>TXFF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.</description>
+              <name>RXFE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.</description>
+              <name>BUSY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.</description>
+              <name>DCD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW.</description>
+              <name>DSR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW.</description>
+              <name>CTS</name>
+            </field>
+          </fields>
+          <name>UARTFR</name>
+          <resetValue>0x00000090</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>IrDA Low-Power Counter Register, UARTILPR</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>8-bit low-power divisor value. These bits are cleared to 0 at reset.</description>
+              <name>ILPDVSR</name>
+            </field>
+          </fields>
+          <name>UARTILPR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0024</addressOffset>
+          <description>Integer Baud Rate Register, UARTIBRD</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>The integer baud rate divisor. These bits are cleared to 0 on reset.</description>
+              <name>BAUD_DIVINT</name>
+            </field>
+          </fields>
+          <name>UARTIBRD</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0028</addressOffset>
+          <description>Fractional Baud Rate Register, UARTFBRD</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <description>The fractional baud rate divisor. These bits are cleared to 0 on reset.</description>
+              <name>BAUD_DIVFRAC</name>
+            </field>
+          </fields>
+          <name>UARTFBRD</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x002c</addressOffset>
+          <description>Line Control Register, UARTLCR_H</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.</description>
+              <name>SPS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:5]</bitRange>
+              <description>Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.</description>
+              <name>WLEN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).</description>
+              <name>FEN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.</description>
+              <name>STP2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.</description>
+              <name>EPS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.</description>
+              <name>PEN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.</description>
+              <name>BRK</name>
+            </field>
+          </fields>
+          <name>UARTLCR_H</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0030</addressOffset>
+          <description>Control Register, UARTCR</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.</description>
+              <name>CTSEN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.</description>
+              <name>RTSEN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).</description>
+              <name>OUT2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).</description>
+              <name>OUT1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.</description>
+              <name>RTS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.</description>
+              <name>DTR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.</description>
+              <name>RXE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.</description>
+              <name>TXE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.</description>
+              <name>LBE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.</description>
+              <name>SIRLP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.</description>
+              <name>SIREN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.</description>
+              <name>UARTEN</name>
+            </field>
+          </fields>
+          <name>UARTCR</name>
+          <resetValue>0x00000300</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0034</addressOffset>
+          <description>Interrupt FIFO Level Select Register, UARTIFLS</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:3]</bitRange>
+              <description>Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes &gt;= 1 / 8 full b001 = Receive FIFO becomes &gt;= 1 / 4 full b010 = Receive FIFO becomes &gt;= 1 / 2 full b011 = Receive FIFO becomes &gt;= 3 / 4 full b100 = Receive FIFO becomes &gt;= 7 / 8 full b101-b111 = reserved.</description>
+              <name>RXIFLSEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:0]</bitRange>
+              <description>Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes &lt;= 1 / 8 full b001 = Transmit FIFO becomes &lt;= 1 / 4 full b010 = Transmit FIFO becomes &lt;= 1 / 2 full b011 = Transmit FIFO becomes &lt;= 3 / 4 full b100 = Transmit FIFO becomes &lt;= 7 / 8 full b101-b111 = reserved.</description>
+              <name>TXIFLSEL</name>
+            </field>
+          </fields>
+          <name>UARTIFLS</name>
+          <resetValue>0x00000012</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0038</addressOffset>
+          <description>Interrupt Mask Set/Clear Register, UARTIMSC</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.</description>
+              <name>OEIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.</description>
+              <name>BEIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.</description>
+              <name>PEIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.</description>
+              <name>FEIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.</description>
+              <name>RTIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.</description>
+              <name>TXIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.</description>
+              <name>RXIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.</description>
+              <name>DSRMIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.</description>
+              <name>DCDMIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.</description>
+              <name>CTSMIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.</description>
+              <name>RIMIM</name>
+            </field>
+          </fields>
+          <name>UARTIMSC</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x003c</addressOffset>
+          <description>Raw Interrupt Status Register, UARTRIS</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.</description>
+              <name>OERIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.</description>
+              <name>BERIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.</description>
+              <name>PERIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.</description>
+              <name>FERIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a</description>
+              <name>RTRIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.</description>
+              <name>TXRIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.</description>
+              <name>RXRIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt.</description>
+              <name>DSRRMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt.</description>
+              <name>DCDRMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt.</description>
+              <name>CTSRMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt.</description>
+              <name>RIRMIS</name>
+            </field>
+          </fields>
+          <name>UARTRIS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0040</addressOffset>
+          <description>Masked Interrupt Status Register, UARTMIS</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.</description>
+              <name>OEMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.</description>
+              <name>BEMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.</description>
+              <name>PEMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.</description>
+              <name>FEMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.</description>
+              <name>RTMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.</description>
+              <name>TXMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.</description>
+              <name>RXMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.</description>
+              <name>DSRMMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.</description>
+              <name>DCDMMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.</description>
+              <name>CTSMMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.</description>
+              <name>RIMMIS</name>
+            </field>
+          </fields>
+          <name>UARTMIS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0044</addressOffset>
+          <description>Interrupt Clear Register, UARTICR</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Overrun error interrupt clear. Clears the UARTOEINTR interrupt.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>OEIC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Break error interrupt clear. Clears the UARTBEINTR interrupt.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>BEIC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Parity error interrupt clear. Clears the UARTPEINTR interrupt.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>PEIC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Framing error interrupt clear. Clears the UARTFEINTR interrupt.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>FEIC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>RTIC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Transmit interrupt clear. Clears the UARTTXINTR interrupt.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>TXIC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Receive interrupt clear. Clears the UARTRXINTR interrupt.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>RXIC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>DSRMIC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>DCDMIC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CTSMIC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>RIMIC</name>
+            </field>
+          </fields>
+          <name>UARTICR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0048</addressOffset>
+          <description>DMA Control Register, UARTDMACR</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.</description>
+              <name>DMAONERR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.</description>
+              <name>TXDMAE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.</description>
+              <name>RXDMAE</name>
+            </field>
+          </fields>
+          <name>UARTDMACR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0fe0</addressOffset>
+          <description>UARTPeriphID0 Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>These bits read back as 0x11</description>
+              <name>PARTNUMBER0</name>
+            </field>
+          </fields>
+          <name>UARTPERIPHID0</name>
+          <resetValue>0x00000011</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0fe4</addressOffset>
+          <description>UARTPeriphID1 Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:4]</bitRange>
+              <description>These bits read back as 0x1</description>
+              <name>DESIGNER0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:0]</bitRange>
+              <description>These bits read back as 0x0</description>
+              <name>PARTNUMBER1</name>
+            </field>
+          </fields>
+          <name>UARTPERIPHID1</name>
+          <resetValue>0x00000010</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0fe8</addressOffset>
+          <description>UARTPeriphID2 Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:4]</bitRange>
+              <description>This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3</description>
+              <name>REVISION</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:0]</bitRange>
+              <description>These bits read back as 0x4</description>
+              <name>DESIGNER1</name>
+            </field>
+          </fields>
+          <name>UARTPERIPHID2</name>
+          <resetValue>0x00000034</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0fec</addressOffset>
+          <description>UARTPeriphID3 Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>These bits read back as 0x00</description>
+              <name>CONFIGURATION</name>
+            </field>
+          </fields>
+          <name>UARTPERIPHID3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0ff0</addressOffset>
+          <description>UARTPCellID0 Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>These bits read back as 0x0D</description>
+              <name>UARTPCELLID0</name>
+            </field>
+          </fields>
+          <name>UARTPCELLID0</name>
+          <resetValue>0x0000000d</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0ff4</addressOffset>
+          <description>UARTPCellID1 Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>These bits read back as 0xF0</description>
+              <name>UARTPCELLID1</name>
+            </field>
+          </fields>
+          <name>UARTPCELLID1</name>
+          <resetValue>0x000000f0</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0ff8</addressOffset>
+          <description>UARTPCellID2 Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>These bits read back as 0x05</description>
+              <name>UARTPCELLID2</name>
+            </field>
+          </fields>
+          <name>UARTPCELLID2</name>
+          <resetValue>0x00000005</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0ffc</addressOffset>
+          <description>UARTPCellID3 Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>These bits read back as 0xB1</description>
+              <name>UARTPCELLID3</name>
+            </field>
+          </fields>
+          <name>UARTPCELLID3</name>
+          <resetValue>0x000000b1</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral derivedFrom="UART0">
+      <baseAddress>0x40038000</baseAddress>
+      <interrupt>
+        <name>UART1_IRQ</name>
+        <value>21</value>
+      </interrupt>
+      <name>UART1</name>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x4003c000</baseAddress>
+      <interrupt>
+        <name>SPI0_IRQ</name>
+        <value>18</value>
+      </interrupt>
+      <name>SPI0</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Control register 0, SSPCR0 on page 3-4</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:8]</bitRange>
+              <description>Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.</description>
+              <name>SCR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.</description>
+              <name>SPH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.</description>
+              <name>SPO</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <description>Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.</description>
+              <name>FRF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <description>Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.</description>
+              <name>DSS</name>
+            </field>
+          </fields>
+          <name>SSPCR0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Control register 1, SSPCR1 on page 3-5</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.</description>
+              <name>SOD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.</description>
+              <name>MS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.</description>
+              <name>SSE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.</description>
+              <name>LBM</name>
+            </field>
+          </fields>
+          <name>SSPCR1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>Data register, SSPDR on page 3-6</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.</description>
+              <name>DATA</name>
+            </field>
+          </fields>
+          <name>SSPDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>Status register, SSPSR on page 3-7</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.</description>
+              <name>BSY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.</description>
+              <name>RFF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty.</description>
+              <name>RNE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full.</description>
+              <name>TNF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.</description>
+              <name>TFE</name>
+            </field>
+          </fields>
+          <name>SSPSR</name>
+          <resetValue>0x00000003</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>Clock prescale register, SSPCPSR on page 3-8</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.</description>
+              <name>CPSDVSR</name>
+            </field>
+          </fields>
+          <name>SSPCPSR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>Interrupt mask set or clear register, SSPIMSC on page 3-9</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.</description>
+              <name>TXIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.</description>
+              <name>RXIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.</description>
+              <name>RTIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.</description>
+              <name>RORIM</name>
+            </field>
+          </fields>
+          <name>SSPIMSC</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>Raw interrupt status register, SSPRIS on page 3-10</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt</description>
+              <name>TXRIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt</description>
+              <name>RXRIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt</description>
+              <name>RTRIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt</description>
+              <name>RORRIS</name>
+            </field>
+          </fields>
+          <name>SSPRIS</name>
+          <resetValue>0x00000008</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>Masked interrupt status register, SSPMIS on page 3-11</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt</description>
+              <name>TXMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt</description>
+              <name>RXMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt</description>
+              <name>RTMIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt</description>
+              <name>RORMIS</name>
+            </field>
+          </fields>
+          <name>SSPMIS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>Interrupt clear register, SSPICR on page 3-11</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Clears the SSPRTINTR interrupt</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>RTIC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Clears the SSPRORINTR interrupt</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>RORIC</name>
+            </field>
+          </fields>
+          <name>SSPICR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0024</addressOffset>
+          <description>DMA control register, SSPDMACR on page 3-12</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.</description>
+              <name>TXDMAE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.</description>
+              <name>RXDMAE</name>
+            </field>
+          </fields>
+          <name>SSPDMACR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0fe0</addressOffset>
+          <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>These bits read back as 0x22</description>
+              <name>PARTNUMBER0</name>
+            </field>
+          </fields>
+          <name>SSPPERIPHID0</name>
+          <resetValue>0x00000022</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0fe4</addressOffset>
+          <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:4]</bitRange>
+              <description>These bits read back as 0x1</description>
+              <name>DESIGNER0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:0]</bitRange>
+              <description>These bits read back as 0x0</description>
+              <name>PARTNUMBER1</name>
+            </field>
+          </fields>
+          <name>SSPPERIPHID1</name>
+          <resetValue>0x00000010</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0fe8</addressOffset>
+          <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:4]</bitRange>
+              <description>These bits return the peripheral revision</description>
+              <name>REVISION</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:0]</bitRange>
+              <description>These bits read back as 0x4</description>
+              <name>DESIGNER1</name>
+            </field>
+          </fields>
+          <name>SSPPERIPHID2</name>
+          <resetValue>0x00000034</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0fec</addressOffset>
+          <description>Peripheral identification registers, SSPPeriphID0-3 on page 3-13</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>These bits read back as 0x00</description>
+              <name>CONFIGURATION</name>
+            </field>
+          </fields>
+          <name>SSPPERIPHID3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0ff0</addressOffset>
+          <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>These bits read back as 0x0D</description>
+              <name>SSPPCELLID0</name>
+            </field>
+          </fields>
+          <name>SSPPCELLID0</name>
+          <resetValue>0x0000000d</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0ff4</addressOffset>
+          <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>These bits read back as 0xF0</description>
+              <name>SSPPCELLID1</name>
+            </field>
+          </fields>
+          <name>SSPPCELLID1</name>
+          <resetValue>0x000000f0</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0ff8</addressOffset>
+          <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>These bits read back as 0x05</description>
+              <name>SSPPCELLID2</name>
+            </field>
+          </fields>
+          <name>SSPPCELLID2</name>
+          <resetValue>0x00000005</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0ffc</addressOffset>
+          <description>PrimeCell identification registers, SSPPCellID0-3 on page 3-16</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>These bits read back as 0xB1</description>
+              <name>SSPPCELLID3</name>
+            </field>
+          </fields>
+          <name>SSPPCELLID3</name>
+          <resetValue>0x000000b1</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral derivedFrom="SPI0">
+      <baseAddress>0x40040000</baseAddress>
+      <interrupt>
+        <name>SPI1_IRQ</name>
+        <value>19</value>
+      </interrupt>
+      <name>SPI1</name>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x0100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40044000</baseAddress>
+      <description>DW_apb_i2c address block\n\n
+        List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\n\n
+        IC_ULTRA_FAST_MODE ................ 0x0\n
+        IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n
+        IC_UFM_SCL_LOW_COUNT .............. 0x0008\n
+        IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n
+        IC_TX_TL .......................... 0x0\n
+        IC_TX_CMD_BLOCK ................... 0x1\n
+        IC_HAS_DMA ........................ 0x1\n
+        IC_HAS_ASYNC_FIFO ................. 0x0\n
+        IC_SMBUS_ARP ...................... 0x0\n
+        IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n
+        IC_INTR_IO ........................ 0x1\n
+        IC_MASTER_MODE .................... 0x1\n
+        IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n
+        IC_INTR_POL ....................... 0x1\n
+        IC_OPTIONAL_SAR ................... 0x0\n
+        IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n
+        IC_DEFAULT_SLAVE_ADDR ............. 0x055\n
+        IC_DEFAULT_HS_SPKLEN .............. 0x1\n
+        IC_FS_SCL_HIGH_COUNT .............. 0x0006\n
+        IC_HS_SCL_LOW_COUNT ............... 0x0008\n
+        IC_DEVICE_ID_VALUE ................ 0x0\n
+        IC_10BITADDR_MASTER ............... 0x0\n
+        IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n
+        IC_DEFAULT_FS_SPKLEN .............. 0x7\n
+        IC_ADD_ENCODED_PARAMS ............. 0x0\n
+        IC_DEFAULT_SDA_HOLD ............... 0x000001\n
+        IC_DEFAULT_SDA_SETUP .............. 0x64\n
+        IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n
+        IC_CLOCK_PERIOD ................... 100\n
+        IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n
+        IC_RESTART_EN ..................... 0x1\n
+        IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n
+        IC_BUS_CLEAR_FEATURE .............. 0x0\n
+        IC_CAP_LOADING .................... 100\n
+        IC_FS_SCL_LOW_COUNT ............... 0x000d\n
+        APB_DATA_WIDTH .................... 32\n
+        IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n
+        IC_SLV_DATA_NACK_ONLY ............. 0x1\n
+        IC_10BITADDR_SLAVE ................ 0x0\n
+        IC_CLK_TYPE ....................... 0x0\n
+        IC_SMBUS_UDID_MSB ................. 0x0\n
+        IC_SMBUS_SUSPEND_ALERT ............ 0x0\n
+        IC_HS_SCL_HIGH_COUNT .............. 0x0006\n
+        IC_SLV_RESTART_DET_EN ............. 0x1\n
+        IC_SMBUS .......................... 0x0\n
+        IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n
+        IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n
+        IC_USE_COUNTS ..................... 0x0\n
+        IC_RX_BUFFER_DEPTH ................ 16\n
+        IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n
+        IC_RX_FULL_HLD_BUS_EN ............. 0x1\n
+        IC_SLAVE_DISABLE .................. 0x1\n
+        IC_RX_TL .......................... 0x0\n
+        IC_DEVICE_ID ...................... 0x0\n
+        IC_HC_COUNT_VALUES ................ 0x0\n
+        I2C_DYNAMIC_TAR_UPDATE ............ 0\n
+        IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n
+        IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n
+        IC_HS_MASTER_CODE ................. 0x1\n
+        IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n
+        IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n
+        IC_SS_SCL_HIGH_COUNT .............. 0x0028\n
+        IC_SS_SCL_LOW_COUNT ............... 0x002f\n
+        IC_MAX_SPEED_MODE ................. 0x2\n
+        IC_STAT_FOR_CLK_STRETCH ........... 0x0\n
+        IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n
+        IC_DEFAULT_UFM_SPKLEN ............. 0x1\n
+        IC_TX_BUFFER_DEPTH ................ 16</description>
+      <interrupt>
+        <name>I2C0_IRQ</name>
+        <value>23</value>
+      </interrupt>
+      <name>I2C0</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
+            Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Master issues the STOP_DET interrupt irrespective of whether master is active or not</description>
+              <name>STOP_DET_IF_MASTER_ACTIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <description>This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n
+                Reset value: 0x0.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Overflow when RX_FIFO is full</description>
+                  <name>DISABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Hold bus when RX_FIFO is full</description>
+                  <name>ENABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RX_FIFO_FULL_HLD_CTRL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <description>This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\n\n
+                Reset value: 0x0.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Default behaviour of TX_EMPTY interrupt</description>
+                  <name>DISABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Controlled generation of TX_EMPTY interrupt</description>
+                  <name>ENABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TX_EMPTY_CTRL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>In slave mode: - 1'b1:  issues the STOP_DET interrupt only when it is addressed. - 1'b0:  issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\n\n
+                NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR).</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>slave issues STOP_DET intr always</description>
+                  <name>DISABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>slave issues STOP_DET intr only if addressed</description>
+                  <name>ENABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>STOP_DET_IFADDRESSED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\n\n
+                If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.\n\n
+                NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Slave mode is enabled</description>
+                  <name>SLAVE_ENABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Slave mode is disabled</description>
+                  <name>SLAVE_DISABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IC_SLAVE_DISABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n
+                Reset value: ENABLED</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Master restart disabled</description>
+                  <name>DISABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Master restart enabled</description>
+                  <name>ENABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IC_RESTART_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Master 7Bit addressing mode</description>
+                  <name>ADDR_7BITS</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Master 10Bit addressing mode</description>
+                  <name>ADDR_10BITS</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IC_10BITADDR_MASTER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Slave 7Bit addressing</description>
+                  <name>ADDR_7BITS</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Slave 10Bit addressing</description>
+                  <name>ADDR_10BITS</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IC_10BITADDR_SLAVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:1]</bitRange>
+              <description>These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\n\n
+                This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.\n\n
+                1: standard mode (100 kbit/s)\n\n
+                2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s)\n\n
+                3: high speed mode (3.4 Mbit/s)\n\n
+                Note: This field is not applicable when IC_ULTRA_FAST_MODE=1</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Standard Speed mode of operation</description>
+                  <name>STANDARD</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Fast or Fast Plus mode of operation</description>
+                  <name>FAST</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>High Speed mode of operation</description>
+                  <name>HIGH</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>SPEED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>This bit controls whether the DW_apb_i2c master is enabled.\n\n
+                NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Master mode is disabled</description>
+                  <name>DISABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Master mode is enabled</description>
+                  <name>ENABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>MASTER_MODE</name>
+            </field>
+          </fields>
+          <name>IC_CON</name>
+          <resetValue>0x00000065</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>I2C Target Address Register\n\n
+            This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.\n\n
+            Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Disables programming of GENERAL_CALL or START_BYTE transmission</description>
+                  <name>DISABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Enables programming of GENERAL_CALL or START_BYTE transmission</description>
+                  <name>ENABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>SPECIAL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>GENERAL_CALL byte transmission</description>
+                  <name>GENERAL_CALL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>START byte transmission</description>
+                  <name>START_BYTE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>GC_OR_START</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\n\n
+                If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave.</description>
+              <name>IC_TAR</name>
+            </field>
+          </fields>
+          <name>IC_TAR</name>
+          <resetValue>0x00000055</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>I2C Slave Address Register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n
+                This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
+                Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to &lt;&lt;table_I2C_firstbyte_bit_defs&gt;&gt; for a complete list of these reserved values.</description>
+              <name>IC_SAR</name>
+            </field>
+          </fields>
+          <name>IC_SAR</name>
+          <resetValue>0x00000055</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.\n\n
+            The size of the register changes as follows:\n\n
+            Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\n\n
+                Reset value : 0x0\n\n
+                NOTE:  In case of APB_DATA_WIDTH=8,\n\n
+                1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.\n\n
+                2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).\n\n
+                3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Sequential data byte received</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Non sequential data byte received</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FIRST_DATA_BYTE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>This bit controls whether a RESTART is issued before the byte is sent or received.\n\n
+                1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n
+                0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Don't Issue RESTART before this command</description>
+                  <name>DISABLE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Issue RESTART before this command</description>
+                  <name>ENABLE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>RESTART</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <description>This bit controls whether a STOP is issued after the byte is sent or received.\n\n
+                - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Don't Issue STOP after this command</description>
+                  <name>DISABLE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Issue STOP after this command</description>
+                  <name>ENABLE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>STOP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <description>This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\n\n
+                When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.\n\n
+                When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Master Write Command</description>
+                  <name>WRITE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Master Read Command</description>
+                  <name>READ</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>CMD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\n\n
+                Reset value: 0x0</description>
+              <name>DAT</name>
+            </field>
+          </fields>
+          <name>IC_DATA_CMD</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>Standard Speed I2C Clock SCL High Count Register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
+                This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
+                The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.\n\n
+                NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.</description>
+              <name>IC_SS_SCL_HCNT</name>
+            </field>
+          </fields>
+          <name>IC_SS_SCL_HCNT</name>
+          <resetValue>0x00000028</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>Standard Speed I2C Clock SCL Low Count Register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\n\n
+                This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
+                The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed.</description>
+              <name>IC_SS_SCL_LCNT</name>
+            </field>
+          </fields>
+          <name>IC_SS_SCL_LCNT</name>
+          <resetValue>0x0000002f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
+                This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
+                The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.</description>
+              <name>IC_FS_SCL_HCNT</name>
+            </field>
+          </fields>
+          <name>IC_FS_SCL_HCNT</name>
+          <resetValue>0x00000006</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n
+                This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.\n\n
+                This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n
+                The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8.</description>
+              <name>IC_FS_SCL_LCNT</name>
+            </field>
+          </fields>
+          <name>IC_FS_SCL_LCNT</name>
+          <resetValue>0x0000000d</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x002c</addressOffset>
+          <description>I2C Interrupt Status Register\n\n
+            Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>R_RESTART_DET interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>R_RESTART_DET interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>R_RESTART_DET</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <description>See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>R_GEN_CALL interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>R_GEN_CALL interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>R_GEN_CALL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <description>See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>R_START_DET interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>R_START_DET interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>R_START_DET</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>R_STOP_DET interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>R_STOP_DET interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>R_STOP_DET</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>R_ACTIVITY interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>R_ACTIVITY interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>R_ACTIVITY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>R_RX_DONE interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>R_RX_DONE interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>R_RX_DONE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>R_TX_ABRT interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>R_TX_ABRT interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>R_TX_ABRT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <description>See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>R_RD_REQ interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>R_RD_REQ interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>R_RD_REQ</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>R_TX_EMPTY interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>R_TX_EMPTY interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>R_TX_EMPTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>R_TX_OVER interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>R_TX_OVER interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>R_TX_OVER</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>R_RX_FULL interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>R_RX_FULL interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>R_RX_FULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>R_RX_OVER interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>R_RX_OVER interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>R_RX_OVER</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>RX_UNDER interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>RX_UNDER interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>R_RX_UNDER</name>
+            </field>
+          </fields>
+          <name>IC_INTR_STAT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0030</addressOffset>
+          <description>I2C Interrupt Mask Register.\n\n
+            These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>RESTART_DET interrupt is masked</description>
+                  <name>ENABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>RESTART_DET interrupt is unmasked</description>
+                  <name>DISABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>M_RESTART_DET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n
+                Reset value: 0x1</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>GEN_CALL interrupt is masked</description>
+                  <name>ENABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>GEN_CALL interrupt is unmasked</description>
+                  <name>DISABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>M_GEN_CALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>START_DET interrupt is masked</description>
+                  <name>ENABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>START_DET interrupt is unmasked</description>
+                  <name>DISABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>M_START_DET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <description>This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>STOP_DET interrupt is masked</description>
+                  <name>ENABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>STOP_DET interrupt is unmasked</description>
+                  <name>DISABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>M_STOP_DET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <description>This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>ACTIVITY interrupt is masked</description>
+                  <name>ENABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>ACTIVITY interrupt is unmasked</description>
+                  <name>DISABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>M_ACTIVITY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n
+                Reset value: 0x1</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>RX_DONE interrupt is masked</description>
+                  <name>ENABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>RX_DONE interrupt is unmasked</description>
+                  <name>DISABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>M_RX_DONE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n
+                Reset value: 0x1</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>TX_ABORT interrupt is masked</description>
+                  <name>ENABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>TX_ABORT interrupt is unmasked</description>
+                  <name>DISABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>M_TX_ABRT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n
+                Reset value: 0x1</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>RD_REQ interrupt is masked</description>
+                  <name>ENABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>RD_REQ interrupt is unmasked</description>
+                  <name>DISABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>M_RD_REQ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n
+                Reset value: 0x1</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>TX_EMPTY interrupt is masked</description>
+                  <name>ENABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>TX_EMPTY interrupt is unmasked</description>
+                  <name>DISABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>M_TX_EMPTY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n
+                Reset value: 0x1</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>TX_OVER interrupt is masked</description>
+                  <name>ENABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>TX_OVER interrupt is unmasked</description>
+                  <name>DISABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>M_TX_OVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n
+                Reset value: 0x1</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>RX_FULL interrupt is masked</description>
+                  <name>ENABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>RX_FULL interrupt is unmasked</description>
+                  <name>DISABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>M_RX_FULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n
+                Reset value: 0x1</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>RX_OVER interrupt is masked</description>
+                  <name>ENABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>RX_OVER interrupt is unmasked</description>
+                  <name>DISABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>M_RX_OVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n
+                Reset value: 0x1</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>RX_UNDER interrupt is masked</description>
+                  <name>ENABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>RX_UNDER interrupt is unmasked</description>
+                  <name>DISABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>M_RX_UNDER</name>
+            </field>
+          </fields>
+          <name>IC_INTR_MASK</name>
+          <resetValue>0x000008ff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0034</addressOffset>
+          <description>I2C Raw Interrupt Status Register\n\n
+            Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.\n\n
+                Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>RESTART_DET interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>RESTART_DET interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RESTART_DET</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>GEN_CALL interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>GEN_CALL interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>GEN_CALL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>START_DET interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>START_DET interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>START_DET</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n
+                In Slave Mode: - If IC_CON[7]=1'b1  (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1  (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0  (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>STOP_DET interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>STOP_DET interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>STOP_DET</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>RAW_INTR_ACTIVITY interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>RAW_INTR_ACTIVITY interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ACTIVITY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <description>When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>RX_DONE interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>RX_DONE interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RX_DONE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <description>This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.\n\n
+                Note:  The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>TX_ABRT interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>TX_ABRT interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TX_ABRT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <description>This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>RD_REQ interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>RD_REQ interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RD_REQ</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.\n\n
+                Reset value: 0x0.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>TX_EMPTY interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>TX_EMPTY interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TX_EMPTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>TX_OVER interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>TX_OVER interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TX_OVER</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>RX_FULL interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>RX_FULL interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RX_FULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
+                Note:  If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>RX_OVER interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>RX_OVER interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RX_OVER</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>RX_UNDER interrupt is inactive</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>RX_UNDER interrupt is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RX_UNDER</name>
+            </field>
+          </fields>
+          <name>IC_RAW_INTR_STAT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0038</addressOffset>
+          <description>I2C Receive FIFO Threshold Register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Receive FIFO Threshold Level.\n\n
+                Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.</description>
+              <name>RX_TL</name>
+            </field>
+          </fields>
+          <name>IC_RX_TL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x003c</addressOffset>
+          <description>I2C Transmit FIFO Threshold Register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Transmit FIFO Threshold Level.\n\n
+                Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.</description>
+              <name>TX_TL</name>
+            </field>
+          </fields>
+          <name>IC_TX_TL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0040</addressOffset>
+          <description>Clear Combined and Individual Interrupt Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n
+                Reset value: 0x0</description>
+              <name>CLR_INTR</name>
+            </field>
+          </fields>
+          <name>IC_CLR_INTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0044</addressOffset>
+          <description>Clear RX_UNDER Interrupt Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\n\n
+                Reset value: 0x0</description>
+              <name>CLR_RX_UNDER</name>
+            </field>
+          </fields>
+          <name>IC_CLR_RX_UNDER</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0048</addressOffset>
+          <description>Clear RX_OVER Interrupt Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\n\n
+                Reset value: 0x0</description>
+              <name>CLR_RX_OVER</name>
+            </field>
+          </fields>
+          <name>IC_CLR_RX_OVER</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x004c</addressOffset>
+          <description>Clear TX_OVER Interrupt Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\n\n
+                Reset value: 0x0</description>
+              <name>CLR_TX_OVER</name>
+            </field>
+          </fields>
+          <name>IC_CLR_TX_OVER</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0050</addressOffset>
+          <description>Clear RD_REQ Interrupt Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\n\n
+                Reset value: 0x0</description>
+              <name>CLR_RD_REQ</name>
+            </field>
+          </fields>
+          <name>IC_CLR_RD_REQ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0054</addressOffset>
+          <description>Clear TX_ABRT Interrupt Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n
+                Reset value: 0x0</description>
+              <name>CLR_TX_ABRT</name>
+            </field>
+          </fields>
+          <name>IC_CLR_TX_ABRT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0058</addressOffset>
+          <description>Clear RX_DONE Interrupt Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\n\n
+                Reset value: 0x0</description>
+              <name>CLR_RX_DONE</name>
+            </field>
+          </fields>
+          <name>IC_CLR_RX_DONE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x005c</addressOffset>
+          <description>Clear ACTIVITY Interrupt Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.\n\n
+                Reset value: 0x0</description>
+              <name>CLR_ACTIVITY</name>
+            </field>
+          </fields>
+          <name>IC_CLR_ACTIVITY</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0060</addressOffset>
+          <description>Clear STOP_DET Interrupt Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\n\n
+                Reset value: 0x0</description>
+              <name>CLR_STOP_DET</name>
+            </field>
+          </fields>
+          <name>IC_CLR_STOP_DET</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0064</addressOffset>
+          <description>Clear START_DET Interrupt Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\n\n
+                Reset value: 0x0</description>
+              <name>CLR_START_DET</name>
+            </field>
+          </fields>
+          <name>IC_CLR_START_DET</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0068</addressOffset>
+          <description>Clear GEN_CALL Interrupt Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.\n\n
+                Reset value: 0x0</description>
+              <name>CLR_GEN_CALL</name>
+            </field>
+          </fields>
+          <name>IC_CLR_GEN_CALL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x006c</addressOffset>
+          <description>I2C Enable Register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value:  IC_TX_CMD_BLOCK_DEFAULT</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Tx Command execution not blocked</description>
+                  <name>NOT_BLOCKED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Tx Command execution blocked</description>
+                  <name>BLOCKED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TX_CMD_BLOCK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.\n\n
+                For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>ABORT operation not in progress</description>
+                  <name>DISABLE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>ABORT operation in progress</description>
+                  <name>ENABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABORT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.\n\n
+                When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.\n\n
+                In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>I2C is disabled</description>
+                  <name>DISABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>I2C is enabled</description>
+                  <name>ENABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENABLE</name>
+            </field>
+          </fields>
+          <name>IC_ENABLE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0070</addressOffset>
+          <description>I2C Status Register\n\n
+            This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.\n\n
+            When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Slave is idle</description>
+                  <name>IDLE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Slave not idle</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>SLV_ACTIVITY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Master is idle</description>
+                  <name>IDLE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Master not idle</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>MST_ACTIVITY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Rx FIFO not full</description>
+                  <name>NOT_FULL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Rx FIFO is full</description>
+                  <name>FULL</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RFF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Rx FIFO is empty</description>
+                  <name>EMPTY</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Rx FIFO not empty</description>
+                  <name>NOT_EMPTY</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RFNE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Tx FIFO not empty</description>
+                  <name>NON_EMPTY</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Tx FIFO is empty</description>
+                  <name>EMPTY</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TFE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Tx FIFO is full</description>
+                  <name>FULL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Tx FIFO not full</description>
+                  <name>NOT_FULL</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TFNF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>I2C Activity Status. Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>I2C is idle</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>I2C is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ACTIVITY</name>
+            </field>
+          </fields>
+          <name>IC_STATUS</name>
+          <resetValue>0x00000006</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0074</addressOffset>
+          <description>I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:0]</bitRange>
+              <description>Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.\n\n
+                Reset value: 0x0</description>
+              <name>TXFLR</name>
+            </field>
+          </fields>
+          <name>IC_TXFLR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0078</addressOffset>
+          <description>I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:0]</bitRange>
+              <description>Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.\n\n
+                Reset value: 0x0</description>
+              <name>RXFLR</name>
+            </field>
+          </fields>
+          <name>IC_RXFLR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x007c</addressOffset>
+          <description>I2C SDA Hold Time Length Register\n\n
+            The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n
+            The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n
+            Writes to this register succeed only when IC_ENABLE[0]=0.\n\n
+            The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.\n\n
+            The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:16]</bitRange>
+              <description>Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.\n\n
+                Reset value: IC_DEFAULT_SDA_HOLD[23:16].</description>
+              <name>IC_SDA_RX_HOLD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.\n\n
+                Reset value: IC_DEFAULT_SDA_HOLD[15:0].</description>
+              <name>IC_SDA_TX_HOLD</name>
+            </field>
+          </fields>
+          <name>IC_SDA_HOLD</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0080</addressOffset>
+          <description>I2C Transmit Abort Source Register\n\n
+            This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).\n\n
+            Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:23]</bitRange>
+              <description>This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master-Transmitter or Slave-Transmitter</description>
+              <name>TX_FLUSH_CNT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <description>This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master-Transmitter</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Transfer abort detected by master- scenario not present</description>
+                  <name>ABRT_USER_ABRT_VOID</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Transfer abort detected by master</description>
+                  <name>ABRT_USER_ABRT_GENERATED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_USER_ABRT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <description>1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Slave-Transmitter</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Slave trying to transmit to remote master in read mode- scenario not present</description>
+                  <name>ABRT_SLVRD_INTX_VOID</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Slave trying to transmit to remote master in read mode</description>
+                  <name>ABRT_SLVRD_INTX_GENERATED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_SLVRD_INTX</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <description>This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note:  Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Slave-Transmitter</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Slave lost arbitration to remote master- scenario not present</description>
+                  <name>ABRT_SLV_ARBLOST_VOID</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Slave lost arbitration to remote master</description>
+                  <name>ABRT_SLV_ARBLOST_GENERATED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_SLV_ARBLOST</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Slave-Transmitter</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Slave flushes existing data in TX-FIFO upon getting read command- scenario not present</description>
+                  <name>ABRT_SLVFLUSH_TXFIFO_VOID</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Slave flushes existing data in TX-FIFO upon getting read command</description>
+                  <name>ABRT_SLVFLUSH_TXFIFO_GENERATED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_SLVFLUSH_TXFIFO</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master-Transmitter or Slave-Transmitter</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Master or Slave-Transmitter lost arbitration- scenario not present</description>
+                  <name>ABRT_LOST_VOID</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Master or Slave-Transmitter lost arbitration</description>
+                  <name>ABRT_LOST_GENERATED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ARB_LOST</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <description>This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>User initiating master operation when MASTER disabled- scenario not present</description>
+                  <name>ABRT_MASTER_DIS_VOID</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>User initiating master operation when MASTER disabled</description>
+                  <name>ABRT_MASTER_DIS_GENERATED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_MASTER_DIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <description>This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master-Receiver</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Master not trying to read in 10Bit addressing mode when RESTART disabled</description>
+                  <name>ABRT_10B_RD_VOID</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Master trying to read in 10Bit addressing mode when RESTART disabled</description>
+                  <name>ABRT_10B_RD_GENERATED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_10B_RD_NORSTRT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>User trying to send START byte when RESTART disabled- scenario not present</description>
+                  <name>ABRT_SBYTE_NORSTRT_VOID</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>User trying to send START byte when RESTART disabled</description>
+                  <name>ABRT_SBYTE_NORSTRT_GENERATED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_SBYTE_NORSTRT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>User trying to switch Master to HS mode when RESTART disabled- scenario not present</description>
+                  <name>ABRT_HS_NORSTRT_VOID</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>User trying to switch Master to HS mode when RESTART disabled</description>
+                  <name>ABRT_HS_NORSTRT_GENERATED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_HS_NORSTRT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <description>This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>ACK detected for START byte- scenario not present</description>
+                  <name>ABRT_SBYTE_ACKDET_VOID</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>ACK detected for START byte</description>
+                  <name>ABRT_SBYTE_ACKDET_GENERATED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_SBYTE_ACKDET</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <description>This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>HS Master code ACKed in HS Mode- scenario not present</description>
+                  <name>ABRT_HS_ACK_VOID</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>HS Master code ACKed in HS Mode</description>
+                  <name>ABRT_HS_ACK_GENERATED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_HS_ACKDET</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <description>This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master-Transmitter</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>GCALL is followed by read from bus-scenario not present</description>
+                  <name>ABRT_GCALL_READ_VOID</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>GCALL is followed by read from bus</description>
+                  <name>ABRT_GCALL_READ_GENERATED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_GCALL_READ</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master-Transmitter</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>GCALL not ACKed by any slave-scenario not present</description>
+                  <name>ABRT_GCALL_NOACK_VOID</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>GCALL not ACKed by any slave</description>
+                  <name>ABRT_GCALL_NOACK_GENERATED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_GCALL_NOACK</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master-Transmitter</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Transmitted data non-ACKed by addressed slave-scenario not present</description>
+                  <name>ABRT_TXDATA_NOACK_VOID</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Transmitted data not ACKed by addressed slave</description>
+                  <name>ABRT_TXDATA_NOACK_GENERATED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_TXDATA_NOACK</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>This abort is not generated</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Byte 2 of 10Bit Address not ACKed by any slave</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_10ADDR2_NOACK</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>This abort is not generated</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Byte 1 of 10Bit Address not ACKed by any slave</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_10ADDR1_NOACK</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\n\n
+                Reset value: 0x0\n\n
+                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>This abort is not generated</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>This abort is generated because of NOACK for 7-bit address</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ABRT_7B_ADDR_NOACK</name>
+            </field>
+          </fields>
+          <name>IC_TX_ABRT_SOURCE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0084</addressOffset>
+          <description>Generate Slave Data NACK Register\n\n
+            The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.\n\n
+            A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\n\n
+                When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Slave receiver generates NACK normally</description>
+                  <name>DISABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Slave receiver generates NACK upon data reception only</description>
+                  <name>ENABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>NACK</name>
+            </field>
+          </fields>
+          <name>IC_SLV_DATA_NACK_ONLY</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0088</addressOffset>
+          <description>DMA Control Register\n\n
+            The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>transmit FIFO DMA channel disabled</description>
+                  <name>DISABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Transmit FIFO DMA channel enabled</description>
+                  <name>ENABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TDMAE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Receive FIFO DMA channel disabled</description>
+                  <name>DISABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Receive FIFO DMA channel enabled</description>
+                  <name>ENABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RDMAE</name>
+            </field>
+          </fields>
+          <name>IC_DMA_CR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x008c</addressOffset>
+          <description>DMA Transmit Data Level Register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <description>Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n
+                Reset value: 0x0</description>
+              <name>DMATDL</name>
+            </field>
+          </fields>
+          <name>IC_DMA_TDLR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0090</addressOffset>
+          <description>I2C Receive Data Level Register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <description>Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\n\n
+                Reset value: 0x0</description>
+              <name>DMARDL</name>
+            </field>
+          </fields>
+          <name>IC_DMA_RDLR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0094</addressOffset>
+          <description>I2C SDA Setup Register\n\n
+            This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.\n\n
+            Writes to this register succeed only when IC_ENABLE[0] = 0.\n\n
+            Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.</description>
+              <name>SDA_SETUP</name>
+            </field>
+          </fields>
+          <name>IC_SDA_SETUP</name>
+          <resetValue>0x00000064</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0098</addressOffset>
+          <description>I2C ACK General Call Register\n\n
+            The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.\n\n
+            This register is applicable only when the DW_apb_i2c is in slave mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe).</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Generate NACK for a General Call</description>
+                  <name>DISABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Generate ACK for a General Call</description>
+                  <name>ENABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ACK_GEN_CALL</name>
+            </field>
+          </fields>
+          <name>IC_ACK_GENERAL_CALL</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x009c</addressOffset>
+          <description>I2C Enable Status Register\n\n
+            The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.\n\n
+            If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.\n\n
+            If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.\n\n
+            Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.\n\n
+                Note:  If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.\n\n
+                When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.\n\n
+                Note:  The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Slave RX Data is not lost</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Slave RX Data is lost</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>SLV_RX_DATA_LOST</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:\n\n
+                (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;\n\n
+                OR,\n\n
+                (b) address and data bytes of the Slave-Receiver operation from a remote master.\n\n
+                When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.\n\n
+                Note:  If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.\n\n
+                When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.\n\n
+                Note:  The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Slave is disabled when it is idle</description>
+                  <name>INACTIVE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Slave is disabled when it is active</description>
+                  <name>ACTIVE</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>SLV_DISABLED_WHILE_BUSY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note:  The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n
+                Reset value: 0x0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>I2C disabled</description>
+                  <name>DISABLED</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>I2C enabled</description>
+                  <name>ENABLED</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>IC_EN</name>
+            </field>
+          </fields>
+          <name>IC_ENABLE_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a0</addressOffset>
+          <description>I2C SS, FS or FM+ spike suppression limit\n\n
+            This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'.</description>
+              <name>IC_FS_SPKLEN</name>
+            </field>
+          </fields>
+          <name>IC_FS_SPKLEN</name>
+          <resetValue>0x00000007</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a8</addressOffset>
+          <description>Clear RESTART_DET Interrupt Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\n\n
+                Reset value: 0x0</description>
+              <name>CLR_RESTART_DET</name>
+            </field>
+          </fields>
+          <name>IC_CLR_RESTART_DET</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f4</addressOffset>
+          <description>Component Parameter Register 1\n\n
+            Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:16]</bitRange>
+              <description>TX Buffer Depth = 16</description>
+              <name>TX_BUFFER_DEPTH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:8]</bitRange>
+              <description>RX Buffer Depth = 16</description>
+              <name>RX_BUFFER_DEPTH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Encoded parameters not visible</description>
+              <name>ADD_ENCODED_PARAMS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <description>DMA handshaking signals are enabled</description>
+              <name>HAS_DMA</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <description>COMBINED Interrupt outputs</description>
+              <name>INTR_IO</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Programmable count values for each mode.</description>
+              <name>HC_COUNT_VALUES</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:2]</bitRange>
+              <description>MAX SPEED MODE = FAST MODE</description>
+              <name>MAX_SPEED_MODE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:0]</bitRange>
+              <description>APB data bus width is 32 bits</description>
+              <name>APB_DATA_WIDTH</name>
+            </field>
+          </fields>
+          <name>IC_COMP_PARAM_1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f8</addressOffset>
+          <description>I2C Component Version Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:0]</bitRange>
+              <name>IC_COMP_VERSION</name>
+            </field>
+          </fields>
+          <name>IC_COMP_VERSION</name>
+          <resetValue>0x3230312a</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00fc</addressOffset>
+          <description>I2C Component Type Register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:0]</bitRange>
+              <description>Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number.</description>
+              <name>IC_COMP_TYPE</name>
+            </field>
+          </fields>
+          <name>IC_COMP_TYPE</name>
+          <resetValue>0x44570140</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral derivedFrom="I2C0">
+      <baseAddress>0x40048000</baseAddress>
+      <interrupt>
+        <name>I2C1_IRQ</name>
+        <value>24</value>
+      </interrupt>
+      <name>I2C1</name>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x4004c000</baseAddress>
+      <description>Control and data interface to SAR ADC</description>
+      <interrupt>
+        <name>ADC_IRQ_FIFO</name>
+        <value>22</value>
+      </interrupt>
+      <name>ADC</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>ADC Control and Status</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:16]</bitRange>
+              <description>Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n
+                Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.\n
+                The first channel to be sampled will be the one currently indicated by AINSEL.\n
+                AINSEL will be updated after each conversion with the newly-selected channel.</description>
+              <name>RROBIN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:12]</bitRange>
+              <description>Select analog mux input. Updated automatically in round-robin mode.</description>
+              <name>AINSEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Some past ADC conversion encountered an error. Write 1 to clear.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>ERR_STICKY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>The most recent ADC conversion encountered an error; result is undefined or noisy.</description>
+              <name>ERR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.\n
+                0 whilst conversion in progress.</description>
+              <name>READY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.</description>
+              <name>START_MANY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Start a single conversion. Self-clearing. Ignored if start_many is asserted.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>START_ONCE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Power on temperature sensor. 1 - enabled. 0 - disabled.</description>
+              <name>TS_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Power on ADC and enable its clock.\n
+                1 - enabled. 0 - disabled.</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Result of most recent ADC conversion</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:0]</bitRange>
+              <name>RESULT</name>
+            </field>
+          </fields>
+          <name>RESULT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>FIFO control and status</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:24]</bitRange>
+              <description>DREQ/IRQ asserted when level &gt;= threshold</description>
+              <name>THRESH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:16]</bitRange>
+              <description>The number of conversion results currently waiting in the FIFO</description>
+              <name>LEVEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>1 if the FIFO has been overflowed. Write 1 to clear.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>OVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>1 if the FIFO has been underflowed. Write 1 to clear.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>UNDER</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>FULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>EMPTY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>If 1: assert DMA requests when FIFO contains data</description>
+              <name>DREQ_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>If 1: conversion error bit appears in the FIFO alongside the result</description>
+              <name>ERR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.</description>
+              <name>SHIFT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>If 1: write result to the FIFO after each conversion.</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>FCS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>Conversion result FIFO</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <description>1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted.</description>
+              <name>ERR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:0]</bitRange>
+              <name>VAL</name>
+            </field>
+          </fields>
+          <name>FIFO</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>Clock divider. If non-zero, CS_START_MANY will start conversions\n
+            at regular intervals rather than back-to-back.\n
+            The divider is reset when either of these fields are written.\n
+            Total period is 1 + INT + FRAC / 256</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:8]</bitRange>
+              <description>Integer part of clock divisor.</description>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Fractional part of clock divisor. First-order delta-sigma.</description>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>DIV</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>Raw Interrupts</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Triggered when the sample FIFO reaches a certain level.\n
+                This level can be programmed via the FCS_THRESH field.</description>
+              <name>FIFO</name>
+            </field>
+          </fields>
+          <name>INTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>Interrupt Enable</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Triggered when the sample FIFO reaches a certain level.\n
+                This level can be programmed via the FCS_THRESH field.</description>
+              <name>FIFO</name>
+            </field>
+          </fields>
+          <name>INTE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>Interrupt Force</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Triggered when the sample FIFO reaches a certain level.\n
+                This level can be programmed via the FCS_THRESH field.</description>
+              <name>FIFO</name>
+            </field>
+          </fields>
+          <name>INTF</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>Interrupt status after masking &amp; forcing</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Triggered when the sample FIFO reaches a certain level.\n
+                This level can be programmed via the FCS_THRESH field.</description>
+              <name>FIFO</name>
+            </field>
+          </fields>
+          <name>INTS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>2</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40050000</baseAddress>
+      <description>Simple PWM</description>
+      <interrupt>
+        <name>PWM_IRQ_WRAP</name>
+        <value>4</value>
+      </interrupt>
+      <name>PWM</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Control and status register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Advance the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running\n
+                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_ADV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Retard the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_RET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Free-running counting at rate dictated by fractional divider</description>
+                  <name>div</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Fractional divider operation is gated by the PWM B pin.</description>
+                  <name>level</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each rising edge of the PWM B pin.</description>
+                  <name>rise</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each falling edge of the PWM B pin.</description>
+                  <name>fall</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DIVMODE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Invert output B</description>
+              <name>B_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Invert output A</description>
+              <name>A_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+              <name>PH_CORRECT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enable the PWM channel.</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH0_CSR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>INT and FRAC form a fixed-point fractional number.\n
+            Counting rate is system clock frequency divided by this number.\n
+            Fractional division uses simple 1st-order sigma-delta.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:4]</bitRange>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>CH0_DIV</name>
+          <resetValue>0x00000010</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>Direct access to the PWM counter</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH0_CTR</name>
+            </field>
+          </fields>
+          <name>CH0_CTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>Counter compare values</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <name>B</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>A</name>
+            </field>
+          </fields>
+          <name>CH0_CC</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>Counter wrap value</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH0_TOP</name>
+            </field>
+          </fields>
+          <name>CH0_TOP</name>
+          <resetValue>0x0000ffff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>Control and status register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Advance the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running\n
+                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_ADV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Retard the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_RET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Free-running counting at rate dictated by fractional divider</description>
+                  <name>div</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Fractional divider operation is gated by the PWM B pin.</description>
+                  <name>level</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each rising edge of the PWM B pin.</description>
+                  <name>rise</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each falling edge of the PWM B pin.</description>
+                  <name>fall</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DIVMODE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Invert output B</description>
+              <name>B_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Invert output A</description>
+              <name>A_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+              <name>PH_CORRECT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enable the PWM channel.</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH1_CSR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>INT and FRAC form a fixed-point fractional number.\n
+            Counting rate is system clock frequency divided by this number.\n
+            Fractional division uses simple 1st-order sigma-delta.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:4]</bitRange>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>CH1_DIV</name>
+          <resetValue>0x00000010</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>Direct access to the PWM counter</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH1_CTR</name>
+            </field>
+          </fields>
+          <name>CH1_CTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>Counter compare values</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <name>B</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>A</name>
+            </field>
+          </fields>
+          <name>CH1_CC</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0024</addressOffset>
+          <description>Counter wrap value</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH1_TOP</name>
+            </field>
+          </fields>
+          <name>CH1_TOP</name>
+          <resetValue>0x0000ffff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0028</addressOffset>
+          <description>Control and status register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Advance the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running\n
+                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_ADV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Retard the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_RET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Free-running counting at rate dictated by fractional divider</description>
+                  <name>div</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Fractional divider operation is gated by the PWM B pin.</description>
+                  <name>level</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each rising edge of the PWM B pin.</description>
+                  <name>rise</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each falling edge of the PWM B pin.</description>
+                  <name>fall</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DIVMODE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Invert output B</description>
+              <name>B_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Invert output A</description>
+              <name>A_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+              <name>PH_CORRECT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enable the PWM channel.</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH2_CSR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x002c</addressOffset>
+          <description>INT and FRAC form a fixed-point fractional number.\n
+            Counting rate is system clock frequency divided by this number.\n
+            Fractional division uses simple 1st-order sigma-delta.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:4]</bitRange>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>CH2_DIV</name>
+          <resetValue>0x00000010</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0030</addressOffset>
+          <description>Direct access to the PWM counter</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH2_CTR</name>
+            </field>
+          </fields>
+          <name>CH2_CTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0034</addressOffset>
+          <description>Counter compare values</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <name>B</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>A</name>
+            </field>
+          </fields>
+          <name>CH2_CC</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0038</addressOffset>
+          <description>Counter wrap value</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH2_TOP</name>
+            </field>
+          </fields>
+          <name>CH2_TOP</name>
+          <resetValue>0x0000ffff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x003c</addressOffset>
+          <description>Control and status register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Advance the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running\n
+                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_ADV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Retard the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_RET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Free-running counting at rate dictated by fractional divider</description>
+                  <name>div</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Fractional divider operation is gated by the PWM B pin.</description>
+                  <name>level</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each rising edge of the PWM B pin.</description>
+                  <name>rise</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each falling edge of the PWM B pin.</description>
+                  <name>fall</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DIVMODE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Invert output B</description>
+              <name>B_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Invert output A</description>
+              <name>A_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+              <name>PH_CORRECT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enable the PWM channel.</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH3_CSR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0040</addressOffset>
+          <description>INT and FRAC form a fixed-point fractional number.\n
+            Counting rate is system clock frequency divided by this number.\n
+            Fractional division uses simple 1st-order sigma-delta.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:4]</bitRange>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>CH3_DIV</name>
+          <resetValue>0x00000010</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0044</addressOffset>
+          <description>Direct access to the PWM counter</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH3_CTR</name>
+            </field>
+          </fields>
+          <name>CH3_CTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0048</addressOffset>
+          <description>Counter compare values</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <name>B</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>A</name>
+            </field>
+          </fields>
+          <name>CH3_CC</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x004c</addressOffset>
+          <description>Counter wrap value</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH3_TOP</name>
+            </field>
+          </fields>
+          <name>CH3_TOP</name>
+          <resetValue>0x0000ffff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0050</addressOffset>
+          <description>Control and status register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Advance the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running\n
+                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_ADV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Retard the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_RET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Free-running counting at rate dictated by fractional divider</description>
+                  <name>div</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Fractional divider operation is gated by the PWM B pin.</description>
+                  <name>level</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each rising edge of the PWM B pin.</description>
+                  <name>rise</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each falling edge of the PWM B pin.</description>
+                  <name>fall</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DIVMODE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Invert output B</description>
+              <name>B_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Invert output A</description>
+              <name>A_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+              <name>PH_CORRECT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enable the PWM channel.</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH4_CSR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0054</addressOffset>
+          <description>INT and FRAC form a fixed-point fractional number.\n
+            Counting rate is system clock frequency divided by this number.\n
+            Fractional division uses simple 1st-order sigma-delta.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:4]</bitRange>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>CH4_DIV</name>
+          <resetValue>0x00000010</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0058</addressOffset>
+          <description>Direct access to the PWM counter</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH4_CTR</name>
+            </field>
+          </fields>
+          <name>CH4_CTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x005c</addressOffset>
+          <description>Counter compare values</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <name>B</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>A</name>
+            </field>
+          </fields>
+          <name>CH4_CC</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0060</addressOffset>
+          <description>Counter wrap value</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH4_TOP</name>
+            </field>
+          </fields>
+          <name>CH4_TOP</name>
+          <resetValue>0x0000ffff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0064</addressOffset>
+          <description>Control and status register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Advance the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running\n
+                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_ADV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Retard the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_RET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Free-running counting at rate dictated by fractional divider</description>
+                  <name>div</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Fractional divider operation is gated by the PWM B pin.</description>
+                  <name>level</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each rising edge of the PWM B pin.</description>
+                  <name>rise</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each falling edge of the PWM B pin.</description>
+                  <name>fall</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DIVMODE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Invert output B</description>
+              <name>B_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Invert output A</description>
+              <name>A_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+              <name>PH_CORRECT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enable the PWM channel.</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH5_CSR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0068</addressOffset>
+          <description>INT and FRAC form a fixed-point fractional number.\n
+            Counting rate is system clock frequency divided by this number.\n
+            Fractional division uses simple 1st-order sigma-delta.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:4]</bitRange>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>CH5_DIV</name>
+          <resetValue>0x00000010</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x006c</addressOffset>
+          <description>Direct access to the PWM counter</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH5_CTR</name>
+            </field>
+          </fields>
+          <name>CH5_CTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0070</addressOffset>
+          <description>Counter compare values</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <name>B</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>A</name>
+            </field>
+          </fields>
+          <name>CH5_CC</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0074</addressOffset>
+          <description>Counter wrap value</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH5_TOP</name>
+            </field>
+          </fields>
+          <name>CH5_TOP</name>
+          <resetValue>0x0000ffff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0078</addressOffset>
+          <description>Control and status register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Advance the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running\n
+                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_ADV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Retard the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_RET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Free-running counting at rate dictated by fractional divider</description>
+                  <name>div</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Fractional divider operation is gated by the PWM B pin.</description>
+                  <name>level</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each rising edge of the PWM B pin.</description>
+                  <name>rise</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each falling edge of the PWM B pin.</description>
+                  <name>fall</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DIVMODE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Invert output B</description>
+              <name>B_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Invert output A</description>
+              <name>A_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+              <name>PH_CORRECT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enable the PWM channel.</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH6_CSR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x007c</addressOffset>
+          <description>INT and FRAC form a fixed-point fractional number.\n
+            Counting rate is system clock frequency divided by this number.\n
+            Fractional division uses simple 1st-order sigma-delta.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:4]</bitRange>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>CH6_DIV</name>
+          <resetValue>0x00000010</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0080</addressOffset>
+          <description>Direct access to the PWM counter</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH6_CTR</name>
+            </field>
+          </fields>
+          <name>CH6_CTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0084</addressOffset>
+          <description>Counter compare values</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <name>B</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>A</name>
+            </field>
+          </fields>
+          <name>CH6_CC</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0088</addressOffset>
+          <description>Counter wrap value</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH6_TOP</name>
+            </field>
+          </fields>
+          <name>CH6_TOP</name>
+          <resetValue>0x0000ffff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x008c</addressOffset>
+          <description>Control and status register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Advance the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running\n
+                at less than full speed (div_int + div_frac / 16 &gt; 1)</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_ADV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Retard the phase of the counter by 1 count, while it is running.\n
+                Self-clearing. Write a 1, and poll until low. Counter must be running.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>PH_RET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:4]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Free-running counting at rate dictated by fractional divider</description>
+                  <name>div</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Fractional divider operation is gated by the PWM B pin.</description>
+                  <name>level</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each rising edge of the PWM B pin.</description>
+                  <name>rise</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Counter advances with each falling edge of the PWM B pin.</description>
+                  <name>fall</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DIVMODE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Invert output B</description>
+              <name>B_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Invert output A</description>
+              <name>A_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>1: Enable phase-correct modulation. 0: Trailing-edge</description>
+              <name>PH_CORRECT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enable the PWM channel.</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH7_CSR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0090</addressOffset>
+          <description>INT and FRAC form a fixed-point fractional number.\n
+            Counting rate is system clock frequency divided by this number.\n
+            Fractional division uses simple 1st-order sigma-delta.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:4]</bitRange>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>CH7_DIV</name>
+          <resetValue>0x00000010</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0094</addressOffset>
+          <description>Direct access to the PWM counter</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH7_CTR</name>
+            </field>
+          </fields>
+          <name>CH7_CTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0098</addressOffset>
+          <description>Counter compare values</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <name>B</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>A</name>
+            </field>
+          </fields>
+          <name>CH7_CC</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x009c</addressOffset>
+          <description>Counter wrap value</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CH7_TOP</name>
+            </field>
+          </fields>
+          <name>CH7_TOP</name>
+          <resetValue>0x0000ffff</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a0</addressOffset>
+          <description>This register aliases the CSR_EN bits for all channels.\n
+            Writing to this register allows multiple channels to be enabled\n
+            or disabled simultaneously, so they can run in perfect sync.\n
+            For each channel, there is only one physical EN register bit,\n
+            which can be accessed through here or CHx_CSR.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>CH7</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>CH6</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>CH5</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>CH4</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>CH3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>CH2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>CH1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>CH0</name>
+            </field>
+          </fields>
+          <name>EN</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a4</addressOffset>
+          <description>Raw Interrupts</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH7</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH6</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH5</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH4</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH0</name>
+            </field>
+          </fields>
+          <name>INTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a8</addressOffset>
+          <description>Interrupt Enable</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>CH7</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>CH6</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>CH5</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>CH4</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>CH3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>CH2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>CH1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>CH0</name>
+            </field>
+          </fields>
+          <name>INTE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00ac</addressOffset>
+          <description>Interrupt Force</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>CH7</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>CH6</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>CH5</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>CH4</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>CH3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>CH2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>CH1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>CH0</name>
+            </field>
+          </fields>
+          <name>INTF</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b0</addressOffset>
+          <description>Interrupt status after masking &amp; forcing</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>CH7</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>CH6</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>CH5</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>CH4</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>CH3</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>CH2</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>CH1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>CH0</name>
+            </field>
+          </fields>
+          <name>INTS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40054000</baseAddress>
+      <description>Controls time and alarms\n
+        time is a 64 bit value indicating the time in usec since power-on\n
+        timeh is the top 32 bits of time &amp; timel is the bottom 32 bits\n
+        to change time write to timelw before timehw\n
+        to read time read from timelr before timehr\n
+        An alarm is set by setting alarm_enable and writing to the corresponding alarm register\n
+        When an alarm is pending, the corresponding alarm_running signal will be high\n
+        An alarm can be cancelled before it has finished by clearing the alarm_enable\n
+        When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared\n
+        To clear the interrupt write a 1 to the corresponding alarm_irq</description>
+      <interrupt>
+        <name>TIMER_IRQ_0</name>
+        <value>0</value>
+      </interrupt>
+      <interrupt>
+        <name>TIMER_IRQ_1</name>
+        <value>1</value>
+      </interrupt>
+      <interrupt>
+        <name>TIMER_IRQ_2</name>
+        <value>2</value>
+      </interrupt>
+      <interrupt>
+        <name>TIMER_IRQ_3</name>
+        <value>3</value>
+      </interrupt>
+      <name>TIMER</name>
+      <registers>
+        <register>
+          <access>write-only</access>
+          <addressOffset>0x0000</addressOffset>
+          <description>Write to bits 63:32 of time\n
+            always write timelw before timehw</description>
+          <name>TIMEHW</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>write-only</access>
+          <addressOffset>0x0004</addressOffset>
+          <description>Write to bits 31:0 of time\n
+            writes do not get copied to time until timehw is written</description>
+          <name>TIMELW</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0008</addressOffset>
+          <description>Read from bits 63:32 of time\n
+            always read timelr before timehr</description>
+          <name>TIMEHR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x000c</addressOffset>
+          <description>Read from bits 31:0 of time</description>
+          <name>TIMELR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0010</addressOffset>
+          <description>Arm alarm 0, and configure the time it will fire.\n
+            Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.\n
+            The alarm will disarm itself once it fires, and can\n
+            be disarmed early using the ARMED status register.</description>
+          <name>ALARM0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0014</addressOffset>
+          <description>Arm alarm 1, and configure the time it will fire.\n
+            Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.\n
+            The alarm will disarm itself once it fires, and can\n
+            be disarmed early using the ARMED status register.</description>
+          <name>ALARM1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0018</addressOffset>
+          <description>Arm alarm 2, and configure the time it will fire.\n
+            Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.\n
+            The alarm will disarm itself once it fires, and can\n
+            be disarmed early using the ARMED status register.</description>
+          <name>ALARM2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x001c</addressOffset>
+          <description>Arm alarm 3, and configure the time it will fire.\n
+            Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.\n
+            The alarm will disarm itself once it fires, and can\n
+            be disarmed early using the ARMED status register.</description>
+          <name>ALARM3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>Indicates the armed/disarmed status of each alarm.\n
+            A write to the corresponding ALARMx register arms the alarm.\n
+            Alarms automatically disarm upon firing, but writing ones here\n
+            will disarm immediately without waiting to fire.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>ARMED</name>
+            </field>
+          </fields>
+          <name>ARMED</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0024</addressOffset>
+          <description>Raw read from bits 63:32 of time (no side effects)</description>
+          <name>TIMERAWH</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0028</addressOffset>
+          <description>Raw read from bits 31:0 of time (no side effects)</description>
+          <name>TIMERAWL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x002c</addressOffset>
+          <description>Set bits high to enable pause when the corresponding debug ports are active</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Pause when processor 1 is in debug mode</description>
+              <name>DBG1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Pause when processor 0 is in debug mode</description>
+              <name>DBG0</name>
+            </field>
+          </fields>
+          <name>DBGPAUSE</name>
+          <resetValue>0x00000007</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0030</addressOffset>
+          <description>Set high to pause the timer</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>PAUSE</name>
+            </field>
+          </fields>
+          <name>PAUSE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0034</addressOffset>
+          <description>Raw Interrupts</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>ALARM_3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>ALARM_2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>ALARM_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>ALARM_0</name>
+            </field>
+          </fields>
+          <name>INTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0038</addressOffset>
+          <description>Interrupt Enable</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>ALARM_3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>ALARM_2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>ALARM_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>ALARM_0</name>
+            </field>
+          </fields>
+          <name>INTE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x003c</addressOffset>
+          <description>Interrupt Force</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>ALARM_3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>ALARM_2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>ALARM_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>ALARM_0</name>
+            </field>
+          </fields>
+          <name>INTF</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0040</addressOffset>
+          <description>Interrupt status after masking &amp; forcing</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>ALARM_3</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>ALARM_2</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>ALARM_1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>ALARM_0</name>
+            </field>
+          </fields>
+          <name>INTS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40058000</baseAddress>
+      <name>WATCHDOG</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Watchdog control\n
+            The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.\n
+            The watchdog can be triggered in software.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Trigger a watchdog reset</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>TRIGGER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>When not enabled the watchdog timer is paused</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Pause the watchdog timer when processor 1 is in debug mode</description>
+              <name>PAUSE_DBG1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Pause the watchdog timer when processor 0 is in debug mode</description>
+              <name>PAUSE_DBG0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <description>Pause the watchdog timer when JTAG is accessing the bus fabric</description>
+              <name>PAUSE_JTAG</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:0]</bitRange>
+              <description>Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered</description>
+              <name>TIME</name>
+            </field>
+          </fields>
+          <name>CTRL</name>
+          <resetValue>0x07000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1).</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[23:0]</bitRange>
+              <name>LOAD</name>
+            </field>
+          </fields>
+          <name>LOAD</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>Logs the reason for the last reset. Both bits are zero for the case of a hardware reset.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>FORCE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>TIMER</name>
+            </field>
+          </fields>
+          <name>REASON</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x000c</addressOffset>
+          <description>Scratch register. Information persists through soft reset of the chip.</description>
+          <name>SCRATCH0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0010</addressOffset>
+          <description>Scratch register. Information persists through soft reset of the chip.</description>
+          <name>SCRATCH1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0014</addressOffset>
+          <description>Scratch register. Information persists through soft reset of the chip.</description>
+          <name>SCRATCH2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0018</addressOffset>
+          <description>Scratch register. Information persists through soft reset of the chip.</description>
+          <name>SCRATCH3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x001c</addressOffset>
+          <description>Scratch register. Information persists through soft reset of the chip.</description>
+          <name>SCRATCH4</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0020</addressOffset>
+          <description>Scratch register. Information persists through soft reset of the chip.</description>
+          <name>SCRATCH5</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0024</addressOffset>
+          <description>Scratch register. Information persists through soft reset of the chip.</description>
+          <name>SCRATCH6</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0028</addressOffset>
+          <description>Scratch register. Information persists through soft reset of the chip.</description>
+          <name>SCRATCH7</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x002c</addressOffset>
+          <description>Controls the tick generator</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:11]</bitRange>
+              <description>Count down timer: the remaining number clk_tick cycles before the next tick is generated.</description>
+              <name>COUNT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Is the tick generator running?</description>
+              <name>RUNNING</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <description>start / stop tick generation</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:0]</bitRange>
+              <description>Total number of clk_tick cycles before the next tick.</description>
+              <name>CYCLES</name>
+            </field>
+          </fields>
+          <name>TICK</name>
+          <resetValue>0x00000200</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x4005c000</baseAddress>
+      <description>Register block to control RTC</description>
+      <interrupt>
+        <name>RTC_IRQ</name>
+        <value>25</value>
+      </interrupt>
+      <name>RTC</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>CLKDIV_M1</name>
+            </field>
+          </fields>
+          <name>CLKDIV_M1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>RTC setup register 0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:12]</bitRange>
+              <description>Year</description>
+              <name>YEAR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:8]</bitRange>
+              <description>Month (1..12)</description>
+              <name>MONTH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>Day of the month (1..31)</description>
+              <name>DAY</name>
+            </field>
+          </fields>
+          <name>SETUP_0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>RTC setup register 1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:24]</bitRange>
+              <description>Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7</description>
+              <name>DOTW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:16]</bitRange>
+              <description>Hours</description>
+              <name>HOUR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:8]</bitRange>
+              <description>Minutes</description>
+              <name>MIN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <description>Seconds</description>
+              <name>SEC</name>
+            </field>
+          </fields>
+          <name>SETUP_1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>RTC Control and status</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <description>If set, leapyear is forced off.\n
+                Useful for years divisible by 100 but not by 400</description>
+              <name>FORCE_NOTLEAPYEAR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Load RTC</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>LOAD</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>RTC enabled (running)</description>
+              <name>RTC_ACTIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enable RTC</description>
+              <name>RTC_ENABLE</name>
+            </field>
+          </fields>
+          <name>CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>Interrupt setup register 0</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>MATCH_ACTIVE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Global match enable. Don't change any other value while this one is enabled</description>
+              <name>MATCH_ENA</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Enable year matching</description>
+              <name>YEAR_ENA</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Enable month matching</description>
+              <name>MONTH_ENA</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <description>Enable day matching</description>
+              <name>DAY_ENA</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:12]</bitRange>
+              <description>Year</description>
+              <name>YEAR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:8]</bitRange>
+              <description>Month (1..12)</description>
+              <name>MONTH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>Day of the month (1..31)</description>
+              <name>DAY</name>
+            </field>
+          </fields>
+          <name>IRQ_SETUP_0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>Interrupt setup register 1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable day of the week matching</description>
+              <name>DOTW_ENA</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Enable hour matching</description>
+              <name>HOUR_ENA</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Enable minute matching</description>
+              <name>MIN_ENA</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Enable second matching</description>
+              <name>SEC_ENA</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:24]</bitRange>
+              <description>Day of the week</description>
+              <name>DOTW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:16]</bitRange>
+              <description>Hours</description>
+              <name>HOUR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:8]</bitRange>
+              <description>Minutes</description>
+              <name>MIN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <description>Seconds</description>
+              <name>SEC</name>
+            </field>
+          </fields>
+          <name>IRQ_SETUP_1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>RTC register 1.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:12]</bitRange>
+              <description>Year</description>
+              <name>YEAR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:8]</bitRange>
+              <description>Month (1..12)</description>
+              <name>MONTH</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:0]</bitRange>
+              <description>Day of the month (1..31)</description>
+              <name>DAY</name>
+            </field>
+          </fields>
+          <name>RTC_1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>RTC register 0\n
+            Read this before RTC 1!</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:24]</bitRange>
+              <description>Day of the week</description>
+              <name>DOTW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:16]</bitRange>
+              <description>Hours</description>
+              <name>HOUR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:8]</bitRange>
+              <description>Minutes</description>
+              <name>MIN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:0]</bitRange>
+              <description>Seconds</description>
+              <name>SEC</name>
+            </field>
+          </fields>
+          <name>RTC_0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>Raw Interrupts</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>RTC</name>
+            </field>
+          </fields>
+          <name>INTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0024</addressOffset>
+          <description>Interrupt Enable</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>RTC</name>
+            </field>
+          </fields>
+          <name>INTE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0028</addressOffset>
+          <description>Interrupt Force</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>RTC</name>
+            </field>
+          </fields>
+          <name>INTF</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x002c</addressOffset>
+          <description>Interrupt status after masking &amp; forcing</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>RTC</name>
+            </field>
+          </fields>
+          <name>INTS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40060000</baseAddress>
+      <name>ROSC</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Ring Oscillator control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:12]</bitRange>
+              <description>On power-up this field is initialised to ENABLE\n
+                The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up\n
+                The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>DISABLE</name>
+                  <value>3358</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>ENABLE</name>
+                  <value>4011</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:0]</bitRange>
+              <description>Controls the number of delay stages in the ROSC ring\n
+                LOW uses stages 0 to 7\n
+                MEDIUM uses stages 0 to 5\n
+                HIGH uses stages 0 to 3\n
+                TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications\n
+                The clock output will not glitch when changing the range up one step at a time\n
+                The clock output will glitch when changing the range down\n
+                Note: the values here are gray coded which is why HIGH comes before TOOHIGH</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>LOW</name>
+                  <value>4004</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MEDIUM</name>
+                  <value>4005</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>HIGH</name>
+                  <value>4007</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>TOOHIGH</name>
+                  <value>4006</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>FREQ_RANGE</name>
+            </field>
+          </fields>
+          <name>CTRL</name>
+          <resetValue>0x00000aa0</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>The FREQA &amp; FREQB registers control the frequency by controlling the drive strength of each stage\n
+            The drive strength has 4 levels determined by the number of bits set\n
+            Increasing the number of bits set increases the drive strength and increases the oscillation frequency\n
+            0 bits set is the default drive strength\n
+            1 bit set doubles the drive strength\n
+            2 bits set triples drive strength\n
+            3 bits set quadruples drive strength</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <description>Set to 0x9696 to apply the settings\n
+                Any other value in this field will set all drive strengths to 0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PASS</name>
+                  <value>38550</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>PASSWD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:12]</bitRange>
+              <description>Stage 3 drive strength</description>
+              <name>DS3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:8]</bitRange>
+              <description>Stage 2 drive strength</description>
+              <name>DS2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:4]</bitRange>
+              <description>Stage 1 drive strength</description>
+              <name>DS1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:0]</bitRange>
+              <description>Stage 0 drive strength</description>
+              <name>DS0</name>
+            </field>
+          </fields>
+          <name>FREQA</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>For a detailed description see freqa register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <description>Set to 0x9696 to apply the settings\n
+                Any other value in this field will set all drive strengths to 0</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PASS</name>
+                  <value>38550</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>PASSWD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:12]</bitRange>
+              <description>Stage 7 drive strength</description>
+              <name>DS7</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:8]</bitRange>
+              <description>Stage 6 drive strength</description>
+              <name>DS6</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:4]</bitRange>
+              <description>Stage 5 drive strength</description>
+              <name>DS5</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:0]</bitRange>
+              <description>Stage 4 drive strength</description>
+              <name>DS4</name>
+            </field>
+          </fields>
+          <name>FREQB</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x000c</addressOffset>
+          <description>Ring Oscillator pause control\n
+            This is used to save power by pausing the ROSC\n
+            On power-up this field is initialised to WAKE\n
+            An invalid write will also select WAKE\n
+            Warning: setup the irq before selecting dormant mode</description>
+          <name>DORMANT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>Controls the output divider</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:0]</bitRange>
+              <description>set to 0xaa0 + div where\n
+                div = 0 divides by 32\n
+                div = 1-31 divides by div\n
+                any other value sets div=31\n
+                this register resets to div=16</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>PASS</name>
+                  <value>2720</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DIV</name>
+            </field>
+          </fields>
+          <name>DIV</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>Controls the phase shifted output</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:4]</bitRange>
+              <description>set to 0xaa\n
+                any other value enables the output with shift=0</description>
+              <name>PASSWD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>enable the phase-shifted output\n
+                this can be changed on-the-fly</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>invert the phase-shifted output\n
+                this is ignored when div=1</description>
+              <name>FLIP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:0]</bitRange>
+              <description>phase shift the phase-shifted output by SHIFT input clocks\n
+                this can be changed on-the-fly\n
+                must be set to 0 before setting div=1</description>
+              <name>SHIFT</name>
+            </field>
+          </fields>
+          <name>PHASE</name>
+          <resetValue>0x00000008</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>Ring Oscillator Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Oscillator is running and stable</description>
+              <name>STABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <description>An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>BADWRITE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <description>post-divider is running\n
+                this resets to 0 but transitions to 1 during chip startup</description>
+              <name>DIV_RUNNING</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Oscillator is enabled but not necessarily running and stable\n
+                this resets to 0 but transitions to 1 during chip startup</description>
+              <name>ENABLED</name>
+            </field>
+          </fields>
+          <name>STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>RANDOMBIT</name>
+            </field>
+          </fields>
+          <name>RANDOMBIT</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>A down counter running at the ROSC frequency which counts to zero and stops.\n
+            To start the counter write a non-zero value.\n
+            Can be used for short software pauses when setting up time sensitive hardware.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <name>COUNT</name>
+            </field>
+          </fields>
+          <name>COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x40064000</baseAddress>
+      <description>control and status for on-chip voltage regulator and chip level reset subsystem</description>
+      <name>VREG_AND_CHIP_RESET</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Voltage regulator control and status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>regulation status\n
+                0=not in regulation, 1=in regulation</description>
+              <name>ROK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:4]</bitRange>
+              <description>output voltage select\n
+                0000 to 0101 - 0.80V\n
+                0110         - 0.85V\n
+                0111         - 0.90V\n
+                1000         - 0.95V\n
+                1001         - 1.00V\n
+                1010         - 1.05V\n
+                1011         - 1.10V (default)\n
+                1100         - 1.15V\n
+                1101         - 1.20V\n
+                1110         - 1.25V\n
+                1111         - 1.30V</description>
+              <name>VSEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>high impedance mode select\n
+                0=not in high impedance mode, 1=in high impedance mode</description>
+              <name>HIZ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>enable\n
+                0=not enabled, 1=enabled</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>VREG</name>
+          <resetValue>0x000000b1</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>brown-out detection control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:4]</bitRange>
+              <description>threshold select\n
+                0000 - 0.473V\n
+                0001 - 0.516V\n
+                0010 - 0.559V\n
+                0011 - 0.602V\n
+                0100 - 0.645V\n
+                0101 - 0.688V\n
+                0110 - 0.731V\n
+                0111 - 0.774V\n
+                1000 - 0.817V\n
+                1001 - 0.860V (default)\n
+                1010 - 0.903V\n
+                1011 - 0.946V\n
+                1100 - 0.989V\n
+                1101 - 1.032V\n
+                1110 - 1.075V\n
+                1111 - 1.118V</description>
+              <name>VSEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>enable\n
+                0=not enabled, 1=enabled</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>BOD</name>
+          <resetValue>0x00000091</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>Chip reset control and status</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <description>This is set by psm_restart from the debugger.\n
+                Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.\n
+                In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>PSM_RESTART_FLAG</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <description>Last reset was from the debug port</description>
+              <name>HAD_PSM_RESTART</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Last reset was from the RUN pin</description>
+              <name>HAD_RUN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Last reset was from the power-on reset or brown-out detection blocks</description>
+              <name>HAD_POR</name>
+            </field>
+          </fields>
+          <name>CHIP_RESET</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x4006c000</baseAddress>
+      <description>Testbench manager. Allows the programmer to know what platform their software is running on.</description>
+      <name>TBMAN</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Indicates the type of platform in use</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Indicates the platform is an FPGA</description>
+              <name>FPGA</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Indicates the platform is an ASIC</description>
+              <name>ASIC</name>
+            </field>
+          </fields>
+          <name>PLATFORM</name>
+          <resetValue>0x00000005</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x50000000</baseAddress>
+      <description>DMA with separate read and write masters</description>
+      <interrupt>
+        <name>DMA_IRQ_0</name>
+        <value>11</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_IRQ_1</name>
+        <value>12</value>
+      </interrupt>
+      <name>DMA</name>
+      <registers>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0000</addressOffset>
+          <description>DMA Channel 0 Read Address pointer\n
+            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+          <name>CH0_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0004</addressOffset>
+          <description>DMA Channel 0 Write Address pointer\n
+            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+          <name>CH0_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0008</addressOffset>
+          <description>DMA Channel 0 Transfer Count\n
+            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
+            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
+            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
+            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+          <name>CH0_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>DMA Channel 0 Control and Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+              <name>AHB_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the channel received a read bus error. Write one to clear.\n
+                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>READ_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, the channel received a write bus error. Write one to clear.\n
+                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>WRITE_ERROR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
+                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+              <name>BUSY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
+                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+              <name>SNIFF_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <description>Apply byte-swap transformation to DMA data.\n
+                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+              <name>BSWAP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
+                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+              <name>IRQ_QUIET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:15]</bitRange>
+              <description>Select a Transfer Request signal.\n
+                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
+                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Select Timer 0 as TREQ</description>
+                  <name>TIMER0</name>
+                  <value>59</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 1 as TREQ</description>
+                  <name>TIMER1</name>
+                  <value>60</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 2 as TREQ (Optional)</description>
+                  <name>TIMER2</name>
+                  <value>61</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 3 as TREQ (Optional)</description>
+                  <name>TIMER3</name>
+                  <value>62</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Permanent request, for unpaced transfers.</description>
+                  <name>PERMANENT</name>
+                  <value>63</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TREQ_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:11]</bitRange>
+              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
+                Reset value is equal to channel number (0).</description>
+              <name>CHAIN_TO</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Select whether RING_SIZE applies to read or write addresses.\n
+                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+              <name>RING_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:6]</bitRange>
+              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RING_NONE</name>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RING_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
+                Generally this should be disabled for memory-to-peripheral transfers.</description>
+              <name>INCR_WRITE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
+                Generally this should be disabled for peripheral-to-memory transfers.</description>
+              <name>INCR_READ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:2]</bitRange>
+              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SIZE_BYTE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_HALFWORD</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_WORD</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DATA_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
+                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+              <name>HIGH_PRIORITY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>DMA Channel Enable.\n
+                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH0_CTRL_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0010</addressOffset>
+          <description>Alias for channel 0 CTRL register</description>
+          <name>CH0_AL1_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0014</addressOffset>
+          <description>Alias for channel 0 READ_ADDR register</description>
+          <name>CH0_AL1_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0018</addressOffset>
+          <description>Alias for channel 0 WRITE_ADDR register</description>
+          <name>CH0_AL1_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x001c</addressOffset>
+          <description>Alias for channel 0 TRANS_COUNT register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH0_AL1_TRANS_COUNT_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0020</addressOffset>
+          <description>Alias for channel 0 CTRL register</description>
+          <name>CH0_AL2_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0024</addressOffset>
+          <description>Alias for channel 0 TRANS_COUNT register</description>
+          <name>CH0_AL2_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0028</addressOffset>
+          <description>Alias for channel 0 READ_ADDR register</description>
+          <name>CH0_AL2_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x002c</addressOffset>
+          <description>Alias for channel 0 WRITE_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH0_AL2_WRITE_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0030</addressOffset>
+          <description>Alias for channel 0 CTRL register</description>
+          <name>CH0_AL3_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0034</addressOffset>
+          <description>Alias for channel 0 WRITE_ADDR register</description>
+          <name>CH0_AL3_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0038</addressOffset>
+          <description>Alias for channel 0 TRANS_COUNT register</description>
+          <name>CH0_AL3_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x003c</addressOffset>
+          <description>Alias for channel 0 READ_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH0_AL3_READ_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0040</addressOffset>
+          <description>DMA Channel 1 Read Address pointer\n
+            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+          <name>CH1_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0044</addressOffset>
+          <description>DMA Channel 1 Write Address pointer\n
+            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+          <name>CH1_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0048</addressOffset>
+          <description>DMA Channel 1 Transfer Count\n
+            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
+            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
+            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
+            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+          <name>CH1_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x004c</addressOffset>
+          <description>DMA Channel 1 Control and Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+              <name>AHB_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the channel received a read bus error. Write one to clear.\n
+                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>READ_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, the channel received a write bus error. Write one to clear.\n
+                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>WRITE_ERROR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
+                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+              <name>BUSY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
+                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+              <name>SNIFF_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <description>Apply byte-swap transformation to DMA data.\n
+                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+              <name>BSWAP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
+                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+              <name>IRQ_QUIET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:15]</bitRange>
+              <description>Select a Transfer Request signal.\n
+                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
+                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Select Timer 0 as TREQ</description>
+                  <name>TIMER0</name>
+                  <value>59</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 1 as TREQ</description>
+                  <name>TIMER1</name>
+                  <value>60</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 2 as TREQ (Optional)</description>
+                  <name>TIMER2</name>
+                  <value>61</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 3 as TREQ (Optional)</description>
+                  <name>TIMER3</name>
+                  <value>62</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Permanent request, for unpaced transfers.</description>
+                  <name>PERMANENT</name>
+                  <value>63</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TREQ_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:11]</bitRange>
+              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
+                Reset value is equal to channel number (1).</description>
+              <name>CHAIN_TO</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Select whether RING_SIZE applies to read or write addresses.\n
+                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+              <name>RING_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:6]</bitRange>
+              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RING_NONE</name>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RING_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
+                Generally this should be disabled for memory-to-peripheral transfers.</description>
+              <name>INCR_WRITE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
+                Generally this should be disabled for peripheral-to-memory transfers.</description>
+              <name>INCR_READ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:2]</bitRange>
+              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SIZE_BYTE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_HALFWORD</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_WORD</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DATA_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
+                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+              <name>HIGH_PRIORITY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>DMA Channel Enable.\n
+                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH1_CTRL_TRIG</name>
+          <resetValue>0x00000800</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0050</addressOffset>
+          <description>Alias for channel 1 CTRL register</description>
+          <name>CH1_AL1_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0054</addressOffset>
+          <description>Alias for channel 1 READ_ADDR register</description>
+          <name>CH1_AL1_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0058</addressOffset>
+          <description>Alias for channel 1 WRITE_ADDR register</description>
+          <name>CH1_AL1_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x005c</addressOffset>
+          <description>Alias for channel 1 TRANS_COUNT register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH1_AL1_TRANS_COUNT_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0060</addressOffset>
+          <description>Alias for channel 1 CTRL register</description>
+          <name>CH1_AL2_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0064</addressOffset>
+          <description>Alias for channel 1 TRANS_COUNT register</description>
+          <name>CH1_AL2_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0068</addressOffset>
+          <description>Alias for channel 1 READ_ADDR register</description>
+          <name>CH1_AL2_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x006c</addressOffset>
+          <description>Alias for channel 1 WRITE_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH1_AL2_WRITE_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0070</addressOffset>
+          <description>Alias for channel 1 CTRL register</description>
+          <name>CH1_AL3_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0074</addressOffset>
+          <description>Alias for channel 1 WRITE_ADDR register</description>
+          <name>CH1_AL3_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0078</addressOffset>
+          <description>Alias for channel 1 TRANS_COUNT register</description>
+          <name>CH1_AL3_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x007c</addressOffset>
+          <description>Alias for channel 1 READ_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH1_AL3_READ_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0080</addressOffset>
+          <description>DMA Channel 2 Read Address pointer\n
+            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+          <name>CH2_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0084</addressOffset>
+          <description>DMA Channel 2 Write Address pointer\n
+            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+          <name>CH2_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0088</addressOffset>
+          <description>DMA Channel 2 Transfer Count\n
+            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
+            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
+            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
+            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+          <name>CH2_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x008c</addressOffset>
+          <description>DMA Channel 2 Control and Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+              <name>AHB_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the channel received a read bus error. Write one to clear.\n
+                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>READ_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, the channel received a write bus error. Write one to clear.\n
+                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>WRITE_ERROR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
+                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+              <name>BUSY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
+                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+              <name>SNIFF_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <description>Apply byte-swap transformation to DMA data.\n
+                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+              <name>BSWAP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
+                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+              <name>IRQ_QUIET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:15]</bitRange>
+              <description>Select a Transfer Request signal.\n
+                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
+                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Select Timer 0 as TREQ</description>
+                  <name>TIMER0</name>
+                  <value>59</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 1 as TREQ</description>
+                  <name>TIMER1</name>
+                  <value>60</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 2 as TREQ (Optional)</description>
+                  <name>TIMER2</name>
+                  <value>61</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 3 as TREQ (Optional)</description>
+                  <name>TIMER3</name>
+                  <value>62</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Permanent request, for unpaced transfers.</description>
+                  <name>PERMANENT</name>
+                  <value>63</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TREQ_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:11]</bitRange>
+              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
+                Reset value is equal to channel number (2).</description>
+              <name>CHAIN_TO</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Select whether RING_SIZE applies to read or write addresses.\n
+                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+              <name>RING_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:6]</bitRange>
+              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RING_NONE</name>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RING_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
+                Generally this should be disabled for memory-to-peripheral transfers.</description>
+              <name>INCR_WRITE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
+                Generally this should be disabled for peripheral-to-memory transfers.</description>
+              <name>INCR_READ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:2]</bitRange>
+              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SIZE_BYTE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_HALFWORD</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_WORD</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DATA_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
+                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+              <name>HIGH_PRIORITY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>DMA Channel Enable.\n
+                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH2_CTRL_TRIG</name>
+          <resetValue>0x00001000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0090</addressOffset>
+          <description>Alias for channel 2 CTRL register</description>
+          <name>CH2_AL1_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0094</addressOffset>
+          <description>Alias for channel 2 READ_ADDR register</description>
+          <name>CH2_AL1_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0098</addressOffset>
+          <description>Alias for channel 2 WRITE_ADDR register</description>
+          <name>CH2_AL1_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x009c</addressOffset>
+          <description>Alias for channel 2 TRANS_COUNT register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH2_AL1_TRANS_COUNT_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00a0</addressOffset>
+          <description>Alias for channel 2 CTRL register</description>
+          <name>CH2_AL2_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00a4</addressOffset>
+          <description>Alias for channel 2 TRANS_COUNT register</description>
+          <name>CH2_AL2_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00a8</addressOffset>
+          <description>Alias for channel 2 READ_ADDR register</description>
+          <name>CH2_AL2_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00ac</addressOffset>
+          <description>Alias for channel 2 WRITE_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH2_AL2_WRITE_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00b0</addressOffset>
+          <description>Alias for channel 2 CTRL register</description>
+          <name>CH2_AL3_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00b4</addressOffset>
+          <description>Alias for channel 2 WRITE_ADDR register</description>
+          <name>CH2_AL3_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00b8</addressOffset>
+          <description>Alias for channel 2 TRANS_COUNT register</description>
+          <name>CH2_AL3_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00bc</addressOffset>
+          <description>Alias for channel 2 READ_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH2_AL3_READ_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00c0</addressOffset>
+          <description>DMA Channel 3 Read Address pointer\n
+            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+          <name>CH3_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00c4</addressOffset>
+          <description>DMA Channel 3 Write Address pointer\n
+            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+          <name>CH3_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00c8</addressOffset>
+          <description>DMA Channel 3 Transfer Count\n
+            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
+            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
+            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
+            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+          <name>CH3_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00cc</addressOffset>
+          <description>DMA Channel 3 Control and Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+              <name>AHB_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the channel received a read bus error. Write one to clear.\n
+                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>READ_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, the channel received a write bus error. Write one to clear.\n
+                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>WRITE_ERROR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
+                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+              <name>BUSY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
+                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+              <name>SNIFF_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <description>Apply byte-swap transformation to DMA data.\n
+                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+              <name>BSWAP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
+                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+              <name>IRQ_QUIET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:15]</bitRange>
+              <description>Select a Transfer Request signal.\n
+                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
+                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Select Timer 0 as TREQ</description>
+                  <name>TIMER0</name>
+                  <value>59</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 1 as TREQ</description>
+                  <name>TIMER1</name>
+                  <value>60</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 2 as TREQ (Optional)</description>
+                  <name>TIMER2</name>
+                  <value>61</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 3 as TREQ (Optional)</description>
+                  <name>TIMER3</name>
+                  <value>62</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Permanent request, for unpaced transfers.</description>
+                  <name>PERMANENT</name>
+                  <value>63</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TREQ_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:11]</bitRange>
+              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
+                Reset value is equal to channel number (3).</description>
+              <name>CHAIN_TO</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Select whether RING_SIZE applies to read or write addresses.\n
+                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+              <name>RING_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:6]</bitRange>
+              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RING_NONE</name>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RING_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
+                Generally this should be disabled for memory-to-peripheral transfers.</description>
+              <name>INCR_WRITE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
+                Generally this should be disabled for peripheral-to-memory transfers.</description>
+              <name>INCR_READ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:2]</bitRange>
+              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SIZE_BYTE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_HALFWORD</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_WORD</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DATA_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
+                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+              <name>HIGH_PRIORITY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>DMA Channel Enable.\n
+                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH3_CTRL_TRIG</name>
+          <resetValue>0x00001800</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00d0</addressOffset>
+          <description>Alias for channel 3 CTRL register</description>
+          <name>CH3_AL1_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00d4</addressOffset>
+          <description>Alias for channel 3 READ_ADDR register</description>
+          <name>CH3_AL1_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00d8</addressOffset>
+          <description>Alias for channel 3 WRITE_ADDR register</description>
+          <name>CH3_AL1_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00dc</addressOffset>
+          <description>Alias for channel 3 TRANS_COUNT register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH3_AL1_TRANS_COUNT_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00e0</addressOffset>
+          <description>Alias for channel 3 CTRL register</description>
+          <name>CH3_AL2_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00e4</addressOffset>
+          <description>Alias for channel 3 TRANS_COUNT register</description>
+          <name>CH3_AL2_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00e8</addressOffset>
+          <description>Alias for channel 3 READ_ADDR register</description>
+          <name>CH3_AL2_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00ec</addressOffset>
+          <description>Alias for channel 3 WRITE_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH3_AL2_WRITE_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00f0</addressOffset>
+          <description>Alias for channel 3 CTRL register</description>
+          <name>CH3_AL3_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00f4</addressOffset>
+          <description>Alias for channel 3 WRITE_ADDR register</description>
+          <name>CH3_AL3_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00f8</addressOffset>
+          <description>Alias for channel 3 TRANS_COUNT register</description>
+          <name>CH3_AL3_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00fc</addressOffset>
+          <description>Alias for channel 3 READ_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH3_AL3_READ_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0100</addressOffset>
+          <description>DMA Channel 4 Read Address pointer\n
+            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+          <name>CH4_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0104</addressOffset>
+          <description>DMA Channel 4 Write Address pointer\n
+            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+          <name>CH4_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0108</addressOffset>
+          <description>DMA Channel 4 Transfer Count\n
+            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
+            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
+            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
+            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+          <name>CH4_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x010c</addressOffset>
+          <description>DMA Channel 4 Control and Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+              <name>AHB_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the channel received a read bus error. Write one to clear.\n
+                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>READ_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, the channel received a write bus error. Write one to clear.\n
+                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>WRITE_ERROR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
+                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+              <name>BUSY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
+                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+              <name>SNIFF_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <description>Apply byte-swap transformation to DMA data.\n
+                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+              <name>BSWAP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
+                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+              <name>IRQ_QUIET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:15]</bitRange>
+              <description>Select a Transfer Request signal.\n
+                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
+                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Select Timer 0 as TREQ</description>
+                  <name>TIMER0</name>
+                  <value>59</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 1 as TREQ</description>
+                  <name>TIMER1</name>
+                  <value>60</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 2 as TREQ (Optional)</description>
+                  <name>TIMER2</name>
+                  <value>61</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 3 as TREQ (Optional)</description>
+                  <name>TIMER3</name>
+                  <value>62</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Permanent request, for unpaced transfers.</description>
+                  <name>PERMANENT</name>
+                  <value>63</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TREQ_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:11]</bitRange>
+              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
+                Reset value is equal to channel number (4).</description>
+              <name>CHAIN_TO</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Select whether RING_SIZE applies to read or write addresses.\n
+                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+              <name>RING_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:6]</bitRange>
+              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RING_NONE</name>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RING_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
+                Generally this should be disabled for memory-to-peripheral transfers.</description>
+              <name>INCR_WRITE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
+                Generally this should be disabled for peripheral-to-memory transfers.</description>
+              <name>INCR_READ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:2]</bitRange>
+              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SIZE_BYTE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_HALFWORD</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_WORD</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DATA_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
+                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+              <name>HIGH_PRIORITY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>DMA Channel Enable.\n
+                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH4_CTRL_TRIG</name>
+          <resetValue>0x00002000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0110</addressOffset>
+          <description>Alias for channel 4 CTRL register</description>
+          <name>CH4_AL1_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0114</addressOffset>
+          <description>Alias for channel 4 READ_ADDR register</description>
+          <name>CH4_AL1_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0118</addressOffset>
+          <description>Alias for channel 4 WRITE_ADDR register</description>
+          <name>CH4_AL1_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x011c</addressOffset>
+          <description>Alias for channel 4 TRANS_COUNT register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH4_AL1_TRANS_COUNT_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0120</addressOffset>
+          <description>Alias for channel 4 CTRL register</description>
+          <name>CH4_AL2_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0124</addressOffset>
+          <description>Alias for channel 4 TRANS_COUNT register</description>
+          <name>CH4_AL2_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0128</addressOffset>
+          <description>Alias for channel 4 READ_ADDR register</description>
+          <name>CH4_AL2_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x012c</addressOffset>
+          <description>Alias for channel 4 WRITE_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH4_AL2_WRITE_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0130</addressOffset>
+          <description>Alias for channel 4 CTRL register</description>
+          <name>CH4_AL3_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0134</addressOffset>
+          <description>Alias for channel 4 WRITE_ADDR register</description>
+          <name>CH4_AL3_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0138</addressOffset>
+          <description>Alias for channel 4 TRANS_COUNT register</description>
+          <name>CH4_AL3_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x013c</addressOffset>
+          <description>Alias for channel 4 READ_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH4_AL3_READ_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0140</addressOffset>
+          <description>DMA Channel 5 Read Address pointer\n
+            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+          <name>CH5_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0144</addressOffset>
+          <description>DMA Channel 5 Write Address pointer\n
+            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+          <name>CH5_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0148</addressOffset>
+          <description>DMA Channel 5 Transfer Count\n
+            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
+            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
+            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
+            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+          <name>CH5_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x014c</addressOffset>
+          <description>DMA Channel 5 Control and Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+              <name>AHB_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the channel received a read bus error. Write one to clear.\n
+                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>READ_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, the channel received a write bus error. Write one to clear.\n
+                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>WRITE_ERROR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
+                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+              <name>BUSY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
+                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+              <name>SNIFF_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <description>Apply byte-swap transformation to DMA data.\n
+                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+              <name>BSWAP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
+                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+              <name>IRQ_QUIET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:15]</bitRange>
+              <description>Select a Transfer Request signal.\n
+                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
+                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Select Timer 0 as TREQ</description>
+                  <name>TIMER0</name>
+                  <value>59</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 1 as TREQ</description>
+                  <name>TIMER1</name>
+                  <value>60</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 2 as TREQ (Optional)</description>
+                  <name>TIMER2</name>
+                  <value>61</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 3 as TREQ (Optional)</description>
+                  <name>TIMER3</name>
+                  <value>62</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Permanent request, for unpaced transfers.</description>
+                  <name>PERMANENT</name>
+                  <value>63</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TREQ_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:11]</bitRange>
+              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
+                Reset value is equal to channel number (5).</description>
+              <name>CHAIN_TO</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Select whether RING_SIZE applies to read or write addresses.\n
+                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+              <name>RING_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:6]</bitRange>
+              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RING_NONE</name>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RING_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
+                Generally this should be disabled for memory-to-peripheral transfers.</description>
+              <name>INCR_WRITE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
+                Generally this should be disabled for peripheral-to-memory transfers.</description>
+              <name>INCR_READ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:2]</bitRange>
+              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SIZE_BYTE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_HALFWORD</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_WORD</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DATA_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
+                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+              <name>HIGH_PRIORITY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>DMA Channel Enable.\n
+                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH5_CTRL_TRIG</name>
+          <resetValue>0x00002800</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0150</addressOffset>
+          <description>Alias for channel 5 CTRL register</description>
+          <name>CH5_AL1_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0154</addressOffset>
+          <description>Alias for channel 5 READ_ADDR register</description>
+          <name>CH5_AL1_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0158</addressOffset>
+          <description>Alias for channel 5 WRITE_ADDR register</description>
+          <name>CH5_AL1_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x015c</addressOffset>
+          <description>Alias for channel 5 TRANS_COUNT register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH5_AL1_TRANS_COUNT_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0160</addressOffset>
+          <description>Alias for channel 5 CTRL register</description>
+          <name>CH5_AL2_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0164</addressOffset>
+          <description>Alias for channel 5 TRANS_COUNT register</description>
+          <name>CH5_AL2_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0168</addressOffset>
+          <description>Alias for channel 5 READ_ADDR register</description>
+          <name>CH5_AL2_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x016c</addressOffset>
+          <description>Alias for channel 5 WRITE_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH5_AL2_WRITE_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0170</addressOffset>
+          <description>Alias for channel 5 CTRL register</description>
+          <name>CH5_AL3_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0174</addressOffset>
+          <description>Alias for channel 5 WRITE_ADDR register</description>
+          <name>CH5_AL3_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0178</addressOffset>
+          <description>Alias for channel 5 TRANS_COUNT register</description>
+          <name>CH5_AL3_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x017c</addressOffset>
+          <description>Alias for channel 5 READ_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH5_AL3_READ_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0180</addressOffset>
+          <description>DMA Channel 6 Read Address pointer\n
+            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+          <name>CH6_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0184</addressOffset>
+          <description>DMA Channel 6 Write Address pointer\n
+            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+          <name>CH6_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0188</addressOffset>
+          <description>DMA Channel 6 Transfer Count\n
+            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
+            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
+            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
+            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+          <name>CH6_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x018c</addressOffset>
+          <description>DMA Channel 6 Control and Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+              <name>AHB_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the channel received a read bus error. Write one to clear.\n
+                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>READ_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, the channel received a write bus error. Write one to clear.\n
+                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>WRITE_ERROR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
+                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+              <name>BUSY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
+                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+              <name>SNIFF_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <description>Apply byte-swap transformation to DMA data.\n
+                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+              <name>BSWAP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
+                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+              <name>IRQ_QUIET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:15]</bitRange>
+              <description>Select a Transfer Request signal.\n
+                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
+                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Select Timer 0 as TREQ</description>
+                  <name>TIMER0</name>
+                  <value>59</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 1 as TREQ</description>
+                  <name>TIMER1</name>
+                  <value>60</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 2 as TREQ (Optional)</description>
+                  <name>TIMER2</name>
+                  <value>61</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 3 as TREQ (Optional)</description>
+                  <name>TIMER3</name>
+                  <value>62</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Permanent request, for unpaced transfers.</description>
+                  <name>PERMANENT</name>
+                  <value>63</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TREQ_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:11]</bitRange>
+              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
+                Reset value is equal to channel number (6).</description>
+              <name>CHAIN_TO</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Select whether RING_SIZE applies to read or write addresses.\n
+                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+              <name>RING_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:6]</bitRange>
+              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RING_NONE</name>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RING_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
+                Generally this should be disabled for memory-to-peripheral transfers.</description>
+              <name>INCR_WRITE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
+                Generally this should be disabled for peripheral-to-memory transfers.</description>
+              <name>INCR_READ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:2]</bitRange>
+              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SIZE_BYTE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_HALFWORD</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_WORD</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DATA_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
+                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+              <name>HIGH_PRIORITY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>DMA Channel Enable.\n
+                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH6_CTRL_TRIG</name>
+          <resetValue>0x00003000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0190</addressOffset>
+          <description>Alias for channel 6 CTRL register</description>
+          <name>CH6_AL1_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0194</addressOffset>
+          <description>Alias for channel 6 READ_ADDR register</description>
+          <name>CH6_AL1_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0198</addressOffset>
+          <description>Alias for channel 6 WRITE_ADDR register</description>
+          <name>CH6_AL1_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x019c</addressOffset>
+          <description>Alias for channel 6 TRANS_COUNT register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH6_AL1_TRANS_COUNT_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01a0</addressOffset>
+          <description>Alias for channel 6 CTRL register</description>
+          <name>CH6_AL2_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01a4</addressOffset>
+          <description>Alias for channel 6 TRANS_COUNT register</description>
+          <name>CH6_AL2_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01a8</addressOffset>
+          <description>Alias for channel 6 READ_ADDR register</description>
+          <name>CH6_AL2_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01ac</addressOffset>
+          <description>Alias for channel 6 WRITE_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH6_AL2_WRITE_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01b0</addressOffset>
+          <description>Alias for channel 6 CTRL register</description>
+          <name>CH6_AL3_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01b4</addressOffset>
+          <description>Alias for channel 6 WRITE_ADDR register</description>
+          <name>CH6_AL3_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01b8</addressOffset>
+          <description>Alias for channel 6 TRANS_COUNT register</description>
+          <name>CH6_AL3_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01bc</addressOffset>
+          <description>Alias for channel 6 READ_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH6_AL3_READ_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01c0</addressOffset>
+          <description>DMA Channel 7 Read Address pointer\n
+            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+          <name>CH7_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01c4</addressOffset>
+          <description>DMA Channel 7 Write Address pointer\n
+            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+          <name>CH7_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01c8</addressOffset>
+          <description>DMA Channel 7 Transfer Count\n
+            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
+            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
+            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
+            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+          <name>CH7_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x01cc</addressOffset>
+          <description>DMA Channel 7 Control and Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+              <name>AHB_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the channel received a read bus error. Write one to clear.\n
+                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>READ_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, the channel received a write bus error. Write one to clear.\n
+                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>WRITE_ERROR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
+                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+              <name>BUSY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
+                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+              <name>SNIFF_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <description>Apply byte-swap transformation to DMA data.\n
+                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+              <name>BSWAP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
+                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+              <name>IRQ_QUIET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:15]</bitRange>
+              <description>Select a Transfer Request signal.\n
+                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
+                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Select Timer 0 as TREQ</description>
+                  <name>TIMER0</name>
+                  <value>59</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 1 as TREQ</description>
+                  <name>TIMER1</name>
+                  <value>60</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 2 as TREQ (Optional)</description>
+                  <name>TIMER2</name>
+                  <value>61</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 3 as TREQ (Optional)</description>
+                  <name>TIMER3</name>
+                  <value>62</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Permanent request, for unpaced transfers.</description>
+                  <name>PERMANENT</name>
+                  <value>63</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TREQ_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:11]</bitRange>
+              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
+                Reset value is equal to channel number (7).</description>
+              <name>CHAIN_TO</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Select whether RING_SIZE applies to read or write addresses.\n
+                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+              <name>RING_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:6]</bitRange>
+              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RING_NONE</name>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RING_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
+                Generally this should be disabled for memory-to-peripheral transfers.</description>
+              <name>INCR_WRITE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
+                Generally this should be disabled for peripheral-to-memory transfers.</description>
+              <name>INCR_READ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:2]</bitRange>
+              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SIZE_BYTE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_HALFWORD</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_WORD</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DATA_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
+                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+              <name>HIGH_PRIORITY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>DMA Channel Enable.\n
+                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH7_CTRL_TRIG</name>
+          <resetValue>0x00003800</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01d0</addressOffset>
+          <description>Alias for channel 7 CTRL register</description>
+          <name>CH7_AL1_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01d4</addressOffset>
+          <description>Alias for channel 7 READ_ADDR register</description>
+          <name>CH7_AL1_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01d8</addressOffset>
+          <description>Alias for channel 7 WRITE_ADDR register</description>
+          <name>CH7_AL1_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01dc</addressOffset>
+          <description>Alias for channel 7 TRANS_COUNT register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH7_AL1_TRANS_COUNT_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01e0</addressOffset>
+          <description>Alias for channel 7 CTRL register</description>
+          <name>CH7_AL2_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01e4</addressOffset>
+          <description>Alias for channel 7 TRANS_COUNT register</description>
+          <name>CH7_AL2_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01e8</addressOffset>
+          <description>Alias for channel 7 READ_ADDR register</description>
+          <name>CH7_AL2_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01ec</addressOffset>
+          <description>Alias for channel 7 WRITE_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH7_AL2_WRITE_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01f0</addressOffset>
+          <description>Alias for channel 7 CTRL register</description>
+          <name>CH7_AL3_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01f4</addressOffset>
+          <description>Alias for channel 7 WRITE_ADDR register</description>
+          <name>CH7_AL3_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01f8</addressOffset>
+          <description>Alias for channel 7 TRANS_COUNT register</description>
+          <name>CH7_AL3_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x01fc</addressOffset>
+          <description>Alias for channel 7 READ_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH7_AL3_READ_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0200</addressOffset>
+          <description>DMA Channel 8 Read Address pointer\n
+            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+          <name>CH8_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0204</addressOffset>
+          <description>DMA Channel 8 Write Address pointer\n
+            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+          <name>CH8_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0208</addressOffset>
+          <description>DMA Channel 8 Transfer Count\n
+            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
+            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
+            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
+            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+          <name>CH8_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x020c</addressOffset>
+          <description>DMA Channel 8 Control and Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+              <name>AHB_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the channel received a read bus error. Write one to clear.\n
+                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>READ_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, the channel received a write bus error. Write one to clear.\n
+                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>WRITE_ERROR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
+                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+              <name>BUSY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
+                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+              <name>SNIFF_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <description>Apply byte-swap transformation to DMA data.\n
+                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+              <name>BSWAP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
+                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+              <name>IRQ_QUIET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:15]</bitRange>
+              <description>Select a Transfer Request signal.\n
+                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
+                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Select Timer 0 as TREQ</description>
+                  <name>TIMER0</name>
+                  <value>59</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 1 as TREQ</description>
+                  <name>TIMER1</name>
+                  <value>60</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 2 as TREQ (Optional)</description>
+                  <name>TIMER2</name>
+                  <value>61</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 3 as TREQ (Optional)</description>
+                  <name>TIMER3</name>
+                  <value>62</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Permanent request, for unpaced transfers.</description>
+                  <name>PERMANENT</name>
+                  <value>63</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TREQ_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:11]</bitRange>
+              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
+                Reset value is equal to channel number (8).</description>
+              <name>CHAIN_TO</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Select whether RING_SIZE applies to read or write addresses.\n
+                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+              <name>RING_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:6]</bitRange>
+              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RING_NONE</name>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RING_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
+                Generally this should be disabled for memory-to-peripheral transfers.</description>
+              <name>INCR_WRITE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
+                Generally this should be disabled for peripheral-to-memory transfers.</description>
+              <name>INCR_READ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:2]</bitRange>
+              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SIZE_BYTE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_HALFWORD</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_WORD</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DATA_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
+                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+              <name>HIGH_PRIORITY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>DMA Channel Enable.\n
+                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH8_CTRL_TRIG</name>
+          <resetValue>0x00004000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0210</addressOffset>
+          <description>Alias for channel 8 CTRL register</description>
+          <name>CH8_AL1_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0214</addressOffset>
+          <description>Alias for channel 8 READ_ADDR register</description>
+          <name>CH8_AL1_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0218</addressOffset>
+          <description>Alias for channel 8 WRITE_ADDR register</description>
+          <name>CH8_AL1_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x021c</addressOffset>
+          <description>Alias for channel 8 TRANS_COUNT register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH8_AL1_TRANS_COUNT_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0220</addressOffset>
+          <description>Alias for channel 8 CTRL register</description>
+          <name>CH8_AL2_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0224</addressOffset>
+          <description>Alias for channel 8 TRANS_COUNT register</description>
+          <name>CH8_AL2_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0228</addressOffset>
+          <description>Alias for channel 8 READ_ADDR register</description>
+          <name>CH8_AL2_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x022c</addressOffset>
+          <description>Alias for channel 8 WRITE_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH8_AL2_WRITE_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0230</addressOffset>
+          <description>Alias for channel 8 CTRL register</description>
+          <name>CH8_AL3_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0234</addressOffset>
+          <description>Alias for channel 8 WRITE_ADDR register</description>
+          <name>CH8_AL3_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0238</addressOffset>
+          <description>Alias for channel 8 TRANS_COUNT register</description>
+          <name>CH8_AL3_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x023c</addressOffset>
+          <description>Alias for channel 8 READ_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH8_AL3_READ_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0240</addressOffset>
+          <description>DMA Channel 9 Read Address pointer\n
+            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+          <name>CH9_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0244</addressOffset>
+          <description>DMA Channel 9 Write Address pointer\n
+            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+          <name>CH9_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0248</addressOffset>
+          <description>DMA Channel 9 Transfer Count\n
+            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
+            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
+            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
+            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+          <name>CH9_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x024c</addressOffset>
+          <description>DMA Channel 9 Control and Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+              <name>AHB_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the channel received a read bus error. Write one to clear.\n
+                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>READ_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, the channel received a write bus error. Write one to clear.\n
+                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>WRITE_ERROR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
+                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+              <name>BUSY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
+                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+              <name>SNIFF_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <description>Apply byte-swap transformation to DMA data.\n
+                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+              <name>BSWAP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
+                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+              <name>IRQ_QUIET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:15]</bitRange>
+              <description>Select a Transfer Request signal.\n
+                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
+                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Select Timer 0 as TREQ</description>
+                  <name>TIMER0</name>
+                  <value>59</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 1 as TREQ</description>
+                  <name>TIMER1</name>
+                  <value>60</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 2 as TREQ (Optional)</description>
+                  <name>TIMER2</name>
+                  <value>61</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 3 as TREQ (Optional)</description>
+                  <name>TIMER3</name>
+                  <value>62</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Permanent request, for unpaced transfers.</description>
+                  <name>PERMANENT</name>
+                  <value>63</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TREQ_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:11]</bitRange>
+              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
+                Reset value is equal to channel number (9).</description>
+              <name>CHAIN_TO</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Select whether RING_SIZE applies to read or write addresses.\n
+                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+              <name>RING_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:6]</bitRange>
+              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RING_NONE</name>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RING_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
+                Generally this should be disabled for memory-to-peripheral transfers.</description>
+              <name>INCR_WRITE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
+                Generally this should be disabled for peripheral-to-memory transfers.</description>
+              <name>INCR_READ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:2]</bitRange>
+              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SIZE_BYTE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_HALFWORD</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_WORD</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DATA_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
+                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+              <name>HIGH_PRIORITY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>DMA Channel Enable.\n
+                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH9_CTRL_TRIG</name>
+          <resetValue>0x00004800</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0250</addressOffset>
+          <description>Alias for channel 9 CTRL register</description>
+          <name>CH9_AL1_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0254</addressOffset>
+          <description>Alias for channel 9 READ_ADDR register</description>
+          <name>CH9_AL1_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0258</addressOffset>
+          <description>Alias for channel 9 WRITE_ADDR register</description>
+          <name>CH9_AL1_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x025c</addressOffset>
+          <description>Alias for channel 9 TRANS_COUNT register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH9_AL1_TRANS_COUNT_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0260</addressOffset>
+          <description>Alias for channel 9 CTRL register</description>
+          <name>CH9_AL2_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0264</addressOffset>
+          <description>Alias for channel 9 TRANS_COUNT register</description>
+          <name>CH9_AL2_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0268</addressOffset>
+          <description>Alias for channel 9 READ_ADDR register</description>
+          <name>CH9_AL2_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x026c</addressOffset>
+          <description>Alias for channel 9 WRITE_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH9_AL2_WRITE_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0270</addressOffset>
+          <description>Alias for channel 9 CTRL register</description>
+          <name>CH9_AL3_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0274</addressOffset>
+          <description>Alias for channel 9 WRITE_ADDR register</description>
+          <name>CH9_AL3_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0278</addressOffset>
+          <description>Alias for channel 9 TRANS_COUNT register</description>
+          <name>CH9_AL3_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x027c</addressOffset>
+          <description>Alias for channel 9 READ_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH9_AL3_READ_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0280</addressOffset>
+          <description>DMA Channel 10 Read Address pointer\n
+            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+          <name>CH10_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0284</addressOffset>
+          <description>DMA Channel 10 Write Address pointer\n
+            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+          <name>CH10_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0288</addressOffset>
+          <description>DMA Channel 10 Transfer Count\n
+            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
+            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
+            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
+            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+          <name>CH10_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x028c</addressOffset>
+          <description>DMA Channel 10 Control and Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+              <name>AHB_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the channel received a read bus error. Write one to clear.\n
+                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>READ_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, the channel received a write bus error. Write one to clear.\n
+                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>WRITE_ERROR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
+                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+              <name>BUSY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
+                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+              <name>SNIFF_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <description>Apply byte-swap transformation to DMA data.\n
+                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+              <name>BSWAP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
+                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+              <name>IRQ_QUIET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:15]</bitRange>
+              <description>Select a Transfer Request signal.\n
+                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
+                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Select Timer 0 as TREQ</description>
+                  <name>TIMER0</name>
+                  <value>59</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 1 as TREQ</description>
+                  <name>TIMER1</name>
+                  <value>60</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 2 as TREQ (Optional)</description>
+                  <name>TIMER2</name>
+                  <value>61</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 3 as TREQ (Optional)</description>
+                  <name>TIMER3</name>
+                  <value>62</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Permanent request, for unpaced transfers.</description>
+                  <name>PERMANENT</name>
+                  <value>63</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TREQ_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:11]</bitRange>
+              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
+                Reset value is equal to channel number (10).</description>
+              <name>CHAIN_TO</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Select whether RING_SIZE applies to read or write addresses.\n
+                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+              <name>RING_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:6]</bitRange>
+              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RING_NONE</name>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RING_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
+                Generally this should be disabled for memory-to-peripheral transfers.</description>
+              <name>INCR_WRITE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
+                Generally this should be disabled for peripheral-to-memory transfers.</description>
+              <name>INCR_READ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:2]</bitRange>
+              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SIZE_BYTE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_HALFWORD</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_WORD</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DATA_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
+                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+              <name>HIGH_PRIORITY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>DMA Channel Enable.\n
+                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH10_CTRL_TRIG</name>
+          <resetValue>0x00005000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0290</addressOffset>
+          <description>Alias for channel 10 CTRL register</description>
+          <name>CH10_AL1_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0294</addressOffset>
+          <description>Alias for channel 10 READ_ADDR register</description>
+          <name>CH10_AL1_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0298</addressOffset>
+          <description>Alias for channel 10 WRITE_ADDR register</description>
+          <name>CH10_AL1_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x029c</addressOffset>
+          <description>Alias for channel 10 TRANS_COUNT register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH10_AL1_TRANS_COUNT_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02a0</addressOffset>
+          <description>Alias for channel 10 CTRL register</description>
+          <name>CH10_AL2_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02a4</addressOffset>
+          <description>Alias for channel 10 TRANS_COUNT register</description>
+          <name>CH10_AL2_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02a8</addressOffset>
+          <description>Alias for channel 10 READ_ADDR register</description>
+          <name>CH10_AL2_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02ac</addressOffset>
+          <description>Alias for channel 10 WRITE_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH10_AL2_WRITE_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02b0</addressOffset>
+          <description>Alias for channel 10 CTRL register</description>
+          <name>CH10_AL3_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02b4</addressOffset>
+          <description>Alias for channel 10 WRITE_ADDR register</description>
+          <name>CH10_AL3_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02b8</addressOffset>
+          <description>Alias for channel 10 TRANS_COUNT register</description>
+          <name>CH10_AL3_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02bc</addressOffset>
+          <description>Alias for channel 10 READ_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH10_AL3_READ_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02c0</addressOffset>
+          <description>DMA Channel 11 Read Address pointer\n
+            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.</description>
+          <name>CH11_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02c4</addressOffset>
+          <description>DMA Channel 11 Write Address pointer\n
+            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.</description>
+          <name>CH11_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02c8</addressOffset>
+          <description>DMA Channel 11 Transfer Count\n
+            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n
+            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n
+            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n
+            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.</description>
+          <name>CH11_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x02cc</addressOffset>
+          <description>DMA Channel 11 Control and Status</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.</description>
+              <name>AHB_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the channel received a read bus error. Write one to clear.\n
+                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>READ_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, the channel received a write bus error. Write one to clear.\n
+                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>WRITE_ERROR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n
+                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.</description>
+              <name>BUSY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <description>If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n
+                This allows checksum to be enabled or disabled on a per-control- block basis.</description>
+              <name>SNIFF_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <description>Apply byte-swap transformation to DMA data.\n
+                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.</description>
+              <name>BSWAP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <description>In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n
+                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.</description>
+              <name>IRQ_QUIET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:15]</bitRange>
+              <description>Select a Transfer Request signal.\n
+                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n
+                0x0 to 0x3a -&gt; select DREQ n as TREQ</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Select Timer 0 as TREQ</description>
+                  <name>TIMER0</name>
+                  <value>59</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 1 as TREQ</description>
+                  <name>TIMER1</name>
+                  <value>60</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 2 as TREQ (Optional)</description>
+                  <name>TIMER2</name>
+                  <value>61</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Select Timer 3 as TREQ (Optional)</description>
+                  <name>TIMER3</name>
+                  <value>62</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Permanent request, for unpaced transfers.</description>
+                  <name>PERMANENT</name>
+                  <value>63</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>TREQ_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:11]</bitRange>
+              <description>When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.\n
+                Reset value is equal to channel number (11).</description>
+              <name>CHAIN_TO</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Select whether RING_SIZE applies to read or write addresses.\n
+                If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped.</description>
+              <name>RING_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:6]</bitRange>
+              <description>Size of address wrap region. If 0, don't wrap. For values n &gt; 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n
+                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RING_NONE</name>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>RING_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n
+                Generally this should be disabled for memory-to-peripheral transfers.</description>
+              <name>INCR_WRITE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n
+                Generally this should be disabled for peripheral-to-memory transfers.</description>
+              <name>INCR_READ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:2]</bitRange>
+              <description>Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>SIZE_BYTE</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_HALFWORD</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>SIZE_WORD</name>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DATA_SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n
+                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.</description>
+              <name>HIGH_PRIORITY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>DMA Channel Enable.\n
+                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>CH11_CTRL_TRIG</name>
+          <resetValue>0x00005800</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02d0</addressOffset>
+          <description>Alias for channel 11 CTRL register</description>
+          <name>CH11_AL1_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02d4</addressOffset>
+          <description>Alias for channel 11 READ_ADDR register</description>
+          <name>CH11_AL1_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02d8</addressOffset>
+          <description>Alias for channel 11 WRITE_ADDR register</description>
+          <name>CH11_AL1_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02dc</addressOffset>
+          <description>Alias for channel 11 TRANS_COUNT register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH11_AL1_TRANS_COUNT_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02e0</addressOffset>
+          <description>Alias for channel 11 CTRL register</description>
+          <name>CH11_AL2_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02e4</addressOffset>
+          <description>Alias for channel 11 TRANS_COUNT register</description>
+          <name>CH11_AL2_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02e8</addressOffset>
+          <description>Alias for channel 11 READ_ADDR register</description>
+          <name>CH11_AL2_READ_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02ec</addressOffset>
+          <description>Alias for channel 11 WRITE_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH11_AL2_WRITE_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02f0</addressOffset>
+          <description>Alias for channel 11 CTRL register</description>
+          <name>CH11_AL3_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02f4</addressOffset>
+          <description>Alias for channel 11 WRITE_ADDR register</description>
+          <name>CH11_AL3_WRITE_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02f8</addressOffset>
+          <description>Alias for channel 11 TRANS_COUNT register</description>
+          <name>CH11_AL3_TRANS_COUNT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x02fc</addressOffset>
+          <description>Alias for channel 11 READ_ADDR register\n
+            This is a trigger register (0xc). Writing a nonzero value will\n
+            reload the channel counter and start the channel.</description>
+          <name>CH11_AL3_READ_ADDR_TRIG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0400</addressOffset>
+          <description>Interrupt Status (raw)</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.\n\n
+                Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.\n\n
+                This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.\n\n
+                It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.</description>
+              <name>INTR</name>
+            </field>
+          </fields>
+          <name>INTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0404</addressOffset>
+          <description>Interrupt Enables for IRQ 0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Set bit n to pass interrupts from channel n to DMA IRQ 0.</description>
+              <name>INTE0</name>
+            </field>
+          </fields>
+          <name>INTE0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0408</addressOffset>
+          <description>Force Interrupts</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.</description>
+              <name>INTF0</name>
+            </field>
+          </fields>
+          <name>INTF0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x040c</addressOffset>
+          <description>Interrupt Status for IRQ 0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.\n
+                Channel interrupts can be cleared by writing a bit mask here.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>INTS0</name>
+            </field>
+          </fields>
+          <name>INTS0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0414</addressOffset>
+          <description>Interrupt Enables for IRQ 1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Set bit n to pass interrupts from channel n to DMA IRQ 1.</description>
+              <name>INTE1</name>
+            </field>
+          </fields>
+          <name>INTE1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0418</addressOffset>
+          <description>Force Interrupts for IRQ 1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.</description>
+              <name>INTF1</name>
+            </field>
+          </fields>
+          <name>INTF1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x041c</addressOffset>
+          <description>Interrupt Status (masked) for IRQ 1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.\n
+                Channel interrupts can be cleared by writing a bit mask here.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>INTS1</name>
+            </field>
+          </fields>
+          <name>INTS1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0420</addressOffset>
+          <description>Pacing (X/Y) Fractional Timer\n
+            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
+              <name>X</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
+              <name>Y</name>
+            </field>
+          </fields>
+          <name>TIMER0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0424</addressOffset>
+          <description>Pacing (X/Y) Fractional Timer\n
+            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
+              <name>X</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
+              <name>Y</name>
+            </field>
+          </fields>
+          <name>TIMER1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0428</addressOffset>
+          <description>Pacing (X/Y) Fractional Timer\n
+            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
+              <name>X</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
+              <name>Y</name>
+            </field>
+          </fields>
+          <name>TIMER2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x042c</addressOffset>
+          <description>Pacing (X/Y) Fractional Timer\n
+            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <description>Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.</description>
+              <name>X</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.</description>
+              <name>Y</name>
+            </field>
+          </fields>
+          <name>TIMER3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0430</addressOffset>
+          <description>Trigger one or more channels simultaneously</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>MULTI_CHAN_TRIGGER</name>
+            </field>
+          </fields>
+          <name>MULTI_CHAN_TRIGGER</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0434</addressOffset>
+          <description>Sniffer Control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.</description>
+              <name>OUT_INV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.</description>
+              <name>OUT_REV</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Locally perform a byte reverse on the sniffed data, before feeding into checksum.\n\n
+                Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view.</description>
+              <name>BSWAP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:5]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>Calculate a CRC-32 (IEEE802.3 polynomial)</description>
+                  <name>CRC32</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data</description>
+                  <name>CRC32R</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Calculate a CRC-16-CCITT</description>
+                  <name>CRC16</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Calculate a CRC-16-CCITT with bit reversed data</description>
+                  <name>CRC16R</name>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>XOR reduction over all data. == 1 if the total 1 population count is odd.</description>
+                  <name>EVEN</name>
+                  <value>14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)</description>
+                  <name>SUM</name>
+                  <value>15</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>CALC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:1]</bitRange>
+              <description>DMA channel for Sniffer to observe</description>
+              <name>DMACH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enable sniffer</description>
+              <name>EN</name>
+            </field>
+          </fields>
+          <name>SNIFF_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0438</addressOffset>
+          <description>Data accumulator for sniff hardware\n
+            Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.</description>
+          <name>SNIFF_DATA</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0440</addressOffset>
+          <description>Debug RAF, WAF, TDF levels</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:16]</bitRange>
+              <description>Current Read-Address-FIFO fill level</description>
+              <name>RAF_LVL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:8]</bitRange>
+              <description>Current Write-Address-FIFO fill level</description>
+              <name>WAF_LVL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:0]</bitRange>
+              <description>Current Transfer-Data-FIFO fill level</description>
+              <name>TDF_LVL</name>
+            </field>
+          </fields>
+          <name>FIFO_LEVELS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0444</addressOffset>
+          <description>Abort an in-progress transfer sequence on one or more channels</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.\n\n
+                After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>CHAN_ABORT</name>
+            </field>
+          </fields>
+          <name>CHAN_ABORT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0448</addressOffset>
+          <description>The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:0]</bitRange>
+              <name>N_CHANNELS</name>
+            </field>
+          </fields>
+          <name>N_CHANNELS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0800</addressOffset>
+          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH0_DBG_CTDREQ</name>
+            </field>
+          </fields>
+          <name>CH0_DBG_CTDREQ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0804</addressOffset>
+          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+          <name>CH0_DBG_TCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0840</addressOffset>
+          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH1_DBG_CTDREQ</name>
+            </field>
+          </fields>
+          <name>CH1_DBG_CTDREQ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0844</addressOffset>
+          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+          <name>CH1_DBG_TCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0880</addressOffset>
+          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH2_DBG_CTDREQ</name>
+            </field>
+          </fields>
+          <name>CH2_DBG_CTDREQ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0884</addressOffset>
+          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+          <name>CH2_DBG_TCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x08c0</addressOffset>
+          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH3_DBG_CTDREQ</name>
+            </field>
+          </fields>
+          <name>CH3_DBG_CTDREQ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x08c4</addressOffset>
+          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+          <name>CH3_DBG_TCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0900</addressOffset>
+          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH4_DBG_CTDREQ</name>
+            </field>
+          </fields>
+          <name>CH4_DBG_CTDREQ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0904</addressOffset>
+          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+          <name>CH4_DBG_TCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0940</addressOffset>
+          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH5_DBG_CTDREQ</name>
+            </field>
+          </fields>
+          <name>CH5_DBG_CTDREQ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0944</addressOffset>
+          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+          <name>CH5_DBG_TCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0980</addressOffset>
+          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH6_DBG_CTDREQ</name>
+            </field>
+          </fields>
+          <name>CH6_DBG_CTDREQ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0984</addressOffset>
+          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+          <name>CH6_DBG_TCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x09c0</addressOffset>
+          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH7_DBG_CTDREQ</name>
+            </field>
+          </fields>
+          <name>CH7_DBG_CTDREQ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x09c4</addressOffset>
+          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+          <name>CH7_DBG_TCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0a00</addressOffset>
+          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH8_DBG_CTDREQ</name>
+            </field>
+          </fields>
+          <name>CH8_DBG_CTDREQ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0a04</addressOffset>
+          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+          <name>CH8_DBG_TCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0a40</addressOffset>
+          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH9_DBG_CTDREQ</name>
+            </field>
+          </fields>
+          <name>CH9_DBG_CTDREQ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0a44</addressOffset>
+          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+          <name>CH9_DBG_TCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0a80</addressOffset>
+          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH10_DBG_CTDREQ</name>
+            </field>
+          </fields>
+          <name>CH10_DBG_CTDREQ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0a84</addressOffset>
+          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+          <name>CH10_DBG_TCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0ac0</addressOffset>
+          <description>Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CH11_DBG_CTDREQ</name>
+            </field>
+          </fields>
+          <name>CH11_DBG_CTDREQ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0ac4</addressOffset>
+          <description>Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</description>
+          <name>CH11_DBG_TCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x0100</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x50100000</baseAddress>
+      <description>DPRAM layout for USB device.</description>
+      <name>USBCTRL_DPRAM</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Bytes 0-3 of the SETUP packet from the host.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <name>WVALUE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:8]</bitRange>
+              <name>BREQUEST</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <name>BMREQUESTTYPE</name>
+            </field>
+          </fields>
+          <name>SETUP_PACKET_LOW</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Bytes 4-7 of the setup packet from the host.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <name>WLENGTH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>WINDEX</name>
+            </field>
+          </fields>
+          <name>SETUP_PACKET_HIGH</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP1_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP1_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP2_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP2_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP3_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP3_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP4_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0024</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP4_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0028</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP5_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x002c</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP5_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0030</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP6_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0034</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP6_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0038</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP7_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x003c</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP7_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0040</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP8_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0044</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP8_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0048</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP9_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x004c</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP9_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0050</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP10_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0054</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP10_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0058</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP11_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x005c</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP11_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0060</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP12_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0064</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP12_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0068</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP13_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x006c</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP13_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0070</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP14_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0074</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP14_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0078</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP15_IN_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x007c</addressOffset>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.</description>
+              <name>ENABLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>This endpoint is double buffered.</description>
+              <name>DOUBLE_BUFFERED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Trigger an interrupt each time a buffer is done.</description>
+              <name>INTERRUPT_PER_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.</description>
+              <name>INTERRUPT_PER_DOUBLE_BUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:26]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Control</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Isochronous</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Bulk</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Interrupt</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>ENDPOINT_TYPE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Trigger an interrupt if a STALL is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Trigger an interrupt if a NAK is sent. Intended for debug only.</description>
+              <name>INTERRUPT_ON_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <description>64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.</description>
+              <name>BUFFER_ADDRESS</name>
+            </field>
+          </fields>
+          <name>EP15_OUT_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0080</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP0_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0084</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP0_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0088</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP1_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x008c</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP1_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0090</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP2_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0094</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP2_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0098</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP3_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x009c</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP3_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a0</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP4_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a4</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP4_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a8</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP5_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00ac</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP5_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b0</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP6_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b4</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP6_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b8</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP7_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00bc</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP7_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00c0</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP8_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00c4</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP8_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00c8</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP9_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00cc</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP9_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00d0</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP10_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00d4</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP10_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00d8</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP11_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00dc</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP11_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00e0</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP12_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00e4</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP12_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00e8</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP13_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00ec</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP13_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f0</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP14_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f4</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP14_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f8</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP15_IN_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00fc</addressOffset>
+          <description>Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n
+            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Buffer 1 is the last buffer of the transfer.</description>
+              <name>LAST_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>The data pid of buffer 1.</description>
+              <name>PID_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:27]</bitRange>
+              <description>The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n
+                For a non Isochronous endpoint the offset is always 64 bytes.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>128</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>256</name>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>512</name>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>1024</name>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>DOUBLE_BUFFER_ISO_OFFSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>The length of the data in buffer 1.</description>
+              <name>LENGTH_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.</description>
+              <name>FULL_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Buffer 0 is the last buffer of the transfer.</description>
+              <name>LAST_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>The data pid of buffer 0.</description>
+              <name>PID_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Reset the buffer selector to buffer 0.</description>
+              <name>RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Reply with a stall (valid for both buffers).</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.</description>
+              <name>AVAILABLE_0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>The length of the data in buffer 0.</description>
+              <name>LENGTH_0</name>
+            </field>
+          </fields>
+          <name>EP15_OUT_BUFFER_CONTROL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x50110000</baseAddress>
+      <description>USB FS/LS controller device registers</description>
+      <interrupt>
+        <name>USBCTRL_IRQ</name>
+        <value>5</value>
+      </interrupt>
+      <name>USBCTRL_REGS</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>Device address and endpoint control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Device endpoint to send data to. Only valid for HOST mode.</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with.</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Interrupt endpoint 1. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>Interrupt endpoint 2. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>Interrupt endpoint 3. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>Interrupt endpoint 4. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP4</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>Interrupt endpoint 5. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP5</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>Interrupt endpoint 6. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP6</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>Interrupt endpoint 7. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP7</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>Interrupt endpoint 8. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP8</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0024</addressOffset>
+          <description>Interrupt endpoint 9. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP9</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0028</addressOffset>
+          <description>Interrupt endpoint 10. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP10</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x002c</addressOffset>
+          <description>Interrupt endpoint 11. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP11</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0030</addressOffset>
+          <description>Interrupt endpoint 12. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP12</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0034</addressOffset>
+          <description>Interrupt endpoint 13. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP13</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0038</addressOffset>
+          <description>Interrupt endpoint 14. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP14</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x003c</addressOffset>
+          <description>Interrupt endpoint 15. Only valid for HOST mode.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Interrupt EP requires preamble (is a low speed device on a full speed hub)</description>
+              <name>INTEP_PREAMBLE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direction of the interrupt endpoint. In=0, Out=1</description>
+              <name>INTEP_DIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Endpoint number of the interrupt endpoint</description>
+              <name>ENDPOINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:0]</bitRange>
+              <description>Device address</description>
+              <name>ADDRESS</name>
+            </field>
+          </fields>
+          <name>ADDR_ENDP15</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0040</addressOffset>
+          <description>Main control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Reduced timings for simulation</description>
+              <name>SIM_TIMING</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Device mode = 0, Host mode = 1</description>
+              <name>HOST_NDEVICE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enable controller</description>
+              <name>CONTROLLER_EN</name>
+            </field>
+          </fields>
+          <name>MAIN_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0044</addressOffset>
+          <description>Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time.</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[10:0]</bitRange>
+              <name>COUNT</name>
+            </field>
+          </fields>
+          <name>SOF_WR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0048</addressOffset>
+          <description>Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:0]</bitRange>
+              <name>COUNT</name>
+            </field>
+          </fields>
+          <name>SOF_RD</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x004c</addressOffset>
+          <description>SIE control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL</description>
+              <name>EP0_INT_STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>Device: EP0 single buffered = 0, double buffered = 1</description>
+              <name>EP0_DOUBLE_BUF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Device: Set bit in BUFF_STATUS for every buffer completed on EP0</description>
+              <name>EP0_INT_1BUF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0</description>
+              <name>EP0_INT_2BUF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <description>Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK</description>
+              <name>EP0_INT_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>Direct bus drive enable</description>
+              <name>DIRECT_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Direct control of DP</description>
+              <name>DIRECT_DP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <description>Direct control of DM</description>
+              <name>DIRECT_DM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>Power down bus transceiver</description>
+              <name>TRANSCEIVER_PD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Device: Pull-up strength (0=1K2, 1=2k3)</description>
+              <name>RPU_OPT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Device: Enable pull up resistor</description>
+              <name>PULLUP_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Host: Enable pull down resistors</description>
+              <name>PULLDOWN_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>Host: Reset bus</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>RESET_BUS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Device: Remote wakeup. Device can initiate its own resume after suspend.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>RESUME</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Host: Enable VBUS</description>
+              <name>VBUS_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Host: Enable keep alive packet (for low speed bus)</description>
+              <name>KEEP_ALIVE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Host: Enable SOF generation (for full speed bus)</description>
+              <name>SOF_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Host: Delay packet(s) until after SOF</description>
+              <name>SOF_SYNC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Host: Preable enable for LS device on FS hub</description>
+              <name>PREAMBLE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Host: Stop transaction</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>STOP_TRANS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Host: Receive transaction (IN to host)</description>
+              <name>RECEIVE_DATA</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Host: Send transaction (OUT from host)</description>
+              <name>SEND_DATA</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Host: Send Setup packet</description>
+              <name>SEND_SETUP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Host: Start transaction</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>START_TRANS</name>
+            </field>
+          </fields>
+          <name>SIE_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0050</addressOffset>
+          <description>SIE status register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Data Sequence Error.\n\n
+                The device can raise a sequence error in the following conditions:\n\n
+                * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM\n\n
+                The host can raise a data sequence error in the following conditions:\n\n
+                * An IN packet from the device has the wrong data PID</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>DATA_SEQ_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>ACK received. Raised by both host and device.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>ACK_REC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>Host: STALL received</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>STALL_REC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>Host: NAK received</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>NAK_REC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <description>RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>RX_TIMEOUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>RX overflow is raised by the Serial RX engine if the incoming data is too fast.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>RX_OVERFLOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Bit Stuff Error. Raised by the Serial RX engine.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>BIT_STUFF_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <description>CRC Error. Raised by the Serial RX engine.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CRC_ERROR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <description>Device: bus reset received</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>BUS_RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>Transaction complete.\n\n
+                Raised by device if:\n\n
+                * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register\n\n
+                Raised by host if:\n\n
+                * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>TRANS_COMPLETE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Device: Setup packet received</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>SETUP_REC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Device: connected</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>CONNECTED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Host: Device has initiated a remote resume. Device: host has initiated a resume.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>RESUME</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <description>VBUS over current detected</description>
+              <name>VBUS_OVER_CURR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:8]</bitRange>
+              <description>Host: device speed. Disconnected = 00, LS = 01, FS = 10</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>SPEED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>SUSPENDED</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:2]</bitRange>
+              <description>USB bus line state</description>
+              <name>LINE_STATE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Device: VBUS Detected</description>
+              <name>VBUS_DETECTED</name>
+            </field>
+          </fields>
+          <name>SIE_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0054</addressOffset>
+          <description>interrupt endpoint control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:1]</bitRange>
+              <description>Host: Enable interrupt endpoint 1 -&gt; 15</description>
+              <name>INT_EP_ACTIVE</name>
+            </field>
+          </fields>
+          <name>INT_EP_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0058</addressOffset>
+          <description>Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP15_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP15_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP14_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP14_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP13_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP13_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP12_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP12_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP11_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP11_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP10_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP10_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP9_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP9_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP8_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP8_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP7_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP7_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP6_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP6_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP5_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP5_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP4_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP4_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP3_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP3_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP2_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP2_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP1_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP1_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP0_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP0_IN</name>
+            </field>
+          </fields>
+          <name>BUFF_STATUS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x005c</addressOffset>
+          <description>Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <name>EP15_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[30:30]</bitRange>
+              <name>EP15_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:29]</bitRange>
+              <name>EP14_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[28:28]</bitRange>
+              <name>EP14_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[27:27]</bitRange>
+              <name>EP13_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[26:26]</bitRange>
+              <name>EP13_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <name>EP12_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <name>EP12_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <name>EP11_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <name>EP11_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <name>EP10_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <name>EP10_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <name>EP9_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <name>EP9_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <name>EP8_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <name>EP8_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <name>EP7_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <name>EP7_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <name>EP6_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <name>EP6_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>EP5_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>EP5_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>EP4_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>EP4_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>EP3_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>EP3_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>EP2_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>EP2_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>EP1_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>EP1_IN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>EP0_OUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>EP0_IN</name>
+            </field>
+          </fields>
+          <name>BUFF_CPU_SHOULD_HANDLE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0060</addressOffset>
+          <description>Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <name>EP15_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <name>EP15_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <name>EP14_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <name>EP14_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <name>EP13_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <name>EP13_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <name>EP12_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <name>EP12_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <name>EP11_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <name>EP11_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <name>EP10_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <name>EP10_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <name>EP9_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <name>EP9_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <name>EP8_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <name>EP8_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>EP7_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <name>EP7_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <name>EP6_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>EP6_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>EP5_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>EP5_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>EP4_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>EP4_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>EP3_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>EP3_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>EP2_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>EP2_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>EP1_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>EP1_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>EP0_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>EP0_IN</name>
+            </field>
+          </fields>
+          <name>EP_ABORT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0064</addressOffset>
+          <description>Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP15_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP15_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP14_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP14_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP13_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP13_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP12_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP12_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP11_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP11_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP10_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP10_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP9_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP9_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP8_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP8_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP7_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP7_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP6_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP6_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP5_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP5_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP4_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP4_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP3_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP3_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP2_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP2_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP1_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP1_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP0_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP0_IN</name>
+            </field>
+          </fields>
+          <name>EP_ABORT_DONE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0068</addressOffset>
+          <description>Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>EP0_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>EP0_IN</name>
+            </field>
+          </fields>
+          <name>EP_STALL_ARM</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x006c</addressOffset>
+          <description>Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:16]</bitRange>
+              <description>NAK polling interval for a full speed device</description>
+              <name>DELAY_FS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:0]</bitRange>
+              <description>NAK polling interval for a low speed device</description>
+              <name>DELAY_LS</name>
+            </field>
+          </fields>
+          <name>NAK_POLL</name>
+          <resetValue>0x00100010</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0070</addressOffset>
+          <description>Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP15_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP15_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP14_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP14_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP13_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP13_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP12_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:24]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP12_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:23]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP11_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP11_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP10_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:20]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP10_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP9_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP9_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP8_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP8_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP7_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP7_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP6_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP6_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP5_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP5_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP4_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP4_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP3_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP3_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP2_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP2_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP1_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP1_IN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP0_OUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>EP0_IN</name>
+            </field>
+          </fields>
+          <name>EP_STATUS_STALL_NAK</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0074</addressOffset>
+          <description>Where to connect the USB controller. Should be to_phy by default.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>SOFTCON</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>TO_DIGITAL_PAD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>TO_EXTPHY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>TO_PHY</name>
+            </field>
+          </fields>
+          <name>USB_MUXING</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0078</addressOffset>
+          <description>Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>OVERCURR_DETECT_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>OVERCURR_DETECT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>VBUS_DETECT_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>VBUS_DETECT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>VBUS_EN_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>VBUS_EN</name>
+            </field>
+          </fields>
+          <name>USB_PWR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x007c</addressOffset>
+          <description>This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <description>DM over voltage</description>
+              <name>DM_OVV</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:21]</bitRange>
+              <description>DP over voltage</description>
+              <name>DP_OVV</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:20]</bitRange>
+              <description>DM overcurrent</description>
+              <name>DM_OVCN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>DP overcurrent</description>
+              <name>DP_OVCN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <description>DPM pin state</description>
+              <name>RX_DM</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>DPP pin state</description>
+              <name>RX_DP</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Differential RX</description>
+              <name>RX_DD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>TX_DIFFMODE=0: Single ended mode\n
+                TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)</description>
+              <name>TX_DIFFMODE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>TX_FSSLEW=0: Low speed slew rate\n
+                TX_FSSLEW=1: Full speed slew rate</description>
+              <name>TX_FSSLEW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>TX power down override (if override enable is set). 1 = powered down.</description>
+              <name>TX_PD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>RX power down override (if override enable is set). 1 = powered down.</description>
+              <name>RX_PD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Output data. TX_DIFFMODE=1, Ignored\n
+                TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM</description>
+              <name>TX_DM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP\n
+                If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP</description>
+              <name>TX_DP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Output enable. If TX_DIFFMODE=1, Ignored.\n
+                If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving</description>
+              <name>TX_DM_OE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving\n
+                If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving</description>
+              <name>TX_DP_OE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>DM pull down enable</description>
+              <name>DM_PULLDN_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>DM pull up enable</description>
+              <name>DM_PULLUP_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2</description>
+              <name>DM_PULLUP_HISEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>DP pull down enable</description>
+              <name>DP_PULLDN_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>DP pull up enable</description>
+              <name>DP_PULLUP_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2</description>
+              <name>DP_PULLUP_HISEL</name>
+            </field>
+          </fields>
+          <name>USBPHY_DIRECT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0080</addressOffset>
+          <description>Override enable for each control in usbphy_direct</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <name>TX_DIFFMODE_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <name>DM_PULLUP_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>TX_FSSLEW_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>TX_PD_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>RX_PD_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>TX_DM_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>TX_DP_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>TX_DM_OE_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>TX_DP_OE_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>DM_PULLDN_EN_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>DP_PULLDN_EN_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>DP_PULLUP_EN_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>DM_PULLUP_HISEL_OVERRIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>DP_PULLUP_HISEL_OVERRIDE_EN</name>
+            </field>
+          </fields>
+          <name>USBPHY_DIRECT_OVERRIDE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0084</addressOffset>
+          <description>Used to adjust trim values of USB phy pull down resistors.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:8]</bitRange>
+              <description>Value to drive to USB PHY\n
+                DM pulldown resistor trim control\n
+                Experimental data suggests that the reset value will work, but this register allows adjustment if required</description>
+              <name>DM_PULLDN_TRIM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>Value to drive to USB PHY\n
+                DP pulldown resistor trim control\n
+                Experimental data suggests that the reset value will work, but this register allows adjustment if required</description>
+              <name>DP_PULLDN_TRIM</name>
+            </field>
+          </fields>
+          <name>USBPHY_TRIM</name>
+          <resetValue>0x00001f1f</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x008c</addressOffset>
+          <description>Raw Interrupts</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
+              <name>EP_STALL_NAK</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
+              <name>ABORT_DONE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
+              <name>DEV_SOF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Device. Source: SIE_STATUS.SETUP_REC</description>
+              <name>SETUP_REQ</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
+              <name>DEV_RESUME_FROM_HOST</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
+              <name>DEV_SUSPEND</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
+              <name>DEV_CONN_DIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Source: SIE_STATUS.BUS_RESET</description>
+              <name>BUS_RESET</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
+              <name>VBUS_DETECT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Source: SIE_STATUS.STALL_REC</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Source: SIE_STATUS.CRC_ERROR</description>
+              <name>ERROR_CRC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
+              <name>ERROR_BIT_STUFF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Source: SIE_STATUS.RX_OVERFLOW</description>
+              <name>ERROR_RX_OVERFLOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Source: SIE_STATUS.RX_TIMEOUT</description>
+              <name>ERROR_RX_TIMEOUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
+              <name>ERROR_DATA_SEQ</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
+              <name>BUFF_STATUS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
+              <name>TRANS_COMPLETE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
+              <name>HOST_SOF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
+              <name>HOST_RESUME</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
+              <name>HOST_CONN_DIS</name>
+            </field>
+          </fields>
+          <name>INTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0090</addressOffset>
+          <description>Interrupt Enable</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
+              <name>EP_STALL_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
+              <name>ABORT_DONE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
+              <name>DEV_SOF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Device. Source: SIE_STATUS.SETUP_REC</description>
+              <name>SETUP_REQ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
+              <name>DEV_RESUME_FROM_HOST</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
+              <name>DEV_SUSPEND</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
+              <name>DEV_CONN_DIS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Source: SIE_STATUS.BUS_RESET</description>
+              <name>BUS_RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
+              <name>VBUS_DETECT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Source: SIE_STATUS.STALL_REC</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Source: SIE_STATUS.CRC_ERROR</description>
+              <name>ERROR_CRC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
+              <name>ERROR_BIT_STUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Source: SIE_STATUS.RX_OVERFLOW</description>
+              <name>ERROR_RX_OVERFLOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Source: SIE_STATUS.RX_TIMEOUT</description>
+              <name>ERROR_RX_TIMEOUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
+              <name>ERROR_DATA_SEQ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
+              <name>BUFF_STATUS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
+              <name>TRANS_COMPLETE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
+              <name>HOST_SOF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
+              <name>HOST_RESUME</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
+              <name>HOST_CONN_DIS</name>
+            </field>
+          </fields>
+          <name>INTE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0094</addressOffset>
+          <description>Interrupt Force</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
+              <name>EP_STALL_NAK</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
+              <name>ABORT_DONE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
+              <name>DEV_SOF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Device. Source: SIE_STATUS.SETUP_REC</description>
+              <name>SETUP_REQ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
+              <name>DEV_RESUME_FROM_HOST</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
+              <name>DEV_SUSPEND</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[13:13]</bitRange>
+              <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
+              <name>DEV_CONN_DIS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Source: SIE_STATUS.BUS_RESET</description>
+              <name>BUS_RESET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
+              <name>VBUS_DETECT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Source: SIE_STATUS.STALL_REC</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Source: SIE_STATUS.CRC_ERROR</description>
+              <name>ERROR_CRC</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
+              <name>ERROR_BIT_STUFF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Source: SIE_STATUS.RX_OVERFLOW</description>
+              <name>ERROR_RX_OVERFLOW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Source: SIE_STATUS.RX_TIMEOUT</description>
+              <name>ERROR_RX_TIMEOUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
+              <name>ERROR_DATA_SEQ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
+              <name>BUFF_STATUS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
+              <name>TRANS_COMPLETE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
+              <name>HOST_SOF</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
+              <name>HOST_RESUME</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
+              <name>HOST_CONN_DIS</name>
+            </field>
+          </fields>
+          <name>INTF</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0098</addressOffset>
+          <description>Interrupt status after masking &amp; forcing</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:19]</bitRange>
+              <description>Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.</description>
+              <name>EP_STALL_NAK</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[18:18]</bitRange>
+              <description>Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.</description>
+              <name>ABORT_DONE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD</description>
+              <name>DEV_SOF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Device. Source: SIE_STATUS.SETUP_REC</description>
+              <name>SETUP_REQ</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME</description>
+              <name>DEV_RESUME_FROM_HOST</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[14:14]</bitRange>
+              <description>Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED</description>
+              <name>DEV_SUSPEND</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[13:13]</bitRange>
+              <description>Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED</description>
+              <name>DEV_CONN_DIS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[12:12]</bitRange>
+              <description>Source: SIE_STATUS.BUS_RESET</description>
+              <name>BUS_RESET</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <description>Source: SIE_STATUS.VBUS_DETECTED</description>
+              <name>VBUS_DETECT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <description>Source: SIE_STATUS.STALL_REC</description>
+              <name>STALL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Source: SIE_STATUS.CRC_ERROR</description>
+              <name>ERROR_CRC</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <description>Source: SIE_STATUS.BIT_STUFF_ERROR</description>
+              <name>ERROR_BIT_STUFF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <description>Source: SIE_STATUS.RX_OVERFLOW</description>
+              <name>ERROR_RX_OVERFLOW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <description>Source: SIE_STATUS.RX_TIMEOUT</description>
+              <name>ERROR_RX_TIMEOUT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <description>Source: SIE_STATUS.DATA_SEQ_ERROR</description>
+              <name>ERROR_DATA_SEQ</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.</description>
+              <name>BUFF_STATUS</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.</description>
+              <name>TRANS_COMPLETE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD</description>
+              <name>HOST_SOF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME</description>
+              <name>HOST_RESUME</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED</description>
+              <name>HOST_CONN_DIS</name>
+            </field>
+          </fields>
+          <name>INTS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0x50200000</baseAddress>
+      <description>Programmable IO block</description>
+      <interrupt>
+        <name>PIO0_IRQ_0</name>
+        <value>7</value>
+      </interrupt>
+      <interrupt>
+        <name>PIO0_IRQ_1</name>
+        <value>8</value>
+      </interrupt>
+      <name>PIO0</name>
+      <registers>
+        <register>
+          <addressOffset>0x0000</addressOffset>
+          <description>PIO control register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:8]</bitRange>
+              <description>Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.\n\n
+                Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.\n\n
+                Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>CLKDIV_RESTART</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:4]</bitRange>
+              <description>Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.\n\n
+                Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.</description>
+              <modifiedWriteValues>clear</modifiedWriteValues>
+              <name>SM_RESTART</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <description>Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously.</description>
+              <name>SM_ENABLE</name>
+            </field>
+          </fields>
+          <name>CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>FIFO status register</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[27:24]</bitRange>
+              <description>State machine TX FIFO is empty</description>
+              <name>TXEMPTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:16]</bitRange>
+              <description>State machine TX FIFO is full</description>
+              <name>TXFULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:8]</bitRange>
+              <description>State machine RX FIFO is empty</description>
+              <name>RXEMPTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:0]</bitRange>
+              <description>State machine RX FIFO is full</description>
+              <name>RXFULL</name>
+            </field>
+          </fields>
+          <name>FSTAT</name>
+          <resetValue>0x0f000f00</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>FIFO debug register</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:24]</bitRange>
+              <description>State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>TXSTALL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:16]</bitRange>
+              <description>TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>TXOVER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:8]</bitRange>
+              <description>RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>RXUNDER</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <description>State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>RXSTALL</name>
+            </field>
+          </fields>
+          <name>FDEBUG</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x000c</addressOffset>
+          <description>FIFO levels</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:28]</bitRange>
+              <name>RX3</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[27:24]</bitRange>
+              <name>TX3</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:20]</bitRange>
+              <name>RX2</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:16]</bitRange>
+              <name>TX2</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:12]</bitRange>
+              <name>RX1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:8]</bitRange>
+              <name>TX1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:4]</bitRange>
+              <name>RX0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:0]</bitRange>
+              <name>TX0</name>
+            </field>
+          </fields>
+          <name>FLEVEL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>write-only</access>
+          <addressOffset>0x0010</addressOffset>
+          <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
+          <name>TXF0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>write-only</access>
+          <addressOffset>0x0014</addressOffset>
+          <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
+          <name>TXF1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>write-only</access>
+          <addressOffset>0x0018</addressOffset>
+          <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
+          <name>TXF2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>write-only</access>
+          <addressOffset>0x001c</addressOffset>
+          <description>Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.</description>
+          <name>TXF3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0020</addressOffset>
+          <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
+          <name>RXF0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0024</addressOffset>
+          <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
+          <name>RXF1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0028</addressOffset>
+          <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
+          <name>RXF2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x002c</addressOffset>
+          <description>Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.</description>
+          <name>RXF3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0030</addressOffset>
+          <description>State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag.\n\n
+            Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:0]</bitRange>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>IRQ</name>
+            </field>
+          </fields>
+          <name>IRQ</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0034</addressOffset>
+          <description>Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[7:0]</bitRange>
+              <name>IRQ_FORCE</name>
+            </field>
+          </fields>
+          <name>IRQ_FORCE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0038</addressOffset>
+          <description>There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.\n
+            0 -&gt; input is synchronized (default)\n
+            1 -&gt; synchronizer is bypassed\n
+            If in doubt, leave this register as all zeroes.</description>
+          <name>INPUT_SYNC_BYPASS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x003c</addressOffset>
+          <description>Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</description>
+          <name>DBG_PADOUT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0040</addressOffset>
+          <description>Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.</description>
+          <name>DBG_PADOE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0044</addressOffset>
+          <description>The PIO hardware has some free parameters that may vary between chip products.\n
+            These should be provided in the chip datasheet, but are also exposed here.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[21:16]</bitRange>
+              <description>The size of the instruction memory, measured in units of one instruction</description>
+              <name>IMEM_SIZE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:8]</bitRange>
+              <description>The number of state machines this PIO instance is equipped with.</description>
+              <name>SM_COUNT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:0]</bitRange>
+              <description>The depth of the state machine TX/RX FIFOs, measured in words.\n
+                Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\n
+                this depth.</description>
+              <name>FIFO_DEPTH</name>
+            </field>
+          </fields>
+          <name>DBG_CFGINFO</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0048</addressOffset>
+          <description>Write-only access to instruction memory location 0</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM0</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x004c</addressOffset>
+          <description>Write-only access to instruction memory location 1</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM1</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0050</addressOffset>
+          <description>Write-only access to instruction memory location 2</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM2</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0054</addressOffset>
+          <description>Write-only access to instruction memory location 3</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM3</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0058</addressOffset>
+          <description>Write-only access to instruction memory location 4</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM4</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM4</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x005c</addressOffset>
+          <description>Write-only access to instruction memory location 5</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM5</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM5</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0060</addressOffset>
+          <description>Write-only access to instruction memory location 6</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM6</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM6</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0064</addressOffset>
+          <description>Write-only access to instruction memory location 7</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM7</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM7</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0068</addressOffset>
+          <description>Write-only access to instruction memory location 8</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM8</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM8</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x006c</addressOffset>
+          <description>Write-only access to instruction memory location 9</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM9</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM9</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0070</addressOffset>
+          <description>Write-only access to instruction memory location 10</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM10</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM10</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0074</addressOffset>
+          <description>Write-only access to instruction memory location 11</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM11</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM11</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0078</addressOffset>
+          <description>Write-only access to instruction memory location 12</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM12</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM12</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x007c</addressOffset>
+          <description>Write-only access to instruction memory location 13</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM13</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM13</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0080</addressOffset>
+          <description>Write-only access to instruction memory location 14</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM14</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM14</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0084</addressOffset>
+          <description>Write-only access to instruction memory location 15</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM15</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM15</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0088</addressOffset>
+          <description>Write-only access to instruction memory location 16</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM16</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM16</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x008c</addressOffset>
+          <description>Write-only access to instruction memory location 17</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM17</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM17</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0090</addressOffset>
+          <description>Write-only access to instruction memory location 18</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM18</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM18</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0094</addressOffset>
+          <description>Write-only access to instruction memory location 19</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM19</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM19</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0098</addressOffset>
+          <description>Write-only access to instruction memory location 20</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM20</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM20</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x009c</addressOffset>
+          <description>Write-only access to instruction memory location 21</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM21</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM21</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a0</addressOffset>
+          <description>Write-only access to instruction memory location 22</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM22</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM22</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a4</addressOffset>
+          <description>Write-only access to instruction memory location 23</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM23</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM23</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00a8</addressOffset>
+          <description>Write-only access to instruction memory location 24</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM24</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM24</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00ac</addressOffset>
+          <description>Write-only access to instruction memory location 25</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM25</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM25</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b0</addressOffset>
+          <description>Write-only access to instruction memory location 26</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM26</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM26</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b4</addressOffset>
+          <description>Write-only access to instruction memory location 27</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM27</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM27</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b8</addressOffset>
+          <description>Write-only access to instruction memory location 28</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM28</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM28</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00bc</addressOffset>
+          <description>Write-only access to instruction memory location 29</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM29</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM29</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00c0</addressOffset>
+          <description>Write-only access to instruction memory location 30</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM30</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM30</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00c4</addressOffset>
+          <description>Write-only access to instruction memory location 31</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[15:0]</bitRange>
+              <name>INSTR_MEM31</name>
+            </field>
+          </fields>
+          <name>INSTR_MEM31</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00c8</addressOffset>
+          <description>Clock divisor register for state machine 0\n
+            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <description>Effective frequency is sysclk/(int + frac/256).\n
+                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:8]</bitRange>
+              <description>Fractional part of clock divisor</description>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>SM0_CLKDIV</name>
+          <resetValue>0x00010000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00cc</addressOffset>
+          <description>Execution/behavioural settings for state machine 0</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
+              <name>EXEC_STALLED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
+              <name>SIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
+              <name>SIDE_PINDIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:24]</bitRange>
+              <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
+              <name>JMP_PIN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:19]</bitRange>
+              <description>Which data bit to use for inline OUT enable</description>
+              <name>OUT_EN_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>If 1, use a bit of OUT data as an auxiliary write enable\n
+                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
+                deassert the latest pin write. This can create useful masking/override behaviour\n
+                due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
+              <name>INLINE_OUT_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Continuously assert the most recent OUT/SET to the pins</description>
+              <name>OUT_STICKY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:12]</bitRange>
+              <description>After reaching this address, execution is wrapped to wrap_bottom.\n
+                If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
+              <name>WRAP_TOP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:7]</bitRange>
+              <description>After reaching wrap_top, execution is wrapped to this address.</description>
+              <name>WRAP_BOTTOM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Comparison used for the MOV x, STATUS instruction.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
+                  <name>TXLEVEL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
+                  <name>RXLEVEL</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>STATUS_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <description>Comparison level for the MOV x, STATUS instruction</description>
+              <name>STATUS_N</name>
+            </field>
+          </fields>
+          <name>SM0_EXECCTRL</name>
+          <resetValue>0x0001f000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00d0</addressOffset>
+          <description>Control behaviour of the input/output shift registers for state machine 0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
+                TX FIFO is disabled as a result (always reads as both full and empty).\n
+                FIFOs are flushed when this bit is changed.</description>
+              <name>FJOIN_RX</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
+                RX FIFO is disabled as a result (always reads as both full and empty).\n
+                FIFOs are flushed when this bit is changed.</description>
+              <name>FJOIN_TX</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:25]</bitRange>
+              <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
+                Write 0 for value of 32.</description>
+              <name>PULL_THRESH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:20]</bitRange>
+              <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
+                Write 0 for value of 32.</description>
+              <name>PUSH_THRESH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <description>1 = shift out of output shift register to right. 0 = to left.</description>
+              <name>OUT_SHIFTDIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
+              <name>IN_SHIFTDIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
+              <name>AUTOPULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
+              <name>AUTOPUSH</name>
+            </field>
+          </fields>
+          <name>SM0_SHIFTCTRL</name>
+          <resetValue>0x000c0000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00d4</addressOffset>
+          <description>Current instruction address of state machine 0</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:0]</bitRange>
+              <name>SM0_ADDR</name>
+            </field>
+          </fields>
+          <name>SM0_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00d8</addressOffset>
+          <description>Read to see the instruction currently addressed by state machine 0's program counter\n
+            Write to execute an instruction immediately (including jumps) and then resume execution.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>SM0_INSTR</name>
+            </field>
+          </fields>
+          <name>SM0_INSTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00dc</addressOffset>
+          <description>State machine pin control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:29]</bitRange>
+              <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
+              <name>SIDESET_COUNT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:26]</bitRange>
+              <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
+              <name>SET_COUNT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:20]</bitRange>
+              <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
+              <name>OUT_COUNT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:15]</bitRange>
+              <description>The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
+              <name>IN_BASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:10]</bitRange>
+              <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
+              <name>SIDESET_BASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:5]</bitRange>
+              <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
+              <name>SET_BASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
+              <name>OUT_BASE</name>
+            </field>
+          </fields>
+          <name>SM0_PINCTRL</name>
+          <resetValue>0x14000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00e0</addressOffset>
+          <description>Clock divisor register for state machine 1\n
+            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <description>Effective frequency is sysclk/(int + frac/256).\n
+                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:8]</bitRange>
+              <description>Fractional part of clock divisor</description>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>SM1_CLKDIV</name>
+          <resetValue>0x00010000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00e4</addressOffset>
+          <description>Execution/behavioural settings for state machine 1</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
+              <name>EXEC_STALLED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
+              <name>SIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
+              <name>SIDE_PINDIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:24]</bitRange>
+              <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
+              <name>JMP_PIN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:19]</bitRange>
+              <description>Which data bit to use for inline OUT enable</description>
+              <name>OUT_EN_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>If 1, use a bit of OUT data as an auxiliary write enable\n
+                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
+                deassert the latest pin write. This can create useful masking/override behaviour\n
+                due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
+              <name>INLINE_OUT_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Continuously assert the most recent OUT/SET to the pins</description>
+              <name>OUT_STICKY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:12]</bitRange>
+              <description>After reaching this address, execution is wrapped to wrap_bottom.\n
+                If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
+              <name>WRAP_TOP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:7]</bitRange>
+              <description>After reaching wrap_top, execution is wrapped to this address.</description>
+              <name>WRAP_BOTTOM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Comparison used for the MOV x, STATUS instruction.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
+                  <name>TXLEVEL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
+                  <name>RXLEVEL</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>STATUS_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <description>Comparison level for the MOV x, STATUS instruction</description>
+              <name>STATUS_N</name>
+            </field>
+          </fields>
+          <name>SM1_EXECCTRL</name>
+          <resetValue>0x0001f000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00e8</addressOffset>
+          <description>Control behaviour of the input/output shift registers for state machine 1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
+                TX FIFO is disabled as a result (always reads as both full and empty).\n
+                FIFOs are flushed when this bit is changed.</description>
+              <name>FJOIN_RX</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
+                RX FIFO is disabled as a result (always reads as both full and empty).\n
+                FIFOs are flushed when this bit is changed.</description>
+              <name>FJOIN_TX</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:25]</bitRange>
+              <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
+                Write 0 for value of 32.</description>
+              <name>PULL_THRESH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:20]</bitRange>
+              <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
+                Write 0 for value of 32.</description>
+              <name>PUSH_THRESH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <description>1 = shift out of output shift register to right. 0 = to left.</description>
+              <name>OUT_SHIFTDIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
+              <name>IN_SHIFTDIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
+              <name>AUTOPULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
+              <name>AUTOPUSH</name>
+            </field>
+          </fields>
+          <name>SM1_SHIFTCTRL</name>
+          <resetValue>0x000c0000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00ec</addressOffset>
+          <description>Current instruction address of state machine 1</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:0]</bitRange>
+              <name>SM1_ADDR</name>
+            </field>
+          </fields>
+          <name>SM1_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f0</addressOffset>
+          <description>Read to see the instruction currently addressed by state machine 1's program counter\n
+            Write to execute an instruction immediately (including jumps) and then resume execution.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>SM1_INSTR</name>
+            </field>
+          </fields>
+          <name>SM1_INSTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f4</addressOffset>
+          <description>State machine pin control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:29]</bitRange>
+              <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
+              <name>SIDESET_COUNT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:26]</bitRange>
+              <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
+              <name>SET_COUNT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:20]</bitRange>
+              <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
+              <name>OUT_COUNT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:15]</bitRange>
+              <description>The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
+              <name>IN_BASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:10]</bitRange>
+              <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
+              <name>SIDESET_BASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:5]</bitRange>
+              <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
+              <name>SET_BASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
+              <name>OUT_BASE</name>
+            </field>
+          </fields>
+          <name>SM1_PINCTRL</name>
+          <resetValue>0x14000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f8</addressOffset>
+          <description>Clock divisor register for state machine 2\n
+            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <description>Effective frequency is sysclk/(int + frac/256).\n
+                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:8]</bitRange>
+              <description>Fractional part of clock divisor</description>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>SM2_CLKDIV</name>
+          <resetValue>0x00010000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00fc</addressOffset>
+          <description>Execution/behavioural settings for state machine 2</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
+              <name>EXEC_STALLED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
+              <name>SIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
+              <name>SIDE_PINDIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:24]</bitRange>
+              <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
+              <name>JMP_PIN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:19]</bitRange>
+              <description>Which data bit to use for inline OUT enable</description>
+              <name>OUT_EN_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>If 1, use a bit of OUT data as an auxiliary write enable\n
+                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
+                deassert the latest pin write. This can create useful masking/override behaviour\n
+                due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
+              <name>INLINE_OUT_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Continuously assert the most recent OUT/SET to the pins</description>
+              <name>OUT_STICKY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:12]</bitRange>
+              <description>After reaching this address, execution is wrapped to wrap_bottom.\n
+                If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
+              <name>WRAP_TOP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:7]</bitRange>
+              <description>After reaching wrap_top, execution is wrapped to this address.</description>
+              <name>WRAP_BOTTOM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Comparison used for the MOV x, STATUS instruction.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
+                  <name>TXLEVEL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
+                  <name>RXLEVEL</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>STATUS_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <description>Comparison level for the MOV x, STATUS instruction</description>
+              <name>STATUS_N</name>
+            </field>
+          </fields>
+          <name>SM2_EXECCTRL</name>
+          <resetValue>0x0001f000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0100</addressOffset>
+          <description>Control behaviour of the input/output shift registers for state machine 2</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
+                TX FIFO is disabled as a result (always reads as both full and empty).\n
+                FIFOs are flushed when this bit is changed.</description>
+              <name>FJOIN_RX</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
+                RX FIFO is disabled as a result (always reads as both full and empty).\n
+                FIFOs are flushed when this bit is changed.</description>
+              <name>FJOIN_TX</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:25]</bitRange>
+              <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
+                Write 0 for value of 32.</description>
+              <name>PULL_THRESH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:20]</bitRange>
+              <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
+                Write 0 for value of 32.</description>
+              <name>PUSH_THRESH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <description>1 = shift out of output shift register to right. 0 = to left.</description>
+              <name>OUT_SHIFTDIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
+              <name>IN_SHIFTDIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
+              <name>AUTOPULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
+              <name>AUTOPUSH</name>
+            </field>
+          </fields>
+          <name>SM2_SHIFTCTRL</name>
+          <resetValue>0x000c0000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0104</addressOffset>
+          <description>Current instruction address of state machine 2</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:0]</bitRange>
+              <name>SM2_ADDR</name>
+            </field>
+          </fields>
+          <name>SM2_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0108</addressOffset>
+          <description>Read to see the instruction currently addressed by state machine 2's program counter\n
+            Write to execute an instruction immediately (including jumps) and then resume execution.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>SM2_INSTR</name>
+            </field>
+          </fields>
+          <name>SM2_INSTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x010c</addressOffset>
+          <description>State machine pin control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:29]</bitRange>
+              <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
+              <name>SIDESET_COUNT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:26]</bitRange>
+              <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
+              <name>SET_COUNT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:20]</bitRange>
+              <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
+              <name>OUT_COUNT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:15]</bitRange>
+              <description>The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
+              <name>IN_BASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:10]</bitRange>
+              <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
+              <name>SIDESET_BASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:5]</bitRange>
+              <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
+              <name>SET_BASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
+              <name>OUT_BASE</name>
+            </field>
+          </fields>
+          <name>SM2_PINCTRL</name>
+          <resetValue>0x14000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0110</addressOffset>
+          <description>Clock divisor register for state machine 3\n
+            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <description>Effective frequency is sysclk/(int + frac/256).\n
+                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.</description>
+              <name>INT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:8]</bitRange>
+              <description>Fractional part of clock divisor</description>
+              <name>FRAC</name>
+            </field>
+          </fields>
+          <name>SM3_CLKDIV</name>
+          <resetValue>0x00010000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0114</addressOffset>
+          <description>Execution/behavioural settings for state machine 3</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.</description>
+              <name>EXEC_STALLED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.</description>
+              <name>SIDE_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:29]</bitRange>
+              <description>If 1, side-set data is asserted to pin directions, instead of pin values</description>
+              <name>SIDE_PINDIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:24]</bitRange>
+              <description>The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.</description>
+              <name>JMP_PIN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:19]</bitRange>
+              <description>Which data bit to use for inline OUT enable</description>
+              <name>OUT_EN_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>If 1, use a bit of OUT data as an auxiliary write enable\n
+                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
+                deassert the latest pin write. This can create useful masking/override behaviour\n
+                due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)</description>
+              <name>INLINE_OUT_EN</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Continuously assert the most recent OUT/SET to the pins</description>
+              <name>OUT_STICKY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:12]</bitRange>
+              <description>After reaching this address, execution is wrapped to wrap_bottom.\n
+                If the instruction is a jump, and the jump condition is true, the jump takes priority.</description>
+              <name>WRAP_TOP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:7]</bitRange>
+              <description>After reaching wrap_top, execution is wrapped to this address.</description>
+              <name>WRAP_BOTTOM</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Comparison used for the MOV x, STATUS instruction.</description>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <description>All-ones if TX FIFO level &lt; N, otherwise all-zeroes</description>
+                  <name>TXLEVEL</name>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <description>All-ones if RX FIFO level &lt; N, otherwise all-zeroes</description>
+                  <name>RXLEVEL</name>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+              <name>STATUS_SEL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <description>Comparison level for the MOV x, STATUS instruction</description>
+              <name>STATUS_N</name>
+            </field>
+          </fields>
+          <name>SM3_EXECCTRL</name>
+          <resetValue>0x0001f000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0118</addressOffset>
+          <description>Control behaviour of the input/output shift registers for state machine 3</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
+                TX FIFO is disabled as a result (always reads as both full and empty).\n
+                FIFOs are flushed when this bit is changed.</description>
+              <name>FJOIN_RX</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[30:30]</bitRange>
+              <description>When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
+                RX FIFO is disabled as a result (always reads as both full and empty).\n
+                FIFOs are flushed when this bit is changed.</description>
+              <name>FJOIN_TX</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:25]</bitRange>
+              <description>Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n
+                Write 0 for value of 32.</description>
+              <name>PULL_THRESH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[24:20]</bitRange>
+              <description>Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n
+                Write 0 for value of 32.</description>
+              <name>PUSH_THRESH</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:19]</bitRange>
+              <description>1 = shift out of output shift register to right. 0 = to left.</description>
+              <name>OUT_SHIFTDIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>1 = shift input shift register to right (data enters from left). 0 = to left.</description>
+              <name>IN_SHIFTDIR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.</description>
+              <name>AUTOPULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.</description>
+              <name>AUTOPUSH</name>
+            </field>
+          </fields>
+          <name>SM3_SHIFTCTRL</name>
+          <resetValue>0x000c0000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x011c</addressOffset>
+          <description>Current instruction address of state machine 3</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:0]</bitRange>
+              <name>SM3_ADDR</name>
+            </field>
+          </fields>
+          <name>SM3_ADDR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0120</addressOffset>
+          <description>Read to see the instruction currently addressed by state machine 3's program counter\n
+            Write to execute an instruction immediately (including jumps) and then resume execution.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:0]</bitRange>
+              <name>SM3_INSTR</name>
+            </field>
+          </fields>
+          <name>SM3_INSTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0124</addressOffset>
+          <description>State machine pin control</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:29]</bitRange>
+              <description>The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).</description>
+              <name>SIDESET_COUNT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:26]</bitRange>
+              <description>The number of pins asserted by a SET. In the range 0 to 5 inclusive.</description>
+              <name>SET_COUNT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:20]</bitRange>
+              <description>The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.</description>
+              <name>OUT_COUNT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[19:15]</bitRange>
+              <description>The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.</description>
+              <name>IN_BASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:10]</bitRange>
+              <description>The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.</description>
+              <name>SIDESET_BASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:5]</bitRange>
+              <description>The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.</description>
+              <name>SET_BASE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.</description>
+              <name>OUT_BASE</name>
+            </field>
+          </fields>
+          <name>SM3_PINCTRL</name>
+          <resetValue>0x14000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0128</addressOffset>
+          <description>Raw Interrupts</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>SM3</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>SM2</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>SM1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>SM0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>SM3_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>SM2_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>SM1_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>SM0_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>SM3_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>SM2_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>SM1_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>SM0_RXNEMPTY</name>
+            </field>
+          </fields>
+          <name>INTR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x012c</addressOffset>
+          <description>Interrupt Enable for irq0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>SM3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>SM2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>SM1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>SM0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>SM3_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>SM2_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>SM1_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>SM0_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>SM3_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>SM2_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>SM1_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>SM0_RXNEMPTY</name>
+            </field>
+          </fields>
+          <name>IRQ0_INTE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0130</addressOffset>
+          <description>Interrupt Force for irq0</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>SM3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>SM2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>SM1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>SM0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>SM3_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>SM2_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>SM1_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>SM0_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>SM3_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>SM2_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>SM1_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>SM0_RXNEMPTY</name>
+            </field>
+          </fields>
+          <name>IRQ0_INTF</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0134</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for irq0</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>SM3</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>SM2</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>SM1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>SM0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>SM3_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>SM2_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>SM1_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>SM0_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>SM3_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>SM2_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>SM1_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>SM0_RXNEMPTY</name>
+            </field>
+          </fields>
+          <name>IRQ0_INTS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0138</addressOffset>
+          <description>Interrupt Enable for irq1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>SM3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>SM2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>SM1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>SM0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>SM3_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>SM2_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>SM1_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>SM0_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>SM3_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>SM2_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>SM1_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>SM0_RXNEMPTY</name>
+            </field>
+          </fields>
+          <name>IRQ1_INTE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x013c</addressOffset>
+          <description>Interrupt Force for irq1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[11:11]</bitRange>
+              <name>SM3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[10:10]</bitRange>
+              <name>SM2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:9]</bitRange>
+              <name>SM1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[8:8]</bitRange>
+              <name>SM0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:7]</bitRange>
+              <name>SM3_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[6:6]</bitRange>
+              <name>SM2_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:5]</bitRange>
+              <name>SM1_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <name>SM0_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <name>SM3_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <name>SM2_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <name>SM1_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <name>SM0_RXNEMPTY</name>
+            </field>
+          </fields>
+          <name>IRQ1_INTF</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0140</addressOffset>
+          <description>Interrupt status after masking &amp; forcing for irq1</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[11:11]</bitRange>
+              <name>SM3</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[10:10]</bitRange>
+              <name>SM2</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <name>SM1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:8]</bitRange>
+              <name>SM0</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[7:7]</bitRange>
+              <name>SM3_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[6:6]</bitRange>
+              <name>SM2_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:5]</bitRange>
+              <name>SM1_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[4:4]</bitRange>
+              <name>SM0_TXNFULL</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <name>SM3_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[2:2]</bitRange>
+              <name>SM2_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <name>SM1_RXNEMPTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <name>SM0_RXNEMPTY</name>
+            </field>
+          </fields>
+          <name>IRQ1_INTS</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral derivedFrom="PIO0">
+      <baseAddress>0x50300000</baseAddress>
+      <interrupt>
+        <name>PIO1_IRQ_0</name>
+        <value>9</value>
+      </interrupt>
+      <interrupt>
+        <name>PIO1_IRQ_1</name>
+        <value>10</value>
+      </interrupt>
+      <name>PIO1</name>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x0200</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0xd0000000</baseAddress>
+      <description>Single-cycle IO block\n
+        Provides core-local and inter-core hardware for the two processors, with single-cycle access.</description>
+      <interrupt>
+        <name>SIO_IRQ_PROC0</name>
+        <value>15</value>
+      </interrupt>
+      <interrupt>
+        <name>SIO_IRQ_PROC1</name>
+        <value>16</value>
+      </interrupt>
+      <name>SIO</name>
+      <registers>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0000</addressOffset>
+          <description>Processor core identifier\n
+            Value is 0 when read from processor core 0, and 1 when read from processor core 1.</description>
+          <name>CPUID</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0004</addressOffset>
+          <description>Input value for GPIO pins</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[29:0]</bitRange>
+              <description>Input value for GPIO0...29</description>
+              <name>GPIO_IN</name>
+            </field>
+          </fields>
+          <name>GPIO_IN</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0008</addressOffset>
+          <description>Input value for QSPI pins</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[5:0]</bitRange>
+              <description>Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3</description>
+              <name>GPIO_HI_IN</name>
+            </field>
+          </fields>
+          <name>GPIO_HI_IN</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0010</addressOffset>
+          <description>GPIO output value</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:0]</bitRange>
+              <description>Set output level (1/0 -&gt; high/low) for GPIO0...29.\n
+                Reading back gives the last value written, NOT the input value from the pins.\n
+                If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),\n
+                the result is as though the write from core 0 took place first,\n
+                and the write from core 1 was then applied to that intermediate result.</description>
+              <name>GPIO_OUT</name>
+            </field>
+          </fields>
+          <name>GPIO_OUT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0014</addressOffset>
+          <description>GPIO output value set</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[29:0]</bitRange>
+              <description>Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`</description>
+              <name>GPIO_OUT_SET</name>
+            </field>
+          </fields>
+          <name>GPIO_OUT_SET</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0018</addressOffset>
+          <description>GPIO output value clear</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[29:0]</bitRange>
+              <description>Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &amp;= ~wdata`</description>
+              <name>GPIO_OUT_CLR</name>
+            </field>
+          </fields>
+          <name>GPIO_OUT_CLR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x001c</addressOffset>
+          <description>GPIO output value XOR</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[29:0]</bitRange>
+              <description>Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`</description>
+              <name>GPIO_OUT_XOR</name>
+            </field>
+          </fields>
+          <name>GPIO_OUT_XOR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0020</addressOffset>
+          <description>GPIO output enable</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[29:0]</bitRange>
+              <description>Set output enable (1/0 -&gt; output/input) for GPIO0...29.\n
+                Reading back gives the last value written.\n
+                If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),\n
+                the result is as though the write from core 0 took place first,\n
+                and the write from core 1 was then applied to that intermediate result.</description>
+              <name>GPIO_OE</name>
+            </field>
+          </fields>
+          <name>GPIO_OE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0024</addressOffset>
+          <description>GPIO output enable set</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[29:0]</bitRange>
+              <description>Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`</description>
+              <name>GPIO_OE_SET</name>
+            </field>
+          </fields>
+          <name>GPIO_OE_SET</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0028</addressOffset>
+          <description>GPIO output enable clear</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[29:0]</bitRange>
+              <description>Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &amp;= ~wdata`</description>
+              <name>GPIO_OE_CLR</name>
+            </field>
+          </fields>
+          <name>GPIO_OE_CLR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x002c</addressOffset>
+          <description>GPIO output enable XOR</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[29:0]</bitRange>
+              <description>Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`</description>
+              <name>GPIO_OE_XOR</name>
+            </field>
+          </fields>
+          <name>GPIO_OE_XOR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0030</addressOffset>
+          <description>QSPI output value</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <description>Set output level (1/0 -&gt; high/low) for QSPI IO0...5.\n
+                Reading back gives the last value written, NOT the input value from the pins.\n
+                If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),\n
+                the result is as though the write from core 0 took place first,\n
+                and the write from core 1 was then applied to that intermediate result.</description>
+              <name>GPIO_HI_OUT</name>
+            </field>
+          </fields>
+          <name>GPIO_HI_OUT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0034</addressOffset>
+          <description>QSPI output value set</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[5:0]</bitRange>
+              <description>Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`</description>
+              <name>GPIO_HI_OUT_SET</name>
+            </field>
+          </fields>
+          <name>GPIO_HI_OUT_SET</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0038</addressOffset>
+          <description>QSPI output value clear</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[5:0]</bitRange>
+              <description>Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &amp;= ~wdata`</description>
+              <name>GPIO_HI_OUT_CLR</name>
+            </field>
+          </fields>
+          <name>GPIO_HI_OUT_CLR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x003c</addressOffset>
+          <description>QSPI output value XOR</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[5:0]</bitRange>
+              <description>Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`</description>
+              <name>GPIO_HI_OUT_XOR</name>
+            </field>
+          </fields>
+          <name>GPIO_HI_OUT_XOR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0040</addressOffset>
+          <description>QSPI output enable</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:0]</bitRange>
+              <description>Set output enable (1/0 -&gt; output/input) for QSPI IO0...5.\n
+                Reading back gives the last value written.\n
+                If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),\n
+                the result is as though the write from core 0 took place first,\n
+                and the write from core 1 was then applied to that intermediate result.</description>
+              <name>GPIO_HI_OE</name>
+            </field>
+          </fields>
+          <name>GPIO_HI_OE</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0044</addressOffset>
+          <description>QSPI output enable set</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[5:0]</bitRange>
+              <description>Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`</description>
+              <name>GPIO_HI_OE_SET</name>
+            </field>
+          </fields>
+          <name>GPIO_HI_OE_SET</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0048</addressOffset>
+          <description>QSPI output enable clear</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[5:0]</bitRange>
+              <description>Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &amp;= ~wdata`</description>
+              <name>GPIO_HI_OE_CLR</name>
+            </field>
+          </fields>
+          <name>GPIO_HI_OE_CLR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x004c</addressOffset>
+          <description>QSPI output enable XOR</description>
+          <fields>
+            <field>
+              <access>write-only</access>
+              <bitRange>[5:0]</bitRange>
+              <description>Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`</description>
+              <name>GPIO_HI_OE_XOR</name>
+            </field>
+          </fields>
+          <name>GPIO_HI_OE_XOR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0050</addressOffset>
+          <description>Status register for inter-core FIFOs (mailboxes).\n
+            There is one FIFO in the core 0 -&gt; core 1 direction, and one core 1 -&gt; core 0. Both are 32 bits wide and 8 words deep.\n
+            Core 0 can see the read side of the 1-&gt;0 FIFO (RX), and the write side of 0-&gt;1 FIFO (TX).\n
+            Core 1 can see the read side of the 0-&gt;1 FIFO (RX), and the write side of 1-&gt;0 FIFO (TX).\n
+            The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>ROE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.</description>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+              <name>WOF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)</description>
+              <name>RDY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)</description>
+              <name>VLD</name>
+            </field>
+          </fields>
+          <name>FIFO_ST</name>
+          <resetValue>0x00000002</resetValue>
+        </register>
+        <register>
+          <access>write-only</access>
+          <addressOffset>0x0054</addressOffset>
+          <description>Write access to this core's TX FIFO</description>
+          <name>FIFO_WR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0058</addressOffset>
+          <description>Read access to this core's RX FIFO</description>
+          <name>FIFO_RD</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x005c</addressOffset>
+          <description>Spinlock state\n
+            A bitmap containing the state of all 32 spinlocks (1=locked).\n
+            Mainly intended for debugging.</description>
+          <name>SPINLOCK_ST</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0060</addressOffset>
+          <description>Divider unsigned dividend\n
+            Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.\n
+            Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n
+            UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n
+            unsigned calculation, and the S alias starts a signed calculation.</description>
+          <name>DIV_UDIVIDEND</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0064</addressOffset>
+          <description>Divider unsigned divisor\n
+            Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.\n
+            Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n
+            UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n
+            unsigned calculation, and the S alias starts a signed calculation.</description>
+          <name>DIV_UDIVISOR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0068</addressOffset>
+          <description>Divider signed dividend\n
+            The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.</description>
+          <name>DIV_SDIVIDEND</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x006c</addressOffset>
+          <description>Divider signed divisor\n
+            The same as UDIVISOR, but starts a signed calculation, rather than unsigned.</description>
+          <name>DIV_SDIVISOR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0070</addressOffset>
+          <description>Divider result quotient\n
+            The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.\n
+            For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.\n
+            This register can be written to directly, for context save/restore purposes. This halts any\n
+            in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.\n
+            Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order\n
+            REMAINDER, QUOTIENT if CSR_DIRTY is used.</description>
+          <name>DIV_QUOTIENT</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0074</addressOffset>
+          <description>Divider result remainder\n
+            The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.\n
+            For signed calculations, REMAINDER is negative only when DIVIDEND is negative.\n
+            This register can be written to directly, for context save/restore purposes. This halts any\n
+            in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.</description>
+          <name>DIV_REMAINDER</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x0078</addressOffset>
+          <description>Control and status register for divider.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.\n
+                Software can use this flag to make save/restore more efficient (skip if not DIRTY).\n
+                If the flag is used in this way, it's recommended to either read QUOTIENT only,\n
+                or REMAINDER and then QUOTIENT, to prevent data loss on context switch.</description>
+              <name>DIRTY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Reads as 0 when a calculation is in progress, 1 otherwise.\n
+                Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no\n
+                matter if one is already in progress.\n
+                Writing to a result register will immediately terminate any in-progress calculation\n
+                and set the READY and DIRTY flags.</description>
+              <name>READY</name>
+            </field>
+          </fields>
+          <name>DIV_CSR</name>
+          <resetValue>0x00000001</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0080</addressOffset>
+          <description>Read/write access to accumulator 0</description>
+          <name>INTERP0_ACCUM0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0084</addressOffset>
+          <description>Read/write access to accumulator 1</description>
+          <name>INTERP0_ACCUM1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0088</addressOffset>
+          <description>Read/write access to BASE0 register.</description>
+          <name>INTERP0_BASE0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x008c</addressOffset>
+          <description>Read/write access to BASE1 register.</description>
+          <name>INTERP0_BASE1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0090</addressOffset>
+          <description>Read/write access to BASE2 register.</description>
+          <name>INTERP0_BASE2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0094</addressOffset>
+          <description>Read LANE0 result, and simultaneously write lane results to both accumulators (POP).</description>
+          <name>INTERP0_POP_LANE0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x0098</addressOffset>
+          <description>Read LANE1 result, and simultaneously write lane results to both accumulators (POP).</description>
+          <name>INTERP0_POP_LANE1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x009c</addressOffset>
+          <description>Read FULL result, and simultaneously write lane results to both accumulators (POP).</description>
+          <name>INTERP0_POP_FULL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x00a0</addressOffset>
+          <description>Read LANE0 result, without altering any internal state (PEEK).</description>
+          <name>INTERP0_PEEK_LANE0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x00a4</addressOffset>
+          <description>Read LANE1 result, without altering any internal state (PEEK).</description>
+          <name>INTERP0_PEEK_LANE1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x00a8</addressOffset>
+          <description>Read FULL result, without altering any internal state (PEEK).</description>
+          <name>INTERP0_PEEK_FULL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00ac</addressOffset>
+          <description>Control register for lane 0</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Set if either OVERF0 or OVERF1 is set.</description>
+              <name>OVERF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>Indicates if any masked-off MSBs in ACCUM1 are set.</description>
+              <name>OVERF1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <description>Indicates if any masked-off MSBs in ACCUM0 are set.</description>
+              <name>OVERF0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[21:21]</bitRange>
+              <description>Only present on INTERP0 on each core. If BLEND mode is enabled:\n
+                - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled\n
+                by the 8 LSBs of lane 1 shift and mask value (a fractional number between\n
+                0 and 255/256ths)\n
+                - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)\n
+                - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)\n
+                LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.</description>
+              <name>BLEND</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:19]</bitRange>
+              <description>ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
+                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n
+                of pointers into flash or SRAM.</description>
+              <name>FORCE_MSB</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.</description>
+              <name>ADD_RAW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>If 1, feed the opposite lane's result into this lane's accumulator on POP.</description>
+              <name>CROSS_RESULT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
+                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
+              <name>CROSS_INPUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
+                before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.</description>
+              <name>SIGNED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:10]</bitRange>
+              <description>The most-significant bit allowed to pass by the mask (inclusive)\n
+                Setting MSB &lt; LSB may cause chip to turn inside-out</description>
+              <name>MASK_MSB</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:5]</bitRange>
+              <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
+              <name>MASK_LSB</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>Logical right-shift applied to accumulator before masking</description>
+              <name>SHIFT</name>
+            </field>
+          </fields>
+          <name>INTERP0_CTRL_LANE0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b0</addressOffset>
+          <description>Control register for lane 1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:19]</bitRange>
+              <description>ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
+                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n
+                of pointers into flash or SRAM.</description>
+              <name>FORCE_MSB</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.</description>
+              <name>ADD_RAW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>If 1, feed the opposite lane's result into this lane's accumulator on POP.</description>
+              <name>CROSS_RESULT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
+                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
+              <name>CROSS_INPUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
+                before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.</description>
+              <name>SIGNED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:10]</bitRange>
+              <description>The most-significant bit allowed to pass by the mask (inclusive)\n
+                Setting MSB &lt; LSB may cause chip to turn inside-out</description>
+              <name>MASK_MSB</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:5]</bitRange>
+              <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
+              <name>MASK_LSB</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>Logical right-shift applied to accumulator before masking</description>
+              <name>SHIFT</name>
+            </field>
+          </fields>
+          <name>INTERP0_CTRL_LANE1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b4</addressOffset>
+          <description>Values written here are atomically added to ACCUM0\n
+            Reading yields lane 0's raw shift and mask value (BASE0 not added).</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:0]</bitRange>
+              <name>INTERP0_ACCUM0_ADD</name>
+            </field>
+          </fields>
+          <name>INTERP0_ACCUM0_ADD</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00b8</addressOffset>
+          <description>Values written here are atomically added to ACCUM1\n
+            Reading yields lane 1's raw shift and mask value (BASE1 not added).</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:0]</bitRange>
+              <name>INTERP0_ACCUM1_ADD</name>
+            </field>
+          </fields>
+          <name>INTERP0_ACCUM1_ADD</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>write-only</access>
+          <addressOffset>0x00bc</addressOffset>
+          <description>On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n
+            Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.</description>
+          <name>INTERP0_BASE_1AND0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00c0</addressOffset>
+          <description>Read/write access to accumulator 0</description>
+          <name>INTERP1_ACCUM0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00c4</addressOffset>
+          <description>Read/write access to accumulator 1</description>
+          <name>INTERP1_ACCUM1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00c8</addressOffset>
+          <description>Read/write access to BASE0 register.</description>
+          <name>INTERP1_BASE0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00cc</addressOffset>
+          <description>Read/write access to BASE1 register.</description>
+          <name>INTERP1_BASE1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x00d0</addressOffset>
+          <description>Read/write access to BASE2 register.</description>
+          <name>INTERP1_BASE2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x00d4</addressOffset>
+          <description>Read LANE0 result, and simultaneously write lane results to both accumulators (POP).</description>
+          <name>INTERP1_POP_LANE0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x00d8</addressOffset>
+          <description>Read LANE1 result, and simultaneously write lane results to both accumulators (POP).</description>
+          <name>INTERP1_POP_LANE1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x00dc</addressOffset>
+          <description>Read FULL result, and simultaneously write lane results to both accumulators (POP).</description>
+          <name>INTERP1_POP_FULL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x00e0</addressOffset>
+          <description>Read LANE0 result, without altering any internal state (PEEK).</description>
+          <name>INTERP1_PEEK_LANE0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x00e4</addressOffset>
+          <description>Read LANE1 result, without altering any internal state (PEEK).</description>
+          <name>INTERP1_PEEK_LANE1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-only</access>
+          <addressOffset>0x00e8</addressOffset>
+          <description>Read FULL result, without altering any internal state (PEEK).</description>
+          <name>INTERP1_PEEK_FULL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00ec</addressOffset>
+          <description>Control register for lane 0</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[25:25]</bitRange>
+              <description>Set if either OVERF0 or OVERF1 is set.</description>
+              <name>OVERF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[24:24]</bitRange>
+              <description>Indicates if any masked-off MSBs in ACCUM1 are set.</description>
+              <name>OVERF1</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <description>Indicates if any masked-off MSBs in ACCUM0 are set.</description>
+              <name>OVERF0</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[22:22]</bitRange>
+              <description>Only present on INTERP1 on each core. If CLAMP mode is enabled:\n
+                - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of\n
+                BASE0 and an upper bound of BASE1.\n
+                - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED</description>
+              <name>CLAMP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:19]</bitRange>
+              <description>ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
+                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n
+                of pointers into flash or SRAM.</description>
+              <name>FORCE_MSB</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.</description>
+              <name>ADD_RAW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>If 1, feed the opposite lane's result into this lane's accumulator on POP.</description>
+              <name>CROSS_RESULT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
+                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
+              <name>CROSS_INPUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
+                before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.</description>
+              <name>SIGNED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:10]</bitRange>
+              <description>The most-significant bit allowed to pass by the mask (inclusive)\n
+                Setting MSB &lt; LSB may cause chip to turn inside-out</description>
+              <name>MASK_MSB</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:5]</bitRange>
+              <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
+              <name>MASK_LSB</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>Logical right-shift applied to accumulator before masking</description>
+              <name>SHIFT</name>
+            </field>
+          </fields>
+          <name>INTERP1_CTRL_LANE0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f0</addressOffset>
+          <description>Control register for lane 1</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[20:19]</bitRange>
+              <description>ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
+                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n
+                of pointers into flash or SRAM.</description>
+              <name>FORCE_MSB</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[18:18]</bitRange>
+              <description>If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.</description>
+              <name>ADD_RAW</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[17:17]</bitRange>
+              <description>If 1, feed the opposite lane's result into this lane's accumulator on POP.</description>
+              <name>CROSS_RESULT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[16:16]</bitRange>
+              <description>If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n
+                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)</description>
+              <name>CROSS_INPUT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n
+                before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.</description>
+              <name>SIGNED</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[14:10]</bitRange>
+              <description>The most-significant bit allowed to pass by the mask (inclusive)\n
+                Setting MSB &lt; LSB may cause chip to turn inside-out</description>
+              <name>MASK_MSB</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[9:5]</bitRange>
+              <description>The least-significant bit allowed to pass by the mask (inclusive)</description>
+              <name>MASK_LSB</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:0]</bitRange>
+              <description>Logical right-shift applied to accumulator before masking</description>
+              <name>SHIFT</name>
+            </field>
+          </fields>
+          <name>INTERP1_CTRL_LANE1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f4</addressOffset>
+          <description>Values written here are atomically added to ACCUM0\n
+            Reading yields lane 0's raw shift and mask value (BASE0 not added).</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:0]</bitRange>
+              <name>INTERP1_ACCUM0_ADD</name>
+            </field>
+          </fields>
+          <name>INTERP1_ACCUM0_ADD</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0x00f8</addressOffset>
+          <description>Values written here are atomically added to ACCUM1\n
+            Reading yields lane 1's raw shift and mask value (BASE1 not added).</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:0]</bitRange>
+              <name>INTERP1_ACCUM1_ADD</name>
+            </field>
+          </fields>
+          <name>INTERP1_ACCUM1_ADD</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>write-only</access>
+          <addressOffset>0x00fc</addressOffset>
+          <description>On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n
+            Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.</description>
+          <name>INTERP1_BASE_1AND0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0100</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0104</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0108</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x010c</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0110</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK4</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0114</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK5</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0118</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK6</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x011c</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK7</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0120</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK8</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0124</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK9</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0128</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK10</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x012c</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK11</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0130</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK12</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0134</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK13</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0138</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK14</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x013c</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK15</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0140</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK16</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0144</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK17</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0148</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK18</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x014c</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK19</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0150</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK20</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0154</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK21</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0158</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK22</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x015c</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK23</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0160</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK24</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0164</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK25</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0168</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK26</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x016c</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK27</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0170</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK28</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0174</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK29</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x0178</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK30</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <access>read-write</access>
+          <addressOffset>0x017c</addressOffset>
+          <description>Reading from a spinlock address will:\n
+            - Return 0 if lock is already locked\n
+            - Otherwise return nonzero, and simultaneously claim the lock\n\n
+            Writing (any value) releases the lock.\n
+            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n
+            The value returned on success is 0x1 &lt;&lt; lock number.</description>
+          <name>SPINLOCK31</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+    <peripheral>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x10000</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <baseAddress>0xe0000000</baseAddress>
+      <name>PPB</name>
+      <registers>
+        <register>
+          <addressOffset>0xe010</addressOffset>
+          <description>Use the SysTick Control and Status Register to enable the SysTick features.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[16:16]</bitRange>
+              <description>Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger.</description>
+              <name>COUNTFLAG</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\n
+                Selects the SysTick timer clock source:\n
+                0 = External reference clock.\n
+                1 = Processor clock.</description>
+              <name>CLKSOURCE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Enables SysTick exception request:\n
+                0 = Counting down to zero does not assert the SysTick exception request.\n
+                1 = Counting down to zero to asserts the SysTick exception request.</description>
+              <name>TICKINT</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enable SysTick counter:\n
+                0 = Counter disabled.\n
+                1 = Counter enabled.</description>
+              <name>ENABLE</name>
+            </field>
+          </fields>
+          <name>SYST_CSR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe014</addressOffset>
+          <description>Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.\n
+            To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:0]</bitRange>
+              <description>Value to load into the SysTick Current Value Register when the counter reaches 0.</description>
+              <name>RELOAD</name>
+            </field>
+          </fields>
+          <name>SYST_RVR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe018</addressOffset>
+          <description>Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:0]</bitRange>
+              <description>Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.</description>
+              <name>CURRENT</name>
+            </field>
+          </fields>
+          <name>SYST_CVR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe01c</addressOffset>
+          <description>Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:31]</bitRange>
+              <description>If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0.</description>
+              <name>NOREF</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[30:30]</bitRange>
+              <description>If reads as 1, the calibration value for 10ms is inexact (due to clock frequency).</description>
+              <name>SKEW</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:0]</bitRange>
+              <description>An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known.</description>
+              <name>TENMS</name>
+            </field>
+          </fields>
+          <name>SYST_CALIB</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe100</addressOffset>
+          <description>Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.\n
+            If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:0]</bitRange>
+              <description>Interrupt set-enable bits.\n
+                Write:\n
+                0 = No effect.\n
+                1 = Enable interrupt.\n
+                Read:\n
+                0 = Interrupt disabled.\n
+                1 = Interrupt enabled.</description>
+              <name>SETENA</name>
+            </field>
+          </fields>
+          <name>NVIC_ISER</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe180</addressOffset>
+          <description>Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:0]</bitRange>
+              <description>Interrupt clear-enable bits.\n
+                Write:\n
+                0 = No effect.\n
+                1 = Disable interrupt.\n
+                Read:\n
+                0 = Interrupt disabled.\n
+                1 = Interrupt enabled.</description>
+              <name>CLRENA</name>
+            </field>
+          </fields>
+          <name>NVIC_ICER</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe200</addressOffset>
+          <description>The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:0]</bitRange>
+              <description>Interrupt set-pending bits.\n
+                Write:\n
+                0 = No effect.\n
+                1 = Changes interrupt state to pending.\n
+                Read:\n
+                0 = Interrupt is not pending.\n
+                1 = Interrupt is pending.\n
+                Note: Writing 1 to the NVIC_ISPR bit corresponding to:\n
+                An interrupt that is pending has no effect.\n
+                A disabled interrupt sets the state of that interrupt to pending.</description>
+              <name>SETPEND</name>
+            </field>
+          </fields>
+          <name>NVIC_ISPR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe280</addressOffset>
+          <description>Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:0]</bitRange>
+              <description>Interrupt clear-pending bits.\n
+                Write:\n
+                0 = No effect.\n
+                1 = Removes pending state and interrupt.\n
+                Read:\n
+                0 = Interrupt is not pending.\n
+                1 = Interrupt is pending.</description>
+              <name>CLRPEND</name>
+            </field>
+          </fields>
+          <name>NVIC_ICPR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe400</addressOffset>
+          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.\n
+            Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.\n
+            These registers are only word-accessible</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:30]</bitRange>
+              <description>Priority of interrupt 3</description>
+              <name>IP_3</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:22]</bitRange>
+              <description>Priority of interrupt 2</description>
+              <name>IP_2</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:14]</bitRange>
+              <description>Priority of interrupt 1</description>
+              <name>IP_1</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:6]</bitRange>
+              <description>Priority of interrupt 0</description>
+              <name>IP_0</name>
+            </field>
+          </fields>
+          <name>NVIC_IPR0</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe404</addressOffset>
+          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:30]</bitRange>
+              <description>Priority of interrupt 7</description>
+              <name>IP_7</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:22]</bitRange>
+              <description>Priority of interrupt 6</description>
+              <name>IP_6</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:14]</bitRange>
+              <description>Priority of interrupt 5</description>
+              <name>IP_5</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:6]</bitRange>
+              <description>Priority of interrupt 4</description>
+              <name>IP_4</name>
+            </field>
+          </fields>
+          <name>NVIC_IPR1</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe408</addressOffset>
+          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:30]</bitRange>
+              <description>Priority of interrupt 11</description>
+              <name>IP_11</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:22]</bitRange>
+              <description>Priority of interrupt 10</description>
+              <name>IP_10</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:14]</bitRange>
+              <description>Priority of interrupt 9</description>
+              <name>IP_9</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:6]</bitRange>
+              <description>Priority of interrupt 8</description>
+              <name>IP_8</name>
+            </field>
+          </fields>
+          <name>NVIC_IPR2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe40c</addressOffset>
+          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:30]</bitRange>
+              <description>Priority of interrupt 15</description>
+              <name>IP_15</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:22]</bitRange>
+              <description>Priority of interrupt 14</description>
+              <name>IP_14</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:14]</bitRange>
+              <description>Priority of interrupt 13</description>
+              <name>IP_13</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:6]</bitRange>
+              <description>Priority of interrupt 12</description>
+              <name>IP_12</name>
+            </field>
+          </fields>
+          <name>NVIC_IPR3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe410</addressOffset>
+          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:30]</bitRange>
+              <description>Priority of interrupt 19</description>
+              <name>IP_19</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:22]</bitRange>
+              <description>Priority of interrupt 18</description>
+              <name>IP_18</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:14]</bitRange>
+              <description>Priority of interrupt 17</description>
+              <name>IP_17</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:6]</bitRange>
+              <description>Priority of interrupt 16</description>
+              <name>IP_16</name>
+            </field>
+          </fields>
+          <name>NVIC_IPR4</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe414</addressOffset>
+          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:30]</bitRange>
+              <description>Priority of interrupt 23</description>
+              <name>IP_23</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:22]</bitRange>
+              <description>Priority of interrupt 22</description>
+              <name>IP_22</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:14]</bitRange>
+              <description>Priority of interrupt 21</description>
+              <name>IP_21</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:6]</bitRange>
+              <description>Priority of interrupt 20</description>
+              <name>IP_20</name>
+            </field>
+          </fields>
+          <name>NVIC_IPR5</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe418</addressOffset>
+          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:30]</bitRange>
+              <description>Priority of interrupt 27</description>
+              <name>IP_27</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:22]</bitRange>
+              <description>Priority of interrupt 26</description>
+              <name>IP_26</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:14]</bitRange>
+              <description>Priority of interrupt 25</description>
+              <name>IP_25</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:6]</bitRange>
+              <description>Priority of interrupt 24</description>
+              <name>IP_24</name>
+            </field>
+          </fields>
+          <name>NVIC_IPR6</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xe41c</addressOffset>
+          <description>Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:30]</bitRange>
+              <description>Priority of interrupt 31</description>
+              <name>IP_31</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:22]</bitRange>
+              <description>Priority of interrupt 30</description>
+              <name>IP_30</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:14]</bitRange>
+              <description>Priority of interrupt 29</description>
+              <name>IP_29</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[7:6]</bitRange>
+              <description>Priority of interrupt 28</description>
+              <name>IP_28</name>
+            </field>
+          </fields>
+          <name>NVIC_IPR7</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xed00</addressOffset>
+          <description>Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[31:24]</bitRange>
+              <description>Implementor code: 0x41 = ARM</description>
+              <name>IMPLEMENTER</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:20]</bitRange>
+              <description>Major revision number n in the rnpm revision status:\n
+                0x0 = Revision 0.</description>
+              <name>VARIANT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[19:16]</bitRange>
+              <description>Constant that defines the architecture of the processor:\n
+                0xC = ARMv6-M architecture.</description>
+              <name>ARCHITECTURE</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:4]</bitRange>
+              <description>Number of processor within family: 0xC60 = Cortex-M0+</description>
+              <name>PARTNO</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:0]</bitRange>
+              <description>Minor revision number m in the rnpm revision status:\n
+                0x1 = Patch 1.</description>
+              <name>REVISION</name>
+            </field>
+          </fields>
+          <name>CPUID</name>
+          <resetValue>0x410cc601</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xed04</addressOffset>
+          <description>Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:31]</bitRange>
+              <description>Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.\n
+                NMI set-pending bit.\n
+                Write:\n
+                0 = No effect.\n
+                1 = Changes NMI exception state to pending.\n
+                Read:\n
+                0 = NMI exception is not pending.\n
+                1 = NMI exception is pending.\n
+                Because NMI is the highest-priority exception, normally the processor enters the NMI\n
+                exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears\n
+                this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the\n
+                NMI signal is reasserted while the processor is executing that handler.</description>
+              <name>NMIPENDSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[28:28]</bitRange>
+              <description>PendSV set-pending bit.\n
+                Write:\n
+                0 = No effect.\n
+                1 = Changes PendSV exception state to pending.\n
+                Read:\n
+                0 = PendSV exception is not pending.\n
+                1 = PendSV exception is pending.\n
+                Writing 1 to this bit is the only way to set the PendSV exception state to pending.</description>
+              <name>PENDSVSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[27:27]</bitRange>
+              <description>PendSV clear-pending bit.\n
+                Write:\n
+                0 = No effect.\n
+                1 = Removes the pending state from the PendSV exception.</description>
+              <name>PENDSVCLR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[26:26]</bitRange>
+              <description>SysTick exception set-pending bit.\n
+                Write:\n
+                0 = No effect.\n
+                1 = Changes SysTick exception state to pending.\n
+                Read:\n
+                0 = SysTick exception is not pending.\n
+                1 = SysTick exception is pending.</description>
+              <name>PENDSTSET</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[25:25]</bitRange>
+              <description>SysTick exception clear-pending bit.\n
+                Write:\n
+                0 = No effect.\n
+                1 = Removes the pending state from the SysTick exception.\n
+                This bit is WO. On a register read its value is Unknown.</description>
+              <name>PENDSTCLR</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:23]</bitRange>
+              <description>The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.</description>
+              <name>ISRPREEMPT</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[22:22]</bitRange>
+              <description>External interrupt pending flag</description>
+              <name>ISRPENDING</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[20:12]</bitRange>
+              <description>Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier.</description>
+              <name>VECTPENDING</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[8:0]</bitRange>
+              <description>Active exception number field. Reset clears the VECTACTIVE field.</description>
+              <name>VECTACTIVE</name>
+            </field>
+          </fields>
+          <name>ICSR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xed08</addressOffset>
+          <description>The VTOR holds the vector table offset address.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:8]</bitRange>
+              <description>Bits [31:8] of the indicate the vector table offset address.</description>
+              <name>TBLOFF</name>
+            </field>
+          </fields>
+          <name>VTOR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xed0c</addressOffset>
+          <description>Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <description>Register key:\n
+                Reads as Unknown\n
+                On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.</description>
+              <name>VECTKEY</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Data endianness implemented:\n
+                0 = Little-endian.</description>
+              <name>ENDIANESS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.</description>
+              <name>SYSRESETREQ</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted.  When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.</description>
+              <name>VECTCLRACTIVE</name>
+            </field>
+          </fields>
+          <name>AIRCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xed10</addressOffset>
+          <description>System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>Send Event on Pending bit:\n
+                0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.\n
+                1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.\n
+                When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the\n
+                processor is not waiting for an event, the event is registered and affects the next WFE.\n
+                The processor also wakes up on execution of an SEV instruction or an external event.</description>
+              <name>SEVONPEND</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Controls whether the processor uses sleep or deep sleep as its low power mode:\n
+                0 = Sleep.\n
+                1 = Deep sleep.</description>
+              <name>SLEEPDEEP</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n
+                0 = Do not sleep when returning to Thread mode.\n
+                1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.\n
+                Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.</description>
+              <name>SLEEPONEXIT</name>
+            </field>
+          </fields>
+          <name>SCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xed14</addressOffset>
+          <description>The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[9:9]</bitRange>
+              <description>Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.</description>
+              <name>STKALIGN</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[3:3]</bitRange>
+              <description>Always reads as one, indicates that all unaligned accesses generate a HardFault.</description>
+              <name>UNALIGN_TRP</name>
+            </field>
+          </fields>
+          <name>CCR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xed1c</addressOffset>
+          <description>System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:30]</bitRange>
+              <description>Priority of system handler 11, SVCall</description>
+              <name>PRI_11</name>
+            </field>
+          </fields>
+          <name>SHPR2</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xed20</addressOffset>
+          <description>System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:30]</bitRange>
+              <description>Priority of system handler 15, SysTick</description>
+              <name>PRI_15</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[23:22]</bitRange>
+              <description>Priority of system handler 14, PendSV</description>
+              <name>PRI_14</name>
+            </field>
+          </fields>
+          <name>SHPR3</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xed24</addressOffset>
+          <description>Use the System Handler Control and State Register to determine or clear the pending status of SVCall.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:15]</bitRange>
+              <description>Reads as 1 if SVCall is Pending.  Write 1 to set pending SVCall, write 0 to clear pending SVCall.</description>
+              <name>SVCALLPENDED</name>
+            </field>
+          </fields>
+          <name>SHCSR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xed90</addressOffset>
+          <description>Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.</description>
+          <fields>
+            <field>
+              <access>read-only</access>
+              <bitRange>[23:16]</bitRange>
+              <description>Instruction region. Reads as zero as ARMv6-M only supports a unified MPU.</description>
+              <name>IREGION</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[15:8]</bitRange>
+              <description>Number of regions supported by the MPU.</description>
+              <name>DREGION</name>
+            </field>
+            <field>
+              <access>read-only</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU.</description>
+              <name>SEPARATE</name>
+            </field>
+          </fields>
+          <name>MPU_TYPE</name>
+          <resetValue>0x00000800</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xed94</addressOffset>
+          <description>Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[2:2]</bitRange>
+              <description>Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.\n
+                0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not\n
+                covered by any enabled region causes a fault.\n
+                1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.\n
+                When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.</description>
+              <name>PRIVDEFENA</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[1:1]</bitRange>
+              <description>Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.\n
+                When the MPU is enabled:\n
+                0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.\n
+                1 = the MPU is enabled during HardFault and NMI handlers.</description>
+              <name>HFNMIENA</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.\n
+                0 = MPU disabled.\n
+                1 = MPU enabled.</description>
+              <name>ENABLE</name>
+            </field>
+          </fields>
+          <name>MPU_CTRL</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xed98</addressOffset>
+          <description>Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <description>Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\n
+                The MPU supports 8 memory regions, so the permitted values of this field are 0-7.</description>
+              <name>REGION</name>
+            </field>
+          </fields>
+          <name>MPU_RNR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xed9c</addressOffset>
+          <description>Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:8]</bitRange>
+              <description>Base address of the region.</description>
+              <name>ADDR</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[4:4]</bitRange>
+              <description>On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.\n
+                Write:\n
+                0 = MPU_RNR not changed, and the processor:\n
+                Updates the base address for the region specified in the MPU_RNR.\n
+                Ignores the value of the REGION field.\n
+                1 = The processor:\n
+                Updates the value of the MPU_RNR to the value of the REGION field.\n
+                Updates the base address for the region specified in the REGION field.\n
+                Always reads as zero.</description>
+              <name>VALID</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[3:0]</bitRange>
+              <description>On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR.</description>
+              <name>REGION</name>
+            </field>
+          </fields>
+          <name>MPU_RBAR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+        <register>
+          <addressOffset>0xeda0</addressOffset>
+          <description>Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.</description>
+          <fields>
+            <field>
+              <access>read-write</access>
+              <bitRange>[31:16]</bitRange>
+              <description>The MPU Region Attribute field. Use to define the region attribute control.\n
+                28 = XN: Instruction access disable bit:\n
+                0 = Instruction fetches enabled.\n
+                1 = Instruction fetches disabled.\n
+                26:24 = AP: Access permission field\n
+                18 = S: Shareable bit\n
+                17 = C: Cacheable bit\n
+                16 = B: Bufferable bit</description>
+              <name>ATTRS</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[15:8]</bitRange>
+              <description>Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled.</description>
+              <name>SRD</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[5:1]</bitRange>
+              <description>Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes</description>
+              <name>SIZE</name>
+            </field>
+            <field>
+              <access>read-write</access>
+              <bitRange>[0:0]</bitRange>
+              <description>Enables the region.</description>
+              <name>ENABLE</name>
+            </field>
+          </fields>
+          <name>MPU_RASR</name>
+          <resetValue>0x00000000</resetValue>
+        </register>
+      </registers>
+      <size>32</size>
+      <version>1</version>
+    </peripheral>
+  </peripherals>
+</device>
\ No newline at end of file
diff --git a/src/rp2040/hardware_structs/CMakeLists.txt b/src/rp2040/hardware_structs/CMakeLists.txt
new file mode 100644
index 0000000..9c39eef
--- /dev/null
+++ b/src/rp2040/hardware_structs/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_library(hardware_structs INTERFACE)
+target_include_directories(hardware_structs INTERFACE include)
+target_link_libraries(hardware_structs INTERFACE hardware_regs)
\ No newline at end of file
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/adc.h b/src/rp2040/hardware_structs/include/hardware/structs/adc.h
new file mode 100644
index 0000000..c47e9d4
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/adc.h
@@ -0,0 +1,91 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_ADC_H
+#define _HARDWARE_STRUCTS_ADC_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/adc.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/adc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(ADC_CS_OFFSET) // ADC_CS
+    // ADC Control and Status
+    // 0x001f0000 [20:16] : RROBIN (0): Round-robin sampling
+    // 0x00007000 [14:12] : AINSEL (0): Select analog mux input
+    // 0x00000400 [10]    : ERR_STICKY (0): Some past ADC conversion encountered an error
+    // 0x00000200 [9]     : ERR (0): The most recent ADC conversion encountered an error; result is undefined or noisy
+    // 0x00000100 [8]     : READY (0): 1 if the ADC is ready to start a new conversion
+    // 0x00000008 [3]     : START_MANY (0): Continuously perform conversions whilst this bit is 1
+    // 0x00000004 [2]     : START_ONCE (0): Start a single conversion
+    // 0x00000002 [1]     : TS_EN (0): Power on temperature sensor
+    // 0x00000001 [0]     : EN (0): Power on ADC and enable its clock
+    io_rw_32 cs;
+
+    _REG_(ADC_RESULT_OFFSET) // ADC_RESULT
+    // Result of most recent ADC conversion
+    // 0x00000fff [11:0]  : RESULT (0)
+    io_ro_32 result;
+
+    _REG_(ADC_FCS_OFFSET) // ADC_FCS
+    // FIFO control and status
+    // 0x0f000000 [27:24] : THRESH (0): DREQ/IRQ asserted when level >= threshold
+    // 0x000f0000 [19:16] : LEVEL (0): The number of conversion results currently waiting in the FIFO
+    // 0x00000800 [11]    : OVER (0): 1 if the FIFO has been overflowed
+    // 0x00000400 [10]    : UNDER (0): 1 if the FIFO has been underflowed
+    // 0x00000200 [9]     : FULL (0)
+    // 0x00000100 [8]     : EMPTY (0)
+    // 0x00000008 [3]     : DREQ_EN (0): If 1: assert DMA requests when FIFO contains data
+    // 0x00000004 [2]     : ERR (0): If 1: conversion error bit appears in the FIFO alongside the result
+    // 0x00000002 [1]     : SHIFT (0): If 1: FIFO results are right-shifted to be one byte in size
+    // 0x00000001 [0]     : EN (0): If 1: write result to the FIFO after each conversion
+    io_rw_32 fcs;
+
+    _REG_(ADC_FIFO_OFFSET) // ADC_FIFO
+    // Conversion result FIFO
+    // 0x00008000 [15]    : ERR (0): 1 if this particular sample experienced a conversion error
+    // 0x00000fff [11:0]  : VAL (0)
+    io_ro_32 fifo;
+
+    _REG_(ADC_DIV_OFFSET) // ADC_DIV
+    // Clock divider
+    // 0x00ffff00 [23:8]  : INT (0): Integer part of clock divisor
+    // 0x000000ff [7:0]   : FRAC (0): Fractional part of clock divisor
+    io_rw_32 div;
+
+    _REG_(ADC_INTR_OFFSET) // ADC_INTR
+    // Raw Interrupts
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
+    io_ro_32 intr;
+
+    _REG_(ADC_INTE_OFFSET) // ADC_INTE
+    // Interrupt Enable
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
+    io_rw_32 inte;
+
+    _REG_(ADC_INTF_OFFSET) // ADC_INTF
+    // Interrupt Force
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
+    io_rw_32 intf;
+
+    _REG_(ADC_INTS_OFFSET) // ADC_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000001 [0]     : FIFO (0): Triggered when the sample FIFO reaches a certain level
+    io_ro_32 ints;
+} adc_hw_t;
+
+#define adc_hw ((adc_hw_t *const)ADC_BASE)
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h b/src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h
new file mode 100644
index 0000000..81118a8
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h
@@ -0,0 +1,77 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_BUS_CTRL_H
+#define _HARDWARE_STRUCTS_BUS_CTRL_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/busctrl.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+enum bus_ctrl_perf_counter {
+    arbiter_rom_perf_event_access = 19,
+    arbiter_rom_perf_event_access_contested = 18,
+    arbiter_xip_main_perf_event_access = 17,
+    arbiter_xip_main_perf_event_access_contested = 16,
+    arbiter_sram0_perf_event_access = 15,
+    arbiter_sram0_perf_event_access_contested = 14,
+    arbiter_sram1_perf_event_access = 13,
+    arbiter_sram1_perf_event_access_contested = 12,
+    arbiter_sram2_perf_event_access = 11,
+    arbiter_sram2_perf_event_access_contested = 10,
+    arbiter_sram3_perf_event_access = 9,
+    arbiter_sram3_perf_event_access_contested = 8,
+    arbiter_sram4_perf_event_access = 7,
+    arbiter_sram4_perf_event_access_contested = 6,
+    arbiter_sram5_perf_event_access = 5,
+    arbiter_sram5_perf_event_access_contested = 4,
+    arbiter_fastperi_perf_event_access = 3,
+    arbiter_fastperi_perf_event_access_contested = 2,
+    arbiter_apb_perf_event_access = 1,
+    arbiter_apb_perf_event_access_contested = 0
+};
+
+typedef struct {
+    _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0
+    // Bus fabric performance counter 0
+    // 0x00ffffff [23:0]  : PERFCTR0 (0): Busfabric saturating performance counter 0
+    io_rw_32 value;
+
+    _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0
+    // Bus fabric performance event select for PERFCTR0
+    // 0x0000001f [4:0]   : PERFSEL0 (0x1f): Select an event for PERFCTR0
+    io_rw_32 sel;
+} bus_ctrl_perf_hw_t;
+
+typedef struct {
+    _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY
+    // Set the priority of each master for bus arbitration
+    // 0x00001000 [12]    : DMA_W (0): 0 - low priority, 1 - high priority
+    // 0x00000100 [8]     : DMA_R (0): 0 - low priority, 1 - high priority
+    // 0x00000010 [4]     : PROC1 (0): 0 - low priority, 1 - high priority
+    // 0x00000001 [0]     : PROC0 (0): 0 - low priority, 1 - high priority
+    io_rw_32 priority;
+
+    _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK
+    // Bus priority acknowledge
+    // 0x00000001 [0]     : BUS_PRIORITY_ACK (0): Goes to 1 once all arbiters have registered the new global priority levels
+    io_ro_32 priority_ack;
+
+    bus_ctrl_perf_hw_t counter[4];
+} bus_ctrl_hw_t;
+
+#define bus_ctrl_hw ((bus_ctrl_hw_t *const)BUSCTRL_BASE)
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/clocks.h b/src/rp2040/hardware_structs/include/hardware/structs/clocks.h
new file mode 100644
index 0000000..a245dbd
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/clocks.h
@@ -0,0 +1,326 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_CLOCKS_H
+#define _HARDWARE_STRUCTS_CLOCKS_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/clocks.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+/*! \brief Enumeration identifying a hardware clock
+ *  \ingroup hardware_clocks
+ */
+/// \tag::clkenum[]
+enum clock_index {
+    clk_gpout0 = 0,     ///< GPIO Muxing 0
+    clk_gpout1,         ///< GPIO Muxing 1
+    clk_gpout2,         ///< GPIO Muxing 2
+    clk_gpout3,         ///< GPIO Muxing 3
+    clk_ref,            ///< Watchdog and timers reference clock
+    clk_sys,            ///< Processors, bus fabric, memory, memory mapped registers
+    clk_peri,           ///< Peripheral clock for UART and SPI
+    clk_usb,            ///< USB clock
+    clk_adc,            ///< ADC clock
+    clk_rtc,            ///< Real time clock
+    CLK_COUNT
+};
+/// \end::clkenum[]
+
+/// \tag::clock_hw[]
+typedef struct {
+    _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL
+    // Clock control, can be changed on-the-fly (except for auxsrc)
+    // 0x00100000 [20]    : NUDGE (0): An edge on this signal shifts the phase of the output by 1 cycle of the input clock
+    // 0x00030000 [17:16] : PHASE (0): This delays the enable signal by up to 3 cycles of the input clock
+    // 0x00001000 [12]    : DC50 (0): Enables duty cycle correction for odd divisors
+    // 0x00000800 [11]    : ENABLE (0): Starts and stops the clock generator cleanly
+    // 0x00000400 [10]    : KILL (0): Asynchronously kills the clock generator
+    // 0x000001e0 [8:5]   : AUXSRC (0): Selects the auxiliary clock source, will glitch when switching
+    io_rw_32 ctrl;
+
+    _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV
+    // Clock divisor, can be changed on-the-fly
+    // 0xffffff00 [31:8]  : INT (1): Integer component of the divisor, 0 -> divide by 2^16
+    // 0x000000ff [7:0]   : FRAC (0): Fractional component of the divisor
+    io_rw_32 div;
+
+    _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED
+    // Indicates which SRC is currently selected by the glitchless mux (one-hot)
+    io_ro_32 selected;
+} clock_hw_t;
+/// \end::clock_hw[]
+
+typedef struct {
+    _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL
+    // 0x00010000 [16]    : CLEAR (0): For clearing the resus after the fault that triggered it has been corrected
+    // 0x00001000 [12]    : FRCE (0): Force a resus, for test purposes only
+    // 0x00000100 [8]     : ENABLE (0): Enable resus
+    // 0x000000ff [7:0]   : TIMEOUT (0xff): This is expressed as a number of clk_ref cycles
+    io_rw_32 ctrl;
+
+    _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS
+    // 0x00000001 [0]     : RESUSSED (0): Clock has been resuscitated, correct the error then send ctrl_clear=1
+    io_ro_32 status;
+} clock_resus_hw_t;
+
+typedef struct {
+    _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ
+    // Reference clock frequency in kHz
+    // 0x000fffff [19:0]  : FC0_REF_KHZ (0)
+    io_rw_32 ref_khz;
+
+    _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ
+    // Minimum pass frequency in kHz
+    // 0x01ffffff [24:0]  : FC0_MIN_KHZ (0)
+    io_rw_32 min_khz;
+
+    _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ
+    // Maximum pass frequency in kHz
+    // 0x01ffffff [24:0]  : FC0_MAX_KHZ (0x1ffffff)
+    io_rw_32 max_khz;
+
+    _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY
+    // Delays the start of frequency counting to allow the mux to settle
+    // 0x00000007 [2:0]   : FC0_DELAY (1)
+    io_rw_32 delay;
+
+    _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL
+    // The test interval is 0
+    // 0x0000000f [3:0]   : FC0_INTERVAL (0x8)
+    io_rw_32 interval;
+
+    _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC
+    // Clock sent to frequency counter, set to 0 when not required
+    // 0x000000ff [7:0]   : FC0_SRC (0)
+    io_rw_32 src;
+
+    _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS
+    // Frequency counter status
+    // 0x10000000 [28]    : DIED (0): Test clock stopped during test
+    // 0x01000000 [24]    : FAST (0): Test clock faster than expected, only valid when status_done=1
+    // 0x00100000 [20]    : SLOW (0): Test clock slower than expected, only valid when status_done=1
+    // 0x00010000 [16]    : FAIL (0): Test failed
+    // 0x00001000 [12]    : WAITING (0): Waiting for test clock to start
+    // 0x00000100 [8]     : RUNNING (0): Test running
+    // 0x00000010 [4]     : DONE (0): Test complete
+    // 0x00000001 [0]     : PASS (0): Test passed
+    io_ro_32 status;
+
+    _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT
+    // Result of frequency measurement, only valid when status_done=1
+    // 0x3fffffe0 [29:5]  : KHZ (0)
+    // 0x0000001f [4:0]   : FRAC (0)
+    io_ro_32 result;
+} fc_hw_t;
+
+typedef struct {
+    clock_hw_t clk[CLK_COUNT]; // 10
+
+    clock_resus_hw_t resus;
+
+    fc_hw_t fc0;
+
+    _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
+    // enable clock in wake mode
+    // 0x80000000 [31]    : clk_sys_sram3 (1)
+    // 0x40000000 [30]    : clk_sys_sram2 (1)
+    // 0x20000000 [29]    : clk_sys_sram1 (1)
+    // 0x10000000 [28]    : clk_sys_sram0 (1)
+    // 0x08000000 [27]    : clk_sys_spi1 (1)
+    // 0x04000000 [26]    : clk_peri_spi1 (1)
+    // 0x02000000 [25]    : clk_sys_spi0 (1)
+    // 0x01000000 [24]    : clk_peri_spi0 (1)
+    // 0x00800000 [23]    : clk_sys_sio (1)
+    // 0x00400000 [22]    : clk_sys_rtc (1)
+    // 0x00200000 [21]    : clk_rtc_rtc (1)
+    // 0x00100000 [20]    : clk_sys_rosc (1)
+    // 0x00080000 [19]    : clk_sys_rom (1)
+    // 0x00040000 [18]    : clk_sys_resets (1)
+    // 0x00020000 [17]    : clk_sys_pwm (1)
+    // 0x00010000 [16]    : clk_sys_psm (1)
+    // 0x00008000 [15]    : clk_sys_pll_usb (1)
+    // 0x00004000 [14]    : clk_sys_pll_sys (1)
+    // 0x00002000 [13]    : clk_sys_pio1 (1)
+    // 0x00001000 [12]    : clk_sys_pio0 (1)
+    // 0x00000800 [11]    : clk_sys_pads (1)
+    // 0x00000400 [10]    : clk_sys_vreg_and_chip_reset (1)
+    // 0x00000200 [9]     : clk_sys_jtag (1)
+    // 0x00000100 [8]     : clk_sys_io (1)
+    // 0x00000080 [7]     : clk_sys_i2c1 (1)
+    // 0x00000040 [6]     : clk_sys_i2c0 (1)
+    // 0x00000020 [5]     : clk_sys_dma (1)
+    // 0x00000010 [4]     : clk_sys_busfabric (1)
+    // 0x00000008 [3]     : clk_sys_busctrl (1)
+    // 0x00000004 [2]     : clk_sys_adc (1)
+    // 0x00000002 [1]     : clk_adc_adc (1)
+    // 0x00000001 [0]     : clk_sys_clocks (1)
+    io_rw_32 wake_en0;
+
+    _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1
+    // enable clock in wake mode
+    // 0x00004000 [14]    : clk_sys_xosc (1)
+    // 0x00002000 [13]    : clk_sys_xip (1)
+    // 0x00001000 [12]    : clk_sys_watchdog (1)
+    // 0x00000800 [11]    : clk_usb_usbctrl (1)
+    // 0x00000400 [10]    : clk_sys_usbctrl (1)
+    // 0x00000200 [9]     : clk_sys_uart1 (1)
+    // 0x00000100 [8]     : clk_peri_uart1 (1)
+    // 0x00000080 [7]     : clk_sys_uart0 (1)
+    // 0x00000040 [6]     : clk_peri_uart0 (1)
+    // 0x00000020 [5]     : clk_sys_timer (1)
+    // 0x00000010 [4]     : clk_sys_tbman (1)
+    // 0x00000008 [3]     : clk_sys_sysinfo (1)
+    // 0x00000004 [2]     : clk_sys_syscfg (1)
+    // 0x00000002 [1]     : clk_sys_sram5 (1)
+    // 0x00000001 [0]     : clk_sys_sram4 (1)
+    io_rw_32 wake_en1;
+
+    _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
+    // enable clock in sleep mode
+    // 0x80000000 [31]    : clk_sys_sram3 (1)
+    // 0x40000000 [30]    : clk_sys_sram2 (1)
+    // 0x20000000 [29]    : clk_sys_sram1 (1)
+    // 0x10000000 [28]    : clk_sys_sram0 (1)
+    // 0x08000000 [27]    : clk_sys_spi1 (1)
+    // 0x04000000 [26]    : clk_peri_spi1 (1)
+    // 0x02000000 [25]    : clk_sys_spi0 (1)
+    // 0x01000000 [24]    : clk_peri_spi0 (1)
+    // 0x00800000 [23]    : clk_sys_sio (1)
+    // 0x00400000 [22]    : clk_sys_rtc (1)
+    // 0x00200000 [21]    : clk_rtc_rtc (1)
+    // 0x00100000 [20]    : clk_sys_rosc (1)
+    // 0x00080000 [19]    : clk_sys_rom (1)
+    // 0x00040000 [18]    : clk_sys_resets (1)
+    // 0x00020000 [17]    : clk_sys_pwm (1)
+    // 0x00010000 [16]    : clk_sys_psm (1)
+    // 0x00008000 [15]    : clk_sys_pll_usb (1)
+    // 0x00004000 [14]    : clk_sys_pll_sys (1)
+    // 0x00002000 [13]    : clk_sys_pio1 (1)
+    // 0x00001000 [12]    : clk_sys_pio0 (1)
+    // 0x00000800 [11]    : clk_sys_pads (1)
+    // 0x00000400 [10]    : clk_sys_vreg_and_chip_reset (1)
+    // 0x00000200 [9]     : clk_sys_jtag (1)
+    // 0x00000100 [8]     : clk_sys_io (1)
+    // 0x00000080 [7]     : clk_sys_i2c1 (1)
+    // 0x00000040 [6]     : clk_sys_i2c0 (1)
+    // 0x00000020 [5]     : clk_sys_dma (1)
+    // 0x00000010 [4]     : clk_sys_busfabric (1)
+    // 0x00000008 [3]     : clk_sys_busctrl (1)
+    // 0x00000004 [2]     : clk_sys_adc (1)
+    // 0x00000002 [1]     : clk_adc_adc (1)
+    // 0x00000001 [0]     : clk_sys_clocks (1)
+    io_rw_32 sleep_en0;
+
+    _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1
+    // enable clock in sleep mode
+    // 0x00004000 [14]    : clk_sys_xosc (1)
+    // 0x00002000 [13]    : clk_sys_xip (1)
+    // 0x00001000 [12]    : clk_sys_watchdog (1)
+    // 0x00000800 [11]    : clk_usb_usbctrl (1)
+    // 0x00000400 [10]    : clk_sys_usbctrl (1)
+    // 0x00000200 [9]     : clk_sys_uart1 (1)
+    // 0x00000100 [8]     : clk_peri_uart1 (1)
+    // 0x00000080 [7]     : clk_sys_uart0 (1)
+    // 0x00000040 [6]     : clk_peri_uart0 (1)
+    // 0x00000020 [5]     : clk_sys_timer (1)
+    // 0x00000010 [4]     : clk_sys_tbman (1)
+    // 0x00000008 [3]     : clk_sys_sysinfo (1)
+    // 0x00000004 [2]     : clk_sys_syscfg (1)
+    // 0x00000002 [1]     : clk_sys_sram5 (1)
+    // 0x00000001 [0]     : clk_sys_sram4 (1)
+    io_rw_32 sleep_en1;
+
+    _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
+    // indicates the state of the clock enable
+    // 0x80000000 [31]    : clk_sys_sram3 (0)
+    // 0x40000000 [30]    : clk_sys_sram2 (0)
+    // 0x20000000 [29]    : clk_sys_sram1 (0)
+    // 0x10000000 [28]    : clk_sys_sram0 (0)
+    // 0x08000000 [27]    : clk_sys_spi1 (0)
+    // 0x04000000 [26]    : clk_peri_spi1 (0)
+    // 0x02000000 [25]    : clk_sys_spi0 (0)
+    // 0x01000000 [24]    : clk_peri_spi0 (0)
+    // 0x00800000 [23]    : clk_sys_sio (0)
+    // 0x00400000 [22]    : clk_sys_rtc (0)
+    // 0x00200000 [21]    : clk_rtc_rtc (0)
+    // 0x00100000 [20]    : clk_sys_rosc (0)
+    // 0x00080000 [19]    : clk_sys_rom (0)
+    // 0x00040000 [18]    : clk_sys_resets (0)
+    // 0x00020000 [17]    : clk_sys_pwm (0)
+    // 0x00010000 [16]    : clk_sys_psm (0)
+    // 0x00008000 [15]    : clk_sys_pll_usb (0)
+    // 0x00004000 [14]    : clk_sys_pll_sys (0)
+    // 0x00002000 [13]    : clk_sys_pio1 (0)
+    // 0x00001000 [12]    : clk_sys_pio0 (0)
+    // 0x00000800 [11]    : clk_sys_pads (0)
+    // 0x00000400 [10]    : clk_sys_vreg_and_chip_reset (0)
+    // 0x00000200 [9]     : clk_sys_jtag (0)
+    // 0x00000100 [8]     : clk_sys_io (0)
+    // 0x00000080 [7]     : clk_sys_i2c1 (0)
+    // 0x00000040 [6]     : clk_sys_i2c0 (0)
+    // 0x00000020 [5]     : clk_sys_dma (0)
+    // 0x00000010 [4]     : clk_sys_busfabric (0)
+    // 0x00000008 [3]     : clk_sys_busctrl (0)
+    // 0x00000004 [2]     : clk_sys_adc (0)
+    // 0x00000002 [1]     : clk_adc_adc (0)
+    // 0x00000001 [0]     : clk_sys_clocks (0)
+    io_ro_32 enabled0;
+
+    _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1
+    // indicates the state of the clock enable
+    // 0x00004000 [14]    : clk_sys_xosc (0)
+    // 0x00002000 [13]    : clk_sys_xip (0)
+    // 0x00001000 [12]    : clk_sys_watchdog (0)
+    // 0x00000800 [11]    : clk_usb_usbctrl (0)
+    // 0x00000400 [10]    : clk_sys_usbctrl (0)
+    // 0x00000200 [9]     : clk_sys_uart1 (0)
+    // 0x00000100 [8]     : clk_peri_uart1 (0)
+    // 0x00000080 [7]     : clk_sys_uart0 (0)
+    // 0x00000040 [6]     : clk_peri_uart0 (0)
+    // 0x00000020 [5]     : clk_sys_timer (0)
+    // 0x00000010 [4]     : clk_sys_tbman (0)
+    // 0x00000008 [3]     : clk_sys_sysinfo (0)
+    // 0x00000004 [2]     : clk_sys_syscfg (0)
+    // 0x00000002 [1]     : clk_sys_sram5 (0)
+    // 0x00000001 [0]     : clk_sys_sram4 (0)
+    io_ro_32 enabled1;
+
+    _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR
+    // Raw Interrupts
+    // 0x00000001 [0]     : CLK_SYS_RESUS (0)
+    io_ro_32 intr;
+
+    _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE
+    // Interrupt Enable
+    // 0x00000001 [0]     : CLK_SYS_RESUS (0)
+    io_rw_32 inte;
+
+    _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF
+    // Interrupt Force
+    // 0x00000001 [0]     : CLK_SYS_RESUS (0)
+    io_rw_32 intf;
+
+    _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000001 [0]     : CLK_SYS_RESUS (0)
+    io_ro_32 ints;
+} clocks_hw_t;
+
+#define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE)
+
+static_assert( CLK_COUNT == 10, "");
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/dma.h b/src/rp2040/hardware_structs/include/hardware/structs/dma.h
new file mode 100644
index 0000000..0d20641
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/dma.h
@@ -0,0 +1,203 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_DMA_H
+#define _HARDWARE_STRUCTS_DMA_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/dma.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR
+    // DMA Channel 0 Read Address pointer
+    io_rw_32 read_addr;
+
+    _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR
+    // DMA Channel 0 Write Address pointer
+    io_rw_32 write_addr;
+
+    _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT
+    // DMA Channel 0 Transfer Count
+    io_rw_32 transfer_count;
+
+    _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG
+    // DMA Channel 0 Control and Status
+    // 0x80000000 [31]    : AHB_ERROR (0): Logical OR of the READ_ERROR and WRITE_ERROR flags
+    // 0x40000000 [30]    : READ_ERROR (0): If 1, the channel received a read bus error
+    // 0x20000000 [29]    : WRITE_ERROR (0): If 1, the channel received a write bus error
+    // 0x01000000 [24]    : BUSY (0): This flag goes high when the channel starts a new transfer sequence, and low when the...
+    // 0x00800000 [23]    : SNIFF_EN (0): If 1, this channel's data transfers are visible to the sniff hardware, and each...
+    // 0x00400000 [22]    : BSWAP (0): Apply byte-swap transformation to DMA data
+    // 0x00200000 [21]    : IRQ_QUIET (0): In QUIET mode, the channel does not generate IRQs at the end of every transfer block
+    // 0x001f8000 [20:15] : TREQ_SEL (0): Select a Transfer Request signal
+    // 0x00007800 [14:11] : CHAIN_TO (0): When this channel completes, it will trigger the channel indicated by CHAIN_TO
+    // 0x00000400 [10]    : RING_SEL (0): Select whether RING_SIZE applies to read or write addresses
+    // 0x000003c0 [9:6]   : RING_SIZE (0): Size of address wrap region
+    // 0x00000020 [5]     : INCR_WRITE (0): If 1, the write address increments with each transfer
+    // 0x00000010 [4]     : INCR_READ (0): If 1, the read address increments with each transfer
+    // 0x0000000c [3:2]   : DATA_SIZE (0): Set the size of each bus transfer (byte/halfword/word)
+    // 0x00000002 [1]     : HIGH_PRIORITY (0): HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in...
+    // 0x00000001 [0]     : EN (0): DMA Channel Enable
+    io_rw_32 ctrl_trig;
+
+    _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL
+    // Alias for channel 0 CTRL register
+    io_rw_32 al1_ctrl;
+
+    _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR
+    // Alias for channel 0 READ_ADDR register
+    io_rw_32 al1_read_addr;
+
+    _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR
+    // Alias for channel 0 WRITE_ADDR register
+    io_rw_32 al1_write_addr;
+
+    _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG
+    // Alias for channel 0 TRANS_COUNT register
+    io_rw_32 al1_transfer_count_trig;
+
+    _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL
+    // Alias for channel 0 CTRL register
+    io_rw_32 al2_ctrl;
+
+    _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT
+    // Alias for channel 0 TRANS_COUNT register
+    io_rw_32 al2_transfer_count;
+
+    _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR
+    // Alias for channel 0 READ_ADDR register
+    io_rw_32 al2_read_addr;
+
+    _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG
+    // Alias for channel 0 WRITE_ADDR register
+    io_rw_32 al2_write_addr_trig;
+
+    _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL
+    // Alias for channel 0 CTRL register
+    io_rw_32 al3_ctrl;
+
+    _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR
+    // Alias for channel 0 WRITE_ADDR register
+    io_rw_32 al3_write_addr;
+
+    _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT
+    // Alias for channel 0 TRANS_COUNT register
+    io_rw_32 al3_transfer_count;
+
+    _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG
+    // Alias for channel 0 READ_ADDR register
+    io_rw_32 al3_read_addr_trig;
+} dma_channel_hw_t;
+
+typedef struct {
+    dma_channel_hw_t ch[NUM_DMA_CHANNELS]; // 12
+
+    uint32_t _pad0[64];
+
+    _REG_(DMA_INTR_OFFSET) // DMA_INTR
+    // Interrupt Status (raw)
+    // 0x0000ffff [15:0]  : INTR (0): Raw interrupt status for DMA Channels 0
+    io_ro_32 intr;
+
+    _REG_(DMA_INTE0_OFFSET) // DMA_INTE0
+    // Interrupt Enables for IRQ 0
+    // 0x0000ffff [15:0]  : INTE0 (0): Set bit n to pass interrupts from channel n to DMA IRQ 0
+    io_rw_32 inte0;
+
+    _REG_(DMA_INTF0_OFFSET) // DMA_INTF0
+    // Force Interrupts
+    // 0x0000ffff [15:0]  : INTF0 (0): Write 1s to force the corresponding bits in INTE0
+    io_rw_32 intf0;
+
+    _REG_(DMA_INTS0_OFFSET) // DMA_INTS0
+    // Interrupt Status for IRQ 0
+    // 0x0000ffff [15:0]  : INTS0 (0): Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted
+    io_rw_32 ints0;
+
+    uint32_t _pad1;
+
+    _REG_(DMA_INTE1_OFFSET) // DMA_INTE1
+    // Interrupt Enables for IRQ 1
+    // 0x0000ffff [15:0]  : INTE1 (0): Set bit n to pass interrupts from channel n to DMA IRQ 1
+    io_rw_32 inte1;
+
+    _REG_(DMA_INTF1_OFFSET) // DMA_INTF1
+    // Force Interrupts for IRQ 1
+    // 0x0000ffff [15:0]  : INTF1 (0): Write 1s to force the corresponding bits in INTE0
+    io_rw_32 intf1;
+
+    _REG_(DMA_INTS1_OFFSET) // DMA_INTS1
+    // Interrupt Status (masked) for IRQ 1
+    // 0x0000ffff [15:0]  : INTS1 (0): Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted
+    io_rw_32 ints1;
+
+    _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0
+    // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes)
+    //
+    // Pacing (X/Y) Fractional Timer
+    // 0xffff0000 [31:16] : X (0): Pacing Timer Dividend
+    // 0x0000ffff [15:0]  : Y (0): Pacing Timer Divisor
+    io_rw_32 timer[NUM_DMA_TIMERS]; // 4
+
+    _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER
+    // Trigger one or more channels simultaneously
+    // 0x0000ffff [15:0]  : MULTI_CHAN_TRIGGER (0): Each bit in this register corresponds to a DMA channel
+    io_rw_32 multi_channel_trigger;
+
+    _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL
+    // Sniffer Control
+    // 0x00000800 [11]    : OUT_INV (0): If set, the result appears inverted (bitwise complement) when read
+    // 0x00000400 [10]    : OUT_REV (0): If set, the result appears bit-reversed when read
+    // 0x00000200 [9]     : BSWAP (0): Locally perform a byte reverse on the sniffed data, before feeding into checksum
+    // 0x000001e0 [8:5]   : CALC (0)
+    // 0x0000001e [4:1]   : DMACH (0): DMA channel for Sniffer to observe
+    // 0x00000001 [0]     : EN (0): Enable sniffer
+    io_rw_32 sniff_ctrl;
+
+    _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA
+    // Data accumulator for sniff hardware
+    io_rw_32 sniff_data;
+
+    uint32_t _pad2;
+
+    _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS
+    // Debug RAF, WAF, TDF levels
+    // 0x00ff0000 [23:16] : RAF_LVL (0): Current Read-Address-FIFO fill level
+    // 0x0000ff00 [15:8]  : WAF_LVL (0): Current Write-Address-FIFO fill level
+    // 0x000000ff [7:0]   : TDF_LVL (0): Current Transfer-Data-FIFO fill level
+    io_ro_32 fifo_levels;
+
+    _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT
+    // Abort an in-progress transfer sequence on one or more channels
+    // 0x0000ffff [15:0]  : CHAN_ABORT (0): Each bit corresponds to a channel
+    io_rw_32 abort;
+} dma_hw_t;
+
+typedef struct {
+    struct dma_debug_hw_channel {
+        io_rw_32 ctrdeq;
+        io_ro_32 tcr;
+        uint32_t pad[14];
+    } ch[NUM_DMA_CHANNELS];
+} dma_debug_hw_t;
+
+#define dma_hw ((dma_hw_t *const)DMA_BASE)
+#define dma_debug_hw ((dma_debug_hw_t *const)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET))
+
+static_assert( NUM_DMA_TIMERS == 4, "");
+static_assert( NUM_DMA_CHANNELS == 12, "");
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/i2c.h b/src/rp2040/hardware_structs/include/hardware/structs/i2c.h
new file mode 100644
index 0000000..43d6086
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/i2c.h
@@ -0,0 +1,333 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_I2C_H
+#define _HARDWARE_STRUCTS_I2C_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/i2c.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON
+    // I2C Control Register
+    // 0x00000400 [10]    : STOP_DET_IF_MASTER_ACTIVE (0): Master issues the STOP_DET interrupt irrespective of whether...
+    // 0x00000200 [9]     : RX_FIFO_FULL_HLD_CTRL (0): This bit controls whether DW_apb_i2c should hold the bus when the Rx...
+    // 0x00000100 [8]     : TX_EMPTY_CTRL (0): This bit controls the generation of the TX_EMPTY interrupt, as described in...
+    // 0x00000080 [7]     : STOP_DET_IFADDRESSED (0): In slave mode: - 1'b1:  issues the STOP_DET interrupt only when it is...
+    // 0x00000040 [6]     : IC_SLAVE_DISABLE (1): This bit controls whether I2C has its slave disabled, which means once...
+    // 0x00000020 [5]     : IC_RESTART_EN (1): Determines whether RESTART conditions may be sent when acting as a master
+    // 0x00000010 [4]     : IC_10BITADDR_MASTER (0): Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit...
+    // 0x00000008 [3]     : IC_10BITADDR_SLAVE (0): When acting as a slave, this bit controls whether the DW_apb_i2c...
+    // 0x00000006 [2:1]   : SPEED (0x2): These bits control at which speed the DW_apb_i2c operates; its setting is relevant...
+    // 0x00000001 [0]     : MASTER_MODE (1): This bit controls whether the DW_apb_i2c master is enabled
+    io_rw_32 con;
+
+    _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR
+    // I2C Target Address Register
+    // 0x00000800 [11]    : SPECIAL (0): This bit indicates whether software performs a Device-ID or General Call or START...
+    // 0x00000400 [10]    : GC_OR_START (0): If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this...
+    // 0x000003ff [9:0]   : IC_TAR (0x55): This is the target address for any master transaction
+    io_rw_32 tar;
+
+    _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR
+    // I2C Slave Address Register
+    // 0x000003ff [9:0]   : IC_SAR (0x55): The IC_SAR holds the slave address when the I2C is operating as a slave
+    io_rw_32 sar;
+
+    uint32_t _pad0;
+
+    _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD
+    // I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the...
+    // 0x00000800 [11]    : FIRST_DATA_BYTE (0): Indicates the first data byte received after the address phase for receive...
+    // 0x00000400 [10]    : RESTART (0): This bit controls whether a RESTART is issued before the byte is sent or received
+    // 0x00000200 [9]     : STOP (0): This bit controls whether a STOP is issued after the byte is sent or received
+    // 0x00000100 [8]     : CMD (0): This bit controls whether a read or a write is performed
+    // 0x000000ff [7:0]   : DAT (0): This register contains the data to be transmitted or received on the I2C bus
+    io_rw_32 data_cmd;
+
+    _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT
+    // Standard Speed I2C Clock SCL High Count Register
+    // 0x0000ffff [15:0]  : IC_SS_SCL_HCNT (0x28): This register must be set before any I2C bus transaction can take place...
+    io_rw_32 ss_scl_hcnt;
+
+    _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT
+    // Standard Speed I2C Clock SCL Low Count Register
+    // 0x0000ffff [15:0]  : IC_SS_SCL_LCNT (0x2f): This register must be set before any I2C bus transaction can take place...
+    io_rw_32 ss_scl_lcnt;
+
+    _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT
+    // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
+    // 0x0000ffff [15:0]  : IC_FS_SCL_HCNT (0x6): This register must be set before any I2C bus transaction can take place...
+    io_rw_32 fs_scl_hcnt;
+
+    _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT
+    // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
+    // 0x0000ffff [15:0]  : IC_FS_SCL_LCNT (0xd): This register must be set before any I2C bus transaction can take place...
+    io_rw_32 fs_scl_lcnt;
+
+    uint32_t _pad1[2];
+
+    _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT
+    // I2C Interrupt Status Register
+    // 0x00001000 [12]    : R_RESTART_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit
+    // 0x00000800 [11]    : R_GEN_CALL (0): See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit
+    // 0x00000400 [10]    : R_START_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit
+    // 0x00000200 [9]     : R_STOP_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit
+    // 0x00000100 [8]     : R_ACTIVITY (0): See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit
+    // 0x00000080 [7]     : R_RX_DONE (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit
+    // 0x00000040 [6]     : R_TX_ABRT (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit
+    // 0x00000020 [5]     : R_RD_REQ (0): See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit
+    // 0x00000010 [4]     : R_TX_EMPTY (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit
+    // 0x00000008 [3]     : R_TX_OVER (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit
+    // 0x00000004 [2]     : R_RX_FULL (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit
+    // 0x00000002 [1]     : R_RX_OVER (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit
+    // 0x00000001 [0]     : R_RX_UNDER (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit
+    io_ro_32 intr_stat;
+
+    _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK
+    // I2C Interrupt Mask Register
+    // 0x00001000 [12]    : M_RESTART_DET (0): This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register
+    // 0x00000800 [11]    : M_GEN_CALL (1): This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register
+    // 0x00000400 [10]    : M_START_DET (0): This bit masks the R_START_DET interrupt in IC_INTR_STAT register
+    // 0x00000200 [9]     : M_STOP_DET (0): This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register
+    // 0x00000100 [8]     : M_ACTIVITY (0): This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register
+    // 0x00000080 [7]     : M_RX_DONE (1): This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register
+    // 0x00000040 [6]     : M_TX_ABRT (1): This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register
+    // 0x00000020 [5]     : M_RD_REQ (1): This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register
+    // 0x00000010 [4]     : M_TX_EMPTY (1): This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register
+    // 0x00000008 [3]     : M_TX_OVER (1): This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register
+    // 0x00000004 [2]     : M_RX_FULL (1): This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register
+    // 0x00000002 [1]     : M_RX_OVER (1): This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register
+    // 0x00000001 [0]     : M_RX_UNDER (1): This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register
+    io_rw_32 intr_mask;
+
+    _REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT
+    // I2C Raw Interrupt Status Register
+    // 0x00001000 [12]    : RESTART_DET (0): Indicates whether a RESTART condition has occurred on the I2C interface when...
+    // 0x00000800 [11]    : GEN_CALL (0): Set only when a General Call address is received and it is acknowledged
+    // 0x00000400 [10]    : START_DET (0): Indicates whether a START or RESTART condition has occurred on the I2C interface...
+    // 0x00000200 [9]     : STOP_DET (0): Indicates whether a STOP condition has occurred on the I2C interface regardless...
+    // 0x00000100 [8]     : ACTIVITY (0): This bit captures DW_apb_i2c activity and stays set until it is cleared
+    // 0x00000080 [7]     : RX_DONE (0): When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the...
+    // 0x00000040 [6]     : TX_ABRT (0): This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the...
+    // 0x00000020 [5]     : RD_REQ (0): This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is...
+    // 0x00000010 [4]     : TX_EMPTY (0): The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL...
+    // 0x00000008 [3]     : TX_OVER (0): Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the...
+    // 0x00000004 [2]     : RX_FULL (0): Set when the receive buffer reaches or goes above the RX_TL threshold in the...
+    // 0x00000002 [1]     : RX_OVER (0): Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an...
+    // 0x00000001 [0]     : RX_UNDER (0): Set if the processor attempts to read the receive buffer when it is empty by...
+    io_ro_32 raw_intr_stat;
+
+    _REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL
+    // I2C Receive FIFO Threshold Register
+    // 0x000000ff [7:0]   : RX_TL (0): Receive FIFO Threshold Level
+    io_rw_32 rx_tl;
+
+    _REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL
+    // I2C Transmit FIFO Threshold Register
+    // 0x000000ff [7:0]   : TX_TL (0): Transmit FIFO Threshold Level
+    io_rw_32 tx_tl;
+
+    _REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR
+    // Clear Combined and Individual Interrupt Register
+    // 0x00000001 [0]     : CLR_INTR (0): Read this register to clear the combined interrupt, all individual interrupts,...
+    io_ro_32 clr_intr;
+
+    _REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER
+    // Clear RX_UNDER Interrupt Register
+    // 0x00000001 [0]     : CLR_RX_UNDER (0): Read this register to clear the RX_UNDER interrupt (bit 0) of the...
+    io_ro_32 clr_rx_under;
+
+    _REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER
+    // Clear RX_OVER Interrupt Register
+    // 0x00000001 [0]     : CLR_RX_OVER (0): Read this register to clear the RX_OVER interrupt (bit 1) of the...
+    io_ro_32 clr_rx_over;
+
+    _REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER
+    // Clear TX_OVER Interrupt Register
+    // 0x00000001 [0]     : CLR_TX_OVER (0): Read this register to clear the TX_OVER interrupt (bit 3) of the...
+    io_ro_32 clr_tx_over;
+
+    _REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ
+    // Clear RD_REQ Interrupt Register
+    // 0x00000001 [0]     : CLR_RD_REQ (0): Read this register to clear the RD_REQ interrupt (bit 5) of the...
+    io_ro_32 clr_rd_req;
+
+    _REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT
+    // Clear TX_ABRT Interrupt Register
+    // 0x00000001 [0]     : CLR_TX_ABRT (0): Read this register to clear the TX_ABRT interrupt (bit 6) of the...
+    io_ro_32 clr_tx_abrt;
+
+    _REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE
+    // Clear RX_DONE Interrupt Register
+    // 0x00000001 [0]     : CLR_RX_DONE (0): Read this register to clear the RX_DONE interrupt (bit 7) of the...
+    io_ro_32 clr_rx_done;
+
+    _REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY
+    // Clear ACTIVITY Interrupt Register
+    // 0x00000001 [0]     : CLR_ACTIVITY (0): Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore
+    io_ro_32 clr_activity;
+
+    _REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET
+    // Clear STOP_DET Interrupt Register
+    // 0x00000001 [0]     : CLR_STOP_DET (0): Read this register to clear the STOP_DET interrupt (bit 9) of the...
+    io_ro_32 clr_stop_det;
+
+    _REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET
+    // Clear START_DET Interrupt Register
+    // 0x00000001 [0]     : CLR_START_DET (0): Read this register to clear the START_DET interrupt (bit 10) of the...
+    io_ro_32 clr_start_det;
+
+    _REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL
+    // Clear GEN_CALL Interrupt Register
+    // 0x00000001 [0]     : CLR_GEN_CALL (0): Read this register to clear the GEN_CALL interrupt (bit 11) of...
+    io_ro_32 clr_gen_call;
+
+    _REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE
+    // I2C Enable Register
+    // 0x00000004 [2]     : TX_CMD_BLOCK (0): In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx...
+    // 0x00000002 [1]     : ABORT (0): When set, the controller initiates the transfer abort
+    // 0x00000001 [0]     : ENABLE (0): Controls whether the DW_apb_i2c is enabled
+    io_rw_32 enable;
+
+    _REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS
+    // I2C Status Register
+    // 0x00000040 [6]     : SLV_ACTIVITY (0): Slave FSM Activity Status
+    // 0x00000020 [5]     : MST_ACTIVITY (0): Master FSM Activity Status
+    // 0x00000010 [4]     : RFF (0): Receive FIFO Completely Full
+    // 0x00000008 [3]     : RFNE (0): Receive FIFO Not Empty
+    // 0x00000004 [2]     : TFE (1): Transmit FIFO Completely Empty
+    // 0x00000002 [1]     : TFNF (1): Transmit FIFO Not Full
+    // 0x00000001 [0]     : ACTIVITY (0): I2C Activity Status
+    io_ro_32 status;
+
+    _REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR
+    // I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer
+    // 0x0000001f [4:0]   : TXFLR (0): Transmit FIFO Level
+    io_ro_32 txflr;
+
+    _REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR
+    // I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer
+    // 0x0000001f [4:0]   : RXFLR (0): Receive FIFO Level
+    io_ro_32 rxflr;
+
+    _REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD
+    // I2C SDA Hold Time Length Register
+    // 0x00ff0000 [23:16] : IC_SDA_RX_HOLD (0): Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c...
+    // 0x0000ffff [15:0]  : IC_SDA_TX_HOLD (1): Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c...
+    io_rw_32 sda_hold;
+
+    _REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE
+    // I2C Transmit Abort Source Register
+    // 0xff800000 [31:23] : TX_FLUSH_CNT (0): This field indicates the number of Tx FIFO Data Commands which are flushed...
+    // 0x00010000 [16]    : ABRT_USER_ABRT (0): This is a master-mode-only bit
+    // 0x00008000 [15]    : ABRT_SLVRD_INTX (0): 1: When the processor side responds to a slave mode request for data to be...
+    // 0x00004000 [14]    : ABRT_SLV_ARBLOST (0): This field indicates that a Slave has lost the bus while transmitting...
+    // 0x00002000 [13]    : ABRT_SLVFLUSH_TXFIFO (0): This field specifies that the Slave has received a read command and...
+    // 0x00001000 [12]    : ARB_LOST (0): This field specifies that the Master has lost arbitration, or if...
+    // 0x00000800 [11]    : ABRT_MASTER_DIS (0): This field indicates that the User tries to initiate a Master operation...
+    // 0x00000400 [10]    : ABRT_10B_RD_NORSTRT (0): This field indicates that the restart is disabled (IC_RESTART_EN bit...
+    // 0x00000200 [9]     : ABRT_SBYTE_NORSTRT (0): To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed...
+    // 0x00000100 [8]     : ABRT_HS_NORSTRT (0): This field indicates that the restart is disabled (IC_RESTART_EN bit...
+    // 0x00000080 [7]     : ABRT_SBYTE_ACKDET (0): This field indicates that the Master has sent a START Byte and the START...
+    // 0x00000040 [6]     : ABRT_HS_ACKDET (0): This field indicates that the Master is in High Speed mode and the High...
+    // 0x00000020 [5]     : ABRT_GCALL_READ (0): This field indicates that DW_apb_i2c in the master mode has sent a General...
+    // 0x00000010 [4]     : ABRT_GCALL_NOACK (0): This field indicates that DW_apb_i2c in master mode has sent a General...
+    // 0x00000008 [3]     : ABRT_TXDATA_NOACK (0): This field indicates the master-mode only bit
+    // 0x00000004 [2]     : ABRT_10ADDR2_NOACK (0): This field indicates that the Master is in 10-bit address mode and that...
+    // 0x00000002 [1]     : ABRT_10ADDR1_NOACK (0): This field indicates that the Master is in 10-bit address mode and the...
+    // 0x00000001 [0]     : ABRT_7B_ADDR_NOACK (0): This field indicates that the Master is in 7-bit addressing mode and...
+    io_ro_32 tx_abrt_source;
+
+    _REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY
+    // Generate Slave Data NACK Register
+    // 0x00000001 [0]     : NACK (0): Generate NACK
+    io_rw_32 slv_data_nack_only;
+
+    _REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR
+    // DMA Control Register
+    // 0x00000002 [1]     : TDMAE (0): Transmit DMA Enable
+    // 0x00000001 [0]     : RDMAE (0): Receive DMA Enable
+    io_rw_32 dma_cr;
+
+    _REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR
+    // DMA Transmit Data Level Register
+    // 0x0000000f [3:0]   : DMATDL (0): Transmit Data Level
+    io_rw_32 dma_tdlr;
+
+    _REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR
+    // I2C Receive Data Level Register
+    // 0x0000000f [3:0]   : DMARDL (0): Receive Data Level
+    io_rw_32 dma_rdlr;
+
+    _REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP
+    // I2C SDA Setup Register
+    // 0x000000ff [7:0]   : SDA_SETUP (0x64): SDA Setup
+    io_rw_32 sda_setup;
+
+    _REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL
+    // I2C ACK General Call Register
+    // 0x00000001 [0]     : ACK_GEN_CALL (1): ACK General Call
+    io_rw_32 ack_general_call;
+
+    _REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS
+    // I2C Enable Status Register
+    // 0x00000004 [2]     : SLV_RX_DATA_LOST (0): Slave Received Data Lost
+    // 0x00000002 [1]     : SLV_DISABLED_WHILE_BUSY (0): Slave Disabled While Busy (Transmit, Receive)
+    // 0x00000001 [0]     : IC_EN (0): ic_en Status
+    io_ro_32 enable_status;
+
+    _REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN
+    // I2C SS, FS or FM+ spike suppression limit
+    // 0x000000ff [7:0]   : IC_FS_SPKLEN (0x7): This register must be set before any I2C bus transaction can take place to...
+    io_rw_32 fs_spklen;
+
+    uint32_t _pad2;
+
+    _REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET
+    // Clear RESTART_DET Interrupt Register
+    // 0x00000001 [0]     : CLR_RESTART_DET (0): Read this register to clear the RESTART_DET interrupt (bit 12) of...
+    io_ro_32 clr_restart_det;
+
+    uint32_t _pad3[18];
+
+    _REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1
+    // Component Parameter Register 1
+    // 0x00ff0000 [23:16] : TX_BUFFER_DEPTH (0): TX Buffer Depth = 16
+    // 0x0000ff00 [15:8]  : RX_BUFFER_DEPTH (0): RX Buffer Depth = 16
+    // 0x00000080 [7]     : ADD_ENCODED_PARAMS (0): Encoded parameters not visible
+    // 0x00000040 [6]     : HAS_DMA (0): DMA handshaking signals are enabled
+    // 0x00000020 [5]     : INTR_IO (0): COMBINED Interrupt outputs
+    // 0x00000010 [4]     : HC_COUNT_VALUES (0): Programmable count values for each mode
+    // 0x0000000c [3:2]   : MAX_SPEED_MODE (0): MAX SPEED MODE = FAST MODE
+    // 0x00000003 [1:0]   : APB_DATA_WIDTH (0): APB data bus width is 32 bits
+    io_ro_32 comp_param_1;
+
+    _REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION
+    // I2C Component Version Register
+    // 0xffffffff [31:0]  : IC_COMP_VERSION (0x3230312a)
+    io_ro_32 comp_version;
+
+    _REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE
+    // I2C Component Type Register
+    // 0xffffffff [31:0]  : IC_COMP_TYPE (0x44570140): Designware Component Type number = 0x44_57_01_40
+    io_ro_32 comp_type;
+} i2c_hw_t;
+
+#define i2c0_hw ((i2c_hw_t *const)I2C0_BASE)
+#define i2c1_hw ((i2c_hw_t *const)I2C1_BASE)
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/interp.h b/src/rp2040/hardware_structs/include/hardware/structs/interp.h
new file mode 100644
index 0000000..e96caab
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/interp.h
@@ -0,0 +1,82 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_INTERP_H
+#define _HARDWARE_STRUCTS_INTERP_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/sio.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0
+    // (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes)
+    //
+    // Read/write access to accumulator 0
+    io_rw_32 accum[2];
+
+    _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0
+    // (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes)
+    //
+    // Read/write access to BASE0 register
+    io_rw_32 base[3];
+
+    _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0
+    // (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes)
+    //
+    // Read LANE0 result, and simultaneously write lane results to both accumulators (POP)
+    io_ro_32 pop[3];
+
+    _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0
+    // (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes)
+    //
+    // Read LANE0 result, without altering any internal state (PEEK)
+    io_ro_32 peek[3];
+
+    _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0
+    // (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes)
+    //
+    // Control register for lane 0
+    // 0x02000000 [25]    : OVERF (0): Set if either OVERF0 or OVERF1 is set
+    // 0x01000000 [24]    : OVERF1 (0): Indicates if any masked-off MSBs in ACCUM1 are set
+    // 0x00800000 [23]    : OVERF0 (0): Indicates if any masked-off MSBs in ACCUM0 are set
+    // 0x00200000 [21]    : BLEND (0): Only present on INTERP0 on each core
+    // 0x00180000 [20:19] : FORCE_MSB (0): ORed into bits 29:28 of the lane result presented to the processor on the bus
+    // 0x00040000 [18]    : ADD_RAW (0): If 1, mask + shift is bypassed for LANE0 result
+    // 0x00020000 [17]    : CROSS_RESULT (0): If 1, feed the opposite lane's result into this lane's accumulator on POP
+    // 0x00010000 [16]    : CROSS_INPUT (0): If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware
+    // 0x00008000 [15]    : SIGNED (0): If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
+    // 0x00007c00 [14:10] : MASK_MSB (0): The most-significant bit allowed to pass by the mask (inclusive)
+    // 0x000003e0 [9:5]   : MASK_LSB (0): The least-significant bit allowed to pass by the mask (inclusive)
+    // 0x0000001f [4:0]   : SHIFT (0): Logical right-shift applied to accumulator before masking
+    io_rw_32 ctrl[2];
+
+    _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD
+    // (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes)
+    //
+    // Values written here are atomically added to ACCUM0
+    // 0x00ffffff [23:0]  : INTERP0_ACCUM0_ADD (0)
+    io_rw_32 add_raw[2];
+
+    _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0
+    // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously
+    io_wo_32 base01;
+} interp_hw_t;
+
+#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET))
+#define interp0_hw (&interp_hw_array[0])
+#define interp1_hw (&interp_hw_array[1])
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/iobank0.h b/src/rp2040/hardware_structs/include/hardware/structs/iobank0.h
new file mode 100644
index 0000000..aae74b2
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/iobank0.h
@@ -0,0 +1,216 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_IOBANK0_H
+#define _HARDWARE_STRUCTS_IOBANK0_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/io_bank0.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS
+    // GPIO status
+    // 0x04000000 [26]    : IRQTOPROC (0): interrupt to processors, after override is applied
+    // 0x01000000 [24]    : IRQFROMPAD (0): interrupt from pad before override is applied
+    // 0x00080000 [19]    : INTOPERI (0): input signal to peripheral, after override is applied
+    // 0x00020000 [17]    : INFROMPAD (0): input signal from pad, before override is applied
+    // 0x00002000 [13]    : OETOPAD (0): output enable to pad after register override is applied
+    // 0x00001000 [12]    : OEFROMPERI (0): output enable from selected peripheral, before register override is applied
+    // 0x00000200 [9]     : OUTTOPAD (0): output signal to pad after register override is applied
+    // 0x00000100 [8]     : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied
+    io_ro_32 status;
+
+    _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL
+    // GPIO control including function select and overrides
+    // 0x30000000 [29:28] : IRQOVER (0)
+    // 0x00030000 [17:16] : INOVER (0)
+    // 0x00003000 [13:12] : OEOVER (0)
+    // 0x00000300 [9:8]   : OUTOVER (0)
+    // 0x0000001f [4:0]   : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table
+    io_rw_32 ctrl;
+} iobank0_status_ctrl_hw_t;
+
+typedef struct {
+    _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0
+    // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes)
+    //
+    // Interrupt Enable for proc0
+    // 0x80000000 [31]    : GPIO7_EDGE_HIGH (0)
+    // 0x40000000 [30]    : GPIO7_EDGE_LOW (0)
+    // 0x20000000 [29]    : GPIO7_LEVEL_HIGH (0)
+    // 0x10000000 [28]    : GPIO7_LEVEL_LOW (0)
+    // 0x08000000 [27]    : GPIO6_EDGE_HIGH (0)
+    // 0x04000000 [26]    : GPIO6_EDGE_LOW (0)
+    // 0x02000000 [25]    : GPIO6_LEVEL_HIGH (0)
+    // 0x01000000 [24]    : GPIO6_LEVEL_LOW (0)
+    // 0x00800000 [23]    : GPIO5_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO5_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO5_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO5_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO4_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO4_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO4_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO4_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO3_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO3_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO3_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO3_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO2_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO2_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO2_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO2_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO1_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO1_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO1_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO1_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO0_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO0_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO0_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO0_LEVEL_LOW (0)
+    io_rw_32 inte[4];
+
+    _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0
+    // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes)
+    //
+    // Interrupt Force for proc0
+    // 0x80000000 [31]    : GPIO7_EDGE_HIGH (0)
+    // 0x40000000 [30]    : GPIO7_EDGE_LOW (0)
+    // 0x20000000 [29]    : GPIO7_LEVEL_HIGH (0)
+    // 0x10000000 [28]    : GPIO7_LEVEL_LOW (0)
+    // 0x08000000 [27]    : GPIO6_EDGE_HIGH (0)
+    // 0x04000000 [26]    : GPIO6_EDGE_LOW (0)
+    // 0x02000000 [25]    : GPIO6_LEVEL_HIGH (0)
+    // 0x01000000 [24]    : GPIO6_LEVEL_LOW (0)
+    // 0x00800000 [23]    : GPIO5_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO5_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO5_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO5_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO4_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO4_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO4_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO4_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO3_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO3_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO3_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO3_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO2_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO2_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO2_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO2_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO1_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO1_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO1_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO1_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO0_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO0_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO0_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO0_LEVEL_LOW (0)
+    io_rw_32 intf[4];
+
+    _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0
+    // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes)
+    //
+    // Interrupt status after masking & forcing for proc0
+    // 0x80000000 [31]    : GPIO7_EDGE_HIGH (0)
+    // 0x40000000 [30]    : GPIO7_EDGE_LOW (0)
+    // 0x20000000 [29]    : GPIO7_LEVEL_HIGH (0)
+    // 0x10000000 [28]    : GPIO7_LEVEL_LOW (0)
+    // 0x08000000 [27]    : GPIO6_EDGE_HIGH (0)
+    // 0x04000000 [26]    : GPIO6_EDGE_LOW (0)
+    // 0x02000000 [25]    : GPIO6_LEVEL_HIGH (0)
+    // 0x01000000 [24]    : GPIO6_LEVEL_LOW (0)
+    // 0x00800000 [23]    : GPIO5_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO5_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO5_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO5_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO4_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO4_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO4_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO4_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO3_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO3_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO3_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO3_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO2_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO2_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO2_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO2_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO1_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO1_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO1_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO1_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO0_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO0_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO0_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO0_LEVEL_LOW (0)
+    io_ro_32 ints[4];
+} io_irq_ctrl_hw_t;
+
+/// \tag::iobank0_hw[]
+typedef struct {
+    iobank0_status_ctrl_hw_t io[NUM_BANK0_GPIOS]; // 30
+
+    _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0
+    // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes)
+    //
+    // Raw Interrupts
+    // 0x80000000 [31]    : GPIO7_EDGE_HIGH (0)
+    // 0x40000000 [30]    : GPIO7_EDGE_LOW (0)
+    // 0x20000000 [29]    : GPIO7_LEVEL_HIGH (0)
+    // 0x10000000 [28]    : GPIO7_LEVEL_LOW (0)
+    // 0x08000000 [27]    : GPIO6_EDGE_HIGH (0)
+    // 0x04000000 [26]    : GPIO6_EDGE_LOW (0)
+    // 0x02000000 [25]    : GPIO6_LEVEL_HIGH (0)
+    // 0x01000000 [24]    : GPIO6_LEVEL_LOW (0)
+    // 0x00800000 [23]    : GPIO5_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO5_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO5_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO5_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO4_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO4_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO4_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO4_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO3_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO3_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO3_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO3_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO2_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO2_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO2_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO2_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO1_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO1_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO1_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO1_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO0_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO0_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO0_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO0_LEVEL_LOW (0)
+    io_rw_32 intr[4];
+
+    io_irq_ctrl_hw_t proc0_irq_ctrl;
+
+    io_irq_ctrl_hw_t proc1_irq_ctrl;
+
+    io_irq_ctrl_hw_t dormant_wake_irq_ctrl;
+} iobank0_hw_t;
+
+#define iobank0_hw ((iobank0_hw_t *const)IO_BANK0_BASE)
+/// \end::iobank0_hw[]
+
+static_assert( NUM_BANK0_GPIOS == 30, "");
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/ioqspi.h b/src/rp2040/hardware_structs/include/hardware/structs/ioqspi.h
new file mode 100644
index 0000000..2992bfe
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/ioqspi.h
@@ -0,0 +1,174 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_IOQSPI_H
+#define _HARDWARE_STRUCTS_IOQSPI_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/io_qspi.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS
+    // GPIO status
+    // 0x04000000 [26]    : IRQTOPROC (0): interrupt to processors, after override is applied
+    // 0x01000000 [24]    : IRQFROMPAD (0): interrupt from pad before override is applied
+    // 0x00080000 [19]    : INTOPERI (0): input signal to peripheral, after override is applied
+    // 0x00020000 [17]    : INFROMPAD (0): input signal from pad, before override is applied
+    // 0x00002000 [13]    : OETOPAD (0): output enable to pad after register override is applied
+    // 0x00001000 [12]    : OEFROMPERI (0): output enable from selected peripheral, before register override is applied
+    // 0x00000200 [9]     : OUTTOPAD (0): output signal to pad after register override is applied
+    // 0x00000100 [8]     : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied
+    io_ro_32 status;
+
+    _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL
+    // GPIO control including function select and overrides
+    // 0x30000000 [29:28] : IRQOVER (0)
+    // 0x00030000 [17:16] : INOVER (0)
+    // 0x00003000 [13:12] : OEOVER (0)
+    // 0x00000300 [9:8]   : OUTOVER (0)
+    // 0x0000001f [4:0]   : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table
+    io_rw_32 ctrl;
+} ioqspi_status_ctrl_hw_t;
+
+typedef struct {
+    _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE
+    // Interrupt Enable for proc0
+    // 0x00800000 [23]    : GPIO_QSPI_SD3_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO_QSPI_SD3_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO_QSPI_SD3_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO_QSPI_SD2_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO_QSPI_SD2_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO_QSPI_SD2_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO_QSPI_SD1_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO_QSPI_SD1_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO_QSPI_SD1_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO_QSPI_SD0_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO_QSPI_SD0_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO_QSPI_SD0_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO_QSPI_SS_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO_QSPI_SS_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO_QSPI_SS_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO_QSPI_SS_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO_QSPI_SCLK_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+    io_rw_32 inte;
+
+    _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF
+    // Interrupt Force for proc0
+    // 0x00800000 [23]    : GPIO_QSPI_SD3_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO_QSPI_SD3_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO_QSPI_SD3_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO_QSPI_SD2_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO_QSPI_SD2_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO_QSPI_SD2_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO_QSPI_SD1_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO_QSPI_SD1_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO_QSPI_SD1_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO_QSPI_SD0_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO_QSPI_SD0_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO_QSPI_SD0_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO_QSPI_SS_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO_QSPI_SS_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO_QSPI_SS_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO_QSPI_SS_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO_QSPI_SCLK_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+    io_rw_32 intf;
+
+    _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS
+    // Interrupt status after masking & forcing for proc0
+    // 0x00800000 [23]    : GPIO_QSPI_SD3_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO_QSPI_SD3_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO_QSPI_SD3_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO_QSPI_SD2_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO_QSPI_SD2_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO_QSPI_SD2_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO_QSPI_SD1_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO_QSPI_SD1_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO_QSPI_SD1_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO_QSPI_SD0_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO_QSPI_SD0_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO_QSPI_SD0_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO_QSPI_SS_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO_QSPI_SS_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO_QSPI_SS_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO_QSPI_SS_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO_QSPI_SCLK_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+    io_ro_32 ints;
+} io_qspi_ctrl_hw_t;
+
+typedef struct {
+    ioqspi_status_ctrl_hw_t io[NUM_QSPI_GPIOS]; // 6
+
+    _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR
+    // Raw Interrupts
+    // 0x00800000 [23]    : GPIO_QSPI_SD3_EDGE_HIGH (0)
+    // 0x00400000 [22]    : GPIO_QSPI_SD3_EDGE_LOW (0)
+    // 0x00200000 [21]    : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+    // 0x00100000 [20]    : GPIO_QSPI_SD3_LEVEL_LOW (0)
+    // 0x00080000 [19]    : GPIO_QSPI_SD2_EDGE_HIGH (0)
+    // 0x00040000 [18]    : GPIO_QSPI_SD2_EDGE_LOW (0)
+    // 0x00020000 [17]    : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+    // 0x00010000 [16]    : GPIO_QSPI_SD2_LEVEL_LOW (0)
+    // 0x00008000 [15]    : GPIO_QSPI_SD1_EDGE_HIGH (0)
+    // 0x00004000 [14]    : GPIO_QSPI_SD1_EDGE_LOW (0)
+    // 0x00002000 [13]    : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+    // 0x00001000 [12]    : GPIO_QSPI_SD1_LEVEL_LOW (0)
+    // 0x00000800 [11]    : GPIO_QSPI_SD0_EDGE_HIGH (0)
+    // 0x00000400 [10]    : GPIO_QSPI_SD0_EDGE_LOW (0)
+    // 0x00000200 [9]     : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+    // 0x00000100 [8]     : GPIO_QSPI_SD0_LEVEL_LOW (0)
+    // 0x00000080 [7]     : GPIO_QSPI_SS_EDGE_HIGH (0)
+    // 0x00000040 [6]     : GPIO_QSPI_SS_EDGE_LOW (0)
+    // 0x00000020 [5]     : GPIO_QSPI_SS_LEVEL_HIGH (0)
+    // 0x00000010 [4]     : GPIO_QSPI_SS_LEVEL_LOW (0)
+    // 0x00000008 [3]     : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+    // 0x00000004 [2]     : GPIO_QSPI_SCLK_EDGE_LOW (0)
+    // 0x00000002 [1]     : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+    // 0x00000001 [0]     : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+    io_rw_32 intr;
+
+    io_qspi_ctrl_hw_t proc0_qspi_ctrl;
+
+    io_qspi_ctrl_hw_t proc1_qspi_ctrl;
+
+    io_qspi_ctrl_hw_t dormant_wake_qspi_ctrl;
+} ioqspi_hw_t;
+
+#define ioqspi_hw ((ioqspi_hw_t *const)IO_QSPI_BASE)
+
+static_assert( NUM_QSPI_GPIOS == 6, "");
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/mpu.h b/src/rp2040/hardware_structs/include/hardware/structs/mpu.h
new file mode 100644
index 0000000..e647220
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/mpu.h
@@ -0,0 +1,61 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_MPU_H
+#define _HARDWARE_STRUCTS_MPU_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/m0plus.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE
+    // Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports
+    // 0x00ff0000 [23:16] : IREGION (0): Instruction region
+    // 0x0000ff00 [15:8]  : DREGION (0x8): Number of regions supported by the MPU
+    // 0x00000001 [0]     : SEPARATE (0): Indicates support for separate instruction and data address maps
+    io_ro_32 type;
+
+    _REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL
+    // Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled...
+    // 0x00000004 [2]     : PRIVDEFENA (0): Controls whether the default memory map is enabled as a background region for...
+    // 0x00000002 [1]     : HFNMIENA (0): Controls the use of the MPU for HardFaults and NMIs
+    // 0x00000001 [0]     : ENABLE (0): Enables the MPU
+    io_rw_32 ctrl;
+
+    _REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR
+    // Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR
+    // 0x0000000f [3:0]   : REGION (0): Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers
+    io_rw_32 rnr;
+
+    _REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR
+    // Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR
+    // 0xffffff00 [31:8]  : ADDR (0): Base address of the region
+    // 0x00000010 [4]     : VALID (0): On writes, indicates whether the write must update the base address of the region...
+    // 0x0000000f [3:0]   : REGION (0): On writes, specifies the number of the region whose base address to update provided...
+    io_rw_32 rbar;
+
+    _REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR
+    // Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region...
+    // 0xffff0000 [31:16] : ATTRS (0): The MPU Region Attribute field
+    // 0x0000ff00 [15:8]  : SRD (0): Subregion Disable
+    // 0x0000003e [5:1]   : SIZE (0): Indicates the region size
+    // 0x00000001 [0]     : ENABLE (0): Enables the region
+    io_rw_32 rasr;
+} mpu_hw_t;
+
+#define mpu_hw ((mpu_hw_t *const)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET))
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h b/src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h
new file mode 100644
index 0000000..8036cd9
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h
@@ -0,0 +1,47 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H
+#define _HARDWARE_STRUCTS_PADS_QSPI_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/pads_qspi.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT
+    // Voltage select
+    // 0x00000001 [0]     : VOLTAGE_SELECT (0)
+    io_rw_32 voltage_select;
+
+    _REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK
+    // (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes)
+    //
+    // Pad control register
+    // 0x00000080 [7]     : OD (0): Output disable
+    // 0x00000040 [6]     : IE (1): Input enable
+    // 0x00000030 [5:4]   : DRIVE (1): Drive strength
+    // 0x00000008 [3]     : PUE (0): Pull up enable
+    // 0x00000004 [2]     : PDE (1): Pull down enable
+    // 0x00000002 [1]     : SCHMITT (1): Enable schmitt trigger
+    // 0x00000001 [0]     : SLEWFAST (0): Slew rate control
+    io_rw_32 io[NUM_QSPI_GPIOS]; // 6
+} pads_qspi_hw_t;
+
+#define pads_qspi_hw ((pads_qspi_hw_t *const)PADS_QSPI_BASE)
+
+static_assert( NUM_QSPI_GPIOS == 6, "");
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/padsbank0.h b/src/rp2040/hardware_structs/include/hardware/structs/padsbank0.h
new file mode 100644
index 0000000..2c067fa
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/padsbank0.h
@@ -0,0 +1,47 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_PADSBANK0_H
+#define _HARDWARE_STRUCTS_PADSBANK0_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/pads_bank0.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT
+    // Voltage select
+    // 0x00000001 [0]     : VOLTAGE_SELECT (0)
+    io_rw_32 voltage_select;
+
+    _REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0
+    // (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes)
+    //
+    // Pad control register
+    // 0x00000080 [7]     : OD (0): Output disable
+    // 0x00000040 [6]     : IE (1): Input enable
+    // 0x00000030 [5:4]   : DRIVE (1): Drive strength
+    // 0x00000008 [3]     : PUE (0): Pull up enable
+    // 0x00000004 [2]     : PDE (1): Pull down enable
+    // 0x00000002 [1]     : SCHMITT (1): Enable schmitt trigger
+    // 0x00000001 [0]     : SLEWFAST (0): Slew rate control
+    io_rw_32 io[NUM_BANK0_GPIOS]; // 30
+} padsbank0_hw_t;
+
+#define padsbank0_hw ((padsbank0_hw_t *const)PADS_BANK0_BASE)
+
+static_assert( NUM_BANK0_GPIOS == 30, "");
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/pio.h b/src/rp2040/hardware_structs/include/hardware/structs/pio.h
new file mode 100644
index 0000000..515e4d1
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/pio.h
@@ -0,0 +1,284 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_PIO_H
+#define _HARDWARE_STRUCTS_PIO_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/pio.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pio
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/pio.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct pio_sm_hw {
+    _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV
+    // Clock divisor register for state machine 0
+    // 0xffff0000 [31:16] : INT (1): Effective frequency is sysclk/(int + frac/256)
+    // 0x0000ff00 [15:8]  : FRAC (0): Fractional part of clock divisor
+    io_rw_32 clkdiv;
+
+    _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL
+    // Execution/behavioural settings for state machine 0
+    // 0x80000000 [31]    : EXEC_STALLED (0): If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine
+    // 0x40000000 [30]    : SIDE_EN (0): If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable,...
+    // 0x20000000 [29]    : SIDE_PINDIR (0): If 1, side-set data is asserted to pin directions, instead of pin values
+    // 0x1f000000 [28:24] : JMP_PIN (0): The GPIO number to use as condition for JMP PIN
+    // 0x00f80000 [23:19] : OUT_EN_SEL (0): Which data bit to use for inline OUT enable
+    // 0x00040000 [18]    : INLINE_OUT_EN (0): If 1, use a bit of OUT data as an auxiliary write enable
+    // 0x00020000 [17]    : OUT_STICKY (0): Continuously assert the most recent OUT/SET to the pins
+    // 0x0001f000 [16:12] : WRAP_TOP (0x1f): After reaching this address, execution is wrapped to wrap_bottom
+    // 0x00000f80 [11:7]  : WRAP_BOTTOM (0): After reaching wrap_top, execution is wrapped to this address
+    // 0x00000010 [4]     : STATUS_SEL (0): Comparison used for the MOV x, STATUS instruction
+    // 0x0000000f [3:0]   : STATUS_N (0): Comparison level for the MOV x, STATUS instruction
+    io_rw_32 execctrl;
+
+    _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL
+    // Control behaviour of the input/output shift registers for state machine 0
+    // 0x80000000 [31]    : FJOIN_RX (0): When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep
+    // 0x40000000 [30]    : FJOIN_TX (0): When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep
+    // 0x3e000000 [29:25] : PULL_THRESH (0): Number of bits shifted out of OSR before autopull, or conditional pull (PULL...
+    // 0x01f00000 [24:20] : PUSH_THRESH (0): Number of bits shifted into ISR before autopush, or conditional push (PUSH...
+    // 0x00080000 [19]    : OUT_SHIFTDIR (1): 1 = shift out of output shift register to right
+    // 0x00040000 [18]    : IN_SHIFTDIR (1): 1 = shift input shift register to right (data enters from left)
+    // 0x00020000 [17]    : AUTOPULL (0): Pull automatically when the output shift register is emptied, i
+    // 0x00010000 [16]    : AUTOPUSH (0): Push automatically when the input shift register is filled, i
+    io_rw_32 shiftctrl;
+
+    _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR
+    // Current instruction address of state machine 0
+    // 0x0000001f [4:0]   : SM0_ADDR (0)
+    io_ro_32 addr;
+
+    _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR
+    // Read to see the instruction currently addressed by state machine 0's program counter
+    // 0x0000ffff [15:0]  : SM0_INSTR (0)
+    io_rw_32 instr;
+
+    _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL
+    // State machine pin control
+    // 0xe0000000 [31:29] : SIDESET_COUNT (0): The number of MSBs of the Delay/Side-set instruction field which are used...
+    // 0x1c000000 [28:26] : SET_COUNT (0x5): The number of pins asserted by a SET
+    // 0x03f00000 [25:20] : OUT_COUNT (0): The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction
+    // 0x000f8000 [19:15] : IN_BASE (0): The pin which is mapped to the least-significant bit of a state machine's IN data bus
+    // 0x00007c00 [14:10] : SIDESET_BASE (0): The lowest-numbered pin that will be affected by a side-set operation
+    // 0x000003e0 [9:5]   : SET_BASE (0): The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction
+    // 0x0000001f [4:0]   : OUT_BASE (0): The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV...
+    io_rw_32 pinctrl;
+} pio_sm_hw_t;
+
+typedef struct {
+    _REG_(PIO_CTRL_OFFSET) // PIO_CTRL
+    // PIO control register
+    // 0x00000f00 [11:8]  : CLKDIV_RESTART (0): Restart a state machine's clock divider from an initial phase of 0
+    // 0x000000f0 [7:4]   : SM_RESTART (0): Write 1 to instantly clear internal SM state which may be otherwise difficult...
+    // 0x0000000f [3:0]   : SM_ENABLE (0): Enable/disable each of the four state machines by writing 1/0 to each of these four bits
+    io_rw_32 ctrl;
+
+    _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT
+    // FIFO status register
+    // 0x0f000000 [27:24] : TXEMPTY (0xf): State machine TX FIFO is empty
+    // 0x000f0000 [19:16] : TXFULL (0): State machine TX FIFO is full
+    // 0x00000f00 [11:8]  : RXEMPTY (0xf): State machine RX FIFO is empty
+    // 0x0000000f [3:0]   : RXFULL (0): State machine RX FIFO is full
+    io_ro_32 fstat;
+
+    _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG
+    // FIFO debug register
+    // 0x0f000000 [27:24] : TXSTALL (0): State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with...
+    // 0x000f0000 [19:16] : TXOVER (0): TX FIFO overflow (i
+    // 0x00000f00 [11:8]  : RXUNDER (0): RX FIFO underflow (i
+    // 0x0000000f [3:0]   : RXSTALL (0): State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with...
+    io_rw_32 fdebug;
+
+    _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL
+    // FIFO levels
+    // 0xf0000000 [31:28] : RX3 (0)
+    // 0x0f000000 [27:24] : TX3 (0)
+    // 0x00f00000 [23:20] : RX2 (0)
+    // 0x000f0000 [19:16] : TX2 (0)
+    // 0x0000f000 [15:12] : RX1 (0)
+    // 0x00000f00 [11:8]  : TX1 (0)
+    // 0x000000f0 [7:4]   : RX0 (0)
+    // 0x0000000f [3:0]   : TX0 (0)
+    io_ro_32 flevel;
+
+    _REG_(PIO_TXF0_OFFSET) // PIO_TXF0
+    // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes)
+    //
+    // Direct write access to the TX FIFO for this state machine
+    io_wo_32 txf[NUM_PIO_STATE_MACHINES]; // 4
+
+    _REG_(PIO_RXF0_OFFSET) // PIO_RXF0
+    // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes)
+    //
+    // Direct read access to the RX FIFO for this state machine
+    io_ro_32 rxf[NUM_PIO_STATE_MACHINES]; // 4
+
+    _REG_(PIO_IRQ_OFFSET) // PIO_IRQ
+    // State machine IRQ flags register
+    // 0x000000ff [7:0]   : IRQ (0)
+    io_rw_32 irq;
+
+    _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE
+    // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ
+    // 0x000000ff [7:0]   : IRQ_FORCE (0)
+    io_wo_32 irq_force;
+
+    _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS
+    // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities
+    io_rw_32 input_sync_bypass;
+
+    _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT
+    // Read to sample the pad output values PIO is currently driving to the GPIOs
+    io_ro_32 dbg_padout;
+
+    _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE
+    // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs
+    io_ro_32 dbg_padoe;
+
+    _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO
+    // The PIO hardware has some free parameters that may vary between chip products
+    // 0x003f0000 [21:16] : IMEM_SIZE (0): The size of the instruction memory, measured in units of one instruction
+    // 0x00000f00 [11:8]  : SM_COUNT (0): The number of state machines this PIO instance is equipped with
+    // 0x0000003f [5:0]   : FIFO_DEPTH (0): The depth of the state machine TX/RX FIFOs, measured in words
+    io_ro_32 dbg_cfginfo;
+
+    _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0
+    // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes)
+    //
+    // Write-only access to instruction memory location 0
+    // 0x0000ffff [15:0]  : INSTR_MEM0 (0)
+    io_wo_32 instr_mem[PIO_INSTRUCTION_COUNT]; // 32
+
+    pio_sm_hw_t sm[NUM_PIO_STATE_MACHINES]; // 4
+
+    _REG_(PIO_INTR_OFFSET) // PIO_INTR
+    // Raw Interrupts
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
+    io_ro_32 intr;
+
+    _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE
+    // Interrupt Enable for irq0
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
+    io_rw_32 inte0;
+
+    _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF
+    // Interrupt Force for irq0
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
+    io_rw_32 intf0;
+
+    _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS
+    // Interrupt status after masking & forcing for irq0
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
+    io_ro_32 ints0;
+
+    _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE
+    // Interrupt Enable for irq1
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
+    io_rw_32 inte1;
+
+    _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF
+    // Interrupt Force for irq1
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
+    io_rw_32 intf1;
+
+    _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS
+    // Interrupt status after masking & forcing for irq1
+    // 0x00000800 [11]    : SM3 (0)
+    // 0x00000400 [10]    : SM2 (0)
+    // 0x00000200 [9]     : SM1 (0)
+    // 0x00000100 [8]     : SM0 (0)
+    // 0x00000080 [7]     : SM3_TXNFULL (0)
+    // 0x00000040 [6]     : SM2_TXNFULL (0)
+    // 0x00000020 [5]     : SM1_TXNFULL (0)
+    // 0x00000010 [4]     : SM0_TXNFULL (0)
+    // 0x00000008 [3]     : SM3_RXNEMPTY (0)
+    // 0x00000004 [2]     : SM2_RXNEMPTY (0)
+    // 0x00000002 [1]     : SM1_RXNEMPTY (0)
+    // 0x00000001 [0]     : SM0_RXNEMPTY (0)
+    io_ro_32 ints1;
+} pio_hw_t;
+
+#define pio0_hw ((pio_hw_t *const)PIO0_BASE)
+#define pio1_hw ((pio_hw_t *const)PIO1_BASE)
+
+static_assert( NUM_PIO_STATE_MACHINES == 4, "");
+static_assert( PIO_INSTRUCTION_COUNT == 32, "");
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/pll.h b/src/rp2040/hardware_structs/include/hardware/structs/pll.h
new file mode 100644
index 0000000..5a506e3
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/pll.h
@@ -0,0 +1,56 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_PLL_H
+#define _HARDWARE_STRUCTS_PLL_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/pll.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pll
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/pll.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+/// \tag::pll_hw[]
+typedef struct {
+    _REG_(PLL_CS_OFFSET) // PLL_CS
+    // Control and Status
+    // 0x80000000 [31]    : LOCK (0): PLL is locked
+    // 0x00000100 [8]     : BYPASS (0): Passes the reference clock to the output instead of the divided VCO
+    // 0x0000003f [5:0]   : REFDIV (1): Divides the PLL input reference clock
+    io_rw_32 cs;
+
+    _REG_(PLL_PWR_OFFSET) // PLL_PWR
+    // Controls the PLL power modes
+    // 0x00000020 [5]     : VCOPD (1): PLL VCO powerdown
+    // 0x00000008 [3]     : POSTDIVPD (1): PLL post divider powerdown
+    // 0x00000004 [2]     : DSMPD (1): PLL DSM powerdown
+    // 0x00000001 [0]     : PD (1): PLL powerdown
+    io_rw_32 pwr;
+
+    _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT
+    // Feedback divisor
+    // 0x00000fff [11:0]  : FBDIV_INT (0): see ctrl reg description for constraints
+    io_rw_32 fbdiv_int;
+
+    _REG_(PLL_PRIM_OFFSET) // PLL_PRIM
+    // Controls the PLL post dividers for the primary output
+    // 0x00070000 [18:16] : POSTDIV1 (0x7): divide by 1-7
+    // 0x00007000 [14:12] : POSTDIV2 (0x7): divide by 1-7
+    io_rw_32 prim;
+} pll_hw_t;
+
+#define pll_sys_hw ((pll_hw_t *const)PLL_SYS_BASE)
+#define pll_usb_hw ((pll_hw_t *const)PLL_USB_BASE)
+/// \end::pll_hw[]
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/psm.h b/src/rp2040/hardware_structs/include/hardware/structs/psm.h
new file mode 100644
index 0000000..cdfb2e3
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/psm.h
@@ -0,0 +1,111 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_PSM_H
+#define _HARDWARE_STRUCTS_PSM_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/psm.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_psm
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/psm.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON
+    // Force block out of reset (i
+    // 0x00010000 [16]    : proc1 (0)
+    // 0x00008000 [15]    : proc0 (0)
+    // 0x00004000 [14]    : sio (0)
+    // 0x00002000 [13]    : vreg_and_chip_reset (0)
+    // 0x00001000 [12]    : xip (0)
+    // 0x00000800 [11]    : sram5 (0)
+    // 0x00000400 [10]    : sram4 (0)
+    // 0x00000200 [9]     : sram3 (0)
+    // 0x00000100 [8]     : sram2 (0)
+    // 0x00000080 [7]     : sram1 (0)
+    // 0x00000040 [6]     : sram0 (0)
+    // 0x00000020 [5]     : rom (0)
+    // 0x00000010 [4]     : busfabric (0)
+    // 0x00000008 [3]     : resets (0)
+    // 0x00000004 [2]     : clocks (0)
+    // 0x00000002 [1]     : xosc (0)
+    // 0x00000001 [0]     : rosc (0)
+    io_rw_32 frce_on;
+
+    _REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF
+    // Force into reset (i
+    // 0x00010000 [16]    : proc1 (0)
+    // 0x00008000 [15]    : proc0 (0)
+    // 0x00004000 [14]    : sio (0)
+    // 0x00002000 [13]    : vreg_and_chip_reset (0)
+    // 0x00001000 [12]    : xip (0)
+    // 0x00000800 [11]    : sram5 (0)
+    // 0x00000400 [10]    : sram4 (0)
+    // 0x00000200 [9]     : sram3 (0)
+    // 0x00000100 [8]     : sram2 (0)
+    // 0x00000080 [7]     : sram1 (0)
+    // 0x00000040 [6]     : sram0 (0)
+    // 0x00000020 [5]     : rom (0)
+    // 0x00000010 [4]     : busfabric (0)
+    // 0x00000008 [3]     : resets (0)
+    // 0x00000004 [2]     : clocks (0)
+    // 0x00000002 [1]     : xosc (0)
+    // 0x00000001 [0]     : rosc (0)
+    io_rw_32 frce_off;
+
+    _REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL
+    // Set to 1 if this peripheral should be reset when the watchdog fires
+    // 0x00010000 [16]    : proc1 (0)
+    // 0x00008000 [15]    : proc0 (0)
+    // 0x00004000 [14]    : sio (0)
+    // 0x00002000 [13]    : vreg_and_chip_reset (0)
+    // 0x00001000 [12]    : xip (0)
+    // 0x00000800 [11]    : sram5 (0)
+    // 0x00000400 [10]    : sram4 (0)
+    // 0x00000200 [9]     : sram3 (0)
+    // 0x00000100 [8]     : sram2 (0)
+    // 0x00000080 [7]     : sram1 (0)
+    // 0x00000040 [6]     : sram0 (0)
+    // 0x00000020 [5]     : rom (0)
+    // 0x00000010 [4]     : busfabric (0)
+    // 0x00000008 [3]     : resets (0)
+    // 0x00000004 [2]     : clocks (0)
+    // 0x00000002 [1]     : xosc (0)
+    // 0x00000001 [0]     : rosc (0)
+    io_rw_32 wdsel;
+
+    _REG_(PSM_DONE_OFFSET) // PSM_DONE
+    // Indicates the peripheral's registers are ready to access
+    // 0x00010000 [16]    : proc1 (0)
+    // 0x00008000 [15]    : proc0 (0)
+    // 0x00004000 [14]    : sio (0)
+    // 0x00002000 [13]    : vreg_and_chip_reset (0)
+    // 0x00001000 [12]    : xip (0)
+    // 0x00000800 [11]    : sram5 (0)
+    // 0x00000400 [10]    : sram4 (0)
+    // 0x00000200 [9]     : sram3 (0)
+    // 0x00000100 [8]     : sram2 (0)
+    // 0x00000080 [7]     : sram1 (0)
+    // 0x00000040 [6]     : sram0 (0)
+    // 0x00000020 [5]     : rom (0)
+    // 0x00000010 [4]     : busfabric (0)
+    // 0x00000008 [3]     : resets (0)
+    // 0x00000004 [2]     : clocks (0)
+    // 0x00000002 [1]     : xosc (0)
+    // 0x00000001 [0]     : rosc (0)
+    io_ro_32 done;
+} psm_hw_t;
+
+#define psm_hw ((psm_hw_t *const)PSM_BASE)
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/pwm.h b/src/rp2040/hardware_structs/include/hardware/structs/pwm.h
new file mode 100644
index 0000000..fd9a75c
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/pwm.h
@@ -0,0 +1,126 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_PWM_H
+#define _HARDWARE_STRUCTS_PWM_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/pwm.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pwm
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct pwm_slice_hw {
+    _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR
+    // Control and status register
+    // 0x00000080 [7]     : PH_ADV (0): Advance the phase of the counter by 1 count, while it is running
+    // 0x00000040 [6]     : PH_RET (0): Retard the phase of the counter by 1 count, while it is running
+    // 0x00000030 [5:4]   : DIVMODE (0)
+    // 0x00000008 [3]     : B_INV (0): Invert output B
+    // 0x00000004 [2]     : A_INV (0): Invert output A
+    // 0x00000002 [1]     : PH_CORRECT (0): 1: Enable phase-correct modulation
+    // 0x00000001 [0]     : EN (0): Enable the PWM channel
+    io_rw_32 csr;
+
+    _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV
+    // INT and FRAC form a fixed-point fractional number
+    // 0x00000ff0 [11:4]  : INT (1)
+    // 0x0000000f [3:0]   : FRAC (0)
+    io_rw_32 div;
+
+    _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR
+    // Direct access to the PWM counter
+    // 0x0000ffff [15:0]  : CH0_CTR (0)
+    io_rw_32 ctr;
+
+    _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC
+    // Counter compare values
+    // 0xffff0000 [31:16] : B (0)
+    // 0x0000ffff [15:0]  : A (0)
+    io_rw_32 cc;
+
+    _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP
+    // Counter wrap value
+    // 0x0000ffff [15:0]  : CH0_TOP (0xffff)
+    io_rw_32 top;
+} pwm_slice_hw_t;
+
+typedef struct {
+    pwm_slice_hw_t slice[NUM_PWM_SLICES]; // 8
+
+    _REG_(PWM_EN_OFFSET) // PWM_EN
+    // This register aliases the CSR_EN bits for all channels
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
+    io_rw_32 en;
+
+    _REG_(PWM_INTR_OFFSET) // PWM_INTR
+    // Raw Interrupts
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
+    io_rw_32 intr;
+
+    _REG_(PWM_INTE_OFFSET) // PWM_INTE
+    // Interrupt Enable
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
+    io_rw_32 inte;
+
+    _REG_(PWM_INTF_OFFSET) // PWM_INTF
+    // Interrupt Force
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
+    io_rw_32 intf;
+
+    _REG_(PWM_INTS_OFFSET) // PWM_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000080 [7]     : CH7 (0)
+    // 0x00000040 [6]     : CH6 (0)
+    // 0x00000020 [5]     : CH5 (0)
+    // 0x00000010 [4]     : CH4 (0)
+    // 0x00000008 [3]     : CH3 (0)
+    // 0x00000004 [2]     : CH2 (0)
+    // 0x00000002 [1]     : CH1 (0)
+    // 0x00000001 [0]     : CH0 (0)
+    io_ro_32 ints;
+} pwm_hw_t;
+
+#define pwm_hw ((pwm_hw_t *const)PWM_BASE)
+
+static_assert( NUM_PWM_SLICES == 8, "");
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/resets.h b/src/rp2040/hardware_structs/include/hardware/structs/resets.h
new file mode 100644
index 0000000..bc1c10c
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/resets.h
@@ -0,0 +1,116 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_RESETS_H
+#define _HARDWARE_STRUCTS_RESETS_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/resets.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_resets
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/resets.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+/// \tag::resets_hw[]
+typedef struct {
+    _REG_(RESETS_RESET_OFFSET) // RESETS_RESET
+    // Reset control
+    // 0x01000000 [24]    : usbctrl (1)
+    // 0x00800000 [23]    : uart1 (1)
+    // 0x00400000 [22]    : uart0 (1)
+    // 0x00200000 [21]    : timer (1)
+    // 0x00100000 [20]    : tbman (1)
+    // 0x00080000 [19]    : sysinfo (1)
+    // 0x00040000 [18]    : syscfg (1)
+    // 0x00020000 [17]    : spi1 (1)
+    // 0x00010000 [16]    : spi0 (1)
+    // 0x00008000 [15]    : rtc (1)
+    // 0x00004000 [14]    : pwm (1)
+    // 0x00002000 [13]    : pll_usb (1)
+    // 0x00001000 [12]    : pll_sys (1)
+    // 0x00000800 [11]    : pio1 (1)
+    // 0x00000400 [10]    : pio0 (1)
+    // 0x00000200 [9]     : pads_qspi (1)
+    // 0x00000100 [8]     : pads_bank0 (1)
+    // 0x00000080 [7]     : jtag (1)
+    // 0x00000040 [6]     : io_qspi (1)
+    // 0x00000020 [5]     : io_bank0 (1)
+    // 0x00000010 [4]     : i2c1 (1)
+    // 0x00000008 [3]     : i2c0 (1)
+    // 0x00000004 [2]     : dma (1)
+    // 0x00000002 [1]     : busctrl (1)
+    // 0x00000001 [0]     : adc (1)
+    io_rw_32 reset;
+
+    _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL
+    // Watchdog select
+    // 0x01000000 [24]    : usbctrl (0)
+    // 0x00800000 [23]    : uart1 (0)
+    // 0x00400000 [22]    : uart0 (0)
+    // 0x00200000 [21]    : timer (0)
+    // 0x00100000 [20]    : tbman (0)
+    // 0x00080000 [19]    : sysinfo (0)
+    // 0x00040000 [18]    : syscfg (0)
+    // 0x00020000 [17]    : spi1 (0)
+    // 0x00010000 [16]    : spi0 (0)
+    // 0x00008000 [15]    : rtc (0)
+    // 0x00004000 [14]    : pwm (0)
+    // 0x00002000 [13]    : pll_usb (0)
+    // 0x00001000 [12]    : pll_sys (0)
+    // 0x00000800 [11]    : pio1 (0)
+    // 0x00000400 [10]    : pio0 (0)
+    // 0x00000200 [9]     : pads_qspi (0)
+    // 0x00000100 [8]     : pads_bank0 (0)
+    // 0x00000080 [7]     : jtag (0)
+    // 0x00000040 [6]     : io_qspi (0)
+    // 0x00000020 [5]     : io_bank0 (0)
+    // 0x00000010 [4]     : i2c1 (0)
+    // 0x00000008 [3]     : i2c0 (0)
+    // 0x00000004 [2]     : dma (0)
+    // 0x00000002 [1]     : busctrl (0)
+    // 0x00000001 [0]     : adc (0)
+    io_rw_32 wdsel;
+
+    _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE
+    // Reset done
+    // 0x01000000 [24]    : usbctrl (0)
+    // 0x00800000 [23]    : uart1 (0)
+    // 0x00400000 [22]    : uart0 (0)
+    // 0x00200000 [21]    : timer (0)
+    // 0x00100000 [20]    : tbman (0)
+    // 0x00080000 [19]    : sysinfo (0)
+    // 0x00040000 [18]    : syscfg (0)
+    // 0x00020000 [17]    : spi1 (0)
+    // 0x00010000 [16]    : spi0 (0)
+    // 0x00008000 [15]    : rtc (0)
+    // 0x00004000 [14]    : pwm (0)
+    // 0x00002000 [13]    : pll_usb (0)
+    // 0x00001000 [12]    : pll_sys (0)
+    // 0x00000800 [11]    : pio1 (0)
+    // 0x00000400 [10]    : pio0 (0)
+    // 0x00000200 [9]     : pads_qspi (0)
+    // 0x00000100 [8]     : pads_bank0 (0)
+    // 0x00000080 [7]     : jtag (0)
+    // 0x00000040 [6]     : io_qspi (0)
+    // 0x00000020 [5]     : io_bank0 (0)
+    // 0x00000010 [4]     : i2c1 (0)
+    // 0x00000008 [3]     : i2c0 (0)
+    // 0x00000004 [2]     : dma (0)
+    // 0x00000002 [1]     : busctrl (0)
+    // 0x00000001 [0]     : adc (0)
+    io_ro_32 reset_done;
+} resets_hw_t;
+
+#define resets_hw ((resets_hw_t *const)RESETS_BASE)
+/// \end::resets_hw[]
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/rosc.h b/src/rp2040/hardware_structs/include/hardware/structs/rosc.h
new file mode 100644
index 0000000..114c602
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/rosc.h
@@ -0,0 +1,86 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_ROSC_H
+#define _HARDWARE_STRUCTS_ROSC_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/rosc.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rosc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL
+    // Ring Oscillator control
+    // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to ENABLE
+    // 0x00000fff [11:0]  : FREQ_RANGE (0xaa0): Controls the number of delay stages in the ROSC ring
+    io_rw_32 ctrl;
+
+    _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA
+    // The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage
+    // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings
+    // 0x00007000 [14:12] : DS3 (0): Stage 3 drive strength
+    // 0x00000700 [10:8]  : DS2 (0): Stage 2 drive strength
+    // 0x00000070 [6:4]   : DS1 (0): Stage 1 drive strength
+    // 0x00000007 [2:0]   : DS0 (0): Stage 0 drive strength
+    io_rw_32 freqa;
+
+    _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB
+    // For a detailed description see freqa register
+    // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings
+    // 0x00007000 [14:12] : DS7 (0): Stage 7 drive strength
+    // 0x00000700 [10:8]  : DS6 (0): Stage 6 drive strength
+    // 0x00000070 [6:4]   : DS5 (0): Stage 5 drive strength
+    // 0x00000007 [2:0]   : DS4 (0): Stage 4 drive strength
+    io_rw_32 freqb;
+
+    _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT
+    // Ring Oscillator pause control
+    io_rw_32 dormant;
+
+    _REG_(ROSC_DIV_OFFSET) // ROSC_DIV
+    // Controls the output divider
+    // 0x00000fff [11:0]  : DIV (0): set to 0xaa0 + div where
+    io_rw_32 div;
+
+    _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE
+    // Controls the phase shifted output
+    // 0x00000ff0 [11:4]  : PASSWD (0): set to 0xaa
+    // 0x00000008 [3]     : ENABLE (1): enable the phase-shifted output
+    // 0x00000004 [2]     : FLIP (0): invert the phase-shifted output
+    // 0x00000003 [1:0]   : SHIFT (0): phase shift the phase-shifted output by SHIFT input clocks
+    io_rw_32 phase;
+
+    _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS
+    // Ring Oscillator Status
+    // 0x80000000 [31]    : STABLE (0): Oscillator is running and stable
+    // 0x01000000 [24]    : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or...
+    // 0x00010000 [16]    : DIV_RUNNING (0): post-divider is running
+    // 0x00001000 [12]    : ENABLED (0): Oscillator is enabled but not necessarily running and stable
+    io_rw_32 status;
+
+    _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT
+    // This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or...
+    // 0x00000001 [0]     : RANDOMBIT (1)
+    io_ro_32 randombit;
+
+    _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT
+    // A down counter running at the ROSC frequency which counts to zero and stops
+    // 0x000000ff [7:0]   : COUNT (0)
+    io_rw_32 count;
+} rosc_hw_t;
+
+#define rosc_hw ((rosc_hw_t *const)ROSC_BASE)
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/rtc.h b/src/rp2040/hardware_structs/include/hardware/structs/rtc.h
new file mode 100644
index 0000000..794a0e0
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/rtc.h
@@ -0,0 +1,114 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_RTC_H
+#define _HARDWARE_STRUCTS_RTC_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/rtc.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rtc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/rtc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(RTC_CLKDIV_M1_OFFSET) // RTC_CLKDIV_M1
+    // Divider minus 1 for the 1 second counter
+    // 0x0000ffff [15:0]  : CLKDIV_M1 (0)
+    io_rw_32 clkdiv_m1;
+
+    _REG_(RTC_SETUP_0_OFFSET) // RTC_SETUP_0
+    // RTC setup register 0
+    // 0x00fff000 [23:12] : YEAR (0): Year
+    // 0x00000f00 [11:8]  : MONTH (0): Month (1
+    // 0x0000001f [4:0]   : DAY (0): Day of the month (1
+    io_rw_32 setup_0;
+
+    _REG_(RTC_SETUP_1_OFFSET) // RTC_SETUP_1
+    // RTC setup register 1
+    // 0x07000000 [26:24] : DOTW (0): Day of the week: 1-Monday
+    // 0x001f0000 [20:16] : HOUR (0): Hours
+    // 0x00003f00 [13:8]  : MIN (0): Minutes
+    // 0x0000003f [5:0]   : SEC (0): Seconds
+    io_rw_32 setup_1;
+
+    _REG_(RTC_CTRL_OFFSET) // RTC_CTRL
+    // RTC Control and status
+    // 0x00000100 [8]     : FORCE_NOTLEAPYEAR (0): If set, leapyear is forced off
+    // 0x00000010 [4]     : LOAD (0): Load RTC
+    // 0x00000002 [1]     : RTC_ACTIVE (0): RTC enabled (running)
+    // 0x00000001 [0]     : RTC_ENABLE (0): Enable RTC
+    io_rw_32 ctrl;
+
+    _REG_(RTC_IRQ_SETUP_0_OFFSET) // RTC_IRQ_SETUP_0
+    // Interrupt setup register 0
+    // 0x20000000 [29]    : MATCH_ACTIVE (0)
+    // 0x10000000 [28]    : MATCH_ENA (0): Global match enable
+    // 0x04000000 [26]    : YEAR_ENA (0): Enable year matching
+    // 0x02000000 [25]    : MONTH_ENA (0): Enable month matching
+    // 0x01000000 [24]    : DAY_ENA (0): Enable day matching
+    // 0x00fff000 [23:12] : YEAR (0): Year
+    // 0x00000f00 [11:8]  : MONTH (0): Month (1
+    // 0x0000001f [4:0]   : DAY (0): Day of the month (1
+    io_rw_32 irq_setup_0;
+
+    _REG_(RTC_IRQ_SETUP_1_OFFSET) // RTC_IRQ_SETUP_1
+    // Interrupt setup register 1
+    // 0x80000000 [31]    : DOTW_ENA (0): Enable day of the week matching
+    // 0x40000000 [30]    : HOUR_ENA (0): Enable hour matching
+    // 0x20000000 [29]    : MIN_ENA (0): Enable minute matching
+    // 0x10000000 [28]    : SEC_ENA (0): Enable second matching
+    // 0x07000000 [26:24] : DOTW (0): Day of the week
+    // 0x001f0000 [20:16] : HOUR (0): Hours
+    // 0x00003f00 [13:8]  : MIN (0): Minutes
+    // 0x0000003f [5:0]   : SEC (0): Seconds
+    io_rw_32 irq_setup_1;
+
+    _REG_(RTC_RTC_1_OFFSET) // RTC_RTC_1
+    // RTC register 1
+    // 0x00fff000 [23:12] : YEAR (0): Year
+    // 0x00000f00 [11:8]  : MONTH (0): Month (1
+    // 0x0000001f [4:0]   : DAY (0): Day of the month (1
+    io_ro_32 rtc_1;
+
+    _REG_(RTC_RTC_0_OFFSET) // RTC_RTC_0
+    // RTC register 0
+    // 0x07000000 [26:24] : DOTW (0): Day of the week
+    // 0x001f0000 [20:16] : HOUR (0): Hours
+    // 0x00003f00 [13:8]  : MIN (0): Minutes
+    // 0x0000003f [5:0]   : SEC (0): Seconds
+    io_ro_32 rtc_0;
+
+    _REG_(RTC_INTR_OFFSET) // RTC_INTR
+    // Raw Interrupts
+    // 0x00000001 [0]     : RTC (0)
+    io_ro_32 intr;
+
+    _REG_(RTC_INTE_OFFSET) // RTC_INTE
+    // Interrupt Enable
+    // 0x00000001 [0]     : RTC (0)
+    io_rw_32 inte;
+
+    _REG_(RTC_INTF_OFFSET) // RTC_INTF
+    // Interrupt Force
+    // 0x00000001 [0]     : RTC (0)
+    io_rw_32 intf;
+
+    _REG_(RTC_INTS_OFFSET) // RTC_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000001 [0]     : RTC (0)
+    io_ro_32 ints;
+} rtc_hw_t;
+
+#define rtc_hw ((rtc_hw_t *const)RTC_BASE)
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/scb.h b/src/rp2040/hardware_structs/include/hardware/structs/scb.h
new file mode 100644
index 0000000..42569c7
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/scb.h
@@ -0,0 +1,69 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_SCB_H
+#define _HARDWARE_STRUCTS_SCB_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/m0plus.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID
+    // Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor...
+    // 0xff000000 [31:24] : IMPLEMENTER (0x41): Implementor code: 0x41 = ARM
+    // 0x00f00000 [23:20] : VARIANT (0): Major revision number n in the rnpm revision status:
+    // 0x000f0000 [19:16] : ARCHITECTURE (0xc): Constant that defines the architecture of the processor:
+    // 0x0000fff0 [15:4]  : PARTNO (0xc60): Number of processor within family: 0xC60 = Cortex-M0+
+    // 0x0000000f [3:0]   : REVISION (1): Minor revision number m in the rnpm revision status:
+    io_ro_32 cpuid;
+
+    _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR
+    // Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending...
+    // 0x80000000 [31]    : NMIPENDSET (0): Setting this bit will activate an NMI
+    // 0x10000000 [28]    : PENDSVSET (0): PendSV set-pending bit
+    // 0x08000000 [27]    : PENDSVCLR (0): PendSV clear-pending bit
+    // 0x04000000 [26]    : PENDSTSET (0): SysTick exception set-pending bit
+    // 0x02000000 [25]    : PENDSTCLR (0): SysTick exception clear-pending bit
+    // 0x00800000 [23]    : ISRPREEMPT (0): The system can only access this bit when the core is halted
+    // 0x00400000 [22]    : ISRPENDING (0): External interrupt pending flag
+    // 0x001ff000 [20:12] : VECTPENDING (0): Indicates the exception number for the highest priority pending exception: 0 =...
+    // 0x000001ff [8:0]   : VECTACTIVE (0): Active exception number field
+    io_rw_32 icsr;
+
+    _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR
+    // The VTOR holds the vector table offset address
+    // 0xffffff00 [31:8]  : TBLOFF (0): Bits [31:8] of the indicate the vector table offset address
+    io_rw_32 vtor;
+
+    _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR
+    // Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state...
+    // 0xffff0000 [31:16] : VECTKEY (0): Register key:
+    // 0x00008000 [15]    : ENDIANESS (0): Data endianness implemented:
+    // 0x00000004 [2]     : SYSRESETREQ (0): Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be...
+    // 0x00000002 [1]     : VECTCLRACTIVE (0): Clears all active state information for fixed and configurable exceptions
+    io_rw_32 aircr;
+
+    _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR
+    // System Control Register
+    // 0x00000010 [4]     : SEVONPEND (0): Send Event on Pending bit:
+    // 0x00000004 [2]     : SLEEPDEEP (0): Controls whether the processor uses sleep or deep sleep as its low power mode:
+    // 0x00000002 [1]     : SLEEPONEXIT (0): Indicates sleep-on-exit when returning from Handler mode to Thread mode:
+    io_rw_32 scr;
+} armv6m_scb_t;
+
+#define scb_hw ((armv6m_scb_t *const)(PPB_BASE + M0PLUS_CPUID_OFFSET))
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/sio.h b/src/rp2040/hardware_structs/include/hardware/structs/sio.h
new file mode 100644
index 0000000..00b7e7e
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/sio.h
@@ -0,0 +1,176 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_SIO_H
+#define _HARDWARE_STRUCTS_SIO_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/sio.h"
+#include "hardware/structs/interp.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(SIO_CPUID_OFFSET) // SIO_CPUID
+    // Processor core identifier
+    io_ro_32 cpuid;
+
+    _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN
+    // Input value for GPIO pins
+    // 0x3fffffff [29:0]  : GPIO_IN (0): Input value for GPIO0
+    io_ro_32 gpio_in;
+
+    _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN
+    // Input value for QSPI pins
+    // 0x0000003f [5:0]   : GPIO_HI_IN (0): Input value on QSPI IO in order 0
+    io_ro_32 gpio_hi_in;
+
+    uint32_t _pad0;
+
+    _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT
+    // GPIO output value
+    // 0x3fffffff [29:0]  : GPIO_OUT (0): Set output level (1/0 -> high/low) for GPIO0
+    io_rw_32 gpio_out;
+
+    _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET
+    // GPIO output value set
+    // 0x3fffffff [29:0]  : GPIO_OUT_SET (0): Perform an atomic bit-set on GPIO_OUT, i
+    io_wo_32 gpio_set;
+
+    _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR
+    // GPIO output value clear
+    // 0x3fffffff [29:0]  : GPIO_OUT_CLR (0): Perform an atomic bit-clear on GPIO_OUT, i
+    io_wo_32 gpio_clr;
+
+    _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR
+    // GPIO output value XOR
+    // 0x3fffffff [29:0]  : GPIO_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_OUT, i
+    io_wo_32 gpio_togl;
+
+    _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE
+    // GPIO output enable
+    // 0x3fffffff [29:0]  : GPIO_OE (0): Set output enable (1/0 -> output/input) for GPIO0
+    io_rw_32 gpio_oe;
+
+    _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET
+    // GPIO output enable set
+    // 0x3fffffff [29:0]  : GPIO_OE_SET (0): Perform an atomic bit-set on GPIO_OE, i
+    io_wo_32 gpio_oe_set;
+
+    _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR
+    // GPIO output enable clear
+    // 0x3fffffff [29:0]  : GPIO_OE_CLR (0): Perform an atomic bit-clear on GPIO_OE, i
+    io_wo_32 gpio_oe_clr;
+
+    _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR
+    // GPIO output enable XOR
+    // 0x3fffffff [29:0]  : GPIO_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_OE, i
+    io_wo_32 gpio_oe_togl;
+
+    _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT
+    // QSPI output value
+    // 0x0000003f [5:0]   : GPIO_HI_OUT (0): Set output level (1/0 -> high/low) for QSPI IO0
+    io_rw_32 gpio_hi_out;
+
+    _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET
+    // QSPI output value set
+    // 0x0000003f [5:0]   : GPIO_HI_OUT_SET (0): Perform an atomic bit-set on GPIO_HI_OUT, i
+    io_wo_32 gpio_hi_set;
+
+    _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR
+    // QSPI output value clear
+    // 0x0000003f [5:0]   : GPIO_HI_OUT_CLR (0): Perform an atomic bit-clear on GPIO_HI_OUT, i
+    io_wo_32 gpio_hi_clr;
+
+    _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR
+    // QSPI output value XOR
+    // 0x0000003f [5:0]   : GPIO_HI_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OUT, i
+    io_wo_32 gpio_hi_togl;
+
+    _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE
+    // QSPI output enable
+    // 0x0000003f [5:0]   : GPIO_HI_OE (0): Set output enable (1/0 -> output/input) for QSPI IO0
+    io_rw_32 gpio_hi_oe;
+
+    _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET
+    // QSPI output enable set
+    // 0x0000003f [5:0]   : GPIO_HI_OE_SET (0): Perform an atomic bit-set on GPIO_HI_OE, i
+    io_wo_32 gpio_hi_oe_set;
+
+    _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR
+    // QSPI output enable clear
+    // 0x0000003f [5:0]   : GPIO_HI_OE_CLR (0): Perform an atomic bit-clear on GPIO_HI_OE, i
+    io_wo_32 gpio_hi_oe_clr;
+
+    _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR
+    // QSPI output enable XOR
+    // 0x0000003f [5:0]   : GPIO_HI_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OE, i
+    io_wo_32 gpio_hi_oe_togl;
+
+    _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST
+    // Status register for inter-core FIFOs (mailboxes)
+    // 0x00000008 [3]     : ROE (0): Sticky flag indicating the RX FIFO was read when empty
+    // 0x00000004 [2]     : WOF (0): Sticky flag indicating the TX FIFO was written when full
+    // 0x00000002 [1]     : RDY (1): Value is 1 if this core's TX FIFO is not full (i
+    // 0x00000001 [0]     : VLD (0): Value is 1 if this core's RX FIFO is not empty (i
+    io_rw_32 fifo_st;
+
+    _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR
+    // Write access to this core's TX FIFO
+    io_wo_32 fifo_wr;
+
+    _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD
+    // Read access to this core's RX FIFO
+    io_ro_32 fifo_rd;
+
+    _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST
+    // Spinlock state
+    io_ro_32 spinlock_st;
+
+    _REG_(SIO_DIV_UDIVIDEND_OFFSET) // SIO_DIV_UDIVIDEND
+    // Divider unsigned dividend
+    io_rw_32 div_udividend;
+
+    _REG_(SIO_DIV_UDIVISOR_OFFSET) // SIO_DIV_UDIVISOR
+    // Divider unsigned divisor
+    io_rw_32 div_udivisor;
+
+    _REG_(SIO_DIV_SDIVIDEND_OFFSET) // SIO_DIV_SDIVIDEND
+    // Divider signed dividend
+    io_rw_32 div_sdividend;
+
+    _REG_(SIO_DIV_SDIVISOR_OFFSET) // SIO_DIV_SDIVISOR
+    // Divider signed divisor
+    io_rw_32 div_sdivisor;
+
+    _REG_(SIO_DIV_QUOTIENT_OFFSET) // SIO_DIV_QUOTIENT
+    // Divider result quotient
+    io_rw_32 div_quotient;
+
+    _REG_(SIO_DIV_REMAINDER_OFFSET) // SIO_DIV_REMAINDER
+    // Divider result remainder
+    io_rw_32 div_remainder;
+
+    _REG_(SIO_DIV_CSR_OFFSET) // SIO_DIV_CSR
+    // Control and status register for divider
+    // 0x00000002 [1]     : DIRTY (0): Changes to 1 when any register is written, and back to 0 when QUOTIENT is read
+    // 0x00000001 [0]     : READY (1): Reads as 0 when a calculation is in progress, 1 otherwise
+    io_ro_32 div_csr;
+    uint32_t _pad1;
+    interp_hw_t interp[2];
+} sio_hw_t;
+
+#define sio_hw ((sio_hw_t *const)SIO_BASE)
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/spi.h b/src/rp2040/hardware_structs/include/hardware/structs/spi.h
new file mode 100644
index 0000000..f7fffb8
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/spi.h
@@ -0,0 +1,100 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_SPI_H
+#define _HARDWARE_STRUCTS_SPI_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/spi.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_spi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/spi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0
+    // Control register 0, SSPCR0 on page 3-4
+    // 0x0000ff00 [15:8]  : SCR (0): Serial clock rate
+    // 0x00000080 [7]     : SPH (0): SSPCLKOUT phase, applicable to Motorola SPI frame format only
+    // 0x00000040 [6]     : SPO (0): SSPCLKOUT polarity, applicable to Motorola SPI frame format only
+    // 0x00000030 [5:4]   : FRF (0): Frame format: 00 Motorola SPI frame format
+    // 0x0000000f [3:0]   : DSS (0): Data Size Select: 0000 Reserved, undefined operation
+    io_rw_32 cr0;
+
+    _REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1
+    // Control register 1, SSPCR1 on page 3-5
+    // 0x00000008 [3]     : SOD (0): Slave-mode output disable
+    // 0x00000004 [2]     : MS (0): Master or slave mode select
+    // 0x00000002 [1]     : SSE (0): Synchronous serial port enable: 0 SSP operation disabled
+    // 0x00000001 [0]     : LBM (0): Loop back mode: 0 Normal serial port operation enabled
+    io_rw_32 cr1;
+
+    _REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR
+    // Data register, SSPDR on page 3-6
+    // 0x0000ffff [15:0]  : DATA (0): Transmit/Receive FIFO: Read Receive FIFO
+    io_rw_32 dr;
+
+    _REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR
+    // Status register, SSPSR on page 3-7
+    // 0x00000010 [4]     : BSY (0): PrimeCell SSP busy flag, RO: 0 SSP is idle
+    // 0x00000008 [3]     : RFF (0): Receive FIFO full, RO: 0 Receive FIFO is not full
+    // 0x00000004 [2]     : RNE (0): Receive FIFO not empty, RO: 0 Receive FIFO is empty
+    // 0x00000002 [1]     : TNF (1): Transmit FIFO not full, RO: 0 Transmit FIFO is full
+    // 0x00000001 [0]     : TFE (1): Transmit FIFO empty, RO: 0 Transmit FIFO is not empty
+    io_ro_32 sr;
+
+    _REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR
+    // Clock prescale register, SSPCPSR on page 3-8
+    // 0x000000ff [7:0]   : CPSDVSR (0): Clock prescale divisor
+    io_rw_32 cpsr;
+
+    _REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC
+    // Interrupt mask set or clear register, SSPIMSC on page 3-9
+    // 0x00000008 [3]     : TXIM (0): Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked
+    // 0x00000004 [2]     : RXIM (0): Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked
+    // 0x00000002 [1]     : RTIM (0): Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout...
+    // 0x00000001 [0]     : RORIM (0): Receive overrun interrupt mask: 0 Receive FIFO written to while full condition...
+    io_rw_32 imsc;
+
+    _REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS
+    // Raw interrupt status register, SSPRIS on page 3-10
+    // 0x00000008 [3]     : TXRIS (1): Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt
+    // 0x00000004 [2]     : RXRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt
+    // 0x00000002 [1]     : RTRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt
+    // 0x00000001 [0]     : RORRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
+    io_ro_32 ris;
+
+    _REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS
+    // Masked interrupt status register, SSPMIS on page 3-11
+    // 0x00000008 [3]     : TXMIS (0): Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
+    // 0x00000004 [2]     : RXMIS (0): Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
+    // 0x00000002 [1]     : RTMIS (0): Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
+    // 0x00000001 [0]     : RORMIS (0): Gives the receive over run masked interrupt status, after masking, of the...
+    io_ro_32 mis;
+
+    _REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR
+    // Interrupt clear register, SSPICR on page 3-11
+    // 0x00000002 [1]     : RTIC (0): Clears the SSPRTINTR interrupt
+    // 0x00000001 [0]     : RORIC (0): Clears the SSPRORINTR interrupt
+    io_rw_32 icr;
+
+    _REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR
+    // DMA control register, SSPDMACR on page 3-12
+    // 0x00000002 [1]     : TXDMAE (0): Transmit DMA Enable
+    // 0x00000001 [0]     : RXDMAE (0): Receive DMA Enable
+    io_rw_32 dmacr;
+} spi_hw_t;
+
+#define spi0_hw ((spi_hw_t *const)SPI0_BASE)
+#define spi1_hw ((spi_hw_t *const)SPI1_BASE)
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/ssi.h b/src/rp2040/hardware_structs/include/hardware/structs/ssi.h
new file mode 100644
index 0000000..0ab18be
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/ssi.h
@@ -0,0 +1,210 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_SSI_H
+#define _HARDWARE_STRUCTS_SSI_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/ssi.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_ssi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/ssi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(SSI_CTRLR0_OFFSET) // SSI_CTRLR0
+    // Control register 0
+    // 0x01000000 [24]    : SSTE (0): Slave select toggle enable
+    // 0x00600000 [22:21] : SPI_FRF (0): SPI frame format
+    // 0x001f0000 [20:16] : DFS_32 (0): Data frame size in 32b transfer mode
+    // 0x0000f000 [15:12] : CFS (0): Control frame size
+    // 0x00000800 [11]    : SRL (0): Shift register loop (test mode)
+    // 0x00000400 [10]    : SLV_OE (0): Slave output enable
+    // 0x00000300 [9:8]   : TMOD (0): Transfer mode
+    // 0x00000080 [7]     : SCPOL (0): Serial clock polarity
+    // 0x00000040 [6]     : SCPH (0): Serial clock phase
+    // 0x00000030 [5:4]   : FRF (0): Frame format
+    // 0x0000000f [3:0]   : DFS (0): Data frame size
+    io_rw_32 ctrlr0;
+
+    _REG_(SSI_CTRLR1_OFFSET) // SSI_CTRLR1
+    // Master Control register 1
+    // 0x0000ffff [15:0]  : NDF (0): Number of data frames
+    io_rw_32 ctrlr1;
+
+    _REG_(SSI_SSIENR_OFFSET) // SSI_SSIENR
+    // SSI Enable
+    // 0x00000001 [0]     : SSI_EN (0): SSI enable
+    io_rw_32 ssienr;
+
+    _REG_(SSI_MWCR_OFFSET) // SSI_MWCR
+    // Microwire Control
+    // 0x00000004 [2]     : MHS (0): Microwire handshaking
+    // 0x00000002 [1]     : MDD (0): Microwire control
+    // 0x00000001 [0]     : MWMOD (0): Microwire transfer mode
+    io_rw_32 mwcr;
+
+    _REG_(SSI_SER_OFFSET) // SSI_SER
+    // Slave enable
+    // 0x00000001 [0]     : SER (0): For each bit:
+    io_rw_32 ser;
+
+    _REG_(SSI_BAUDR_OFFSET) // SSI_BAUDR
+    // Baud rate
+    // 0x0000ffff [15:0]  : SCKDV (0): SSI clock divider
+    io_rw_32 baudr;
+
+    _REG_(SSI_TXFTLR_OFFSET) // SSI_TXFTLR
+    // TX FIFO threshold level
+    // 0x000000ff [7:0]   : TFT (0): Transmit FIFO threshold
+    io_rw_32 txftlr;
+
+    _REG_(SSI_RXFTLR_OFFSET) // SSI_RXFTLR
+    // RX FIFO threshold level
+    // 0x000000ff [7:0]   : RFT (0): Receive FIFO threshold
+    io_rw_32 rxftlr;
+
+    _REG_(SSI_TXFLR_OFFSET) // SSI_TXFLR
+    // TX FIFO level
+    // 0x000000ff [7:0]   : TFTFL (0): Transmit FIFO level
+    io_ro_32 txflr;
+
+    _REG_(SSI_RXFLR_OFFSET) // SSI_RXFLR
+    // RX FIFO level
+    // 0x000000ff [7:0]   : RXTFL (0): Receive FIFO level
+    io_ro_32 rxflr;
+
+    _REG_(SSI_SR_OFFSET) // SSI_SR
+    // Status register
+    // 0x00000040 [6]     : DCOL (0): Data collision error
+    // 0x00000020 [5]     : TXE (0): Transmission error
+    // 0x00000010 [4]     : RFF (0): Receive FIFO full
+    // 0x00000008 [3]     : RFNE (0): Receive FIFO not empty
+    // 0x00000004 [2]     : TFE (0): Transmit FIFO empty
+    // 0x00000002 [1]     : TFNF (0): Transmit FIFO not full
+    // 0x00000001 [0]     : BUSY (0): SSI busy flag
+    io_ro_32 sr;
+
+    _REG_(SSI_IMR_OFFSET) // SSI_IMR
+    // Interrupt mask
+    // 0x00000020 [5]     : MSTIM (0): Multi-master contention interrupt mask
+    // 0x00000010 [4]     : RXFIM (0): Receive FIFO full interrupt mask
+    // 0x00000008 [3]     : RXOIM (0): Receive FIFO overflow interrupt mask
+    // 0x00000004 [2]     : RXUIM (0): Receive FIFO underflow interrupt mask
+    // 0x00000002 [1]     : TXOIM (0): Transmit FIFO overflow interrupt mask
+    // 0x00000001 [0]     : TXEIM (0): Transmit FIFO empty interrupt mask
+    io_rw_32 imr;
+
+    _REG_(SSI_ISR_OFFSET) // SSI_ISR
+    // Interrupt status
+    // 0x00000020 [5]     : MSTIS (0): Multi-master contention interrupt status
+    // 0x00000010 [4]     : RXFIS (0): Receive FIFO full interrupt status
+    // 0x00000008 [3]     : RXOIS (0): Receive FIFO overflow interrupt status
+    // 0x00000004 [2]     : RXUIS (0): Receive FIFO underflow interrupt status
+    // 0x00000002 [1]     : TXOIS (0): Transmit FIFO overflow interrupt status
+    // 0x00000001 [0]     : TXEIS (0): Transmit FIFO empty interrupt status
+    io_ro_32 isr;
+
+    _REG_(SSI_RISR_OFFSET) // SSI_RISR
+    // Raw interrupt status
+    // 0x00000020 [5]     : MSTIR (0): Multi-master contention raw interrupt status
+    // 0x00000010 [4]     : RXFIR (0): Receive FIFO full raw interrupt status
+    // 0x00000008 [3]     : RXOIR (0): Receive FIFO overflow raw interrupt status
+    // 0x00000004 [2]     : RXUIR (0): Receive FIFO underflow raw interrupt status
+    // 0x00000002 [1]     : TXOIR (0): Transmit FIFO overflow raw interrupt status
+    // 0x00000001 [0]     : TXEIR (0): Transmit FIFO empty raw interrupt status
+    io_ro_32 risr;
+
+    _REG_(SSI_TXOICR_OFFSET) // SSI_TXOICR
+    // TX FIFO overflow interrupt clear
+    // 0x00000001 [0]     : TXOICR (0): Clear-on-read transmit FIFO overflow interrupt
+    io_ro_32 txoicr;
+
+    _REG_(SSI_RXOICR_OFFSET) // SSI_RXOICR
+    // RX FIFO overflow interrupt clear
+    // 0x00000001 [0]     : RXOICR (0): Clear-on-read receive FIFO overflow interrupt
+    io_ro_32 rxoicr;
+
+    _REG_(SSI_RXUICR_OFFSET) // SSI_RXUICR
+    // RX FIFO underflow interrupt clear
+    // 0x00000001 [0]     : RXUICR (0): Clear-on-read receive FIFO underflow interrupt
+    io_ro_32 rxuicr;
+
+    _REG_(SSI_MSTICR_OFFSET) // SSI_MSTICR
+    // Multi-master interrupt clear
+    // 0x00000001 [0]     : MSTICR (0): Clear-on-read multi-master contention interrupt
+    io_ro_32 msticr;
+
+    _REG_(SSI_ICR_OFFSET) // SSI_ICR
+    // Interrupt clear
+    // 0x00000001 [0]     : ICR (0): Clear-on-read all active interrupts
+    io_ro_32 icr;
+
+    _REG_(SSI_DMACR_OFFSET) // SSI_DMACR
+    // DMA control
+    // 0x00000002 [1]     : TDMAE (0): Transmit DMA enable
+    // 0x00000001 [0]     : RDMAE (0): Receive DMA enable
+    io_rw_32 dmacr;
+
+    _REG_(SSI_DMATDLR_OFFSET) // SSI_DMATDLR
+    // DMA TX data level
+    // 0x000000ff [7:0]   : DMATDL (0): Transmit data watermark level
+    io_rw_32 dmatdlr;
+
+    _REG_(SSI_DMARDLR_OFFSET) // SSI_DMARDLR
+    // DMA RX data level
+    // 0x000000ff [7:0]   : DMARDL (0): Receive data watermark level (DMARDLR+1)
+    io_rw_32 dmardlr;
+
+    _REG_(SSI_IDR_OFFSET) // SSI_IDR
+    // Identification register
+    // 0xffffffff [31:0]  : IDCODE (0x51535049): Peripheral dentification code
+    io_ro_32 idr;
+
+    _REG_(SSI_SSI_VERSION_ID_OFFSET) // SSI_SSI_VERSION_ID
+    // Version ID
+    // 0xffffffff [31:0]  : SSI_COMP_VERSION (0x3430312a): SNPS component version (format X
+    io_ro_32 ssi_version_id;
+
+    _REG_(SSI_DR0_OFFSET) // SSI_DR0
+    // Data Register 0 (of 36)
+    // 0xffffffff [31:0]  : DR (0): First data register of 36
+    io_rw_32 dr0;
+
+    uint32_t _pad0[35];
+
+    _REG_(SSI_RX_SAMPLE_DLY_OFFSET) // SSI_RX_SAMPLE_DLY
+    // RX sample delay
+    // 0x000000ff [7:0]   : RSD (0): RXD sample delay (in SCLK cycles)
+    io_rw_32 rx_sample_dly;
+
+    _REG_(SSI_SPI_CTRLR0_OFFSET) // SSI_SPI_CTRLR0
+    // SPI control
+    // 0xff000000 [31:24] : XIP_CMD (0x3): SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)
+    // 0x00040000 [18]    : SPI_RXDS_EN (0): Read data strobe enable
+    // 0x00020000 [17]    : INST_DDR_EN (0): Instruction DDR transfer enable
+    // 0x00010000 [16]    : SPI_DDR_EN (0): SPI DDR transfer enable
+    // 0x0000f800 [15:11] : WAIT_CYCLES (0): Wait cycles between control frame transmit and data reception (in SCLK cycles)
+    // 0x00000300 [9:8]   : INST_L (0): Instruction length (0/4/8/16b)
+    // 0x0000003c [5:2]   : ADDR_L (0): Address length (0b-60b in 4b increments)
+    // 0x00000003 [1:0]   : TRANS_TYPE (0): Address and instruction transfer format
+    io_rw_32 spi_ctrlr0;
+
+    _REG_(SSI_TXD_DRIVE_EDGE_OFFSET) // SSI_TXD_DRIVE_EDGE
+    // TX drive edge
+    // 0x000000ff [7:0]   : TDE (0): TXD drive edge
+    io_rw_32 txd_drive_edge;
+} ssi_hw_t;
+
+#define ssi_hw ((ssi_hw_t *const)XIP_SSI_BASE)
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/syscfg.h b/src/rp2040/hardware_structs/include/hardware/structs/syscfg.h
new file mode 100644
index 0000000..52218fb
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/syscfg.h
@@ -0,0 +1,77 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_SYSCFG_H
+#define _HARDWARE_STRUCTS_SYSCFG_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/syscfg.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_syscfg
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(SYSCFG_PROC0_NMI_MASK_OFFSET) // SYSCFG_PROC0_NMI_MASK
+    // Processor core 0 NMI source mask
+    io_rw_32 proc0_nmi_mask;
+
+    _REG_(SYSCFG_PROC1_NMI_MASK_OFFSET) // SYSCFG_PROC1_NMI_MASK
+    // Processor core 1 NMI source mask
+    io_rw_32 proc1_nmi_mask;
+
+    _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG
+    // Configuration for processors
+    // 0xf0000000 [31:28] : PROC1_DAP_INSTID (1): Configure proc1 DAP instance ID
+    // 0x0f000000 [27:24] : PROC0_DAP_INSTID (0): Configure proc0 DAP instance ID
+    // 0x00000002 [1]     : PROC1_HALTED (0): Indication that proc1 has halted
+    // 0x00000001 [0]     : PROC0_HALTED (0): Indication that proc0 has halted
+    io_rw_32 proc_config;
+
+    _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS
+    // For each bit, if 1, bypass the input synchronizer between that GPIO
+    // 0x3fffffff [29:0]  : PROC_IN_SYNC_BYPASS (0)
+    io_rw_32 proc_in_sync_bypass;
+
+    _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI
+    // For each bit, if 1, bypass the input synchronizer between that GPIO
+    // 0x0000003f [5:0]   : PROC_IN_SYNC_BYPASS_HI (0)
+    io_rw_32 proc_in_sync_bypass_hi;
+
+    _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE
+    // Directly control the SWD debug port of either processor
+    // 0x00000080 [7]     : PROC1_ATTACH (0): Attach processor 1 debug port to syscfg controls, and disconnect it from...
+    // 0x00000040 [6]     : PROC1_SWCLK (1): Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
+    // 0x00000020 [5]     : PROC1_SWDI (1): Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
+    // 0x00000010 [4]     : PROC1_SWDO (0): Observe the value of processor 1 SWDIO output
+    // 0x00000008 [3]     : PROC0_ATTACH (0): Attach processor 0 debug port to syscfg controls, and disconnect it from...
+    // 0x00000004 [2]     : PROC0_SWCLK (1): Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
+    // 0x00000002 [1]     : PROC0_SWDI (1): Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
+    // 0x00000001 [0]     : PROC0_SWDO (0): Observe the value of processor 0 SWDIO output
+    io_rw_32 dbgforce;
+
+    _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN
+    // Control power downs to memories
+    // 0x00000080 [7]     : ROM (0)
+    // 0x00000040 [6]     : USB (0)
+    // 0x00000020 [5]     : SRAM5 (0)
+    // 0x00000010 [4]     : SRAM4 (0)
+    // 0x00000008 [3]     : SRAM3 (0)
+    // 0x00000004 [2]     : SRAM2 (0)
+    // 0x00000002 [1]     : SRAM1 (0)
+    // 0x00000001 [0]     : SRAM0 (0)
+    io_rw_32 mempowerdown;
+} syscfg_hw_t;
+
+#define syscfg_hw ((syscfg_hw_t *const)SYSCFG_BASE)
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/systick.h b/src/rp2040/hardware_structs/include/hardware/structs/systick.h
new file mode 100644
index 0000000..a859fea
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/systick.h
@@ -0,0 +1,52 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_SYSTICK_H
+#define _HARDWARE_STRUCTS_SYSTICK_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/m0plus.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR
+    // Use the SysTick Control and Status Register to enable the SysTick features
+    // 0x00010000 [16]    : COUNTFLAG (0): Returns 1 if timer counted to 0 since last time this was read
+    // 0x00000004 [2]     : CLKSOURCE (0): SysTick clock source
+    // 0x00000002 [1]     : TICKINT (0): Enables SysTick exception request:
+    // 0x00000001 [0]     : ENABLE (0): Enable SysTick counter:
+    io_rw_32 csr;
+
+    _REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR
+    // Use the SysTick Reload Value Register to specify the start value to load into the current value register when the...
+    // 0x00ffffff [23:0]  : RELOAD (0): Value to load into the SysTick Current Value Register when the counter reaches 0
+    io_rw_32 rvr;
+
+    _REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR
+    // Use the SysTick Current Value Register to find the current value in the register
+    // 0x00ffffff [23:0]  : CURRENT (0): Reads return the current value of the SysTick counter
+    io_rw_32 cvr;
+
+    _REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB
+    // Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply
+    // 0x80000000 [31]    : NOREF (0): If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the...
+    // 0x40000000 [30]    : SKEW (0): If reads as 1, the calibration value for 10ms is inexact (due to clock frequency)
+    // 0x00ffffff [23:0]  : TENMS (0): An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock...
+    io_ro_32 calib;
+} systick_hw_t;
+
+#define systick_hw ((systick_hw_t *const)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET))
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/timer.h b/src/rp2040/hardware_structs/include/hardware/structs/timer.h
new file mode 100644
index 0000000..c7c7066
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/timer.h
@@ -0,0 +1,107 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_TIMER_H
+#define _HARDWARE_STRUCTS_TIMER_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/timer.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_timer
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/timer.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW
+    // Write to bits 63:32 of time
+    io_wo_32 timehw;
+
+    _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW
+    // Write to bits 31:0 of time
+    io_wo_32 timelw;
+
+    _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR
+    // Read from bits 63:32 of time
+    io_ro_32 timehr;
+
+    _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR
+    // Read from bits 31:0 of time
+    io_ro_32 timelr;
+
+    _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0
+    // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes)
+    //
+    // Arm alarm 0, and configure the time it will fire
+    io_rw_32 alarm[NUM_TIMERS]; // 4
+
+    _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED
+    // Indicates the armed/disarmed status of each alarm
+    // 0x0000000f [3:0]   : ARMED (0)
+    io_rw_32 armed;
+
+    _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH
+    // Raw read from bits 63:32 of time (no side effects)
+    io_ro_32 timerawh;
+
+    _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL
+    // Raw read from bits 31:0 of time (no side effects)
+    io_ro_32 timerawl;
+
+    _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE
+    // Set bits high to enable pause when the corresponding debug ports are active
+    // 0x00000004 [2]     : DBG1 (1): Pause when processor 1 is in debug mode
+    // 0x00000002 [1]     : DBG0 (1): Pause when processor 0 is in debug mode
+    io_rw_32 dbgpause;
+
+    _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE
+    // Set high to pause the timer
+    // 0x00000001 [0]     : PAUSE (0)
+    io_rw_32 pause;
+
+    _REG_(TIMER_INTR_OFFSET) // TIMER_INTR
+    // Raw Interrupts
+    // 0x00000008 [3]     : ALARM_3 (0)
+    // 0x00000004 [2]     : ALARM_2 (0)
+    // 0x00000002 [1]     : ALARM_1 (0)
+    // 0x00000001 [0]     : ALARM_0 (0)
+    io_rw_32 intr;
+
+    _REG_(TIMER_INTE_OFFSET) // TIMER_INTE
+    // Interrupt Enable
+    // 0x00000008 [3]     : ALARM_3 (0)
+    // 0x00000004 [2]     : ALARM_2 (0)
+    // 0x00000002 [1]     : ALARM_1 (0)
+    // 0x00000001 [0]     : ALARM_0 (0)
+    io_rw_32 inte;
+
+    _REG_(TIMER_INTF_OFFSET) // TIMER_INTF
+    // Interrupt Force
+    // 0x00000008 [3]     : ALARM_3 (0)
+    // 0x00000004 [2]     : ALARM_2 (0)
+    // 0x00000002 [1]     : ALARM_1 (0)
+    // 0x00000001 [0]     : ALARM_0 (0)
+    io_rw_32 intf;
+
+    _REG_(TIMER_INTS_OFFSET) // TIMER_INTS
+    // Interrupt status after masking & forcing
+    // 0x00000008 [3]     : ALARM_3 (0)
+    // 0x00000004 [2]     : ALARM_2 (0)
+    // 0x00000002 [1]     : ALARM_1 (0)
+    // 0x00000001 [0]     : ALARM_0 (0)
+    io_ro_32 ints;
+} timer_hw_t;
+
+#define timer_hw ((timer_hw_t *const)TIMER_BASE)
+
+static_assert( NUM_TIMERS == 4, "");
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/uart.h b/src/rp2040/hardware_structs/include/hardware/structs/uart.h
new file mode 100644
index 0000000..09af33e
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/uart.h
@@ -0,0 +1,177 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_UART_H
+#define _HARDWARE_STRUCTS_UART_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/uart.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_uart
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/uart.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(UART_UARTDR_OFFSET) // UART_UARTDR
+    // Data Register, UARTDR
+    // 0x00000800 [11]    : OE (0): Overrun error
+    // 0x00000400 [10]    : BE (0): Break error
+    // 0x00000200 [9]     : PE (0): Parity error
+    // 0x00000100 [8]     : FE (0): Framing error
+    // 0x000000ff [7:0]   : DATA (0): Receive (read) data character
+    io_rw_32 dr;
+
+    _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR
+    // Receive Status Register/Error Clear Register, UARTRSR/UARTECR
+    // 0x00000008 [3]     : OE (0): Overrun error
+    // 0x00000004 [2]     : BE (0): Break error
+    // 0x00000002 [1]     : PE (0): Parity error
+    // 0x00000001 [0]     : FE (0): Framing error
+    io_rw_32 rsr;
+
+    uint32_t _pad0[4];
+
+    _REG_(UART_UARTFR_OFFSET) // UART_UARTFR
+    // Flag Register, UARTFR
+    // 0x00000100 [8]     : RI (0): Ring indicator
+    // 0x00000080 [7]     : TXFE (1): Transmit FIFO empty
+    // 0x00000040 [6]     : RXFF (0): Receive FIFO full
+    // 0x00000020 [5]     : TXFF (0): Transmit FIFO full
+    // 0x00000010 [4]     : RXFE (1): Receive FIFO empty
+    // 0x00000008 [3]     : BUSY (0): UART busy
+    // 0x00000004 [2]     : DCD (0): Data carrier detect
+    // 0x00000002 [1]     : DSR (0): Data set ready
+    // 0x00000001 [0]     : CTS (0): Clear to send
+    io_ro_32 fr;
+
+    uint32_t _pad1;
+
+    _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR
+    // IrDA Low-Power Counter Register, UARTILPR
+    // 0x000000ff [7:0]   : ILPDVSR (0): 8-bit low-power divisor value
+    io_rw_32 ilpr;
+
+    _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD
+    // Integer Baud Rate Register, UARTIBRD
+    // 0x0000ffff [15:0]  : BAUD_DIVINT (0): The integer baud rate divisor
+    io_rw_32 ibrd;
+
+    _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD
+    // Fractional Baud Rate Register, UARTFBRD
+    // 0x0000003f [5:0]   : BAUD_DIVFRAC (0): The fractional baud rate divisor
+    io_rw_32 fbrd;
+
+    _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H
+    // Line Control Register, UARTLCR_H
+    // 0x00000080 [7]     : SPS (0): Stick parity select
+    // 0x00000060 [6:5]   : WLEN (0): Word length
+    // 0x00000010 [4]     : FEN (0): Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become...
+    // 0x00000008 [3]     : STP2 (0): Two stop bits select
+    // 0x00000004 [2]     : EPS (0): Even parity select
+    // 0x00000002 [1]     : PEN (0): Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 =...
+    // 0x00000001 [0]     : BRK (0): Send break
+    io_rw_32 lcr_h;
+
+    _REG_(UART_UARTCR_OFFSET) // UART_UARTCR
+    // Control Register, UARTCR
+    // 0x00008000 [15]    : CTSEN (0): CTS hardware flow control enable
+    // 0x00004000 [14]    : RTSEN (0): RTS hardware flow control enable
+    // 0x00002000 [13]    : OUT2 (0): This bit is the complement of the UART Out2 (nUARTOut2) modem status output
+    // 0x00001000 [12]    : OUT1 (0): This bit is the complement of the UART Out1 (nUARTOut1) modem status output
+    // 0x00000800 [11]    : RTS (0): Request to send
+    // 0x00000400 [10]    : DTR (0): Data transmit ready
+    // 0x00000200 [9]     : RXE (1): Receive enable
+    // 0x00000100 [8]     : TXE (1): Transmit enable
+    // 0x00000080 [7]     : LBE (0): Loopback enable
+    // 0x00000004 [2]     : SIRLP (0): SIR low-power IrDA mode
+    // 0x00000002 [1]     : SIREN (0): SIR enable: 0 = IrDA SIR ENDEC is disabled
+    // 0x00000001 [0]     : UARTEN (0): UART enable: 0 = UART is disabled
+    io_rw_32 cr;
+
+    _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS
+    // Interrupt FIFO Level Select Register, UARTIFLS
+    // 0x00000038 [5:3]   : RXIFLSEL (0x2): Receive interrupt FIFO level select
+    // 0x00000007 [2:0]   : TXIFLSEL (0x2): Transmit interrupt FIFO level select
+    io_rw_32 ifls;
+
+    _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC
+    // Interrupt Mask Set/Clear Register, UARTIMSC
+    // 0x00000400 [10]    : OEIM (0): Overrun error interrupt mask
+    // 0x00000200 [9]     : BEIM (0): Break error interrupt mask
+    // 0x00000100 [8]     : PEIM (0): Parity error interrupt mask
+    // 0x00000080 [7]     : FEIM (0): Framing error interrupt mask
+    // 0x00000040 [6]     : RTIM (0): Receive timeout interrupt mask
+    // 0x00000020 [5]     : TXIM (0): Transmit interrupt mask
+    // 0x00000010 [4]     : RXIM (0): Receive interrupt mask
+    // 0x00000008 [3]     : DSRMIM (0): nUARTDSR modem interrupt mask
+    // 0x00000004 [2]     : DCDMIM (0): nUARTDCD modem interrupt mask
+    // 0x00000002 [1]     : CTSMIM (0): nUARTCTS modem interrupt mask
+    // 0x00000001 [0]     : RIMIM (0): nUARTRI modem interrupt mask
+    io_rw_32 imsc;
+
+    _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS
+    // Raw Interrupt Status Register, UARTRIS
+    // 0x00000400 [10]    : OERIS (0): Overrun error interrupt status
+    // 0x00000200 [9]     : BERIS (0): Break error interrupt status
+    // 0x00000100 [8]     : PERIS (0): Parity error interrupt status
+    // 0x00000080 [7]     : FERIS (0): Framing error interrupt status
+    // 0x00000040 [6]     : RTRIS (0): Receive timeout interrupt status
+    // 0x00000020 [5]     : TXRIS (0): Transmit interrupt status
+    // 0x00000010 [4]     : RXRIS (0): Receive interrupt status
+    // 0x00000008 [3]     : DSRRMIS (0): nUARTDSR modem interrupt status
+    // 0x00000004 [2]     : DCDRMIS (0): nUARTDCD modem interrupt status
+    // 0x00000002 [1]     : CTSRMIS (0): nUARTCTS modem interrupt status
+    // 0x00000001 [0]     : RIRMIS (0): nUARTRI modem interrupt status
+    io_ro_32 ris;
+
+    _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS
+    // Masked Interrupt Status Register, UARTMIS
+    // 0x00000400 [10]    : OEMIS (0): Overrun error masked interrupt status
+    // 0x00000200 [9]     : BEMIS (0): Break error masked interrupt status
+    // 0x00000100 [8]     : PEMIS (0): Parity error masked interrupt status
+    // 0x00000080 [7]     : FEMIS (0): Framing error masked interrupt status
+    // 0x00000040 [6]     : RTMIS (0): Receive timeout masked interrupt status
+    // 0x00000020 [5]     : TXMIS (0): Transmit masked interrupt status
+    // 0x00000010 [4]     : RXMIS (0): Receive masked interrupt status
+    // 0x00000008 [3]     : DSRMMIS (0): nUARTDSR modem masked interrupt status
+    // 0x00000004 [2]     : DCDMMIS (0): nUARTDCD modem masked interrupt status
+    // 0x00000002 [1]     : CTSMMIS (0): nUARTCTS modem masked interrupt status
+    // 0x00000001 [0]     : RIMMIS (0): nUARTRI modem masked interrupt status
+    io_ro_32 mis;
+
+    _REG_(UART_UARTICR_OFFSET) // UART_UARTICR
+    // Interrupt Clear Register, UARTICR
+    // 0x00000400 [10]    : OEIC (0): Overrun error interrupt clear
+    // 0x00000200 [9]     : BEIC (0): Break error interrupt clear
+    // 0x00000100 [8]     : PEIC (0): Parity error interrupt clear
+    // 0x00000080 [7]     : FEIC (0): Framing error interrupt clear
+    // 0x00000040 [6]     : RTIC (0): Receive timeout interrupt clear
+    // 0x00000020 [5]     : TXIC (0): Transmit interrupt clear
+    // 0x00000010 [4]     : RXIC (0): Receive interrupt clear
+    // 0x00000008 [3]     : DSRMIC (0): nUARTDSR modem interrupt clear
+    // 0x00000004 [2]     : DCDMIC (0): nUARTDCD modem interrupt clear
+    // 0x00000002 [1]     : CTSMIC (0): nUARTCTS modem interrupt clear
+    // 0x00000001 [0]     : RIMIC (0): nUARTRI modem interrupt clear
+    io_rw_32 icr;
+
+    _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR
+    // DMA Control Register, UARTDMACR
+    // 0x00000004 [2]     : DMAONERR (0): DMA on error
+    // 0x00000002 [1]     : TXDMAE (0): Transmit DMA enable
+    // 0x00000001 [0]     : RXDMAE (0): Receive DMA enable
+    io_rw_32 dmacr;
+} uart_hw_t;
+
+#define uart0_hw ((uart_hw_t *const)UART0_BASE)
+#define uart1_hw ((uart_hw_t *const)UART1_BASE)
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/usb.h b/src/rp2040/hardware_structs/include/hardware/structs/usb.h
new file mode 100644
index 0000000..c9455d0
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/usb.h
@@ -0,0 +1,578 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_USB_H
+#define _HARDWARE_STRUCTS_USB_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/usb.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_usb
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/usb.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+// 0-15
+#define USB_NUM_ENDPOINTS 16
+
+// allow user to restrict number of endpoints available to save RAN
+#ifndef USB_MAX_ENDPOINTS
+#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS
+#endif
+
+// 1-15
+#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1)
+
+// Endpoint buffer control bits
+#define USB_BUF_CTRL_FULL      0x00008000u
+#define USB_BUF_CTRL_LAST      0x00004000u
+#define USB_BUF_CTRL_DATA0_PID 0x00000000u
+#define USB_BUF_CTRL_DATA1_PID 0x00002000u
+#define USB_BUF_CTRL_SEL       0x00001000u
+#define USB_BUF_CTRL_STALL     0x00000800u
+#define USB_BUF_CTRL_AVAIL     0x00000400u
+#define USB_BUF_CTRL_LEN_MASK  0x000003FFu
+#define USB_BUF_CTRL_LEN_LSB   0
+
+// ep_inout_ctrl bits
+#define EP_CTRL_ENABLE_BITS (1u << 31u)
+#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30)
+#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29)
+#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28)
+#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16)
+#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17)
+#define EP_CTRL_BUFFER_TYPE_LSB 26u
+#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u
+
+#define USB_DPRAM_SIZE 4096u
+
+// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb
+// Allow user to claim some of the USB RAM for themselves
+#ifndef USB_DPRAM_MAX
+#define USB_DPRAM_MAX USB_DPRAM_SIZE
+#endif
+
+// Define maximum packet sizes
+#define USB_MAX_ISO_PACKET_SIZE 1023
+#define USB_MAX_PACKET_SIZE 64
+
+typedef struct {
+    // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
+    volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets
+
+    // Starts at ep1
+    struct usb_device_dpram_ep_ctrl {
+        io_rw_32 in;
+        io_rw_32 out;
+    } ep_ctrl[USB_NUM_ENDPOINTS - 1];
+
+    // Starts at ep0
+    struct usb_device_dpram_ep_buf_ctrl {
+        io_rw_32 in;
+        io_rw_32 out;
+    } ep_buf_ctrl[USB_NUM_ENDPOINTS];
+
+    // EP0 buffers are fixed. Assumes single buffered mode for EP0
+    uint8_t ep0_buf_a[0x40];
+    uint8_t ep0_buf_b[0x40];
+
+    // Rest of DPRAM can be carved up as needed
+    uint8_t epx_data[USB_DPRAM_MAX - 0x180];
+} usb_device_dpram_t;
+
+static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, "");
+static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, "");
+
+typedef struct {
+    // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
+    volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets
+
+    // Interrupt endpoint control 1 -> 15
+    struct usb_host_dpram_ep_ctrl {
+        io_rw_32 ctrl;
+        io_rw_32 spare;
+    } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
+
+    io_rw_32 epx_buf_ctrl;
+    io_rw_32 _spare0;
+
+    // Interrupt endpoint buffer control
+    struct usb_host_dpram_ep_buf_ctrl {
+        io_rw_32 ctrl;
+        io_rw_32 spare;
+    } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
+
+    io_rw_32 epx_ctrl;
+
+    uint8_t _spare1[124];
+
+    // Should start at 0x180
+    uint8_t epx_data[USB_DPRAM_MAX - 0x180];
+} usb_host_dpram_t;
+
+static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, "");
+static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, "");
+
+typedef struct {
+    _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP
+    // Device address and endpoint control
+    // 0x000f0000 [19:16] : ENDPOINT (0): Device endpoint to send data to
+    // 0x0000007f [6:0]   : ADDRESS (0): In device mode, the address that the device should respond to
+    io_rw_32 dev_addr_ctrl;
+
+    _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1
+    // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes)
+    //
+    // Interrupt endpoint 1
+    // 0x04000000 [26]    : INTEP_PREAMBLE (0): Interrupt EP requires preamble (is a low speed device on a full speed hub)
+    // 0x02000000 [25]    : INTEP_DIR (0): Direction of the interrupt endpoint
+    // 0x000f0000 [19:16] : ENDPOINT (0): Endpoint number of the interrupt endpoint
+    // 0x0000007f [6:0]   : ADDRESS (0): Device address
+    io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; // 15
+
+    _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL
+    // Main control register
+    // 0x80000000 [31]    : SIM_TIMING (0): Reduced timings for simulation
+    // 0x00000002 [1]     : HOST_NDEVICE (0): Device mode = 0, Host mode = 1
+    // 0x00000001 [0]     : CONTROLLER_EN (0): Enable controller
+    io_rw_32 main_ctrl;
+
+    _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR
+    // Set the SOF (Start of Frame) frame number in the host controller
+    // 0x000007ff [10:0]  : COUNT (0)
+    io_wo_32 sof_rw;
+
+    _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD
+    // Read the last SOF (Start of Frame) frame number seen
+    // 0x000007ff [10:0]  : COUNT (0)
+    io_ro_32 sof_rd;
+
+    _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL
+    // SIE control register
+    // 0x80000000 [31]    : EP0_INT_STALL (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
+    // 0x40000000 [30]    : EP0_DOUBLE_BUF (0): Device: EP0 single buffered = 0, double buffered = 1
+    // 0x20000000 [29]    : EP0_INT_1BUF (0): Device: Set bit in BUFF_STATUS for every buffer completed on EP0
+    // 0x10000000 [28]    : EP0_INT_2BUF (0): Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0
+    // 0x08000000 [27]    : EP0_INT_NAK (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
+    // 0x04000000 [26]    : DIRECT_EN (0): Direct bus drive enable
+    // 0x02000000 [25]    : DIRECT_DP (0): Direct control of DP
+    // 0x01000000 [24]    : DIRECT_DM (0): Direct control of DM
+    // 0x00040000 [18]    : TRANSCEIVER_PD (0): Power down bus transceiver
+    // 0x00020000 [17]    : RPU_OPT (0): Device: Pull-up strength (0=1K2, 1=2k3)
+    // 0x00010000 [16]    : PULLUP_EN (0): Device: Enable pull up resistor
+    // 0x00008000 [15]    : PULLDOWN_EN (0): Host: Enable pull down resistors
+    // 0x00002000 [13]    : RESET_BUS (0): Host: Reset bus
+    // 0x00001000 [12]    : RESUME (0): Device: Remote wakeup
+    // 0x00000800 [11]    : VBUS_EN (0): Host: Enable VBUS
+    // 0x00000400 [10]    : KEEP_ALIVE_EN (0): Host: Enable keep alive packet (for low speed bus)
+    // 0x00000200 [9]     : SOF_EN (0): Host: Enable SOF generation (for full speed bus)
+    // 0x00000100 [8]     : SOF_SYNC (0): Host: Delay packet(s) until after SOF
+    // 0x00000040 [6]     : PREAMBLE_EN (0): Host: Preable enable for LS device on FS hub
+    // 0x00000010 [4]     : STOP_TRANS (0): Host: Stop transaction
+    // 0x00000008 [3]     : RECEIVE_DATA (0): Host: Receive transaction (IN to host)
+    // 0x00000004 [2]     : SEND_DATA (0): Host: Send transaction (OUT from host)
+    // 0x00000002 [1]     : SEND_SETUP (0): Host: Send Setup packet
+    // 0x00000001 [0]     : START_TRANS (0): Host: Start transaction
+    io_rw_32 sie_ctrl;
+
+    _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS
+    // SIE status register
+    // 0x80000000 [31]    : DATA_SEQ_ERROR (0): Data Sequence Error
+    // 0x40000000 [30]    : ACK_REC (0): ACK received
+    // 0x20000000 [29]    : STALL_REC (0): Host: STALL received
+    // 0x10000000 [28]    : NAK_REC (0): Host: NAK received
+    // 0x08000000 [27]    : RX_TIMEOUT (0): RX timeout is raised by both the host and device if an ACK is not received in...
+    // 0x04000000 [26]    : RX_OVERFLOW (0): RX overflow is raised by the Serial RX engine if the incoming data is too fast
+    // 0x02000000 [25]    : BIT_STUFF_ERROR (0): Bit Stuff Error
+    // 0x01000000 [24]    : CRC_ERROR (0): CRC Error
+    // 0x00080000 [19]    : BUS_RESET (0): Device: bus reset received
+    // 0x00040000 [18]    : TRANS_COMPLETE (0): Transaction complete
+    // 0x00020000 [17]    : SETUP_REC (0): Device: Setup packet received
+    // 0x00010000 [16]    : CONNECTED (0): Device: connected
+    // 0x00000800 [11]    : RESUME (0): Host: Device has initiated a remote resume
+    // 0x00000400 [10]    : VBUS_OVER_CURR (0): VBUS over current detected
+    // 0x00000300 [9:8]   : SPEED (0): Host: device speed
+    // 0x00000010 [4]     : SUSPENDED (0): Bus in suspended state
+    // 0x0000000c [3:2]   : LINE_STATE (0): USB bus line state
+    // 0x00000001 [0]     : VBUS_DETECTED (0): Device: VBUS Detected
+    io_rw_32 sie_status;
+
+    _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL
+    // interrupt endpoint control register
+    // 0x0000fffe [15:1]  : INT_EP_ACTIVE (0): Host: Enable interrupt endpoint 1 -> 15
+    io_rw_32 int_ep_ctrl;
+
+    _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS
+    // Buffer status register
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
+    io_rw_32 buf_status;
+
+    _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE
+    // Which of the double buffers should be handled
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
+    io_ro_32 buf_cpu_should_handle;
+
+    _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT
+    // Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
+    io_rw_32 abort;
+
+    _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE
+    // Device only: Used in conjunction with `EP_ABORT`
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
+    io_rw_32 abort_done;
+
+    _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM
+    // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
+    io_rw_32 ep_stall_arm;
+
+    _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL
+    // Used by the host controller
+    // 0x03ff0000 [25:16] : DELAY_FS (0x10): NAK polling interval for a full speed device
+    // 0x000003ff [9:0]   : DELAY_LS (0x10): NAK polling interval for a low speed device
+    io_rw_32 nak_poll;
+
+    _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK
+    // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set
+    // 0x80000000 [31]    : EP15_OUT (0)
+    // 0x40000000 [30]    : EP15_IN (0)
+    // 0x20000000 [29]    : EP14_OUT (0)
+    // 0x10000000 [28]    : EP14_IN (0)
+    // 0x08000000 [27]    : EP13_OUT (0)
+    // 0x04000000 [26]    : EP13_IN (0)
+    // 0x02000000 [25]    : EP12_OUT (0)
+    // 0x01000000 [24]    : EP12_IN (0)
+    // 0x00800000 [23]    : EP11_OUT (0)
+    // 0x00400000 [22]    : EP11_IN (0)
+    // 0x00200000 [21]    : EP10_OUT (0)
+    // 0x00100000 [20]    : EP10_IN (0)
+    // 0x00080000 [19]    : EP9_OUT (0)
+    // 0x00040000 [18]    : EP9_IN (0)
+    // 0x00020000 [17]    : EP8_OUT (0)
+    // 0x00010000 [16]    : EP8_IN (0)
+    // 0x00008000 [15]    : EP7_OUT (0)
+    // 0x00004000 [14]    : EP7_IN (0)
+    // 0x00002000 [13]    : EP6_OUT (0)
+    // 0x00001000 [12]    : EP6_IN (0)
+    // 0x00000800 [11]    : EP5_OUT (0)
+    // 0x00000400 [10]    : EP5_IN (0)
+    // 0x00000200 [9]     : EP4_OUT (0)
+    // 0x00000100 [8]     : EP4_IN (0)
+    // 0x00000080 [7]     : EP3_OUT (0)
+    // 0x00000040 [6]     : EP3_IN (0)
+    // 0x00000020 [5]     : EP2_OUT (0)
+    // 0x00000010 [4]     : EP2_IN (0)
+    // 0x00000008 [3]     : EP1_OUT (0)
+    // 0x00000004 [2]     : EP1_IN (0)
+    // 0x00000002 [1]     : EP0_OUT (0)
+    // 0x00000001 [0]     : EP0_IN (0)
+    io_rw_32 ep_nak_stall_status;
+
+    _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING
+    // Where to connect the USB controller
+    // 0x00000008 [3]     : SOFTCON (0)
+    // 0x00000004 [2]     : TO_DIGITAL_PAD (0)
+    // 0x00000002 [1]     : TO_EXTPHY (0)
+    // 0x00000001 [0]     : TO_PHY (0)
+    io_rw_32 muxing;
+
+    _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR
+    // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO
+    // 0x00000020 [5]     : OVERCURR_DETECT_EN (0)
+    // 0x00000010 [4]     : OVERCURR_DETECT (0)
+    // 0x00000008 [3]     : VBUS_DETECT_OVERRIDE_EN (0)
+    // 0x00000004 [2]     : VBUS_DETECT (0)
+    // 0x00000002 [1]     : VBUS_EN_OVERRIDE_EN (0)
+    // 0x00000001 [0]     : VBUS_EN (0)
+    io_rw_32 pwr;
+
+    _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT
+    // This register allows for direct control of the USB phy
+    // 0x00400000 [22]    : DM_OVV (0): DM over voltage
+    // 0x00200000 [21]    : DP_OVV (0): DP over voltage
+    // 0x00100000 [20]    : DM_OVCN (0): DM overcurrent
+    // 0x00080000 [19]    : DP_OVCN (0): DP overcurrent
+    // 0x00040000 [18]    : RX_DM (0): DPM pin state
+    // 0x00020000 [17]    : RX_DP (0): DPP pin state
+    // 0x00010000 [16]    : RX_DD (0): Differential RX
+    // 0x00008000 [15]    : TX_DIFFMODE (0): TX_DIFFMODE=0: Single ended mode
+    // 0x00004000 [14]    : TX_FSSLEW (0): TX_FSSLEW=0: Low speed slew rate
+    // 0x00002000 [13]    : TX_PD (0): TX power down override (if override enable is set)
+    // 0x00001000 [12]    : RX_PD (0): RX power down override (if override enable is set)
+    // 0x00000800 [11]    : TX_DM (0): Output data
+    // 0x00000400 [10]    : TX_DP (0): Output data
+    // 0x00000200 [9]     : TX_DM_OE (0): Output enable
+    // 0x00000100 [8]     : TX_DP_OE (0): Output enable
+    // 0x00000040 [6]     : DM_PULLDN_EN (0): DM pull down enable
+    // 0x00000020 [5]     : DM_PULLUP_EN (0): DM pull up enable
+    // 0x00000010 [4]     : DM_PULLUP_HISEL (0): Enable the second DM pull up resistor
+    // 0x00000004 [2]     : DP_PULLDN_EN (0): DP pull down enable
+    // 0x00000002 [1]     : DP_PULLUP_EN (0): DP pull up enable
+    // 0x00000001 [0]     : DP_PULLUP_HISEL (0): Enable the second DP pull up resistor
+    io_rw_32 phy_direct;
+
+    _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE
+    // Override enable for each control in usbphy_direct
+    // 0x00008000 [15]    : TX_DIFFMODE_OVERRIDE_EN (0)
+    // 0x00001000 [12]    : DM_PULLUP_OVERRIDE_EN (0)
+    // 0x00000800 [11]    : TX_FSSLEW_OVERRIDE_EN (0)
+    // 0x00000400 [10]    : TX_PD_OVERRIDE_EN (0)
+    // 0x00000200 [9]     : RX_PD_OVERRIDE_EN (0)
+    // 0x00000100 [8]     : TX_DM_OVERRIDE_EN (0)
+    // 0x00000080 [7]     : TX_DP_OVERRIDE_EN (0)
+    // 0x00000040 [6]     : TX_DM_OE_OVERRIDE_EN (0)
+    // 0x00000020 [5]     : TX_DP_OE_OVERRIDE_EN (0)
+    // 0x00000010 [4]     : DM_PULLDN_EN_OVERRIDE_EN (0)
+    // 0x00000008 [3]     : DP_PULLDN_EN_OVERRIDE_EN (0)
+    // 0x00000004 [2]     : DP_PULLUP_EN_OVERRIDE_EN (0)
+    // 0x00000002 [1]     : DM_PULLUP_HISEL_OVERRIDE_EN (0)
+    // 0x00000001 [0]     : DP_PULLUP_HISEL_OVERRIDE_EN (0)
+    io_rw_32 phy_direct_override;
+
+    _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM
+    // Used to adjust trim values of USB phy pull down resistors
+    // 0x00001f00 [12:8]  : DM_PULLDN_TRIM (0x1f): Value to drive to USB PHY
+    // 0x0000001f [4:0]   : DP_PULLDN_TRIM (0x1f): Value to drive to USB PHY
+    io_rw_32 phy_trim;
+
+    uint32_t _pad0;
+
+    _REG_(USB_INTR_OFFSET) // USB_INTR
+    // Raw Interrupts
+    // 0x00080000 [19]    : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+    // 0x00040000 [18]    : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+    // 0x00020000 [17]    : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+    // 0x00010000 [16]    : SETUP_REQ (0): Device
+    // 0x00008000 [15]    : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+    // 0x00004000 [14]    : DEV_SUSPEND (0): Set when the device suspend state changes
+    // 0x00002000 [13]    : DEV_CONN_DIS (0): Set when the device connection state changes
+    // 0x00001000 [12]    : BUS_RESET (0): Source: SIE_STATUS
+    // 0x00000800 [11]    : VBUS_DETECT (0): Source: SIE_STATUS
+    // 0x00000400 [10]    : STALL (0): Source: SIE_STATUS
+    // 0x00000200 [9]     : ERROR_CRC (0): Source: SIE_STATUS
+    // 0x00000100 [8]     : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+    // 0x00000080 [7]     : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+    // 0x00000040 [6]     : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+    // 0x00000020 [5]     : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+    // 0x00000010 [4]     : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+    // 0x00000008 [3]     : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+    // 0x00000004 [2]     : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+    // 0x00000002 [1]     : HOST_RESUME (0): Host: raised when a device wakes up the host
+    // 0x00000001 [0]     : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
+    io_ro_32 intr;
+
+    _REG_(USB_INTE_OFFSET) // USB_INTE
+    // Interrupt Enable
+    // 0x00080000 [19]    : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+    // 0x00040000 [18]    : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+    // 0x00020000 [17]    : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+    // 0x00010000 [16]    : SETUP_REQ (0): Device
+    // 0x00008000 [15]    : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+    // 0x00004000 [14]    : DEV_SUSPEND (0): Set when the device suspend state changes
+    // 0x00002000 [13]    : DEV_CONN_DIS (0): Set when the device connection state changes
+    // 0x00001000 [12]    : BUS_RESET (0): Source: SIE_STATUS
+    // 0x00000800 [11]    : VBUS_DETECT (0): Source: SIE_STATUS
+    // 0x00000400 [10]    : STALL (0): Source: SIE_STATUS
+    // 0x00000200 [9]     : ERROR_CRC (0): Source: SIE_STATUS
+    // 0x00000100 [8]     : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+    // 0x00000080 [7]     : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+    // 0x00000040 [6]     : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+    // 0x00000020 [5]     : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+    // 0x00000010 [4]     : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+    // 0x00000008 [3]     : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+    // 0x00000004 [2]     : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+    // 0x00000002 [1]     : HOST_RESUME (0): Host: raised when a device wakes up the host
+    // 0x00000001 [0]     : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
+    io_rw_32 inte;
+
+    _REG_(USB_INTF_OFFSET) // USB_INTF
+    // Interrupt Force
+    // 0x00080000 [19]    : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+    // 0x00040000 [18]    : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+    // 0x00020000 [17]    : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+    // 0x00010000 [16]    : SETUP_REQ (0): Device
+    // 0x00008000 [15]    : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+    // 0x00004000 [14]    : DEV_SUSPEND (0): Set when the device suspend state changes
+    // 0x00002000 [13]    : DEV_CONN_DIS (0): Set when the device connection state changes
+    // 0x00001000 [12]    : BUS_RESET (0): Source: SIE_STATUS
+    // 0x00000800 [11]    : VBUS_DETECT (0): Source: SIE_STATUS
+    // 0x00000400 [10]    : STALL (0): Source: SIE_STATUS
+    // 0x00000200 [9]     : ERROR_CRC (0): Source: SIE_STATUS
+    // 0x00000100 [8]     : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+    // 0x00000080 [7]     : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+    // 0x00000040 [6]     : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+    // 0x00000020 [5]     : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+    // 0x00000010 [4]     : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+    // 0x00000008 [3]     : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+    // 0x00000004 [2]     : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+    // 0x00000002 [1]     : HOST_RESUME (0): Host: raised when a device wakes up the host
+    // 0x00000001 [0]     : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
+    io_rw_32 intf;
+
+    _REG_(USB_INTS_OFFSET) // USB_INTS
+    // Interrupt status after masking & forcing
+    // 0x00080000 [19]    : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+    // 0x00040000 [18]    : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+    // 0x00020000 [17]    : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+    // 0x00010000 [16]    : SETUP_REQ (0): Device
+    // 0x00008000 [15]    : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+    // 0x00004000 [14]    : DEV_SUSPEND (0): Set when the device suspend state changes
+    // 0x00002000 [13]    : DEV_CONN_DIS (0): Set when the device connection state changes
+    // 0x00001000 [12]    : BUS_RESET (0): Source: SIE_STATUS
+    // 0x00000800 [11]    : VBUS_DETECT (0): Source: SIE_STATUS
+    // 0x00000400 [10]    : STALL (0): Source: SIE_STATUS
+    // 0x00000200 [9]     : ERROR_CRC (0): Source: SIE_STATUS
+    // 0x00000100 [8]     : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+    // 0x00000080 [7]     : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+    // 0x00000040 [6]     : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+    // 0x00000020 [5]     : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+    // 0x00000010 [4]     : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+    // 0x00000008 [3]     : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+    // 0x00000004 [2]     : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+    // 0x00000002 [1]     : HOST_RESUME (0): Host: raised when a device wakes up the host
+    // 0x00000001 [0]     : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
+    io_ro_32 ints;
+} usb_hw_t;
+
+#define usb_hw ((usb_hw_t *const)USBCTRL_REGS_BASE)
+
+#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE)
+#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE)
+
+static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, "");
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h b/src/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h
new file mode 100644
index 0000000..554d9e4
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h
@@ -0,0 +1,49 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H
+#define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/vreg_and_chip_reset.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_vreg_and_chip_reset
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/vreg_and_chip_reset.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(VREG_AND_CHIP_RESET_VREG_OFFSET) // VREG_AND_CHIP_RESET_VREG
+    // Voltage regulator control and status
+    // 0x00001000 [12]    : ROK (0): regulation status
+    // 0x000000f0 [7:4]   : VSEL (0xb): output voltage select
+    // 0x00000002 [1]     : HIZ (0): high impedance mode select
+    // 0x00000001 [0]     : EN (1): enable
+    io_rw_32 vreg;
+
+    _REG_(VREG_AND_CHIP_RESET_BOD_OFFSET) // VREG_AND_CHIP_RESET_BOD
+    // brown-out detection control
+    // 0x000000f0 [7:4]   : VSEL (0x9): threshold select
+    // 0x00000001 [0]     : EN (1): enable
+    io_rw_32 bod;
+
+    _REG_(VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET) // VREG_AND_CHIP_RESET_CHIP_RESET
+    // Chip reset control and status
+    // 0x01000000 [24]    : PSM_RESTART_FLAG (0): This is set by psm_restart from the debugger
+    // 0x00100000 [20]    : HAD_PSM_RESTART (0): Last reset was from the debug port
+    // 0x00010000 [16]    : HAD_RUN (0): Last reset was from the RUN pin
+    // 0x00000100 [8]     : HAD_POR (0): Last reset was from the power-on reset or brown-out detection blocks
+    io_rw_32 chip_reset;
+} vreg_and_chip_reset_hw_t;
+
+#define vreg_and_chip_reset_hw ((vreg_and_chip_reset_hw_t *const)VREG_AND_CHIP_RESET_BASE)
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/watchdog.h b/src/rp2040/hardware_structs/include/hardware/structs/watchdog.h
new file mode 100644
index 0000000..9579700
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/watchdog.h
@@ -0,0 +1,62 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_WATCHDOG_H
+#define _HARDWARE_STRUCTS_WATCHDOG_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/watchdog.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_watchdog
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL
+    // Watchdog control
+    // 0x80000000 [31]    : TRIGGER (0): Trigger a watchdog reset
+    // 0x40000000 [30]    : ENABLE (0): When not enabled the watchdog timer is paused
+    // 0x04000000 [26]    : PAUSE_DBG1 (1): Pause the watchdog timer when processor 1 is in debug mode
+    // 0x02000000 [25]    : PAUSE_DBG0 (1): Pause the watchdog timer when processor 0 is in debug mode
+    // 0x01000000 [24]    : PAUSE_JTAG (1): Pause the watchdog timer when JTAG is accessing the bus fabric
+    // 0x00ffffff [23:0]  : TIME (0): Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will...
+    io_rw_32 ctrl;
+
+    _REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD
+    // Load the watchdog timer
+    // 0x00ffffff [23:0]  : LOAD (0)
+    io_wo_32 load;
+
+    _REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON
+    // Logs the reason for the last reset
+    // 0x00000002 [1]     : FORCE (0)
+    // 0x00000001 [0]     : TIMER (0)
+    io_ro_32 reason;
+
+    _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0
+    // (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes)
+    //
+    // Scratch register
+    io_rw_32 scratch[8];
+
+    _REG_(WATCHDOG_TICK_OFFSET) // WATCHDOG_TICK
+    // Controls the tick generator
+    // 0x000ff800 [19:11] : COUNT (0): Count down timer: the remaining number clk_tick cycles before the next tick is generated
+    // 0x00000400 [10]    : RUNNING (0): Is the tick generator running?
+    // 0x00000200 [9]     : ENABLE (1): start / stop tick generation
+    // 0x000001ff [8:0]   : CYCLES (0): Total number of clk_tick cycles before the next tick
+    io_rw_32 tick;
+} watchdog_hw_t;
+
+#define watchdog_hw ((watchdog_hw_t *const)WATCHDOG_BASE)
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h b/src/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h
new file mode 100644
index 0000000..21885e8
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h
@@ -0,0 +1,72 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_XIP_CTRL_H
+#define _HARDWARE_STRUCTS_XIP_CTRL_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/xip.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/xip.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+    _REG_(XIP_CTRL_OFFSET) // XIP_CTRL
+    // Cache control
+    // 0x00000008 [3]     : POWER_DOWN (0): When 1, the cache memories are powered down
+    // 0x00000002 [1]     : ERR_BADWRITE (1): When 1, writes to any alias other than 0x0 (caching, allocating)
+    // 0x00000001 [0]     : EN (1): When 1, enable the cache
+    io_rw_32 ctrl;
+
+    _REG_(XIP_FLUSH_OFFSET) // XIP_FLUSH
+    // Cache Flush control
+    // 0x00000001 [0]     : FLUSH (0): Write 1 to flush the cache
+    io_rw_32 flush;
+
+    _REG_(XIP_STAT_OFFSET) // XIP_STAT
+    // Cache Status
+    // 0x00000004 [2]     : FIFO_FULL (0): When 1, indicates the XIP streaming FIFO is completely full
+    // 0x00000002 [1]     : FIFO_EMPTY (1): When 1, indicates the XIP streaming FIFO is completely empty
+    // 0x00000001 [0]     : FLUSH_READY (0): Reads as 0 while a cache flush is in progress, and 1 otherwise
+    io_ro_32 stat;
+
+    _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT
+    // Cache Hit counter
+    io_rw_32 ctr_hit;
+
+    _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC
+    // Cache Access counter
+    io_rw_32 ctr_acc;
+
+    _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR
+    // FIFO stream address
+    // 0xfffffffc [31:2]  : STREAM_ADDR (0): The address of the next word to be streamed from flash to the streaming FIFO
+    io_rw_32 stream_addr;
+
+    _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR
+    // FIFO stream control
+    // 0x003fffff [21:0]  : STREAM_CTR (0): Write a nonzero value to start a streaming read
+    io_rw_32 stream_ctr;
+
+    _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO
+    // FIFO stream data
+    io_ro_32 stream_fifo;
+} xip_ctrl_hw_t;
+
+#define xip_ctrl_hw ((xip_ctrl_hw_t *const)XIP_CTRL_BASE)
+
+#define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS
+#define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS
+#define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS
+
+#endif
diff --git a/src/rp2040/hardware_structs/include/hardware/structs/xosc.h b/src/rp2040/hardware_structs/include/hardware/structs/xosc.h
new file mode 100644
index 0000000..0ff4db4
--- /dev/null
+++ b/src/rp2040/hardware_structs/include/hardware/structs/xosc.h
@@ -0,0 +1,60 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_XOSC_H
+#define _HARDWARE_STRUCTS_XOSC_H
+
+#include "hardware/address_mapped.h"
+#include "hardware/regs/xosc.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xosc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in hardware/regs/xosc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+/// \tag::xosc_hw[]
+typedef struct {
+    _REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL
+    // Crystal Oscillator Control
+    // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to DISABLE and the chip runs from the ROSC
+    // 0x00000fff [11:0]  : FREQ_RANGE (0): Frequency range
+    io_rw_32 ctrl;
+
+    _REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS
+    // Crystal Oscillator Status
+    // 0x80000000 [31]    : STABLE (0): Oscillator is running and stable
+    // 0x01000000 [24]    : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT
+    // 0x00001000 [12]    : ENABLED (0): Oscillator is enabled but not necessarily running and stable, resets to 0
+    // 0x00000003 [1:0]   : FREQ_RANGE (0): The current frequency range setting, always reads 0
+    io_rw_32 status;
+
+    _REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT
+    // Crystal Oscillator pause control
+    io_rw_32 dormant;
+
+    _REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP
+    // Controls the startup delay
+    // 0x00100000 [20]    : X4 (0): Multiplies the startup_delay by 4
+    // 0x00003fff [13:0]  : DELAY (0xc4): in multiples of 256*xtal_period
+    io_rw_32 startup;
+
+    uint32_t _pad0[3];
+
+    _REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT
+    // A down counter running at the xosc frequency which counts to zero and stops
+    // 0x000000ff [7:0]   : COUNT (0)
+    io_rw_32 count;
+} xosc_hw_t;
+
+#define xosc_hw ((xosc_hw_t *const)XOSC_BASE)
+/// \end::xosc_hw[]
+
+#endif
diff --git a/src/rp2_common.cmake b/src/rp2_common.cmake
new file mode 100644
index 0000000..c04e551
--- /dev/null
+++ b/src/rp2_common.cmake
@@ -0,0 +1,59 @@
+# include targets for all for PICO on device
+
+enable_language(ASM)
+
+function(pico_add_hex_output TARGET)
+    add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${TARGET}> $<IF:$<BOOL:$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>>,$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>,$<TARGET_PROPERTY:${TARGET},NAME>>.hex)
+endfunction()
+
+function(pico_add_bin_output TARGET)
+    add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${TARGET}> $<IF:$<BOOL:$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>>,$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>,$<TARGET_PROPERTY:${TARGET},NAME>>.bin)
+endfunction()
+
+function(pico_add_dis_output TARGET)
+    add_custom_command(TARGET ${TARGET} POST_BUILD
+            COMMAND ${CMAKE_OBJDUMP} -h $<TARGET_FILE:${TARGET}> >$<IF:$<BOOL:$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>>,$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>,$<TARGET_PROPERTY:${TARGET},NAME>>.dis
+            COMMAND ${CMAKE_OBJDUMP} -d $<TARGET_FILE:${TARGET}> >>$<IF:$<BOOL:$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>>,$<TARGET_PROPERTY:${TARGET},OUTPUT_NAME>,$<TARGET_PROPERTY:${TARGET},NAME>>.dis
+            )
+endfunction()
+
+function(pico_add_extra_outputs TARGET)
+    pico_add_hex_output(${TARGET})
+    pico_add_bin_output(${TARGET})
+    pico_add_dis_output(${TARGET})
+
+    # PICO_CMAKE_CONFIG: PICO_NO_TARGET_NAME, Don't defined PICO_TARGET_NAME, type=bool, default=0, group=build
+    # PICO_BUILD_DEFINE: PICO_TARGET_NAME, The name of the build target being compiled (unless PICO_NO_TARGET_NAME set in build), type=string, default=target name, group=build
+    if (NOT PICO_NO_TARGET_NAME)
+        target_compile_definitions(${TARGET} PRIVATE
+                PICO_TARGET_NAME="${TARGET}"
+                )
+    endif()
+
+    if (PICO_SYMLINK_ELF_AS_FILENAME)
+        add_custom_target(${TARGET}_symlinked)
+        add_dependencies(${TARGET}_symlinked ${TARGET})
+
+        add_custom_command(TARGET ${TARGET}_symlinked POST_BUILD
+                COMMAND rm -f "${PICO_SYMLINK_ELF_AS_FILENAME}"
+                COMMAND ln -s -r $<TARGET_FILE:${TARGET}> "${PICO_SYMLINK_ELF_AS_FILENAME}"
+                COMMENT "Symlinking from ${PICO_SYMLINK_ELF_AS_FILENAME} to ${TARGET}"
+                )
+    endif ()
+    # PICO_CMAKE_CONFIG: PICO_NO_UF2, Disable UF2 output, type=bool, default=0, group=build
+    if (NOT PICO_NO_UF2)
+        pico_add_uf2_output(${TARGET})
+    endif()
+endfunction()
+
+add_subdirectory(common)
+add_subdirectory(rp2_common)
+
+# PICO_CMAKE_CONFIG: PICO_NO_HARDWARE, OPTION: Whether the build is not targeting an RP2040 device,  type=bool, default=1 for PICO_PLATFORM=host 0 otherwise, group=build
+# PICO_BUILD_DEFINE: PICO_NO_HARDWARE, Whether the build is not targeting an RP2040 device,  type=bool, default=1 for PICO_PLATFORM=host 0 otherwise, group=build
+set(PICO_NO_HARDWARE "0" CACHE INTERNAL "")
+# PICO_CMAKE_CONFIG: PICO_ON_DEVICE, OPTION: Whether the build is targeting an RP2040 device,  type=bool, default=0 for PICO_PLATFORM=host 1 otherwise, group=build
+# PICO_BUILD_DEFIN: PICO_ON_DEVICE, Whether the build is targeting an RP2040 device,  type=bool, default=0 for PICO_PLATFORM=host 1 otherwise, group=build
+set(PICO_ON_DEVICE "1" CACHE INTERNAL "")
+
+set(CMAKE_EXECUTABLE_SUFFIX .elf PARENT_SCOPE)
diff --git a/src/rp2_common/CMakeLists.txt b/src/rp2_common/CMakeLists.txt
new file mode 100644
index 0000000..4ca55be
--- /dev/null
+++ b/src/rp2_common/CMakeLists.txt
@@ -0,0 +1,77 @@
+option(PICO_NO_FLASH "Default binaries to not not use flash")
+option(PICO_COPY_TO_RAM "Default binaries to Copy code to RAM when booting from flash")
+
+set(CMAKE_EXECUTABLE_SUFFIX .elf)
+
+pico_add_subdirectory(hardware_base)
+pico_add_subdirectory(hardware_claim)
+# HAL items which expose a public (inline) functions/macro API above the raw hardware
+pico_add_subdirectory(hardware_adc)
+pico_add_subdirectory(hardware_clocks)
+pico_add_subdirectory(hardware_dma)
+pico_add_subdirectory(hardware_divider)
+pico_add_subdirectory(hardware_exception)
+pico_add_subdirectory(hardware_flash)
+pico_add_subdirectory(hardware_gpio)
+pico_add_subdirectory(hardware_i2c)
+pico_add_subdirectory(hardware_interp)
+pico_add_subdirectory(hardware_irq)
+pico_add_subdirectory(hardware_pio)
+pico_add_subdirectory(hardware_pll)
+pico_add_subdirectory(hardware_pwm)
+pico_add_subdirectory(hardware_resets)
+pico_add_subdirectory(hardware_rtc)
+pico_add_subdirectory(hardware_spi)
+pico_add_subdirectory(hardware_sync)
+pico_add_subdirectory(hardware_timer)
+pico_add_subdirectory(hardware_uart)
+pico_add_subdirectory(hardware_vreg)
+pico_add_subdirectory(hardware_watchdog)
+pico_add_subdirectory(hardware_xosc)
+
+# Helper functions to connect to data/functions in the bootrom
+pico_add_subdirectory(pico_bootrom)
+pico_add_subdirectory(pico_platform)
+
+if (NOT PICO_BARE_METAL)
+    # NOTE THE ORDERING HERE IS IMPORTANT AS SOME TARGETS CHECK ON EXISTENCE OF OTHER TARGETS
+    pico_add_subdirectory(boot_stage2)
+
+    pico_add_subdirectory(pico_bootsel_via_double_reset)
+    pico_add_subdirectory(pico_multicore)
+    pico_add_subdirectory(pico_unique_id)
+
+    pico_add_subdirectory(pico_bit_ops)
+    pico_add_subdirectory(pico_divider)
+    pico_add_subdirectory(pico_double)
+    pico_add_subdirectory(pico_int64_ops)
+    pico_add_subdirectory(pico_float)
+    pico_add_subdirectory(pico_mem_ops)
+    pico_add_subdirectory(pico_malloc)
+    pico_add_subdirectory(pico_printf)
+
+    pico_add_subdirectory(pico_stdio)
+    pico_add_subdirectory(pico_stdio_semihosting)
+    pico_add_subdirectory(pico_stdio_uart)
+
+    pico_add_subdirectory(cmsis)
+    pico_add_subdirectory(tinyusb)
+    pico_add_subdirectory(pico_stdio_usb)
+
+    pico_add_subdirectory(pico_stdlib)
+
+    pico_add_subdirectory(pico_cxx_options)
+    pico_add_subdirectory(pico_standard_link)
+
+    pico_add_subdirectory(pico_fix)
+
+    pico_add_subdirectory(pico_runtime)
+
+endif()
+
+set(CMAKE_EXECUTABLE_SUFFIX "${CMAKE_EXECUTABLE_SUFFIX}" PARENT_SCOPE)
+
+pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR})
+pico_add_doxygen_exclude(${CMAKE_CURRENT_LIST_DIR}/cmsis)
+
+pico_promote_common_scope_vars()
\ No newline at end of file
diff --git a/src/rp2_common/README.md b/src/rp2_common/README.md
new file mode 100644
index 0000000..b893801
--- /dev/null
+++ b/src/rp2_common/README.md
@@ -0,0 +1,8 @@
+This directory contains libraries specifically targeting the RP2040 or possible future related devices. It is selected when
+`PICO_PLATFORM=rp2040` (the default) is specified for the build
+
+`hardware_` libraries exist for individual hardware components to provide a simple API
+providing a thin abstraction hiding the details of accessing the hardware registers directly.
+
+`pico_` provides higher level functionality you might generally find in say an OS kernel, as well
+as runtime support familiar to most C programmers.
diff --git a/src/rp2_common/boot_stage2/CMakeLists.txt b/src/rp2_common/boot_stage2/CMakeLists.txt
new file mode 100644
index 0000000..a2f3960
--- /dev/null
+++ b/src/rp2_common/boot_stage2/CMakeLists.txt
@@ -0,0 +1,107 @@
+# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2_FILE, Default boot stage 2 file to use unless overridden by pico_set_boot_stage2 on the TARGET; this setting is useful when explicitly setting the default build from a per board CMake file, group=build
+# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2, Simpler alternative to specifying PICO_DEFAULT_BOOT_STAGE2_FILE where the file is src/rp2_common/boot_stage2/{PICO_DEFAULT_BOOT_STAGE2}.S, default=compile_time_choice, group=build
+
+if (DEFINED ENV{PICO_DEFAULT_BOOT_STAGE2_FILE})
+    set(PICO_DEFAULT_BOOT_STAGE2_FILE $ENV{PICO_DEFAULT_BOOT_STAGE2_FILE})
+    message("Using PICO_DEFAULT_BOOT_STAGE2_FILE from environment ('${PICO_DEFAULT_BOOT_STAGE2_FILE}')")
+elseif (PICO_DEFAULT_BOOT_STAGE2_FILE)
+    # explicitly set, so cache it
+    set(PICO_DEFAULT_BOOT_STAGE2_FILE "${PICO_DEFAULT_BOOT_STAGE2_FILE}" CACHE STRING "boot stage 2 source file" FORCE)
+endif()
+
+set(PICO_BOOT_STAGE2_COMPILE_TIME_CHOICE_NAME compile_time_choice) # local var
+if (NOT PICO_DEFAULT_BOOT_STAGE2_FILE)
+    if (DEFINED ENV{PICO_DEFAULT_BOOT_STAGE2})
+        set(PICO_DEFAULT_BOOT_STAGE2 $ENV{PICO_DEFAULT_BOOT_STAGE2})
+        message("Using PICO_DEFAULT_BOOT_STAGE2 from environment ('${PICO_DEFAULT_BOOT_STAGE2}')")
+    endif()
+    if (NOT DEFINED PICO_DEFAULT_BOOT_STAGE2)
+        set(PICO_DEFAULT_BOOT_STAGE2 ${PICO_BOOT_STAGE2_COMPILE_TIME_CHOICE_NAME})
+    endif()
+    set(PICO_DEFAULT_BOOT_STAGE2 "${PICO_DEFAULT_BOOT_STAGE2}" CACHE STRING "boot stage 2 short name" FORCE)
+    set(PICO_DEFAULT_BOOT_STAGE2_FILE "${CMAKE_CURRENT_LIST_DIR}/${PICO_DEFAULT_BOOT_STAGE2}.S")
+endif()
+
+if (NOT EXISTS ${PICO_DEFAULT_BOOT_STAGE2_FILE})
+    message(FATAL_ERROR "Specified boot stage 2 source '${PICO_DEFAULT_BOOT_STAGE2_FILE}' does not exist.")
+endif()
+pico_register_common_scope_var(PICO_DEFAULT_BOOT_STAGE2_FILE)
+
+# needed by function below
+set(PICO_BOOT_STAGE2_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "")
+
+add_library(boot_stage2_headers INTERFACE)
+target_include_directories(boot_stage2_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+# by convention the first source file name without extension is used for the binary info name
+function(pico_define_boot_stage2 NAME SOURCES)
+    add_executable(${NAME}
+            ${SOURCES}
+    )
+
+    # todo bit of an abstraction failure - revisit for Clang support anyway
+    if (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+        target_link_options(${NAME} PRIVATE "-nostdlib")
+    else ()
+        target_link_options(${NAME} PRIVATE "--specs=nosys.specs")
+        target_link_options(${NAME} PRIVATE "-nostartfiles")
+    endif ()
+
+    # boot2_helpers include dir
+    target_include_directories(${NAME} PRIVATE ${PICO_BOOT_STAGE2_DIR}/asminclude)
+
+    target_link_libraries(${NAME} hardware_regs boot_stage2_headers)
+    target_link_options(${NAME} PRIVATE "LINKER:--script=${PICO_BOOT_STAGE2_DIR}/boot_stage2.ld")
+    set_target_properties(${NAME} PROPERTIES LINK_DEPENDS ${PICO_BOOT_STAGE2_DIR}/boot_stage2.ld)
+
+    pico_add_dis_output(${NAME})
+    pico_add_map_output(${NAME})
+
+    set(ORIGINAL_BIN ${CMAKE_CURRENT_BINARY_DIR}/${NAME}.bin)
+    set(PADDED_CHECKSUMMED_ASM ${CMAKE_CURRENT_BINARY_DIR}/${NAME}_padded_checksummed.S)
+
+    find_package (Python3 REQUIRED COMPONENTS Interpreter)
+
+    add_custom_target(${NAME}_bin DEPENDS ${ORIGINAL_BIN})
+    add_custom_command(OUTPUT ${ORIGINAL_BIN} DEPENDS ${NAME} COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${NAME}> ${ORIGINAL_BIN})
+
+    add_custom_target(${NAME}_padded_checksummed_asm DEPENDS ${PADDED_CHECKSUMMED_ASM})
+    add_custom_command(OUTPUT ${PADDED_CHECKSUMMED_ASM} DEPENDS ${ORIGINAL_BIN}
+            COMMAND ${Python3_EXECUTABLE} ${PICO_BOOT_STAGE2_DIR}/pad_checksum -s 0xffffffff ${ORIGINAL_BIN} ${PADDED_CHECKSUMMED_ASM}
+            )
+
+    add_library(${NAME}_library INTERFACE)
+    add_dependencies(${NAME}_library ${NAME}_padded_checksummed_asm)
+    # not strictly (or indeed actually) a link library, but this avoids dependency cycle
+    target_link_libraries(${NAME}_library INTERFACE ${PADDED_CHECKSUMMED_ASM})
+    target_link_libraries(${NAME}_library INTERFACE boot_stage2_headers)
+
+    list(GET SOURCES 0 FIRST_SOURCE)
+    get_filename_component(BOOT_STAGE2_BI_NAME ${FIRST_SOURCE} NAME_WE)
+
+    # we only set the PICO_BUILD_STAGE2_NAME if it isn't 'compile_time_choice'
+    if (NOT BOOT_STAGE2_BI_NAME STREQUAL PICO_BOOT_STAGE2_COMPILE_TIME_CHOICE_NAME)
+        target_compile_definitions(${NAME} INTERFACE
+                -DPICO_BUILD_BOOT_STAGE2_NAME="${BOOT_STAGE2_BI_NAME}")
+        target_compile_definitions(${NAME}_library INTERFACE
+                -DPICO_BUILD_BOOT_STAGE2_NAME="${BOOT_STAGE2_BI_NAME}")
+    endif()
+endfunction()
+
+macro(pico_set_boot_stage2 TARGET NAME)
+    get_target_property(target_type ${TARGET} TYPE)
+    if ("EXECUTABLE" STREQUAL "${target_type}")
+        set_target_properties(${TARGET} PROPERTIES PICO_TARGET_BOOT_STAGE2 "${NAME}")
+    else()
+        message(FATAL_ERROR "boot stage 2 implementation must be set on executable not library")
+    endif()
+endmacro()
+
+pico_define_boot_stage2(bs2_default ${PICO_DEFAULT_BOOT_STAGE2_FILE})
+
+# Create a new boot stage 2 target using the default implementation for the current build (PICO_BOARD derived)
+function(pico_clone_default_boot_stage2 NAME)
+    pico_define_boot_stage2(${NAME} ${PICO_DEFAULT_BOOT_STAGE2_FILE})
+endfunction()
+
+pico_promote_common_scope_vars()
\ No newline at end of file
diff --git a/src/rp2_common/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S b/src/rp2_common/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S
new file mode 100644
index 0000000..6f06fc1
--- /dev/null
+++ b/src/rp2_common/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOOT2_HELPER_EXIT_FROM_BOOT2
+#define _BOOT2_HELPER_EXIT_FROM_BOOT2
+
+#include "hardware/regs/m0plus.h"
+
+// If entered from the bootrom, lr (which we earlier pushed) will be 0,
+// and we vector through the table at the start of the main flash image.
+// Any regular function call will have a nonzero value for lr.
+check_return:
+    pop {r0}
+    cmp r0, #0
+    beq vector_into_flash
+    bx r0
+vector_into_flash:
+    ldr r0, =(XIP_BASE + 0x100)
+    ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET)
+    str r0, [r1]
+    ldmia r0, {r0, r1}
+    msr msp, r0
+    bx r1
+
+#endif
diff --git a/src/rp2_common/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S b/src/rp2_common/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S
new file mode 100644
index 0000000..83698ed
--- /dev/null
+++ b/src/rp2_common/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOOT2_HELPER_READ_FLASH_SREG
+#define _BOOT2_HELPER_READ_FLASH_SREG
+
+#include "boot2_helpers/wait_ssi_ready.S"
+
+// Pass status read cmd into r0.
+// Returns status value in r0.
+.global read_flash_sreg
+.type read_flash_sreg,%function
+.thumb_func
+read_flash_sreg:
+    push {r1, lr}
+    str r0, [r3, #SSI_DR0_OFFSET]
+    // Dummy byte:
+    str r0, [r3, #SSI_DR0_OFFSET]
+    
+    bl wait_ssi_ready
+    // Discard first byte and combine the next two
+    ldr r0, [r3, #SSI_DR0_OFFSET]
+    ldr r0, [r3, #SSI_DR0_OFFSET]
+
+    pop {r1, pc}
+
+#endif
diff --git a/src/rp2_common/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S b/src/rp2_common/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S
new file mode 100644
index 0000000..2e49b64
--- /dev/null
+++ b/src/rp2_common/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOOT2_HELPER_WAIT_SSI_READY
+#define _BOOT2_HELPER_WAIT_SSI_READY
+
+wait_ssi_ready:
+    push {r0, r1, lr}
+
+    // Command is complete when there is nothing left to send
+    // (TX FIFO empty) and SSI is no longer busy (CSn deasserted)
+1:
+    ldr r1, [r3, #SSI_SR_OFFSET]
+    movs r0, #SSI_SR_TFE_BITS
+    tst r1, r0
+    beq 1b
+    movs r0, #SSI_SR_BUSY_BITS
+    tst r1, r0
+    bne 1b
+
+    pop {r0, r1, pc}
+
+#endif
diff --git a/src/rp2_common/boot_stage2/boot2_at25sf128a.S b/src/rp2_common/boot_stage2/boot2_at25sf128a.S
new file mode 100644
index 0000000..be232ff
--- /dev/null
+++ b/src/rp2_common/boot_stage2/boot2_at25sf128a.S
@@ -0,0 +1,285 @@
+// ----------------------------------------------------------------------------
+// Second stage boot code
+// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// Device:      Adesto AT25SF128A
+//              Based on W25Q080 code: main difference is the QE bit is being set
+//              via command 0x31
+//
+// Description: Configures AT25SF128A to run in Quad I/O continuous read XIP mode
+//
+// Details:     * Check status register 2 to determine if QSPI mode is enabled,
+//                and perform an SR2 programming cycle if necessary.
+//              * Use SSI to perform a dummy 0xEB read command, with the mode
+//                continuation bits set, so that the flash will not require
+//                0xEB instruction prefix on subsequent reads.
+//              * Configure SSI to write address, mode bits, but no instruction.
+//                SSI + flash are now jointly in a state where continuous reads
+//                can take place.
+//              * Jump to exit pointer passed in via lr. Bootrom passes null,
+//                in which case this code uses a default 256 byte flash offset
+//
+// Building:    * This code must be position-independent, and use stack only
+//              * The code will be padded to a size of 256 bytes, including a
+//                4-byte checksum. Therefore code size cannot exceed 252 bytes.
+// ----------------------------------------------------------------------------
+
+#include "pico/asm_helper.S"
+#include "hardware/regs/addressmap.h"
+#include "hardware/regs/ssi.h"
+#include "hardware/regs/pads_qspi.h"
+
+// ----------------------------------------------------------------------------
+// Config section
+// ----------------------------------------------------------------------------
+// It should be possible to support most flash devices by modifying this section
+
+// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
+// This must be a positive, even integer.
+// The bootrom is very conservative with SPI frequency, but here we should be
+// as aggressive as possible.
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 4
+#endif
+#if PICO_FLASH_SPI_CLKDIV & 1
+#error PICO_FLASH_SPI_CLKDIV must be even
+#endif
+
+// Define interface width: single/dual/quad IO
+#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
+
+// For W25Q080 this is the "Read data fast quad IO" instruction:
+#define CMD_READ 0xeb
+
+// "Mode bits" are 8 special bits sent immediately after
+// the address bits in a "Read Data Fast Quad I/O" command sequence. 
+// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
+// next read does not require the 0xeb instruction prefix.
+#define MODE_CONTINUOUS_READ 0x20
+
+// The number of address + mode bits, divided by 4 (always 4, not function of
+// interface width).
+#define ADDR_L 8
+
+// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles
+// are required.
+#define WAIT_CYCLES 4
+
+// If defined, we will read status reg, compare to SREG_DATA, and overwrite
+// with our value if the SR doesn't match.
+// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to
+// SR2 (31h cmd) as the latter command isn't supported by WX25Q080.
+// This isn't great because it will remove block protections.
+// A better solution is to use a volatile SR write if your device supports it.
+#define PROGRAM_STATUS_REG
+
+#define CMD_WRITE_ENABLE 0x06
+#define CMD_READ_STATUS 0x05
+#define CMD_READ_STATUS2 0x35
+#define CMD_WRITE_STATUS 0x01
+#define CMD_WRITE_STATUS2 0x31
+#define SREG_DATA 0x02  // Enable quad-SPI mode
+
+// ----------------------------------------------------------------------------
+// Start of 2nd Stage Boot Code
+// ----------------------------------------------------------------------------
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.section .text
+
+// The exit point is passed in lr. If entered from bootrom, this will be the
+// flash address immediately following this second stage (0x10000100).
+// Otherwise it will be a return address -- second stage being called as a
+// function by user code, after copying out of XIP region. r3 holds SSI base,
+// r0...2 used as temporaries. Other GPRs not used.
+.global _stage2_boot
+.type _stage2_boot,%function
+.thumb_func
+_stage2_boot:
+    push {lr}
+
+    // Set pad configuration:
+    // - SCLK 8mA drive, no slew limiting
+    // - SDx disable input Schmitt to reduce delay
+
+    ldr r3, =PADS_QSPI_BASE
+    movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS)
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
+    ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
+    movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS
+    bics r0, r1
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET]
+
+    ldr r3, =XIP_SSI_BASE
+
+    // Disable SSI to allow further config
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    // Set baud rate
+    movs r1, #PICO_FLASH_SPI_CLKDIV
+    str r1, [r3, #SSI_BAUDR_OFFSET]
+
+    // Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means,
+    // if the flash launches data on SCLK posedge, we capture it at the time that
+    // the next SCLK posedge is launched. This is shortly before that posedge
+    // arrives at the flash, so data hold time should be ok. For
+    // PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect.
+
+    movs r1, #1
+    movs r2, #SSI_RX_SAMPLE_DLY_OFFSET  // == 0xf0 so need 8 bits of offset significance
+    str r1, [r3, r2]
+
+
+// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
+// (i.e. turn WPn and HOLDn into IO2/IO3)
+#ifdef PROGRAM_STATUS_REG
+program_sregs:
+#define CTRL0_SPI_TXRX \
+    (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \
+    (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB)
+
+    ldr r1, =(CTRL0_SPI_TXRX)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+     // Enable SSI and select slave 0
+    movs r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    // Check whether SR needs updating
+    movs r0, #CMD_READ_STATUS2
+    bl read_flash_sreg
+    movs r2, #SREG_DATA
+    cmp r0, r2
+    beq skip_sreg_programming
+
+    // Send write enable command
+    movs r1, #CMD_WRITE_ENABLE
+    str r1, [r3, #SSI_DR0_OFFSET]
+
+    // Poll for completion and discard RX
+    bl wait_ssi_ready
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+
+    // Send status write command followed by data bytes
+    movs r1, #CMD_WRITE_STATUS2
+    str r1, [r3, #SSI_DR0_OFFSET]
+    str r2, [r3, #SSI_DR0_OFFSET]
+
+    bl wait_ssi_ready
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+
+    // Poll status register for write completion
+1:
+    movs r0, #CMD_READ_STATUS
+    bl read_flash_sreg
+    movs r1, #1
+    tst r0, r1
+    bne 1b
+
+skip_sreg_programming:
+
+    // Disable SSI again so that it can be reconfigured
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+#endif
+
+// Currently the flash expects an 8 bit serial command prefix on every
+// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O
+// command, with mode bits set such that the flash will not expect a serial
+// command prefix on *subsequent* transfers. We don't care about the results
+// of the read, the important part is the mode bits.
+
+dummy_read:
+#define CTRLR0_ENTER_XIP \
+    (FRAME_FORMAT                          /* Quad I/O mode */                \
+        << SSI_CTRLR0_SPI_FRF_LSB) |                                          \
+    (31 << SSI_CTRLR0_DFS_32_LSB)  |       /* 32 data bits */                 \
+    (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ     /* Send INST/ADDR, Receive Data */ \
+        << SSI_CTRLR0_TMOD_LSB)
+
+    ldr r1, =(CTRLR0_ENTER_XIP)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+    movs r1, #0x0                    // NDF=0 (single 32b read)
+    str r1, [r3, #SSI_CTRLR1_OFFSET]
+
+#define SPI_CTRLR0_ENTER_XIP \
+    (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |     /* Address + mode bits */ \
+    (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_8B \
+        << SSI_SPI_CTRLR0_INST_L_LSB) |        /* 8-bit instruction */ \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A      /* Send Command in serial mode then address in Quad I/O mode */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_ENTER_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)  // SPI_CTRL0 Register
+    str r1, [r0]
+
+    movs r1, #1                      // Re-enable SSI
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    movs r1, #CMD_READ
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push SPI command into TX FIFO
+    movs r1, #MODE_CONTINUOUS_READ   // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push Address into TX FIFO - this will trigger the transaction
+
+    // Poll for completion
+    bl wait_ssi_ready
+
+// The flash is in a state where we can blast addresses in parallel, and get
+// parallel data back. Now configure the SSI to translate XIP bus accesses
+// into QSPI transfers of this form.
+
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Disable SSI (and clear FIFO) to allow further config
+
+// Note that the INST_L field is used to select what XIP data gets pushed into
+// the TX FIFO:
+//      INST_L_0_BITS   {ADDR[23:0],XIP_CMD[7:0]}       Load "mode bits" into XIP_CMD
+//      Anything else   {XIP_CMD[7:0],ADDR[23:0]}       Load SPI command into XIP_CMD
+configure_ssi:
+#define SPI_CTRLR0_XIP \
+    (MODE_CONTINUOUS_READ                      /* Mode bits to keep flash in continuous read mode */ \
+        << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
+    (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |    /* Total number of address + mode bits */ \
+    (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) |    /* Hi-Z dummy clocks following address + mode */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_NONE          /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
+        << SSI_SPI_CTRLR0_INST_L_LSB) | \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A      /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
+    str r1, [r0]
+
+    movs r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Re-enable SSI
+
+// Bus accesses to the XIP window will now be transparently serviced by the
+// external flash on cache miss. We are ready to run code from flash.
+
+// Pull in standard exit routine
+#include "boot2_helpers/exit_from_boot2.S"
+
+// Common functions
+#include "boot2_helpers/wait_ssi_ready.S"
+#ifdef PROGRAM_STATUS_REG
+#include "boot2_helpers/read_flash_sreg.S"
+#endif
+
+.global literals
+literals:
+.ltorg
+
+.end
diff --git a/src/rp2_common/boot_stage2/boot2_generic_03h.S b/src/rp2_common/boot_stage2/boot2_generic_03h.S
new file mode 100644
index 0000000..a10e66a
--- /dev/null
+++ b/src/rp2_common/boot_stage2/boot2_generic_03h.S
@@ -0,0 +1,103 @@
+// ----------------------------------------------------------------------------
+// Second stage boot code
+// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// Device:      Anything which responds to 03h serial read command
+//
+// Details:     * Configure SSI to translate each APB read into a 03h command
+//              * 8 command clocks, 24 address clocks and 32 data clocks
+//              * This enables you to boot from almost anything: you can pretty
+//                much solder a potato to your PCB, or a piece of cheese
+//              * The tradeoff is performance around 3x worse than QSPI XIP
+//
+// Building:    * This code must be position-independent, and use stack only
+//              * The code will be padded to a size of 256 bytes, including a
+//                4-byte checksum. Therefore code size cannot exceed 252 bytes.
+// ----------------------------------------------------------------------------
+
+#include "pico/asm_helper.S"
+#include "hardware/regs/addressmap.h"
+#include "hardware/regs/ssi.h"
+
+// ----------------------------------------------------------------------------
+// Config section
+// ----------------------------------------------------------------------------
+// It should be possible to support most flash devices by modifying this section
+
+// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
+// This must be a positive, even integer.
+// The bootrom is very conservative with SPI frequency, but here we should be
+// as aggressive as possible.
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 4
+#endif
+
+#define CMD_READ 0x03
+
+// Value is number of address bits divided by 4
+#define ADDR_L 6
+
+#define CTRLR0_XIP \
+    (SSI_CTRLR0_SPI_FRF_VALUE_STD << SSI_CTRLR0_SPI_FRF_LSB) |  /* Standard 1-bit SPI serial frames */ \
+    (31 << SSI_CTRLR0_DFS_32_LSB)  |                            /* 32 clocks per data frame */ \
+    (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ  << SSI_CTRLR0_TMOD_LSB) /* Send instr + addr, receive data */
+
+#define SPI_CTRLR0_XIP \
+    (CMD_READ << SSI_SPI_CTRLR0_XIP_CMD_LSB) |        /* Value of instruction prefix */ \
+    (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |           /* Total number of address + mode bits */ \
+    (2 << SSI_SPI_CTRLR0_INST_L_LSB) |                /* 8 bit command prefix (field value is bits divided by 4) */ \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) /* command and address both in serial format */
+
+// ----------------------------------------------------------------------------
+// Start of 2nd Stage Boot Code
+// ----------------------------------------------------------------------------
+
+.cpu cortex-m0
+.thumb
+
+.section .text
+
+.global _stage2_boot
+.type _stage2_boot,%function
+.thumb_func
+_stage2_boot:
+    push {lr}
+
+    ldr r3, =XIP_SSI_BASE                // Use as base address where possible
+
+    // Disable SSI to allow further config
+    mov r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    // Set baud rate
+    mov r1, #PICO_FLASH_SPI_CLKDIV
+    str r1, [r3, #SSI_BAUDR_OFFSET]
+
+    ldr r1, =(CTRLR0_XIP)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+    ldr r1, =(SPI_CTRLR0_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
+    str r1, [r0]
+
+    // NDF=0 (single 32b read)
+    mov r1, #0x0
+    str r1, [r3, #SSI_CTRLR1_OFFSET]
+
+    // Re-enable SSI
+    mov r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+// We are now in XIP mode. Any bus accesses to the XIP address window will be
+// translated by the SSI into 03h read commands to the external flash (if cache is missed),
+// and the data will be returned to the bus.
+
+// Pull in standard exit routine
+#include "boot2_helpers/exit_from_boot2.S"
+
+.global literals
+literals:
+.ltorg
+
+.end
diff --git a/src/rp2_common/boot_stage2/boot2_is25lp080.S b/src/rp2_common/boot_stage2/boot2_is25lp080.S
new file mode 100644
index 0000000..80bf9d1
--- /dev/null
+++ b/src/rp2_common/boot_stage2/boot2_is25lp080.S
@@ -0,0 +1,262 @@
+// ----------------------------------------------------------------------------
+// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// Device:      ISSI IS25LP080D
+//              Based on W25Q080 code: main difference is the QE bit being in
+//              SR1 instead of SR2.
+//
+// Description: Configures IS25LP080D to run in Quad I/O continuous read XIP mode
+//
+// Details:     * Check status register to determine if QSPI mode is enabled,
+//                and perform an SR programming cycle if necessary.
+//              * Use SSI to perform a dummy 0xEB read command, with the mode
+//                continuation bits set, so that the flash will not require
+//                0xEB instruction prefix on subsequent reads.
+//              * Configure SSI to write address, mode bits, but no instruction.
+//                SSI + flash are now jointly in a state where continuous reads
+//                can take place.
+//              * Set VTOR = 0x10000100 (user vector table immediately after
+//                this boot2 image).
+//              * Read stack pointer (MSP) and reset vector from the flash
+//                vector table; set SP and jump, as though the processor had
+//                booted directly from flash.
+//
+// Building:    * This code must be linked to run at 0x20027f00
+//              * The code will be padded to a size of 256 bytes, including a
+//                4-byte checksum. Therefore code size cannot exceed 252 bytes.
+// ----------------------------------------------------------------------------
+
+#include "pico/asm_helper.S"
+#include "hardware/regs/addressmap.h"
+#include "hardware/regs/ssi.h"
+
+// ----------------------------------------------------------------------------
+// Config section
+// ----------------------------------------------------------------------------
+// It should be possible to support most flash devices by modifying this section
+
+// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
+// This must be a positive, even integer.
+// The bootrom is very conservative with SPI frequency, but here we should be
+// as aggressive as possible.
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 4
+#endif
+
+
+// Define interface width: single/dual/quad IO
+#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
+
+// For W25Q080 this is the "Read data fast quad IO" instruction:
+#define CMD_READ 0xeb
+
+// "Mode bits" are 8 special bits sent immediately after
+// the address bits in a "Read Data Fast Quad I/O" command sequence. 
+// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
+// next read does not require the 0xeb instruction prefix.
+#define MODE_CONTINUOUS_READ 0xa0
+
+// The number of address + mode bits, divided by 4 (always 4, not function of
+// interface width).
+#define ADDR_L 8
+
+// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles
+// are required.
+#define WAIT_CYCLES 4
+
+// If defined, we will read status reg, compare to SREG_DATA, and overwrite
+// with our value if the SR doesn't match.
+// This isn't great because it will remove block protections.
+// A better solution is to use a volatile SR write if your device supports it.
+#define PROGRAM_STATUS_REG
+
+#define CMD_WRITE_ENABLE 0x06
+#define CMD_READ_STATUS 0x05
+#define CMD_WRITE_STATUS 0x01
+#define SREG_DATA 0x40  // Enable quad-SPI mode
+
+// ----------------------------------------------------------------------------
+// Start of 2nd Stage Boot Code
+// ----------------------------------------------------------------------------
+
+.cpu cortex-m0
+.thumb
+
+.section .text
+
+.global _stage2_boot
+.type _stage2_boot,%function
+.thumb_func
+_stage2_boot:
+    push {lr}
+
+    ldr r3, =XIP_SSI_BASE                // Use as base address where possible
+
+    // Disable SSI to allow further config
+    mov r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    // Set baud rate
+    mov r1, #PICO_FLASH_SPI_CLKDIV
+    str r1, [r3, #SSI_BAUDR_OFFSET]
+
+// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
+// (i.e. turn WPn and HOLDn into IO2/IO3)
+#ifdef PROGRAM_STATUS_REG
+program_sregs:
+#define CTRL0_SPI_TXRX \
+    (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \
+    (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB)
+
+    ldr r1, =(CTRL0_SPI_TXRX)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+     // Enable SSI and select slave 0
+    mov r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    // Check whether SR needs updating
+    ldr r0, =CMD_READ_STATUS
+    bl read_flash_sreg
+    ldr r2, =SREG_DATA
+    cmp r0, r2
+    beq skip_sreg_programming
+
+    // Send write enable command
+    mov r1, #CMD_WRITE_ENABLE
+    str r1, [r3, #SSI_DR0_OFFSET]
+
+    // Poll for completion and discard RX
+    bl wait_ssi_ready
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+
+    // Send status write command followed by data bytes
+    mov r1, #CMD_WRITE_STATUS
+    str r1, [r3, #SSI_DR0_OFFSET]
+    mov r0, #0
+    str r2, [r3, #SSI_DR0_OFFSET]
+
+    bl wait_ssi_ready
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+
+    // Poll status register for write completion
+1:
+    ldr r0, =CMD_READ_STATUS
+    bl read_flash_sreg
+    mov r1, #1
+    tst r0, r1
+    bne 1b
+
+skip_sreg_programming:
+
+    // Send a 0xA3 high-performance-mode instruction
+//    ldr r1, =0xa3
+//    str r1, [r3, #SSI_DR0_OFFSET]
+//    bl wait_ssi_ready
+
+    // Disable SSI again so that it can be reconfigured
+    mov r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+#endif
+
+
+// First we need to send the initial command to get us in to Fast Read Quad I/O
+// mode.  As this transaction requires a command, we can't send it in XIP mode.
+// To enter Continuous Read mode as well we need to append 4'b0010 to the address
+// bits and then add a further 4 don't care bits.  We will construct this by
+// specifying a 28-bit address, with the least significant bits being 4'b0010.
+// This is just a dummy transaction so we'll perform a read from address zero
+// and then discard what comes back.  All we really care about is that at the
+// end of the transaction, the flash device is in Continuous Read mode
+// and from then on will only expect to receive addresses.
+dummy_read:
+#define CTRLR0_ENTER_XIP \
+    (FRAME_FORMAT                          /* Quad I/O mode */                \
+        << SSI_CTRLR0_SPI_FRF_LSB) |                                          \
+    (31 << SSI_CTRLR0_DFS_32_LSB)  |       /* 32 data bits */                 \
+    (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ     /* Send INST/ADDR, Receive Data */ \
+        << SSI_CTRLR0_TMOD_LSB)
+
+    ldr r1, =(CTRLR0_ENTER_XIP)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+    mov r1, #0x0                    // NDF=0 (single 32b read)
+    str r1, [r3, #SSI_CTRLR1_OFFSET]
+
+#define SPI_CTRLR0_ENTER_XIP \
+    (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |     /* Address + mode bits */ \
+    (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_8B \
+        << SSI_SPI_CTRLR0_INST_L_LSB) |        /* 8-bit instruction */ \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A      /* Send Command in serial mode then address in Quad I/O mode */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_ENTER_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)  // SPI_CTRL0 Register
+    str r1, [r0]
+
+    mov r1, #1                      // Re-enable SSI
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    mov r1, #CMD_READ 
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push SPI command into TX FIFO
+    mov r1, #MODE_CONTINUOUS_READ   // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push Address into TX FIFO - this will trigger the transaction
+
+    // Poll for completion
+    bl wait_ssi_ready
+
+// At this point CN# will be deasserted and the SPI clock will not be running.
+// The Winbond WX25X10CL device will be in continuous read, dual I/O mode and
+// only expecting address bits after the next CN# assertion.  So long as we
+// send 4'b0010 (and 4 more dummy HiZ bits) after every subsequent 24b address
+// then the Winbond device will remain in continuous read mode.  This is the
+// ideal mode for Execute-In-Place.
+// (If we want to exit continuous read mode then we will need to switch back
+// to APM mode and generate a 28-bit address phase with the extra nibble set
+// to 4'b0000).
+
+    mov r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Disable SSI (and clear FIFO) to allow further config
+
+// Note that the INST_L field is used to select what XIP data gets pushed into
+// the TX FIFO:
+//      INST_L_0_BITS   {ADDR[23:0],XIP_CMD[7:0]}       Load "mode bits" into XIP_CMD
+//      Anything else   {XIP_CMD[7:0],ADDR[23:0]}       Load SPI command into XIP_CMD
+configure_ssi:
+#define SPI_CTRLR0_XIP \
+    (MODE_CONTINUOUS_READ                      /* Mode bits to keep flash in continuous read mode */ \
+        << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
+    (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |    /* Total number of address + mode bits */ \
+    (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) |    /* Hi-Z dummy clocks following address + mode */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_NONE          /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
+        << SSI_SPI_CTRLR0_INST_L_LSB) | \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A      /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
+    str r1, [r0]
+
+    mov r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Re-enable SSI
+
+// We are now in XIP mode, with all transactions using Dual I/O and only
+// needing to send 24-bit addresses (plus mode bits) for each read transaction.
+
+// Pull in standard exit routine
+#include "boot2_helpers/exit_from_boot2.S"
+
+// Common functions
+#include "boot2_helpers/wait_ssi_ready.S"
+#ifdef PROGRAM_STATUS_REG
+#include "boot2_helpers/read_flash_sreg.S"
+#endif
+
+.global literals
+literals:
+.ltorg
+
+.end
diff --git a/src/rp2_common/boot_stage2/boot2_usb_blinky.S b/src/rp2_common/boot_stage2/boot2_usb_blinky.S
new file mode 100644
index 0000000..74c47a3
--- /dev/null
+++ b/src/rp2_common/boot_stage2/boot2_usb_blinky.S
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// Stub second stage which calls into USB bootcode, with parameters.
+// USB boot takes two parameters:
+// - A GPIO mask for activity LED -- if mask is 0, don't touch GPIOs at all
+// - A mask of interfaces to disable. Bit 0 disables MSC, bit 1 disables PICOBoot
+// The bootrom passes 0 for both of these parameters, but user code (or this
+// second stage) can pass anything.
+
+#define USB_BOOT_MSD_AND_PICOBOOT 0x0
+#define USB_BOOT_MSD_ONLY 0x2
+#define USB_BOOT_PICOBOOT_ONLY 0x1
+
+// Config
+#define ACTIVITY_LED 0
+#define BOOT_MODE USB_BOOT_MSD_AND_PICOBOOT
+
+.cpu cortex-m0
+.thumb
+
+.section .text
+
+.global _stage2_boot
+.type _stage2_boot,%function
+
+.thumb_func
+_stage2_boot:
+    mov r7, #0x14               // Pointer to _well_known pointer table in ROM
+    ldrh r0, [r7, #0]           // Offset 0 is 16 bit pointer to function table
+    ldrh r7, [r7, #4]           // Offset 4 is 16 bit pointer to table lookup routine
+    ldr r1, =('U' | ('B' << 8)) // Symbol for USB Boot
+    blx r7
+    cmp r0, #0
+    beq dead
+
+    mov r7, r0
+    ldr r0, =(1u << ACTIVITY_LED) // Mask of which GPIO (or GPIOs) to use
+    mov r1, #BOOT_MODE
+    blx r7
+
+dead:
+    wfi
+    b dead
+
+.global literals
+literals:
+.ltorg
+
+.end
diff --git a/src/rp2_common/boot_stage2/boot2_w25q080.S b/src/rp2_common/boot_stage2/boot2_w25q080.S
new file mode 100644
index 0000000..ad3238e
--- /dev/null
+++ b/src/rp2_common/boot_stage2/boot2_w25q080.S
@@ -0,0 +1,287 @@
+// ----------------------------------------------------------------------------
+// Second stage boot code
+// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// Device:      Winbond W25Q080
+//              Also supports W25Q16JV (which has some different SR instructions)
+//              Also supports AT25SF081
+//              Also supports S25FL132K0
+//
+// Description: Configures W25Q080 to run in Quad I/O continuous read XIP mode
+//
+// Details:     * Check status register 2 to determine if QSPI mode is enabled,
+//                and perform an SR2 programming cycle if necessary.
+//              * Use SSI to perform a dummy 0xEB read command, with the mode
+//                continuation bits set, so that the flash will not require
+//                0xEB instruction prefix on subsequent reads.
+//              * Configure SSI to write address, mode bits, but no instruction.
+//                SSI + flash are now jointly in a state where continuous reads
+//                can take place.
+//              * Jump to exit pointer passed in via lr. Bootrom passes null,
+//                in which case this code uses a default 256 byte flash offset
+//
+// Building:    * This code must be position-independent, and use stack only
+//              * The code will be padded to a size of 256 bytes, including a
+//                4-byte checksum. Therefore code size cannot exceed 252 bytes.
+// ----------------------------------------------------------------------------
+
+#include "pico/asm_helper.S"
+#include "hardware/regs/addressmap.h"
+#include "hardware/regs/ssi.h"
+#include "hardware/regs/pads_qspi.h"
+
+// ----------------------------------------------------------------------------
+// Config section
+// ----------------------------------------------------------------------------
+// It should be possible to support most flash devices by modifying this section
+
+// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
+// This must be a positive, even integer.
+// The bootrom is very conservative with SPI frequency, but here we should be
+// as aggressive as possible.
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 4
+#endif
+#if PICO_FLASH_SPI_CLKDIV & 1
+#error PICO_FLASH_SPI_CLKDIV must be even
+#endif
+
+// Define interface width: single/dual/quad IO
+#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
+
+// For W25Q080 this is the "Read data fast quad IO" instruction:
+#define CMD_READ 0xeb
+
+// "Mode bits" are 8 special bits sent immediately after
+// the address bits in a "Read Data Fast Quad I/O" command sequence. 
+// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
+// next read does not require the 0xeb instruction prefix.
+#define MODE_CONTINUOUS_READ 0xa0
+
+// The number of address + mode bits, divided by 4 (always 4, not function of
+// interface width).
+#define ADDR_L 8
+
+// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles
+// are required.
+#define WAIT_CYCLES 4
+
+// If defined, we will read status reg, compare to SREG_DATA, and overwrite
+// with our value if the SR doesn't match.
+// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to
+// SR2 (31h cmd) as the latter command isn't supported by WX25Q080.
+// This isn't great because it will remove block protections.
+// A better solution is to use a volatile SR write if your device supports it.
+#define PROGRAM_STATUS_REG
+
+#define CMD_WRITE_ENABLE 0x06
+#define CMD_READ_STATUS 0x05
+#define CMD_READ_STATUS2 0x35
+#define CMD_WRITE_STATUS 0x01
+#define SREG_DATA 0x02  // Enable quad-SPI mode
+
+// ----------------------------------------------------------------------------
+// Start of 2nd Stage Boot Code
+// ----------------------------------------------------------------------------
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.section .text
+
+// The exit point is passed in lr. If entered from bootrom, this will be the
+// flash address immediately following this second stage (0x10000100).
+// Otherwise it will be a return address -- second stage being called as a
+// function by user code, after copying out of XIP region. r3 holds SSI base,
+// r0...2 used as temporaries. Other GPRs not used.
+.global _stage2_boot
+.type _stage2_boot,%function
+.thumb_func
+_stage2_boot:
+    push {lr}
+
+    // Set pad configuration:
+    // - SCLK 8mA drive, no slew limiting
+    // - SDx disable input Schmitt to reduce delay
+
+    ldr r3, =PADS_QSPI_BASE
+    movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS)
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
+    ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
+    movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS
+    bics r0, r1
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET]
+
+    ldr r3, =XIP_SSI_BASE
+
+    // Disable SSI to allow further config
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    // Set baud rate
+    movs r1, #PICO_FLASH_SPI_CLKDIV
+    str r1, [r3, #SSI_BAUDR_OFFSET]
+
+    // Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means,
+    // if the flash launches data on SCLK posedge, we capture it at the time that
+    // the next SCLK posedge is launched. This is shortly before that posedge
+    // arrives at the flash, so data hold time should be ok. For
+    // PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect.
+
+    movs r1, #1
+    movs r2, #SSI_RX_SAMPLE_DLY_OFFSET  // == 0xf0 so need 8 bits of offset significance
+    str r1, [r3, r2]
+
+
+// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
+// (i.e. turn WPn and HOLDn into IO2/IO3)
+#ifdef PROGRAM_STATUS_REG
+program_sregs:
+#define CTRL0_SPI_TXRX \
+    (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \
+    (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB)
+
+    ldr r1, =(CTRL0_SPI_TXRX)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+     // Enable SSI and select slave 0
+    movs r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    // Check whether SR needs updating
+    movs r0, #CMD_READ_STATUS2
+    bl read_flash_sreg
+    movs r2, #SREG_DATA
+    cmp r0, r2
+    beq skip_sreg_programming
+
+    // Send write enable command
+    movs r1, #CMD_WRITE_ENABLE
+    str r1, [r3, #SSI_DR0_OFFSET]
+
+    // Poll for completion and discard RX
+    bl wait_ssi_ready
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+
+    // Send status write command followed by data bytes
+    movs r1, #CMD_WRITE_STATUS
+    str r1, [r3, #SSI_DR0_OFFSET]
+    movs r0, #0
+    str r0, [r3, #SSI_DR0_OFFSET]
+    str r2, [r3, #SSI_DR0_OFFSET]
+
+    bl wait_ssi_ready
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+
+    // Poll status register for write completion
+1:
+    movs r0, #CMD_READ_STATUS
+    bl read_flash_sreg
+    movs r1, #1
+    tst r0, r1
+    bne 1b
+
+skip_sreg_programming:
+
+    // Disable SSI again so that it can be reconfigured
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+#endif
+
+// Currently the flash expects an 8 bit serial command prefix on every
+// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O
+// command, with mode bits set such that the flash will not expect a serial
+// command prefix on *subsequent* transfers. We don't care about the results
+// of the read, the important part is the mode bits.
+
+dummy_read:
+#define CTRLR0_ENTER_XIP \
+    (FRAME_FORMAT                          /* Quad I/O mode */                \
+        << SSI_CTRLR0_SPI_FRF_LSB) |                                          \
+    (31 << SSI_CTRLR0_DFS_32_LSB)  |       /* 32 data bits */                 \
+    (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ     /* Send INST/ADDR, Receive Data */ \
+        << SSI_CTRLR0_TMOD_LSB)
+
+    ldr r1, =(CTRLR0_ENTER_XIP)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+    movs r1, #0x0                    // NDF=0 (single 32b read)
+    str r1, [r3, #SSI_CTRLR1_OFFSET]
+
+#define SPI_CTRLR0_ENTER_XIP \
+    (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |     /* Address + mode bits */ \
+    (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_8B \
+        << SSI_SPI_CTRLR0_INST_L_LSB) |        /* 8-bit instruction */ \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A      /* Send Command in serial mode then address in Quad I/O mode */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_ENTER_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)  // SPI_CTRL0 Register
+    str r1, [r0]
+
+    movs r1, #1                      // Re-enable SSI
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    movs r1, #CMD_READ
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push SPI command into TX FIFO
+    movs r1, #MODE_CONTINUOUS_READ   // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push Address into TX FIFO - this will trigger the transaction
+
+    // Poll for completion
+    bl wait_ssi_ready
+
+// The flash is in a state where we can blast addresses in parallel, and get
+// parallel data back. Now configure the SSI to translate XIP bus accesses
+// into QSPI transfers of this form.
+
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Disable SSI (and clear FIFO) to allow further config
+
+// Note that the INST_L field is used to select what XIP data gets pushed into
+// the TX FIFO:
+//      INST_L_0_BITS   {ADDR[23:0],XIP_CMD[7:0]}       Load "mode bits" into XIP_CMD
+//      Anything else   {XIP_CMD[7:0],ADDR[23:0]}       Load SPI command into XIP_CMD
+configure_ssi:
+#define SPI_CTRLR0_XIP \
+    (MODE_CONTINUOUS_READ                      /* Mode bits to keep flash in continuous read mode */ \
+        << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
+    (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |    /* Total number of address + mode bits */ \
+    (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) |    /* Hi-Z dummy clocks following address + mode */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_NONE          /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
+        << SSI_SPI_CTRLR0_INST_L_LSB) | \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A      /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
+    str r1, [r0]
+
+    movs r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Re-enable SSI
+
+// Bus accesses to the XIP window will now be transparently serviced by the
+// external flash on cache miss. We are ready to run code from flash.
+
+// Pull in standard exit routine
+#include "boot2_helpers/exit_from_boot2.S"
+
+// Common functions
+#include "boot2_helpers/wait_ssi_ready.S"
+#ifdef PROGRAM_STATUS_REG
+#include "boot2_helpers/read_flash_sreg.S"
+#endif
+
+.global literals
+literals:
+.ltorg
+
+.end
diff --git a/src/rp2_common/boot_stage2/boot2_w25x10cl.S b/src/rp2_common/boot_stage2/boot2_w25x10cl.S
new file mode 100644
index 0000000..02628d4
--- /dev/null
+++ b/src/rp2_common/boot_stage2/boot2_w25x10cl.S
@@ -0,0 +1,196 @@
+// ----------------------------------------------------------------------------
+// Second stage boot code
+// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// Device:      Winbond W25X10CL
+//
+// Description: Configures W25X10CL to run in Dual I/O continuous read XIP mode
+//
+// Details:     * Disable SSI
+//              * Configure SSI to generate 8b command + 28b address + 2 wait,
+//                with address and data using dual SPI mode
+//              * Enable SSI
+//              * Generate dummy read with command = 0xBB, top 24b of address
+//                of 0x000000 followed by M[7:0]=0010zzzz (with the HiZ being
+//                generated by 2 wait cycles).  This leaves the W25X10CL in
+//                continuous read mode
+//              * Disable SSI
+//              * Configure SSI to generate 0b command + 28b address + 2 wait,
+//                with the extra 4 bits of address LSB being 0x2 to keep the
+//                W25X10CL in continuous read mode forever
+//              * Enable SSI
+//              * Set VTOR = 0x10000100
+//              * Read MSP reset vector from 0x10000100 and write to MSP (this
+//                will also enable XIP mode in the SSI wrapper)
+//              * Read PC reset vector from 0x10000104 and jump to it
+//
+// Building:    * This code must be linked to run at 0x20000000
+//              * The code will be padded to a size of 256 bytes, including a
+//                4-byte checksum. Therefore code size cannot exceed 252 bytes.
+// ----------------------------------------------------------------------------
+
+#include "pico/asm_helper.S"
+#include "hardware/regs/addressmap.h"
+#include "hardware/regs/ssi.h"
+
+// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
+// This must be an even number.
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 4
+#endif
+
+// ----------------------------------------------------------------------------
+// The "System Control Block" is a set of internal Cortex-M0+ control registers
+// that are memory mapped and accessed like any other H/W register.  They have
+// fixed addresses in the address map of every Cortex-M0+ system.
+// ----------------------------------------------------------------------------
+
+.equ SCB_VTOR,          0xE000ED08      // RW Vector Table Offset Register
+
+// ----------------------------------------------------------------------------
+// Winbond W25X10CL Supported Commands
+// Taken from "w25x10cl_reg_021714.pdf"
+// ----------------------------------------------------------------------------
+
+.equ W25X10CL_CMD_READ_DATA_FAST_DUAL_IO, 0xbb
+
+// ----------------------------------------------------------------------------
+// Winbond W25X10CL "Mode bits" are 8 special bits sent immediately after
+// the address bits in a "Read Data Fast Dual I/O" command sequence.
+// Of M[7:4], they say M[7:6] are reserved (set to zero), and bits M[3:0]
+// are don't care (we HiZ).  Only M[5:4] are used, and they must be set
+// to M[5:4] = 2'b10 to enable continuous read mode.
+// ----------------------------------------------------------------------------
+
+.equ W25X10CL_MODE_CONTINUOUS_READ,        0x20
+
+// ----------------------------------------------------------------------------
+// Start of 2nd Stage Boot Code
+// ----------------------------------------------------------------------------
+
+.cpu cortex-m0
+.thumb
+
+.org 0
+
+.section .text
+
+// This code will get copied to 0x20000000 and then executed
+
+.global _stage2_boot
+.type _stage2_boot,%function
+.thumb_func
+_stage2_boot:
+    push {lr}
+    ldr r3, =XIP_SSI_BASE                // Use as base address where possible
+
+// We are primarily interested in setting up Flash for DSPI XIP w/ continuous read
+
+    mov r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI to allow further config
+
+// The Boot ROM sets a very conservative SPI clock frequency to be sure it can
+// read the initial 256 bytes from any device.  Here we can be more aggressive.
+
+    mov r1, #PICO_FLASH_SPI_CLKDIV
+    str r1, [r3, #SSI_BAUDR_OFFSET]  // Set SSI Clock
+
+// First we need to send the initial command to get us in to Fast Read Dual I/O
+// mode.  As this transaction requires a command, we can't send it in XIP mode.
+// To enter Continuous Read mode as well we need to append 4'b0010 to the address
+// bits and then add a further 4 don't care bits.  We will construct this by
+// specifying a 28-bit address, with the least significant bits being 4'b0010.
+// This is just a dummy transaction so we'll perform a read from address zero
+// and then discard what comes back.  All we really care about is that at the
+// end of the transaction, the Winbond W25X10CL device is in Continuous Read mode
+// and from then on will only expect to receive addresses.
+
+#define CTRLR0_ENTER_XIP \
+    (SSI_CTRLR0_SPI_FRF_VALUE_DUAL         /* Dual I/O mode */                \
+        << SSI_CTRLR0_SPI_FRF_LSB) |                                          \
+    (31 << SSI_CTRLR0_DFS_32_LSB)  |       /* 32 data bits */    \
+    (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ     /* Send INST/ADDR, Receive Data */ \
+        << SSI_CTRLR0_TMOD_LSB)
+
+    ldr r1, =(CTRLR0_ENTER_XIP)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+    mov r1, #0x0                    // NDF=0 (single 32b read)
+    str r1, [r3, #SSI_CTRLR1_OFFSET]
+
+#define SPI_CTRLR0_ENTER_XIP \
+    (7 << SSI_SPI_CTRLR0_ADDR_L_LSB) |         /* Send 28 bits (24 address + 4 mode) */ \
+    (2 << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) |    /* Hi-Z the other 4 mode bits (2 cycles @ dual I/O = 4 bits) */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_8B \
+        << SSI_SPI_CTRLR0_INST_L_LSB) |        /* 8-bit instruction */ \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A      /* Send Command in serial mode then address in Dual I/O mode */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_ENTER_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)  // SPI_CTRL0 Register
+    str r1, [r0]
+
+    mov r1, #1                      // Re-enable SSI
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    mov r1, #W25X10CL_CMD_READ_DATA_FAST_DUAL_IO    // 8b command = 0xBB
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push SPI command into TX FIFO
+    mov r1, #0x0000002              // 28-bit Address for dummy read = 0x000000 + 0x2 Mode bits to set M[5:4]=10
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push Address into TX FIFO - this will trigger the transaction
+
+// Now we wait for the read transaction to complete by monitoring the SSI
+// status register and checking for the "RX FIFO Not Empty" flag to assert.
+
+    mov r1, #SSI_SR_RFNE_BITS
+00:
+    ldr r0, [r3, #SSI_SR_OFFSET]    // Read status register
+    tst r0, r1                      // RFNE status flag set?
+    beq 00b                         // If not then wait
+
+// At this point CN# will be deasserted and the SPI clock will not be running.
+// The Winbond WX25X10CL device will be in continuous read, dual I/O mode and
+// only expecting address bits after the next CN# assertion.  So long as we
+// send 4'b0010 (and 4 more dummy HiZ bits) after every subsequent 24b address
+// then the Winbond device will remain in continuous read mode.  This is the
+// ideal mode for Execute-In-Place.
+// (If we want to exit continuous read mode then we will need to switch back
+// to APM mode and generate a 28-bit address phase with the extra nibble set
+// to 4'b0000).
+
+    mov r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Disable SSI (and clear FIFO) to allow further config
+
+// Note that the INST_L field is used to select what XIP data gets pushed into
+// the TX FIFO:
+//      INST_L_0_BITS   {ADDR[23:0],XIP_CMD[7:0]}       Load "mode bits" into XIP_CMD
+//      Anything else   {XIP_CMD[7:0],ADDR[23:0]}       Load SPI command into XIP_CMD
+
+#define SPI_CTRLR0_XIP \
+    (W25X10CL_MODE_CONTINUOUS_READ              /* Mode bits to keep Winbond in continuous read mode */ \
+        << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
+    (7 << SSI_SPI_CTRLR0_ADDR_L_LSB) |         /* Send 28 bits (24 address + 4 mode) */ \
+    (2 << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) |    /* Hi-Z the other 4 mode bits (2 cycles @ dual I/O = 4 bits) */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_NONE          /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
+        << SSI_SPI_CTRLR0_INST_L_LSB) | \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A      /* Send Address in Dual I/O mode (and Command but that is zero bits long) */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
+    str r1, [r0]
+
+    mov r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Re-enable SSI
+
+// We are now in XIP mode, with all transactions using Dual I/O and only
+// needing to send 24-bit addresses (plus mode bits) for each read transaction.
+
+// Pull in standard exit routine
+#include "boot2_helpers/exit_from_boot2.S"
+
+.global literals
+literals:
+.ltorg
+
+.end
diff --git a/src/rp2_common/boot_stage2/boot_stage2.ld b/src/rp2_common/boot_stage2/boot_stage2.ld
new file mode 100644
index 0000000..f8669ab
--- /dev/null
+++ b/src/rp2_common/boot_stage2/boot_stage2.ld
@@ -0,0 +1,13 @@
+MEMORY {
+    /* We are loaded to the top 256 bytes of SRAM, which is above the bootrom
+       stack. Note 4 bytes occupied by checksum. */
+    SRAM(rx) : ORIGIN = 0x20041f00, LENGTH = 252
+}
+
+SECTIONS {
+    . = ORIGIN(SRAM);
+    .text : {
+        *(.entry)
+        *(.text)
+    } >SRAM
+}
diff --git a/src/rp2_common/boot_stage2/compile_time_choice.S b/src/rp2_common/boot_stage2/compile_time_choice.S
new file mode 100644
index 0000000..5aa2b96
--- /dev/null
+++ b/src/rp2_common/boot_stage2/compile_time_choice.S
@@ -0,0 +1,19 @@
+// ----------------------------------------------------------------------------
+// Second stage boot code
+// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
+// SPDX-License-Identifier: BSD-3-Clause
+// ----------------------------------------------------------------------------
+//
+// This implementation uses the PICO_BOOT_STAGE2_CHOOSE_ preprocessor defines to pick
+// amongst a menu of known boot stage 2 implementations, allowing the board
+// configuration header to be able to specify the boot stage 2
+
+#include "boot_stage2/config.h"
+
+#ifdef PICO_BUILD_BOOT_STAGE2_NAME
+    // boot stage 2 is configured by cmake, so use the name specified there
+    #error PICO_BUILD_BOOT_STAGE2_NAME should not be defined for compile_time_choice builds
+#else
+    // boot stage 2 is selected by board config header, and PICO_BOOT_STAGE2_ASM is set in boot_stage2/config.h
+    #include PICO_BOOT_STAGE2_ASM
+#endif
diff --git a/src/rp2_common/boot_stage2/doc.h b/src/rp2_common/boot_stage2/doc.h
new file mode 100644
index 0000000..483dd68
--- /dev/null
+++ b/src/rp2_common/boot_stage2/doc.h
@@ -0,0 +1,4 @@
+/**
+ * \defgroup boot_stage2 boot_stage2
+ * \brief Second stage boot loaders responsible for setting up external flash
+ */
diff --git a/src/rp2_common/boot_stage2/include/boot_stage2/config.h b/src/rp2_common/boot_stage2/include/boot_stage2/config.h
new file mode 100644
index 0000000..5e57f95
--- /dev/null
+++ b/src/rp2_common/boot_stage2/include/boot_stage2/config.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOOT_STAGE2_CONFIG_H_
+#define _BOOT_STAGE2_CONFIG_H_
+
+// NOTE THIS HEADER IS INCLUDED FROM ASSEMBLY
+
+#include "pico/config.h"
+
+// PICO_CONFIG: PICO_BUILD_BOOT_STAGE2_NAME, The name of the boot stage 2 if selected by the build, group=boot_stage2
+#ifdef PICO_BUILD_BOOT_STAGE2_NAME
+    #define _BOOT_STAGE2_SELECTED
+#else
+    // check that multiple boot stage 2 options haven't been set...
+
+// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_IS25LP080, Select boot2_is25lp080 as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2
+#ifndef PICO_BOOT_STAGE2_CHOOSE_IS25LP080
+    #define PICO_BOOT_STAGE2_CHOOSE_IS25LP080 0
+#elif PICO_BOOT_STAGE2_CHOOSE_IS25LP080
+    #ifdef _BOOT_STAGE2_SELECTED
+        #error multiple boot stage 2 options chosen
+    #endif
+    #define _BOOT_STAGE2_SELECTED
+#endif
+// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_W25Q080, Select boot2_w25q080 as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2
+#ifndef PICO_BOOT_STAGE2_CHOOSE_W25Q080
+    #define PICO_BOOT_STAGE2_CHOOSE_W25Q080 0
+#elif PICO_BOOT_STAGE2_CHOOSE_W25Q080
+    #ifdef _BOOT_STAGE2_SELECTED
+        #error multiple boot stage 2 options chosen
+    #endif
+    #define _BOOT_STAGE2_SELECTED
+#endif
+// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_W25X10CL, Select boot2_w25x10cl as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2
+#ifndef PICO_BOOT_STAGE2_CHOOSE_W25X10CL
+    #define PICO_BOOT_STAGE2_CHOOSE_W25X10CL 0
+#elif PICO_BOOT_STAGE2_CHOOSE_W25X10CL
+    #ifdef _BOOT_STAGE2_SELECTED
+        #error multiple boot stage 2 options chosen
+    #endif
+    #define _BOOT_STAGE2_SELECTED
+#endif
+// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_AT25SF128A, Select boot2_at25sf128a as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2
+#ifndef PICO_BOOT_STAGE2_CHOOSE_AT25SF128A
+    #define PICO_BOOT_STAGE2_CHOOSE_AT25SF128A 0
+#elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A
+    #ifdef _BOOT_STAGE2_SELECTED
+        #error multiple boot stage 2 options chosen
+    #endif
+    #define _BOOT_STAGE2_SELECTED
+#endif
+
+// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H, Select boot2_generic_03h as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=1, group=boot_stage2
+#if defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) && PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H
+    #ifdef _BOOT_STAGE2_SELECTED
+        #error multiple boot stage 2 options chosen
+    #endif
+    #define _BOOT_STAGE2_SELECTED
+#endif
+
+#endif // PICO_BUILD_BOOT_STAGE2_NAME
+
+#ifdef PICO_BUILD_BOOT_STAGE2_NAME
+    // boot stage 2 is configured by cmake, so use the name specified there
+    #define PICO_BOOT_STAGE2_NAME PICO_BUILD_BOOT_STAGE2_NAME
+#else
+    // boot stage 2 is selected by board config header, so we have to do some work
+    #if PICO_BOOT_STAGE2_CHOOSE_IS25LP080
+        #define _BOOT_STAGE2 boot2_is25lp080
+    #elif PICO_BOOT_STAGE2_CHOOSE_W25Q080
+        #define _BOOT_STAGE2 boot2_w25q080
+    #elif PICO_BOOT_STAGE2_CHOOSE_W25X10CL
+        #define _BOOT_STAGE2 boot2_w25x10cl
+    #elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A
+        #define _BOOT_STAGE2 boot2_at25sf128a
+    #elif !defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) || PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H
+        #undef PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H
+        #define PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H 1
+        #define _BOOT_STAGE2 boot2_generic_03h
+    #else
+        #error no boot stage 2 is defined by PICO_BOOT_STAGE2_CHOOSE_ macro
+    #endif
+    // we can't include cdefs in assembly, so define our own, but avoid conflict with real ones for c inclusion
+    #define _PICO__STRING(x) #x
+    #define _PICO__XSTRING(x) _PICO__STRING(x)
+    #define _PICO__CONCAT1(x, y) x ## y
+    #define PICO_BOOT_STAGE2_NAME _PICO__XSTRING(_BOOT_STAGE2)
+    #define PICO_BOOT_STAGE2_ASM _PICO__XSTRING(_PICO__CONCAT1(_BOOT_STAGE2,.S))
+#endif
+#endif
diff --git a/src/rp2_common/boot_stage2/pad_checksum b/src/rp2_common/boot_stage2/pad_checksum
new file mode 100755
index 0000000..356227d
--- /dev/null
+++ b/src/rp2_common/boot_stage2/pad_checksum
@@ -0,0 +1,55 @@
+#!/usr/bin/env python3
+
+import argparse
+import binascii
+import struct
+import sys
+
+
+def any_int(x):
+    try:
+        return int(x, 0)
+    except:
+        raise argparse.ArgumentTypeError("expected an integer, not '{!r}'".format(x))
+
+
+def bitrev(x, width):
+    return int("{:0{w}b}".format(x, w=width)[::-1], 2)
+
+
+parser = argparse.ArgumentParser()
+parser.add_argument("ifile", help="Input file (binary)")
+parser.add_argument("ofile", help="Output file (assembly)")
+parser.add_argument("-p", "--pad", help="Padded size (bytes), including 4-byte checksum, default 256",
+                    type=any_int, default=256)
+parser.add_argument("-s", "--seed", help="Checksum seed value, default 0",
+                    type=any_int, default=0)
+args = parser.parse_args()
+
+try:
+    idata = open(args.ifile, "rb").read()
+except:
+    sys.exit("Could not open input file '{}'".format(args.ifile))
+
+if len(idata) >= args.pad - 4:
+    sys.exit("Input file size ({} bytes) too large for final size ({} bytes)".format(len(idata), args.pad))
+
+idata_padded = idata + bytes(args.pad - 4 - len(idata))
+
+# Our bootrom CRC32 is slightly bass-ackward but it's best to work around for now (FIXME)
+# 100% worth it to save two Thumb instructions
+checksum = bitrev(
+    (binascii.crc32(bytes(bitrev(b, 8) for b in idata_padded), args.seed ^ 0xffffffff) ^ 0xffffffff) & 0xffffffff, 32)
+odata = idata_padded + struct.pack("<L", checksum)
+
+try:
+    with open(args.ofile, "w") as ofile:
+        ofile.write("// Padded and checksummed version of: {}\n\n".format(args.ifile))
+        ofile.write(".cpu cortex-m0plus\n")
+        ofile.write(".thumb\n\n")
+        ofile.write(".section .boot2, \"ax\"\n\n")
+        for offs in range(0, len(odata), 16):
+            chunk = odata[offs:min(offs + 16, len(odata))]
+            ofile.write(".byte {}\n".format(", ".join("0x{:02x}".format(b) for b in chunk)))
+except:
+    sys.exit("Could not open output file '{}'".format(args.ofile))
diff --git a/src/rp2_common/cmsis/CMakeLists.txt b/src/rp2_common/cmsis/CMakeLists.txt
new file mode 100644
index 0000000..0d663e1
--- /dev/null
+++ b/src/rp2_common/cmsis/CMakeLists.txt
@@ -0,0 +1,66 @@
+# Deferring this config until we decide how to include other CMSIS libraries... it is likely that we always want to use the stub version of the core
+# at least if the vendor/device is RaspberryPi/RP2040...
+
+## PICO_CMAKE_CONFIG: PICO_CMSIS_PATH, directory to locate CMSIS installation, default="included stub CORE only impl", group=build
+#if (DEFINED PICO_CMSIS_PATH)
+#    set(PICO_CMSIS_PATH "${PICO_CMSIS_PATH}" CACHE PATH "Path to the CMSIS tree to use with Raspberry Pi Pico SDK")
+#    message("Using specified PICO_CMSIS_PATH for CMSIS ('${PICO_CMSIS_PATH}')")
+#elseif (DEFINED ENV{PICO_CMSIS_PATH})
+#    set(PICO_CMSIS_PATH $ENV{PICO_CMSIS_PATH})
+#    message("Using PICO_CMSIS_PATH from environment for CMSIS ('${PICO_CMSIS_PATH}')")
+#endif()
+#
+## PICO_CMAKE_CONFIG: PICO_CMSIS_VENDOR, vendor name for CMSIS, default="RaspberryPi", group=build
+#if (DEFINED PICO_CMSIS_VENDOR)
+#    set(PICO_CMSIS_VENDOR "${PICO_CMSIS_VENDOR}" CACHE STRING "CMSIS vendor name to use")
+#    message("Using specified PICO_CMSIS_VENDOR for CMSIS ('${PICO_CMSIS_VENDOR}')")
+#elseif (DEFINED ENV{PICO_CMSIS_VENDOR})
+#    set(PICO_CMSIS_VENDOR $ENV{PICO_CMSIS_VENDOR})
+#    message("Using PICO_CMSIS_VENDOR from environment for CMSIS ('${PICO_CMSIS_VENDOR}')")
+#else()
+#    set(PICO_CMSIS_VENDOR RaspberryPi)
+#endif()
+#
+## PICO_CMAKE_CONFIG: PICO_CMSIS_DEVICE, device name for CMSIS, default="RP2040", group=build
+#if (DEFINED PICO_CMSIS_DEVICE)
+#    set(PICO_CMSIS_DEVICE "${PICO_CMSIS_DEVICE}" CACHE STRING "CMSIS device name to use")
+#    message("Using specified PICO_CMSIS_DEVICE for CMSIS ('${PICO_CMSIS_DEVICE}')")
+#elseif (DEFINED ENV{PICO_CMSIS_DEVICE})
+#    set(PICO_CMSIS_DEVICE $ENV{PICO_CMSIS_DEVICE})
+#    message("Using PICO_CMSIS_DEVICE from environment for CMSIS ('${PICO_CMSIS_DEVICE}')")
+#else()
+#    set(PICO_CMSIS_DEVICE RP2040)
+#endif()
+#
+#if (PICO_CMSIS_PATH AND EXISTS ${PICO_CMSIS_PATH}/CMSIS/Core/${PICO_CMSIS_VENDOR}/${PICO_CMSIS_DEVICE})
+#    message("CMSIS Core found for path ${PICO_CMSIS_PATH}, vendor ${PICO_CMSIS_VENDOR}, device ${PICO_CMSIS_DEVICE}")
+#    set(PICO_CMSIS_CORE_PATH ${PICO_CMSIS_PATH}/CMSIS/Core)
+#elseif (PICO_CMSIS_VENDOR STREQUAL "RaspberryPi" AND PICO_CMSIS_DEVICE STREQUAL "RP2040")
+#    set(PICO_CMSIS_CORE_PATH ${CMAKE_CURRENT_LIST_DIR}/stub)
+#elseif (PICO_CMSIS_PATH)
+#    message(WARNING "CMSIS core not found in ${PICO_CMSIS_PATH} for vendor ${PICO_CMSIS_VENDOR}, device ${PICO_CMSIS_DEVICE}")
+#    set(PICO_CMSIS_CORE_PATH)
+#else()
+#    message(WARNING "Non-standard vendor ${PICO_CMSIS_VENDOR} amd device ${PICO_CMSIS_DEVICE} specified, but PICO_CMSIS_PATH was not set")
+#endif()
+
+# ... using these 3 lines instead
+set(PICO_CMSIS_CORE_PATH ${CMAKE_CURRENT_LIST_DIR}/stub)
+set(PICO_CMSIS_VENDOR RaspberryPi)
+set(PICO_CMSIS_DEVICE RP2040)
+
+if (PICO_CMSIS_CORE_PATH)
+    pico_add_impl_library(cmsis_core)
+    target_sources(cmsis_core INTERFACE
+            ${PICO_CMSIS_CORE_PATH}/CMSIS/Device/${PICO_CMSIS_VENDOR}/${PICO_CMSIS_DEVICE}/Source/system_${PICO_CMSIS_DEVICE}.c
+    )
+    target_include_directories(cmsis_core INTERFACE
+            ${PICO_CMSIS_CORE_PATH}/CMSIS/Core/Include
+            ${PICO_CMSIS_CORE_PATH}/CMSIS/Device/${PICO_CMSIS_VENDOR}/${PICO_CMSIS_DEVICE}/Include
+    )
+    target_link_libraries(cmsis_core INTERFACE hardware_clocks pico_platform)
+
+    list(APPEND PICO_RP2040_CONFIG_HEADER_FILES ${CMAKE_CURRENT_LIST_DIR}/include/cmsis/rename_exceptions.h)
+    pico_promote_common_scope_vars()
+endif()
+
diff --git a/src/rp2_common/cmsis/include/cmsis/rename_exceptions.h b/src/rp2_common/cmsis/include/cmsis/rename_exceptions.h
new file mode 100644
index 0000000..a523d27
--- /dev/null
+++ b/src/rp2_common/cmsis/include/cmsis/rename_exceptions.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CMSIS_RENAME_EXCEPTIONS_H
+#define _CMSIS_RENAME_EXCEPTIONS_H
+
+#if LIB_CMSIS_CORE
+// PICO_CONFIG: PICO_CMSIS_RENAME_EXCEPTIONS, Whether to rename SDK exceptions such as isr_nmi to their CMSIS equivalent i.e. NMI_Handler, type=bool, default=1, group=cmsis_core
+
+// Note that since this header is included at the config stage, if you wish to override this you should do so via build compiler define
+#ifndef PICO_CMSIS_RENAME_EXCEPTIONS
+#define PICO_CMSIS_RENAME_EXCEPTIONS 1
+#endif
+
+#if PICO_CMSIS_RENAME_EXCEPTIONS
+#define isr_nmi NMI_Handler
+#define isr_hardfault HardFault_Handler
+#define isr_svcall SVC_Handler
+#define isr_pendsv PendSV_Handler
+#define isr_systick SysTick_Handler
+#define isr_irq0 TIMER_IRQ_0_Handler
+#define isr_irq1 TIMER_IRQ_1_Handler
+#define isr_irq2 TIMER_IRQ_2_Handler
+#define isr_irq3 TIMER_IRQ_3_Handler
+#define isr_irq4 PWM_IRQ_WRAP_Handler
+#define isr_irq5 USBCTRL_IRQ_Handler
+#define isr_irq6 XIP_IRQ_Handler
+#define isr_irq7 PIO0_IRQ_0_Handler
+#define isr_irq8 PIO0_IRQ_1_Handler
+#define isr_irq9 PIO1_IRQ_0_Handler
+#define isr_irq10 PIO1_IRQ_1_Handler
+#define isr_irq11 DMA_IRQ_0_Handler
+#define isr_irq12 DMA_IRQ_1_Handler
+#define isr_irq13 IO_IRQ_BANK0_Handler
+#define isr_irq14 IO_IRQ_QSPI_Handler
+#define isr_irq15 SIO_IRQ_PROC0_Handler
+#define isr_irq16 SIO_IRQ_PROC1_Handler
+#define isr_irq17 CLOCKS_IRQ_Handler
+#define isr_irq18 SPI0_IRQ_Handler
+#define isr_irq19 SPI1_IRQ_Handler
+#define isr_irq20 UART0_IRQ_Handler
+#define isr_irq21 UART1_IRQ_Handler
+#define isr_irq22 ADC_IRQ_FIFO_Handler
+#define isr_irq23 I2C0_IRQ_Handler
+#define isr_irq24 I2C1_IRQ_Handler
+#define isr_irq25 RTC_IRQ_Handler
+#endif
+
+#endif
+#endif /* _CMSIS_RENAME_EXCEPTIONS_H */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armcc.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armcc.h
new file mode 100644
index 0000000..237ff6e
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armcc.h
@@ -0,0 +1,885 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.2.1
+ * @date     26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+  /* __ARM_ARCH_8_1M_MAIN__  not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __ARM_FEATURE_DSP         1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __memory_changed()
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h
new file mode 100644
index 0000000..90de9db
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h
@@ -0,0 +1,1467 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.3.1
+ * @date     26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF)
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF)
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+          (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+          (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+          (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+           
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define     __SADD8                 __builtin_arm_sadd8
+#define     __QADD8                 __builtin_arm_qadd8
+#define     __SHADD8                __builtin_arm_shadd8
+#define     __UADD8                 __builtin_arm_uadd8
+#define     __UQADD8                __builtin_arm_uqadd8
+#define     __UHADD8                __builtin_arm_uhadd8
+#define     __SSUB8                 __builtin_arm_ssub8
+#define     __QSUB8                 __builtin_arm_qsub8
+#define     __SHSUB8                __builtin_arm_shsub8
+#define     __USUB8                 __builtin_arm_usub8
+#define     __UQSUB8                __builtin_arm_uqsub8
+#define     __UHSUB8                __builtin_arm_uhsub8
+#define     __SADD16                __builtin_arm_sadd16
+#define     __QADD16                __builtin_arm_qadd16
+#define     __SHADD16               __builtin_arm_shadd16
+#define     __UADD16                __builtin_arm_uadd16
+#define     __UQADD16               __builtin_arm_uqadd16
+#define     __UHADD16               __builtin_arm_uhadd16
+#define     __SSUB16                __builtin_arm_ssub16
+#define     __QSUB16                __builtin_arm_qsub16
+#define     __SHSUB16               __builtin_arm_shsub16
+#define     __USUB16                __builtin_arm_usub16
+#define     __UQSUB16               __builtin_arm_uqsub16
+#define     __UHSUB16               __builtin_arm_uhsub16
+#define     __SASX                  __builtin_arm_sasx
+#define     __QASX                  __builtin_arm_qasx
+#define     __SHASX                 __builtin_arm_shasx
+#define     __UASX                  __builtin_arm_uasx
+#define     __UQASX                 __builtin_arm_uqasx
+#define     __UHASX                 __builtin_arm_uhasx
+#define     __SSAX                  __builtin_arm_ssax
+#define     __QSAX                  __builtin_arm_qsax
+#define     __SHSAX                 __builtin_arm_shsax
+#define     __USAX                  __builtin_arm_usax
+#define     __UQSAX                 __builtin_arm_uqsax
+#define     __UHSAX                 __builtin_arm_uhsax
+#define     __USAD8                 __builtin_arm_usad8
+#define     __USADA8                __builtin_arm_usada8
+#define     __SSAT16                __builtin_arm_ssat16
+#define     __USAT16                __builtin_arm_usat16
+#define     __UXTB16                __builtin_arm_uxtb16
+#define     __UXTAB16               __builtin_arm_uxtab16
+#define     __SXTB16                __builtin_arm_sxtb16
+#define     __SXTAB16               __builtin_arm_sxtab16
+#define     __SMUAD                 __builtin_arm_smuad
+#define     __SMUADX                __builtin_arm_smuadx
+#define     __SMLAD                 __builtin_arm_smlad
+#define     __SMLADX                __builtin_arm_smladx
+#define     __SMLALD                __builtin_arm_smlald
+#define     __SMLALDX               __builtin_arm_smlaldx
+#define     __SMUSD                 __builtin_arm_smusd
+#define     __SMUSDX                __builtin_arm_smusdx
+#define     __SMLSD                 __builtin_arm_smlsd
+#define     __SMLSDX                __builtin_arm_smlsdx
+#define     __SMLSLD                __builtin_arm_smlsld
+#define     __SMLSLDX               __builtin_arm_smlsldx
+#define     __SEL                   __builtin_arm_sel
+#define     __QADD                  __builtin_arm_qadd
+#define     __QSUB                  __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h
new file mode 100644
index 0000000..0e5c734
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h
@@ -0,0 +1,1893 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang_ltm.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V1.3.0
+ * @date     26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF)
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF)
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h
new file mode 100644
index 0000000..adbf296
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h
@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h
new file mode 100644
index 0000000..a2778f5
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h
@@ -0,0 +1,2177 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.3.0
+ * @date     26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+  \brief   Initializes data and bss sections
+  \details This default implementations initialized all data and additional bss
+           sections relying on .copy.table and .zero.table specified properly
+           in the used linker script.
+  
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+  extern void _start(void) __NO_RETURN;
+  
+  typedef struct {
+    uint32_t const* src;
+    uint32_t* dest;
+    uint32_t  wlen;
+  } __copy_table_t;
+  
+  typedef struct {
+    uint32_t* dest;
+    uint32_t  wlen;
+  } __zero_table_t;
+  
+  extern const __copy_table_t __copy_table_start__;
+  extern const __copy_table_t __copy_table_end__;
+  extern const __zero_table_t __zero_table_start__;
+  extern const __zero_table_t __zero_table_end__;
+
+  for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+    for(uint32_t i=0u; i<pTable->wlen; ++i) {
+      pTable->dest[i] = pTable->src[i];
+    }
+  }
+ 
+  for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+    for(uint32_t i=0u; i<pTable->wlen; ++i) {
+      pTable->dest[i] = 0u;
+    }
+  }
+ 
+  _start();
+}
+  
+#define __PROGRAM_START           __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) 
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi":::"memory")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe":::"memory")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1, ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1, ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1, ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1, ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
+{
+  uint32_t result;
+
+  __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
+
+  return result;
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h
new file mode 100644
index 0000000..7eeffca
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h
@@ -0,0 +1,968 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.2.0
+ * @date     28. January 2020
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved. 
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #if __ICCARM_V8
+    #define __RESTRICT            __restrict
+  #else
+    /* Needs IAR language extensions */
+    #define __RESTRICT            restrict
+  #endif
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM volatile("RRX      %0, %1" : "=r"(result) : "r" (value));
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h
new file mode 100644
index 0000000..2f048e4
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.4
+ * @date     23. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 4U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h
new file mode 100644
index 0000000..4e7179a
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h
@@ -0,0 +1,1087 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.9
+ * @date     21. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+#else
+  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt */
+  *(vectors + (int32_t)IRQn) = vector;                              /* use pointer arithmetic to access vector */
+#endif
+  /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+#else
+  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt */
+  return *(vectors + (int32_t)IRQn);                                /* use pointer arithmetic to access vector */
+#endif
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv7.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv7.h
new file mode 100644
index 0000000..791a8da
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv7.h
@@ -0,0 +1,275 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.1.1
+ * @date     10. February 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
+   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
+   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
+   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
+  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
+   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
+   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
+   (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if shareable) or 010b (if non-shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h b/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h
new file mode 100644
index 0000000..a29b9e0
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h
@@ -0,0 +1,109 @@
+/*************************************************************************//**
+ * @file     RP2040.h
+ * @brief    CMSIS-Core(M) Device Peripheral Access Layer Header File for
+ *           Device RP2040
+ * @version  V1.0.0
+ * @date     5. May 2021
+ *****************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CMSIS_RP2040_H_
+#define _CMSIS_RP2040_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+
+typedef enum
+{
+  /* =======================================  ARM Cortex-M0+ Specific Interrupt Numbers  ======================================= */
+    Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
+    NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
+    HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
+    SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
+    PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
+    SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
+  /* ===========================================  RP2040 Specific Interrupt Numbers  =========================================== */
+    TIMER_IRQ_0_IRQn          =   0,              /*!< 0  TIMER_IRQ_0                                                            */
+    TIMER_IRQ_1_IRQn          =   1,              /*!< 1  TIMER_IRQ_1                                                            */
+    TIMER_IRQ_2_IRQn          =   2,              /*!< 2  TIMER_IRQ_2                                                            */
+    TIMER_IRQ_3_IRQn          =   3,              /*!< 3  TIMER_IRQ_3                                                            */
+    PWM_IRQ_WRAP_IRQn         =   4,              /*!< 4  PWM_IRQ_WRAP                                                           */
+    USBCTRL_IRQ_IRQn          =   5,              /*!< 5  USBCTRL_IRQ                                                            */
+    XIP_IRQ_IRQn              =   6,              /*!< 6  XIP_IRQ                                                                */
+    PIO0_IRQ_0_IRQn           =   7,              /*!< 7  PIO0_IRQ_0                                                             */
+    PIO0_IRQ_1_IRQn           =   8,              /*!< 8  PIO0_IRQ_1                                                             */
+    PIO1_IRQ_0_IRQn           =   9,              /*!< 9  PIO1_IRQ_0                                                             */
+    PIO1_IRQ_1_IRQn           =  10,              /*!< 10 PIO1_IRQ_1                                                             */
+    DMA_IRQ_0_IRQn            =  11,              /*!< 11 DMA_IRQ_0                                                              */
+    DMA_IRQ_1_IRQn            =  12,              /*!< 12 DMA_IRQ_1                                                              */
+    IO_IRQ_BANK0_IRQn         =  13,              /*!< 13 IO_IRQ_BANK0                                                           */
+    IO_IRQ_QSPI_IRQn          =  14,              /*!< 14 IO_IRQ_QSPI                                                            */
+    SIO_IRQ_PROC0_IRQn        =  15,              /*!< 15 SIO_IRQ_PROC0                                                          */
+    SIO_IRQ_PROC1_IRQn        =  16,              /*!< 16 SIO_IRQ_PROC1                                                          */
+    CLOCKS_IRQ_IRQn           =  17,              /*!< 17 CLOCKS_IRQ                                                             */
+    SPI0_IRQ_IRQn             =  18,              /*!< 18 SPI0_IRQ                                                               */
+    SPI1_IRQ_IRQn             =  19,              /*!< 19 SPI1_IRQ                                                               */
+    UART0_IRQ_IRQn            =  20,              /*!< 20 UART0_IRQ                                                              */
+    UART1_IRQ_IRQn            =  21,              /*!< 21 UART1_IRQ                                                              */
+    ADC_IRQ_FIFO_IRQn         =  22,              /*!< 22 ADC_IRQ_FIFO                                                           */
+    I2C0_IRQ_IRQn             =  23,              /*!< 23 I2C0_IRQ                                                               */
+    I2C1_IRQ_IRQn             =  24,              /*!< 24 I2C1_IRQ                                                               */
+    RTC_IRQ_IRQn              =  25               /*!< 25 RTC_IRQ                                                                */
+} IRQn_Type;
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+/* ==========================  Configuration of the ARM Cortex-M0+ Processor and Core Peripherals  =========================== */
+#define __CM0PLUS_REV                  0x0001U  /*!< CM0PLUS Core Revision                                                     */
+#define __NVIC_PRIO_BITS               2        /*!< Number of Bits used for Priority Levels                                   */
+#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
+#define __VTOR_PRESENT                 1        /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
+#define __MPU_PRESENT                  1        /*!< MPU present                                                               */
+#define __FPU_PRESENT                  0        /*!< FPU present                                                               */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0plus.h"                       /*!< ARM Cortex-M0+ processor and core peripherals                             */
+#include "system_RP2040.h"                      /*!< RP2040 System                                                             */
+
+#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
+#define __IM   __I
+#endif
+#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
+#define __OM   __O
+#endif
+#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
+#define __IOM  __IO
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CMSIS_RP2040_H */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h b/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h
new file mode 100644
index 0000000..30881cc
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h
@@ -0,0 +1,65 @@
+/*************************************************************************//**
+ * @file     system_RP2040.h
+ * @brief    CMSIS-Core(M) Device Peripheral Access Layer Header File for
+ *           Device RP2040
+ * @version  V1.0.0
+ * @date     5. May 2021
+ *****************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CMSIS_SYSTEM_RP2040_H
+#define _CMSIS_SYSTEM_RP2040_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \brief Exception / Interrupt Handler Function Prototype
+*/
+typedef void(*VECTOR_TABLE_Type)(void);
+
+/**
+  \brief System Clock Frequency (Core Clock)
+*/
+extern uint32_t SystemCoreClock;
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CMSIS_SYSTEM_RP2040_H */
diff --git a/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c b/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c
new file mode 100644
index 0000000..055a075
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c
@@ -0,0 +1,52 @@
+/*************************************************************************//**
+ * @file     system_RP2040.c
+ * @brief    CMSIS-Core(M) Device Peripheral Access Layer Header File for
+ *           Device RP2040
+ * @version  V1.0.0
+ * @date     5. May 2021
+ *****************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "RP2040.h"
+#include "hardware/clocks.h"
+
+/*---------------------------------------------------------------------------
+  System Core Clock Variable
+ *---------------------------------------------------------------------------*/
+uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock)*/
+
+/*---------------------------------------------------------------------------
+  System Core Clock function
+ *---------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+    SystemCoreClock = clock_get_hz(clk_sys);
+}
+
+/*---------------------------------------------------------------------------
+  System initialization function
+ *---------------------------------------------------------------------------*/
+void __attribute__((constructor)) SystemInit (void)
+{
+    SystemCoreClockUpdate();
+}
\ No newline at end of file
diff --git a/src/rp2_common/cmsis/stub/CMSIS/LICENSE.txt b/src/rp2_common/cmsis/stub/CMSIS/LICENSE.txt
new file mode 100644
index 0000000..8dada3e
--- /dev/null
+++ b/src/rp2_common/cmsis/stub/CMSIS/LICENSE.txt
@@ -0,0 +1,201 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
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+
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+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
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+
+      "Derivative Works" shall mean any work, whether in Source or Object
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diff --git a/src/rp2_common/hardware_adc/CMakeLists.txt b/src/rp2_common/hardware_adc/CMakeLists.txt
new file mode 100644
index 0000000..291428a
--- /dev/null
+++ b/src/rp2_common/hardware_adc/CMakeLists.txt
@@ -0,0 +1,4 @@
+pico_simple_hardware_target(adc)
+
+# additional library
+target_link_libraries(hardware_adc INTERFACE hardware_resets)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_adc/adc.c b/src/rp2_common/hardware_adc/adc.c
new file mode 100644
index 0000000..9058de0
--- /dev/null
+++ b/src/rp2_common/hardware_adc/adc.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+#include "hardware/adc.h"
+#include "hardware/resets.h"
+
+void adc_init(void) {
+    // ADC is in an unknown state. We should start by resetting it
+    reset_block(RESETS_RESET_ADC_BITS);
+    unreset_block_wait(RESETS_RESET_ADC_BITS);
+
+    // Now turn it back on. Staging of clock etc is handled internally
+    adc_hw->cs = ADC_CS_EN_BITS;
+
+    // Internal staging completes in a few cycles, but poll to be sure
+    while (!(adc_hw->cs & ADC_CS_READY_BITS)) {
+        tight_loop_contents();
+    }
+}
diff --git a/src/rp2_common/hardware_adc/include/hardware/adc.h b/src/rp2_common/hardware_adc/include/hardware/adc.h
new file mode 100644
index 0000000..be82025
--- /dev/null
+++ b/src/rp2_common/hardware_adc/include/hardware/adc.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_ADC_H_
+#define _HARDWARE_ADC_H_
+
+#include "pico.h"
+#include "hardware/structs/adc.h"
+#include "hardware/gpio.h"
+
+/** \file hardware/adc.h
+ *  \defgroup hardware_adc hardware_adc
+ *
+ * Analog to Digital Converter (ADC) API
+ *
+ * The RP2040 has an internal analogue-digital converter (ADC) with the following features:
+ * - SAR ADC
+ * - 500 kS/s (Using an independent 48MHz clock)
+ * - 12 bit (8.7 ENOB)
+ * - 5 input mux:
+ *  - 4 inputs that are available on package pins shared with GPIO[29:26]
+ *  - 1 input is dedicated to the internal temperature sensor
+ * - 4 element receive sample FIFO
+ * - Interrupt generation
+ * - DMA interface
+ *
+ * Although there is only one ADC you can specify the input to it using the adc_select_input() function.
+ * In round robin mode (adc_set_round_robin()), the ADC will use that input and move to the next one after a read.
+ *
+ * User ADC inputs are on 0-3 (GPIO 26-29), the temperature sensor is on input 4.
+ *
+ * Temperature sensor values can be approximated in centigrade as:
+ *
+ * T = 27 - (ADC_Voltage - 0.706)/0.001721
+ *
+ * The FIFO, if used, can contain up to 4 entries.
+ *
+ * \subsection adc_example Example
+ * \addtogroup hardware_adc
+ *
+ * \include hello_adc.c
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_ADC, Enable/disable assertions in the ADC module, type=bool, default=0, group=hardware_adc
+#ifndef PARAM_ASSERTIONS_ENABLED_ADC
+#define PARAM_ASSERTIONS_ENABLED_ADC 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief  Initialise the ADC HW
+ *  \ingroup hardware_adc
+ *
+ */
+void adc_init(void);
+
+/*! \brief  Initialise the gpio for use as an ADC pin
+ *  \ingroup hardware_adc
+ *
+ * Prepare a GPIO for use with ADC by disabling all digital functions.
+ *
+ * \param gpio The GPIO number to use. Allowable GPIO numbers are 26 to 29 inclusive.
+ */
+static inline void adc_gpio_init(uint gpio) {
+    invalid_params_if(ADC, gpio < 26 || gpio > 29);
+    // Select NULL function to make output driver hi-Z
+    gpio_set_function(gpio, GPIO_FUNC_NULL);
+    // Also disable digital pulls and digital receiver
+    gpio_disable_pulls(gpio);
+    gpio_set_input_enabled(gpio, false);
+}
+
+/*! \brief  ADC input select
+ *  \ingroup hardware_adc
+ *
+ * Select an ADC input. 0...3 are GPIOs 26...29 respectively.
+ * Input 4 is the onboard temperature sensor.
+ *
+ * \param input Input to select.
+ */
+static inline void adc_select_input(uint input) {
+    valid_params_if(ADC, input < NUM_ADC_CHANNELS);
+    hw_write_masked(&adc_hw->cs, input << ADC_CS_AINSEL_LSB, ADC_CS_AINSEL_BITS);
+}
+
+/*! \brief  Get the currently selected ADC input channel
+ *  \ingroup hardware_adc
+ *
+ * \return The currently selected input channel. 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor.
+ */
+static inline uint adc_get_selected_input(void) {
+    return (adc_hw->cs & ADC_CS_AINSEL_BITS) >> ADC_CS_AINSEL_LSB;
+}
+
+/*! \brief  Round Robin sampling selector
+ *  \ingroup hardware_adc
+ *
+ * This function sets which inputs are to be run through in round robin mode.
+ * Value between 0 and 0x1f (bit 0 to bit 4 for GPIO 26 to 29 and temperature sensor input respectively)
+ *
+ * \param input_mask A bit pattern indicating which of the 5 inputs are to be sampled. Write a value of 0 to disable round robin sampling.
+ */
+static inline void adc_set_round_robin(uint input_mask) {
+    invalid_params_if(ADC, input_mask & ~ADC_CS_RROBIN_BITS);
+    hw_write_masked(&adc_hw->cs, input_mask << ADC_CS_RROBIN_LSB, ADC_CS_RROBIN_BITS);
+}
+
+/*! \brief Enable the onboard temperature sensor
+ *  \ingroup hardware_adc
+ *
+ * \param enable Set true to power on the onboard temperature sensor, false to power off.
+ *
+ */
+static inline void adc_set_temp_sensor_enabled(bool enable) {
+    if (enable)
+        hw_set_bits(&adc_hw->cs, ADC_CS_TS_EN_BITS);
+    else
+        hw_clear_bits(&adc_hw->cs, ADC_CS_TS_EN_BITS);
+}
+
+/*! \brief Perform a single conversion
+ *  \ingroup hardware_adc
+ *
+ *  Performs an ADC conversion, waits for the result, and then returns it.
+ *
+ * \return Result of the conversion.
+ */
+static inline uint16_t adc_read(void) {
+    hw_set_bits(&adc_hw->cs, ADC_CS_START_ONCE_BITS);
+
+    while (!(adc_hw->cs & ADC_CS_READY_BITS))
+        tight_loop_contents();
+
+    return (uint16_t) adc_hw->result;
+}
+
+/*! \brief Enable or disable free-running sampling mode
+ *  \ingroup hardware_adc
+ *
+ * \param run false to disable, true to enable free running conversion mode.
+ */
+static inline void adc_run(bool run) {
+    if (run)
+        hw_set_bits(&adc_hw->cs, ADC_CS_START_MANY_BITS);
+    else
+        hw_clear_bits(&adc_hw->cs, ADC_CS_START_MANY_BITS);
+}
+
+/*! \brief Set the ADC Clock divisor
+ *  \ingroup hardware_adc
+ *
+ * Period of samples will be (1 + div) cycles on average. Note it takes 96 cycles to perform a conversion,
+ * so any period less than that will be clamped to 96.
+ *
+ * \param clkdiv If non-zero, conversion will be started at intervals rather than back to back.
+ */
+static inline void adc_set_clkdiv(float clkdiv) {
+    invalid_params_if(ADC, clkdiv >= 1 << (ADC_DIV_INT_MSB - ADC_DIV_INT_LSB + 1));
+    adc_hw->div = (uint32_t)(clkdiv * (float) (1 << ADC_DIV_INT_LSB));
+}
+
+/*! \brief Setup the ADC FIFO
+ *  \ingroup hardware_adc
+ *
+ * FIFO is 4 samples long, if a conversion is completed and the FIFO is full, the result is dropped.
+ *
+ * \param en Enables write each conversion result to the FIFO
+ * \param dreq_en Enable DMA requests when FIFO contains data
+ * \param dreq_thresh Threshold for DMA requests/FIFO IRQ if enabled.
+ * \param err_in_fifo If enabled, bit 15 of the FIFO contains error flag for each sample
+ * \param byte_shift Shift FIFO contents to be one byte in size (for byte DMA) - enables DMA to byte buffers.
+ */
+ static inline void adc_fifo_setup(bool en, bool dreq_en, uint16_t dreq_thresh, bool err_in_fifo, bool byte_shift) {
+    hw_write_masked(&adc_hw->fcs,
+                   (bool_to_bit(en) << ADC_FCS_EN_LSB) |
+                   (bool_to_bit(dreq_en) << ADC_FCS_DREQ_EN_LSB) |
+                   (((uint)dreq_thresh) << ADC_FCS_THRESH_LSB) |
+                   (bool_to_bit(err_in_fifo) << ADC_FCS_ERR_LSB) |
+                   (bool_to_bit(byte_shift) << ADC_FCS_SHIFT_LSB),
+                   ADC_FCS_EN_BITS |
+                   ADC_FCS_DREQ_EN_BITS |
+                   ADC_FCS_THRESH_BITS |
+                   ADC_FCS_ERR_BITS |
+                   ADC_FCS_SHIFT_BITS
+    );
+}
+
+/*! \brief Check FIFO empty state
+ *  \ingroup hardware_adc
+ *
+ * \return Returns true if the FIFO is empty
+ */
+static inline bool adc_fifo_is_empty(void) {
+    return !!(adc_hw->fcs & ADC_FCS_EMPTY_BITS);
+}
+
+/*! \brief Get number of entries in the ADC FIFO
+ *  \ingroup hardware_adc
+ *
+ * The ADC FIFO is 4 entries long. This function will return how many samples are currently present.
+ */
+static inline uint8_t adc_fifo_get_level(void) {
+    return (adc_hw->fcs & ADC_FCS_LEVEL_BITS) >> ADC_FCS_LEVEL_LSB;
+}
+
+/*! \brief Get ADC result from FIFO
+ *  \ingroup hardware_adc
+ *
+ * Pops the latest result from the ADC FIFO.
+ */
+static inline uint16_t adc_fifo_get(void) {
+    return (uint16_t)adc_hw->fifo;
+}
+
+/*! \brief Wait for the ADC FIFO to have data.
+ *  \ingroup hardware_adc
+ *
+ * Blocks until data is present in the FIFO
+ */
+static inline uint16_t adc_fifo_get_blocking(void) {
+    while (adc_fifo_is_empty())
+        tight_loop_contents();
+    return (uint16_t)adc_hw->fifo;
+}
+
+/*! \brief Drain the ADC FIFO
+ *  \ingroup hardware_adc
+ *
+ * Will wait for any conversion to complete then drain the FIFO, discarding any results.
+ */
+static inline void adc_fifo_drain(void) {
+    // Potentially there is still a conversion in progress -- wait for this to complete before draining
+    while (!(adc_hw->cs & ADC_CS_READY_BITS))
+        tight_loop_contents();
+    while (!adc_fifo_is_empty())
+        (void) adc_fifo_get();
+}
+
+/*! \brief Enable/Disable ADC interrupts.
+ *  \ingroup hardware_adc
+ *
+ * \param enabled Set to true to enable the ADC interrupts, false to disable
+ */
+static inline void adc_irq_set_enabled(bool enabled) {
+    adc_hw->inte = !!enabled;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_base/CMakeLists.txt b/src/rp2_common/hardware_base/CMakeLists.txt
new file mode 100644
index 0000000..e045618
--- /dev/null
+++ b/src/rp2_common/hardware_base/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_library(hardware_base INTERFACE)
+target_include_directories(hardware_base INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+target_link_libraries(hardware_base INTERFACE pico_base_headers)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_base/include/hardware/address_mapped.h b/src/rp2_common/hardware_base/include/hardware/address_mapped.h
new file mode 100644
index 0000000..a3b9584
--- /dev/null
+++ b/src/rp2_common/hardware_base/include/hardware/address_mapped.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_ADDRESS_MAPPED_H
+#define _HARDWARE_ADDRESS_MAPPED_H
+
+#include "pico.h"
+#include "hardware/regs/addressmap.h"
+
+/** \file address_mapped.h
+ *  \defgroup hardware_base hardware_base
+ *
+ *  Low-level types and (atomic) accessors for memory-mapped hardware registers
+ *
+ *  `hardware_base` defines the low level types and access functions for memory mapped hardware registers. It is included
+ *  by default by all other hardware libraries.
+ *
+ *  The following register access typedefs codify the access type (read/write) and the bus size (8/16/32) of the hardware register.
+ *  The register type names are formed by concatenating one from each of the 3 parts A, B, C
+
+ *   A    | B | C | Meaning
+ *  ------|---|---|--------
+ *  io_   |   |   | A Memory mapped IO register
+ *  &nbsp;|ro_|   | read-only access
+ *  &nbsp;|rw_|   | read-write access
+ *  &nbsp;|wo_|   | write-only access (can't actually be enforced via C API)
+ *  &nbsp;|   |  8| 8-bit wide access
+ *  &nbsp;|   | 16| 16-bit wide access
+ *  &nbsp;|   | 32| 32-bit wide access
+ *
+ *  When dealing with these types, you will always use a pointer, i.e. `io_rw_32 *some_reg` is a pointer to a read/write
+ *  32 bit register that you can write with `*some_reg = value`, or read with `value = *some_reg`.
+ *
+ *  RP2040 hardware is also aliased to provide atomic setting, clear or flipping of a subset of the bits within
+ *  a hardware register so that concurrent access by two cores is always consistent with one atomic operation
+ *  being performed first, followed by the second.
+ *
+ *  See hw_set_bits(), hw_clear_bits() and hw_xor_bits() provide for atomic access via a pointer to a 32 bit register
+ *
+ *  Additionally given a pointer to a structure representing a piece of hardware (e.g. `dma_hw_t *dma_hw` for the DMA controller), you can
+ *  get an alias to the entire structure such that writing any member (register) within the structure is equivalent
+ *  to an atomic operation via hw_set_alias(), hw_clear_alias() or hw_xor_alias()...
+ *
+ *  For example `hw_set_alias(dma_hw)->inte1 = 0x80;` will set bit 7 of the INTE1 register of the DMA controller,
+ *  leaving the other bits unchanged.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define check_hw_layout(type, member, offset) static_assert(offsetof(type, member) == (offset), "hw offset mismatch")
+#define check_hw_size(type, size) static_assert(sizeof(type) == (size), "hw size mismatch")
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS, Enable/disable assertions in memory address aliasing macros, type=bool, default=0, group=hardware_base
+#ifndef PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS
+#define PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS 0
+#endif
+
+typedef volatile uint32_t io_rw_32;
+typedef const volatile uint32_t io_ro_32;
+typedef volatile uint32_t io_wo_32;
+typedef volatile uint16_t io_rw_16;
+typedef const volatile uint16_t io_ro_16;
+typedef volatile uint16_t io_wo_16;
+typedef volatile uint8_t io_rw_8;
+typedef const volatile uint8_t io_ro_8;
+typedef volatile uint8_t io_wo_8;
+
+typedef volatile uint8_t *const ioptr;
+typedef ioptr const const_ioptr;
+
+// A non-functional (empty) helper macro to help IDEs follow links from the autogenerated
+// hardware struct headers in hardware/structs/xxx.h to the raw register definitions
+// in hardware/regs/xxx.h. A preprocessor define such as TIMER_TIMEHW_OFFSET (a timer register offset)
+// is not generally clickable (in an IDE) if placed in a C comment, so _REG_(TIMER_TIMEHW_OFFSET) is
+// included outside of a comment instead
+#define _REG_(x)
+
+// Helper method used by hw_alias macros to optionally check input validity
+#define hw_alias_check_addr(addr) ((uintptr_t)(addr))
+// can't use the following impl as it breaks existing static declarations using hw_alias, so would be a backwards incompatibility
+//static __force_inline uint32_t hw_alias_check_addr(volatile void *addr) {
+//    uint32_t rc = (uintptr_t)addr;
+//    invalid_params_if(ADDRESS_ALIAS, rc < 0x40000000); // catch likely non HW pointer types
+//    return rc;
+//}
+
+// Helper method used by xip_alias macros to optionally check input validity
+static __force_inline uint32_t xip_alias_check_addr(const void *addr) {
+    uint32_t rc = (uintptr_t)addr;
+    valid_params_if(ADDRESS_ALIAS, rc >= XIP_MAIN_BASE && rc < XIP_NOALLOC_BASE);
+    return rc;
+}
+
+// Untyped conversion alias pointer generation macros
+#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | hw_alias_check_addr(addr)))
+#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | hw_alias_check_addr(addr)))
+#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | hw_alias_check_addr(addr)))
+#define xip_noalloc_alias_untyped(addr) ((void *)(XIP_NOALLOC_BASE | xip_alias_check_addr(addr)))
+#define xip_nocache_alias_untyped(addr) ((void *)(XIP_NOCACHE_BASE | xip_alias_check_addr(addr)))
+#define xip_nocache_noalloc_alias_untyped(addr) ((void *)(XIP_NOCACHE_NOALLOC_BASE | xip_alias_check_addr(addr)))
+
+// Typed conversion alias pointer generation macros
+#define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p))
+#define hw_clear_alias(p) ((typeof(p))hw_clear_alias_untyped(p))
+#define hw_xor_alias(p) ((typeof(p))hw_xor_alias_untyped(p))
+#define xip_noalloc_alias(p) ((typeof(p))xip_noalloc_alias_untyped(p))
+#define xip_nocache_alias(p) ((typeof(p))xip_nocache_alias_untyped(p))
+#define xip_nocache_noalloc_alias(p) ((typeof(p))xip_nocache_noalloc_alias_untyped(p))
+
+/*! \brief Atomically set the specified bits to 1 in a HW register
+ *  \ingroup hardware_base
+ *
+ * \param addr Address of writable register
+ * \param mask Bit-mask specifying bits to set
+ */
+__force_inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) {
+    *(io_rw_32 *) hw_set_alias_untyped((volatile void *) addr) = mask;
+}
+
+/*! \brief Atomically clear the specified bits to 0 in a HW register
+ *  \ingroup hardware_base
+ *
+ * \param addr Address of writable register
+ * \param mask Bit-mask specifying bits to clear
+ */
+__force_inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) {
+    *(io_rw_32 *) hw_clear_alias_untyped((volatile void *) addr) = mask;
+}
+
+/*! \brief Atomically flip the specified bits in a HW register
+ *  \ingroup hardware_base
+ *
+ * \param addr Address of writable register
+ * \param mask Bit-mask specifying bits to invert
+ */
+__force_inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) {
+    *(io_rw_32 *) hw_xor_alias_untyped((volatile void *) addr) = mask;
+}
+
+/*! \brief Set new values for a sub-set of the bits in a HW register
+ *  \ingroup hardware_base
+ *
+ * Sets destination bits to values specified in \p values, if and only if corresponding bit in \p write_mask is set
+ *
+ * Note: this method allows safe concurrent modification of *different* bits of
+ * a register, but multiple concurrent access to the same bits is still unsafe.
+ *
+ * \param addr Address of writable register
+ * \param values Bits values
+ * \param write_mask Mask of bits to change
+ */
+__force_inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask) {
+    hw_xor_bits(addr, (*addr ^ values) & write_mask);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_claim/CMakeLists.txt b/src/rp2_common/hardware_claim/CMakeLists.txt
new file mode 100644
index 0000000..63f4806
--- /dev/null
+++ b/src/rp2_common/hardware_claim/CMakeLists.txt
@@ -0,0 +1,2 @@
+pico_simple_hardware_target(claim)
+target_link_libraries(hardware_claim INTERFACE hardware_sync)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_claim/claim.c b/src/rp2_common/hardware_claim/claim.c
new file mode 100644
index 0000000..c96764f
--- /dev/null
+++ b/src/rp2_common/hardware_claim/claim.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/claim.h"
+
+uint32_t hw_claim_lock() {
+    return spin_lock_blocking(spin_lock_instance(PICO_SPINLOCK_ID_HARDWARE_CLAIM));
+}
+
+void hw_claim_unlock(uint32_t save) {
+    spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_HARDWARE_CLAIM), save);
+}
+
+inline bool hw_is_claimed(const uint8_t *bits, uint bit_index) {
+    return (bits[bit_index >> 3u] & (1u << (bit_index & 7u)));
+}
+
+void hw_claim_or_assert(uint8_t *bits, uint bit_index, const char *message) {
+    uint32_t save = hw_claim_lock();
+    if (hw_is_claimed(bits, bit_index)) {
+        panic(message, bit_index);
+    } else {
+        bits[bit_index >> 3u] |= (uint8_t)(1u << (bit_index & 7u));
+    }
+    hw_claim_unlock(save);
+}
+
+int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint bit_msb, const char *message) {
+    // don't bother check lsb / msb order as if wrong, then it'll fail anyway
+    uint32_t save = hw_claim_lock();
+    int found_bit = -1;
+    for(uint bit=bit_lsb; bit <= bit_msb; bit++) {
+        if (!hw_is_claimed(bits, bit)) {
+            bits[bit >> 3u] |= (uint8_t)(1u << (bit & 7u));
+            found_bit = (int)bit;
+            break;
+        }
+    }
+    hw_claim_unlock(save);
+    if (found_bit < 0 && required) {
+        panic(message);
+    }
+    return found_bit;
+}
+
+void hw_claim_clear(uint8_t *bits, uint bit_index) {
+    uint32_t save = hw_claim_lock();
+    assert(hw_is_claimed(bits, bit_index));
+    bits[bit_index >> 3u] &= (uint8_t) ~(1u << (bit_index & 7u));
+    hw_claim_unlock(save);
+}
+
+
diff --git a/src/rp2_common/hardware_claim/include/hardware/claim.h b/src/rp2_common/hardware_claim/include/hardware/claim.h
new file mode 100644
index 0000000..5c93453
--- /dev/null
+++ b/src/rp2_common/hardware_claim/include/hardware/claim.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_CLAIM_H
+#define _HARDWARE_CLAIM_H
+
+#include "pico.h"
+#include "hardware/sync.h"
+
+/** \file claim.h
+ *  \defgroup hardware_claim hardware_claim
+ *
+ *  Lightweight hardware resource management
+ *
+ * `hardware_claim` provides a simple API for management of hardware resources at runtime.
+ *
+ * This API is usually called by other hardware specific _claiming_ APIs and provides simple
+ * multi-core safe methods to manipulate compact bit-sets representing hardware resources.
+ *
+ * This API allows any other library to cooperatively participate in a scheme by which
+ * both compile time and runtime allocation of resources can co-exist, and conflicts
+ * can be avoided or detected (depending on the use case) without the libraries having
+ * any other knowledge of each other.
+ *
+ * Facilities are providing for:
+ *
+ * 1. Claiming resources (and asserting if they are already claimed)
+ * 2. Freeing (unclaiming) resources
+ * 3. Finding unused resources
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Atomically claim a resource, panicking if it is already in use
+ *  \ingroup hardware_claim
+ *
+ * The resource ownership is indicated by the bit_index bit in an array of bits.
+ *
+ * \param bits pointer to an array of bits (8 bits per byte)
+ * \param bit_index resource to claim (bit index into array of bits)
+ * \param message string to display if the bit cannot be claimed; note this may have a single printf format "%d" for the bit
+ */
+void hw_claim_or_assert(uint8_t *bits, uint bit_index, const char *message);
+
+/*! \brief Atomically claim one resource out of a range of resources, optionally asserting if none are free
+ *  \ingroup hardware_claim
+ *
+ * \param bits pointer to an array of bits (8 bits per byte)
+ * \param required true if this method should panic if the resource is not free
+ * \param bit_lsb the lower bound (inclusive) of the resource range to claim from
+ * \param bit_msb the upper bound (inclusive) of the resource range to claim from
+ * \param message string to display if the bit cannot be claimed
+ * \return the bit index representing the claimed or -1 if none are available in the range, and required = false
+ */
+int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint bit_msb, const char *message);
+
+/*! \brief Determine if a resource is claimed at the time of the call
+ *  \ingroup hardware_claim
+ *
+ * The resource ownership is indicated by the bit_index bit in an array of bits.
+ *
+ * \param bits pointer to an array of bits (8 bits per byte)
+ * \param bit_index resource to check (bit index into array of bits)
+ * \return true if the resource is claimed
+ */
+bool hw_is_claimed(const uint8_t *bits, uint bit_index);
+
+/*! \brief Atomically unclaim a resource
+ *  \ingroup hardware_claim
+ *
+ * The resource ownership is indicated by the bit_index bit in an array of bits.
+ *
+ * \param bits pointer to an array of bits (8 bits per byte)
+ * \param bit_index resource to unclaim (bit index into array of bits)
+ */
+void hw_claim_clear(uint8_t *bits, uint bit_index);
+
+/*! \brief Acquire the runtime mutual exclusion lock provided by the `hardware_claim` library
+ *  \ingroup hardware_claim
+ *
+ * This method is called automatically by the other `hw_claim_` methods, however it is provided as a convenience
+ * to code that might want to protect other hardware initialization code from concurrent use.
+ *
+ * \note hw_claim_lock() uses a spin lock internally, so disables interrupts on the calling core, and will deadlock
+ * if the calling core already owns the lock.
+ *
+ * \return a token to pass to hw_claim_unlock()
+ */
+uint32_t hw_claim_lock(void);
+
+/*! \brief Release the runtime mutual exclusion lock provided by the `hardware_claim` library
+ *  \ingroup hardware_claim
+ *
+ * \note This method MUST be called from the same core that call hw_claim_lock()
+ *
+ * \param token the token returned by the corresponding call to hw_claim_lock()
+ */
+void hw_claim_unlock(uint32_t token);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_clocks/CMakeLists.txt b/src/rp2_common/hardware_clocks/CMakeLists.txt
new file mode 100644
index 0000000..ceb29e2
--- /dev/null
+++ b/src/rp2_common/hardware_clocks/CMakeLists.txt
@@ -0,0 +1,13 @@
+pico_simple_hardware_target(clocks)
+
+target_link_libraries(hardware_clocks INTERFACE
+        hardware_gpio
+        hardware_irq
+        hardware_resets
+        hardware_pll
+        # not currently used by clocks.c, but sensibly bundled here
+        # as changing frequencies may require upping voltage
+        hardware_vreg
+        hardware_watchdog
+        hardware_xosc
+)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_clocks/clocks.c b/src/rp2_common/hardware_clocks/clocks.c
new file mode 100644
index 0000000..f51331a
--- /dev/null
+++ b/src/rp2_common/hardware_clocks/clocks.c
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+#include "hardware/regs/clocks.h"
+#include "hardware/platform_defs.h"
+#include "hardware/clocks.h"
+#include "hardware/watchdog.h"
+#include "hardware/pll.h"
+#include "hardware/xosc.h"
+#include "hardware/irq.h"
+#include "hardware/gpio.h"
+
+check_hw_layout(clocks_hw_t, clk[clk_adc].selected, CLOCKS_CLK_ADC_SELECTED_OFFSET);
+check_hw_layout(clocks_hw_t, fc0.result, CLOCKS_FC0_RESULT_OFFSET);
+check_hw_layout(clocks_hw_t, ints, CLOCKS_INTS_OFFSET);
+
+static uint32_t configured_freq[CLK_COUNT];
+
+static resus_callback_t _resus_callback;
+
+// Clock muxing consists of two components:
+// - A glitchless mux, which can be switched freely, but whose inputs must be
+//   free-running
+// - An auxiliary (glitchy) mux, whose output glitches when switched, but has
+//   no constraints on its inputs
+// Not all clocks have both types of mux.
+static inline bool has_glitchless_mux(enum clock_index clk_index) {
+    return clk_index == clk_sys || clk_index == clk_ref;
+}
+
+void clock_stop(enum clock_index clk_index) {
+    clock_hw_t *clock = &clocks_hw->clk[clk_index];
+    hw_clear_bits(&clock->ctrl, CLOCKS_CLK_USB_CTRL_ENABLE_BITS);
+    configured_freq[clk_index] = 0;
+}
+
+/// \tag::clock_configure[]
+bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq) {
+    uint32_t div;
+
+    assert(src_freq >= freq);
+
+    if (freq > src_freq)
+        return false;
+
+    // Div register is 24.8 int.frac divider so multiply by 2^8 (left shift by 8)
+    div = (uint32_t) (((uint64_t) src_freq << 8) / freq);
+
+    clock_hw_t *clock = &clocks_hw->clk[clk_index];
+
+    // If increasing divisor, set divisor before source. Otherwise set source
+    // before divisor. This avoids a momentary overspeed when e.g. switching
+    // to a faster source and increasing divisor to compensate.
+    if (div > clock->div)
+        clock->div = div;
+
+    // If switching a glitchless slice (ref or sys) to an aux source, switch
+    // away from aux *first* to avoid passing glitches when changing aux mux.
+    // Assume (!!!) glitchless source 0 is no faster than the aux source.
+    if (has_glitchless_mux(clk_index) && src == CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX) {
+        hw_clear_bits(&clock->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS);
+        while (!(clock->selected & 1u))
+            tight_loop_contents();
+    }
+    // If no glitchless mux, cleanly stop the clock to avoid glitches
+    // propagating when changing aux mux. Note it would be a really bad idea
+    // to do this on one of the glitchless clocks (clk_sys, clk_ref).
+    else {
+        // Disable clock. On clk_ref and clk_sys this does nothing,
+        // all other clocks have the ENABLE bit in the same position.
+        hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
+        if (configured_freq[clk_index] > 0) {
+            // Delay for 3 cycles of the target clock, for ENABLE propagation.
+            // Note XOSC_COUNT is not helpful here because XOSC is not
+            // necessarily running, nor is timer... so, 3 cycles per loop:
+            uint delay_cyc = configured_freq[clk_sys] / configured_freq[clk_index] + 1;
+            asm volatile (
+                ".syntax unified \n\t"
+                "1: \n\t"
+                "subs %0, #1 \n\t"
+                "bne 1b"
+                : "+r" (delay_cyc)
+            );
+        }
+    }
+
+    // Set aux mux first, and then glitchless mux if this clock has one
+    hw_write_masked(&clock->ctrl,
+        (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB),
+        CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS
+    );
+
+    if (has_glitchless_mux(clk_index)) {
+        hw_write_masked(&clock->ctrl,
+            src << CLOCKS_CLK_REF_CTRL_SRC_LSB,
+            CLOCKS_CLK_REF_CTRL_SRC_BITS
+        );
+        while (!(clock->selected & (1u << src)))
+            tight_loop_contents();
+    }
+
+    // Enable clock. On clk_ref and clk_sys this does nothing,
+    // all other clocks have the ENABLE bit in the same position.
+    hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
+
+    // Now that the source is configured, we can trust that the user-supplied
+    // divisor is a safe value.
+    clock->div = div;
+
+    // Store the configured frequency
+    configured_freq[clk_index] = (uint32_t)(((uint64_t) src_freq << 8) / div);
+
+    return true;
+}
+/// \end::clock_configure[]
+
+void clocks_init(void) {
+    // Start tick in watchdog
+    watchdog_start_tick(XOSC_MHZ);
+
+    // Everything is 48MHz on FPGA apart from RTC. Otherwise set to 0 and will be set in clock configure
+    if (running_on_fpga()) {
+        for (uint i = 0; i < CLK_COUNT; i++) {
+            configured_freq[i] = 48 * MHZ;
+        }
+        configured_freq[clk_rtc] = 46875;
+        return;
+    }
+
+    // Disable resus that may be enabled from previous software
+    clocks_hw->resus.ctrl = 0;
+
+    // Enable the xosc
+    xosc_init();
+
+    // Before we touch PLLs, switch sys and ref cleanly away from their aux sources.
+    hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS);
+    while (clocks_hw->clk[clk_sys].selected != 0x1)
+        tight_loop_contents();
+    hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS);
+    while (clocks_hw->clk[clk_ref].selected != 0x1)
+        tight_loop_contents();
+
+    /// \tag::pll_settings[]
+    // Configure PLLs
+    //                   REF     FBDIV VCO            POSTDIV
+    // PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHZ / 6 / 2 = 125MHz
+    // PLL USB: 12 / 1 = 12MHz * 40  = 480 MHz / 5 / 2 =  48MHz
+    /// \end::pll_settings[]
+
+    /// \tag::pll_init[]
+    pll_init(pll_sys, 1, 1500 * MHZ, 6, 2);
+    pll_init(pll_usb, 1, 480 * MHZ, 5, 2);
+    /// \end::pll_init[]
+
+    // Configure clocks
+    // CLK_REF = XOSC (12MHz) / 1 = 12MHz
+    clock_configure(clk_ref,
+                    CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC,
+                    0, // No aux mux
+                    12 * MHZ,
+                    12 * MHZ);
+
+    /// \tag::configure_clk_sys[]
+    // CLK SYS = PLL SYS (125MHz) / 1 = 125MHz
+    clock_configure(clk_sys,
+                    CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
+                    CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS,
+                    125 * MHZ,
+                    125 * MHZ);
+    /// \end::configure_clk_sys[]
+
+    // CLK USB = PLL USB (48MHz) / 1 = 48MHz
+    clock_configure(clk_usb,
+                    0, // No GLMUX
+                    CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
+                    48 * MHZ,
+                    48 * MHZ);
+
+    // CLK ADC = PLL USB (48MHZ) / 1 = 48MHz
+    clock_configure(clk_adc,
+                    0, // No GLMUX
+                    CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
+                    48 * MHZ,
+                    48 * MHZ);
+
+    // CLK RTC = PLL USB (48MHz) / 1024 = 46875Hz
+    clock_configure(clk_rtc,
+                    0, // No GLMUX
+                    CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
+                    48 * MHZ,
+                    46875);
+
+    // CLK PERI = clk_sys. Used as reference clock for Peripherals. No dividers so just select and enable
+    // Normally choose clk_sys or clk_usb
+    clock_configure(clk_peri,
+                    0,
+                    CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS,
+                    125 * MHZ,
+                    125 * MHZ);
+}
+
+/// \tag::clock_get_hz[]
+uint32_t clock_get_hz(enum clock_index clk_index) {
+    return configured_freq[clk_index];
+}
+/// \end::clock_get_hz[]
+
+void clock_set_reported_hz(enum clock_index clk_index, uint hz) {
+    configured_freq[clk_index] = hz;
+}
+
+/// \tag::frequency_count_khz[]
+uint32_t frequency_count_khz(uint src) {
+    fc_hw_t *fc = &clocks_hw->fc0;
+
+    // If frequency counter is running need to wait for it. It runs even if the source is NULL
+    while(fc->status & CLOCKS_FC0_STATUS_RUNNING_BITS) {
+        tight_loop_contents();
+    }
+
+    // Set reference freq
+    fc->ref_khz = clock_get_hz(clk_ref) / 1000;
+
+    // FIXME: Don't pick random interval. Use best interval
+    fc->interval = 10;
+
+    // No min or max
+    fc->min_khz = 0;
+    fc->max_khz = 0xffffffff;
+
+    // Set SRC which automatically starts the measurement
+    fc->src = src;
+
+    while(!(fc->status & CLOCKS_FC0_STATUS_DONE_BITS)) {
+        tight_loop_contents();
+    }
+
+    // Return the result
+    return fc->result >> CLOCKS_FC0_RESULT_KHZ_LSB;
+}
+/// \end::frequency_count_khz[]
+
+static void clocks_handle_resus(void) {
+    // Set clk_sys back to the ref clock rather than it being forced to clk_ref
+    // by resus. Call the user's resus callback if they have set one
+
+    // CLK SYS = CLK_REF. Must be running for this code to be running
+    uint clk_ref_freq = clock_get_hz(clk_ref);
+    clock_configure(clk_sys,
+                    CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF,
+                    0,
+                    clk_ref_freq,
+                    clk_ref_freq);
+
+    // Assert we have been resussed
+    assert(clocks_hw->resus.status & CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS);
+
+    // Now we have fixed clk_sys we can safely remove the resus
+    hw_set_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS);
+    hw_clear_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS);
+
+    // Now we should no longer be resussed
+    assert(!(clocks_hw->resus.status & CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS));
+
+    // Call the user's callback to notify them of the resus event
+    if (_resus_callback) {
+        _resus_callback();
+    }
+}
+
+static void clocks_irq_handler(void) {
+    // Clocks interrupt handler. Only resus but handle irq
+    // defensively just in case.
+    uint32_t ints = clocks_hw->ints;
+
+    if (ints & CLOCKS_INTE_CLK_SYS_RESUS_BITS) {
+        ints &= ~CLOCKS_INTE_CLK_SYS_RESUS_BITS;
+        clocks_handle_resus();
+    }
+
+#ifndef NDEBUG
+    if (ints) {
+        panic("Unexpected clocks irq\n");
+    }
+#endif
+}
+
+void clocks_enable_resus(resus_callback_t resus_callback) {
+    // Restart clk_sys if it is stopped by forcing it
+    // to the default source of clk_ref. If clk_ref stops running this will
+    // not work.
+
+    // Store user's resus callback
+    _resus_callback = resus_callback;
+
+    irq_set_exclusive_handler(CLOCKS_IRQ, clocks_irq_handler);
+
+    // Enable the resus interrupt in clocks
+    clocks_hw->inte = CLOCKS_INTE_CLK_SYS_RESUS_BITS;
+
+    // Enable the clocks irq
+    irq_set_enabled(CLOCKS_IRQ, true);
+
+    // 2 * clk_ref freq / clk_sys_min_freq;
+    // assume clk_ref is 3MHz and we want clk_sys to be no lower than 1MHz
+    uint timeout = 2 * 3 * 1;
+
+    // Enable resus with the maximum timeout
+    clocks_hw->resus.ctrl = CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS | timeout;
+}
+
+void clock_gpio_init(uint gpio, uint src, uint div) {
+    // Bit messy but it's as much code to loop through a lookup
+    // table. The sources for each gpout generators are the same
+    // so just call with the sources from GP0
+    uint gpclk = 0;
+    if      (gpio == 21) gpclk = clk_gpout0;
+    else if (gpio == 23) gpclk = clk_gpout1;
+    else if (gpio == 24) gpclk = clk_gpout2;
+    else if (gpio == 25) gpclk = clk_gpout3;
+    else {
+        invalid_params_if(CLOCKS, true);
+    }
+
+    // Set up the gpclk generator
+    clocks_hw->clk[gpclk].ctrl = (src << CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB) |
+                                 CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS;
+    clocks_hw->clk[gpclk].div = div << CLOCKS_CLK_GPOUT0_DIV_INT_LSB;
+
+    // Set gpio pin to gpclock function
+    gpio_set_function(gpio, GPIO_FUNC_GPCK);
+}
+
+static const uint8_t gpin0_src[CLK_COUNT] = {
+    CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT0
+    CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT1
+    CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT2
+    CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT3
+    CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0,    // CLK_REF
+    CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0,    // CLK_SYS
+    CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0,   // CLK_PERI
+    CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0,    // CLK_USB
+    CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0,    // CLK_ADC
+    CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0,    // CLK_RTC
+};
+
+// Assert GPIN1 is GPIN0 + 1
+static_assert(CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1    == (CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0    + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1    == (CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0    + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   == (CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1    == (CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0    + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1    == (CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0    + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1    == (CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0    + 1), "hw mismatch");
+
+bool clock_configure_gpin(enum clock_index clk_index, uint gpio, uint32_t src_freq, uint32_t freq) {
+    // Configure a clock to run from a GPIO input
+    uint gpin = 0;
+    if      (gpio == 20) gpin = 0;
+    else if (gpio == 22) gpin = 1;
+    else {
+        invalid_params_if(CLOCKS, true);
+    }
+
+    // Work out sources. GPIN is always an auxsrc
+    uint src = 0;
+
+    // GPIN1 == GPIN0 + 1
+    uint auxsrc = gpin0_src[clk_index] + gpin;
+
+    if (has_glitchless_mux(clk_index)) {
+        // AUX src is always 1
+        src = 1;
+    }
+
+    // Set the GPIO function
+    gpio_set_function(gpio, GPIO_FUNC_GPCK);
+
+    // Now we have the src, auxsrc, and configured the gpio input
+    // call clock configure to run the clock from a gpio
+    return clock_configure(clk_index, src, auxsrc, src_freq, freq);
+}
diff --git a/src/rp2_common/hardware_clocks/include/hardware/clocks.h b/src/rp2_common/hardware_clocks/include/hardware/clocks.h
new file mode 100644
index 0000000..04d373d
--- /dev/null
+++ b/src/rp2_common/hardware_clocks/include/hardware/clocks.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_CLOCKS_H_
+#define _HARDWARE_CLOCKS_H_
+
+#include "pico.h"
+#include "hardware/structs/clocks.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file hardware/clocks.h
+ *  \defgroup hardware_clocks hardware_clocks
+ *
+ * Clock Management API
+ *
+ * This API provides a high level interface to the clock functions.
+ *
+ * The clocks block provides independent clocks to on-chip and external components. It takes inputs from a variety of clock
+ * sources allowing the user to trade off performance against cost, board area and power consumption. From these sources
+ * it uses multiple clock generators to provide the required clocks. This architecture allows the user flexibility to start and
+ * stop clocks independently and to vary some clock frequencies whilst maintaining others at their optimum frequencies
+ *
+ * Please refer to the datasheet for more details on the RP2040 clocks.
+ *
+ * The clock source depends on which clock you are attempting to configure. The first table below shows main clock sources. If
+ * you are not setting the Reference clock or the System clock, or you are specifying that one of those two will be using an auxiliary
+ * clock source, then you will need to use one of the entries from the subsequent tables.
+ *
+ * **Main Clock Sources**
+ *
+ * Source | Reference Clock | System Clock
+ * -------|-----------------|---------
+ * ROSC      | CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH     |  |
+ * Auxiliary | CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX
+ * XOSC      | CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC        |  |
+ * Reference |                                                  | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF
+ *
+ * **Auxiliary Clock Sources**
+ *
+ * The auxiliary clock sources available for use in the configure function depend on which clock is being configured. The following table
+ * describes the available values that can be used. Note that for clk_gpout[x], x can be 0-3.
+ *
+ *
+ * Aux Source | clk_gpout[x] | clk_ref | clk_sys
+ * -----------|------------|---------|--------
+ * System PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS |                                                | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS
+ * GPIO in 0  | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0  | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0
+ * GPIO in 1  | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1  | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1
+ * USB PLL    | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB| CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB
+ * ROSC       | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_ROSC_CLKSRC    |                                                | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC
+ * XOSC       | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    |                                                | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC
+ * System clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_SYS      | | |
+ * USB Clock  | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_USB        | | |
+ * ADC clock  | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_ADC        | | |
+ * RTC Clock  | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_RTC        | | |
+ * Ref clock  | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_REF        | | |
+ *
+ * Aux Source |  clk_peri | clk_usb | clk_adc
+ * -----------|-----------|---------|--------
+ * System PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS    | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS
+ * GPIO in 0  | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0      | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0
+ * GPIO in 1  | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1      | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1
+ * USB PLL    | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB    | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB
+ * ROSC       | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH    | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH
+ * XOSC       | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC       | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC
+ * System clock | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS         | | |
+ *
+ * Aux Source | clk_rtc
+ * -----------|----------
+ * System PLL |  CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS
+ * GPIO in 0  |  CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0
+ * GPIO in 1  |  CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1
+ * USB PLL    |  CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB
+ * ROSC       |  CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH
+ * XOSC       |  CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC
+
+ *
+ * \section clock_example Example
+ * \addtogroup hardware_clocks
+ * \include hello_48MHz.c
+ */
+
+#define KHZ 1000
+#define MHZ 1000000
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_CLOCKS, Enable/disable assertions in the clocks module, type=bool, default=0, group=hardware_clocks
+#ifndef PARAM_ASSERTIONS_ENABLED_CLOCKS
+#define PARAM_ASSERTIONS_ENABLED_CLOCKS 0
+#endif
+
+/*! \brief Initialise the clock hardware
+ *  \ingroup hardware_clocks
+ *
+ *  Must be called before any other clock function.
+ */
+void clocks_init(void);
+
+/*! \brief Configure the specified clock
+ *  \ingroup hardware_clocks
+ *
+ * See the tables in the description for details on the possible values for clock sources.
+ *
+ * \param clk_index The clock to configure
+ * \param src The main clock source, can be 0.
+ * \param auxsrc The auxiliary clock source, which depends on which clock is being set. Can be 0
+ * \param src_freq Frequency of the input clock source
+ * \param freq Requested frequency
+ */
+bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq);
+
+/*! \brief Stop the specified clock
+ *  \ingroup hardware_clocks
+ *
+ * \param clk_index The clock to stop
+ */
+void clock_stop(enum clock_index clk_index);
+
+/*! \brief Get the current frequency of the specified clock
+ *  \ingroup hardware_clocks
+ *
+ * \param clk_index Clock
+ * \return Clock frequency in Hz
+ */
+uint32_t clock_get_hz(enum clock_index clk_index);
+
+/*! \brief Measure a clocks frequency using the Frequency counter.
+ *  \ingroup hardware_clocks
+ *
+ * Uses the inbuilt frequency counter to measure the specified clocks frequency.
+ * Currently, this function is accurate to +-1KHz. See the datasheet for more details.
+ */
+uint32_t frequency_count_khz(uint src);
+
+/*! \brief Set the "current frequency" of the clock as reported by clock_get_hz without actually changing the clock
+ *  \ingroup hardware_clocks
+ *
+ * \see clock_get_hz()
+ */
+void clock_set_reported_hz(enum clock_index clk_index, uint hz);
+
+/// \tag::frequency_count_mhz[]
+static inline float frequency_count_mhz(uint src) {
+    return ((float) (frequency_count_khz(src))) / KHZ;
+}
+/// \end::frequency_count_mhz[]
+
+/*! \brief Resus callback function type.
+ *  \ingroup hardware_clocks
+ *
+ * User provided callback for a resus event (when clk_sys is stopped by the programmer and is restarted for them).
+ */
+typedef void (*resus_callback_t)(void);
+
+/*! \brief Enable the resus function. Restarts clk_sys if it is accidentally stopped.
+ *  \ingroup hardware_clocks
+ *
+ * The resuscitate function will restart the system clock if it falls below a certain speed (or stops). This
+ * could happen if the clock source the system clock is running from stops. For example if a PLL is stopped.
+ *
+ * \param resus_callback a function pointer provided by the user to call if a resus event happens.
+ */
+void clocks_enable_resus(resus_callback_t resus_callback);
+
+/*! \brief Output an optionally divided clock to the specified gpio pin.
+ *  \ingroup hardware_clocks
+ *
+ * \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators.
+ * \param src  The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
+ * \param div  The amount to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock.
+ */
+void clock_gpio_init(uint gpio, uint src, uint div);
+
+/*! \brief Configure a clock to come from a gpio input
+ *  \ingroup hardware_clocks
+ *
+ * \param clk_index The clock to configure
+ * \param gpio The GPIO pin to run the clock from. Valid GPIOs are: 20 and 22.
+ * \param src_freq Frequency of the input clock source
+ * \param freq Requested frequency
+ */
+bool clock_configure_gpin(enum clock_index clk_index, uint gpio, uint32_t src_freq, uint32_t freq);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_clocks/scripts/vcocalc.py b/src/rp2_common/hardware_clocks/scripts/vcocalc.py
new file mode 100755
index 0000000..4d90146
--- /dev/null
+++ b/src/rp2_common/hardware_clocks/scripts/vcocalc.py
@@ -0,0 +1,37 @@
+#!/usr/bin/env python3
+
+import argparse
+
+parser = argparse.ArgumentParser(description="PLL parameter calculator")
+parser.add_argument("--input", "-i", default=12, help="Input (reference) frequency. Default 12 MHz", type=float)
+parser.add_argument("--vco-max", default=1600, help="Override maximum VCO frequency. Default 1600 MHz", type=float)
+parser.add_argument("--vco-min", default=400, help="Override minimum VCO frequency. Default 400 MHz", type=float)
+parser.add_argument("--low-vco", "-l", action="store_true", help="Use a lower VCO frequency when possible. This reduces power consumption, at the cost of increased jitter")
+parser.add_argument("output", help="Output frequency in MHz.", type=float)
+args = parser.parse_args()
+
+# Fixed hardware parameters
+fbdiv_range = range(16, 320 + 1)
+postdiv_range = range(1, 7 + 1)
+
+best = (0, 0, 0, 0)
+best_margin = args.output
+
+for fbdiv in (fbdiv_range if args.low_vco else reversed(fbdiv_range)):
+	vco = args.input * fbdiv
+	if vco < args.vco_min or vco > args.vco_max:
+		continue
+	# pd1 is inner loop so that we prefer higher ratios of pd1:pd2
+	for pd2 in postdiv_range:
+		for pd1 in postdiv_range:
+			out = vco / pd1 / pd2
+			margin = abs(out - args.output)
+			if margin < best_margin:
+				best = (out, fbdiv, pd1, pd2)
+				best_margin = margin
+
+print("Requested: {} MHz".format(args.output))
+print("Achieved: {} MHz".format(best[0]))
+print("FBDIV: {} (VCO = {} MHz)".format(best[1], args.input * best[1]))
+print("PD1: {}".format(best[2]))
+print("PD2: {}".format(best[3]))
diff --git a/src/rp2_common/hardware_divider/CMakeLists.txt b/src/rp2_common/hardware_divider/CMakeLists.txt
new file mode 100644
index 0000000..296a1ef
--- /dev/null
+++ b/src/rp2_common/hardware_divider/CMakeLists.txt
@@ -0,0 +1,3 @@
+pico_simple_hardware_headers_only_target(divider)
+target_sources(hardware_divider INTERFACE ${CMAKE_CURRENT_LIST_DIR}/divider.S)
+target_link_libraries(hardware_divider INTERFACE hardware_structs)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_divider/divider.S b/src/rp2_common/hardware_divider/divider.S
new file mode 100644
index 0000000..b9389c5
--- /dev/null
+++ b/src/rp2_common/hardware_divider/divider.S
@@ -0,0 +1,76 @@
+#include "pico/asm_helper.S"
+#include "hardware/regs/addressmap.h"
+#include "hardware/regs/sio.h"
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+// tag::hw_div_s32[]
+
+.macro __divider_delay
+    // delay 8 cycles
+    b 1f
+1:  b 1f
+1:  b 1f
+1:  b 1f
+1:
+.endm
+
+.align 2
+
+regular_func_with_section hw_divider_divmod_s32
+    ldr r3, =(SIO_BASE)
+    str r0, [r3, #SIO_DIV_SDIVIDEND_OFFSET]
+    str r1, [r3, #SIO_DIV_SDIVISOR_OFFSET]
+    __divider_delay
+    // return 64 bit value so we can efficiently return both (note quotient must be read last)
+    ldr r1, [r3, #SIO_DIV_REMAINDER_OFFSET]
+    ldr r0, [r3, #SIO_DIV_QUOTIENT_OFFSET]
+    bx lr
+// end::hw_div_s32[]
+
+.align 2
+
+// tag::hw_div_u32[]
+regular_func_with_section hw_divider_divmod_u32
+    ldr r3, =(SIO_BASE)
+    str r0, [r3, #SIO_DIV_UDIVIDEND_OFFSET]
+    str r1, [r3, #SIO_DIV_UDIVISOR_OFFSET]
+    __divider_delay
+    // return 64 bit value so we can efficiently return both (note quotient must be read last)
+    ldr r1, [r3, #SIO_DIV_REMAINDER_OFFSET]
+    ldr r0, [r3, #SIO_DIV_QUOTIENT_OFFSET]
+    bx lr
+// end::hw_div_u32[]
+
+#if SIO_DIV_CSR_READY_LSB == 0
+.equ SIO_DIV_CSR_READY_SHIFT_FOR_CARRY, 1
+#else
+#error need to change SHIFT above
+#endif
+
+regular_func_with_section hw_divider_save_state
+    push {r4, r5, lr}
+    ldr r5, =SIO_BASE
+    ldr r4, [r5, #SIO_DIV_CSR_OFFSET]
+    # wait for results as we can't save signed-ness of operation
+1:
+    lsrs r4, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY
+    bcc 1b
+    ldr r1, [r5, #SIO_DIV_UDIVIDEND_OFFSET]
+    ldr r2, [r5, #SIO_DIV_UDIVISOR_OFFSET]
+    ldr r3, [r5, #SIO_DIV_REMAINDER_OFFSET]
+    ldr r4, [r5, #SIO_DIV_QUOTIENT_OFFSET]
+    stmia r0!, {r1-r4}
+    pop {r4, r5, pc}
+
+regular_func_with_section hw_divider_restore_state
+    push {r4, r5, lr}
+    ldr r5, =SIO_BASE
+    ldmia r0!, {r1-r4}
+    str r1, [r5, #SIO_DIV_UDIVIDEND_OFFSET]
+    str r2, [r5, #SIO_DIV_UDIVISOR_OFFSET]
+    str r3, [r5, #SIO_DIV_REMAINDER_OFFSET]
+    str r4, [r5, #SIO_DIV_QUOTIENT_OFFSET]
+    pop {r4, r5, pc}
diff --git a/src/rp2_common/hardware_divider/include/hardware/divider.h b/src/rp2_common/hardware_divider/include/hardware/divider.h
new file mode 100644
index 0000000..0be2ef8
--- /dev/null
+++ b/src/rp2_common/hardware_divider/include/hardware/divider.h
@@ -0,0 +1,403 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_DIVIDER_H
+#define _HARDWARE_DIVIDER_H
+
+#include "pico.h"
+#include "hardware/structs/sio.h"
+
+/** \file hardware/divider.h
+ *  \defgroup hardware_divider hardware_divider
+ *
+ * Low-level hardware-divider access
+ *
+ * The SIO contains an 8-cycle signed/unsigned divide/modulo circuit, per core. Calculation is started by writing a dividend
+ * and divisor to the two argument registers, DIVIDEND and DIVISOR. The divider calculates the quotient / and remainder % of
+ * this division over the next 8 cycles, and on the 9th cycle the results can be read from the two result registers
+ * DIV_QUOTIENT and DIV_REMAINDER. A 'ready' bit in register DIV_CSR can be polled to wait for the calculation to
+ * complete, or software can insert a fixed 8-cycle delay
+ *
+ * This header provides low level macros and inline functions for accessing the hardware dividers directly,
+ * and perhaps most usefully performing asynchronous divides. These functions however do not follow the regular
+ * SDK conventions for saving/restoring the divider state, so are not generally safe to call from interrupt handlers
+ *
+ * The pico_divider library provides a more user friendly set of APIs over the divider (and support for
+ * 64 bit divides), and of course by default regular C language integer divisions are redirected through that library, meaning
+ * you can just use C level `/` and `%` operators and gain the benefits of the fast hardware divider.
+ *
+ * @see pico_divider
+ *
+ * \subsection divider_example Example
+ * \addtogroup hardware_divider
+ * \include hello_divider.c
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef uint64_t divmod_result_t;
+
+/*! \brief Start a signed asynchronous divide
+ *  \ingroup hardware_divider
+ *
+ * Start a divide of the specified signed parameters. You should wait for 8 cycles (__div_pause()) or wait for the ready bit to be set
+ * (hw_divider_wait_ready()) prior to reading the results.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ */
+static inline void hw_divider_divmod_s32_start(int32_t a, int32_t b) {
+    check_hw_layout( sio_hw_t, div_sdividend, SIO_DIV_SDIVIDEND_OFFSET);
+    sio_hw->div_sdividend = (uint32_t)a;
+    sio_hw->div_sdivisor = (uint32_t)b;
+}
+
+/*! \brief Start an unsigned asynchronous divide
+ *  \ingroup hardware_divider
+ *
+ * Start a divide of the specified unsigned parameters. You should wait for 8 cycles (__div_pause()) or wait for the ready bit to be set
+ * (hw_divider_wait_ready()) prior to reading the results.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ */
+static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) {
+    check_hw_layout(
+            sio_hw_t, div_udividend, SIO_DIV_UDIVIDEND_OFFSET);
+    sio_hw->div_udividend = a;
+    sio_hw->div_udivisor = b;
+}
+
+/*! \brief Wait for a divide to complete
+ *  \ingroup hardware_divider
+ *
+ * Wait for a divide to complete
+ */
+static inline void hw_divider_wait_ready(void) {
+    // this is #1 in lsr below
+    static_assert(SIO_DIV_CSR_READY_BITS == 1, "");
+
+    // we use one less register and instruction than gcc which uses a TST instruction
+
+    uint32_t tmp; // allow compiler to pick scratch register
+    asm volatile (
+    "hw_divider_result_loop_%=:"
+    "ldr %0, [%1, %2]\n\t"
+    "lsr %0, #1\n\t"
+    "bcc hw_divider_result_loop_%=\n\t"
+    : "=&l" (tmp)
+    : "l" (sio_hw), "I" (SIO_DIV_CSR_OFFSET)
+    :
+    );
+}
+
+/*! \brief Return result of HW divide, nowait
+ *  \ingroup hardware_divider
+ *
+ * \note This is UNSAFE in that the calculation may not have been completed.
+ *
+ * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient.
+ */
+static inline divmod_result_t hw_divider_result_nowait(void) {
+    // as ugly as this looks it is actually quite efficient
+    divmod_result_t rc = (((divmod_result_t) sio_hw->div_remainder) << 32u) | sio_hw->div_quotient;
+    return rc;
+}
+
+/*! \brief Return result of last asynchronous HW divide
+ *  \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient.
+ */
+static inline divmod_result_t hw_divider_result_wait(void) {
+    hw_divider_wait_ready();
+    return hw_divider_result_nowait();
+}
+
+/*! \brief Return result of last asynchronous HW divide, unsigned quotient only
+ *  \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current unsigned quotient result.
+ */
+static inline uint32_t hw_divider_u32_quotient_wait(void) {
+    hw_divider_wait_ready();
+    return sio_hw->div_quotient;
+}
+
+/*! \brief Return result of last asynchronous HW divide, signed quotient only
+ *  \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current signed quotient result.
+ */
+static inline int32_t hw_divider_s32_quotient_wait(void) {
+    hw_divider_wait_ready();
+    return (int32_t)sio_hw->div_quotient;
+}
+
+/*! \brief Return result of last asynchronous HW divide, unsigned remainder only
+ *  \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current unsigned remainder result.
+ */
+static inline uint32_t hw_divider_u32_remainder_wait(void) {
+    hw_divider_wait_ready();
+    uint32_t rc = sio_hw->div_remainder;
+    sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
+    return rc;
+}
+
+/*! \brief Return result of last asynchronous HW divide, signed remainder only
+ *  \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current remainder results.
+ */
+static inline int32_t hw_divider_s32_remainder_wait(void) {
+    hw_divider_wait_ready();
+    int32_t rc = (int32_t)sio_hw->div_remainder;
+    sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
+    return rc;
+}
+
+/*! \brief Do a signed HW divide and wait for result
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return result as a fixed point 32p32 value.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Results of divide as a 32p32 fixed point value.
+ */
+divmod_result_t hw_divider_divmod_s32(int32_t a, int32_t b);
+
+/*! \brief Do an unsigned HW divide and wait for result
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return result as a fixed point 32p32 value.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Results of divide as a 32p32 fixed point value.
+ */
+divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b);
+
+/*! \brief Efficient extraction of unsigned quotient from 32p32 fixed point
+ *  \ingroup hardware_divider
+ *
+ * \param r 32p32 fixed point value.
+ * \return Unsigned quotient
+ */
+inline static uint32_t to_quotient_u32(divmod_result_t r) {
+    return (uint32_t) r;
+}
+
+/*! \brief Efficient extraction of signed quotient from 32p32 fixed point
+ *  \ingroup hardware_divider
+ *
+ * \param r 32p32 fixed point value.
+ * \return Unsigned quotient
+ */
+inline static int32_t to_quotient_s32(divmod_result_t r) {
+    return (int32_t)(uint32_t)r;
+}
+
+/*! \brief Efficient extraction of unsigned remainder from 32p32 fixed point
+ *  \ingroup hardware_divider
+ *
+ * \param r 32p32 fixed point value.
+ * \return Unsigned remainder
+ *
+ * \note On Arm this is just a 32 bit register move or a nop
+ */
+inline static uint32_t to_remainder_u32(divmod_result_t r) {
+    return (uint32_t)(r >> 32u);
+}
+
+/*! \brief Efficient extraction of signed remainder from 32p32 fixed point
+ *  \ingroup hardware_divider
+ *
+ * \param r 32p32 fixed point value.
+ * \return Signed remainder
+ *
+ * \note On arm this is just a 32 bit register move or a nop
+ */
+inline static int32_t to_remainder_s32(divmod_result_t r) {
+    return (int32_t)(r >> 32u);
+}
+
+/*! \brief Do an unsigned HW divide, wait for result, return quotient
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return quotient.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Quotient results of the divide
+ */
+static inline uint32_t hw_divider_u32_quotient(uint32_t a, uint32_t b) {
+    return to_quotient_u32(hw_divider_divmod_u32(a, b));
+}
+
+/*! \brief Do an unsigned HW divide, wait for result, return remainder
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return remainder.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Remainder results of the divide
+ */
+static inline uint32_t hw_divider_u32_remainder(uint32_t a, uint32_t b) {
+    return to_remainder_u32(hw_divider_divmod_u32(a, b));
+}
+
+/*! \brief Do a signed HW divide, wait for result, return quotient
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return quotient.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Quotient results of the divide
+ */
+static inline int32_t hw_divider_quotient_s32(int32_t a, int32_t b) {
+    return to_quotient_s32(hw_divider_divmod_s32(a, b));
+}
+
+/*! \brief Do a signed HW divide, wait for result, return remainder
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return remainder.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Remainder results of the divide
+ */
+static inline int32_t hw_divider_remainder_s32(int32_t a, int32_t b) {
+    return to_remainder_s32(hw_divider_divmod_s32(a, b));
+}
+
+/*! \brief Pause for exact amount of time needed for a asynchronous divide to complete
+ *  \ingroup hardware_divider
+ */
+static inline void hw_divider_pause(void) {
+    asm volatile (
+    "b _1_%=\n"
+    "_1_%=:\n"
+    "b _2_%=\n"
+    "_2_%=:\n"
+    "b _3_%=\n"
+    "_3_%=:\n"
+    "b _4_%=\n"
+    "_4_%=:\n"
+    :: : );
+}
+
+/*! \brief Do a hardware unsigned HW divide, wait for result, return quotient
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return quotient.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Quotient result of the divide
+ */
+static inline uint32_t hw_divider_u32_quotient_inlined(uint32_t a, uint32_t b) {
+    hw_divider_divmod_u32_start(a, b);
+    hw_divider_pause();
+    return sio_hw->div_quotient;
+}
+
+/*! \brief Do a hardware unsigned HW divide, wait for result, return remainder
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return remainder.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Remainder result of the divide
+ */
+static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b) {
+    hw_divider_divmod_u32_start(a, b);
+    hw_divider_pause();
+    uint32_t rc = sio_hw->div_remainder;
+    sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
+    return rc;
+}
+
+/*! \brief Do a hardware signed HW divide, wait for result, return quotient
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return quotient.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Quotient result of the divide
+ */
+static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) {
+    hw_divider_divmod_s32_start(a, b);
+    hw_divider_pause();
+    return (int32_t)sio_hw->div_quotient;
+}
+
+/*! \brief Do a hardware signed HW divide, wait for result, return remainder
+ *  \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return remainder.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Remainder result of the divide
+ */
+static inline int32_t hw_divider_s32_remainder_inlined(int32_t a, int32_t b) {
+    hw_divider_divmod_s32_start(a, b);
+    hw_divider_pause();
+    int32_t rc = (int32_t)sio_hw->div_remainder;
+    sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
+    return rc;
+}
+
+typedef struct {
+    uint32_t values[4];
+} hw_divider_state_t;
+
+/*! \brief Save the calling cores hardware divider state
+ *  \ingroup hardware_divider
+ *
+ * Copy the current core's hardware divider state into the provided structure. This method
+ * waits for the divider results to be stable, then copies them to memory.
+ * They can be restored via hw_divider_restore_state()
+ *
+ * \param dest the location to store the divider state
+ */
+void hw_divider_save_state(hw_divider_state_t *dest);
+
+/*! \brief Load a saved hardware divider state into the current core's hardware divider
+ *  \ingroup hardware_divider
+ *
+ * Copy the passed hardware divider state into the hardware divider.
+ *
+ * \param src the location to load the divider state from
+ */
+
+void hw_divider_restore_state(hw_divider_state_t *src);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HARDWARE_DIVIDER_H
diff --git a/src/rp2_common/hardware_divider/include/hardware/divider_helper.S b/src/rp2_common/hardware_divider/include/hardware/divider_helper.S
new file mode 100644
index 0000000..062e12d
--- /dev/null
+++ b/src/rp2_common/hardware_divider/include/hardware/divider_helper.S
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/regs/addressmap.h"
+#include "hardware/regs/sio.h"
+
+#if SIO_DIV_CSR_READY_LSB == 0
+.equ SIO_DIV_CSR_READY_SHIFT_FOR_CARRY, 1
+#else
+need to change SHIFT above
+#endif
+#if SIO_DIV_CSR_DIRTY_LSB == 1
+.equ SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY, 2
+#else
+need to change SHIFT above
+#endif
+
+// SIO_BASE ptr in r2; pushes r4-r7, lr to stack
+// requires that division started at least 2 cycles prior to the start of the macro
+.macro save_div_state_and_lr
+// originally we did this, however a) it uses r3, and b) the push takes 6 cycles, b)
+// any IRQ which uses the divider will necessarily put the data back, which will
+// immediately make it ready
+//
+//    // ldr r3, [r2, #SIO_DIV_CSR_OFFSET]
+//    // // wait for results as we can't save signed-ness of operation
+//    // 1:
+//    //     lsrs r3, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY
+//    //     bcc 1b
+
+// 6 cycles
+push {r4, r5, r6, r7, lr}
+// note we must read quotient last, and since it isn't the last reg, we'll not use ldmia!
+ldr r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET]
+ldr r5, [r2, #SIO_DIV_UDIVISOR_OFFSET]
+ldr r7, [r2, #SIO_DIV_REMAINDER_OFFSET]
+ldr r6, [r2, #SIO_DIV_QUOTIENT_OFFSET]
+.endm
+
+// restores divider state from r4-r7, then pops them and pc
+.macro restore_div_state_and_return
+// writing sdividend (r4), sdivisor (r5), quotient (r6), remainder (r7) in that order
+//
+// it is worth considering what happens if we are interrupted
+//
+// after writing r4: we are DIRTY and !READY
+//    ... interruptor using div will complete based on incorrect inputs, but dividend at least will be
+//        saved/restored correctly and we'll restore the rest ourselves
+// after writing r4, r5: we are DIRTY and !READY
+//    ... interruptor using div will complete based on possibly wrongly signed inputs, but dividend, divisor
+//        at least will be saved/restored correctly and and we'll restore the rest ourselves
+// after writing r4, r5, r6: we are DIRTY and READY
+//    ... interruptor using div will dividend, divisor, quotient registers as is (what we just restored ourselves),
+//        and we'll restore the remainder after the fact
+
+// note we are not use STM not because it can be restarted due to interrupt which is harmless, more because this is 1 cycle IO space
+//      and so 4 reads is cheaper (and we don't have to adjust r2)
+// note also, that we must restore via UDIVI* rather than SDIVI* to prevent the quotient/remainder being negated on read based
+//      on the signs of the inputs
+str r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET]
+str r5, [r2, #SIO_DIV_UDIVISOR_OFFSET]
+str r7, [r2, #SIO_DIV_REMAINDER_OFFSET]
+str r6, [r2, #SIO_DIV_QUOTIENT_OFFSET]
+pop {r4, r5, r6, r7, pc}
+.endm
\ No newline at end of file
diff --git a/src/rp2_common/hardware_dma/CMakeLists.txt b/src/rp2_common/hardware_dma/CMakeLists.txt
new file mode 100644
index 0000000..fe08541
--- /dev/null
+++ b/src/rp2_common/hardware_dma/CMakeLists.txt
@@ -0,0 +1,2 @@
+pico_simple_hardware_target(dma)
+target_link_libraries(hardware_dma INTERFACE hardware_claim)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_dma/dma.c b/src/rp2_common/hardware_dma/dma.c
new file mode 100644
index 0000000..90fde06
--- /dev/null
+++ b/src/rp2_common/hardware_dma/dma.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include "hardware/dma.h"
+#include "hardware/claim.h"
+
+#define DMA_CHAN_STRIDE (DMA_CH1_CTRL_TRIG_OFFSET - DMA_CH0_CTRL_TRIG_OFFSET)
+check_hw_size(dma_channel_hw_t, DMA_CHAN_STRIDE);
+check_hw_layout(dma_hw_t, abort, DMA_CHAN_ABORT_OFFSET);
+
+// sanity check
+static_assert(__builtin_offsetof(dma_hw_t, ch[0].ctrl_trig) == DMA_CH0_CTRL_TRIG_OFFSET, "hw mismatch");
+static_assert(__builtin_offsetof(dma_hw_t, ch[1].ctrl_trig) == DMA_CH1_CTRL_TRIG_OFFSET, "hw mismatch");
+
+static_assert(NUM_DMA_CHANNELS <= 16, "");
+static uint16_t _claimed;
+static uint8_t _timer_claimed;
+
+void dma_channel_claim(uint channel) {
+    check_dma_channel_param(channel);
+    hw_claim_or_assert((uint8_t *) &_claimed, channel, "DMA channel %d is already claimed");
+}
+
+void dma_claim_mask(uint32_t mask) {
+    for(uint i = 0; mask; i++, mask >>= 1u) {
+        if (mask & 1u) dma_channel_claim(i);
+    }
+}
+
+void dma_channel_unclaim(uint channel) {
+    check_dma_channel_param(channel);
+    hw_claim_clear((uint8_t *) &_claimed, channel);
+}
+
+int dma_claim_unused_channel(bool required) {
+    return hw_claim_unused_from_range((uint8_t*)&_claimed, required, 0, NUM_DMA_CHANNELS-1, "No DMA channels are available");
+}
+
+bool dma_channel_is_claimed(uint channel) {
+    check_dma_channel_param(channel);
+    return hw_is_claimed((uint8_t *) &_claimed, channel);
+}
+
+void dma_timer_claim(uint timer) {
+    check_dma_timer_param(timer);
+    hw_claim_or_assert(&_timer_claimed, timer, "DMA timer %d is already claimed");
+}
+
+void dma_timer_unclaim(uint timer) {
+    check_dma_timer_param(timer);
+    hw_claim_clear(&_timer_claimed, timer);
+}
+
+int dma_claim_unused_timer(bool required) {
+    return hw_claim_unused_from_range(&_timer_claimed, required, 0, NUM_DMA_TIMERS-1, "No DMA timers are available");
+}
+
+bool dma_timer_is_claimed(uint timer) {
+    check_dma_timer_param(timer);
+    return hw_is_claimed(&_timer_claimed, timer);
+}
+
+#ifndef NDEBUG
+
+void print_dma_ctrl(dma_channel_hw_t *channel) {
+    uint32_t ctrl = channel->ctrl_trig;
+    int rgsz = (ctrl & DMA_CH0_CTRL_TRIG_RING_SIZE_BITS) >> DMA_CH0_CTRL_TRIG_RING_SIZE_LSB;
+    printf("(%08x) ber %d rer %d wer %d busy %d trq %d cto %d rgsl %d rgsz %d inw %d inr %d sz %d hip %d en %d",
+           (uint) ctrl,
+           ctrl & DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS ? 1 : 0,
+           ctrl & DMA_CH0_CTRL_TRIG_READ_ERROR_BITS ? 1 : 0,
+           ctrl & DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS ? 1 : 0,
+           ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS ? 1 : 0,
+           (int) ((ctrl & DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) >> DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB),
+           (int) ((ctrl & DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) >> DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB),
+           ctrl & DMA_CH0_CTRL_TRIG_RING_SEL_BITS ? 1 : 0,
+           rgsz ? (1 << rgsz) : 0,
+           ctrl & DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS ? 1 : 0,
+           ctrl & DMA_CH0_CTRL_TRIG_INCR_READ_BITS ? 1 : 0,
+           1 << ((ctrl & DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) >> DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB),
+           ctrl & DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS ? 1 : 0,
+           ctrl & DMA_CH0_CTRL_TRIG_EN_BITS ? 1 : 0);
+}
+#endif
+
+#if PARAM_ASSERTIONS_ENABLED(DMA)
+void check_dma_channel_param_impl(uint __unused channel) {
+    valid_params_if(DMA, channel < NUM_DMA_CHANNELS);
+}
+#endif
diff --git a/src/rp2_common/hardware_dma/include/hardware/dma.h b/src/rp2_common/hardware_dma/include/hardware/dma.h
new file mode 100644
index 0000000..7c9406f
--- /dev/null
+++ b/src/rp2_common/hardware_dma/include/hardware/dma.h
@@ -0,0 +1,795 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_DMA_H_
+#define _HARDWARE_DMA_H_
+
+#include "pico.h"
+#include "hardware/structs/dma.h"
+#include "hardware/regs/dreq.h"
+#include "pico/assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file hardware/dma.h
+ *  \defgroup hardware_dma hardware_dma
+ *
+ * DMA Controller API
+ *
+ * The RP2040 Direct Memory Access (DMA) master performs bulk data transfers on a processor’s
+ * behalf. This leaves processors free to attend to other tasks, or enter low-power sleep states. The
+ * data throughput of the DMA is also significantly higher than one of RP2040’s processors.
+ *
+ * The DMA can perform one read access and one write access, up to 32 bits in size, every clock cycle.
+ * There are 12 independent channels, which each supervise a sequence of bus transfers, usually in
+ * one of the following scenarios:
+ *
+ * * Memory to peripheral
+ * * Peripheral to memory
+ * * Memory to memory
+ */
+
+// these are not defined in generated dreq.h
+#define DREQ_DMA_TIMER0 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0
+#define DREQ_DMA_TIMER1 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1
+#define DREQ_DMA_TIMER2 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2
+#define DREQ_DMA_TIMER3 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3
+#define DREQ_FORCE      DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_DMA, Enable/disable DMA assertions, type=bool, default=0, group=hardware_dma
+#ifndef PARAM_ASSERTIONS_ENABLED_DMA
+#define PARAM_ASSERTIONS_ENABLED_DMA 0
+#endif
+
+static inline void check_dma_channel_param(__unused uint channel) {
+#if PARAM_ASSERTIONS_ENABLED(DMA)
+    // this method is used a lot by inline functions so avoid code bloat by deferring to function
+    extern void check_dma_channel_param_impl(uint channel);
+    check_dma_channel_param_impl(channel);
+#endif
+}
+
+static inline void check_dma_timer_param(__unused uint timer_num) {
+    valid_params_if(DMA, timer_num < NUM_DMA_TIMERS);
+}
+
+inline static dma_channel_hw_t *dma_channel_hw_addr(uint channel) {
+    check_dma_channel_param(channel);
+    return &dma_hw->ch[channel];
+}
+
+/*! \brief Mark a dma channel as used
+ *  \ingroup hardware_dma
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if the channel
+ * is already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param channel the dma channel
+ */
+void dma_channel_claim(uint channel);
+
+/*! \brief Mark multiple dma channels as used
+ *  \ingroup hardware_dma
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if any of the channels
+ * are already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param channel_mask Bitfield of all required channels to claim (bit 0 == channel 0, bit 1 == channel 1 etc)
+ */
+void dma_claim_mask(uint32_t channel_mask);
+
+/*! \brief Mark a dma channel as no longer used
+ *  \ingroup hardware_dma
+ *
+ * Method for cooperative claiming of hardware.
+ *
+ * \param channel the dma channel to release
+ */
+void dma_channel_unclaim(uint channel);
+
+/*! \brief Claim a free dma channel
+ *  \ingroup hardware_dma
+ *
+ * \param required if true the function will panic if none are available
+ * \return the dma channel number or -1 if required was false, and none were free
+ */
+int dma_claim_unused_channel(bool required);
+
+/*! \brief Determine if a dma channel is claimed
+ *  \ingroup hardware_dma
+ *
+ * \param channel the dma channel
+ * \return true if the channel is claimed, false otherwise
+ * \see dma_channel_claim
+ * \see dma_channel_claim_mask
+ */
+bool dma_channel_is_claimed(uint channel);
+
+/** \brief DMA channel configuration
+ *  \defgroup channel_config channel_config
+ *  \ingroup hardware_dma
+ *
+ * A DMA channel needs to be configured, these functions provide handy helpers to set up configuration
+ * structures. See \ref dma_channel_config
+ *
+ */
+
+/*! \brief Enumeration of available DMA channel transfer sizes.
+ *  \ingroup hardware_dma
+ *
+ * Names indicate the number of bits.
+ */
+enum dma_channel_transfer_size {
+    DMA_SIZE_8 = 0,    ///< Byte transfer (8 bits)
+    DMA_SIZE_16 = 1,   ///< Half word transfer (16 bits)
+    DMA_SIZE_32 = 2    ///< Word transfer (32 bits)
+};
+
+typedef struct {
+    uint32_t ctrl;
+} dma_channel_config;
+
+/*! \brief  Set DMA channel read increment
+ *  \ingroup channel_config
+ *
+ * \param c Pointer to channel configuration data
+ * \param incr True to enable read address increments, if false, each read will be from the same address
+ *             Usually disabled for peripheral to memory transfers
+ */
+static inline void channel_config_set_read_increment(dma_channel_config *c, bool incr) {
+    c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_READ_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR_READ_BITS);
+}
+
+/*! \brief  Set DMA channel write increment
+ *  \ingroup channel_config
+ *
+ * \param c Pointer to channel configuration data
+ * \param incr True to enable write address increments, if false, each write will be to the same address
+ *             Usually disabled for memory to peripheral transfers
+ * Usually disabled for memory to peripheral transfers
+ */
+static inline void channel_config_set_write_increment(dma_channel_config *c, bool incr) {
+    c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS);
+}
+
+/*! \brief  Select a transfer request signal
+ *  \ingroup channel_config
+ *
+ * The channel uses the transfer request signal to pace its data transfer rate.
+ * Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
+ * 0x0 to 0x3a -> select DREQ n as TREQ
+ * 0x3b -> Select Timer 0 as TREQ
+ * 0x3c -> Select Timer 1 as TREQ
+ * 0x3d -> Select Timer 2 as TREQ (Optional)
+ * 0x3e -> Select Timer 3 as TREQ (Optional)
+ * 0x3f -> Permanent request, for unpaced transfers.
+ *
+ * \param c Pointer to channel configuration data
+ * \param dreq Source (see description)
+ */
+static inline void channel_config_set_dreq(dma_channel_config *c, uint dreq) {
+    assert(dreq <= DREQ_FORCE);
+    c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) | (dreq << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB);
+}
+
+/*! \brief  Set DMA channel completion channel
+ *  \ingroup channel_config
+ *
+ * When this channel completes, it will trigger the channel indicated by chain_to. Disable by
+ * setting chain_to to itself (the same channel)
+ *
+ * \param c Pointer to channel configuration data
+ * \param chain_to Channel to trigger when this channel completes.
+ */
+static inline void channel_config_set_chain_to(dma_channel_config *c, uint chain_to) {
+    assert(chain_to <= NUM_DMA_CHANNELS);
+    c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) | (chain_to << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB);
+}
+
+/*! \brief Set the size of each DMA bus transfer
+ *  \ingroup channel_config
+ *
+ * Set the size of each bus transfer (byte/halfword/word). The read and write addresses
+ * advance by the specific amount (1/2/4 bytes) with each transfer.
+ *
+ * \param c Pointer to channel configuration data
+ * \param size See enum for possible values.
+ */
+static inline void channel_config_set_transfer_data_size(dma_channel_config *c, enum dma_channel_transfer_size size) {
+    assert(size == DMA_SIZE_8 || size == DMA_SIZE_16 || size == DMA_SIZE_32);
+    c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (((uint)size) << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB);
+}
+
+/*! \brief  Set address wrapping parameters
+ *  \ingroup channel_config
+ *
+ * Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address
+ * will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned
+ * ring buffers.
+ * Ring sizes between 2 and 32768 bytes are possible (size_bits from 1 - 15)
+ *
+ * 0x0 -> No wrapping.
+ *
+ * \param c Pointer to channel configuration data
+ * \param write True to apply to write addresses, false to apply to read addresses
+ * \param size_bits 0 to disable wrapping. Otherwise the size in bits of the changing part of the address.
+ *        Effectively wraps the address on a (1 << size_bits) byte boundary.
+ */
+static inline void channel_config_set_ring(dma_channel_config *c, bool write, uint size_bits) {
+    assert(size_bits < 32);
+    c->ctrl = (c->ctrl & ~(DMA_CH0_CTRL_TRIG_RING_SIZE_BITS | DMA_CH0_CTRL_TRIG_RING_SEL_BITS)) |
+              (size_bits << DMA_CH0_CTRL_TRIG_RING_SIZE_LSB) |
+              (write ? DMA_CH0_CTRL_TRIG_RING_SEL_BITS : 0);
+}
+
+/*! \brief  Set DMA byte swapping
+ *  \ingroup channel_config
+ *
+ * No effect for byte data, for halfword data, the two bytes of each halfword are
+ * swapped. For word data, the four bytes of each word are swapped to reverse their order.
+ *
+ * \param c Pointer to channel configuration data
+ * \param bswap True to enable byte swapping
+ */
+static inline void channel_config_set_bswap(dma_channel_config *c, bool bswap) {
+    c->ctrl = bswap ? (c->ctrl | DMA_CH0_CTRL_TRIG_BSWAP_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_BSWAP_BITS);
+}
+
+/*! \brief  Set IRQ quiet mode
+ *  \ingroup channel_config
+ *
+ * In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead,
+ * an IRQ is raised when NULL is written to a trigger register, indicating the end of a control
+ * block chain.
+ *
+ * \param c Pointer to channel configuration data
+ * \param irq_quiet True to enable quiet mode, false to disable.
+ */
+static inline void channel_config_set_irq_quiet(dma_channel_config *c, bool irq_quiet) {
+    c->ctrl = irq_quiet ? (c->ctrl | DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS);
+}
+
+/*!
+ *  \brief Enable/Disable the DMA channel
+ *  \ingroup channel_config
+ *
+ * When false, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will
+ * remain high if already high)
+ *
+ * \param c Pointer to channel configuration data
+ * \param enable True to enable the DMA channel. When enabled, the channel will respond to triggering events, and start transferring data.
+ *
+ */
+static inline void channel_config_set_enable(dma_channel_config *c, bool enable) {
+    c->ctrl = enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_EN_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_EN_BITS);
+}
+
+/*! \brief  Enable access to channel by sniff hardware.
+ *  \ingroup channel_config
+ *
+ * Sniff HW must be enabled and have this channel selected.
+ *
+ * \param c Pointer to channel configuration data
+ * \param sniff_enable True to enable the Sniff HW access to this DMA channel.
+ */
+static inline void channel_config_set_sniff_enable(dma_channel_config *c, bool sniff_enable) {
+    c->ctrl = sniff_enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS) : (c->ctrl &
+                                                                             ~DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS);
+}
+
+/*! \brief  Get the default channel configuration for a given channel
+ *  \ingroup channel_config
+ *
+ * Setting | Default
+ * --------|--------
+ * Read Increment | true
+ * Write Increment | false
+ * DReq | DREQ_FORCE
+ * Chain to | self
+ * Data size | DMA_SIZE_32
+ * Ring | write=false, size=0 (i.e. off)
+ * Byte Swap | false
+ * Quiet IRQs | false
+ * Channel Enable | true
+ * Sniff Enable | false
+ *
+ * \param channel DMA channel
+ * \return the default configuration which can then be modified.
+ */
+static inline dma_channel_config dma_channel_get_default_config(uint channel) {
+    dma_channel_config c = {0};
+    channel_config_set_read_increment(&c, true);
+    channel_config_set_write_increment(&c, false);
+    channel_config_set_dreq(&c, DREQ_FORCE);
+    channel_config_set_chain_to(&c, channel);
+    channel_config_set_transfer_data_size(&c, DMA_SIZE_32);
+    channel_config_set_ring(&c, false, 0);
+    channel_config_set_bswap(&c, false);
+    channel_config_set_irq_quiet(&c, false);
+    channel_config_set_enable(&c, true);
+    channel_config_set_sniff_enable(&c, false);
+    return c;
+}
+
+/*! \brief  Get the current configuration for the specified channel.
+ *  \ingroup channel_config
+ *
+ * \param channel DMA channel
+ * \return The current configuration as read from the HW register (not cached)
+ */
+static inline dma_channel_config dma_get_channel_config(uint channel) {
+    dma_channel_config c;
+    c.ctrl = dma_channel_hw_addr(channel)->ctrl_trig;
+    return c;
+}
+
+/*! \brief  Get the raw configuration register from a channel configuration
+ *  \ingroup channel_config
+ *
+ * \param config Pointer to a config structure.
+ * \return Register content
+ */
+static inline uint32_t channel_config_get_ctrl_value(const dma_channel_config *config) {
+    return config->ctrl;
+}
+
+/*! \brief  Set a channel configuration
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param config Pointer to a config structure with required configuration
+ * \param trigger True to trigger the transfer immediately
+ */
+static inline void dma_channel_set_config(uint channel, const dma_channel_config *config, bool trigger) {
+    // Don't use CTRL_TRIG since we don't want to start a transfer
+    if (!trigger) {
+        dma_channel_hw_addr(channel)->al1_ctrl = channel_config_get_ctrl_value(config);
+    } else {
+        dma_channel_hw_addr(channel)->ctrl_trig = channel_config_get_ctrl_value(config);
+    }
+}
+
+/*! \brief  Set the DMA initial read address.
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param read_addr Initial read address of transfer.
+ * \param trigger True to start the transfer immediately
+ */
+static inline void dma_channel_set_read_addr(uint channel, const volatile void *read_addr, bool trigger) {
+    if (!trigger) {
+        dma_channel_hw_addr(channel)->read_addr = (uintptr_t) read_addr;
+    } else {
+        dma_channel_hw_addr(channel)->al3_read_addr_trig = (uintptr_t) read_addr;
+    }
+}
+
+/*! \brief  Set the DMA initial write address
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param write_addr Initial write address of transfer.
+ * \param trigger True to start the transfer immediately
+ */
+static inline void dma_channel_set_write_addr(uint channel, volatile void *write_addr, bool trigger) {
+    if (!trigger) {
+        dma_channel_hw_addr(channel)->write_addr = (uintptr_t) write_addr;
+    } else {
+        dma_channel_hw_addr(channel)->al2_write_addr_trig = (uintptr_t) write_addr;
+    }
+}
+
+/*! \brief  Set the number of bus transfers the channel will do
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param trans_count The number of transfers (not NOT bytes, see channel_config_set_transfer_data_size)
+ * \param trigger True to start the transfer immediately
+ */
+static inline void dma_channel_set_trans_count(uint channel, uint32_t trans_count, bool trigger) {
+    if (!trigger) {
+        dma_channel_hw_addr(channel)->transfer_count = trans_count;
+    } else {
+        dma_channel_hw_addr(channel)->al1_transfer_count_trig = trans_count;
+    }
+}
+
+/*! \brief  Configure all DMA parameters and optionally start transfer
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param config Pointer to DMA config structure
+ * \param write_addr Initial write address
+ * \param read_addr Initial read address
+ * \param transfer_count Number of transfers to perform
+ * \param trigger True to start the transfer immediately
+ */
+static inline void dma_channel_configure(uint channel, const dma_channel_config *config, volatile void *write_addr,
+                                         const volatile void *read_addr,
+                                         uint transfer_count, bool trigger) {
+    dma_channel_set_read_addr(channel, read_addr, false);
+    dma_channel_set_write_addr(channel, write_addr, false);
+    dma_channel_set_trans_count(channel, transfer_count, false);
+    dma_channel_set_config(channel, config, trigger);
+}
+
+/*! \brief Start a DMA transfer from a buffer immediately
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param read_addr Sets the initial read address
+ * \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent.
+ */
+inline static void __attribute__((always_inline)) dma_channel_transfer_from_buffer_now(uint channel, 
+                                                                                       const volatile void *read_addr,
+                                                                                       uint32_t transfer_count) {
+//    check_dma_channel_param(channel);
+    dma_channel_hw_t *hw = dma_channel_hw_addr(channel);
+    hw->read_addr = (uintptr_t) read_addr;
+    hw->al1_transfer_count_trig = transfer_count;
+}
+
+/*! \brief Start a DMA transfer to a buffer immediately
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param write_addr Sets the initial write address
+ * \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent.
+ */
+inline static void dma_channel_transfer_to_buffer_now(uint channel, volatile void *write_addr, uint32_t transfer_count) {
+    dma_channel_hw_t *hw = dma_channel_hw_addr(channel);
+    hw->write_addr = (uintptr_t) write_addr;
+    hw->al1_transfer_count_trig = transfer_count;
+}
+
+/*! \brief  Start one or more channels simultaneously
+ *  \ingroup hardware_dma
+ *
+ * \param chan_mask Bitmask of all the channels requiring starting. Channel 0 = bit 0, channel 1 = bit 1 etc.
+ */
+static inline void dma_start_channel_mask(uint32_t chan_mask) {
+    valid_params_if(DMA, chan_mask && chan_mask < (1u << NUM_DMA_CHANNELS));
+    dma_hw->multi_channel_trigger = chan_mask;
+}
+
+/*! \brief  Start a single DMA channel
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ */
+static inline void dma_channel_start(uint channel) {
+    dma_start_channel_mask(1u << channel);
+}
+
+/*! \brief  Stop a DMA transfer
+ *  \ingroup hardware_dma
+ *
+ * Function will only return once the DMA has stopped.
+ *
+ * \param channel DMA channel
+ */
+static inline void dma_channel_abort(uint channel) {
+    check_dma_channel_param(channel);
+    dma_hw->abort = 1u << channel;
+    // Bit will go 0 once channel has reached safe state
+    // (i.e. any in-flight transfers have retired)
+    while (dma_hw->abort & (1ul << channel)) tight_loop_contents();
+}
+
+/*! \brief  Enable single DMA channel's interrupt via DMA_IRQ_0
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param enabled true to enable interrupt 0 on specified channel, false to disable.
+ */
+static inline void dma_channel_set_irq0_enabled(uint channel, bool enabled) {
+    check_dma_channel_param(channel);
+    check_hw_layout(dma_hw_t, inte0, DMA_INTE0_OFFSET);
+    if (enabled)
+        hw_set_bits(&dma_hw->inte0, 1u << channel);
+    else
+        hw_clear_bits(&dma_hw->inte0, 1u << channel);
+}
+
+/*! \brief  Enable multiple DMA channels' interrupts via DMA_IRQ_0
+ *  \ingroup hardware_dma
+ *
+ * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
+ * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask.
+ */
+static inline void dma_set_irq0_channel_mask_enabled(uint32_t channel_mask, bool enabled) {
+    if (enabled) {
+        hw_set_bits(&dma_hw->inte0, channel_mask);
+    } else {
+        hw_clear_bits(&dma_hw->inte0, channel_mask);
+    }
+}
+
+/*! \brief  Enable single DMA channel's interrupt via DMA_IRQ_1
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param enabled true to enable interrupt 1 on specified channel, false to disable.
+ */
+static inline void dma_channel_set_irq1_enabled(uint channel, bool enabled) {
+    check_dma_channel_param(channel);
+    check_hw_layout(dma_hw_t, inte1, DMA_INTE1_OFFSET);
+    if (enabled)
+        hw_set_bits(&dma_hw->inte1, 1u << channel);
+    else
+        hw_clear_bits(&dma_hw->inte1, 1u << channel);
+}
+
+/*! \brief  Enable multiple DMA channels' interrupts via DMA_IRQ_1
+ *  \ingroup hardware_dma
+ *
+ * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
+ * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask.
+ */
+static inline void dma_set_irq1_channel_mask_enabled(uint32_t channel_mask, bool enabled) {
+    if (enabled) {
+        hw_set_bits(&dma_hw->inte1, channel_mask);
+    } else {
+        hw_clear_bits(&dma_hw->inte1, channel_mask);
+    }
+}
+
+/*! \brief  Enable single DMA channel interrupt on either DMA_IRQ_0 or DMA_IRQ_1
+ *  \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel DMA channel
+ * \param enabled true to enable interrupt via irq_index for specified channel, false to disable.
+ */
+static inline void dma_irqn_set_channel_enabled(uint irq_index, uint channel, bool enabled) {
+    invalid_params_if(DMA, irq_index > 1);
+    if (irq_index) {
+        dma_channel_set_irq1_enabled(channel, enabled);
+    } else {
+        dma_channel_set_irq0_enabled(channel, enabled);
+    }
+}
+
+/*! \brief  Enable multiple DMA channels' interrupt via either DMA_IRQ_0 or DMA_IRQ_1
+ *  \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
+ * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask.
+ */
+static inline void dma_irqn_set_channel_mask_enabled(uint irq_index, uint32_t channel_mask,  bool enabled) {
+    invalid_params_if(DMA, irq_index > 1);
+    if (irq_index) {
+        dma_set_irq1_channel_mask_enabled(channel_mask, enabled);
+    } else {
+        dma_set_irq0_channel_mask_enabled(channel_mask, enabled);
+    }
+}
+
+/*! \brief  Determine if a particular channel is a cause of DMA_IRQ_0
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \return true if the channel is a cause of DMA_IRQ_0, false otherwise
+ */
+static inline bool dma_channel_get_irq0_status(uint channel) {
+    check_dma_channel_param(channel);
+    return dma_hw->ints0 & (1u << channel);
+}
+
+/*! \brief  Determine if a particular channel is a cause of DMA_IRQ_1
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \return true if the channel is a cause of DMA_IRQ_1, false otherwise
+ */
+static inline bool dma_channel_get_irq1_status(uint channel) {
+    check_dma_channel_param(channel);
+    return dma_hw->ints1 & (1u << channel);
+}
+
+/*! \brief  Determine if a particular channel is a cause of DMA_IRQ_N
+ *  \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel DMA channel
+ * \return true if the channel is a cause of the DMA_IRQ_N, false otherwise
+ */
+static inline bool dma_irqn_get_channel_status(uint irq_index, uint channel) {
+    invalid_params_if(DMA, irq_index > 1);
+    check_dma_channel_param(channel);
+    return (irq_index ? dma_hw->ints1 : dma_hw->ints0) & (1u << channel);
+}
+
+/*! \brief  Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_0
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ */
+static inline void dma_channel_acknowledge_irq0(uint channel) {
+    check_dma_channel_param(channel);
+    hw_set_bits(&dma_hw->ints0, (1u << channel));
+}
+
+/*! \brief  Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_1
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ */
+static inline void dma_channel_acknowledge_irq1(uint channel) {
+    check_dma_channel_param(channel);
+    hw_set_bits(&dma_hw->ints1, (1u << channel));
+}
+
+/*! \brief  Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_N
+ *  \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel DMA channel
+ */
+static inline void dma_irqn_acknowledge_channel(uint irq_index, uint channel) {
+    invalid_params_if(DMA, irq_index > 1);
+    check_dma_channel_param(channel);
+    hw_set_bits(irq_index ? &dma_hw->ints1 : &dma_hw->ints0, (1u << channel));
+}
+
+/*! \brief  Check if DMA channel is busy
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \return true if the channel is currently busy
+ */
+inline static bool dma_channel_is_busy(uint channel) {
+    check_dma_channel_param(channel);
+    return !!(dma_hw->ch[channel].al1_ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS);
+}
+
+/*! \brief  Wait for a DMA channel transfer to complete
+ *  \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ */
+inline static void dma_channel_wait_for_finish_blocking(uint channel) {
+    while (dma_channel_is_busy(channel)) tight_loop_contents();
+    // stop the compiler hoisting a non volatile buffer access above the DMA completion.
+    __compiler_memory_barrier();
+}
+
+/*! \brief Enable the DMA sniffing targeting the specified channel
+ *  \ingroup hardware_dma
+ *
+ * The mode can be one of the following:
+ *
+ * Mode | Function
+ * -----|---------
+ * 0x0 | Calculate a CRC-32 (IEEE802.3 polynomial)
+ * 0x1 | Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data
+ * 0x2 | Calculate a CRC-16-CCITT
+ * 0x3 | Calculate a CRC-16-CCITT with bit reversed data
+ * 0xe | XOR reduction over all data. == 1 if the total 1 population count is odd.
+ * 0xf | Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)
+ *
+ * \param channel DMA channel
+ * \param mode See description
+ * \param force_channel_enable Set true to also turn on sniffing in the channel configuration (this
+ * is usually what you want, but sometimes you might have a chain DMA with only certain segments
+ * of the chain sniffed, in which case you might pass false).
+ */
+inline static void dma_sniffer_enable(uint channel, uint mode, bool force_channel_enable) {
+    check_dma_channel_param(channel);
+    check_hw_layout(dma_hw_t, sniff_ctrl, DMA_SNIFF_CTRL_OFFSET);
+    if (force_channel_enable) {
+        hw_set_bits(&dma_hw->ch[channel].al1_ctrl, DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS);
+    }
+    dma_hw->sniff_ctrl = ((channel << DMA_SNIFF_CTRL_DMACH_LSB) & DMA_SNIFF_CTRL_DMACH_BITS) |
+                         ((mode << DMA_SNIFF_CTRL_CALC_LSB) & DMA_SNIFF_CTRL_CALC_BITS) |
+                         DMA_SNIFF_CTRL_EN_BITS;
+}
+
+/*! \brief Enable the Sniffer byte swap function
+ *  \ingroup hardware_dma
+ *
+ * Locally perform a byte reverse on the sniffed data, before feeding into checksum.
+ *
+ * Note that the sniff hardware is downstream of the DMA channel byteswap performed in the
+ * read master: if channel_config_set_bswap() and dma_sniffer_set_byte_swap_enabled() are both enabled,
+ * their effects cancel from the sniffer’s point of view.
+ *
+ * \param swap Set true to enable byte swapping
+ */
+inline static void dma_sniffer_set_byte_swap_enabled(bool swap) {
+    if (swap)
+        hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS);
+    else
+        hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS);
+}
+
+/*! \brief Disable the DMA sniffer
+ *  \ingroup hardware_dma
+ *
+ */
+inline static void dma_sniffer_disable(void) {
+    dma_hw->sniff_ctrl = 0;
+}
+
+/*! \brief Mark a dma timer as used
+ *  \ingroup hardware_dma
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if the timer
+ * is already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param timer the dma timer
+ */
+void dma_timer_claim(uint timer);
+
+/*! \brief Mark a dma timer as no longer used
+ *  \ingroup hardware_dma
+ *
+ * Method for cooperative claiming of hardware.
+ *
+ * \param timer the dma timer to release
+ */
+void dma_timer_unclaim(uint timer);
+
+/*! \brief Claim a free dma timer
+ *  \ingroup hardware_dma
+ *
+ * \param required if true the function will panic if none are available
+ * \return the dma timer number or -1 if required was false, and none were free
+ */
+int dma_claim_unused_timer(bool required);
+
+/*! \brief Determine if a dma timer is claimed
+ *  \ingroup hardware_dma
+ *
+ * \param timer the dma timer
+ * \return true if the timer is claimed, false otherwise
+ * \see dma_timer_claim
+ */
+bool dma_timer_is_claimed(uint timer);
+
+/*! \brief Set the divider for the given DMA timer
+ *  \ingroup hardware_dma
+ *
+ * The timer will run at the system_clock_freq * numerator / denominator, so this is the speed
+ * that data elements will be transferred at via a DMA channel using this timer as a DREQ
+ *
+ * \param timer the dma timer
+ * \param numerator the fraction's numerator
+ * \param denominator the fraction's denominator
+ */
+static inline void dma_timer_set_fraction(uint timer, uint16_t numerator, uint16_t denominator) {
+    check_dma_timer_param(timer);
+    dma_hw->timer[timer] = (((uint32_t)numerator) << DMA_TIMER0_X_LSB) | (((uint32_t)denominator) << DMA_TIMER0_Y_LSB);
+}
+
+/*! \brief Return the DREQ number for a given DMA timer
+ *  \ingroup hardware_dma
+ *
+ * \param timer_num DMA timer number 0-3
+ */
+static inline uint dma_get_timer_dreq(uint timer_num) {
+    static_assert(DREQ_DMA_TIMER1 == DREQ_DMA_TIMER0 + 1, "");
+    static_assert(DREQ_DMA_TIMER2 == DREQ_DMA_TIMER0 + 2, "");
+    static_assert(DREQ_DMA_TIMER3 == DREQ_DMA_TIMER0 + 3, "");
+    check_dma_timer_param(timer_num);
+    return DREQ_DMA_TIMER0 + timer_num;
+}
+
+#ifndef NDEBUG
+void print_dma_ctrl(dma_channel_hw_t *channel);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_exception/CMakeLists.txt b/src/rp2_common/hardware_exception/CMakeLists.txt
new file mode 100644
index 0000000..a994dc0
--- /dev/null
+++ b/src/rp2_common/hardware_exception/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(exception)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_exception/exception.c b/src/rp2_common/hardware_exception/exception.c
new file mode 100644
index 0000000..8a9a108
--- /dev/null
+++ b/src/rp2_common/hardware_exception/exception.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/exception.h"
+#include "hardware/regs/m0plus.h"
+#include "hardware/platform_defs.h"
+#include "hardware/structs/scb.h"
+
+#include "pico/mutex.h"
+#include "pico/assert.h"
+
+#ifndef exception_is_compile_time_default
+static bool exception_is_compile_time_default(exception_handler_t handler) {
+    extern char __default_isrs_start;
+    extern char __default_isrs_end;
+    return ((uintptr_t)handler) >= (uintptr_t)&__default_isrs_start &&
+            ((uintptr_t)handler) < (uintptr_t)&__default_isrs_end;
+}
+#endif
+
+static inline exception_handler_t *get_vtable(void) {
+    return (exception_handler_t *) scb_hw->vtor;
+}
+
+static void set_raw_exception_handler_and_restore_interrupts(enum exception_number num, exception_handler_t handler, uint32_t save) {
+    // update vtable (vtable_handler may be same or updated depending on cases, but we do it anyway for compactness)
+    get_vtable()[16 + num] = handler;
+    __dmb();
+    restore_interrupts(save);
+}
+
+static inline void check_exception_param(__unused enum exception_number num) {
+    invalid_params_if(EXCEPTION, num < NMI_EXCEPTION || num >=0);
+}
+
+exception_handler_t exception_get_vtable_handler(enum exception_number num) {
+    check_exception_param(num);
+    return get_vtable()[16 + num];
+}
+
+exception_handler_t exception_set_exclusive_handler(enum exception_number num, exception_handler_t handler) {
+    check_exception_param(num);
+#if !PICO_NO_RAM_VECTOR_TABLE
+    uint32_t save = save_and_disable_interrupts();
+    exception_handler_t current = exception_get_vtable_handler(num);
+    hard_assert(handler == current || exception_is_compile_time_default(current));
+    set_raw_exception_handler_and_restore_interrupts(num, handler, save);
+#else
+    panic_unsupported();
+#endif
+    return current;
+}
+
+void exception_restore_handler(enum exception_number num, exception_handler_t original_handler) {
+    hard_assert(exception_is_compile_time_default(original_handler));
+#if !PICO_NO_RAM_VECTOR_TABLE
+    uint32_t save = save_and_disable_interrupts();
+    set_raw_exception_handler_and_restore_interrupts(num, original_handler, save);
+#else
+    panic_unsupported();
+#endif
+}
\ No newline at end of file
diff --git a/src/rp2_common/hardware_exception/include/hardware/exception.h b/src/rp2_common/hardware_exception/include/hardware/exception.h
new file mode 100644
index 0000000..005168b
--- /dev/null
+++ b/src/rp2_common/hardware_exception/include/hardware/exception.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_EXCEPTION_H_
+#define _HARDWARE_EXCEPTION_H_
+
+#include "pico.h"
+#include "hardware/address_mapped.h"
+#include "hardware/regs/m0plus.h"
+
+/** \file exception.h
+ *  \defgroup hardware_exception hardware_exception
+ *
+ * Methods for setting processor exception handlers
+ *
+ * Exceptions are identified by a \ref exception_number which is a number from -15 to -1; these are the numbers relative to
+ * the index of the first IRQ vector in the vector table. (i.e. vector table index is exception_num plus 16)
+ *
+ * There is one set of exception handlers per core, so the exception handlers for each core as set by these methods are independent.
+ *
+ * \note That all exception APIs affect the executing core only (i.e. the core calling the function).
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_EXCEPTION, Enable/disable assertions in the exception module, type=bool, default=0, group=hardware_exception
+#ifndef PARAM_ASSERTIONS_ENABLED_EXCEPTION
+#define PARAM_ASSERTIONS_ENABLED_EXCEPTION 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief  Exception number definitions
+ *
+ * Note for consistency with irq numbers, these numbers are defined to be negative. The VTABLE index is
+ * the number here plus 16.
+ *
+ * Name                 | Value | Exception
+ * ---------------------|-------|----------
+ * NMI_EXCEPTION        |  -14  | Non Maskable Interrupt
+ * HARDFAULT_EXCEPTION  |  -13  | HardFault
+ * SVCALL_EXCEPTION     |   -5  | SV Call
+ * PENDSV_EXCEPTION     |   -2  | Pend SV
+ * SYSTICK_EXCEPTION    |   -1  | System Tick
+ *
+ * \ingroup hardware_exception
+ */
+enum exception_number {
+    NMI_EXCEPTION        = -14,     /* Non Maskable Interrupt */
+    HARDFAULT_EXCEPTION  = -13,     /* HardFault Interrupt */
+    SVCALL_EXCEPTION     =  -5,     /* SV Call Interrupt */
+    PENDSV_EXCEPTION     =  -2,     /* Pend SV Interrupt */
+    SYSTICK_EXCEPTION    =  -1,     /* System Tick Interrupt */
+};
+
+/*! \brief Exception handler function type
+ *  \ingroup hardware_exception
+ *
+ * All exception handlers should be of this type, and follow normal ARM EABI register saving conventions
+ */
+typedef void (*exception_handler_t)(void);
+
+/*! \brief  Set the exception handler for an exception on the executing core.
+ *  \ingroup hardware_exception
+ *
+ * This method will assert if an exception handler has been set for this exception number on this core via
+ * this method, without an intervening restore via exception_restore_handler.
+ *
+ * \note this method may not be used to override an exception handler that was specified at link time by
+ * providing a strong replacement for the weakly defined stub exception handlers. It will assert in this case too.
+ *
+ * \param num Exception number
+ * \param handler The handler to set
+ * \see exception_number
+ */
+exception_handler_t exception_set_exclusive_handler(enum exception_number num, exception_handler_t handler);
+
+/*! \brief Restore the original exception handler for an exception on this core
+ *  \ingroup hardware_exception
+ *
+ * This method may be used to restore the exception handler for an exception on this core to the state
+ * prior to the call to exception_set_exclusive_handler(), so that exception_set_exclusive_handler()
+ * may be called again in the future.
+ *
+ * \param num Exception number \ref exception_number
+ * \param original_handler The original handler returned from \ref exception_set_exclusive_handler
+ * \see exception_set_exclusive_handler()
+ */
+void exception_restore_handler(enum exception_number num, exception_handler_t original_handler);
+
+/*! \brief Get the current exception handler for the specified exception from the currently installed vector table
+ * of the execution core
+ *  \ingroup hardware_exception
+ *
+ * \param num Exception number
+ * \return the address stored in the VTABLE for the given exception number
+ */
+exception_handler_t exception_get_vtable_handler(enum exception_number num);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_flash/CMakeLists.txt b/src/rp2_common/hardware_flash/CMakeLists.txt
new file mode 100644
index 0000000..9682566
--- /dev/null
+++ b/src/rp2_common/hardware_flash/CMakeLists.txt
@@ -0,0 +1,2 @@
+pico_simple_hardware_target(flash)
+target_link_libraries(hardware_flash INTERFACE pico_bootrom)
diff --git a/src/rp2_common/hardware_flash/flash.c b/src/rp2_common/hardware_flash/flash.c
new file mode 100644
index 0000000..5699302
--- /dev/null
+++ b/src/rp2_common/hardware_flash/flash.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/flash.h"
+#include "pico/bootrom.h"
+
+#include "hardware/structs/ssi.h"
+#include "hardware/structs/ioqspi.h"
+
+#define FLASH_BLOCK_ERASE_CMD 0xd8
+
+// Standard RUID instruction: 4Bh command prefix, 32 dummy bits, 64 data bits.
+#define FLASH_RUID_CMD 0x4b
+#define FLASH_RUID_DUMMY_BYTES 4
+#define FLASH_RUID_DATA_BYTES 8
+#define FLASH_RUID_TOTAL_BYTES (1 + FLASH_RUID_DUMMY_BYTES + FLASH_RUID_DATA_BYTES)
+
+//-----------------------------------------------------------------------------
+// Infrastructure for reentering XIP mode after exiting for programming (take
+// a copy of boot2 before XIP exit). Calling boot2 as a function works because
+// it accepts a return vector in LR (and doesn't trash r4-r7). Bootrom passes
+// NULL in LR, instructing boot2 to enter flash vector table's reset handler.
+
+#if !PICO_NO_FLASH
+
+#define BOOT2_SIZE_WORDS 64
+
+static uint32_t boot2_copyout[BOOT2_SIZE_WORDS];
+static bool boot2_copyout_valid = false;
+
+static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) {
+    if (boot2_copyout_valid)
+        return;
+    for (int i = 0; i < BOOT2_SIZE_WORDS; ++i)
+        boot2_copyout[i] = ((uint32_t *)XIP_BASE)[i];
+    __compiler_memory_barrier();
+    boot2_copyout_valid = true;
+}
+
+static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) {
+    ((void (*)(void))boot2_copyout+1)();
+}
+
+#else
+
+static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) {}
+
+static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) {
+    // Set up XIP for 03h read on bus access (slow but generic)
+    rom_flash_enter_cmd_xip_fn flash_enter_cmd_xip = (rom_flash_enter_cmd_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_ENTER_CMD_XIP);
+    assert(flash_enter_cmd_xip);
+    flash_enter_cmd_xip();
+}
+
+#endif
+
+//-----------------------------------------------------------------------------
+// Actual flash programming shims (work whether or not PICO_NO_FLASH==1)
+
+void __no_inline_not_in_flash_func(flash_range_erase)(uint32_t flash_offs, size_t count) {
+#ifdef PICO_FLASH_SIZE_BYTES
+    hard_assert(flash_offs + count <= PICO_FLASH_SIZE_BYTES);
+#endif
+    invalid_params_if(FLASH, flash_offs & (FLASH_SECTOR_SIZE - 1));
+    invalid_params_if(FLASH, count & (FLASH_SECTOR_SIZE - 1));
+    rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
+    rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
+    rom_flash_range_erase_fn flash_range_erase = (rom_flash_range_erase_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_ERASE);
+    rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
+    assert(connect_internal_flash && flash_exit_xip && flash_range_erase && flash_flush_cache);
+    flash_init_boot2_copyout();
+
+    // No flash accesses after this point
+    __compiler_memory_barrier();
+
+    connect_internal_flash();
+    flash_exit_xip();
+    flash_range_erase(flash_offs, count, FLASH_BLOCK_SIZE, FLASH_BLOCK_ERASE_CMD);
+    flash_flush_cache(); // Note this is needed to remove CSn IO force as well as cache flushing
+    flash_enable_xip_via_boot2();
+}
+
+void __no_inline_not_in_flash_func(flash_range_program)(uint32_t flash_offs, const uint8_t *data, size_t count) {
+#ifdef PICO_FLASH_SIZE_BYTES
+    hard_assert(flash_offs + count <= PICO_FLASH_SIZE_BYTES);
+#endif
+    invalid_params_if(FLASH, flash_offs & (FLASH_PAGE_SIZE - 1));
+    invalid_params_if(FLASH, count & (FLASH_PAGE_SIZE - 1));
+    rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
+    rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
+    rom_flash_range_program_fn flash_range_program = (rom_flash_range_program_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_PROGRAM);
+    rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
+    assert(connect_internal_flash && flash_exit_xip && flash_range_program && flash_flush_cache);
+    flash_init_boot2_copyout();
+
+    __compiler_memory_barrier();
+
+    connect_internal_flash();
+    flash_exit_xip();
+    flash_range_program(flash_offs, data, count);
+    flash_flush_cache(); // Note this is needed to remove CSn IO force as well as cache flushing
+    flash_enable_xip_via_boot2();
+}
+
+//-----------------------------------------------------------------------------
+// Lower-level flash access functions
+
+#if !PICO_NO_FLASH
+// Bitbanging the chip select using IO overrides, in case RAM-resident IRQs
+// are still running, and the FIFO bottoms out. (the bootrom does the same)
+static void __no_inline_not_in_flash_func(flash_cs_force)(bool high) {
+    uint32_t field_val = high ?
+        IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH :
+        IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW;
+    hw_write_masked(&ioqspi_hw->io[1].ctrl,
+        field_val << IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB,
+        IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS
+    );
+}
+
+void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) {
+    rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
+    rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
+    rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
+    assert(connect_internal_flash && flash_exit_xip && flash_flush_cache);
+    flash_init_boot2_copyout();
+    __compiler_memory_barrier();
+    connect_internal_flash();
+    flash_exit_xip();
+
+    flash_cs_force(0);
+    size_t tx_remaining = count;
+    size_t rx_remaining = count;
+    // We may be interrupted -- don't want FIFO to overflow if we're distracted.
+    const size_t max_in_flight = 16 - 2;
+    while (tx_remaining || rx_remaining) {
+        uint32_t flags = ssi_hw->sr;
+        bool can_put = !!(flags & SSI_SR_TFNF_BITS);
+        bool can_get = !!(flags & SSI_SR_RFNE_BITS);
+        if (can_put && tx_remaining && rx_remaining - tx_remaining < max_in_flight) {
+            ssi_hw->dr0 = *txbuf++;
+            --tx_remaining;
+        }
+        if (can_get && rx_remaining) {
+            *rxbuf++ = (uint8_t)ssi_hw->dr0;
+            --rx_remaining;
+        }
+    }
+    flash_cs_force(1);
+
+    flash_flush_cache();
+    flash_enable_xip_via_boot2();
+}
+#endif
+
+// Use standard RUID command to get a unique identifier for the flash (and
+// hence the board)
+
+static_assert(FLASH_UNIQUE_ID_SIZE_BYTES == FLASH_RUID_DATA_BYTES, "");
+
+void flash_get_unique_id(uint8_t *id_out) {
+#if PICO_NO_FLASH
+    __unused uint8_t *ignore = id_out;
+    panic_unsupported();
+#else
+    uint8_t txbuf[FLASH_RUID_TOTAL_BYTES] = {0};
+    uint8_t rxbuf[FLASH_RUID_TOTAL_BYTES] = {0};
+    txbuf[0] = FLASH_RUID_CMD;
+    flash_do_cmd(txbuf, rxbuf, FLASH_RUID_TOTAL_BYTES);
+    for (int i = 0; i < FLASH_RUID_DATA_BYTES; i++)
+        id_out[i] = rxbuf[i + 1 + FLASH_RUID_DUMMY_BYTES];
+#endif
+}
diff --git a/src/rp2_common/hardware_flash/include/hardware/flash.h b/src/rp2_common/hardware_flash/include/hardware/flash.h
new file mode 100644
index 0000000..e6cd229
--- /dev/null
+++ b/src/rp2_common/hardware_flash/include/hardware/flash.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_FLASH_H
+#define _HARDWARE_FLASH_H
+
+#include "pico.h"
+
+/** \file flash.h
+ *  \defgroup hardware_flash hardware_flash
+ *
+ * Low level flash programming and erase API
+ *
+ * Note these functions are *unsafe* if you have two cores concurrently
+ * executing from flash. In this case you must perform your own
+ * synchronisation to make sure no XIP accesses take place during flash
+ * programming.
+ *
+ * Likewise they are *unsafe* if you have interrupt handlers or an interrupt
+ * vector table in flash, so you must disable interrupts before calling in
+ * this case.
+ *
+ * If PICO_NO_FLASH=1 is not defined (i.e. if the program is built to run from
+ * flash) then these functions will make a static copy of the second stage
+ * bootloader in SRAM, and use this to reenter execute-in-place mode after
+ * programming or erasing flash, so that they can safely be called from
+ * flash-resident code.
+ *
+ * \subsection flash_example Example
+ * \include flash_program.c
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_FLASH, Enable/disable assertions in the flash module, type=bool, default=0, group=hardware_flash
+#ifndef PARAM_ASSERTIONS_ENABLED_FLASH
+#define PARAM_ASSERTIONS_ENABLED_FLASH 0
+#endif
+
+#define FLASH_PAGE_SIZE (1u << 8)
+#define FLASH_SECTOR_SIZE (1u << 12)
+#define FLASH_BLOCK_SIZE (1u << 16)
+
+#define FLASH_UNIQUE_ID_SIZE_BYTES 8
+
+// PICO_CONFIG: PICO_FLASH_SIZE_BYTES, size of primary flash in bytes, type=int, group=hardware_flash
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief  Erase areas of flash
+ *  \ingroup hardware_flash
+ *
+ * \param flash_offs Offset into flash, in bytes, to start the erase. Must be aligned to a 4096-byte flash sector.
+ * \param count Number of bytes to be erased. Must be a multiple of 4096 bytes (one sector).
+ */
+void flash_range_erase(uint32_t flash_offs, size_t count);
+
+/*! \brief  Program flash
+ *  \ingroup hardware_flash
+ *
+ * \param flash_offs Flash address of the first byte to be programmed. Must be aligned to a 256-byte flash page.
+ * \param data Pointer to the data to program into flash
+ * \param count Number of bytes to program. Must be a multiple of 256 bytes (one page).
+ */
+
+void flash_range_program(uint32_t flash_offs, const uint8_t *data, size_t count);
+
+/*! \brief Get flash unique 64 bit identifier
+ *  \ingroup hardware_flash
+ *
+ * Use a standard 4Bh RUID instruction to retrieve the 64 bit unique
+ * identifier from a flash device attached to the QSPI interface. Since there
+ * is a 1:1 association between the MCU and this flash, this also serves as a
+ * unique identifier for the board.
+ *
+ *  \param id_out Pointer to an 8-byte buffer to which the ID will be written
+ */
+void flash_get_unique_id(uint8_t *id_out);
+
+/*! \brief Execute bidirectional flash command
+ *  \ingroup hardware_flash
+ *
+ * Low-level function to execute a serial command on a flash device attached
+ * to the QSPI interface. Bytes are simultaneously transmitted and received
+ * from txbuf and to rxbuf. Therefore, both buffers must be the same length,
+ * count, which is the length of the overall transaction. This is useful for
+ * reading metadata from the flash chip, such as device ID or SFDP
+ * parameters.
+ *
+ * The XIP cache is flushed following each command, in case flash state
+ * has been modified. Like other hardware_flash functions, the flash is not
+ * accessible for execute-in-place transfers whilst the command is in
+ * progress, so entering a flash-resident interrupt handler or executing flash
+ * code on the second core concurrently will be fatal. To avoid these pitfalls
+ * it is recommended that this function only be used to extract flash metadata
+ * during startup, before the main application begins to run: see the
+ * implementation of pico_get_unique_id() for an example of this.
+ *
+ *  \param txbuf Pointer to a byte buffer which will be transmitted to the flash
+ *  \param rxbuf Pointer to a byte buffer where data received from the flash will be written. txbuf and rxbuf may be the same buffer.
+ *  \param count Length in bytes of txbuf and of rxbuf
+ */
+void flash_do_cmd(const uint8_t *txbuf, uint8_t *rxbuf, size_t count);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_gpio/CMakeLists.txt b/src/rp2_common/hardware_gpio/CMakeLists.txt
new file mode 100644
index 0000000..1bfb078
--- /dev/null
+++ b/src/rp2_common/hardware_gpio/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(gpio)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_gpio/gpio.c b/src/rp2_common/hardware_gpio/gpio.c
new file mode 100644
index 0000000..2816b97
--- /dev/null
+++ b/src/rp2_common/hardware_gpio/gpio.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/gpio.h"
+#include "hardware/sync.h"
+
+#include "hardware/structs/iobank0.h"
+#include "hardware/irq.h"
+
+#if LIB_PICO_BINARY_INFO
+#include "pico/binary_info.h"
+#endif
+
+static gpio_irq_callback_t _callbacks[NUM_CORES];
+
+// Get the raw value from the pin, bypassing any muxing or overrides.
+int gpio_get_pad(uint gpio) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS);
+    return (iobank0_hw->io[gpio].status & IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS)
+            >> IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB;
+}
+
+/// \tag::gpio_set_function[]
+// Select function for this GPIO, and ensure input/output are enabled at the pad.
+// This also clears the input/output/irq override bits.
+void gpio_set_function(uint gpio, enum gpio_function fn) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    invalid_params_if(GPIO, ((uint32_t)fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB) & ~IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS);
+    // Set input enable on, output disable off
+    hw_write_masked(&padsbank0_hw->io[gpio],
+                   PADS_BANK0_GPIO0_IE_BITS,
+                   PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS
+    );
+    // Zero all fields apart from fsel; we want this IO to do what the peripheral tells it.
+    // This doesn't affect e.g. pullup/pulldown, as these are in pad controls.
+    iobank0_hw->io[gpio].ctrl = fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+}
+/// \end::gpio_set_function[]
+
+enum gpio_function gpio_get_function(uint gpio) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    return (enum gpio_function) ((iobank0_hw->io[gpio].ctrl & IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS) >> IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB);
+}
+
+// Note that, on RP2040, setting both pulls enables a "bus keep" function,
+// i.e. weak pull to whatever is current high/low state of GPIO.
+void gpio_set_pulls(uint gpio, bool up, bool down) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    hw_write_masked(
+            &padsbank0_hw->io[gpio],
+            (bool_to_bit(up) << PADS_BANK0_GPIO0_PUE_LSB) | (bool_to_bit(down) << PADS_BANK0_GPIO0_PDE_LSB),
+            PADS_BANK0_GPIO0_PUE_BITS | PADS_BANK0_GPIO0_PDE_BITS
+    );
+}
+
+// Direct override for per-GPIO IRQ signal
+void gpio_set_irqover(uint gpio, uint value) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    hw_write_masked(&iobank0_hw->io[gpio].ctrl,
+                   value << IO_BANK0_GPIO0_CTRL_IRQOVER_LSB,
+                   IO_BANK0_GPIO0_CTRL_IRQOVER_BITS
+    );
+}
+
+// Direct overrides for pad controls
+void gpio_set_inover(uint gpio, uint value) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    hw_write_masked(&iobank0_hw->io[gpio].ctrl,
+                   value << IO_BANK0_GPIO0_CTRL_INOVER_LSB,
+                   IO_BANK0_GPIO0_CTRL_INOVER_BITS
+    );
+}
+
+void gpio_set_outover(uint gpio, uint value) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    hw_write_masked(&iobank0_hw->io[gpio].ctrl,
+                   value << IO_BANK0_GPIO0_CTRL_OUTOVER_LSB,
+                   IO_BANK0_GPIO0_CTRL_OUTOVER_BITS
+    );
+}
+
+void gpio_set_oeover(uint gpio, uint value) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    hw_write_masked(&iobank0_hw->io[gpio].ctrl,
+                   value << IO_BANK0_GPIO0_CTRL_OEOVER_LSB,
+                   IO_BANK0_GPIO0_CTRL_OEOVER_BITS
+    );
+}
+
+void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    if (enabled)
+        hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS);
+    else
+        hw_clear_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS);
+}
+
+
+bool gpio_is_input_hysteresis_enabled(uint gpio) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_SCHMITT_BITS) != 0;
+}
+
+void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    hw_write_masked(&padsbank0_hw->io[gpio],
+                    (uint)slew << PADS_BANK0_GPIO0_SLEWFAST_LSB,
+                    PADS_BANK0_GPIO0_SLEWFAST_BITS
+    );
+}
+
+enum gpio_slew_rate gpio_get_slew_rate(uint gpio) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    return (enum gpio_slew_rate)((padsbank0_hw->io[gpio]
+            & PADS_BANK0_GPIO0_SLEWFAST_BITS)
+            >> PADS_BANK0_GPIO0_SLEWFAST_LSB);
+}
+
+
+// Enum encoding should match hardware encoding on RP2040
+static_assert(PADS_BANK0_GPIO0_DRIVE_VALUE_8MA == GPIO_DRIVE_STRENGTH_8MA, "");
+void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    hw_write_masked(&padsbank0_hw->io[gpio],
+                    (uint)drive << PADS_BANK0_GPIO0_DRIVE_LSB,
+                    PADS_BANK0_GPIO0_DRIVE_BITS
+    );
+}
+
+enum gpio_drive_strength gpio_get_drive_strength(uint gpio) {
+    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+    return (enum gpio_drive_strength)((padsbank0_hw->io[gpio]
+            & PADS_BANK0_GPIO0_DRIVE_BITS)
+            >> PADS_BANK0_GPIO0_DRIVE_LSB);
+}
+
+static void gpio_irq_handler(void) {
+    io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ?
+                                           &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
+    for (uint gpio = 0; gpio < NUM_BANK0_GPIOS; gpio++) {
+        io_ro_32 *status_reg = &irq_ctrl_base->ints[gpio / 8];
+        uint events = (*status_reg >> 4 * (gpio % 8)) & 0xf;
+        if (events) {
+            // TODO: If both cores care about this event then the second core won't get the irq?
+            gpio_acknowledge_irq(gpio, events);
+            gpio_irq_callback_t callback = _callbacks[get_core_num()];
+            if (callback) {
+                callback(gpio, events);
+            }
+        }
+    }
+}
+
+static void _gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled, io_irq_ctrl_hw_t *irq_ctrl_base) {
+    // Clear stale events which might cause immediate spurious handler entry
+    gpio_acknowledge_irq(gpio, events);
+
+    io_rw_32 *en_reg = &irq_ctrl_base->inte[gpio / 8];
+    events <<= 4 * (gpio % 8);
+
+    if (enabled)
+        hw_set_bits(en_reg, events);
+    else
+        hw_clear_bits(en_reg, events);
+}
+
+void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled) {
+    // Separate mask/force/status per-core, so check which core called, and
+    // set the relevant IRQ controls.
+    io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ?
+                                           &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
+    _gpio_set_irq_enabled(gpio, events, enabled, irq_ctrl_base);
+}
+
+void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t events, bool enabled, gpio_irq_callback_t callback) {
+    gpio_set_irq_enabled(gpio, events, enabled);
+
+    // TODO: Do we want to support a callback per GPIO pin?
+    // Install IRQ handler
+    _callbacks[get_core_num()] = callback;
+    irq_set_exclusive_handler(IO_IRQ_BANK0, gpio_irq_handler);
+    irq_set_enabled(IO_IRQ_BANK0, true);
+}
+
+void gpio_set_dormant_irq_enabled(uint gpio, uint32_t events, bool enabled) {
+    io_irq_ctrl_hw_t *irq_ctrl_base = &iobank0_hw->dormant_wake_irq_ctrl;
+    _gpio_set_irq_enabled(gpio, events, enabled, irq_ctrl_base);
+}
+
+void gpio_acknowledge_irq(uint gpio, uint32_t events) {
+    iobank0_hw->intr[gpio / 8] = events << 4 * (gpio % 8);
+}
+
+#define DEBUG_PIN_MASK (((1u << PICO_DEBUG_PIN_COUNT)-1) << PICO_DEBUG_PIN_BASE)
+void gpio_debug_pins_init() {
+    gpio_init_mask(DEBUG_PIN_MASK);
+    gpio_set_dir_masked(DEBUG_PIN_MASK, DEBUG_PIN_MASK);
+#if LIB_PICO_BINARY_INFO
+    bi_decl_if_func_used(bi_pin_mask_with_names(DEBUG_PIN_MASK, "Debug"));
+#endif
+}
+
+void gpio_set_input_enabled(uint gpio, bool enabled) {
+    if (enabled)
+        hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS);
+    else
+        hw_clear_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS);
+}
+
+void gpio_init(uint gpio) {
+    sio_hw->gpio_oe_clr = 1ul << gpio;
+    sio_hw->gpio_clr = 1ul << gpio;
+    gpio_set_function(gpio, GPIO_FUNC_SIO);
+}
+
+void gpio_init_mask(uint gpio_mask) {
+    for(uint i=0;i<32;i++) {
+        if (gpio_mask & 1) {
+            gpio_init(i);
+        }
+        gpio_mask >>= 1;
+    }
+}
+
diff --git a/src/rp2_common/hardware_gpio/include/hardware/gpio.h b/src/rp2_common/hardware_gpio/include/hardware/gpio.h
new file mode 100644
index 0000000..7037e85
--- /dev/null
+++ b/src/rp2_common/hardware_gpio/include/hardware/gpio.h
@@ -0,0 +1,656 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_GPIO_H_
+#define _HARDWARE_GPIO_H_
+
+#include "pico.h"
+#include "hardware/structs/sio.h"
+#include "hardware/structs/padsbank0.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_GPIO, Enable/disable assertions in the GPIO module, type=bool, default=0, group=hardware_gpio
+#ifndef PARAM_ASSERTIONS_ENABLED_GPIO
+#define PARAM_ASSERTIONS_ENABLED_GPIO 0
+#endif
+
+/** \file gpio.h
+ *  \defgroup hardware_gpio hardware_gpio
+ *
+ * General Purpose Input/Output (GPIO) API
+ *
+ * RP2040 has 36 multi-functional General Purpose Input / Output (GPIO) pins, divided into two banks. In a typical use case,
+ * the pins in the QSPI bank (QSPI_SS, QSPI_SCLK and QSPI_SD0 to QSPI_SD3) are used to execute code from an external
+ * flash device, leaving the User bank (GPIO0 to GPIO29) for the programmer to use. All GPIOs support digital input and
+ * output, but GPIO26 to GPIO29 can also be used as inputs to the chip’s Analogue to Digital Converter (ADC). Each GPIO
+ * can be controlled directly by software running on the processors, or by a number of other functional blocks.
+ *
+ * The function allocated to each GPIO is selected by calling the \ref gpio_set_function function. \note Not all functions
+ * are available on all pins.
+ *
+ * Each GPIO can have one function selected at a time. Likewise, each peripheral input (e.g. UART0 RX) should only be selected on
+ * one _GPIO_ at a time. If the same peripheral input is connected to multiple GPIOs, the peripheral sees the logical OR of these
+ * GPIO inputs. Please refer to the datasheet for more information on GPIO function select.
+ *
+ * ### Function Select Table
+ *
+ *  GPIO   | F1       | F2        | F3       | F4     | F5  | F6   | F7   | F8            | F9
+ *  -------|----------|-----------|----------|--------|-----|------|------|---------------|----
+ *  0      | SPI0 RX  | UART0 TX  | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 |               | USB OVCUR DET
+ *  1      | SPI0 CSn | UART0 RX  | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 |               | USB VBUS DET
+ *  2      | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 |               | USB VBUS EN
+ *  3      | SPI0 TX  | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 |               | USB OVCUR DET
+ *  4      | SPI0 RX  | UART1 TX  | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 |               | USB VBUS DET
+ *  5      | SPI0 CSn | UART1 RX  | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 |               | USB VBUS EN
+ *  6      | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 |               | USB OVCUR DET
+ *  7      | SPI0 TX  | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 |               | USB VBUS DET
+ *  8      | SPI1 RX  | UART1 TX  | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 |               | USB VBUS EN
+ *  9      | SPI1 CSn | UART1 RX  | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 |               | USB OVCUR DET
+ *  10     | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 |               | USB VBUS DET
+ *  11     | SPI1 TX  | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 |               | USB VBUS EN
+ *  12     | SPI1 RX  | UART0 TX  | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 |               | USB OVCUR DET
+ *  13     | SPI1 CSn | UART0 RX  | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 |               | USB VBUS DET
+ *  14     | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM7 A | SIO | PIO0 | PIO1 |               | USB VBUS EN
+ *  15     | SPI1 TX  | UART0 RTS | I2C1 SCL | PWM7 B | SIO | PIO0 | PIO1 |               | USB OVCUR DET
+ *  16     | SPI0 RX  | UART0 TX  | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 |               | USB VBUS DET
+ *  17     | SPI0 CSn | UART0 RX  | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 |               | USB VBUS EN
+ *  18     | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 |               | USB OVCUR DET
+ *  19     | SPI0 TX  | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 |               | USB VBUS DET
+ *  20     | SPI0 RX  | UART1 TX  | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | CLOCK GPIN0   | USB VBUS EN
+ *  21     | SPI0 CSn | UART1 RX  | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | CLOCK GPOUT0  | USB OVCUR DET
+ *  22     | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | CLOCK GPIN1   | USB VBUS DET
+ *  23     | SPI0 TX  | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | CLOCK GPOUT1  | USB VBUS EN
+ *  24     | SPI1 RX  | UART1 TX  | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | CLOCK GPOUT2  | USB OVCUR DET
+ *  25     | SPI1 CSn | UART1 RX  | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | CLOCK GPOUT3  | USB VBUS DET
+ *  26     | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 |               | USB VBUS EN
+ *  27     | SPI1 TX  | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 |               | USB OVCUR DET
+ *  28     | SPI1 RX  | UART0 TX  | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 |               | USB VBUS DET
+ *  29     | SPI1 CSn | UART0 RX  | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 |               | USB VBUS EN
+
+ */
+
+/*! \brief  GPIO function definitions for use with function select
+ *  \ingroup hardware_gpio
+ * \brief GPIO function selectors
+ *
+ * Each GPIO can have one function selected at a time. Likewise, each peripheral input (e.g. UART0 RX) should only be
+ * selected on one GPIO at a time. If the same peripheral input is connected to multiple GPIOs, the peripheral sees the logical
+ * OR of these GPIO inputs.
+ *
+ * Please refer to the datsheet for more information on GPIO function selection.
+ */
+enum gpio_function {
+    GPIO_FUNC_XIP = 0,
+    GPIO_FUNC_SPI = 1,
+    GPIO_FUNC_UART = 2,
+    GPIO_FUNC_I2C = 3,
+    GPIO_FUNC_PWM = 4,
+    GPIO_FUNC_SIO = 5,
+    GPIO_FUNC_PIO0 = 6,
+    GPIO_FUNC_PIO1 = 7,
+    GPIO_FUNC_GPCK = 8,
+    GPIO_FUNC_USB = 9,
+    GPIO_FUNC_NULL = 0x1f,
+};
+
+#define GPIO_OUT 1
+#define GPIO_IN 0
+
+/*! \brief  GPIO Interrupt level definitions
+ *  \ingroup hardware_gpio
+ *  \brief GPIO Interrupt levels
+ *
+ * An interrupt can be generated for every GPIO pin in 4 scenarios:
+ *
+ * * Level High: the GPIO pin is a logical 1
+ * * Level Low: the GPIO pin is a logical 0
+ * * Edge High: the GPIO has transitioned from a logical 0 to a logical 1
+ * * Edge Low: the GPIO has transitioned from a logical 1 to a logical 0
+ *
+ * The level interrupts are not latched. This means that if the pin is a logical 1 and the level high interrupt is active, it will
+ * become inactive as soon as the pin changes to a logical 0. The edge interrupts are stored in the INTR register and can be
+ * cleared by writing to the INTR register.
+ */
+enum gpio_irq_level {
+    GPIO_IRQ_LEVEL_LOW = 0x1u,
+    GPIO_IRQ_LEVEL_HIGH = 0x2u,
+    GPIO_IRQ_EDGE_FALL = 0x4u,
+    GPIO_IRQ_EDGE_RISE = 0x8u,
+};
+
+/*! Callback function type for GPIO events
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio Which GPIO caused this interrupt
+ * \param events Which events caused this interrupt. See \ref gpio_set_irq_enabled for details.
+ * \sa gpio_set_irq_enabled_with_callback()
+ */
+typedef void (*gpio_irq_callback_t)(uint gpio, uint32_t events);
+
+enum gpio_override {
+    GPIO_OVERRIDE_NORMAL = 0,      ///< peripheral signal selected via \ref gpio_set_function
+    GPIO_OVERRIDE_INVERT = 1,      ///< invert peripheral signal selected via \ref gpio_set_function
+    GPIO_OVERRIDE_LOW = 2,         ///< drive low/disable output
+    GPIO_OVERRIDE_HIGH = 3,        ///< drive high/enable output
+};
+
+/*! \brief Slew rate limiting levels for GPIO outputs
+ *  \ingroup hardware_gpio
+ *
+ * Slew rate limiting increases the minimum rise/fall time when a GPIO output
+ * is lightly loaded, which can help to reduce electromagnetic emissions.
+ * \sa gpio_set_slew_rate
+ */
+enum gpio_slew_rate {
+    GPIO_SLEW_RATE_SLOW = 0,  ///< Slew rate limiting enabled
+    GPIO_SLEW_RATE_FAST = 1   ///< Slew rate limiting disabled
+};
+
+/*! \brief Drive strength levels for GPIO outputs
+ *  \ingroup hardware_gpio
+ *
+ * Drive strength levels for GPIO outputs.
+ * \sa gpio_set_drive_strength
+ */
+enum gpio_drive_strength {
+    GPIO_DRIVE_STRENGTH_2MA = 0, ///< 2 mA nominal drive strength
+    GPIO_DRIVE_STRENGTH_4MA = 1, ///< 4 mA nominal drive strength
+    GPIO_DRIVE_STRENGTH_8MA = 2, ///< 8 mA nominal drive strength
+    GPIO_DRIVE_STRENGTH_12MA = 3 ///< 12 mA nominal drive strength
+};
+
+// ----------------------------------------------------------------------------
+// Pad Controls + IO Muxing
+// ----------------------------------------------------------------------------
+// Declarations for gpio.c
+
+/*! \brief Select GPIO function
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param fn Which GPIO function select to use from list \ref gpio_function
+ */
+void gpio_set_function(uint gpio, enum gpio_function fn);
+
+/*! \brief Determine current GPIO function
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \return Which GPIO function is currently selected from list \ref gpio_function
+ */
+enum gpio_function gpio_get_function(uint gpio);
+
+/*! \brief Select up and down pulls on specific GPIO
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param up If true set a pull up on the GPIO
+ * \param down If true set a pull down on the GPIO
+ *
+ * \note On the RP2040, setting both pulls enables a "bus keep" function,
+ * i.e. a weak pull to whatever is current high/low state of GPIO.
+ */
+void gpio_set_pulls(uint gpio, bool up, bool down);
+
+/*! \brief Set specified GPIO to be pulled up.
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ */
+static inline void gpio_pull_up(uint gpio) {
+    gpio_set_pulls(gpio, true, false);
+}
+
+/*! \brief Determine if the specified GPIO is pulled up.
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \return true if the GPIO is pulled up
+ */
+static inline bool gpio_is_pulled_up(uint gpio) {
+    return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_PUE_BITS) != 0;
+}
+
+/*! \brief Set specified GPIO to be pulled down.
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ */
+static inline void gpio_pull_down(uint gpio) {
+    gpio_set_pulls(gpio, false, true);
+}
+
+/*! \brief Determine if the specified GPIO is pulled down.
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \return true if the GPIO is pulled down
+ */
+static inline bool gpio_is_pulled_down(uint gpio) {
+    return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_PDE_BITS) != 0;
+}
+
+/*! \brief Disable pulls on specified GPIO
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ */
+static inline void gpio_disable_pulls(uint gpio) {
+    gpio_set_pulls(gpio, false, false);
+}
+
+/*! \brief Set GPIO IRQ override
+ *  \ingroup hardware_gpio
+ *
+ * Optionally invert a GPIO IRQ signal, or drive it high or low
+ *
+ * \param gpio GPIO number
+ * \param value See \ref gpio_override
+ */
+void gpio_set_irqover(uint gpio, uint value);
+
+/*! \brief Set GPIO output override
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param value See \ref gpio_override
+ */
+void gpio_set_outover(uint gpio, uint value);
+
+/*! \brief Select GPIO input override
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param value See \ref gpio_override
+ */
+void gpio_set_inover(uint gpio, uint value);
+
+/*! \brief Select GPIO output enable override
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param value See \ref gpio_override
+ */
+void gpio_set_oeover(uint gpio, uint value);
+
+/*! \brief Enable GPIO input
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param enabled true to enable input on specified GPIO
+ */
+void gpio_set_input_enabled(uint gpio, bool enabled);
+
+/*! \brief Enable/disable GPIO input hysteresis (Schmitt trigger)
+ *  \ingroup hardware_gpio
+ *
+ * Enable or disable the Schmitt trigger hysteresis on a given GPIO. This is
+ * enabled on all GPIOs by default. Disabling input hysteresis can lead to
+ * inconsistent readings when the input signal has very long rise or fall
+ * times, but slightly reduces the GPIO's input delay.
+ *
+ * \sa gpio_is_input_hysteresis_enabled
+ * \param gpio GPIO number
+ * \param enabled true to enable input hysteresis on specified GPIO
+ */
+void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled);
+
+/*! \brief Determine whether input hysteresis is enabled on a specified GPIO
+ *  \ingroup hardware_gpio
+ *
+ * \sa gpio_set_input_hysteresis_enabled
+ * \param gpio GPIO number
+ */
+bool gpio_is_input_hysteresis_enabled(uint gpio);
+
+
+/*! \brief Set slew rate for a specified GPIO
+ *  \ingroup hardware_gpio
+ *
+ * \sa gpio_get_slew_rate
+ * \param gpio GPIO number
+ * \param slew GPIO output slew rate
+ */
+void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew);
+
+/*! \brief Determine current slew rate for a specified GPIO
+ *  \ingroup hardware_gpio
+ *
+ * \sa gpio_set_slew_rate
+ * \param gpio GPIO number
+ * \return Current slew rate of that GPIO
+ */
+enum gpio_slew_rate gpio_get_slew_rate(uint gpio);
+
+/*! \brief Set drive strength for a specified GPIO
+ *  \ingroup hardware_gpio
+ *
+ * \sa gpio_get_drive_strength
+ * \param gpio GPIO number
+ * \param drive GPIO output drive strength
+ */
+void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive);
+
+/*! \brief Determine current slew rate for a specified GPIO
+ *  \ingroup hardware_gpio
+ *
+ * \sa gpio_set_drive_strength
+ * \param gpio GPIO number
+ * \return Current drive strength of that GPIO
+ */
+enum gpio_drive_strength gpio_get_drive_strength(uint gpio);
+
+/*! \brief Enable or disable interrupts for specified GPIO
+ *  \ingroup hardware_gpio
+ *
+ * \note The IO IRQs are independent per-processor. This configures IRQs for
+ * the processor that calls the function.
+ *
+ * \param gpio GPIO number
+ * \param events Which events will cause an interrupt
+ * \param enabled Enable or disable flag
+ *
+ * Events is a bitmask of the following:
+ *
+ * bit | interrupt
+ * ----|----------
+ *   0 | Low level
+ *   1 | High level
+ *   2 | Edge low
+ *   3 | Edge high
+ */
+void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled);
+
+/*! \brief Enable interrupts for specified GPIO
+ *  \ingroup hardware_gpio
+ *
+ * \note The IO IRQs are independent per-processor. This configures IRQs for
+ * the processor that calls the function.
+ *
+ * \param gpio GPIO number
+ * \param events Which events will cause an interrupt. See \ref gpio_set_irq_enabled for details.
+ * \param enabled Enable or disable flag
+ * \param callback user function to call on GPIO irq. Note only one of these can be set per processor.
+ *
+ * \note Currently the GPIO parameter is ignored, and this callback will be called for any enabled GPIO IRQ on any pin.
+ *
+ */
+void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t events, bool enabled, gpio_irq_callback_t callback);
+
+/*! \brief Enable dormant wake up interrupt for specified GPIO
+ *  \ingroup hardware_gpio
+ *
+ * This configures IRQs to restart the XOSC or ROSC when they are
+ * disabled in dormant mode
+ *
+ * \param gpio GPIO number
+ * \param events Which events will cause an interrupt. See \ref gpio_set_irq_enabled for details.
+ * \param enabled Enable/disable flag
+ */
+void gpio_set_dormant_irq_enabled(uint gpio, uint32_t events, bool enabled);
+
+/*! \brief Acknowledge a GPIO interrupt
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param events Bitmask of events to clear. See \ref gpio_set_irq_enabled for details.
+  *
+ */
+void gpio_acknowledge_irq(uint gpio, uint32_t events);
+
+/*! \brief Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO)
+ *  \ingroup hardware_gpio
+ *
+ * Clear the output enable (i.e. set to input).
+ * Clear any output value.
+ *
+ * \param gpio GPIO number
+ */
+void gpio_init(uint gpio);
+
+/*! \brief Initialise multiple GPIOs (enabled I/O and set func to GPIO_FUNC_SIO)
+ *  \ingroup hardware_gpio
+ *
+ * Clear the output enable (i.e. set to input).
+ * Clear any output value.
+ *
+ * \param gpio_mask Mask with 1 bit per GPIO number to initialize
+ */
+void gpio_init_mask(uint gpio_mask);
+// ----------------------------------------------------------------------------
+// Input
+// ----------------------------------------------------------------------------
+
+/*! \brief Get state of a single specified GPIO
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \return Current state of the GPIO. 0 for low, non-zero for high
+ */
+static inline bool gpio_get(uint gpio) {
+    return !!((1ul << gpio) & sio_hw->gpio_in);
+}
+
+/*! \brief Get raw value of all GPIOs
+ *  \ingroup hardware_gpio
+ *
+ * \return Bitmask of raw GPIO values, as bits 0-29
+ */
+static inline uint32_t gpio_get_all(void) {
+    return sio_hw->gpio_in;
+}
+
+// ----------------------------------------------------------------------------
+// Output
+// ----------------------------------------------------------------------------
+
+/*! \brief Drive high every GPIO appearing in mask
+ *  \ingroup hardware_gpio
+ *
+ * \param mask Bitmask of GPIO values to set, as bits 0-29
+ */
+static inline void gpio_set_mask(uint32_t mask) {
+    sio_hw->gpio_set = mask;
+}
+
+/*! \brief Drive low every GPIO appearing in mask
+ *  \ingroup hardware_gpio
+ *
+ * \param mask Bitmask of GPIO values to clear, as bits 0-29
+ */
+static inline void gpio_clr_mask(uint32_t mask) {
+    sio_hw->gpio_clr = mask;
+}
+
+/*! \brief Toggle every GPIO appearing in mask
+ *  \ingroup hardware_gpio
+ *
+ * \param mask Bitmask of GPIO values to toggle, as bits 0-29
+ */
+static inline void gpio_xor_mask(uint32_t mask) {
+    sio_hw->gpio_togl = mask;
+}
+
+/*! \brief Drive GPIO high/low depending on parameters
+ *  \ingroup hardware_gpio
+ *
+ * \param mask Bitmask of GPIO values to change, as bits 0-29
+ * \param value Value to set
+ *
+ * For each 1 bit in \p mask, drive that pin to the value given by
+ * corresponding bit in \p value, leaving other pins unchanged.
+ * Since this uses the TOGL alias, it is concurrency-safe with e.g. an IRQ
+ * bashing different pins from the same core.
+ */
+static inline void gpio_put_masked(uint32_t mask, uint32_t value) {
+    sio_hw->gpio_togl = (sio_hw->gpio_out ^ value) & mask;
+}
+
+/*! \brief Drive all pins simultaneously
+ *  \ingroup hardware_gpio
+ *
+ * \param value Bitmask of GPIO values to change, as bits 0-29
+ */
+static inline void gpio_put_all(uint32_t value) {
+    sio_hw->gpio_out = value;
+}
+
+/*! \brief Drive a single GPIO high/low
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param value If false clear the GPIO, otherwise set it.
+ */
+static inline void gpio_put(uint gpio, bool value) {
+    uint32_t mask = 1ul << gpio;
+    if (value)
+        gpio_set_mask(mask);
+    else
+        gpio_clr_mask(mask);
+}
+
+/*! \brief Determine whether a GPIO is currently driven high or low
+ *  \ingroup hardware_gpio
+ *
+ * This function returns the high/low output level most recently assigned to a
+ * GPIO via gpio_put() or similar. This is the value that is presented outward
+ * to the IO muxing, *not* the input level back from the pad (which can be
+ * read using gpio_get()).
+ *
+ * To avoid races, this function must not be used for read-modify-write
+ * sequences when driving GPIOs -- instead functions like gpio_put() should be
+ * used to atomically update GPIOs. This accessor is intended for debug use
+ * only.
+ *
+ * \param gpio GPIO number
+ * \return true if the GPIO output level is high, false if low.
+ */
+static inline bool gpio_get_out_level(uint gpio) {
+    return !!(sio_hw->gpio_out & (1u << gpio));
+}
+
+// ----------------------------------------------------------------------------
+// Direction
+// ----------------------------------------------------------------------------
+
+/*! \brief Set a number of GPIOs to output
+ *  \ingroup hardware_gpio
+ *
+ * Switch all GPIOs in "mask" to output
+ *
+ * \param mask Bitmask of GPIO to set to output, as bits 0-29
+ */
+static inline void gpio_set_dir_out_masked(uint32_t mask) {
+    sio_hw->gpio_oe_set = mask;
+}
+
+/*! \brief Set a number of GPIOs to input
+ *  \ingroup hardware_gpio
+ *
+ * \param mask Bitmask of GPIO to set to input, as bits 0-29
+ */
+static inline void gpio_set_dir_in_masked(uint32_t mask) {
+    sio_hw->gpio_oe_clr = mask;
+}
+
+/*! \brief Set multiple GPIO directions
+ *  \ingroup hardware_gpio
+ *
+ * \param mask Bitmask of GPIO to set to input, as bits 0-29
+ * \param value Values to set
+ *
+ * For each 1 bit in "mask", switch that pin to the direction given by
+ * corresponding bit in "value", leaving other pins unchanged.
+ * E.g. gpio_set_dir_masked(0x3, 0x2); -> set pin 0 to input, pin 1 to output,
+ * simultaneously.
+ */
+static inline void gpio_set_dir_masked(uint32_t mask, uint32_t value) {
+    sio_hw->gpio_oe_togl = (sio_hw->gpio_oe ^ value) & mask;
+}
+
+/*! \brief Set direction of all pins simultaneously.
+ *  \ingroup hardware_gpio
+ *
+ * \param values individual settings for each gpio; for GPIO N, bit N is 1 for out, 0 for in
+ */
+static inline void gpio_set_dir_all_bits(uint32_t values) {
+    sio_hw->gpio_oe = values;
+}
+
+/*! \brief Set a single GPIO direction
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param out true for out, false for in
+ */
+static inline void gpio_set_dir(uint gpio, bool out) {
+    uint32_t mask = 1ul << gpio;
+    if (out)
+        gpio_set_dir_out_masked(mask);
+    else
+        gpio_set_dir_in_masked(mask);
+}
+
+/*! \brief Check if a specific GPIO direction is OUT
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \return true if the direction for the pin is OUT
+ */
+static inline bool gpio_is_dir_out(uint gpio) {
+    return !!(sio_hw->gpio_oe & (1u << (gpio)));
+}
+
+/*! \brief Get a specific GPIO direction
+ *  \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \return 1 for out, 0 for in
+ */
+static inline uint gpio_get_dir(uint gpio) {
+    return gpio_is_dir_out(gpio); // note GPIO_OUT is 1/true and GPIO_IN is 0/false anyway
+}
+
+extern void gpio_debug_pins_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+// PICO_CONFIG: PICO_DEBUG_PIN_BASE, First pin to use for debug output (if enabled), min=0, max=28, default=19, group=hardware_gpio
+#ifndef PICO_DEBUG_PIN_BASE
+#define PICO_DEBUG_PIN_BASE 19u
+#endif
+
+// PICO_CONFIG: PICO_DEBUG_PIN_COUNT, Number of pins to use for debug output (if enabled), min=1, max=28, default=3, group=hardware_gpio
+#ifndef PICO_DEBUG_PIN_COUNT
+#define PICO_DEBUG_PIN_COUNT 3u
+#endif
+
+#ifndef __cplusplus
+// note these two macros may only be used once per and only apply per compilation unit (hence the CU_)
+#define CU_REGISTER_DEBUG_PINS(...) enum __unused DEBUG_PIN_TYPE { _none = 0, __VA_ARGS__ }; static enum DEBUG_PIN_TYPE __selected_debug_pins;
+#define CU_SELECT_DEBUG_PINS(x) static enum DEBUG_PIN_TYPE __selected_debug_pins = (x);
+#define DEBUG_PINS_ENABLED(p) (__selected_debug_pins == (p))
+#else
+#define CU_REGISTER_DEBUG_PINS(p...) \
+    enum DEBUG_PIN_TYPE { _none = 0, p }; \
+    template <enum DEBUG_PIN_TYPE> class __debug_pin_settings { \
+        public: \
+            static inline bool enabled() { return false; } \
+    };
+#define CU_SELECT_DEBUG_PINS(x) template<> inline bool __debug_pin_settings<x>::enabled() { return true; };
+#define DEBUG_PINS_ENABLED(p) (__debug_pin_settings<p>::enabled())
+#endif
+#define DEBUG_PINS_SET(p, v) if (DEBUG_PINS_ENABLED(p)) gpio_set_mask((unsigned)(v)<<PICO_DEBUG_PIN_BASE)
+#define DEBUG_PINS_CLR(p, v) if (DEBUG_PINS_ENABLED(p)) gpio_clr_mask((unsigned)(v)<<PICO_DEBUG_PIN_BASE)
+#define DEBUG_PINS_XOR(p, v) if (DEBUG_PINS_ENABLED(p)) gpio_xor_mask((unsigned)(v)<<PICO_DEBUG_PIN_BASE)
+
+#endif // _GPIO_H_
diff --git a/src/rp2_common/hardware_i2c/CMakeLists.txt b/src/rp2_common/hardware_i2c/CMakeLists.txt
new file mode 100644
index 0000000..aba48dd
--- /dev/null
+++ b/src/rp2_common/hardware_i2c/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(i2c)
diff --git a/src/rp2_common/hardware_i2c/i2c.c b/src/rp2_common/hardware_i2c/i2c.c
new file mode 100644
index 0000000..95bcfea
--- /dev/null
+++ b/src/rp2_common/hardware_i2c/i2c.c
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/i2c.h"
+#include "hardware/resets.h"
+#include "hardware/clocks.h"
+#include "pico/timeout_helper.h"
+
+check_hw_layout(i2c_hw_t, enable, I2C_IC_ENABLE_OFFSET);
+check_hw_layout(i2c_hw_t, clr_restart_det, I2C_IC_CLR_RESTART_DET_OFFSET);
+
+i2c_inst_t i2c0_inst = {i2c0_hw, false};
+i2c_inst_t i2c1_inst = {i2c1_hw, false};
+
+static inline void i2c_reset(i2c_inst_t *i2c) {
+    invalid_params_if(I2C, i2c != i2c0 && i2c != i2c1);
+    reset_block(i2c == i2c0 ? RESETS_RESET_I2C0_BITS : RESETS_RESET_I2C1_BITS);
+}
+
+static inline void i2c_unreset(i2c_inst_t *i2c) {
+    invalid_params_if(I2C, i2c != i2c0 && i2c != i2c1);
+    unreset_block_wait(i2c == i2c0 ? RESETS_RESET_I2C0_BITS : RESETS_RESET_I2C1_BITS);
+}
+
+// Addresses of the form 000 0xxx or 111 1xxx are reserved. No slave should
+// have these addresses.
+static inline bool i2c_reserved_addr(uint8_t addr) {
+    return (addr & 0x78) == 0 || (addr & 0x78) == 0x78;
+}
+
+uint i2c_init(i2c_inst_t *i2c, uint baudrate) {
+    i2c_reset(i2c);
+    i2c_unreset(i2c);
+    i2c->restart_on_next = false;
+
+    i2c->hw->enable = 0;
+
+    // Configure as a fast-mode master with RepStart support, 7-bit addresses
+    i2c->hw->con =
+            I2C_IC_CON_SPEED_VALUE_FAST << I2C_IC_CON_SPEED_LSB |
+            I2C_IC_CON_MASTER_MODE_BITS |
+            I2C_IC_CON_IC_SLAVE_DISABLE_BITS |
+            I2C_IC_CON_IC_RESTART_EN_BITS |
+            I2C_IC_CON_TX_EMPTY_CTRL_BITS;
+
+    // Set FIFO watermarks to 1 to make things simpler. This is encoded by a register value of 0.
+    i2c->hw->tx_tl = 0;
+    i2c->hw->rx_tl = 0;
+
+    // Always enable the DREQ signalling -- harmless if DMA isn't listening
+    i2c->hw->dma_cr = I2C_IC_DMA_CR_TDMAE_BITS | I2C_IC_DMA_CR_RDMAE_BITS;
+
+    // Re-sets i2c->hw->enable upon returning:
+    return i2c_set_baudrate(i2c, baudrate);
+}
+
+void i2c_deinit(i2c_inst_t *i2c) {
+    i2c_reset(i2c);
+}
+
+uint i2c_set_baudrate(i2c_inst_t *i2c, uint baudrate) {
+    invalid_params_if(I2C, baudrate == 0);
+    // I2C is synchronous design that runs from clk_sys
+    uint freq_in = clock_get_hz(clk_sys);
+
+    // TODO there are some subtleties to I2C timing which we are completely ignoring here
+    uint period = (freq_in + baudrate / 2) / baudrate;
+    uint lcnt = period * 3 / 5; // oof this one hurts
+    uint hcnt = period - lcnt;
+    // Check for out-of-range divisors:
+    invalid_params_if(I2C, hcnt > I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS);
+    invalid_params_if(I2C, lcnt > I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS);
+    invalid_params_if(I2C, hcnt < 8);
+    invalid_params_if(I2C, lcnt < 8);
+
+    // Per I2C-bus specification a device in standard or fast mode must
+    // internally provide a hold time of at least 300ns for the SDA signal to
+    // bridge the undefined region of the falling edge of SCL. A smaller hold
+    // time of 120ns is used for fast mode plus.
+    uint sda_tx_hold_count;
+    if (baudrate < 1000000) {
+        // sda_tx_hold_count = freq_in [cycles/s] * 300ns * (1s / 1e9ns)
+        // Reduce 300/1e9 to 3/1e7 to avoid numbers that don't fit in uint.
+        // Add 1 to avoid division truncation.
+        sda_tx_hold_count = ((freq_in * 3) / 10000000) + 1;
+    } else {
+        // sda_tx_hold_count = freq_in [cycles/s] * 120ns * (1s / 1e9ns)
+        // Reduce 120/1e9 to 3/25e6 to avoid numbers that don't fit in uint.
+        // Add 1 to avoid division truncation.
+        sda_tx_hold_count = ((freq_in * 3) / 25000000) + 1;
+    }
+    assert(sda_tx_hold_count <= lcnt - 2);
+
+    i2c->hw->enable = 0;
+    // Always use "fast" mode (<= 400 kHz, works fine for standard mode too)
+    hw_write_masked(&i2c->hw->con,
+                   I2C_IC_CON_SPEED_VALUE_FAST << I2C_IC_CON_SPEED_LSB,
+                   I2C_IC_CON_SPEED_BITS
+    );
+    i2c->hw->fs_scl_hcnt = hcnt;
+    i2c->hw->fs_scl_lcnt = lcnt;
+    i2c->hw->fs_spklen = lcnt < 16 ? 1 : lcnt / 16;
+    hw_write_masked(&i2c->hw->sda_hold,
+                    sda_tx_hold_count << I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB,
+                    I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS);
+
+    i2c->hw->enable = 1;
+    return freq_in / period;
+}
+
+void i2c_set_slave_mode(i2c_inst_t *i2c, bool slave, uint8_t addr) {
+    invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses
+    invalid_params_if(I2C, i2c_reserved_addr(addr));
+    i2c->hw->enable = 0;
+    uint32_t ctrl_set_if_master = I2C_IC_CON_MASTER_MODE_BITS | I2C_IC_CON_IC_SLAVE_DISABLE_BITS;
+    uint32_t ctrl_set_if_slave = I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS;
+    if (slave) {
+        hw_write_masked(&i2c->hw->con,
+            ctrl_set_if_slave,
+            ctrl_set_if_master | ctrl_set_if_slave
+        );
+        i2c->hw->sar = addr;
+    } else {
+        hw_write_masked(&i2c->hw->con,
+            ctrl_set_if_master,
+            ctrl_set_if_master | ctrl_set_if_slave
+        );
+    }
+    i2c->hw->enable = 1;
+}
+
+static int i2c_write_blocking_internal(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop,
+                                       check_timeout_fn timeout_check, struct timeout_state *ts) {
+    invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses
+    invalid_params_if(I2C, i2c_reserved_addr(addr));
+    // Synopsys hw accepts start/stop flags alongside data items in the same
+    // FIFO word, so no 0 byte transfers.
+    invalid_params_if(I2C, len == 0);
+    invalid_params_if(I2C, ((int)len) < 0);
+
+    i2c->hw->enable = 0;
+    i2c->hw->tar = addr;
+    i2c->hw->enable = 1;
+
+    bool abort = false;
+    bool timeout = false;
+
+    uint32_t abort_reason = 0;
+    int byte_ctr;
+
+    int ilen = (int)len;
+    for (byte_ctr = 0; byte_ctr < ilen; ++byte_ctr) {
+        bool first = byte_ctr == 0;
+        bool last = byte_ctr == ilen - 1;
+
+        i2c->hw->data_cmd =
+                bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB |
+                bool_to_bit(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB |
+                *src++;
+
+        // Wait until the transmission of the address/data from the internal
+        // shift register has completed. For this to function correctly, the
+        // TX_EMPTY_CTRL flag in IC_CON must be set. The TX_EMPTY_CTRL flag
+        // was set in i2c_init.
+        do {
+            if (timeout_check) {
+                timeout = timeout_check(ts);
+                abort |= timeout;
+            }
+            tight_loop_contents();
+        } while (!timeout && !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS));
+
+        // If there was a timeout, don't attempt to do anything else.
+        if (!timeout) {
+            abort_reason = i2c->hw->tx_abrt_source;
+            if (abort_reason) {
+                // Note clearing the abort flag also clears the reason, and
+                // this instance of flag is clear-on-read! Note also the
+                // IC_CLR_TX_ABRT register always reads as 0.
+                i2c->hw->clr_tx_abrt;
+                abort = true;
+            }
+
+            if (abort || (last && !nostop)) {
+                // If the transaction was aborted or if it completed
+                // successfully wait until the STOP condition has occured.
+
+                // TODO Could there be an abort while waiting for the STOP
+                // condition here? If so, additional code would be needed here
+                // to take care of the abort.
+                do {
+                    if (timeout_check) {
+                        timeout = timeout_check(ts);
+                        abort |= timeout;
+                    }
+                    tight_loop_contents();
+                } while (!timeout && !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_STOP_DET_BITS));
+
+                // If there was a timeout, don't attempt to do anything else.
+                if (!timeout) {
+                    i2c->hw->clr_stop_det;
+                }
+            }
+        }
+
+        // Note the hardware issues a STOP automatically on an abort condition.
+        // Note also the hardware clears RX FIFO as well as TX on abort,
+        // because we set hwparam IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT to 0.
+        if (abort)
+            break;
+    }
+
+    int rval;
+
+    // A lot of things could have just happened due to the ingenious and
+    // creative design of I2C. Try to figure things out.
+    if (abort) {
+        if (timeout)
+            rval = PICO_ERROR_TIMEOUT;
+        else if (!abort_reason || abort_reason & I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS) {
+            // No reported errors - seems to happen if there is nothing connected to the bus.
+            // Address byte not acknowledged
+            rval = PICO_ERROR_GENERIC;
+        } else if (abort_reason & I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS) {
+            // Address acknowledged, some data not acknowledged
+            rval = byte_ctr;
+        } else {
+            //panic("Unknown abort from I2C instance @%08x: %08x\n", (uint32_t) i2c->hw, abort_reason);
+            rval = PICO_ERROR_GENERIC;
+        }
+    } else {
+        rval = byte_ctr;
+    }
+
+    // nostop means we are now at the end of a *message* but not the end of a *transfer*
+    i2c->restart_on_next = nostop;
+    return rval;
+}
+
+int i2c_write_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop) {
+    return i2c_write_blocking_internal(i2c, addr, src, len, nostop, NULL, NULL);
+}
+
+int i2c_write_blocking_until(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop,
+                             absolute_time_t until) {
+    timeout_state_t ts;
+    return i2c_write_blocking_internal(i2c, addr, src, len, nostop, init_single_timeout_until(&ts, until), &ts);
+}
+
+int i2c_write_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop,
+                                  uint timeout_per_char_us) {
+    timeout_state_t ts;
+    return i2c_write_blocking_internal(i2c, addr, src, len, nostop,
+                                       init_per_iteration_timeout_us(&ts, timeout_per_char_us), &ts);
+}
+
+static int i2c_read_blocking_internal(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop,
+                               check_timeout_fn timeout_check, timeout_state_t *ts) {
+    invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses
+    invalid_params_if(I2C, i2c_reserved_addr(addr));
+    invalid_params_if(I2C, len == 0);
+    invalid_params_if(I2C, ((int)len) < 0);
+
+    i2c->hw->enable = 0;
+    i2c->hw->tar = addr;
+    i2c->hw->enable = 1;
+
+    bool abort = false;
+    bool timeout = false;
+    uint32_t abort_reason;
+    int byte_ctr;
+    int ilen = (int)len;
+    for (byte_ctr = 0; byte_ctr < ilen; ++byte_ctr) {
+        bool first = byte_ctr == 0;
+        bool last = byte_ctr == ilen - 1;
+        while (!i2c_get_write_available(i2c))
+            tight_loop_contents();
+
+        i2c->hw->data_cmd =
+                bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB |
+                bool_to_bit(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB |
+                I2C_IC_DATA_CMD_CMD_BITS; // -> 1 for read
+
+        do {
+            abort_reason = i2c->hw->tx_abrt_source;
+            abort = (bool) i2c->hw->clr_tx_abrt;
+            if (timeout_check) {
+                timeout = timeout_check(ts);
+                abort |= timeout;
+            }
+        } while (!abort && !i2c_get_read_available(i2c));
+
+        if (abort)
+            break;
+
+        *dst++ = (uint8_t) i2c->hw->data_cmd;
+    }
+
+    int rval;
+
+    if (abort) {
+        if (timeout)
+            rval = PICO_ERROR_TIMEOUT;
+        else if (!abort_reason || abort_reason & I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS) {
+            // No reported errors - seems to happen if there is nothing connected to the bus.
+            // Address byte not acknowledged
+            rval = PICO_ERROR_GENERIC;
+        } else {
+//            panic("Unknown abort from I2C instance @%08x: %08x\n", (uint32_t) i2c->hw, abort_reason);
+            rval = PICO_ERROR_GENERIC;
+        }
+    } else {
+        rval = byte_ctr;
+    }
+
+    i2c->restart_on_next = nostop;
+    return rval;
+}
+
+int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop) {
+    return i2c_read_blocking_internal(i2c, addr, dst, len, nostop, NULL, NULL);
+}
+
+int i2c_read_blocking_until(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, absolute_time_t until) {
+    timeout_state_t ts;
+    return i2c_read_blocking_internal(i2c, addr, dst, len, nostop, init_single_timeout_until(&ts, until), &ts);
+}
+
+int i2c_read_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop,
+                                 uint timeout_per_char_us) {
+    timeout_state_t ts;
+    return i2c_read_blocking_internal(i2c, addr, dst, len, nostop,
+                                      init_per_iteration_timeout_us(&ts, timeout_per_char_us), &ts);
+}
diff --git a/src/rp2_common/hardware_i2c/include/hardware/i2c.h b/src/rp2_common/hardware_i2c/include/hardware/i2c.h
new file mode 100644
index 0000000..23ff8f1
--- /dev/null
+++ b/src/rp2_common/hardware_i2c/include/hardware/i2c.h
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_I2C_H
+#define _HARDWARE_I2C_H
+
+#include "pico.h"
+#include "pico/time.h"
+#include "hardware/structs/i2c.h"
+#include "hardware/regs/dreq.h"
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_I2C, Enable/disable assertions in the I2C module, type=bool, default=0, group=hardware_i2c
+#ifndef PARAM_ASSERTIONS_ENABLED_I2C
+#define PARAM_ASSERTIONS_ENABLED_I2C 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file hardware/i2c.h
+ *  \defgroup hardware_i2c hardware_i2c
+ *
+ * I2C Controller API
+ *
+ * The I2C bus is a two-wire serial interface, consisting of a serial data line SDA and a serial clock SCL. These wires carry
+ * information between the devices connected to the bus. Each device is recognized by a unique 7-bit address and can operate as
+ * either a “transmitter” or “receiver”, depending on the function of the device. Devices can also be considered as masters or
+ * slaves when performing data transfers. A master is a device that initiates a data transfer on the bus and generates the
+ * clock signals to permit that transfer. The first byte in the data transfer always contains the 7-bit address and
+ * a read/write bit in the LSB position. This API takes care of toggling the read/write bit. After this, any device addressed
+ * is considered a slave. 
+ *
+ * This API allows the controller to be set up as a master or a slave using the \ref i2c_set_slave_mode function.
+ *
+ * The external pins of each controller are connected to GPIO pins as defined in the GPIO muxing table in the datasheet. The muxing options
+ * give some IO flexibility, but each controller external pin should be connected to only one GPIO.
+ *
+ * Note that the controller does NOT support High speed mode or Ultra-fast speed mode, the fastest operation being fast mode plus
+ * at up to 1000Kb/s.
+ *
+ * See the datasheet for more information on the I2C controller and its usage.
+ *
+ * \subsection i2c_example Example
+ * \addtogroup hardware_i2c
+ * \include bus_scan.c
+ */
+
+typedef struct i2c_inst i2c_inst_t;
+
+// PICO_CONFIG: PICO_DEFAULT_I2C, Define the default I2C for a board, min=0, max=1, group=hardware_i2c
+// PICO_CONFIG: PICO_DEFAULT_I2C_SDA_PIN, Define the default I2C SDA pin, min=0, max=29, group=hardware_i2c
+// PICO_CONFIG: PICO_DEFAULT_I2C_SCL_PIN, Define the default I2C SCL pin, min=0, max=29, group=hardware_i2c
+
+/** The I2C identifiers for use in I2C functions.
+ *
+ * e.g. i2c_init(i2c0, 48000)
+ *
+ *  \ingroup hardware_i2c
+ * @{
+ */
+extern i2c_inst_t i2c0_inst;
+extern i2c_inst_t i2c1_inst;
+
+#define i2c0 (&i2c0_inst) ///< Identifier for I2C HW Block 0
+#define i2c1 (&i2c1_inst) ///< Identifier for I2C HW Block 1
+
+#if !defined(PICO_DEFAULT_I2C_INSTANCE) && defined(PICO_DEFAULT_I2C)
+#define PICO_DEFAULT_I2C_INSTANCE (__CONCAT(i2c,PICO_DEFAULT_I2C))
+#endif
+
+#ifdef PICO_DEFAULT_I2C_INSTANCE
+#define i2c_default PICO_DEFAULT_I2C_INSTANCE
+#endif
+
+/** @} */
+
+// ----------------------------------------------------------------------------
+// Setup
+
+/*! \brief   Initialise the I2C HW block
+ *  \ingroup hardware_i2c
+ *
+ * Put the I2C hardware into a known state, and enable it. Must be called
+ * before other functions. By default, the I2C is configured to operate as a
+ * master.
+ *
+ * The I2C bus frequency is set as close as possible to requested, and
+ * the return actual rate set is returned
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param baudrate Baudrate in Hz (e.g. 100kHz is 100000)
+ * \return Actual set baudrate
+ */
+uint i2c_init(i2c_inst_t *i2c, uint baudrate);
+
+/*! \brief   Disable the I2C HW block
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ *
+ * Disable the I2C again if it is no longer used. Must be reinitialised before
+ * being used again.
+ */
+void i2c_deinit(i2c_inst_t *i2c);
+
+/*! \brief  Set I2C baudrate
+ *  \ingroup hardware_i2c
+ *
+ * Set I2C bus frequency as close as possible to requested, and return actual
+ * rate set.
+ * Baudrate may not be as exactly requested due to clocking limitations.
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param baudrate Baudrate in Hz (e.g. 100kHz is 100000)
+ * \return Actual set baudrate
+ */
+uint i2c_set_baudrate(i2c_inst_t *i2c, uint baudrate);
+
+/*! \brief  Set I2C port to slave mode
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param slave true to use slave mode, false to use master mode
+ * \param addr If \p slave is true, set the slave address to this value
+ */
+void i2c_set_slave_mode(i2c_inst_t *i2c, bool slave, uint8_t addr);
+
+// ----------------------------------------------------------------------------
+// Generic input/output
+
+struct i2c_inst {
+    i2c_hw_t *hw;
+    bool restart_on_next;
+};
+
+/*! \brief Convert I2C instance to hardware instance number
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c I2C instance
+ * \return Number of I2C, 0 or 1.
+ */
+static inline uint i2c_hw_index(i2c_inst_t *i2c) {
+    invalid_params_if(I2C, i2c != i2c0 && i2c != i2c1);
+    return i2c == i2c1 ? 1 : 0;
+}
+
+static inline i2c_hw_t *i2c_get_hw(i2c_inst_t *i2c) {
+    i2c_hw_index(i2c); // check it is a hw i2c
+    return i2c->hw;
+}
+
+/*! \brief Attempt to write specified number of bytes to address, blocking until the specified absolute time is reached.
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param addr 7-bit address of device to write to
+ * \param src Pointer to data to send
+ * \param len Length of data in bytes to send
+ * \param nostop  If true, master retains control of the bus at the end of the transfer (no Stop is issued),
+ *           and the next transfer will begin with a Restart rather than a Start.
+ * \param until The absolute time that the block will wait until the entire transaction is complete. Note, an individual timeout of
+ *           this value divided by the length of data is applied for each byte transfer, so if the first or subsequent
+ *           bytes fails to transfer within that sub timeout, the function will return with an error.
+ *
+ * \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred.
+ */
+int i2c_write_blocking_until(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, absolute_time_t until);
+
+/*! \brief  Attempt to read specified number of bytes from address, blocking until the specified absolute time is reached.
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param addr 7-bit address of device to read from
+ * \param dst Pointer to buffer to receive data
+ * \param len Length of data in bytes to receive
+ * \param nostop  If true, master retains control of the bus at the end of the transfer (no Stop is issued),
+ *           and the next transfer will begin with a Restart rather than a Start.
+ * \param until The absolute time that the block will wait until the entire transaction is complete.
+ * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred.
+ */
+int i2c_read_blocking_until(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, absolute_time_t until);
+
+/*! \brief Attempt to write specified number of bytes to address, with timeout
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param addr 7-bit address of device to write to
+ * \param src Pointer to data to send
+ * \param len Length of data in bytes to send
+ * \param nostop  If true, master retains control of the bus at the end of the transfer (no Stop is issued),
+ *           and the next transfer will begin with a Restart rather than a Start.
+ * \param timeout_us The time that the function will wait for the entire transaction to complete. Note, an individual timeout of
+ *           this value divided by the length of data is applied for each byte transfer, so if the first or subsequent
+ *           bytes fails to transfer within that sub timeout, the function will return with an error.
+ *
+ * \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred.
+ */
+static inline int i2c_write_timeout_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, uint timeout_us) {
+    absolute_time_t t = make_timeout_time_us(timeout_us);
+    return i2c_write_blocking_until(i2c, addr, src, len, nostop, t);
+}
+
+int i2c_write_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, uint timeout_per_char_us);
+
+/*! \brief  Attempt to read specified number of bytes from address, with timeout
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param addr 7-bit address of device to read from
+ * \param dst Pointer to buffer to receive data
+ * \param len Length of data in bytes to receive
+ * \param nostop  If true, master retains control of the bus at the end of the transfer (no Stop is issued),
+ *           and the next transfer will begin with a Restart rather than a Start.
+ * \param timeout_us The time that the function will wait for the entire transaction to complete
+ * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred.
+ */
+static inline int i2c_read_timeout_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, uint timeout_us) {
+    absolute_time_t t = make_timeout_time_us(timeout_us);
+    return i2c_read_blocking_until(i2c, addr, dst, len, nostop, t);
+}
+
+int i2c_read_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, uint timeout_per_char_us);
+
+/*! \brief Attempt to write specified number of bytes to address, blocking
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param addr 7-bit address of device to write to
+ * \param src Pointer to data to send
+ * \param len Length of data in bytes to send
+ * \param nostop  If true, master retains control of the bus at the end of the transfer (no Stop is issued),
+ *           and the next transfer will begin with a Restart rather than a Start.
+ * \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present.
+ */
+int i2c_write_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop);
+
+/*! \brief  Attempt to read specified number of bytes from address, blocking
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param addr 7-bit address of device to read from
+ * \param dst Pointer to buffer to receive data
+ * \param len Length of data in bytes to receive
+ * \param nostop  If true, master retains control of the bus at the end of the transfer (no Stop is issued),
+ *           and the next transfer will begin with a Restart rather than a Start.
+ * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged or no device present.
+ */
+int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop);
+
+
+/*! \brief Determine non-blocking write space available
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \return 0 if no space is available in the I2C to write more data. If return is nonzero, at
+ * least that many bytes can be written without blocking.
+ */
+static inline size_t i2c_get_write_available(i2c_inst_t *i2c) {
+    const size_t IC_TX_BUFFER_DEPTH = 16;
+    return IC_TX_BUFFER_DEPTH - i2c_get_hw(i2c)->txflr;
+}
+
+/*! \brief Determine number of bytes received
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \return 0 if no data available, if return is nonzero at
+ * least that many bytes can be read without blocking.
+ */
+static inline size_t i2c_get_read_available(i2c_inst_t *i2c) {
+    return i2c_get_hw(i2c)->rxflr;
+}
+
+/*! \brief Write direct to TX FIFO
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param src Data to send
+ * \param len Number of bytes to send
+ *
+ * Writes directly to the I2C TX FIFO which is mainly useful for
+ * slave-mode operation.
+ */
+static inline void i2c_write_raw_blocking(i2c_inst_t *i2c, const uint8_t *src, size_t len) {
+    for (size_t i = 0; i < len; ++i) {
+        // TODO NACK or STOP on end?
+        while (!i2c_get_write_available(i2c))
+            tight_loop_contents();
+        i2c_get_hw(i2c)->data_cmd = *src++;
+    }
+}
+
+/*! \brief Read direct from RX FIFO
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param dst Buffer to accept data
+ * \param len Number of bytes to read
+ *
+ * Reads directly from the I2C RX FIFO which is mainly useful for
+ * slave-mode operation.
+ */
+static inline void i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t len) {
+    for (size_t i = 0; i < len; ++i) {
+        while (!i2c_get_read_available(i2c))
+            tight_loop_contents();
+        *dst++ = (uint8_t)i2c_get_hw(i2c)->data_cmd;
+    }
+}
+
+/*! \brief Return the DREQ to use for pacing transfers to/from a particular I2C instance
+ *  \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param is_tx true for sending data to the I2C instance, false for receiving data from the I2C instance
+ */
+static inline uint i2c_get_dreq(i2c_inst_t *i2c, bool is_tx) {
+    static_assert(DREQ_I2C0_RX == DREQ_I2C0_TX + 1, "");
+    static_assert(DREQ_I2C1_RX == DREQ_I2C1_TX + 1, "");
+    static_assert(DREQ_I2C1_TX == DREQ_I2C0_TX + 2, "");
+    return DREQ_I2C0_TX + i2c_hw_index(i2c) * 2 + !is_tx;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_interp/CMakeLists.txt b/src/rp2_common/hardware_interp/CMakeLists.txt
new file mode 100644
index 0000000..d6d693f
--- /dev/null
+++ b/src/rp2_common/hardware_interp/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(interp)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_interp/include/hardware/interp.h b/src/rp2_common/hardware_interp/include/hardware/interp.h
new file mode 100644
index 0000000..35372e9
--- /dev/null
+++ b/src/rp2_common/hardware_interp/include/hardware/interp.h
@@ -0,0 +1,458 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_INTERP_H
+#define _HARDWARE_INTERP_H
+
+#include "pico.h"
+#include "hardware/structs/interp.h"
+#include "hardware/regs/sio.h"
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_INTERP, Enable/disable assertions in the interpolation module, type=bool, default=0, group=hardware_interp
+#ifndef PARAM_ASSERTIONS_ENABLED_INTERP
+#define PARAM_ASSERTIONS_ENABLED_INTERP 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file hardware/interp.h
+ *  \defgroup hardware_interp hardware_interp
+ *
+ * Hardware Interpolator API
+ *
+ * Each core is equipped with two interpolators (INTERP0 and INTERP1) which can be used to accelerate
+ * tasks by combining certain pre-configured simple operations into a single processor cycle. Intended
+ * for cases where the pre-configured operation is repeated a large number of times, this results in
+ * code which uses both fewer CPU cycles and fewer CPU registers in the time critical sections of the
+ * code.
+ *
+ * The interpolators are used heavily to accelerate audio operations within the SDK, but their
+ * flexible configuration make it possible to optimise many other tasks such as quantization and
+ * dithering, table lookup address generation, affine texture mapping, decompression and linear feedback.
+ *
+ * Please refer to the RP2040 datasheet for more information on the HW interpolators and how they work.
+ */
+
+#define interp0 interp0_hw
+#define interp1 interp1_hw
+
+/** \brief Interpolator configuration
+ *  \defgroup interp_config interp_config
+ *  \ingroup hardware_interp
+ *
+ * Each interpolator needs to be configured, these functions provide handy helpers to set up configuration
+ * structures.
+ *
+ */
+
+typedef struct {
+    uint32_t ctrl;
+} interp_config;
+
+static inline uint interp_index(interp_hw_t *interp) {
+    valid_params_if(INTERP, interp == interp0 || interp == interp1);
+    return interp == interp1 ? 1 : 0;
+}
+
+/*! \brief Claim the interpolator lane specified
+ *  \ingroup hardware_interp
+ *
+ * Use this function to claim exclusive access to the specified interpolator lane.
+ *
+ * This function will panic if the lane is already claimed.
+ *
+ * \param interp Interpolator on which to claim a lane. interp0 or interp1
+ * \param lane The lane number, 0 or 1.
+ */
+void interp_claim_lane(interp_hw_t *interp, uint lane);
+// The above really should be called this for consistency
+#define interp_lane_claim interp_claim_lane
+
+/*! \brief Claim the interpolator lanes specified in the mask
+ *  \ingroup hardware_interp
+ *
+ * \param interp Interpolator on which to claim lanes. interp0 or interp1
+ * \param lane_mask Bit pattern of lanes to claim (only bits 0 and 1 are valid)
+ */
+void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask);
+
+/*! \brief Release a previously claimed interpolator lane
+ *  \ingroup hardware_interp
+ *
+ * \param interp Interpolator on which to release a lane. interp0 or interp1
+ * \param lane The lane number, 0 or 1
+ */
+void interp_unclaim_lane(interp_hw_t *interp, uint lane);
+// The above really should be called this for consistency
+#define interp_lane_unclaim interp_unclaim_lane
+
+/*! \brief Determine if an interpolator lane is claimed
+ *  \ingroup hardware_interp
+ *
+ * \param interp Interpolator whose lane to check
+ * \param lane The lane number, 0 or 1
+ * \return true if claimed, false otherwise
+ * \see interp_claim_lane
+ * \see interp_claim_lane_mask
+ */
+bool interp_lane_is_claimed(interp_hw_t *interp, uint lane);
+
+/*! \brief Release previously claimed interpolator lanes \see interp_claim_lane_mask
+ *  \ingroup hardware_interp
+ *
+ * \param interp Interpolator on which to release lanes. interp0 or interp1
+ * \param lane_mask Bit pattern of lanes to unclaim (only bits 0 and 1 are valid)
+ */
+void interp_unclaim_lane_mask(interp_hw_t *interp, uint lane_mask);
+
+/*! \brief Set the interpolator shift value
+ *  \ingroup interp_config
+ *
+ * Sets the number of bits the accumulator is shifted before masking, on each iteration.
+ *
+ * \param c Pointer to an interpolator config
+ * \param shift Number of bits
+ */
+static inline void interp_config_set_shift(interp_config *c, uint shift) {
+    valid_params_if(INTERP, shift < 32);
+    c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SHIFT_BITS) |
+              ((shift << SIO_INTERP0_CTRL_LANE0_SHIFT_LSB) & SIO_INTERP0_CTRL_LANE0_SHIFT_BITS);
+}
+
+/*! \brief Set the interpolator mask range
+ *  \ingroup interp_config
+ *
+ * Sets the range of bits (least to most) that are allowed to pass through the interpolator
+ *
+ * \param c Pointer to interpolation config
+ * \param mask_lsb The least significant bit allowed to pass
+ * \param mask_msb The most significant bit allowed to pass
+ */
+static inline void interp_config_set_mask(interp_config *c, uint mask_lsb, uint mask_msb) {
+    valid_params_if(INTERP, mask_msb < 32);
+    valid_params_if(INTERP, mask_lsb <= mask_msb);
+    c->ctrl = (c->ctrl & ~(SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS | SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS)) |
+              ((mask_lsb << SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB) & SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS) |
+              ((mask_msb << SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB) & SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS);
+}
+
+/*! \brief Enable cross input
+ *  \ingroup interp_config
+ *
+ *  Allows feeding of the accumulator content from the other lane back in to this lanes shift+mask hardware.
+ *  This will take effect even if the interp_config_set_add_raw option is set as the cross input mux is before the
+ *  shift+mask bypass
+ *
+ * \param c Pointer to interpolation config
+ * \param cross_input If true, enable the cross input.
+ */
+static inline void interp_config_set_cross_input(interp_config *c, bool cross_input) {
+    c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS) |
+              (cross_input ? SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS : 0);
+}
+
+/*! \brief Enable cross results
+ *  \ingroup interp_config
+ *
+ *  Allows feeding of the other lane’s result into this lane’s accumulator on a POP operation.
+ *
+ * \param c Pointer to interpolation config
+ * \param cross_result If true, enables the cross result
+ */
+static inline void interp_config_set_cross_result(interp_config *c, bool cross_result) {
+    c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS) |
+              (cross_result ? SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS : 0);
+}
+
+/*! \brief Set sign extension
+ *  \ingroup interp_config
+ *
+ * Enables signed mode, where the shifted and masked accumulator value is sign-extended to 32 bits
+ * before adding to BASE1, and LANE1 PEEK/POP results appear extended to 32 bits when read by processor.
+ *
+ * \param c Pointer to interpolation config
+ * \param  _signed If true, enables sign extension
+ */
+static inline void interp_config_set_signed(interp_config *c, bool _signed) {
+    c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SIGNED_BITS) |
+              (_signed ? SIO_INTERP0_CTRL_LANE0_SIGNED_BITS : 0);
+}
+
+/*! \brief Set raw add option
+ *  \ingroup interp_config
+ *
+ * When enabled, mask + shift is bypassed for LANE0 result. This does not affect the FULL result.
+ *
+ * \param c Pointer to interpolation config
+ * \param add_raw If true, enable raw add option.
+ */
+static inline void interp_config_set_add_raw(interp_config *c, bool add_raw) {
+    c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS) |
+              (add_raw ? SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS : 0);
+}
+
+/*! \brief Set blend mode
+ *  \ingroup interp_config
+ *
+ * If enabled, LANE1 result is a linear interpolation between BASE0 and BASE1, controlled
+ * by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths)
+ *
+ * LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)
+ *
+ * FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)
+ *
+ * LANE1 SIGNED flag controls whether the interpolation is signed or unsig
+ *
+ * \param c Pointer to interpolation config
+ * \param blend Set true to enable blend mode.
+*/
+static inline void interp_config_set_blend(interp_config *c, bool blend) {
+    c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_BLEND_BITS) |
+              (blend ? SIO_INTERP0_CTRL_LANE0_BLEND_BITS : 0);
+}
+
+/*! \brief Set interpolator clamp mode (Interpolator 1 only)
+ *  \ingroup interp_config
+ *
+ * Only present on INTERP1 on each core. If CLAMP mode is enabled:
+ * - LANE0 result is a shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1.
+ * - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED
+ *
+ * \param c Pointer to interpolation config
+ * \param clamp Set true to enable clamp mode
+ */
+static inline void interp_config_set_clamp(interp_config *c, bool clamp) {
+    c->ctrl = (c->ctrl & ~SIO_INTERP1_CTRL_LANE0_CLAMP_BITS) |
+              (clamp ? SIO_INTERP1_CTRL_LANE0_CLAMP_BITS : 0);
+}
+
+/*! \brief Set interpolator Force bits
+ *  \ingroup interp_config
+ *
+ * ORed into bits 29:28 of the lane result presented to the processor on the bus.
+ *
+ * No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
+ * of pointers into flash or SRAM
+ *
+ * \param c Pointer to interpolation config
+ * \param bits Sets the force bits to that specified. Range 0-3 (two bits)
+ */
+static inline void interp_config_set_force_bits(interp_config *c, uint bits) {
+    invalid_params_if(INTERP, bits > 3);
+    // note cannot use hw_set_bits on SIO
+    c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS) |
+              (bits << SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB);
+}
+
+/*! \brief Get a default configuration
+ *  \ingroup interp_config
+ *
+ * \return A default interpolation configuration
+ */
+static inline interp_config interp_default_config(void) {
+    interp_config c = {0};
+    // Just pass through everything
+    interp_config_set_mask(&c, 0, 31);
+    return c;
+}
+
+/*! \brief Send configuration to a lane
+ *  \ingroup interp_config
+ *
+ * If an invalid configuration is specified (ie a lane specific item is set on wrong lane),
+ * depending on setup this function can panic.
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane to set
+ * \param config Pointer to interpolation config
+ */
+
+static inline void interp_set_config(interp_hw_t *interp, uint lane, interp_config *config) {
+    invalid_params_if(INTERP, lane > 1);
+    invalid_params_if(INTERP, config->ctrl & SIO_INTERP1_CTRL_LANE0_CLAMP_BITS &&
+                              (!interp_index(interp) || lane)); // only interp1 lane 0 has clamp bit
+    invalid_params_if(INTERP, config->ctrl & SIO_INTERP0_CTRL_LANE0_BLEND_BITS &&
+                              (interp_index(interp) || lane)); // only interp0 lane 0 has blend bit
+    interp->ctrl[lane] = config->ctrl;
+}
+
+/*! \brief Directly set the force bits on a specified lane
+ *  \ingroup hardware_interp
+ *
+ * These bits are ORed into bits 29:28 of the lane result presented to the processor on the bus.
+ * There is no effect on the internal 32-bit datapath.
+ *
+ * Useful for using a lane to generate sequence of pointers into flash or SRAM, saving a subsequent
+ * OR or add operation.
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane to set
+ * \param bits The bits to set (bits 0 and 1, value range 0-3)
+ */
+static inline void interp_set_force_bits(interp_hw_t *interp, uint lane, uint bits) {
+    // note cannot use hw_set_bits on SIO
+    interp->ctrl[lane] |= (bits << SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB);
+}
+
+typedef struct {
+    uint32_t accum[2];
+    uint32_t base[3];
+    uint32_t ctrl[2];
+} interp_hw_save_t;
+
+/*! \brief Save the specified interpolator state
+ *  \ingroup hardware_interp
+ *
+ * Can be used to save state if you need an interpolator for another purpose, state
+ * can then be recovered afterwards and continue from that point
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param saver Pointer to the save structure to fill in
+ */
+void interp_save(interp_hw_t *interp, interp_hw_save_t *saver);
+
+/*! \brief Restore an interpolator state
+ *  \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param saver Pointer to save structure to reapply to the specified interpolator
+ */
+void interp_restore(interp_hw_t *interp, interp_hw_save_t *saver);
+
+/*! \brief Sets the interpolator base register by lane
+ *  \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1 or 2
+ * \param val The value to apply to the register
+ */
+static inline void interp_set_base(interp_hw_t *interp, uint lane, uint32_t val) {
+    interp->base[lane] = val;
+}
+
+/*! \brief Gets the content of interpolator base register by lane
+ *  \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1 or 2
+ * \return  The current content of the lane base register
+ */
+static inline uint32_t interp_get_base(interp_hw_t *interp, uint lane) {
+    return interp->base[lane];
+}
+
+/*! \brief Sets the interpolator base registers simultaneously
+ *  \ingroup hardware_interp
+ *
+ *  The lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
+ *  Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param val The value to apply to the register
+ */
+static inline void interp_set_base_both(interp_hw_t *interp, uint32_t val) {
+    interp->base01 = val;
+}
+
+
+/*! \brief Sets the interpolator accumulator register by lane
+ *  \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1
+ * \param val The value to apply to the register
+ */
+static inline void interp_set_accumulator(interp_hw_t *interp, uint lane, uint32_t val) {
+    interp->accum[lane] = val;
+}
+
+/*! \brief Gets the content of the interpolator accumulator register by lane
+ *  \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1
+ * \return The current content of the register
+ */
+static inline uint32_t interp_get_accumulator(interp_hw_t *interp, uint lane) {
+    return interp->accum[lane];
+}
+
+/*! \brief Read lane result, and write lane results to both accumulators to update the interpolator
+ *  \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1
+ * \return The content of the lane result register
+ */
+static inline uint32_t interp_pop_lane_result(interp_hw_t *interp, uint lane) {
+    return interp->pop[lane];
+}
+
+/*! \brief Read lane result
+ *  \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1
+ * \return The content of the lane result register
+ */
+static inline uint32_t interp_peek_lane_result(interp_hw_t *interp, uint lane) {
+    return interp->peek[lane];
+}
+
+/*! \brief Read lane result, and write lane results to both accumulators to update the interpolator
+ *  \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \return The content of the FULL register
+ */
+static inline uint32_t interp_pop_full_result(interp_hw_t *interp) {
+    return interp->pop[2];
+}
+
+/*! \brief Read lane result
+ *  \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \return The content of the FULL register
+ */
+static inline uint32_t interp_peek_full_result(interp_hw_t *interp) {
+    return interp->peek[2];
+}
+
+/*! \brief Add to accumulator
+ *  \ingroup hardware_interp
+ *
+ * Atomically add the specified value to the accumulator on the specified lane
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1
+ * \param val Value to add
+ * \return The content of the FULL register
+ */
+static inline void interp_add_accumulater(interp_hw_t *interp, uint lane, uint32_t val) {
+    interp->add_raw[lane] = val;
+}
+
+/*! \brief Get raw lane value
+ *  \ingroup hardware_interp
+ *
+ * Returns the raw shift and mask value from the specified lane, BASE0 is NOT added
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1
+ * \return The raw shift/mask value
+ */
+static inline uint32_t interp_get_raw(interp_hw_t *interp, uint lane) {
+    return interp->add_raw[lane];
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_interp/interp.c b/src/rp2_common/hardware_interp/interp.c
new file mode 100644
index 0000000..37e8a91
--- /dev/null
+++ b/src/rp2_common/hardware_interp/interp.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/interp.h"
+#include "hardware/structs/sio.h"
+#include "hardware/claim.h"
+
+check_hw_size(interp_hw_t, SIO_INTERP1_ACCUM0_OFFSET - SIO_INTERP0_ACCUM0_OFFSET);
+
+check_hw_layout(sio_hw_t, interp, SIO_INTERP0_ACCUM0_OFFSET);
+
+static_assert(NUM_DMA_CHANNELS <= 16, "");
+
+static uint8_t _claimed;
+
+static inline uint interp_lane_bit(interp_hw_t * interp, uint lane) {
+    return (interp_index(interp) << 1u) | lane;
+}
+
+void interp_claim_lane(interp_hw_t *interp, uint lane) {
+    valid_params_if(INTERP, lane < 2);
+    hw_claim_or_assert((uint8_t *) &_claimed, interp_lane_bit(interp, lane), "Lane is already claimed");
+}
+
+void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask) {
+    valid_params_if(INTERP, lane_mask && lane_mask <= 0x3);
+    if (lane_mask & 1u) interp_claim_lane(interp, 0);
+    if (lane_mask & 2u) interp_claim_lane(interp, 1);
+}
+
+void interp_unclaim_lane(interp_hw_t *interp, uint lane) {
+    valid_params_if(INTERP, lane < 2);
+    hw_claim_clear((uint8_t *) &_claimed, interp_lane_bit(interp, lane));
+}
+
+bool interp_lane_is_claimed(interp_hw_t *interp, uint lane) {
+    valid_params_if(INTERP, lane < 2);
+    return hw_is_claimed((uint8_t *) &_claimed, interp_lane_bit(interp, lane));
+}
+
+void interp_unclaim_lane_mask(interp_hw_t *interp, uint lane_mask) {
+    valid_params_if(INTERP, lane_mask <= 0x3);
+    if (lane_mask & 1u) interp_unclaim_lane(interp, 0);
+    if (lane_mask & 2u) interp_unclaim_lane(interp, 1);
+}
+
+void interp_save(interp_hw_t *interp, interp_hw_save_t *saver) {
+    saver->accum[0] = interp->accum[0];
+    saver->accum[1] = interp->accum[1];
+    saver->base[0] = interp->base[0];
+    saver->base[1] = interp->base[1];
+    saver->base[2] = interp->base[2];
+    saver->ctrl[0] = interp->ctrl[0];
+    saver->ctrl[1] = interp->ctrl[1];
+}
+
+void interp_restore(interp_hw_t *interp, interp_hw_save_t *saver) {
+    interp->accum[0] = saver->accum[0];
+    interp->accum[1] = saver->accum[1];
+    interp->base[0] = saver->base[0];
+    interp->base[1] = saver->base[1];
+    interp->base[2] = saver->base[2];
+    interp->ctrl[0] = saver->ctrl[0];
+    interp->ctrl[1] = saver->ctrl[1];
+}
diff --git a/src/rp2_common/hardware_irq/CMakeLists.txt b/src/rp2_common/hardware_irq/CMakeLists.txt
new file mode 100644
index 0000000..c218231
--- /dev/null
+++ b/src/rp2_common/hardware_irq/CMakeLists.txt
@@ -0,0 +1,6 @@
+pico_simple_hardware_target(irq)
+
+# additional sources/libraries
+
+target_sources(hardware_irq INTERFACE ${CMAKE_CURRENT_LIST_DIR}/irq_handler_chain.S)
+target_link_libraries(hardware_irq INTERFACE pico_sync)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_irq/include/hardware/irq.h b/src/rp2_common/hardware_irq/include/hardware/irq.h
new file mode 100644
index 0000000..424a497
--- /dev/null
+++ b/src/rp2_common/hardware_irq/include/hardware/irq.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_IRQ_H_
+#define _HARDWARE_IRQ_H_
+
+// These two config items are also used by assembler, so keeping separate
+// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum number of shared IRQ handlers, default=4, advanced=true, group=hardware_irq
+#ifndef PICO_MAX_SHARED_IRQ_HANDLERS
+#define PICO_MAX_SHARED_IRQ_HANDLERS 4u
+#endif
+
+// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handlers, type=bool, default=0, group=hardware_irq
+#ifndef PICO_DISABLE_SHARED_IRQ_HANDLERS
+#define PICO_DISABLE_SHARED_IRQ_HANDLERS 0
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include "pico.h"
+#include "hardware/address_mapped.h"
+#include "hardware/regs/intctrl.h"
+#include "hardware/regs/m0plus.h"
+
+/** \file irq.h
+ *  \defgroup hardware_irq hardware_irq
+ *
+ * Hardware interrupt handling
+ *
+ * The RP2040 uses the standard ARM nested vectored interrupt controller (NVIC).
+ *
+ * Interrupts are identified by a number from 0 to 31.
+ *
+ * On the RP2040, only the lower 26 IRQ signals are connected on the NVIC; IRQs 26 to 31 are tied to zero (never firing).
+ *
+ * There is one NVIC per core, and each core's NVIC has the same hardware interrupt lines routed to it, with the exception of the IO interrupts
+ * where there is one IO interrupt per bank, per core. These are completely independent, so, for example, processor 0 can be
+ * interrupted by GPIO 0 in bank 0, and processor 1 by GPIO 1 in the same bank.
+ *
+ * \note That all IRQ APIs affect the executing core only (i.e. the core calling the function).
+ *
+ * \note You should not enable the same (shared) IRQ number on both cores, as this will lead to race conditions
+ * or starvation of one of the cores. Additionally, don't forget that disabling interrupts on one core does not disable interrupts
+ * on the other core.
+ *
+ * There are three different ways to set handlers for an IRQ:
+ *  - Calling irq_add_shared_handler() at runtime to add a handler for a multiplexed interrupt (e.g. GPIO bank) on the current core. Each handler, should check and clear the relevant hardware interrupt source
+ *  - Calling irq_set_exclusive_handler() at runtime to install a single handler for the interrupt on the current core
+ *  - Defining the interrupt handler explicitly in your application (e.g. by defining void `isr_dma_0` will make that function the handler for the DMA_IRQ_0 on core 0, and
+ *    you will not be able to change it using the above APIs at runtime). Using this method can cause link conflicts at runtime, and offers no runtime performance benefit (i.e, it should not generally be used).
+ *
+ * \note If an IRQ is enabled and fires with no handler installed, a breakpoint will be hit and the IRQ number will
+ * be in register r0.
+ *
+ * \section interrupt_nums Interrupt Numbers
+ *
+ * Interrupts are numbered as follows, a set of defines is available (intctrl.h) with these names to avoid using the numbers directly.
+ *
+ * IRQ | Interrupt Source
+ * ----|-----------------
+ *  0 | TIMER_IRQ_0
+ *  1 | TIMER_IRQ_1
+ *  2 | TIMER_IRQ_2
+ *  3 | TIMER_IRQ_3
+ *  4 | PWM_IRQ_WRAP
+ *  5 | USBCTRL_IRQ
+ *  6 | XIP_IRQ
+ *  7 | PIO0_IRQ_0
+ *  8 | PIO0_IRQ_1
+ *  9 | PIO1_IRQ_0
+ * 10 | PIO1_IRQ_1
+ * 11 | DMA_IRQ_0
+ * 12 | DMA_IRQ_1
+ * 13 | IO_IRQ_BANK0
+ * 14 | IO_IRQ_QSPI
+ * 15 | SIO_IRQ_PROC0
+ * 16 | SIO_IRQ_PROC1
+ * 17 | CLOCKS_IRQ
+ * 18 | SPI0_IRQ
+ * 19 | SPI1_IRQ
+ * 20 | UART0_IRQ
+ * 21 | UART1_IRQ
+ * 22 | ADC0_IRQ_FIFO
+ * 23 | I2C0_IRQ
+ * 24 | I2C1_IRQ
+ * 25 | RTC_IRQ
+ *
+ */
+
+// PICO_CONFIG: PICO_DEFAULT_IRQ_PRIORITY, Define the default IRQ priority, default=0x80, group=hardware_irq
+#ifndef PICO_DEFAULT_IRQ_PRIORITY
+#define PICO_DEFAULT_IRQ_PRIORITY 0x80
+#endif
+
+#define PICO_LOWEST_IRQ_PRIORITY 0xff
+#define PICO_HIGHEST_IRQ_PRIORITY 0x00
+
+// PICO_CONFIG: PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, Set default shared IRQ order priority, default=0x80, group=hardware_irq
+#ifndef PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY
+#define PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY 0x80
+#endif
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_IRQ, Enable/disable assertions in the IRQ module, type=bool, default=0, group=hardware_irq
+#ifndef PARAM_ASSERTIONS_ENABLED_IRQ
+#define PARAM_ASSERTIONS_ENABLED_IRQ 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Interrupt handler function type
+ *  \ingroup hardware_irq
+ *
+ * All interrupts handlers should be of this type, and follow normal ARM EABI register saving conventions
+ */
+typedef void (*irq_handler_t)(void);
+
+static inline void check_irq_param(__unused uint num) {
+    invalid_params_if(IRQ, num >= NUM_IRQS);
+}
+
+/*! \brief Set specified interrupt's priority
+ *  \ingroup hardware_irq
+ *
+ * \param num Interrupt number
+ * \param hardware_priority Priority to set.
+ * Numerically-lower values indicate a higher priority. Hardware priorities
+ * range from 0 (highest priority) to 255 (lowest priority) though only the
+ * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify
+ * higher or lower priorities than the default, all IRQ priorities are
+ * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup.
+ * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80
+ */
+void irq_set_priority(uint num, uint8_t hardware_priority);
+
+/*! \brief Get specified interrupt's priority
+ *  \ingroup hardware_irq
+ *
+ * Numerically-lower values indicate a higher priority. Hardware priorities
+ * range from 0 (highest priority) to 255 (lowest priority) though only the
+ * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify
+ * higher or lower priorities than the default, all IRQ priorities are
+ * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup.
+ * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80
+ *
+ * \param num Interrupt number
+ * \return the IRQ priority
+ */
+uint irq_get_priority(uint num);
+
+/*! \brief Enable or disable a specific interrupt on the executing core
+ *  \ingroup hardware_irq
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \param enabled true to enable the interrupt, false to disable
+ */
+void irq_set_enabled(uint num, bool enabled);
+
+/*! \brief Determine if a specific interrupt is enabled on the executing core
+ *  \ingroup hardware_irq
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \return true if the interrupt is enabled
+ */
+bool irq_is_enabled(uint num);
+
+/*! \brief Enable/disable multiple interrupts on the executing core
+ *  \ingroup hardware_irq
+ *
+ * \param mask 32-bit mask with one bits set for the interrupts to enable/disable
+ * \param enabled true to enable the interrupts, false to disable them.
+ */
+void irq_set_mask_enabled(uint32_t mask, bool enabled);
+
+/*! \brief  Set an exclusive interrupt handler for an interrupt on the executing core.
+ *  \ingroup hardware_irq
+ *
+ * Use this method to set a handler for single IRQ source interrupts, or when
+ * your code, use case or performance requirements dictate that there should
+ * no other handlers for the interrupt.
+ *
+ * This method will assert if there is already any sort of interrupt handler installed
+ * for the specified irq number.
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \param handler The handler to set. See \ref irq_handler_t
+ * \see irq_add_shared_handler()
+ */
+void irq_set_exclusive_handler(uint num, irq_handler_t handler);
+
+/*! \brief  Get the exclusive interrupt handler for an interrupt on the executing core.
+ *  \ingroup hardware_irq
+ *
+ * This method will return an exclusive IRQ handler set on this core
+ * by irq_set_exclusive_handler if there is one.
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \see irq_set_exclusive_handler()
+ * \return handler The handler if an exclusive handler is set for the IRQ,
+ *                 NULL if no handler is set or shared/shareable handlers are installed
+ */
+irq_handler_t irq_get_exclusive_handler(uint num);
+
+/*! \brief Add a shared interrupt handler for an interrupt on the executing core
+ *  \ingroup hardware_irq
+ *
+ * Use this method to add a handler on an irq number shared between multiple distinct hardware sources (e.g. GPIO, DMA or PIO IRQs).
+ * Handlers added by this method will all be called in sequence from highest order_priority to lowest. The
+ * irq_set_exclusive_handler() method should be used instead if you know there will or should only ever be one handler for the interrupt.
+ *
+ * This method will assert if there is an exclusive interrupt handler set for this irq number on this core, or if
+ * the (total across all IRQs on both cores) maximum (configurable via PICO_MAX_SHARED_IRQ_HANDLERS) number of shared handlers
+ * would be exceeded.
+ *
+ * \param num Interrupt number
+ * \param handler The handler to set. See \ref irq_handler_t
+ * \param order_priority The order priority controls the order that handlers for the same IRQ number on the core are called.
+ * The shared irq handlers for an interrupt are all called when an IRQ fires, however the order of the calls is based
+ * on the order_priority (higher priorities are called first, identical priorities are called in undefined order). A good
+ * rule of thumb is to use PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY if you don't much care, as it is in the middle of
+ * the priority range by default.
+ *
+ * \see irq_set_exclusive_handler()
+ */
+void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority);
+
+/*! \brief Remove a specific interrupt handler for the given irq number on the executing core
+ *  \ingroup hardware_irq
+ *
+ * This method may be used to remove an irq set via either irq_set_exclusive_handler() or
+ * irq_add_shared_handler(), and will assert if the handler is not currently installed for the given
+ * IRQ number
+ *
+ * \note This method may *only* be called from user (non IRQ code) or from within the handler
+ * itself (i.e. an IRQ handler may remove itself as part of handling the IRQ). Attempts to call
+ * from another IRQ will cause an assertion.
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \param handler The handler to removed.
+ * \see irq_set_exclusive_handler()
+ * \see irq_add_shared_handler()
+ */
+void irq_remove_handler(uint num, irq_handler_t handler);
+
+/*! \brief Get the current IRQ handler for the specified IRQ from the currently installed hardware vector table (VTOR)
+ * of the execution core
+ *  \ingroup hardware_irq
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \return the address stored in the VTABLE for the given irq number
+ */
+irq_handler_t irq_get_vtable_handler(uint num);
+
+/*! \brief Clear a specific interrupt on the executing core
+ *  \ingroup hardware_irq
+ *
+ * \param int_num Interrupt number \ref interrupt_nums
+ */
+static inline void irq_clear(uint int_num) {
+    *((volatile uint32_t *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = (1u << ((uint32_t) (int_num & 0x1F)));
+}
+
+/*! \brief Force an interrupt to be pending on the executing core
+ *  \ingroup hardware_irq
+ *
+ * This should generally not be used for IRQs connected to hardware.
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ */
+void irq_set_pending(uint num);
+
+
+/*! \brief Perform IRQ priority initialization for the current core
+ *
+ * \note This is an internal method and user should generally not call it.
+ */
+void irq_init_priorities(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+#endif
diff --git a/src/rp2_common/hardware_irq/irq.c b/src/rp2_common/hardware_irq/irq.c
new file mode 100644
index 0000000..211f6d0
--- /dev/null
+++ b/src/rp2_common/hardware_irq/irq.c
@@ -0,0 +1,413 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/irq.h"
+#include "hardware/regs/m0plus.h"
+#include "hardware/platform_defs.h"
+#include "hardware/structs/scb.h"
+
+#include "pico/mutex.h"
+#include "pico/assert.h"
+
+extern void __unhandled_user_irq(void);
+
+static inline irq_handler_t *get_vtable(void) {
+    return (irq_handler_t *) scb_hw->vtor;
+}
+
+static inline void *add_thumb_bit(void *addr) {
+    return (void *) (((uintptr_t) addr) | 0x1);
+}
+
+static inline void *remove_thumb_bit(void *addr) {
+    return (void *) (((uintptr_t) addr) & (uint)~0x1);
+}
+
+static void set_raw_irq_handler_and_unlock(uint num, irq_handler_t handler, uint32_t save) {
+    // update vtable (vtable_handler may be same or updated depending on cases, but we do it anyway for compactness)
+    get_vtable()[16 + num] = handler;
+    __dmb();
+    spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_IRQ), save);
+}
+
+void irq_set_enabled(uint num, bool enabled) {
+    check_irq_param(num);
+    irq_set_mask_enabled(1u << num, enabled);
+}
+
+bool irq_is_enabled(uint num) {
+    check_irq_param(num);
+    return 0 != ((1u << num) & *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)));
+}
+
+void irq_set_mask_enabled(uint32_t mask, bool enabled) {
+    if (enabled) {
+        // Clear pending before enable
+        // (if IRQ is actually asserted, it will immediately re-pend)
+        *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = mask;
+        *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)) = mask;
+    } else {
+        *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ICER_OFFSET)) = mask;
+    }
+}
+
+void irq_set_pending(uint num) {
+    check_irq_param(num);
+    *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISPR_OFFSET)) = 1u << num;
+}
+
+#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
+// limited by 8 bit relative links (and reality)
+static_assert(PICO_MAX_SHARED_IRQ_HANDLERS >= 1 && PICO_MAX_SHARED_IRQ_HANDLERS < 0x7f, "");
+
+// note these are not real functions, they are code fragments (i.e. don't call them)
+extern void irq_handler_chain_first_slot(void);
+extern void irq_handler_chain_remove_tail(void);
+
+extern struct irq_handler_chain_slot {
+    // first 3 half words are executable code (raw vtable handler points to one slot, and inst3 will jump to next
+    // in chain (or end of chain handler)
+    uint16_t inst1;
+    uint16_t inst2;
+    uint16_t inst3;
+    union {
+        // when a handler is removed while executing, it needs an extra instruction, which overwrites
+        // the link and the priority; this is ok because no one else is modifying the chain, as
+        // the chain is effectively core local, and the user code which might still need this link
+        // disable the IRQ in question before updating, which means we aren't executing!
+        struct {
+            int8_t link;
+            uint8_t priority;
+        };
+        uint16_t inst4;
+    };
+    irq_handler_t handler;
+} irq_handler_chain_slots[PICO_MAX_SHARED_IRQ_HANDLERS];
+
+static int8_t irq_hander_chain_free_slot_head;
+
+static inline bool is_shared_irq_raw_handler(irq_handler_t raw_handler) {
+    return (uintptr_t)raw_handler - (uintptr_t)irq_handler_chain_slots < sizeof(irq_handler_chain_slots);
+}
+#else
+#define is_shared_irq_raw_handler(h) false
+#endif
+
+irq_handler_t irq_get_vtable_handler(uint num) {
+    check_irq_param(num);
+    return get_vtable()[16 + num];
+}
+
+void irq_set_exclusive_handler(uint num, irq_handler_t handler) {
+    check_irq_param(num);
+#if !PICO_NO_RAM_VECTOR_TABLE
+    spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
+    uint32_t save = spin_lock_blocking(lock);
+    __unused irq_handler_t current = irq_get_vtable_handler(num);
+    hard_assert(current == __unhandled_user_irq || current == handler);
+    set_raw_irq_handler_and_unlock(num, handler, save);
+#else
+    panic_unsupported();
+#endif
+}
+
+irq_handler_t irq_get_exclusive_handler(uint num) {
+    check_irq_param(num);
+#if !PICO_NO_RAM_VECTOR_TABLE
+    spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
+    uint32_t save = spin_lock_blocking(lock);
+    irq_handler_t current = irq_get_vtable_handler(num);
+    spin_unlock(lock, save);
+    if (current == __unhandled_user_irq || is_shared_irq_raw_handler(current)) {
+        return NULL;
+    }
+    return current;
+#else
+    panic_unsupported();
+#endif
+}
+
+
+#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
+static uint16_t make_branch(uint16_t *from, void *to) {
+    uint32_t ui_from = (uint32_t)from;
+    uint32_t ui_to = (uint32_t)to;
+    uint32_t delta = (ui_to - ui_from - 4) / 2;
+    assert(!(delta >> 11u));
+    return (uint16_t)(0xe000 | (delta & 0x7ff));
+}
+
+static void insert_branch_and_link(uint16_t *from, void *to) {
+    uint32_t ui_from = (uint32_t)from;
+    uint32_t ui_to = (uint32_t)to;
+    uint32_t delta = (ui_to - ui_from - 4) / 2;
+    assert(!(delta >> 11u));
+    from[0] = (uint16_t)(0xf000 | ((delta >> 11u) & 0x7ffu));
+    from[1] = (uint16_t)(0xf800 | (delta & 0x7ffu));
+}
+
+static inline void *resolve_branch(uint16_t *inst) {
+    assert(0x1c == (*inst)>>11u);
+    int32_t i_addr = (*inst) << 21u;
+    i_addr /= (int32_t)(1u<<21u);
+    return inst + 2 + i_addr;
+}
+
+// GCC produces horrible code for subtraction of pointers here, and it was bugging me
+static inline int8_t slot_diff(struct irq_handler_chain_slot *to, struct irq_handler_chain_slot *from) {
+    static_assert(sizeof(struct irq_handler_chain_slot) == 12, "");
+    int32_t result = 0xaaaa;
+    // return (to - from);
+    // note this implementation has limited range, but is fine for plenty more than -128->127 result
+    asm (".syntax unified\n"
+         "subs %1, %2\n"
+         "adcs %1, %1\n" // * 2 (and + 1 if negative for rounding)
+         "muls %0, %1\n"
+         "lsrs %0, 20\n"
+         : "+l" (result), "+l" (to)
+         : "l" (from)
+         :
+         );
+    return (int8_t)result;
+}
+
+static inline int8_t get_slot_index(struct irq_handler_chain_slot *slot) {
+    return slot_diff(slot, irq_handler_chain_slots);
+}
+#endif
+
+void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority) {
+    check_irq_param(num);
+#if PICO_NO_RAM_VECTOR_TABLE
+    panic_unsupported()
+#elif PICO_DISABLE_SHARED_IRQ_HANDLERS
+    irq_set_exclusive_handler(num, handler);
+#else
+    spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
+    uint32_t save = spin_lock_blocking(lock);
+    hard_assert(irq_hander_chain_free_slot_head >= 0); // we must have a slot
+    struct irq_handler_chain_slot *slot = &irq_handler_chain_slots[irq_hander_chain_free_slot_head];
+    int8_t slot_index = irq_hander_chain_free_slot_head;
+    irq_hander_chain_free_slot_head = slot->link;
+    irq_handler_t vtable_handler = get_vtable()[16 + num];
+    if (!is_shared_irq_raw_handler(vtable_handler)) {
+        // start new chain
+        hard_assert(vtable_handler == __unhandled_user_irq);
+        struct irq_handler_chain_slot slot_data = {
+                .inst1 = 0xa100,                                                    // add r1, pc, #0
+                .inst2 = make_branch(&slot->inst2, irq_handler_chain_first_slot),   // b irq_handler_chain_first_slot
+                .inst3 = 0xbd00,                                                    // pop {pc}
+                .link = -1,
+                .priority = order_priority,
+                .handler = handler
+        };
+        *slot = slot_data;
+        vtable_handler = (irq_handler_t)add_thumb_bit(slot);
+    } else {
+        assert(!((((uintptr_t)vtable_handler) - ((uintptr_t)irq_handler_chain_slots) - 1)%sizeof(struct irq_handler_chain_slot)));
+        struct irq_handler_chain_slot *prev_slot = NULL;
+        struct irq_handler_chain_slot *existing_vtable_slot = remove_thumb_bit(vtable_handler);
+        struct irq_handler_chain_slot *cur_slot = existing_vtable_slot;
+        while (cur_slot->priority > order_priority) {
+            prev_slot = cur_slot;
+            if (cur_slot->link < 0) break;
+            cur_slot = &irq_handler_chain_slots[cur_slot->link];
+        }
+        if (prev_slot) {
+            // insert into chain
+            struct irq_handler_chain_slot slot_data = {
+                    .inst1 = 0x4801,                                                        // ldr r0, [pc, #4]
+                    .inst2 = 0x4780,                                                        // blx r0
+                    .inst3 = prev_slot->link >= 0 ?
+                            make_branch(&slot->inst3, resolve_branch(&prev_slot->inst3)) : // b next_slot
+                            0xbd00,                                                        // pop {pc}
+                    .link = prev_slot->link,
+                    .priority = order_priority,
+                    .handler = handler
+            };
+            // update code and data links
+            prev_slot->inst3 = make_branch(&prev_slot->inst3, slot),
+            prev_slot->link = slot_index;
+            *slot = slot_data;
+        } else {
+            // update with new chain head
+            struct irq_handler_chain_slot slot_data = {
+                    .inst1 = 0xa100,                                                    // add r1, pc, #0
+                    .inst2 = make_branch(&slot->inst2, irq_handler_chain_first_slot),   // b irq_handler_chain_first_slot
+                    .inst3 = make_branch(&slot->inst3, existing_vtable_slot),           // b existing_slot
+                    .link = get_slot_index(existing_vtable_slot),
+                    .priority = order_priority,
+                    .handler = handler
+            };
+            *slot = slot_data;
+            // fixup previous head slot
+            existing_vtable_slot->inst1 = 0x4801; // ldr r0, [pc, #4]
+            existing_vtable_slot->inst2 = 0x4780; // blx r0
+            vtable_handler = (irq_handler_t)add_thumb_bit(slot);
+        }
+    }
+    set_raw_irq_handler_and_unlock(num, vtable_handler, save);
+#endif
+}
+
+void irq_remove_handler(uint num, irq_handler_t handler) {
+#if !PICO_NO_RAM_VECTOR_TABLE
+    spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
+    uint32_t save = spin_lock_blocking(lock);
+    irq_handler_t vtable_handler = get_vtable()[16 + num];
+    if (vtable_handler != __unhandled_user_irq && vtable_handler != handler) {
+#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
+        if (is_shared_irq_raw_handler(vtable_handler)) {
+            // This is a bit tricky, as an executing IRQ handler doesn't take a lock.
+
+            // First thing to do is to disable the IRQ in question; that takes care of calls from user code.
+            // Note that a irq handler chain is local to our own core, so we don't need to worry about the other core
+            bool was_enabled = irq_is_enabled(num);
+            irq_set_enabled(num, false);
+            __dmb();
+
+            // It is possible we are being called while an IRQ for this chain is already in progress.
+            // The issue we have here is that we must not free a slot that is currently being executed, because
+            // inst3 is still to be executed, and inst3 might get overwritten if the slot is re-used.
+
+            // By disallowing other exceptions from removing an IRQ handler (which seems fair)
+            // we now only have to worry about removing a slot from a chain that is currently executing.
+
+            // Note we expect that the slot we are deleting is the one that is executing.
+            // In particular, bad things happen if the caller were to delete the handler in the chain
+            // before it. This is not an allowed use case though, and I can't imagine anyone wanting to in practice.
+            // Sadly this is not something we can detect.
+
+            uint exception = __get_current_exception();
+            hard_assert(!exception || exception == num + 16);
+
+            struct irq_handler_chain_slot *prev_slot = NULL;
+            struct irq_handler_chain_slot *existing_vtable_slot = remove_thumb_bit(vtable_handler);
+            struct irq_handler_chain_slot *to_free_slot = existing_vtable_slot;
+            int8_t to_free_slot_index = get_slot_index(to_free_slot);
+            while (to_free_slot->handler != handler) {
+                prev_slot = to_free_slot;
+                if (to_free_slot->link < 0) break;
+                to_free_slot = &irq_handler_chain_slots[to_free_slot->link];
+            }
+            if (to_free_slot->handler == handler) {
+                int8_t next_slot_index = to_free_slot->link;
+                if (next_slot_index >= 0) {
+                    // There is another slot in the chain, so copy that over us, so that our inst3 points at something valid
+                    // Note this only matters in the exception case anyway, and it that case, we will skip the next handler,
+                    // however in that case it's IRQ cause should immediately cause re-entry of the IRQ and the only side
+                    // effect will be that there was potentially brief out of priority order execution of the handlers
+                    struct irq_handler_chain_slot *next_slot = &irq_handler_chain_slots[next_slot_index];
+                    to_free_slot->handler = next_slot->handler;
+                    to_free_slot->priority = next_slot->priority;
+                    to_free_slot->link = next_slot->link;
+                    to_free_slot->inst3 = next_slot->link >= 0 ?
+                            make_branch(&to_free_slot->inst3, resolve_branch(&next_slot->inst3)) : // b mext_>slot->next_slot
+                            0xbd00;                                                                // pop {pc}
+
+                    // add old next slot back to free list
+                    next_slot->link = irq_hander_chain_free_slot_head;
+                    irq_hander_chain_free_slot_head = next_slot_index;
+                } else {
+                    // Slot being removed is at the end of the chain
+                    if (!exception) {
+                        // case when we're not in exception, we physically unlink now
+                        if (prev_slot) {
+                            // chain is not empty
+                            prev_slot->link = -1;
+                            prev_slot->inst3 = 0xbd00; // pop {pc}
+                        } else {
+                            // chain is not empty
+                            vtable_handler = __unhandled_user_irq;
+                        }
+                        // add slot back to free list
+                        to_free_slot->link = irq_hander_chain_free_slot_head;
+                        irq_hander_chain_free_slot_head = to_free_slot_index;
+                    } else {
+                        // since we are the last slot we know that our inst3 hasn't executed yet, so we change
+                        // it to bl to irq_handler_chain_remove_tail which will remove the slot.
+                        // NOTE THAT THIS TRASHES PRIORITY AND LINK SINCE THIS IS A 4 BYTE INSTRUCTION
+                        //      BUT THEY ARE NOT NEEDED NOW
+                        insert_branch_and_link(&to_free_slot->inst3, irq_handler_chain_remove_tail);
+                    }
+                }
+            } else {
+                assert(false); // not found
+            }
+            irq_set_enabled(num, was_enabled);
+        }
+#else
+        assert(false); // not found
+#endif
+    } else {
+        vtable_handler = __unhandled_user_irq;
+    }
+    set_raw_irq_handler_and_unlock(num, vtable_handler, save);
+#else
+    panic_unsupported();
+#endif
+}
+
+void irq_set_priority(uint num, uint8_t hardware_priority) {
+    check_irq_param(num);
+
+    // note that only 32 bit writes are supported
+    io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u));
+    *p = (*p & ~(0xffu << (8 * (num & 3u)))) | (((uint32_t) hardware_priority) << (8 * (num & 3u)));
+}
+
+uint irq_get_priority(uint num) {
+    check_irq_param(num);
+
+    // note that only 32 bit reads are supported
+    io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u));
+    return (uint8_t)(*p >> (8 * (num & 3u)));
+}
+
+#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
+// used by irq_handler_chain.S to remove the last link in a handler chain after it executes
+// note this must be called only with the last slot in a chain (and during the exception)
+void irq_add_tail_to_free_list(struct irq_handler_chain_slot *slot) {
+    irq_handler_t slot_handler = (irq_handler_t) add_thumb_bit(slot);
+    assert(is_shared_irq_raw_handler(slot_handler));
+
+    uint exception = __get_current_exception();
+    assert(exception);
+    spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
+    uint32_t save = spin_lock_blocking(lock);
+    int8_t slot_index = get_slot_index(slot);
+    if (slot_handler == get_vtable()[exception]) {
+        get_vtable()[exception] = __unhandled_user_irq;
+    } else {
+        bool __unused found = false;
+        // need to find who points at the slot and update it
+        for(uint i=0;i<count_of(irq_handler_chain_slots);i++) {
+            if (irq_handler_chain_slots[i].link == slot_index) {
+                irq_handler_chain_slots[i].link = -1;
+                irq_handler_chain_slots[i].inst3 = 0xbd00; // pop {pc}
+                found = true;
+                break;
+            }
+        }
+        assert(found);
+    }
+    // add slot to free list
+    slot->link = irq_hander_chain_free_slot_head;
+    irq_hander_chain_free_slot_head = slot_index;
+    spin_unlock(lock, save);
+}
+#endif
+
+void irq_init_priorities() {
+#if PICO_DEFAULT_IRQ_PRIORITY != 0
+    static_assert(!(NUM_IRQS & 3), "");
+    uint32_t prio4 = (PICO_DEFAULT_IRQ_PRIORITY & 0xff) * 0x1010101u;
+    io_rw_32 * p = (io_rw_32 *)(PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET);
+    for (uint i = 0; i < NUM_IRQS / 4; i++) {
+        *p++ = prio4;
+    }
+#endif
+}
diff --git a/src/rp2_common/hardware_irq/irq_handler_chain.S b/src/rp2_common/hardware_irq/irq_handler_chain.S
new file mode 100644
index 0000000..7d7be7d
--- /dev/null
+++ b/src/rp2_common/hardware_irq/irq_handler_chain.S
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+#include "hardware/irq.h"
+
+#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.data
+.align 2
+
+.global irq_handler_chain_slots
+
+.global irq_handler_chain_first_slot
+.global irq_handler_chain_remove_tail
+
+//
+// These Slots make up the code and structure of the handler chains; the only external information are the VTABLE entries
+// (obviously one set per core) and a free list head. Each individual handler chain starts with the VTABLE entry I
+// pointing at the address of slot S (with thumb bit set). Thus each slot which is part of a chain is executble.
+//
+// The execution jumps (via branch instruction) from one slot to the other, then jumps to the end of chain handler.
+// The entirety of the state needed to traverse the chain is contained within the slots of the chain, which is why
+// a VTABLE entry is all that is needed per chain (rather than requiring a separarte set of head pointers)
+//
+
+irq_handler_chain_slots:
+.set next_slot_number, 1
+.rept PICO_MAX_SHARED_IRQ_HANDLERS
+    // a slot is executable and is always 3 instructions long.
+    .hword 0    // inst1 (either: ldr r0, [pc, #4]    or for the FIRST slot : add r1, pc, #0                 )
+    .hword 0    // inst2 (        blx r0                                      b irq_handler_chain_first_slot )
+
+    .hword 0    // inst3 (either: b next_slot         or for the LAST         pop {pc}                       )
+
+    // next is a single byte index of next slot in chain (or -1 to end)
+.if next_slot_number == PICO_MAX_SHARED_IRQ_HANDLERS
+    .byte 0xff
+.else
+    .byte next_slot_number
+.endif
+    // next is the 8 bit unsigned priority
+    .byte 0x00
+1:
+    // and finally the handler function pointer
+    .word 0x00000000
+    .set next_slot_number, next_slot_number + 1
+.endr
+
+irq_handler_chain_first_slot:
+    push {lr}
+    ldr  r0, [r1, #4]
+    adds r1, #1
+    mov  lr, r1
+    bx   r0
+irq_handler_chain_remove_tail:
+    mov  r0, lr
+    subs r0, #9
+    ldr  r1, =irq_add_tail_to_free_list
+    blx  r1
+    pop  {pc}
+
+
+#endif
diff --git a/src/rp2_common/hardware_pio/CMakeLists.txt b/src/rp2_common/hardware_pio/CMakeLists.txt
new file mode 100644
index 0000000..ad01869
--- /dev/null
+++ b/src/rp2_common/hardware_pio/CMakeLists.txt
@@ -0,0 +1,4 @@
+pico_simple_hardware_target(pio)
+
+# additional libraries
+target_link_libraries(hardware_pio INTERFACE hardware_gpio hardware_claim)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_pio/include/hardware/pio.h b/src/rp2_common/hardware_pio/include/hardware/pio.h
new file mode 100644
index 0000000..d2377ac
--- /dev/null
+++ b/src/rp2_common/hardware_pio/include/hardware/pio.h
@@ -0,0 +1,1311 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_PIO_H_
+#define _HARDWARE_PIO_H_
+
+#include "pico.h"
+#include "hardware/address_mapped.h"
+#include "hardware/structs/pio.h"
+#include "hardware/gpio.h"
+#include "hardware/regs/dreq.h"
+#include "hardware/pio_instructions.h"
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO, Enable/disable assertions in the PIO module, type=bool, default=0, group=hardware_pio
+#ifndef PARAM_ASSERTIONS_ENABLED_PIO
+#define PARAM_ASSERTIONS_ENABLED_PIO 0
+#endif
+
+/** \file hardware/pio.h
+ *  \defgroup hardware_pio hardware_pio
+ *
+ * Programmable I/O (PIO) API
+ *
+ * A programmable input/output block (PIO) is a versatile hardware interface which
+ * can support a number of different IO standards. There are two PIO blocks in the RP2040.
+ *
+ * Each PIO is programmable in the same sense as a processor: the four state machines independently
+ * execute short, sequential programs, to manipulate GPIOs and transfer data. Unlike a general
+ * purpose processor, PIO state machines are highly specialised for IO, with a focus on determinism,
+ * precise timing, and close integration with fixed-function hardware. Each state machine is equipped
+ * with:
+ *  * Two 32-bit shift registers – either direction, any shift count
+ *  * Two 32-bit scratch registers
+ *  * 4×32 bit bus FIFO in each direction (TX/RX), reconfigurable as 8×32 in a single direction
+ *  * Fractional clock divider (16 integer, 8 fractional bits)
+ *  * Flexible GPIO mapping
+ *  * DMA interface, sustained throughput up to 1 word per clock from system DMA
+ *  * IRQ flag set/clear/status
+ *
+ * Full details of the PIO can be found in the RP2040 datasheet.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static_assert(PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB == PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB + 1, "");
+
+/** \brief FIFO join states
+ *  \ingroup hardware_pio
+ */
+enum pio_fifo_join {
+    PIO_FIFO_JOIN_NONE = 0,
+    PIO_FIFO_JOIN_TX = 1,
+    PIO_FIFO_JOIN_RX = 2,
+};
+
+/** \brief MOV status types
+ *  \ingroup hardware_pio
+ */
+enum pio_mov_status_type {
+    STATUS_TX_LESSTHAN = 0,
+    STATUS_RX_LESSTHAN = 1
+};
+
+typedef pio_hw_t *PIO;
+
+/** Identifier for the first (PIO 0) hardware PIO instance (for use in PIO functions).
+ *
+ * e.g. pio_gpio_init(pio0, 5)
+ *
+ *  \ingroup hardware_pio
+ * @{
+ */
+#define pio0 pio0_hw
+/** @} */
+
+/** Identifier for the second (PIO 1) hardware PIO instance (for use in PIO functions).
+ *
+ * e.g. pio_gpio_init(pio1, 5)
+ *
+ *  \ingroup hardware_pio
+ * @{
+ */
+#define pio1 pio1_hw
+/** @} */
+
+/** \brief PIO state machine configuration
+ *  \defgroup sm_config sm_config
+ *  \ingroup hardware_pio
+ *
+ * A PIO block needs to be configured, these functions provide helpers to set up configuration
+ * structures. See \ref pio_sm_set_config
+ *
+ */
+
+/** \brief PIO Configuration structure
+ *  \ingroup sm_config
+ */
+typedef struct {
+    uint32_t clkdiv;
+    uint32_t execctrl;
+    uint32_t shiftctrl;
+    uint32_t pinctrl;
+} pio_sm_config;
+
+static inline void check_sm_param(__unused uint sm) {
+    valid_params_if(PIO, sm < NUM_PIO_STATE_MACHINES);
+}
+
+static inline void check_sm_mask(__unused uint mask) {
+    valid_params_if(PIO, mask < (1u << NUM_PIO_STATE_MACHINES));
+}
+
+
+static inline void check_pio_param(__unused PIO pio) {
+    valid_params_if(PIO, pio == pio0 || pio == pio1);
+}
+
+/*! \brief Set the 'out' pins in a state machine configuration
+ *  \ingroup sm_config
+ *
+ * Can overlap with the 'in', 'set' and 'sideset' pins
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param out_base 0-31 First pin to set as output
+ * \param out_count 0-32 Number of pins to set.
+ */
+static inline void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint out_count) {
+    valid_params_if(PIO, out_base < 32);
+    valid_params_if(PIO, out_count <= 32);
+    c->pinctrl = (c->pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) |
+                 (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) |
+                 (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB);
+}
+
+/*! \brief Set the 'set' pins in a state machine configuration
+ *  \ingroup sm_config
+ *
+ * Can overlap with the 'in', 'out' and 'sideset' pins
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param set_base 0-31 First pin to set as
+ * \param set_count 0-5 Number of pins to set.
+ */
+static inline void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint set_count) {
+    valid_params_if(PIO, set_base < 32);
+    valid_params_if(PIO, set_count <= 5);
+    c->pinctrl = (c->pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) |
+                 (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) |
+                 (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB);
+}
+
+/*! \brief Set the 'in' pins in a state machine configuration
+ *  \ingroup sm_config
+ *
+ * Can overlap with the 'out', ''set' and 'sideset' pins
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param in_base 0-31 First pin to use as input
+ */
+static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) {
+    valid_params_if(PIO, in_base < 32);
+    c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) |
+                 (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB);
+}
+
+/*! \brief Set the 'sideset' pins in a state machine configuration
+ *  \ingroup sm_config
+ *
+ * Can overlap with the 'in', 'out' and 'set' pins
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param sideset_base 0-31 base pin for 'side set'
+ */
+static inline void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_base) {
+    valid_params_if(PIO, sideset_base < 32);
+    c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) |
+                 (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB);
+}
+
+/*! \brief Set the 'sideset' options in a state machine configuration
+ *  \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param bit_count Number of bits to steal from delay field in the instruction for use of side set (max 5)
+ * \param optional True if the topmost side set bit is used as a flag for whether to apply side set on that instruction
+ * \param pindirs True if the side set affects pin directions rather than values
+ */
+static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool optional, bool pindirs) {
+    valid_params_if(PIO, bit_count <= 5);
+    valid_params_if(PIO, !optional || bit_count >= 1);
+    c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_COUNT_BITS) |
+                 (bit_count << PIO_SM0_PINCTRL_SIDESET_COUNT_LSB);
+
+    c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_SIDE_EN_BITS | PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS)) |
+                  (bool_to_bit(optional) << PIO_SM0_EXECCTRL_SIDE_EN_LSB) |
+                  (bool_to_bit(pindirs) << PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB);
+}
+
+/*! \brief Set the state machine clock divider (from integer and fractional parts - 16:8) in a state machine configuration
+ *  \ingroup sm_config
+ *
+ * The clock divider can slow the state machine's execution to some rate below
+ * the system clock frequency, by enabling the state machine on some cycles
+ * but not on others, in a regular pattern. This can be used to generate e.g.
+ * a given UART baud rate. See the datasheet for further detail.
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param div_int Integer part of the divisor
+ * \param div_frac Fractional part in 1/256ths
+ * \sa sm_config_set_clkdiv()
+ */
+static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac) {
+    c->clkdiv =
+            (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) |
+            (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB);
+}
+
+static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int, uint8_t *div_frac) {
+    valid_params_if(PIO, div >= 1 && div <= 65536);
+    *div_int = (uint16_t)div;
+    if (*div_int == 0) {
+        *div_frac = 0;
+    } else {
+        *div_frac = (uint8_t)((div - (float)*div_int) * (1u << 8u));
+    }
+}
+
+/*! \brief Set the state machine clock divider (from a floating point value) in a state machine configuration
+ *  \ingroup sm_config
+ *
+ * The clock divider slows the state machine's execution by masking the
+ * system clock on some cycles, in a repeating pattern, so that the state
+ * machine does not advance. Effectively this produces a slower clock for the
+ * state machine to run from, which can be used to generate e.g. a particular
+ * UART baud rate. See the datasheet for further detail.
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param div The fractional divisor to be set. 1 for full speed. An integer clock divisor of n
+ *  will cause the state machine to run 1 cycle in every n.
+ *  Note that for small n, the jitter introduced by a fractional divider (e.g. 2.5) may be unacceptable
+ *  although it will depend on the use case.
+ */
+static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) {
+    uint16_t div_int;
+    uint8_t div_frac;
+    pio_calculate_clkdiv_from_float(div, &div_int, &div_frac);
+    sm_config_set_clkdiv_int_frac(c, div_int, div_frac);
+}
+
+/*! \brief Set the wrap addresses in a state machine configuration
+ *  \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param wrap_target the instruction memory address to wrap to
+ * \param wrap        the instruction memory address after which to set the program counter to wrap_target
+ *                    if the instruction does not itself update the program_counter
+ */
+static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint wrap) {
+    valid_params_if(PIO, wrap < PIO_INSTRUCTION_COUNT);
+    valid_params_if(PIO, wrap_target < PIO_INSTRUCTION_COUNT);
+    c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) |
+                  (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) |
+                  (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB);
+}
+
+/*! \brief Set the 'jmp' pin in a state machine configuration
+ *  \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param pin The raw GPIO pin number to use as the source for a `jmp pin` instruction
+ */
+static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) {
+    valid_params_if(PIO, pin < 32);
+    c->execctrl = (c->execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS) |
+                  (pin << PIO_SM0_EXECCTRL_JMP_PIN_LSB);
+}
+
+/*! \brief Setup 'in' shifting parameters in a state machine configuration
+ *  \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param shift_right true to shift ISR to right, false to shift ISR to left
+ * \param autopush whether autopush is enabled
+ * \param push_threshold threshold in bits to shift in before auto/conditional re-pushing of the ISR
+ */
+static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold) {
+    valid_params_if(PIO, push_threshold <= 32);
+    c->shiftctrl = (c->shiftctrl &
+                    ~(PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS |
+                      PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS |
+                      PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS)) |
+                   (bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB) |
+                   (bool_to_bit(autopush) << PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB) |
+                   ((push_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB);
+}
+
+/*! \brief Setup 'out' shifting parameters in a state machine configuration
+ *  \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param shift_right true to shift OSR to right, false to shift OSR to left
+ * \param autopull whether autopull is enabled
+ * \param pull_threshold threshold in bits to shift out before auto/conditional re-pulling of the OSR
+ */
+static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold) {
+    valid_params_if(PIO, pull_threshold <= 32);
+    c->shiftctrl = (c->shiftctrl &
+                    ~(PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS |
+                      PIO_SM0_SHIFTCTRL_AUTOPULL_BITS |
+                      PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS)) |
+                   (bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB) |
+                   (bool_to_bit(autopull) << PIO_SM0_SHIFTCTRL_AUTOPULL_LSB) |
+                   ((pull_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB);
+}
+
+/*! \brief Setup the FIFO joining in a state machine configuration
+ *  \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param join Specifies the join type. \see enum pio_fifo_join
+ */
+static inline void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join join) {
+    valid_params_if(PIO, join == PIO_FIFO_JOIN_NONE || join == PIO_FIFO_JOIN_TX || join == PIO_FIFO_JOIN_RX);
+    c->shiftctrl = (c->shiftctrl & (uint)~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS)) |
+                   (((uint)join) << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB);
+}
+
+/*! \brief Set special 'out' operations in a state machine configuration
+ *  \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param sticky to enable 'sticky' output (i.e. re-asserting most recent OUT/SET pin values on subsequent cycles)
+ * \param has_enable_pin true to enable auxiliary OUT enable pin
+ * \param enable_pin_index pin index for auxiliary OUT enable
+ */
+static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, uint enable_pin_index) {
+    c->execctrl = (c->execctrl &
+                   (uint)~(PIO_SM0_EXECCTRL_OUT_STICKY_BITS | PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS |
+                     PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS)) |
+                  (bool_to_bit(sticky) << PIO_SM0_EXECCTRL_OUT_STICKY_LSB) |
+                  (bool_to_bit(has_enable_pin) << PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB) |
+                  ((enable_pin_index << PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB) & PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS);
+}
+
+/*! \brief Set source for 'mov status' in a state machine configuration
+ *  \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param status_sel the status operation selector. \see enum pio_mov_status_type
+ * \param status_n parameter for the mov status operation (currently a bit count)
+ */
+static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n) {
+    valid_params_if(PIO, status_sel == STATUS_TX_LESSTHAN || status_sel == STATUS_RX_LESSTHAN);
+    c->execctrl = (c->execctrl
+                  & ~(PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PIO_SM0_EXECCTRL_STATUS_N_BITS))
+                  | ((((uint)status_sel) << PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & PIO_SM0_EXECCTRL_STATUS_SEL_BITS)
+                  | ((status_n << PIO_SM0_EXECCTRL_STATUS_N_LSB) & PIO_SM0_EXECCTRL_STATUS_N_BITS);
+}
+
+
+/*! \brief  Get the default state machine configuration
+ *  \ingroup sm_config
+ *
+ * Setting | Default
+ * --------|--------
+ * Out Pins | 32 starting at 0
+ * Set Pins | 0 starting at 0
+ * In Pins (base) | 0
+ * Side Set Pins (base) | 0
+ * Side Set | disabled
+ * Wrap | wrap=31, wrap_to=0
+ * In Shift | shift_direction=right, autopush=false, push_thrshold=32
+ * Out Shift | shift_direction=right, autopull=false, pull_thrshold=32
+ * Jmp Pin | 0
+ * Out Special | sticky=false, has_enable_pin=false, enable_pin_index=0
+ * Mov Status | status_sel=STATUS_TX_LESSTHAN, n=0
+ *
+ * \return the default state machine configuration which can then be modified.
+ */
+static inline pio_sm_config pio_get_default_sm_config(void) {
+    pio_sm_config c = {0, 0, 0, 0};
+    sm_config_set_clkdiv_int_frac(&c, 1, 0);
+    sm_config_set_wrap(&c, 0, 31);
+    sm_config_set_in_shift(&c, true, false, 32);
+    sm_config_set_out_shift(&c, true, false, 32);
+    return c;
+}
+
+/*! \brief Apply a state machine configuration to a state machine
+ *  \ingroup hardware_pio
+ *
+ * \param pio Handle to PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param config the configuration to apply
+*/
+static inline void pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    pio->sm[sm].clkdiv = config->clkdiv;
+    pio->sm[sm].execctrl = config->execctrl;
+    pio->sm[sm].shiftctrl = config->shiftctrl;
+    pio->sm[sm].pinctrl = config->pinctrl;
+}
+
+/*! \brief Return the instance number of a PIO instance
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \return the PIO instance number (either 0 or 1)
+ */
+static inline uint pio_get_index(PIO pio) {
+    check_pio_param(pio);
+    return pio == pio1 ? 1 : 0;
+}
+
+/*! \brief Setup the function select for a GPIO to use output from the given PIO instance
+ *  \ingroup hardware_pio
+ *
+ * PIO appears as an alternate function in the GPIO muxing, just like an SPI
+ * or UART. This function configures that multiplexing to connect a given PIO
+ * instance to a GPIO. Note that this is not necessary for a state machine to
+ * be able to read the *input* value from a GPIO, but only for it to set the
+ * output value or output enable.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param pin the GPIO pin whose function select to set
+ */
+static inline void pio_gpio_init(PIO pio, uint pin) {
+    check_pio_param(pio);
+    valid_params_if(PIO, pin < 32);
+    gpio_set_function(pin, pio == pio0 ? GPIO_FUNC_PIO0 : GPIO_FUNC_PIO1);
+}
+
+/*! \brief Return the DREQ to use for pacing transfers to/from a particular state machine FIFO
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param is_tx true for sending data to the state machine, false for receiving data from the state machine
+ */
+static inline uint pio_get_dreq(PIO pio, uint sm, bool is_tx) {
+    static_assert(DREQ_PIO0_TX1 == DREQ_PIO0_TX0 + 1, "");
+    static_assert(DREQ_PIO0_TX2 == DREQ_PIO0_TX0 + 2, "");
+    static_assert(DREQ_PIO0_TX3 == DREQ_PIO0_TX0 + 3, "");
+    static_assert(DREQ_PIO0_RX0 == DREQ_PIO0_TX0 + NUM_PIO_STATE_MACHINES, "");
+    static_assert(DREQ_PIO1_RX0 == DREQ_PIO1_TX0 + NUM_PIO_STATE_MACHINES, "");
+    check_pio_param(pio);
+    check_sm_param(sm);
+    return sm + (is_tx ? 0 : NUM_PIO_STATE_MACHINES) + (pio == pio0 ? DREQ_PIO0_TX0 : DREQ_PIO1_TX0);
+}
+
+typedef struct pio_program {
+    const uint16_t *instructions;
+    uint8_t length;
+    int8_t origin; // required instruction memory origin or -1
+} __packed pio_program_t;
+
+/*! \brief Determine whether the given program can (at the time of the call) be loaded onto the PIO instance
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param program the program definition
+ * \return true if the program can be loaded; false if there is not suitable space in the instruction memory
+ */
+bool pio_can_add_program(PIO pio, const pio_program_t *program);
+
+/*! \brief Determine whether the given program can (at the time of the call) be loaded onto the PIO instance starting at a particular location
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param program the program definition
+ * \param offset the instruction memory offset wanted for the start of the program
+ * \return true if the program can be loaded at that location; false if there is not space in the instruction memory
+ */
+bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset);
+
+/*! \brief Attempt to load the program, panicking if not possible
+ *  \ingroup hardware_pio
+ *
+ * \see pio_can_add_program() if you need to check whether the program can be loaded
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param program the program definition
+ * \return the instruction memory offset the program is loaded at
+ */
+uint pio_add_program(PIO pio, const pio_program_t *program);
+
+/*! \brief Attempt to load the program at the specified instruction memory offset, panicking if not possible
+ *  \ingroup hardware_pio
+ *
+ * \see pio_can_add_program_at_offset() if you need to check whether the program can be loaded
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param program the program definition
+ * \param offset the instruction memory offset wanted for the start of the program
+ */
+void pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset);
+
+/*! \brief Remove a program from a PIO instance's instruction memory
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param program the program definition
+ * \param loaded_offset the loaded offset returned when the program was added
+ */
+void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset);
+
+/*! \brief Clears all of a PIO instance's instruction memory
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ */
+void pio_clear_instruction_memory(PIO pio);
+
+/*! \brief Resets the state machine to a consistent state, and configures it
+ *  \ingroup hardware_pio
+ *
+ * This method:
+ * - Disables the state machine (if running)
+ * - Clears the FIFOs
+ * - Applies the configuration specified by 'config'
+ * - Resets any internal state e.g. shift counters
+ * - Jumps to the initial program location given by 'initial_pc'
+ *
+ * The state machine is left disabled on return from this call.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param initial_pc the initial program memory offset to run from
+ * \param config the configuration to apply (or NULL to apply defaults)
+ */
+void pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config);
+
+/*! \brief Enable or disable a PIO state machine
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param enabled true to enable the state machine; false to disable
+ */
+static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    pio->ctrl = (pio->ctrl & ~(1u << sm)) | (bool_to_bit(enabled) << sm);
+}
+
+/*! \brief Enable or disable multiple PIO state machines
+ *  \ingroup hardware_pio
+ *
+ * Note that this method just sets the enabled state of the state machine;
+ * if now enabled they continue exactly from where they left off.
+ *
+ * \see pio_enable_sm_mask_in_sync() if you wish to enable multiple state machines
+ * and ensure their clock dividers are in sync.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param mask bit mask of state machine indexes to modify the enabled state of
+ * \param enabled true to enable the state machines; false to disable
+ */
+static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) {
+    check_pio_param(pio);
+    check_sm_mask(mask);
+    pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u);
+}
+
+/*! \brief Restart a state machine with a known state
+ *  \ingroup hardware_pio
+ *
+ * This method clears the ISR, shift counters, clock divider counter
+ * pin write flags, delay counter, latched EXEC instruction, and IRQ wait condition.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ */
+static inline void pio_sm_restart(PIO pio, uint sm) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    pio->ctrl |= 1u << (PIO_CTRL_SM_RESTART_LSB + sm);
+}
+
+/*! \brief Restart multiple state machine with a known state
+ *  \ingroup hardware_pio
+ *
+ * This method clears the ISR, shift counters, clock divider counter
+ * pin write flags, delay counter, latched EXEC instruction, and IRQ wait condition.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param mask bit mask of state machine indexes to modify the enabled state of
+ */
+static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) {
+    check_pio_param(pio);
+    check_sm_mask(mask);
+    pio->ctrl |= (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS;
+}
+
+/*! \brief Restart a state machine's clock divider from a phase of 0
+ *  \ingroup hardware_pio
+ *
+ * Each state machine's clock divider is a free-running piece of hardware,
+ * that generates a pattern of clock enable pulses for the state machine,
+ * based *only* on the configured integer/fractional divisor. The pattern of
+ * running/halted cycles slows the state machine's execution to some
+ * controlled rate.
+ *
+ * This function clears the divider's integer and fractional phase
+ * accumulators so that it restarts this pattern from the beginning. It is
+ * called automatically by pio_sm_init() but can also be called at a later
+ * time, when you enable the state machine, to ensure precisely consistent
+ * timing each time you load and run a given PIO program.
+ *
+ * More commonly this hardware mechanism is used to synchronise the execution
+ * clocks of multiple state machines -- see pio_clkdiv_restart_sm_mask().
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ */
+static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    pio->ctrl |= 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm);
+}
+
+/*! \brief Restart multiple state machines' clock dividers from a phase of 0.
+ *  \ingroup hardware_pio
+ *
+ * Each state machine's clock divider is a free-running piece of hardware,
+ * that generates a pattern of clock enable pulses for the state machine,
+ * based *only* on the configured integer/fractional divisor. The pattern of
+ * running/halted cycles slows the state machine's execution to some
+ * controlled rate.
+ *
+ * This function simultaneously clears the integer and fractional phase
+ * accumulators of multiple state machines' clock dividers. If these state
+ * machines all have the same integer and fractional divisors configured,
+ * their clock dividers will run in precise deterministic lockstep from this
+ * point.
+ *
+ * With their execution clocks synchronised in this way, it is then safe to
+ * e.g. have multiple state machines performing a 'wait irq' on the same flag,
+ * and all clear it on the same cycle.
+ *
+ * Also note that this function can be called whilst state machines are
+ * running (e.g. if you have just changed the clock divisors of some state
+ * machines and wish to resynchronise them), and that disabling a state
+ * machine does not halt its clock divider: that is, if multiple state
+ * machines have their clocks synchronised, you can safely disable and
+ * reenable one of the state machines without losing synchronisation.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param mask bit mask of state machine indexes to modify the enabled state of
+ */
+static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) {
+    check_pio_param(pio);
+    check_sm_mask(mask);
+    pio->ctrl |= (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS;
+}
+
+/*! \brief Enable multiple PIO state machines synchronizing their clock dividers
+ *  \ingroup hardware_pio
+ *
+ * This is equivalent to calling both pio_set_sm_mask_enabled() and
+ * pio_clkdiv_restart_sm_mask() on the *same* clock cycle. All state machines
+ * specified by 'mask' are started simultaneously and, assuming they have the
+ * same clock divisors, their divided clocks will stay precisely synchronised.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param mask bit mask of state machine indexes to modify the enabled state of
+ */
+static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) {
+    check_pio_param(pio);
+    check_sm_mask(mask);
+    pio->ctrl |= ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) |
+                 ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS);
+}
+
+/*! \brief PIO interrupt source numbers for pio related IRQs
+ * \ingroup hardware_pio
+ */
+enum pio_interrupt_source {
+    pis_interrupt0 = PIO_INTR_SM0_LSB,
+    pis_interrupt1 = PIO_INTR_SM1_LSB,
+    pis_interrupt2 = PIO_INTR_SM2_LSB,
+    pis_interrupt3 = PIO_INTR_SM3_LSB,
+    pis_sm0_tx_fifo_not_full = PIO_INTR_SM0_TXNFULL_LSB,
+    pis_sm1_tx_fifo_not_full = PIO_INTR_SM1_TXNFULL_LSB,
+    pis_sm2_tx_fifo_not_full = PIO_INTR_SM2_TXNFULL_LSB,
+    pis_sm3_tx_fifo_not_full = PIO_INTR_SM3_TXNFULL_LSB,
+    pis_sm0_rx_fifo_not_empty = PIO_INTR_SM0_RXNEMPTY_LSB,
+    pis_sm1_rx_fifo_not_empty = PIO_INTR_SM1_RXNEMPTY_LSB,
+    pis_sm2_rx_fifo_not_empty = PIO_INTR_SM2_RXNEMPTY_LSB,
+    pis_sm3_rx_fifo_not_empty = PIO_INTR_SM3_RXNEMPTY_LSB,
+};
+
+/*! \brief  Enable/Disable a single source on a PIO's IRQ 0
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param source the source number (see \ref pio_interrupt_source)
+ * \param enabled true to enable IRQ 0 for the source, false to disable.
+ */
+static inline void pio_set_irq0_source_enabled(PIO pio, enum pio_interrupt_source source, bool enabled) {
+    check_pio_param(pio);
+    invalid_params_if(PIO, source >= 12);
+    if (enabled)
+        hw_set_bits(&pio->inte0, 1u << source);
+    else
+        hw_clear_bits(&pio->inte0, 1u << source);
+}
+
+/*! \brief  Enable/Disable a single source on a PIO's IRQ 1
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param source the source number (see \ref pio_interrupt_source)
+ * \param enabled true to enable IRQ 0 for the source, false to disable.
+ */
+static inline void pio_set_irq1_source_enabled(PIO pio, enum pio_interrupt_source source, bool enabled) {
+    check_pio_param(pio);
+    invalid_params_if(PIO, source >= 12);
+    if (enabled)
+        hw_set_bits(&pio->inte1, 1u << source);
+    else
+        hw_clear_bits(&pio->inte1, 1u << source);
+}
+
+/*! \brief  Enable/Disable multiple sources on a PIO's IRQ 0
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect
+ * \param enabled true to enable all the sources specified in the mask on IRQ 0, false to disable all the sources specified in the mask on IRQ 0
+ */
+static inline void pio_set_irq0_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) {
+    check_pio_param(pio);
+    invalid_params_if(PIO, source_mask > PIO_INTR_BITS);
+    if (enabled) {
+        hw_set_bits(&pio->inte0, source_mask);
+    } else {
+        hw_clear_bits(&pio->inte0, source_mask);
+    }
+}
+
+/*! \brief  Enable/Disable multiple sources on a PIO's IRQ 1
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect
+ * \param enabled true to enable all the sources specified in the mask on IRQ 1, false to disable all the source specified in the mask on IRQ 1
+ */
+static inline void pio_set_irq1_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) {
+    check_pio_param(pio);
+    invalid_params_if(PIO, source_mask > PIO_INTR_BITS);
+    if (enabled) {
+        hw_set_bits(&pio->inte1, source_mask);
+    } else {
+        hw_clear_bits(&pio->inte1, source_mask);
+    }
+}
+
+/*! \brief  Enable/Disable a single source on a PIO's specified (0/1) IRQ index
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param irq_index the IRQ index; either 0 or 1
+ * \param source the source number (see \ref pio_interrupt_source)
+ * \param enabled true to enable the source on the specified IRQ, false to disable.
+ */
+static inline void pio_set_irqn_source_enabled(PIO pio, uint irq_index, enum pio_interrupt_source source, bool enabled) {
+    invalid_params_if(PIO, irq_index > 1);
+    if (irq_index) {
+        pio_set_irq1_source_enabled(pio, source, enabled);
+    } else {
+        pio_set_irq0_source_enabled(pio, source, enabled);
+    }
+}
+
+/*! \brief  Enable/Disable multiple sources on a PIO's specified (0/1) IRQ index
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param irq_index the IRQ index; either 0 or 1
+ * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect
+ * \param enabled true to enable all the sources specified in the mask on the specified IRQ, false to disable all the sources specified in the mask on the specified IRQ
+ */
+static inline void pio_set_irqn_source_mask_enabled(PIO pio, uint irq_index, uint32_t source_mask, bool enabled) {
+    invalid_params_if(PIO, irq_index > 1);
+    if (irq_index) {
+        pio_set_irq0_source_mask_enabled(pio, source_mask, enabled);
+    } else {
+        pio_set_irq1_source_mask_enabled(pio, source_mask, enabled);
+    }
+}
+
+/*! \brief  Determine if a particular PIO interrupt is set
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param pio_interrupt_num the PIO interrupt number 0-7
+ * \return true if corresponding PIO interrupt is currently set
+ */
+static inline bool pio_interrupt_get(PIO pio, uint pio_interrupt_num) {
+    check_pio_param(pio);
+    invalid_params_if(PIO, pio_interrupt_num >= 8);
+    return pio->irq & (1u << pio_interrupt_num);
+}
+
+/*! \brief  Clear a particular PIO interrupt
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param pio_interrupt_num the PIO interrupt number 0-7
+ */
+static inline void pio_interrupt_clear(PIO pio, uint pio_interrupt_num) {
+    check_pio_param(pio);
+    invalid_params_if(PIO, pio_interrupt_num >= 8);
+    hw_set_bits(&pio->irq, (1u << pio_interrupt_num));
+}
+
+/*! \brief Return the current program counter for a state machine
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return the program counter
+ */
+static inline uint8_t pio_sm_get_pc(PIO pio, uint sm) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    return (uint8_t) pio->sm[sm].addr;
+}
+
+/*! \brief Immediately execute an instruction on a state machine
+ *  \ingroup hardware_pio
+ *
+ * This instruction is executed instead of the next instruction in the normal control flow on the state machine.
+ * Subsequent calls to this method replace the previous executed
+ * instruction if it is still running. \see pio_sm_is_exec_stalled() to see if an executed instruction
+ * is still running (i.e. it is stalled on some condition)
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param instr the encoded PIO instruction
+ */
+inline static void pio_sm_exec(PIO pio, uint sm, uint instr) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    pio->sm[sm].instr = instr;
+}
+
+/*! \brief Determine if an instruction set by pio_sm_exec() is stalled executing
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return true if the executed instruction is still running (stalled)
+ */
+static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    return !!(pio->sm[sm].execctrl & PIO_SM0_EXECCTRL_EXEC_STALLED_BITS);
+}
+
+/*! \brief Immediately execute an instruction on a state machine and wait for it to complete
+ *  \ingroup hardware_pio
+ *
+ * This instruction is executed instead of the next instruction in the normal control flow on the state machine.
+ * Subsequent calls to this method replace the previous executed
+ * instruction if it is still running. \see pio_sm_is_exec_stalled() to see if an executed instruction
+ * is still running (i.e. it is stalled on some condition)
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param instr the encoded PIO instruction
+ */
+static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    pio_sm_exec(pio, sm, instr);
+    while (pio_sm_is_exec_stalled(pio, sm)) tight_loop_contents();
+}
+
+/*! \brief Set the current wrap configuration for a state machine
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param wrap_target the instruction memory address to wrap to
+ * \param wrap        the instruction memory address after which to set the program counter to wrap_target
+ *                    if the instruction does not itself update the program_counter
+ */
+static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    valid_params_if(PIO, wrap < PIO_INSTRUCTION_COUNT);
+    valid_params_if(PIO, wrap_target < PIO_INSTRUCTION_COUNT);
+    pio->sm[sm].execctrl =
+            (pio->sm[sm].execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) |
+            (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) |
+            (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB);
+}
+
+/*! \brief Set the current 'out' pins for a state machine
+ *  \ingroup sm_config
+ *
+ * Can overlap with the 'in', 'set' and 'sideset' pins
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param out_base 0-31 First pin to set as output
+ * \param out_count 0-32 Number of pins to set.
+ */
+static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out_count) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    valid_params_if(PIO, out_base < 32);
+    valid_params_if(PIO, out_count <= 32);
+    pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) |
+                 (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) |
+                 (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB);
+}
+
+
+/*! \brief Set the current 'set' pins for a state machine
+ *  \ingroup sm_config
+ *
+ * Can overlap with the 'in', 'out' and 'sideset' pins
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param set_base 0-31 First pin to set as
+ * \param set_count 0-5 Number of pins to set.
+ */
+static inline void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set_count) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    valid_params_if(PIO, set_base < 32);
+    valid_params_if(PIO, set_count <= 5);
+    pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) |
+                 (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) |
+                 (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB);
+}
+
+/*! \brief Set the current 'in' pins for a state machine
+ *  \ingroup sm_config
+ *
+ * Can overlap with the 'out', ''set' and 'sideset' pins
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param in_base 0-31 First pin to use as input
+ */
+static inline void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    valid_params_if(PIO, in_base < 32);
+    pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) |
+                 (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB);
+}
+
+/*! \brief Set the current 'sideset' pins for a state machine
+ *  \ingroup sm_config
+ *
+ * Can overlap with the 'in', 'out' and 'set' pins
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param sideset_base 0-31 base pin for 'side set'
+ */
+static inline void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    valid_params_if(PIO, sideset_base < 32);
+    pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) |
+                 (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB);
+}
+
+/*! \brief Write a word of data to a state machine's TX FIFO
+ *  \ingroup hardware_pio
+ *
+ * This is a raw FIFO access that does not check for fullness. If the FIFO is
+ * full, the FIFO contents and state are not affected by the write attempt.
+ * Hardware sets the TXOVER sticky flag for this FIFO in FDEBUG, to indicate
+ * that the system attempted to write to a full FIFO.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param data the 32 bit data value
+ *
+ * \sa pio_sm_put_blocking()
+ */
+static inline void pio_sm_put(PIO pio, uint sm, uint32_t data) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    pio->txf[sm] = data;
+}
+
+/*! \brief Read a word of data from a state machine's RX FIFO
+ *  \ingroup hardware_pio
+ *
+ * This is a raw FIFO access that does not check for emptiness. If the FIFO is
+ * empty, the hardware ignores the attempt to read from the FIFO (the FIFO
+ * remains in an empty state following the read) and the sticky RXUNDER flag
+ * for this FIFO is set in FDEBUG to indicate that the system tried to read
+ * from this FIFO when empty. The data returned by this function is undefined
+ * when the FIFO is empty.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ *
+ * \sa pio_sm_get_blocking()
+ */
+static inline uint32_t pio_sm_get(PIO pio, uint sm) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    return pio->rxf[sm];
+}
+
+/*! \brief Determine if a state machine's RX FIFO is full
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return true if the RX FIFO is full
+ */
+static inline bool pio_sm_is_rx_fifo_full(PIO pio, uint sm) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    return (pio->fstat & (1u << (PIO_FSTAT_RXFULL_LSB + sm))) != 0;
+}
+
+/*! \brief Determine if a state machine's RX FIFO is empty
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return true if the RX FIFO is empty
+ */
+static inline bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    return (pio->fstat & (1u << (PIO_FSTAT_RXEMPTY_LSB + sm))) != 0;
+}
+
+/*! \brief Return the number of elements currently in a state machine's RX FIFO
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return the number of elements in the RX FIFO
+ */
+static inline uint pio_sm_get_rx_fifo_level(PIO pio, uint sm) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    uint bitoffs = PIO_FLEVEL_RX0_LSB + sm * (PIO_FLEVEL_RX1_LSB - PIO_FLEVEL_RX0_LSB);
+    const uint32_t mask = PIO_FLEVEL_RX0_BITS >> PIO_FLEVEL_RX0_LSB;
+    return (pio->flevel >> bitoffs) & mask;
+}
+
+/*! \brief Determine if a state machine's TX FIFO is full
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return true if the TX FIFO is full
+ */
+static inline bool pio_sm_is_tx_fifo_full(PIO pio, uint sm) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    return (pio->fstat & (1u << (PIO_FSTAT_TXFULL_LSB + sm))) != 0;
+}
+
+/*! \brief Determine if a state machine's TX FIFO is empty
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return true if the TX FIFO is empty
+ */
+static inline bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    return (pio->fstat & (1u << (PIO_FSTAT_TXEMPTY_LSB + sm))) != 0;
+}
+
+/*! \brief Return the number of elements currently in a state machine's TX FIFO
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return the number of elements in the TX FIFO
+ */
+static inline uint pio_sm_get_tx_fifo_level(PIO pio, uint sm) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    unsigned int bitoffs = PIO_FLEVEL_TX0_LSB + sm * (PIO_FLEVEL_TX1_LSB - PIO_FLEVEL_TX0_LSB);
+    const uint32_t mask = PIO_FLEVEL_TX0_BITS >> PIO_FLEVEL_TX0_LSB;
+    return (pio->flevel >> bitoffs) & mask;
+}
+
+/*! \brief Write a word of data to a state machine's TX FIFO, blocking if the FIFO is full
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param data the 32 bit data value
+ */
+static inline void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    while (pio_sm_is_tx_fifo_full(pio, sm)) tight_loop_contents();
+    pio_sm_put(pio, sm, data);
+}
+
+/*! \brief Read a word of data from a state machine's RX FIFO, blocking if the FIFO is empty
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ */
+static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    while (pio_sm_is_rx_fifo_empty(pio, sm)) tight_loop_contents();
+    return pio_sm_get(pio, sm);
+}
+
+/*! \brief Empty out a state machine's TX FIFO
+ *  \ingroup hardware_pio
+ *
+ * This method executes `pull` instructions on the state machine until the TX
+ * FIFO is empty. This disturbs the contents of the OSR, so see also
+ * pio_sm_clear_fifos() which clears both FIFOs but leaves the state machine's
+ * internal state undisturbed.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ *
+ * \sa pio_sm_clear_fifos()
+ */
+void pio_sm_drain_tx_fifo(PIO pio, uint sm);
+
+/*! \brief set the current clock divider for a state machine using a 16:8 fraction
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param div_int the integer part of the clock divider
+ * \param div_frac the fractional part of the clock divider in 1/256s
+ */
+static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    pio->sm[sm].clkdiv =
+            (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) |
+            (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB);
+}
+
+/*! \brief set the current clock divider for a state machine
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param div the floating point clock divider
+ */
+static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    uint16_t div_int;
+    uint8_t div_frac;
+    pio_calculate_clkdiv_from_float(div, &div_int, &div_frac);
+    pio_sm_set_clkdiv_int_frac(pio, sm, div_int, div_frac);
+}
+
+/*! \brief Clear a state machine's TX and RX FIFOs
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ */
+static inline void pio_sm_clear_fifos(PIO pio, uint sm) {
+    // changing the FIFO join state clears the fifo
+    check_pio_param(pio);
+    check_sm_param(sm);
+    hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS);
+    hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS);
+}
+
+/*! \brief Use a state machine to set a value on all pins for the PIO instance
+ *  \ingroup hardware_pio
+ *
+ * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set values on all 32 pins,
+ * before restoring the state machine's pin configuration to what it was.
+ *
+ * This method is provided as a convenience to set initial pin states, and should not be used against a state machine that is enabled.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3) to use
+ * \param pin_values the pin values to set
+ */
+void pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values);
+
+/*! \brief Use a state machine to set a value on multiple pins for the PIO instance
+ *  \ingroup hardware_pio
+ *
+ * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set values on up to 32 pins,
+ * before restoring the state machine's pin configuration to what it was.
+ *
+ * This method is provided as a convenience to set initial pin states, and should not be used against a state machine that is enabled.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3) to use
+ * \param pin_values the pin values to set (if the corresponding bit in pin_mask is set)
+ * \param pin_mask a bit for each pin to indicate whether the corresponding pin_value for that pin should be applied.
+ */
+void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pin_values, uint32_t pin_mask);
+
+/*! \brief Use a state machine to set the pin directions for multiple pins for the PIO instance
+ *  \ingroup hardware_pio
+ *
+ * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set pin directions on up to 32 pins,
+ * before restoring the state machine's pin configuration to what it was.
+ *
+ * This method is provided as a convenience to set initial pin directions, and should not be used against a state machine that is enabled.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3) to use
+ * \param pin_dirs the pin directions to set - 1 = out, 0 = in (if the corresponding bit in pin_mask is set)
+ * \param pin_mask a bit for each pin to indicate whether the corresponding pin_value for that pin should be applied.
+ */
+void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pin_dirs, uint32_t pin_mask);
+
+/*! \brief Use a state machine to set the same pin direction for multiple consecutive pins for the PIO instance
+ *  \ingroup hardware_pio
+ *
+ * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set the pin direction on consecutive pins,
+ * before restoring the state machine's pin configuration to what it was.
+ *
+ * This method is provided as a convenience to set initial pin directions, and should not be used against a state machine that is enabled.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3) to use
+ * \param pin_base the first pin to set a direction for
+ * \param pin_count the count of consecutive pins to set the direction for
+ * \param is_out the direction to set; true = out, false = in
+ */
+void pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin_base, uint pin_count, bool is_out);
+
+/*! \brief Mark a state machine as used
+ *  \ingroup hardware_pio
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if the state machine
+ * is already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ */
+void pio_sm_claim(PIO pio, uint sm);
+
+/*! \brief Mark multiple state machines as used
+ *  \ingroup hardware_pio
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if any of the state machines
+ * are already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm_mask Mask of state machine indexes
+ */
+void pio_claim_sm_mask(PIO pio, uint sm_mask);
+
+/*! \brief Mark a state machine as no longer used
+ *  \ingroup hardware_pio
+ *
+ * Method for cooperative claiming of hardware.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ */
+void pio_sm_unclaim(PIO pio, uint sm);
+
+/*! \brief Claim a free state machine on a PIO instance
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param required if true the function will panic if none are available
+ * \return the state machine index or -1 if required was false, and none were free
+ */
+int pio_claim_unused_sm(PIO pio, bool required);
+
+/*! \brief Determine if a PIO state machine is claimed
+ *  \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return true if claimed, false otherwise
+ * \see pio_sm_claim
+ * \see pio_claim_sm_mask
+ */
+bool pio_sm_is_claimed(PIO pio, uint sm);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _PIO_H_
diff --git a/src/rp2_common/hardware_pio/include/hardware/pio_instructions.h b/src/rp2_common/hardware_pio/include/hardware/pio_instructions.h
new file mode 100644
index 0000000..3662135
--- /dev/null
+++ b/src/rp2_common/hardware_pio/include/hardware/pio_instructions.h
@@ -0,0 +1,484 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_PIO_INSTRUCTIONS_H_
+#define _HARDWARE_PIO_INSTRUCTIONS_H_
+
+#include "pico.h"
+
+/** \brief PIO instruction encoding 
+ *  \defgroup pio_instructions pio_instructions
+ *  \ingroup hardware_pio
+ * 
+ * Functions for generating PIO instruction encodings programmatically. In debug builds
+ *`PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` can be set to 1 to enable validation of encoding function
+ * parameters.
+ *
+ * For fuller descriptions of the instructions in question see the "RP2040 Datasheet"
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS, Enable/disable assertions in the PIO instructions, type=bool, default=0, group=pio_instructions
+#ifndef PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS
+#define PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum pio_instr_bits {
+    pio_instr_bits_jmp = 0x0000,
+    pio_instr_bits_wait = 0x2000,
+    pio_instr_bits_in = 0x4000,
+    pio_instr_bits_out = 0x6000,
+    pio_instr_bits_push = 0x8000,
+    pio_instr_bits_pull = 0x8080,
+    pio_instr_bits_mov = 0xa000,
+    pio_instr_bits_irq = 0xc000,
+    pio_instr_bits_set = 0xe000,
+};
+
+#ifndef NDEBUG
+#define _PIO_INVALID_IN_SRC    0x08u
+#define _PIO_INVALID_OUT_DEST 0x10u
+#define _PIO_INVALID_SET_DEST 0x20u
+#define _PIO_INVALID_MOV_SRC  0x40u
+#define _PIO_INVALID_MOV_DEST 0x80u
+#else
+#define _PIO_INVALID_IN_SRC    0u
+#define _PIO_INVALID_OUT_DEST 0u
+#define _PIO_INVALID_SET_DEST 0u
+#define _PIO_INVALID_MOV_SRC  0u
+#define _PIO_INVALID_MOV_DEST 0u
+#endif
+
+/*! \brief Enumeration of values to pass for source/destination args for instruction encoding functions
+ *  \ingroup pio_instructions
+ *
+ * \note Not all values are suitable for all functions. Validity is only checked in debug mode when
+ * `PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` is 1
+ */
+enum pio_src_dest {
+    pio_pins = 0u,
+    pio_x = 1u,
+    pio_y = 2u,
+    pio_null = 3u | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST,
+    pio_pindirs = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST,
+    pio_exec_mov = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC,
+    pio_status = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST,
+    pio_pc = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC,
+    pio_isr = 6u | _PIO_INVALID_SET_DEST,
+    pio_osr = 7u | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST,
+    pio_exec_out = 7u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST,
+};
+
+static inline uint _pio_major_instr_bits(uint instr) {
+    return instr & 0xe000u;
+}
+
+static inline uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, uint arg1, uint arg2) {
+    valid_params_if(PIO_INSTRUCTIONS, arg1 <= 0x7);
+#if PARAM_ASSERTIONS_ENABLED(PIO_INSTRUCTIONS)
+    uint32_t major = _pio_major_instr_bits(instr_bits);
+    if (major == pio_instr_bits_in || major == pio_instr_bits_out) {
+        assert(arg2 && arg2 <= 32);
+    } else {
+        assert(arg2 <= 31);
+    }
+#endif
+    return instr_bits | (arg1 << 5u) | (arg2 & 0x1fu);
+}
+
+static inline uint _pio_encode_instr_and_src_dest(enum pio_instr_bits instr_bits, enum pio_src_dest dest, uint value) {
+    return _pio_encode_instr_and_args(instr_bits, dest & 7u, value);
+}
+
+/*! \brief Encode just the delay slot bits of an instruction
+ *  \ingroup pio_instructions
+ *
+ * \note This function does not return a valid instruction encoding; instead it returns an encoding of the delay
+ * slot suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when
+ * combining the results of this function with the results of \ref pio_encode_sideset and \ref pio_encode_sideset_opt
+ * as they share the same bits within the instruction encoding.
+ *
+ * \param cycles the number of cycles 0-31 (or less if side set is being used)
+ * \return the delay slot bits to be ORed with an instruction encoding
+ */
+static inline uint pio_encode_delay(uint cycles) {
+    // note that the maximum cycles will be smaller if sideset_bit_count > 0
+    valid_params_if(PIO_INSTRUCTIONS, cycles <= 0x1f);
+    return cycles << 8u;
+}
+
+/*! \brief Encode just the side set bits of an instruction (in non optional side set mode)
+ *  \ingroup pio_instructions
+ *
+ * \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits
+ * suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when
+ * combining the results of this function with the results of \ref pio_encode_delay as they share the same bits
+ * within the instruction encoding.
+ *
+ * \param sideset_bit_count number of side set bits as would be specified via `.sideset` in pioasm
+ * \param value the value to sideset on the pins
+ * \return the side set bits to be ORed with an instruction encoding
+ */
+static inline uint pio_encode_sideset(uint sideset_bit_count, uint value) {
+    valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 5);
+    valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1));
+    return value << (13u - sideset_bit_count);
+}
+
+/*! \brief Encode just the side set bits of an instruction (in optional -`opt` side set mode)
+ *  \ingroup pio_instructions
+ *
+ * \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits
+ * suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when
+ * combining the results of this function with the results of \ref pio_encode_delay as they share the same bits
+ * within the instruction encoding.
+ *
+ * \param sideset_bit_count number of side set bits as would be specified via `.sideset <n> opt` in pioasm
+ * \param value the value to sideset on the pins
+ * \return the side set bits to be ORed with an instruction encoding
+ */
+static inline uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) {
+    valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 4);
+    valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1));
+    return 0x1000u | value << (12u - sideset_bit_count);
+}
+
+/*! \brief Encode an unconditional JMP instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 0, addr);
+}
+
+/*! \brief Encode a conditional JMP if scratch X zero instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP !X <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_not_x(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 1, addr);
+}
+
+/*! \brief Encode a conditional JMP if scratch X non-zero (and post-decrement X) instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP X-- <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_x_dec(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 2, addr);
+}
+
+/*! \brief Encode a conditional JMP if scratch Y zero instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP !Y <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_not_y(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 3, addr);
+}
+
+/*! \brief Encode a conditional JMP if scratch Y non-zero (and post-decrement Y) instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP Y-- <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_y_dec(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 4, addr);
+}
+
+/*! \brief Encode a conditional JMP if scratch X not equal scratch Y instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP X!=Y <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_x_ne_y(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 5, addr);
+}
+
+/*! \brief Encode a conditional JMP if input pin high instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP PIN <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_pin(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 6, addr);
+}
+
+/*! \brief Encode a conditional JMP if output shift register not empty instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP !OSRE <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_not_osre(uint addr) {
+    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 7, addr);
+}
+
+static inline uint _pio_encode_irq(bool relative, uint irq) {
+    valid_params_if(PIO_INSTRUCTIONS, irq <= 7);
+    return (relative ? 0x10u : 0x0u) | irq;
+}
+
+/*! \brief Encode a WAIT for GPIO pin instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `WAIT <polarity> GPIO <gpio>`
+ *
+ * \param polarity true for `WAIT 1`, false for `WAIT 0`
+ * \param gpio The real GPIO number 0-31
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_wait_gpio(bool polarity, uint gpio) {
+    return _pio_encode_instr_and_args(pio_instr_bits_wait, 0u | (polarity ? 4u : 0u), gpio);
+}
+
+/*! \brief Encode a WAIT for pin instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `WAIT <polarity> PIN <pin>`
+ *
+ * \param polarity true for `WAIT 1`, false for `WAIT 0`
+ * \param pin The pin number 0-31 relative to the executing SM's input pin mapping
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_wait_pin(bool polarity, uint pin) {
+    return _pio_encode_instr_and_args(pio_instr_bits_wait, 1u | (polarity ? 4u : 0u), pin);
+}
+
+/*! \brief Encode a WAIT for IRQ instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `WAIT <polarity> IRQ <irq> <relative>`
+ *
+ * \param polarity true for `WAIT 1`, false for `WAIT 0`
+ * \param relative true for a `WAIT IRQ <irq> REL`, false for regular `WAIT IRQ <irq>`
+ * \param irq the irq number 0-7
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_wait_irq(bool polarity, bool relative, uint irq) {
+    valid_params_if(PIO_INSTRUCTIONS, irq <= 7);
+    return _pio_encode_instr_and_args(pio_instr_bits_wait, 2u | (polarity ? 4u : 0u), _pio_encode_irq(relative, irq));
+}
+
+/*! \brief Encode an IN instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `IN <src>, <count>`
+ *
+ * \param src The source to take data from
+ * \param count The number of bits 1-32
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_in(enum pio_src_dest src, uint count) {
+    valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_IN_SRC));
+    return _pio_encode_instr_and_src_dest(pio_instr_bits_in, src, count);
+}
+
+/*! \brief Encode an OUT instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `OUT <src>, <count>`
+ *
+ * \param dest The destination to write data to
+ * \param count The number of bits 1-32
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_out(enum pio_src_dest dest, uint count) {
+    valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_OUT_DEST));
+    return _pio_encode_instr_and_src_dest(pio_instr_bits_out, dest, count);
+}
+
+/*! \brief Encode a PUSH instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `PUSH <if_full>, <block>`
+ *
+ * \param if_full true for `PUSH IF_FULL ...`, false for `PUSH ...`
+ * \param block true for `PUSH ... BLOCK`, false for `PUSH ...`
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_push(bool if_full, bool block) {
+    return _pio_encode_instr_and_args(pio_instr_bits_push, (if_full ? 2u : 0u) | (block ? 1u : 0u), 0);
+}
+
+/*! \brief Encode a PULL instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `PULL <if_empty>, <block>`
+ *
+ * \param if_empty true for `PULL IF_EMPTY ...`, false for `PULL ...`
+ * \param block true for `PULL ... BLOCK`, false for `PULL ...`
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_pull(bool if_empty, bool block) {
+    return _pio_encode_instr_and_args(pio_instr_bits_pull, (if_empty ? 2u : 0u) | (block ? 1u : 0u), 0);
+}
+
+/*! \brief Encode a MOV instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `MOV <dest>, <src>`
+ *
+ * \param dest The destination to write data to
+ * \param src The source to take data from
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_mov(enum pio_src_dest dest, enum pio_src_dest src) {
+    valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
+    valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
+    return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, src & 7u);
+}
+
+/*! \brief Encode a MOV instruction with bit invert
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `MOV <dest>, ~<src>`
+ *
+ * \param dest The destination to write inverted data to
+ * \param src The source to take data from
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_mov_not(enum pio_src_dest dest, enum pio_src_dest src) {
+    valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
+    valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
+    return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (1u << 3u) | (src & 7u));
+}
+
+/*! \brief Encode a MOV instruction with bit reverse
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `MOV <dest>, ::<src>`
+ *
+ * \param dest The destination to write bit reversed data to
+ * \param src The source to take data from
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_mov_reverse(enum pio_src_dest dest, enum pio_src_dest src) {
+    valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
+    valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
+    return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (2u << 3u) | (src & 7u));
+}
+
+/*! \brief Encode a IRQ SET instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `IRQ SET <irq> <relative>`
+ *
+ * \param relative true for a `IRQ SET <irq> REL`, false for regular `IRQ SET <irq>`
+ * \param irq the irq number 0-7
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_irq_set(bool relative, uint irq) {
+    return _pio_encode_instr_and_args(pio_instr_bits_irq, 0, _pio_encode_irq(relative, irq));
+}
+
+/*! \brief Encode a IRQ WAIT instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `IRQ WAIT <irq> <relative>`
+ *
+ * \param relative true for a `IRQ WAIT <irq> REL`, false for regular `IRQ WAIT <irq>`
+ * \param irq the irq number 0-7
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_irq_wait(bool relative, uint irq) {
+    return _pio_encode_instr_and_args(pio_instr_bits_irq, 1, _pio_encode_irq(relative, irq));
+}
+
+/*! \brief Encode a IRQ CLEAR instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `IRQ CLEAR <irq> <relative>`
+ *
+ * \param relative true for a `IRQ CLEAR <irq> REL`, false for regular `IRQ CLEAR <irq>`
+ * \param irq the irq number 0-7
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_irq_clear(bool relative, uint irq) {
+    return _pio_encode_instr_and_args(pio_instr_bits_irq, 2, _pio_encode_irq(relative, irq));
+}
+
+/*! \brief Encode a SET instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `SET <dest>, <value>`
+ *
+ * \param dest The destination to apply the value to
+ * \param value The value 0-31
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_set(enum pio_src_dest dest, uint value) {
+    valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_SET_DEST));
+    return _pio_encode_instr_and_src_dest(pio_instr_bits_set, dest, value);
+}
+
+/*! \brief Encode a NOP instruction
+ *  \ingroup pio_instructions
+ *
+ * This is the equivalent of `NOP` which is itself encoded as `MOV y, y`
+ *
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_nop(void) {
+    return pio_encode_mov(pio_y, pio_y);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_pio/pio.c b/src/rp2_common/hardware_pio/pio.c
new file mode 100644
index 0000000..0744110
--- /dev/null
+++ b/src/rp2_common/hardware_pio/pio.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/claim.h"
+#include "hardware/pio.h"
+#include "hardware/pio_instructions.h"
+
+// sanity check
+check_hw_layout(pio_hw_t, sm[0].clkdiv, PIO_SM0_CLKDIV_OFFSET);
+check_hw_layout(pio_hw_t, sm[1].clkdiv, PIO_SM1_CLKDIV_OFFSET);
+check_hw_layout(pio_hw_t, instr_mem[0], PIO_INSTR_MEM0_OFFSET);
+check_hw_layout(pio_hw_t, inte0, PIO_IRQ0_INTE_OFFSET);
+check_hw_layout(pio_hw_t, txf[1], PIO_TXF1_OFFSET);
+check_hw_layout(pio_hw_t, rxf[3], PIO_RXF3_OFFSET);
+check_hw_layout(pio_hw_t, ints1, PIO_IRQ1_INTS_OFFSET);
+
+static_assert(NUM_PIO_STATE_MACHINES * NUM_PIOS <= 8, "");
+static uint8_t claimed;
+
+void pio_sm_claim(PIO pio, uint sm) {
+    check_sm_param(sm);
+    uint which = pio_get_index(pio);
+    if (which) {
+        hw_claim_or_assert(&claimed, NUM_PIO_STATE_MACHINES + sm, "PIO 1 SM (%d - 4) already claimed");
+    } else {
+        hw_claim_or_assert(&claimed, sm, "PIO 0 SM %d already claimed");
+    }
+}
+
+void pio_claim_sm_mask(PIO pio, uint sm_mask) {
+    for(uint i = 0; sm_mask; i++, sm_mask >>= 1u) {
+        if (sm_mask & 1u) pio_sm_claim(pio, i);
+    }
+}
+
+void pio_sm_unclaim(PIO pio, uint sm) {
+    check_sm_param(sm);
+    uint which = pio_get_index(pio);
+    hw_claim_clear(&claimed, which * NUM_PIO_STATE_MACHINES + sm);
+}
+
+int pio_claim_unused_sm(PIO pio, bool required) {
+    // PIO index is 0 or 1.
+    uint which = pio_get_index(pio);
+    uint base = which * NUM_PIO_STATE_MACHINES;
+    int index = hw_claim_unused_from_range((uint8_t*)&claimed, required, base,
+                                      base + NUM_PIO_STATE_MACHINES - 1, "No PIO state machines are available");
+    return index >= (int)base ? index - (int)base : -1;
+}
+
+bool pio_sm_is_claimed(PIO pio, uint sm) {
+    check_sm_param(sm);
+    uint which = pio_get_index(pio);
+    return hw_is_claimed(&claimed, which * NUM_PIO_STATE_MACHINES + sm);
+}
+
+static_assert(PIO_INSTRUCTION_COUNT <= 32, "");
+static uint32_t _used_instruction_space[2];
+
+static int _pio_find_offset_for_program(PIO pio, const pio_program_t *program) {
+    assert(program->length <= PIO_INSTRUCTION_COUNT);
+    uint32_t used_mask = _used_instruction_space[pio_get_index(pio)];
+    uint32_t program_mask = (1u << program->length) - 1;
+    if (program->origin >= 0) {
+        if (program->origin > 32 - program->length) return -1;
+        return used_mask & (program_mask << program->origin) ? -1 : program->origin;
+    } else {
+        // work down from the top always
+        for (int i = 32 - program->length; i >= 0; i--) {
+            if (!(used_mask & (program_mask << (uint) i))) {
+                return i;
+            }
+        }
+        return -1;
+    }
+}
+
+bool pio_can_add_program(PIO pio, const pio_program_t *program) {
+    uint32_t save = hw_claim_lock();
+    bool rc =  -1 != _pio_find_offset_for_program(pio, program);
+    hw_claim_unlock(save);
+    return rc;
+}
+
+static bool _pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) {
+    valid_params_if(PIO, offset < PIO_INSTRUCTION_COUNT);
+    valid_params_if(PIO, offset + program->length <= PIO_INSTRUCTION_COUNT);
+    if (program->origin >= 0 && (uint)program->origin != offset) return false;
+    uint32_t used_mask = _used_instruction_space[pio_get_index(pio)];
+    uint32_t program_mask = (1u << program->length) - 1;
+    return !(used_mask & (program_mask << offset));
+}
+
+bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) {
+    uint32_t save = hw_claim_lock();
+    bool rc = _pio_can_add_program_at_offset(pio, program, offset);
+    hw_claim_unlock(save);
+    return rc;
+}
+
+static void _pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) {
+    if (!_pio_can_add_program_at_offset(pio, program, offset)) {
+        panic("No program space");
+    }
+    for (uint i = 0; i < program->length; ++i) {
+        uint16_t instr = program->instructions[i];
+        pio->instr_mem[offset + i] = pio_instr_bits_jmp != _pio_major_instr_bits(instr) ? instr : instr + offset;
+    }
+    uint32_t program_mask = (1u << program->length) - 1;
+    _used_instruction_space[pio_get_index(pio)] |= program_mask << offset;
+}
+
+// these assert if unable
+uint pio_add_program(PIO pio, const pio_program_t *program) {
+    uint32_t save = hw_claim_lock();
+    int offset = _pio_find_offset_for_program(pio, program);
+    if (offset < 0) {
+        panic("No program space");
+    }
+    _pio_add_program_at_offset(pio, program, (uint)offset);
+    hw_claim_unlock(save);
+    return (uint)offset;
+}
+
+void pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) {
+    uint32_t save = hw_claim_lock();
+    _pio_add_program_at_offset(pio, program, offset);
+    hw_claim_unlock(save);
+}
+
+void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset) {
+    uint32_t program_mask = (1u << program->length) - 1;
+    program_mask <<= loaded_offset;
+    uint32_t save = hw_claim_lock();
+    assert(program_mask == (_used_instruction_space[pio_get_index(pio)] & program_mask));
+    _used_instruction_space[pio_get_index(pio)] &= ~program_mask;
+    hw_claim_unlock(save);
+}
+
+void pio_clear_instruction_memory(PIO pio) {
+    uint32_t save = hw_claim_lock();
+    _used_instruction_space[pio_get_index(pio)] = 0;
+    for(uint i=0;i<PIO_INSTRUCTION_COUNT;i++) {
+        pio->instr_mem[i] = pio_encode_jmp(i);
+    }
+    hw_claim_unlock(save);
+}
+
+// Set the value of all PIO pins. This is done by forcibly executing
+// instructions on a "victim" state machine, sm. Ideally you should choose one
+// which is not currently running a program. This is intended for one-time
+// setup of initial pin states.
+void pio_sm_set_pins(PIO pio, uint sm, uint32_t pins) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    uint32_t pinctrl_saved = pio->sm[sm].pinctrl;
+    uint remaining = 32;
+    uint base = 0;
+    while (remaining) {
+        uint decrement = remaining > 5 ? 5 : remaining;
+        pio->sm[sm].pinctrl =
+                (decrement << PIO_SM0_PINCTRL_SET_COUNT_LSB) |
+                (base << PIO_SM0_PINCTRL_SET_BASE_LSB);
+        pio_sm_exec(pio, sm, pio_encode_set(pio_pins, pins & 0x1fu));
+        remaining -= decrement;
+        base += decrement;
+        pins >>= 5;
+    }
+    pio->sm[sm].pinctrl = pinctrl_saved;
+}
+
+void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pinvals, uint32_t pin_mask) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    uint32_t pinctrl_saved = pio->sm[sm].pinctrl;
+    while (pin_mask) {
+        uint base = (uint)__builtin_ctz(pin_mask);
+        pio->sm[sm].pinctrl =
+                (1u << PIO_SM0_PINCTRL_SET_COUNT_LSB) |
+                (base << PIO_SM0_PINCTRL_SET_BASE_LSB);
+        pio_sm_exec(pio, sm, pio_encode_set(pio_pins, (pinvals >> base) & 0x1u));
+        pin_mask &= pin_mask - 1;
+    }
+    pio->sm[sm].pinctrl = pinctrl_saved;
+}
+
+void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pindirs, uint32_t pin_mask) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    uint32_t pinctrl_saved = pio->sm[sm].pinctrl;
+    while (pin_mask) {
+        uint base = (uint)__builtin_ctz(pin_mask);
+        pio->sm[sm].pinctrl =
+                (1u << PIO_SM0_PINCTRL_SET_COUNT_LSB) |
+                (base << PIO_SM0_PINCTRL_SET_BASE_LSB);
+        pio_sm_exec(pio, sm, pio_encode_set(pio_pindirs, (pindirs >> base) & 0x1u));
+        pin_mask &= pin_mask - 1;
+    }
+    pio->sm[sm].pinctrl = pinctrl_saved;
+}
+
+void pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin, uint count, bool is_out) {
+    check_pio_param(pio);
+    check_sm_param(sm);
+    valid_params_if(PIO, pin < 32u);
+    uint32_t pinctrl_saved = pio->sm[sm].pinctrl;
+    uint pindir_val = is_out ? 0x1f : 0;
+    while (count > 5) {
+        pio->sm[sm].pinctrl = (5u << PIO_SM0_PINCTRL_SET_COUNT_LSB) | (pin << PIO_SM0_PINCTRL_SET_BASE_LSB);
+        pio_sm_exec(pio, sm, pio_encode_set(pio_pindirs, pindir_val));
+        count -= 5;
+        pin = (pin + 5) & 0x1f;
+    }
+    pio->sm[sm].pinctrl = (count << PIO_SM0_PINCTRL_SET_COUNT_LSB) | (pin << PIO_SM0_PINCTRL_SET_BASE_LSB);
+    pio_sm_exec(pio, sm, pio_encode_set(pio_pindirs, pindir_val));
+    pio->sm[sm].pinctrl = pinctrl_saved;
+}
+
+void pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config) {
+    valid_params_if(PIO, initial_pc < PIO_INSTRUCTION_COUNT);
+    // Halt the machine, set some sensible defaults
+    pio_sm_set_enabled(pio, sm, false);
+
+    if (config) {
+        pio_sm_set_config(pio, sm, config);
+    } else {
+        pio_sm_config c = pio_get_default_sm_config();
+        pio_sm_set_config(pio, sm, &c);
+    }
+
+    pio_sm_clear_fifos(pio, sm);
+
+    // Clear FIFO debug flags
+    const uint32_t fdebug_sm_mask =
+            (1u << PIO_FDEBUG_TXOVER_LSB) |
+            (1u << PIO_FDEBUG_RXUNDER_LSB) |
+            (1u << PIO_FDEBUG_TXSTALL_LSB) |
+            (1u << PIO_FDEBUG_RXSTALL_LSB);
+    pio->fdebug = fdebug_sm_mask << sm;
+
+    // Finally, clear some internal SM state
+    pio_sm_restart(pio, sm);
+    pio_sm_clkdiv_restart(pio, sm);
+    pio_sm_exec(pio, sm, pio_encode_jmp(initial_pc));
+}
+
+void pio_sm_drain_tx_fifo(PIO pio, uint sm) {
+    uint instr = (pio->sm[sm].shiftctrl & PIO_SM0_SHIFTCTRL_AUTOPULL_BITS) ? pio_encode_out(pio_null, 32) :
+                 pio_encode_pull(false, false);
+    while (!pio_sm_is_tx_fifo_empty(pio, sm)) {
+        pio_sm_exec(pio, sm, instr);
+    }
+}
diff --git a/src/rp2_common/hardware_pll/CMakeLists.txt b/src/rp2_common/hardware_pll/CMakeLists.txt
new file mode 100644
index 0000000..37ff759
--- /dev/null
+++ b/src/rp2_common/hardware_pll/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(pll)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_pll/include/hardware/pll.h b/src/rp2_common/hardware_pll/include/hardware/pll.h
new file mode 100644
index 0000000..ee0c3ae
--- /dev/null
+++ b/src/rp2_common/hardware_pll/include/hardware/pll.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_PLL_H_
+#define _HARDWARE_PLL_H_
+
+#include "pico.h"
+#include "hardware/structs/pll.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file hardware/pll.h
+ *  \defgroup hardware_pll hardware_pll
+ *
+ * Phase Locked Loop control APIs
+ *
+ * There are two PLLs in RP2040. They are:
+ *   - pll_sys - Used to generate up to a 133MHz system clock
+ *   - pll_usb - Used to generate a 48MHz USB reference clock
+ *
+ * For details on how the PLL's are calculated, please refer to the RP2040 datasheet.
+ */
+
+typedef pll_hw_t *PLL;
+
+#define pll_sys pll_sys_hw
+#define pll_usb pll_usb_hw
+
+/*! \brief Initialise specified PLL.
+ *  \ingroup hardware_pll
+ * \param pll pll_sys or pll_usb
+ * \param ref_div Input clock divider.
+ * \param vco_freq  Requested output from the VCO (voltage controlled oscillator)
+ * \param post_div1 Post Divider 1 - range 1-7. Must be >= post_div2
+ * \param post_div2 Post Divider 2 - range 1-7
+ */
+void pll_init(PLL pll, uint ref_div, uint vco_freq, uint post_div1, uint post_div2);
+
+/*! \brief Release/uninitialise specified PLL.
+ *  \ingroup hardware_pll
+ *
+ * This will turn off the power to the specified PLL. Note this function does not currently check if
+ * the PLL is in use before powering it off so should be used with care.
+ *
+ * \param pll pll_sys or pll_usb
+ */
+void pll_deinit(PLL pll);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_pll/pll.c b/src/rp2_common/hardware_pll/pll.c
new file mode 100644
index 0000000..6cc6184
--- /dev/null
+++ b/src/rp2_common/hardware_pll/pll.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// For MHZ definitions etc
+#include "hardware/clocks.h"
+#include "hardware/pll.h"
+#include "hardware/resets.h"
+
+/// \tag::pll_init_calculations[]
+void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div2) {
+    uint32_t ref_mhz = XOSC_MHZ / refdiv;
+
+    // What are we multiplying the reference clock by to get the vco freq
+    // (The regs are called div, because you divide the vco output and compare it to the refclk)
+    uint32_t fbdiv = vco_freq / (ref_mhz * MHZ);
+/// \end::pll_init_calculations[]
+
+    // fbdiv
+    assert(fbdiv >= 16 && fbdiv <= 320);
+
+    // Check divider ranges
+    assert((post_div1 >= 1 && post_div1 <= 7) && (post_div2 >= 1 && post_div2 <= 7));
+
+    // post_div1 should be >= post_div2
+    // from appnote page 11
+    // postdiv1 is designed to operate with a higher input frequency
+    // than postdiv2
+    assert(post_div2 <= post_div1);
+
+    // Check that reference frequency is no greater than vco / 16
+    assert(ref_mhz <= (vco_freq / 16));
+
+    // div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get a divide by 10
+    uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) |
+                    (post_div2 << PLL_PRIM_POSTDIV2_LSB);
+
+/// \tag::pll_init_finish[]
+    if ((pll->cs & PLL_CS_LOCK_BITS) &&
+        (refdiv == (pll->cs & PLL_CS_REFDIV_BITS)) &&
+        (fbdiv  == (pll->fbdiv_int & PLL_FBDIV_INT_BITS)) &&
+        (pdiv   == (pll->prim & (PLL_PRIM_POSTDIV1_BITS & PLL_PRIM_POSTDIV2_BITS)))) {
+        // do not disrupt PLL that is already correctly configured and operating
+        return;
+    }
+
+    uint32_t pll_reset = (pll_usb_hw == pll) ? RESETS_RESET_PLL_USB_BITS : RESETS_RESET_PLL_SYS_BITS;
+    reset_block(pll_reset);
+    unreset_block_wait(pll_reset);
+
+    // Load VCO-related dividers before starting VCO
+    pll->cs = refdiv;
+    pll->fbdiv_int = fbdiv;
+
+    // Turn on PLL
+    uint32_t power = PLL_PWR_PD_BITS | // Main power
+                     PLL_PWR_VCOPD_BITS; // VCO Power
+
+    hw_clear_bits(&pll->pwr, power);
+
+    // Wait for PLL to lock
+    while (!(pll->cs & PLL_CS_LOCK_BITS)) tight_loop_contents();
+
+    // Set up post dividers
+    pll->prim = pdiv;
+
+    // Turn on post divider
+    hw_clear_bits(&pll->pwr, PLL_PWR_POSTDIVPD_BITS);
+/// \end::pll_init_finish[]
+}
+
+void pll_deinit(PLL pll) {
+    // todo: Make sure there are no sources running from this pll?
+    pll->pwr = PLL_PWR_BITS;
+}
diff --git a/src/rp2_common/hardware_pwm/CMakeLists.txt b/src/rp2_common/hardware_pwm/CMakeLists.txt
new file mode 100644
index 0000000..c8d3401
--- /dev/null
+++ b/src/rp2_common/hardware_pwm/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_headers_only_target(pwm)
diff --git a/src/rp2_common/hardware_pwm/include/hardware/pwm.h b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
new file mode 100644
index 0000000..634375e
--- /dev/null
+++ b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
@@ -0,0 +1,559 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_PWM_H
+#define _HARDWARE_PWM_H
+
+#include "pico.h"
+#include "hardware/structs/pwm.h"
+#include "hardware/regs/dreq.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PWM, Enable/disable assertions in the PWM module, type=bool, default=0, group=hardware_pwm
+#ifndef PARAM_ASSERTIONS_ENABLED_PWM
+#define PARAM_ASSERTIONS_ENABLED_PWM 0
+#endif
+
+/** \file hardware/pwm.h
+ *  \defgroup hardware_pwm hardware_pwm
+ *
+ * Hardware Pulse Width Modulation (PWM) API
+ *
+ * The RP2040 PWM block has 8 identical slices. Each slice can drive two PWM output signals, or
+ * measure the frequency or duty cycle of an input signal. This gives a total of up to 16 controllable
+ * PWM outputs. All 30 GPIOs can be driven by the PWM block.
+ *
+ * The PWM hardware functions by continuously comparing the input value to a free-running counter. This produces a
+ * toggling output where the amount of time spent at the high output level is proportional to the input value. The fraction of
+ * time spent at the high signal level is known as the duty cycle of the signal.
+ *
+ * The default behaviour of a PWM slice is to count upward until the wrap value (\ref pwm_config_set_wrap) is reached, and then
+ * immediately wrap to 0. PWM slices also offer a phase-correct mode, where the counter starts to count downward after
+ * reaching TOP, until it reaches 0 again.
+ *
+ * \subsection pwm_example Example
+ * \addtogroup hardware_pwm
+ * \include hello_pwm.c
+ */
+
+/** \brief PWM Divider mode settings
+ *   \ingroup hardware_pwm
+ *
+ */
+enum pwm_clkdiv_mode
+{
+    PWM_DIV_FREE_RUNNING = 0, ///< Free-running counting at rate dictated by fractional divider
+    PWM_DIV_B_HIGH = 1,       ///< Fractional divider is gated by the PWM B pin
+    PWM_DIV_B_RISING = 2,     ///< Fractional divider advances with each rising edge of the PWM B pin
+    PWM_DIV_B_FALLING = 3    ///< Fractional divider advances with each falling edge of the PWM B pin
+};
+
+enum pwm_chan
+{
+    PWM_CHAN_A = 0,
+    PWM_CHAN_B = 1
+};
+
+typedef struct {
+    uint32_t csr;
+    uint32_t div;
+    uint32_t top;
+} pwm_config;
+
+static inline void check_slice_num_param(__unused uint slice_num) {
+    valid_params_if(PWM, slice_num < NUM_PWM_SLICES);
+}
+
+/** \brief Determine the PWM slice that is attached to the specified GPIO
+ *  \ingroup hardware_pwm
+ *
+ * \return The PWM slice number that controls the specified GPIO.
+ */
+static inline uint pwm_gpio_to_slice_num(uint gpio) {
+    valid_params_if(PWM, gpio < NUM_BANK0_GPIOS);
+    return (gpio >> 1u) & 7u;
+}
+
+/** \brief Determine the PWM channel that is attached to the specified GPIO.
+ *  \ingroup hardware_pwm
+ *
+ * Each slice 0 to 7 has two channels, A and B.
+ *
+ * \return The PWM channel that controls the specified GPIO.
+ */
+static inline uint pwm_gpio_to_channel(uint gpio) {
+    valid_params_if(PWM, gpio < NUM_BANK0_GPIOS);
+    return gpio & 1u;
+}
+
+/** \brief Set phase correction in a PWM configuration
+ *  \ingroup hardware_pwm
+ *
+ * \param c PWM configuration struct to modify
+ * \param phase_correct true to set phase correct modulation, false to set trailing edge
+ *
+ * Setting phase control to true means that instead of wrapping back to zero when the wrap point is reached,
+ * the PWM starts counting back down. The output frequency is halved when phase-correct mode is enabled.
+ */
+static inline void pwm_config_set_phase_correct(pwm_config *c, bool phase_correct) {
+    c->csr = (c->csr & ~PWM_CH0_CSR_PH_CORRECT_BITS)
+        | (bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB);
+}
+
+/** \brief Set clock divider in a PWM configuration
+ *  \ingroup hardware_pwm
+ *
+ * \param c PWM configuration struct to modify
+ * \param div Value to divide counting rate by. Must be greater than or equal to 1.
+ *
+ * If the divide mode is free-running, the PWM counter runs at clk_sys / div.
+ * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
+ * before passing them on to the PWM counter.
+ */
+static inline void pwm_config_set_clkdiv(pwm_config *c, float div) {
+    c->div = (uint32_t)(div * (float)(1u << PWM_CH0_DIV_INT_LSB));
+}
+
+/** \brief Set PWM clock divider in a PWM configuration
+ *  \ingroup hardware_pwm
+ *
+ * \param c PWM configuration struct to modify
+ * \param div Integer value to reduce counting rate by. Must be greater than or equal to 1.
+ *
+ * If the divide mode is free-running, the PWM counter runs at clk_sys / div.
+ * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
+ * before passing them on to the PWM counter.
+ */
+static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) {
+    c->div = div << PWM_CH0_DIV_INT_LSB;
+}
+
+/** \brief Set PWM counting mode in a PWM configuration
+ *  \ingroup hardware_pwm
+ *
+ * \param c PWM configuration struct to modify
+ * \param mode PWM divide/count mode
+ *
+ * Configure which event gates the operation of the fractional divider.
+ * The default is always-on (free-running PWM). Can also be configured to count on
+ * high level, rising edge or falling edge of the B pin input.
+ */
+static inline void pwm_config_set_clkdiv_mode(pwm_config *c, enum pwm_clkdiv_mode mode) {
+    valid_params_if(PWM, mode == PWM_DIV_FREE_RUNNING ||
+            mode == PWM_DIV_B_RISING ||
+            mode == PWM_DIV_B_HIGH ||
+            mode == PWM_DIV_B_FALLING);
+    c->csr = (c->csr & ~PWM_CH0_CSR_DIVMODE_BITS)
+        | (((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB);
+}
+
+/** \brief Set output polarity in a PWM configuration
+ *  \ingroup hardware_pwm
+ *
+ * \param c PWM configuration struct to modify
+ * \param a true to invert output A
+ * \param b true to invert output B
+ */
+static inline void pwm_config_set_output_polarity(pwm_config *c, bool a, bool b) {
+    c->csr = (c->csr & ~(PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS))
+        | ((bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB) | (bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB));
+}
+
+/** \brief Set PWM counter wrap value in a PWM configuration
+ *  \ingroup hardware_pwm
+ *
+ * Set the highest value the counter will reach before returning to 0. Also known as TOP.
+ *
+ * \param c PWM configuration struct to modify
+ * \param wrap Value to set wrap to
+ */
+static inline void pwm_config_set_wrap(pwm_config *c, uint16_t wrap) {
+    c->top = wrap;
+}
+
+/** \brief Initialise a PWM with settings from a configuration object
+ *  \ingroup hardware_pwm
+ *
+ * Use the \ref pwm_get_default_config() function to initialise a config structure, make changes as
+ * needed using the pwm_config_* functions, then call this function to set up the PWM.
+ *
+ * \param slice_num PWM slice number
+ * \param c The configuration to use
+ * \param start If true the PWM will be started running once configured. If false you will need to start
+ *  manually using \ref pwm_set_enabled() or \ref pwm_set_mask_enabled()
+ */
+static inline void pwm_init(uint slice_num, pwm_config *c, bool start) {
+    check_slice_num_param(slice_num);
+    pwm_hw->slice[slice_num].csr = 0;
+
+    pwm_hw->slice[slice_num].ctr = PWM_CH0_CTR_RESET;
+    pwm_hw->slice[slice_num].cc = PWM_CH0_CC_RESET;
+    pwm_hw->slice[slice_num].top = c->top;
+    pwm_hw->slice[slice_num].div = c->div;
+    pwm_hw->slice[slice_num].csr = c->csr | (bool_to_bit(start) << PWM_CH0_CSR_EN_LSB);
+}
+
+/** \brief Get a set of default values for PWM configuration
+ *  \ingroup hardware_pwm
+ *
+ * PWM config is free-running at system clock speed, no phase correction, wrapping at 0xffff,
+ * with standard polarities for channels A and B.
+ *
+ * \return Set of default values.
+ */
+static inline pwm_config pwm_get_default_config(void) {
+    pwm_config c = {0, 0, 0};
+    pwm_config_set_phase_correct(&c, false);
+    pwm_config_set_clkdiv_int(&c, 1);
+    pwm_config_set_clkdiv_mode(&c, PWM_DIV_FREE_RUNNING);
+    pwm_config_set_output_polarity(&c, false, false);
+    pwm_config_set_wrap(&c, 0xffffu);
+    return c;
+}
+
+/** \brief Set the current PWM counter wrap value
+ *  \ingroup hardware_pwm
+ *
+ * Set the highest value the counter will reach before returning to 0. Also
+ * known as TOP.
+ *
+ * The counter wrap value is double-buffered in hardware. This means that,
+ * when the PWM is running, a write to the counter wrap value does not take
+ * effect until after the next time the PWM slice wraps (or, in phase-correct
+ * mode, the next time the slice reaches 0). If the PWM is not running, the
+ * write is latched in immediately.
+ *
+ * \param slice_num PWM slice number
+ * \param wrap Value to set wrap to
+ */
+static inline void pwm_set_wrap(uint slice_num, uint16_t wrap) {
+    check_slice_num_param(slice_num);
+    pwm_hw->slice[slice_num].top = wrap;
+}
+
+/** \brief Set the current PWM counter compare value for one channel
+ *  \ingroup hardware_pwm
+ *
+ * Set the value of the PWM counter compare value, for either channel A or channel B.
+ *
+ * The counter compare register is double-buffered in hardware. This means
+ * that, when the PWM is running, a write to the counter compare values does
+ * not take effect until the next time the PWM slice wraps (or, in
+ * phase-correct mode, the next time the slice reaches 0). If the PWM is not
+ * running, the write is latched in immediately.
+ *
+ * \param slice_num PWM slice number
+ * \param chan Which channel to update. 0 for A, 1 for B.
+ * \param level new level for the selected output
+ */
+static inline void pwm_set_chan_level(uint slice_num, uint chan, uint16_t level) {
+    check_slice_num_param(slice_num);
+    hw_write_masked(
+        &pwm_hw->slice[slice_num].cc,
+        ((uint)level) << (chan ? PWM_CH0_CC_B_LSB : PWM_CH0_CC_A_LSB),
+        chan ? PWM_CH0_CC_B_BITS : PWM_CH0_CC_A_BITS
+    );
+}
+
+/** \brief Set PWM counter compare values
+ *  \ingroup hardware_pwm
+ *
+ * Set the value of the PWM counter compare values, A and B.
+ *
+ * The counter compare register is double-buffered in hardware. This means
+ * that, when the PWM is running, a write to the counter compare values does
+ * not take effect until the next time the PWM slice wraps (or, in
+ * phase-correct mode, the next time the slice reaches 0). If the PWM is not
+ * running, the write is latched in immediately.
+ *
+ * \param slice_num PWM slice number
+ * \param level_a Value to set compare A to. When the counter reaches this value the A output is deasserted
+ * \param level_b Value to set compare B to. When the counter reaches this value the B output is deasserted
+ */
+static inline void pwm_set_both_levels(uint slice_num, uint16_t level_a, uint16_t level_b) {
+    check_slice_num_param(slice_num);
+    pwm_hw->slice[slice_num].cc = (((uint)level_b) << PWM_CH0_CC_B_LSB) | (((uint)level_a) << PWM_CH0_CC_A_LSB);
+}
+
+/** \brief Helper function to set the PWM level for the slice and channel associated with a GPIO.
+ *  \ingroup hardware_pwm
+ *
+ * Look up the correct slice (0 to 7) and channel (A or B) for a given GPIO, and update the corresponding
+ * counter compare field.
+ *
+ * This PWM slice should already have been configured and set running. Also be careful of multiple GPIOs
+ * mapping to the same slice and channel (if GPIOs have a difference of 16).
+ *
+ * The counter compare register is double-buffered in hardware. This means
+ * that, when the PWM is running, a write to the counter compare values does
+ * not take effect until the next time the PWM slice wraps (or, in
+ * phase-correct mode, the next time the slice reaches 0). If the PWM is not
+ * running, the write is latched in immediately.
+ *
+ * \param gpio GPIO to set level of
+ * \param level PWM level for this GPIO
+ */
+static inline void pwm_set_gpio_level(uint gpio, uint16_t level) {
+    valid_params_if(PWM, gpio < NUM_BANK0_GPIOS);
+    pwm_set_chan_level(pwm_gpio_to_slice_num(gpio), pwm_gpio_to_channel(gpio), level);
+}
+
+/** \brief Get PWM counter
+ *  \ingroup hardware_pwm
+ *
+ * Get current value of PWM counter
+ *
+ * \param slice_num PWM slice number
+ * \return Current value of the PWM counter
+ */
+static inline uint16_t pwm_get_counter(uint slice_num) {
+    check_slice_num_param(slice_num);
+    return (uint16_t)(pwm_hw->slice[slice_num].ctr);
+}
+
+/** \brief Set PWM counter
+ *  \ingroup hardware_pwm
+ *
+ * Set the value of the PWM counter
+ *
+ * \param slice_num PWM slice number
+ * \param c Value to set the PWM counter to
+ *
+ */
+static inline void pwm_set_counter(uint slice_num, uint16_t c) {
+    check_slice_num_param(slice_num);
+    pwm_hw->slice[slice_num].ctr = c;
+}
+
+/** \brief Advance PWM count
+ *  \ingroup hardware_pwm
+ *
+ * Advance the phase of a running the counter by 1 count.
+ *
+ * This function will return once the increment is complete.
+ *
+ * \param slice_num PWM slice number
+ */
+static inline void pwm_advance_count(uint slice_num) {
+    check_slice_num_param(slice_num);
+    hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_ADV_BITS);
+    while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_ADV_BITS) {
+        tight_loop_contents();
+    }
+}
+
+/** \brief Retard PWM count
+ *  \ingroup hardware_pwm
+ *
+ * Retard the phase of a running counter by 1 count
+ *
+ * This function will return once the retardation is complete.
+ *
+ * \param slice_num PWM slice number
+ */
+static inline void pwm_retard_count(uint slice_num) {
+    check_slice_num_param(slice_num);
+    hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_RET_BITS);
+    while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_RET_BITS) {
+        tight_loop_contents();
+    }
+}
+
+/** \brief Set PWM clock divider using an 8:4 fractional value
+ *  \ingroup hardware_pwm
+ *
+ * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating.
+ *
+ * \param slice_num PWM slice number
+ * \param integer  8 bit integer part of the clock divider
+ * \param fract 4 bit fractional part of the clock divider
+ */
+static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint8_t fract) {
+    check_slice_num_param(slice_num);
+    valid_params_if(PWM, fract < 16);
+    pwm_hw->slice[slice_num].div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB);
+}
+
+/** \brief Set PWM clock divider
+ *  \ingroup hardware_pwm
+ *
+ * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating.
+ *
+ * \param slice_num PWM slice number
+ * \param divider Floating point clock divider,  1.f <= value < 256.f
+ */
+static inline void pwm_set_clkdiv(uint slice_num, float divider) {
+    check_slice_num_param(slice_num);
+    valid_params_if(PWM, divider >= 1.f && divider < 256.f);
+    uint8_t i = (uint8_t)divider;
+    uint8_t f = (uint8_t)((divider - i) * (0x01 << 4));
+    pwm_set_clkdiv_int_frac(slice_num, i, f);
+}
+
+/** \brief Set PWM output polarity
+ *  \ingroup hardware_pwm
+ *
+ * \param slice_num PWM slice number
+ * \param a true to invert output A
+ * \param b true to invert output B
+ */
+static inline void pwm_set_output_polarity(uint slice_num, bool a, bool b) {
+    check_slice_num_param(slice_num);
+    hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB | bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB,
+                     PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS);
+}
+
+
+/** \brief Set PWM divider mode
+ *  \ingroup hardware_pwm
+ *
+ * \param slice_num PWM slice number
+ * \param mode Required divider mode
+ */
+static inline void pwm_set_clkdiv_mode(uint slice_num, enum pwm_clkdiv_mode mode) {
+    check_slice_num_param(slice_num);
+    valid_params_if(PWM, mode == PWM_DIV_FREE_RUNNING ||
+                         mode == PWM_DIV_B_RISING ||
+                         mode == PWM_DIV_B_HIGH ||
+                         mode == PWM_DIV_B_FALLING);
+    hw_write_masked(&pwm_hw->slice[slice_num].csr, ((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB, PWM_CH0_CSR_DIVMODE_BITS);
+}
+
+/** \brief Set PWM phase correct on/off
+ *  \ingroup hardware_pwm
+ *
+ * \param slice_num PWM slice number
+ * \param phase_correct true to set phase correct modulation, false to set trailing edge
+ *
+ * Setting phase control to true means that instead of wrapping back to zero when the wrap point is reached,
+ * the PWM starts counting back down. The output frequency is halved when phase-correct mode is enabled.
+ */
+static inline void pwm_set_phase_correct(uint slice_num, bool phase_correct) {
+    check_slice_num_param(slice_num);
+    hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB, PWM_CH0_CSR_PH_CORRECT_BITS);
+}
+
+/** \brief Enable/Disable PWM
+ *  \ingroup hardware_pwm
+ *
+ * When a PWM is disabled, it halts its counter, and the output pins are left
+ * high or low depending on exactly when the counter is halted. When
+ * re-enabled the PWM resumes immediately from where it left off.
+ *
+ * If the PWM's output pins need to be low when halted:
+ *
+ * - The counter compare can be set to zero whilst the PWM is enabled, and
+ *   then the PWM disabled once both pins are seen to be low
+ *
+ * - The GPIO output overrides can be used to force the actual pins low
+ *
+ * - The PWM can be run for one cycle (i.e. enabled then immediately disabled)
+ *   with a TOP of 0, count of 0 and counter compare of 0, to force the pins
+ *   low when the PWM has already been halted. The same method can be used
+ *   with a counter compare value of 1 to force a pin high.
+ *
+ * Note that, when disabled, the PWM can still be advanced one count at a time
+ * by pulsing the PH_ADV bit in its CSR. The output pins transition as though
+ * the PWM were enabled.
+ *
+ * \param slice_num PWM slice number
+ * \param enabled true to enable the specified PWM, false to disable.
+ */
+static inline void pwm_set_enabled(uint slice_num, bool enabled) {
+    check_slice_num_param(slice_num);
+    hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(enabled) << PWM_CH0_CSR_EN_LSB, PWM_CH0_CSR_EN_BITS);
+}
+
+/** \brief Enable/Disable multiple PWM slices simultaneously
+ *  \ingroup hardware_pwm
+ *
+ * \param mask Bitmap of PWMs to enable/disable. Bits 0 to 7 enable slices 0-7 respectively
+ */
+static inline void pwm_set_mask_enabled(uint32_t mask) {
+    pwm_hw->en = mask;
+}
+
+/*! \brief  Enable PWM instance interrupt
+ *  \ingroup hardware_pwm
+ *
+ * Used to enable a single PWM instance interrupt.
+ *
+ * \param slice_num PWM block to enable/disable
+ * \param enabled true to enable, false to disable
+ */
+static inline void pwm_set_irq_enabled(uint slice_num, bool enabled) {
+    check_slice_num_param(slice_num);
+    if (enabled) {
+        hw_set_bits(&pwm_hw->inte, 1u << slice_num);
+    } else {
+        hw_clear_bits(&pwm_hw->inte, 1u << slice_num);
+    }
+}
+
+/*! \brief  Enable multiple PWM instance interrupts
+ *  \ingroup hardware_pwm
+ *
+ * Use this to enable multiple PWM interrupts at once.
+ *
+ * \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
+ * \param enabled true to enable, false to disable
+ */
+static inline void pwm_set_irq_mask_enabled(uint32_t slice_mask, bool enabled) {
+    valid_params_if(PWM, slice_mask < 256);
+    if (enabled) {
+        hw_set_bits(&pwm_hw->inte, slice_mask);
+    } else {
+        hw_clear_bits(&pwm_hw->inte, slice_mask);
+    }
+}
+
+/*! \brief  Clear a single PWM channel interrupt
+ *  \ingroup hardware_pwm
+ *
+ * \param slice_num PWM slice number
+ */
+static inline void pwm_clear_irq(uint slice_num) {
+    pwm_hw->intr = 1u << slice_num;
+}
+
+/*! \brief  Get PWM interrupt status, raw
+ *  \ingroup hardware_pwm
+ *
+ * \return Bitmask of all PWM interrupts currently set
+ */
+static inline uint32_t pwm_get_irq_status_mask(void) {
+    return pwm_hw->ints;
+}
+
+/*! \brief  Force PWM interrupt
+ *  \ingroup hardware_pwm
+ *
+ * \param slice_num PWM slice number
+ */
+static inline void pwm_force_irq(uint slice_num) {
+    pwm_hw->intf = 1u << slice_num;
+}
+
+/*! \brief Return the DREQ to use for pacing transfers to a particular PWM slice
+ *  \ingroup hardware_pwm
+ *
+ * \param slice_num PWM slice number
+ */
+static inline uint pwm_get_dreq(uint slice_num) {
+    static_assert(DREQ_PWM_WRAP1 == DREQ_PWM_WRAP0 + 1, "");
+    static_assert(DREQ_PWM_WRAP7 == DREQ_PWM_WRAP0 + 7, "");
+    check_slice_num_param(slice_num);
+    return DREQ_PWM_WRAP0 + slice_num;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_resets/CMakeLists.txt b/src/rp2_common/hardware_resets/CMakeLists.txt
new file mode 100644
index 0000000..e0712e7
--- /dev/null
+++ b/src/rp2_common/hardware_resets/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_headers_only_target(resets)
diff --git a/src/rp2_common/hardware_resets/include/hardware/resets.h b/src/rp2_common/hardware_resets/include/hardware/resets.h
new file mode 100644
index 0000000..a3f7014
--- /dev/null
+++ b/src/rp2_common/hardware_resets/include/hardware/resets.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_RESETS_H
+#define _HARDWARE_RESETS_H
+
+#include "pico.h"
+#include "hardware/structs/resets.h"
+
+/** \file hardware/resets.h
+ *  \defgroup hardware_resets hardware_resets
+ *
+ * Hardware Reset API
+ *
+ * The reset controller allows software control of the resets to all of the peripherals that are not
+ * critical to boot the processor in the RP2040.
+ *
+ * \subsubsection reset_bitmask
+ * \addtogroup hardware_resets
+ *
+ * Multiple blocks are referred to using a bitmask as follows:
+ *
+ * Block to reset | Bit
+ * ---------------|----
+ * USB | 24
+ * UART 1 | 23
+ * UART 0 | 22
+ * Timer | 21
+ * TB Manager | 20
+ * SysInfo | 19
+ * System Config | 18
+ * SPI 1 | 17
+ * SPI 0 | 16
+ * RTC | 15
+ * PWM | 14
+ * PLL USB | 13
+ * PLL System | 12
+ * PIO 1 | 11
+ * PIO 0 | 10
+ * Pads - QSPI | 9
+ * Pads - bank 0 | 8
+ * JTAG | 7
+ * IO Bank 1 | 6
+ * IO Bank 0 | 5
+ * I2C 1 | 4
+ * I2C 0 | 3
+ * DMA | 2
+ * Bus Control | 1
+ * ADC 0 | 0
+ *
+ * \subsection reset_example Example
+ * \addtogroup hardware_resets
+ * \include hello_reset.c
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// \tag::reset_funcs[]
+
+/*! \brief Reset the specified HW blocks
+ *  \ingroup hardware_resets
+ *
+ * \param bits Bit pattern indicating blocks to reset. See \ref reset_bitmask
+ */
+static inline void reset_block(uint32_t bits) {
+    hw_set_bits(&resets_hw->reset, bits);
+}
+
+/*! \brief bring specified HW blocks out of reset
+ *  \ingroup hardware_resets
+ *
+ * \param bits Bit pattern indicating blocks to unreset. See \ref reset_bitmask
+ */
+static inline void unreset_block(uint32_t bits) {
+    hw_clear_bits(&resets_hw->reset, bits);
+}
+
+/*! \brief Bring specified HW blocks out of reset and wait for completion
+ *  \ingroup hardware_resets
+ *
+ * \param bits Bit pattern indicating blocks to unreset. See \ref reset_bitmask
+ */
+static inline void unreset_block_wait(uint32_t bits) {
+    hw_clear_bits(&resets_hw->reset, bits);
+    while (~resets_hw->reset_done & bits)
+        tight_loop_contents();
+}
+/// \end::reset_funcs[]
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_rtc/CMakeLists.txt b/src/rp2_common/hardware_rtc/CMakeLists.txt
new file mode 100644
index 0000000..dce6eff
--- /dev/null
+++ b/src/rp2_common/hardware_rtc/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(rtc)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_rtc/include/hardware/rtc.h b/src/rp2_common/hardware_rtc/include/hardware/rtc.h
new file mode 100644
index 0000000..8757e36
--- /dev/null
+++ b/src/rp2_common/hardware_rtc/include/hardware/rtc.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_RTC_H
+#define _HARDWARE_RTC_H
+
+#include "pico.h"
+#include "hardware/structs/rtc.h"
+
+/** \file hardware/rtc.h
+ *  \defgroup hardware_rtc hardware_rtc
+ *
+ * Hardware Real Time Clock API
+ *
+ * The RTC keeps track of time in human readable format and generates events when the time is equal
+ * to a preset value. Think of a digital clock, not epoch time used by most computers. There are seven
+ * fields, one each for year (12 bit), month (4 bit), day (5 bit), day of the week (3 bit), hour (5 bit)
+ * minute (6 bit) and second (6 bit), storing the data in binary format.
+ *
+ * \sa datetime_t
+ *
+ * \subsection rtc_example Example
+ * \addtogroup hardware_rtc
+ *
+ * \include hello_rtc.c
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! Callback function type for RTC alarms
+ *  \ingroup hardware_rtc
+ *
+ * \sa rtc_set_alarm()
+ */
+typedef void (*rtc_callback_t)(void);
+
+/*! \brief Initialise the RTC system
+ *  \ingroup hardware_rtc
+ */
+void rtc_init(void);
+
+/*! \brief Set the RTC to the specified time
+ *  \ingroup hardware_rtc
+ *
+ * \param t Pointer to a \ref datetime_t structure contains time to set
+ * \return true if set, false if the passed in datetime was invalid.
+ */
+bool rtc_set_datetime(datetime_t *t);
+
+/*! \brief Get the current time from the RTC
+ *  \ingroup hardware_rtc
+ *
+ * \param t Pointer to a \ref datetime_t structure to receive the current RTC time
+ * \return true if datetime is valid, false if the RTC is not running.
+ */
+bool rtc_get_datetime(datetime_t *t);
+
+/*! \brief Is the RTC running?
+ *  \ingroup hardware_rtc
+ *
+ */
+bool rtc_running(void);
+
+/*! \brief Set a time in the future for the RTC to call a user provided callback
+ *  \ingroup hardware_rtc
+ *
+ *  \param t Pointer to a \ref datetime_t structure containing a time in the future to fire the alarm. Any values set to -1 will not be matched on.
+ *  \param user_callback pointer to a \ref rtc_callback_t to call when the alarm fires
+ */
+void rtc_set_alarm(datetime_t *t, rtc_callback_t user_callback);
+
+/*! \brief Enable the RTC alarm (if inactive)
+ *  \ingroup hardware_rtc
+ */
+void rtc_enable_alarm(void);
+
+/*! \brief Disable the RTC alarm (if active)
+ *  \ingroup hardware_rtc
+ */
+void rtc_disable_alarm(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_rtc/rtc.c b/src/rp2_common/hardware_rtc/rtc.c
new file mode 100644
index 0000000..5429acd
--- /dev/null
+++ b/src/rp2_common/hardware_rtc/rtc.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+
+#include "hardware/irq.h"
+#include "hardware/rtc.h"
+#include "hardware/resets.h"
+#include "hardware/clocks.h"
+
+// Set this when setting an alarm
+static rtc_callback_t _callback = NULL;
+static bool _alarm_repeats = false;
+
+bool rtc_running(void) {
+    return (rtc_hw->ctrl & RTC_CTRL_RTC_ACTIVE_BITS);
+}
+
+void rtc_init(void) {
+    // Get clk_rtc freq and make sure it is running
+    uint rtc_freq = clock_get_hz(clk_rtc);
+    assert(rtc_freq != 0);
+
+    // Take rtc out of reset now that we know clk_rtc is running
+    reset_block(RESETS_RESET_RTC_BITS);
+    unreset_block_wait(RESETS_RESET_RTC_BITS);
+
+    // Set up the 1 second divider.
+    // If rtc_freq is 400 then clkdiv_m1 should be 399
+    rtc_freq -= 1;
+
+    // Check the freq is not too big to divide
+    assert(rtc_freq <= RTC_CLKDIV_M1_BITS);
+
+    // Write divide value
+    rtc_hw->clkdiv_m1 = rtc_freq;
+}
+
+static bool valid_datetime(datetime_t *t) {
+    // Valid ranges taken from RTC doc. Note when setting an RTC alarm
+    // these values are allowed to be -1 to say "don't match this value"
+    if (!(t->year >= 0 && t->year <= 4095)) return false;
+    if (!(t->month >= 1 && t->month <= 12)) return false;
+    if (!(t->day >= 1 && t->day <= 31)) return false;
+    if (!(t->dotw >= 0 && t->dotw <= 6)) return false;
+    if (!(t->hour >= 0 && t->hour <= 23)) return false;
+    if (!(t->min >= 0 && t->min <= 59)) return false;
+    if (!(t->sec >= 0 && t->sec <= 59)) return false;
+    return true;
+}
+
+bool rtc_set_datetime(datetime_t *t) {
+    if (!valid_datetime(t)) {
+        return false;
+    }
+
+    // Disable RTC
+    rtc_hw->ctrl = 0;
+    // Wait while it is still active
+    while (rtc_running()) {
+        tight_loop_contents();
+    }
+
+    // Write to setup registers
+    rtc_hw->setup_0 = (((uint)t->year)  << RTC_SETUP_0_YEAR_LSB ) |
+                      (((uint)t->month) << RTC_SETUP_0_MONTH_LSB) |
+                      (((uint)t->day)   << RTC_SETUP_0_DAY_LSB);
+    rtc_hw->setup_1 = (((uint)t->dotw)  << RTC_SETUP_1_DOTW_LSB) |
+                      (((uint)t->hour)  << RTC_SETUP_1_HOUR_LSB) |
+                      (((uint)t->min)   << RTC_SETUP_1_MIN_LSB)  |
+                      (((uint)t->sec)   << RTC_SETUP_1_SEC_LSB);
+
+    // Load setup values into rtc clock domain
+    rtc_hw->ctrl = RTC_CTRL_LOAD_BITS;
+
+    // Enable RTC and wait for it to be running
+    rtc_hw->ctrl = RTC_CTRL_RTC_ENABLE_BITS;
+    while (!rtc_running()) {
+        tight_loop_contents();
+    }
+
+    return true;
+}
+
+bool rtc_get_datetime(datetime_t *t) {
+    // Make sure RTC is running
+    if (!rtc_running()) {
+        return false;
+    }
+
+    // Note: RTC_0 should be read before RTC_1
+    uint32_t rtc_0 = rtc_hw->rtc_0;
+    uint32_t rtc_1 = rtc_hw->rtc_1;
+
+    t->dotw  = (rtc_0 & RTC_RTC_0_DOTW_BITS ) >> RTC_RTC_0_DOTW_LSB;
+    t->hour  = (rtc_0 & RTC_RTC_0_HOUR_BITS ) >> RTC_RTC_0_HOUR_LSB;
+    t->min   = (rtc_0 & RTC_RTC_0_MIN_BITS  ) >> RTC_RTC_0_MIN_LSB;
+    t->sec   = (rtc_0 & RTC_RTC_0_SEC_BITS  ) >> RTC_RTC_0_SEC_LSB;
+    t->year  = (rtc_1 & RTC_RTC_1_YEAR_BITS ) >> RTC_RTC_1_YEAR_LSB;
+    t->month = (rtc_1 & RTC_RTC_1_MONTH_BITS) >> RTC_RTC_1_MONTH_LSB;
+    t->day   = (rtc_1 & RTC_RTC_1_DAY_BITS  ) >> RTC_RTC_1_DAY_LSB;
+
+    return true;
+}
+
+void rtc_enable_alarm(void) {
+    // Set matching and wait for it to be enabled
+    hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MATCH_ENA_BITS);
+    while(!(rtc_hw->irq_setup_0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS)) {
+        tight_loop_contents();
+    }
+}
+
+static void rtc_irq_handler(void) {
+    // Always disable the alarm to clear the current IRQ.
+    // Even if it is a repeatable alarm, we don't want it to keep firing.
+    // If it matches on a second it can keep firing for that second.
+    rtc_disable_alarm();
+
+    if (_alarm_repeats) {
+        // If it is a repeatable alarm, re enable the alarm.
+        rtc_enable_alarm();
+    }
+
+    // Call user callback function
+    if (_callback) {
+        _callback();
+    }
+}
+
+static bool rtc_alarm_repeats(datetime_t *t) {
+    // If any value is set to -1 then we don't match on that value
+    // hence the alarm will eventually repeat
+    if (t->year  < 0) return true;
+    if (t->month < 0) return true;
+    if (t->day   < 0) return true;
+    if (t->dotw  < 0) return true;
+    if (t->hour  < 0) return true;
+    if (t->min   < 0) return true;
+    if (t->sec   < 0) return true;
+    return false;
+}
+
+void rtc_set_alarm(datetime_t *t, rtc_callback_t user_callback) {
+    rtc_disable_alarm();
+
+    // Only add to setup if it isn't -1
+    rtc_hw->irq_setup_0 = ((t->year  < 0) ? 0 : (((uint)t->year)  << RTC_IRQ_SETUP_0_YEAR_LSB )) |
+                          ((t->month < 0) ? 0 : (((uint)t->month) << RTC_IRQ_SETUP_0_MONTH_LSB)) |
+                          ((t->day   < 0) ? 0 : (((uint)t->day)   << RTC_IRQ_SETUP_0_DAY_LSB  ));
+    rtc_hw->irq_setup_1 = ((t->dotw  < 0) ? 0 : (((uint)t->dotw)  << RTC_IRQ_SETUP_1_DOTW_LSB)) |
+                          ((t->hour  < 0) ? 0 : (((uint)t->hour)  << RTC_IRQ_SETUP_1_HOUR_LSB)) |
+                          ((t->min   < 0) ? 0 : (((uint)t->min)   << RTC_IRQ_SETUP_1_MIN_LSB )) |
+                          ((t->sec   < 0) ? 0 : (((uint)t->sec)   << RTC_IRQ_SETUP_1_SEC_LSB ));
+
+    // Set the match enable bits for things we care about
+    if (t->year  >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_YEAR_ENA_BITS);
+    if (t->month >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MONTH_ENA_BITS);
+    if (t->day   >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_DAY_ENA_BITS);
+    if (t->dotw  >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_DOTW_ENA_BITS);
+    if (t->hour  >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_HOUR_ENA_BITS);
+    if (t->min   >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_MIN_ENA_BITS);
+    if (t->sec   >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_SEC_ENA_BITS);
+
+    // Does it repeat? I.e. do we not match on any of the bits
+    _alarm_repeats = rtc_alarm_repeats(t);
+
+    // Store function pointer we can call later
+    _callback = user_callback;
+
+    irq_set_exclusive_handler(RTC_IRQ, rtc_irq_handler);
+
+    // Enable the IRQ at the peri
+    rtc_hw->inte = RTC_INTE_RTC_BITS;
+
+    // Enable the IRQ at the proc
+    irq_set_enabled(RTC_IRQ, true);
+
+    rtc_enable_alarm();
+}
+
+void rtc_disable_alarm(void) {
+    // Disable matching and wait for it to stop being active
+    hw_clear_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MATCH_ENA_BITS);
+    while(rtc_hw->irq_setup_0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS) {
+        tight_loop_contents();
+    }
+}
diff --git a/src/rp2_common/hardware_spi/CMakeLists.txt b/src/rp2_common/hardware_spi/CMakeLists.txt
new file mode 100644
index 0000000..03e7f1f
--- /dev/null
+++ b/src/rp2_common/hardware_spi/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(spi)
diff --git a/src/rp2_common/hardware_spi/include/hardware/spi.h b/src/rp2_common/hardware_spi/include/hardware/spi.h
new file mode 100644
index 0000000..e8dc952
--- /dev/null
+++ b/src/rp2_common/hardware_spi/include/hardware/spi.h
@@ -0,0 +1,358 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_SPI_H
+#define _HARDWARE_SPI_H
+
+#include "pico.h"
+#include "pico/time.h"
+#include "hardware/structs/spi.h"
+#include "hardware/regs/dreq.h"
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SPI, Enable/disable assertions in the SPI module, type=bool, default=0, group=hardware_spi
+#ifndef PARAM_ASSERTIONS_ENABLED_SPI
+#define PARAM_ASSERTIONS_ENABLED_SPI 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file hardware/spi.h
+ *  \defgroup hardware_spi hardware_spi
+ *
+ * Hardware SPI API
+ *
+ * RP2040 has 2 identical instances of the Serial Peripheral Interface (SPI) controller.
+ *
+ * The PrimeCell SSP is a master or slave interface for synchronous serial communication with peripheral devices that have
+ * Motorola SPI, National Semiconductor Microwire, or Texas Instruments synchronous serial interfaces.
+ *
+ * Controller can be defined as master or slave using the \ref spi_set_slave function.
+ *
+ * Each controller can be connected to a number of GPIO pins, see the datasheet GPIO function selection table for more information.
+ */
+
+// PICO_CONFIG: PICO_DEFAULT_SPI, Define the default SPI for a board, min=0, max=1, group=hardware_spi
+// PICO_CONFIG: PICO_DEFAULT_SPI_SCK_PIN, Define the default SPI SCK pin, min=0, max=29, group=hardware_spi
+// PICO_CONFIG: PICO_DEFAULT_SPI_TX_PIN, Define the default SPI TX pin, min=0, max=29, group=hardware_spi
+// PICO_CONFIG: PICO_DEFAULT_SPI_RX_PIN, Define the default SPI RX pin, min=0, max=29, group=hardware_spi
+// PICO_CONFIG: PICO_DEFAULT_SPI_CSN_PIN, Define the default SPI CSN pin, min=0, max=29, group=hardware_spi
+
+/**
+ * Opaque type representing an SPI instance.
+ */
+typedef struct spi_inst spi_inst_t;
+
+/** Identifier for the first (SPI 0) hardware SPI instance (for use in SPI functions).
+ *
+ * e.g. spi_init(spi0, 48000)
+ *
+ *  \ingroup hardware_spi
+ */
+#define spi0 ((spi_inst_t * const)spi0_hw)
+
+/** Identifier for the second (SPI 1) hardware SPI instance (for use in SPI functions).
+ *
+ * e.g. spi_init(spi1, 48000)
+ *
+ *  \ingroup hardware_spi
+ */
+#define spi1 ((spi_inst_t * const)spi1_hw)
+
+#if !defined(PICO_DEFAULT_SPI_INSTANCE) && defined(PICO_DEFAULT_SPI)
+#define PICO_DEFAULT_SPI_INSTANCE (__CONCAT(spi,PICO_DEFAULT_SPI))
+#endif
+
+#ifdef PICO_DEFAULT_SPI_INSTANCE
+#define spi_default PICO_DEFAULT_SPI_INSTANCE
+#endif
+
+/** \brief Enumeration of SPI CPHA (clock phase) values.
+ *  \ingroup hardware_spi
+ */
+typedef enum {
+    SPI_CPHA_0 = 0,
+    SPI_CPHA_1 = 1
+} spi_cpha_t;
+
+/** \brief Enumeration of SPI CPOL (clock polarity) values.
+ *  \ingroup hardware_spi
+ */
+typedef enum {
+    SPI_CPOL_0 = 0,
+    SPI_CPOL_1 = 1
+} spi_cpol_t;
+
+/** \brief Enumeration of SPI bit-order values.
+ *  \ingroup hardware_spi
+ */
+typedef enum {
+    SPI_LSB_FIRST = 0,
+    SPI_MSB_FIRST = 1
+} spi_order_t;
+
+// ----------------------------------------------------------------------------
+// Setup
+
+/*! \brief Initialise SPI instances
+ *  \ingroup hardware_spi
+ * Puts the SPI into a known state, and enable it. Must be called before other
+ * functions.
+ *
+ * \note There is no guarantee that the baudrate requested can be achieved exactly; the nearest will be chosen
+ * and returned
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param baudrate Baudrate requested in Hz
+ * \return the actual baud rate set
+ */
+uint spi_init(spi_inst_t *spi, uint baudrate);
+
+/*! \brief Deinitialise SPI instances
+ *  \ingroup hardware_spi
+ * Puts the SPI into a disabled state. Init will need to be called to reenable the device
+ * functions.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ */
+void spi_deinit(spi_inst_t *spi);
+
+/*! \brief Set SPI baudrate
+ *  \ingroup hardware_spi
+ *
+ * Set SPI frequency as close as possible to baudrate, and return the actual
+ * achieved rate.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param baudrate Baudrate required in Hz, should be capable of a bitrate of at least 2Mbps, or higher, depending on system clock settings.
+ * \return The actual baudrate set
+ */
+uint spi_set_baudrate(spi_inst_t *spi, uint baudrate);
+
+/*! \brief Get SPI baudrate
+ *  \ingroup hardware_spi
+ *
+ * Get SPI baudrate which was set by \see spi_set_baudrate
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \return The actual baudrate set
+ */
+uint spi_get_baudrate(const spi_inst_t *spi);
+
+/*! \brief Convert SPI instance to hardware instance number
+ *  \ingroup hardware_spi
+ *
+ * \param spi SPI instance
+ * \return Number of SPI, 0 or 1.
+ */
+static inline uint spi_get_index(const spi_inst_t *spi) {
+    invalid_params_if(SPI, spi != spi0 && spi != spi1);
+    return spi == spi1 ? 1 : 0;
+}
+
+static inline spi_hw_t *spi_get_hw(spi_inst_t *spi) {
+    spi_get_index(spi); // check it is a hw spi
+    return (spi_hw_t *)spi;
+}
+
+static inline const spi_hw_t *spi_get_const_hw(const spi_inst_t *spi) {
+    spi_get_index(spi);  // check it is a hw spi
+    return (const spi_hw_t *)spi;
+}
+
+/*! \brief Configure SPI
+ *  \ingroup hardware_spi
+ *
+ * Configure how the SPI serialises and deserialises data on the wire
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param data_bits Number of data bits per transfer. Valid values 4..16.
+ * \param cpol SSPCLKOUT polarity, applicable to Motorola SPI frame format only.
+ * \param cpha SSPCLKOUT phase, applicable to Motorola SPI frame format only
+ * \param order Must be SPI_MSB_FIRST, no other values supported on the PL022
+ */
+static inline void spi_set_format(spi_inst_t *spi, uint data_bits, spi_cpol_t cpol, spi_cpha_t cpha, __unused spi_order_t order) {
+    invalid_params_if(SPI, data_bits < 4 || data_bits > 16);
+    // LSB-first not supported on PL022:
+    invalid_params_if(SPI, order != SPI_MSB_FIRST);
+    invalid_params_if(SPI, cpol != SPI_CPOL_0 && cpol != SPI_CPOL_1);
+    invalid_params_if(SPI, cpha != SPI_CPHA_0 && cpha != SPI_CPHA_1);
+    hw_write_masked(&spi_get_hw(spi)->cr0,
+                    ((uint)(data_bits - 1)) << SPI_SSPCR0_DSS_LSB |
+                    ((uint)cpol) << SPI_SSPCR0_SPO_LSB |
+                    ((uint)cpha) << SPI_SSPCR0_SPH_LSB,
+        SPI_SSPCR0_DSS_BITS |
+        SPI_SSPCR0_SPO_BITS |
+        SPI_SSPCR0_SPH_BITS);
+}
+
+/*! \brief Set SPI master/slave
+ *  \ingroup hardware_spi
+ *
+ * Configure the SPI for master- or slave-mode operation. By default,
+ * spi_init() sets master-mode.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param slave true to set SPI device as a slave device, false for master.
+ */
+static inline void spi_set_slave(spi_inst_t *spi, bool slave) {
+    if (slave)
+        hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_MS_BITS);
+    else
+        hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_MS_BITS);
+}
+
+// ----------------------------------------------------------------------------
+// Generic input/output
+
+/*! \brief Check whether a write can be done on SPI device
+ *  \ingroup hardware_spi
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \return false if no space is available to write. True if a write is possible
+ */
+static inline bool spi_is_writable(const spi_inst_t *spi) {
+    return (spi_get_const_hw(spi)->sr & SPI_SSPSR_TNF_BITS);
+}
+
+/*! \brief Check whether a read can be done on SPI device
+ *  \ingroup hardware_spi
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \return true if a read is possible i.e. data is present
+ */
+static inline bool spi_is_readable(const spi_inst_t *spi) {
+    return (spi_get_const_hw(spi)->sr & SPI_SSPSR_RNE_BITS);
+}
+
+/*! \brief Check whether SPI is busy
+ *  \ingroup hardware_spi
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \return true if SPI is busy
+ */
+static inline bool spi_is_busy(const spi_inst_t *spi) {
+    return (spi_get_const_hw(spi)->sr & SPI_SSPSR_BSY_BITS);
+}
+
+/*! \brief Write/Read to/from an SPI device
+ *  \ingroup hardware_spi
+ *
+ * Write \p len bytes from \p src to SPI. Simultaneously read \p len bytes from SPI to \p dst.
+ * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param src Buffer of data to write
+ * \param dst Buffer for read data
+ * \param len Length of BOTH buffers
+ * \return Number of bytes written/read
+*/
+int spi_write_read_blocking(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len);
+
+/*! \brief Write to an SPI device, blocking
+ *  \ingroup hardware_spi
+ *
+ * Write \p len bytes from \p src to SPI, and discard any data received back
+ * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param src Buffer of data to write
+ * \param len Length of \p src
+ * \return Number of bytes written/read
+ */
+int spi_write_blocking(spi_inst_t *spi, const uint8_t *src, size_t len);
+
+/*! \brief Read from an SPI device
+ *  \ingroup hardware_spi
+ *
+ * Read \p len bytes from SPI to \p dst.
+ * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate.
+ * \p repeated_tx_data is output repeatedly on TX as data is read in from RX.
+ * Generally this can be 0, but some devices require a specific value here,
+ * e.g. SD cards expect 0xff
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param repeated_tx_data Buffer of data to write
+ * \param dst Buffer for read data
+ * \param len Length of buffer \p dst
+ * \return Number of bytes written/read
+ */
+int spi_read_blocking(spi_inst_t *spi, uint8_t repeated_tx_data, uint8_t *dst, size_t len);
+
+// ----------------------------------------------------------------------------
+// SPI-specific operations and aliases
+
+// FIXME need some instance-private data for select() and deselect() if we are going that route
+
+/*! \brief Write/Read half words to/from an SPI device
+ *  \ingroup hardware_spi
+ *
+ * Write \p len halfwords from \p src to SPI. Simultaneously read \p len halfwords from SPI to \p dst.
+ * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate.
+ *
+ * \note SPI should be initialised with 16 data_bits using \ref spi_set_format first, otherwise this function will only read/write 8 data_bits.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param src Buffer of data to write
+ * \param dst Buffer for read data
+ * \param len Length of BOTH buffers in halfwords
+ * \return Number of halfwords written/read
+*/
+int spi_write16_read16_blocking(spi_inst_t *spi, const uint16_t *src, uint16_t *dst, size_t len);
+
+/*! \brief Write to an SPI device
+ *  \ingroup hardware_spi
+ *
+ * Write \p len halfwords from \p src to SPI. Discard any data received back.
+ * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate.
+ *
+ * \note SPI should be initialised with 16 data_bits using \ref spi_set_format first, otherwise this function will only write 8 data_bits.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param src Buffer of data to write
+ * \param len Length of buffers
+ * \return Number of halfwords written/read
+*/
+int spi_write16_blocking(spi_inst_t *spi, const uint16_t *src, size_t len);
+
+/*! \brief Read from an SPI device
+ *  \ingroup hardware_spi
+ *
+ * Read \p len halfwords from SPI to \p dst.
+ * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate.
+ * \p repeated_tx_data is output repeatedly on TX as data is read in from RX.
+ * Generally this can be 0, but some devices require a specific value here,
+ * e.g. SD cards expect 0xff
+ *
+ * \note SPI should be initialised with 16 data_bits using \ref spi_set_format first, otherwise this function will only read 8 data_bits.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param repeated_tx_data Buffer of data to write
+ * \param dst Buffer for read data
+ * \param len Length of buffer \p dst in halfwords
+ * \return Number of halfwords written/read
+ */
+int spi_read16_blocking(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len);
+
+/*! \brief Return the DREQ to use for pacing transfers to/from a particular SPI instance
+ *  \ingroup hardware_spi
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param is_tx true for sending data to the SPI instance, false for receiving data from the SPI instance
+ */
+static inline uint spi_get_dreq(spi_inst_t *spi, bool is_tx) {
+    static_assert(DREQ_SPI0_RX == DREQ_SPI0_TX + 1, "");
+    static_assert(DREQ_SPI1_RX == DREQ_SPI1_TX + 1, "");
+    static_assert(DREQ_SPI1_TX == DREQ_SPI0_TX + 2, "");
+    return DREQ_SPI0_TX + spi_get_index(spi) * 2 + !is_tx;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_spi/spi.c b/src/rp2_common/hardware_spi/spi.c
new file mode 100644
index 0000000..880b534
--- /dev/null
+++ b/src/rp2_common/hardware_spi/spi.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/resets.h"
+#include "hardware/clocks.h"
+#include "hardware/spi.h"
+
+static inline void spi_reset(spi_inst_t *spi) {
+    invalid_params_if(SPI, spi != spi0 && spi != spi1);
+    reset_block(spi == spi0 ? RESETS_RESET_SPI0_BITS : RESETS_RESET_SPI1_BITS);
+}
+
+static inline void spi_unreset(spi_inst_t *spi) {
+    invalid_params_if(SPI, spi != spi0 && spi != spi1);
+    unreset_block_wait(spi == spi0 ? RESETS_RESET_SPI0_BITS : RESETS_RESET_SPI1_BITS);
+}
+
+uint spi_init(spi_inst_t *spi, uint baudrate) {
+    spi_reset(spi);
+    spi_unreset(spi);
+
+    uint baud = spi_set_baudrate(spi, baudrate);
+    spi_set_format(spi, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);
+    // Always enable DREQ signals -- harmless if DMA is not listening
+    hw_set_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS);
+
+    // Finally enable the SPI
+    hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS);
+    return baud;
+}
+
+void spi_deinit(spi_inst_t *spi) {
+    hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS);
+    hw_clear_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS);
+    spi_reset(spi);
+}
+
+uint spi_set_baudrate(spi_inst_t *spi, uint baudrate) {
+    uint freq_in = clock_get_hz(clk_peri);
+    uint prescale, postdiv;
+    invalid_params_if(SPI, baudrate > freq_in);
+
+    // Find smallest prescale value which puts output frequency in range of
+    // post-divide. Prescale is an even number from 2 to 254 inclusive.
+    for (prescale = 2; prescale <= 254; prescale += 2) {
+        if (freq_in < (prescale + 2) * 256 * (uint64_t) baudrate)
+            break;
+    }
+    invalid_params_if(SPI, prescale > 254); // Frequency too low
+
+    // Find largest post-divide which makes output <= baudrate. Post-divide is
+    // an integer in the range 1 to 256 inclusive.
+    for (postdiv = 256; postdiv > 1; --postdiv) {
+        if (freq_in / (prescale * (postdiv - 1)) > baudrate)
+            break;
+    }
+
+    spi_get_hw(spi)->cpsr = prescale;
+    hw_write_masked(&spi_get_hw(spi)->cr0, (postdiv - 1) << SPI_SSPCR0_SCR_LSB, SPI_SSPCR0_SCR_BITS);
+
+    // Return the frequency we were able to achieve
+    return freq_in / (prescale * postdiv);
+}
+
+uint spi_get_baudrate(const spi_inst_t *spi) {
+    uint prescale = spi_get_const_hw(spi)->cpsr;
+    uint postdiv = ((spi_get_const_hw(spi)->cr0  & SPI_SSPCR0_SCR_BITS) >> SPI_SSPCR0_SCR_LSB) + 1;
+    return clock_get_hz(clk_peri) / (prescale * postdiv);
+}
+
+// Write len bytes from src to SPI. Simultaneously read len bytes from SPI to dst.
+// Note this function is guaranteed to exit in a known amount of time (bits sent * time per bit)
+int __not_in_flash_func(spi_write_read_blocking)(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len) {
+    invalid_params_if(SPI, 0 > (int)len);
+
+    // Never have more transfers in flight than will fit into the RX FIFO,
+    // else FIFO will overflow if this code is heavily interrupted.
+    const size_t fifo_depth = 8;
+    size_t rx_remaining = len, tx_remaining = len;
+
+    while (rx_remaining || tx_remaining) {
+        if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) {
+            spi_get_hw(spi)->dr = (uint32_t) *src++;
+            --tx_remaining;
+        }
+        if (rx_remaining && spi_is_readable(spi)) {
+            *dst++ = (uint8_t) spi_get_hw(spi)->dr;
+            --rx_remaining;
+        }
+    }
+
+    return (int)len;
+}
+
+// Write len bytes directly from src to the SPI, and discard any data received back
+int __not_in_flash_func(spi_write_blocking)(spi_inst_t *spi, const uint8_t *src, size_t len) {
+    invalid_params_if(SPI, 0 > (int)len);
+    // Write to TX FIFO whilst ignoring RX, then clean up afterward. When RX
+    // is full, PL022 inhibits RX pushes, and sets a sticky flag on
+    // push-on-full, but continues shifting. Safe if SSPIMSC_RORIM is not set.
+    for (size_t i = 0; i < len; ++i) {
+        while (!spi_is_writable(spi))
+            tight_loop_contents();
+        spi_get_hw(spi)->dr = (uint32_t)src[i];
+    }
+    // Drain RX FIFO, then wait for shifting to finish (which may be *after*
+    // TX FIFO drains), then drain RX FIFO again
+    while (spi_is_readable(spi))
+        (void)spi_get_hw(spi)->dr;
+    while (spi_get_hw(spi)->sr & SPI_SSPSR_BSY_BITS)
+        tight_loop_contents();
+    while (spi_is_readable(spi))
+        (void)spi_get_hw(spi)->dr;
+
+    // Don't leave overrun flag set
+    spi_get_hw(spi)->icr = SPI_SSPICR_RORIC_BITS;
+
+    return (int)len;
+}
+
+// Read len bytes directly from the SPI to dst.
+// repeated_tx_data is output repeatedly on SO as data is read in from SI.
+// Generally this can be 0, but some devices require a specific value here,
+// e.g. SD cards expect 0xff
+int __not_in_flash_func(spi_read_blocking)(spi_inst_t *spi, uint8_t repeated_tx_data, uint8_t *dst, size_t len) {
+    invalid_params_if(SPI, 0 > (int)len);
+    const size_t fifo_depth = 8;
+    size_t rx_remaining = len, tx_remaining = len;
+
+    while (rx_remaining || tx_remaining) {
+        if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) {
+            spi_get_hw(spi)->dr = (uint32_t) repeated_tx_data;
+            --tx_remaining;
+        }
+        if (rx_remaining && spi_is_readable(spi)) {
+            *dst++ = (uint8_t) spi_get_hw(spi)->dr;
+            --rx_remaining;
+        }
+    }
+
+    return (int)len;
+}
+
+// Write len halfwords from src to SPI. Simultaneously read len halfwords from SPI to dst.
+int __not_in_flash_func(spi_write16_read16_blocking)(spi_inst_t *spi, const uint16_t *src, uint16_t *dst, size_t len) {
+    invalid_params_if(SPI, 0 > (int)len);
+    // Never have more transfers in flight than will fit into the RX FIFO,
+    // else FIFO will overflow if this code is heavily interrupted.
+    const size_t fifo_depth = 8;
+    size_t rx_remaining = len, tx_remaining = len;
+
+    while (rx_remaining || tx_remaining) {
+        if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) {
+            spi_get_hw(spi)->dr = (uint32_t) *src++;
+            --tx_remaining;
+        }
+        if (rx_remaining && spi_is_readable(spi)) {
+            *dst++ = (uint16_t) spi_get_hw(spi)->dr;
+            --rx_remaining;
+        }
+    }
+
+    return (int)len;
+}
+
+// Write len bytes directly from src to the SPI, and discard any data received back
+int __not_in_flash_func(spi_write16_blocking)(spi_inst_t *spi, const uint16_t *src, size_t len) {
+    invalid_params_if(SPI, 0 > (int)len);
+    // Deliberately overflow FIFO, then clean up afterward, to minimise amount
+    // of APB polling required per halfword
+    for (size_t i = 0; i < len; ++i) {
+        while (!spi_is_writable(spi))
+            tight_loop_contents();
+        spi_get_hw(spi)->dr = (uint32_t)src[i];
+    }
+
+    while (spi_is_readable(spi))
+        (void)spi_get_hw(spi)->dr;
+    while (spi_get_hw(spi)->sr & SPI_SSPSR_BSY_BITS)
+        tight_loop_contents();
+    while (spi_is_readable(spi))
+        (void)spi_get_hw(spi)->dr;
+
+    // Don't leave overrun flag set
+    spi_get_hw(spi)->icr = SPI_SSPICR_RORIC_BITS;
+
+    return (int)len;
+}
+
+// Read len halfwords directly from the SPI to dst.
+// repeated_tx_data is output repeatedly on SO as data is read in from SI.
+int __not_in_flash_func(spi_read16_blocking)(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len) {
+    invalid_params_if(SPI, 0 > (int)len);
+    const size_t fifo_depth = 8;
+    size_t rx_remaining = len, tx_remaining = len;
+
+    while (rx_remaining || tx_remaining) {
+        if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) {
+            spi_get_hw(spi)->dr = (uint32_t) repeated_tx_data;
+            --tx_remaining;
+        }
+        if (rx_remaining && spi_is_readable(spi)) {
+            *dst++ = (uint16_t) spi_get_hw(spi)->dr;
+            --rx_remaining;
+        }
+    }
+
+    return (int)len;
+}
diff --git a/src/rp2_common/hardware_sync/CMakeLists.txt b/src/rp2_common/hardware_sync/CMakeLists.txt
new file mode 100644
index 0000000..1c64ed6
--- /dev/null
+++ b/src/rp2_common/hardware_sync/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(sync)
diff --git a/src/rp2_common/hardware_sync/include/hardware/sync.h b/src/rp2_common/hardware_sync/include/hardware/sync.h
new file mode 100644
index 0000000..8f91d55
--- /dev/null
+++ b/src/rp2_common/hardware_sync/include/hardware/sync.h
@@ -0,0 +1,403 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_SYNC_H
+#define _HARDWARE_SYNC_H
+
+#include "pico.h"
+#include "hardware/address_mapped.h"
+#include "hardware/regs/sio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file hardware/sync.h
+ *  \defgroup hardware_sync hardware_sync
+ *
+ * Low level hardware spin locks, barrier and processor event APIs
+ *
+ * Spin Locks
+ * ----------
+ *
+ * The RP2040 provides 32 hardware spin locks, which can be used to manage mutually-exclusive access to shared software
+ * and hardware resources.
+ *
+ * Generally each spin lock itself is a shared resource,
+ * i.e. the same hardware spin lock can be used by multiple higher level primitives (as long as the spin locks are neither held for long periods, nor
+ * held concurrently with other spin locks by the same core - which could lead to deadlock). A hardware spin lock that is exclusively owned can be used
+ * individually without more flexibility and without regard to other software. Note that no hardware spin lock may
+ * be acquired re-entrantly (i.e. hardware spin locks are not on their own safe for use by both thread code and IRQs) however the default spinlock related
+ * methods here (e.g. \ref spin_lock_blocking) always disable interrupts while the lock is held as use by IRQ handlers and user code is common/desirable,
+ * and spin locks are only expected to be held for brief periods.
+ *
+ * The SDK uses the following default spin lock assignments, classifying which spin locks are reserved for exclusive/special purposes
+ * vs those suitable for more general shared use:
+ *
+ * Number (ID) | Description
+ * :---------: | -----------
+ * 0-13        | Currently reserved for exclusive use by the SDK and other libraries. If you use these spin locks, you risk breaking SDK or other library functionality. Each reserved spin lock used individually has its own PICO_SPINLOCK_ID so you can search for those.
+ * 14,15       | (\ref PICO_SPINLOCK_ID_OS1 and \ref PICO_SPINLOCK_ID_OS2). Currently reserved for exclusive use by an operating system (or other system level software) co-existing with the SDK.
+ * 16-23       | (\ref PICO_SPINLOCK_ID_STRIPED_FIRST - \ref PICO_SPINLOCK_ID_STRIPED_LAST). Spin locks from this range are assigned in a round-robin fashion via \ref next_striped_spin_lock_num(). These spin locks are shared, but assigning numbers from a range reduces the probability that two higher level locking primitives using _striped_ spin locks will actually be using the same spin lock.
+ * 24-31       | (\ref PICO_SPINLOCK_ID_CLAIM_FREE_FIRST - \ref PICO_SPINLOCK_ID_CLAIM_FREE_LAST). These are reserved for exclusive use and are allocated on a first come first served basis at runtime via \ref spin_lock_claim_unused()
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SYNC, Enable/disable assertions in the HW sync module, type=bool, default=0, group=hardware_sync
+#ifndef PARAM_ASSERTIONS_ENABLED_SYNC
+#define PARAM_ASSERTIONS_ENABLED_SYNC 0
+#endif
+
+/** \brief A spin lock identifier
+ * \ingroup hardware_sync
+ */
+typedef volatile uint32_t spin_lock_t;
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_IRQ, Spinlock ID for IRQ protection, min=0, max=31, default=9, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_IRQ
+#define PICO_SPINLOCK_ID_IRQ 9
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_TIMER, Spinlock ID for Timer protection, min=0, max=31, default=10, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_TIMER
+#define PICO_SPINLOCK_ID_TIMER 10
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_HARDWARE_CLAIM, Spinlock ID for Hardware claim protection, min=0, max=31, default=11, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_HARDWARE_CLAIM
+#define PICO_SPINLOCK_ID_HARDWARE_CLAIM 11
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_OS1, First Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=14, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_OS1
+#define PICO_SPINLOCK_ID_OS1 14
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_OS2, Second Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=15, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_OS2
+#define PICO_SPINLOCK_ID_OS2 15
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Lowest Spinlock ID in the 'striped' range, min=0, max=31, default=16, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_STRIPED_FIRST
+#define PICO_SPINLOCK_ID_STRIPED_FIRST 16
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Highest Spinlock ID in the 'striped' range, min=0, max=31, default=23, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_STRIPED_LAST
+#define PICO_SPINLOCK_ID_STRIPED_LAST 23
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Lowest Spinlock ID in the 'claim free' range, min=0, max=31, default=24, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_FIRST
+#define PICO_SPINLOCK_ID_CLAIM_FREE_FIRST 24
+#endif
+
+#ifdef PICO_SPINLOCK_ID_CLAIM_FREE_END
+#warning PICO_SPINLOCK_ID_CLAIM_FREE_END has been renamed to PICO_SPINLOCK_ID_CLAIM_FREE_LAST
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_LAST, Highest Spinlock ID in the 'claim free' range, min=0, max=31, default=31, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_LAST
+#define PICO_SPINLOCK_ID_CLAIM_FREE_LAST 31
+#endif
+
+/*! \brief Insert a SEV instruction in to the code path.
+ *  \ingroup hardware_sync
+
+ * The SEV (send event) instruction sends an event to both cores.
+ */
+__force_inline static void __sev(void) {
+    __asm volatile ("sev");
+}
+
+/*! \brief Insert a WFE instruction in to the code path.
+ *  \ingroup hardware_sync
+ *
+ * The WFE (wait for event) instruction waits until one of a number of
+ * events occurs, including events signalled by the SEV instruction on either core.
+ */
+__force_inline static void __wfe(void) {
+    __asm volatile ("wfe");
+}
+
+/*! \brief Insert a WFI instruction in to the code path.
+  *  \ingroup hardware_sync
+*
+ * The WFI (wait for interrupt) instruction waits for a interrupt to wake up the core.
+ */
+__force_inline static void __wfi(void) {
+    __asm volatile ("wfi");
+}
+
+/*! \brief Insert a DMB instruction in to the code path.
+ *  \ingroup hardware_sync
+ *
+ * The DMB (data memory barrier) acts as a memory barrier, all memory accesses prior to this
+ * instruction will be observed before any explicit access after the instruction.
+ */
+__force_inline static void __dmb(void) {
+    __asm volatile ("dmb" : : : "memory");
+}
+
+/*! \brief Insert a DSB instruction in to the code path.
+ *  \ingroup hardware_sync
+ *
+ * The DSB (data synchronization barrier) acts as a special kind of data
+ * memory barrier (DMB). The DSB operation completes when all explicit memory
+ * accesses before this instruction complete.
+ */
+__force_inline static void __dsb(void) {
+    __asm volatile ("dsb" : : : "memory");
+}
+
+/*! \brief Insert a ISB instruction in to the code path.
+ *  \ingroup hardware_sync
+ *
+ * ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor,
+ * so that all instructions following the ISB are fetched from cache or memory again, after
+ * the ISB instruction has been completed.
+ */
+__force_inline static void __isb(void) {
+    __asm volatile ("isb");
+}
+
+/*! \brief Acquire a memory fence
+ *  \ingroup hardware_sync
+ */
+__force_inline static void __mem_fence_acquire(void) {
+    // the original code below makes it hard for us to be included from C++ via a header
+    // which itself is in an extern "C", so just use __dmb instead, which is what
+    // is required on Cortex M0+
+    __dmb();
+//#ifndef __cplusplus
+//    atomic_thread_fence(memory_order_acquire);
+//#else
+//    std::atomic_thread_fence(std::memory_order_acquire);
+//#endif
+}
+
+/*! \brief Release a memory fence
+ *  \ingroup hardware_sync
+ *
+ */
+__force_inline static void __mem_fence_release(void) {
+    // the original code below makes it hard for us to be included from C++ via a header
+    // which itself is in an extern "C", so just use __dmb instead, which is what
+    // is required on Cortex M0+
+    __dmb();
+//#ifndef __cplusplus
+//    atomic_thread_fence(memory_order_release);
+//#else
+//    std::atomic_thread_fence(std::memory_order_release);
+//#endif
+}
+
+/*! \brief Save and disable interrupts
+ *  \ingroup hardware_sync
+ *
+ * \return The prior interrupt enable status for restoration later via restore_interrupts()
+ */
+__force_inline static uint32_t save_and_disable_interrupts(void) {
+    uint32_t status;
+    __asm volatile ("mrs %0, PRIMASK" : "=r" (status)::);
+    __asm volatile ("cpsid i");
+    return status;
+}
+
+/*! \brief Restore interrupts to a specified state
+ *  \ingroup hardware_sync
+ *
+ * \param status Previous interrupt status from save_and_disable_interrupts()
+  */
+__force_inline static void restore_interrupts(uint32_t status) {
+    __asm volatile ("msr PRIMASK,%0"::"r" (status) : );
+}
+
+/*! \brief Get HW Spinlock instance from number
+ *  \ingroup hardware_sync
+ *
+ * \param lock_num Spinlock ID
+ * \return The spinlock instance
+ */
+__force_inline static spin_lock_t *spin_lock_instance(uint lock_num) {
+    invalid_params_if(SYNC, lock_num >= NUM_SPIN_LOCKS);
+    return (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET + lock_num * 4);
+}
+
+/*! \brief Get HW Spinlock number from instance
+ *  \ingroup hardware_sync
+ *
+ * \param lock The Spinlock instance
+ * \return The Spinlock ID
+ */
+__force_inline static uint spin_lock_get_num(spin_lock_t *lock) {
+    invalid_params_if(SYNC, (uint) lock < SIO_BASE + SIO_SPINLOCK0_OFFSET ||
+                            (uint) lock >= NUM_SPIN_LOCKS * sizeof(spin_lock_t) + SIO_BASE + SIO_SPINLOCK0_OFFSET ||
+                            ((uint) lock - SIO_BASE + SIO_SPINLOCK0_OFFSET) % sizeof(spin_lock_t) != 0);
+    return (uint) (lock - (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET));
+}
+
+/*! \brief Acquire a spin lock without disabling interrupts (hence unsafe)
+ *  \ingroup hardware_sync
+ *
+ * \param lock Spinlock instance
+ */
+__force_inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) {
+    // Note we don't do a wfe or anything, because by convention these spin_locks are VERY SHORT LIVED and NEVER BLOCK and run
+    // with INTERRUPTS disabled (to ensure that)... therefore nothing on our core could be blocking us, so we just need to wait on another core
+    // anyway which should be finished soon
+    while (__builtin_expect(!*lock, 0));
+    __mem_fence_acquire();
+}
+
+/*! \brief Release a spin lock without re-enabling interrupts
+ *  \ingroup hardware_sync
+ *
+ * \param lock Spinlock instance
+ */
+__force_inline static void spin_unlock_unsafe(spin_lock_t *lock) {
+    __mem_fence_release();
+    *lock = 0;
+}
+
+/*! \brief Acquire a spin lock safely
+ *  \ingroup hardware_sync
+ *
+ * This function will disable interrupts prior to acquiring the spinlock
+ *
+ * \param lock Spinlock instance
+ * \return interrupt status to be used when unlocking, to restore to original state
+ */
+__force_inline static uint32_t spin_lock_blocking(spin_lock_t *lock) {
+    uint32_t save = save_and_disable_interrupts();
+    spin_lock_unsafe_blocking(lock);
+    return save;
+}
+
+/*! \brief Check to see if a spinlock is currently acquired elsewhere.
+ *  \ingroup hardware_sync
+ *
+ * \param lock Spinlock instance
+ */
+inline static bool is_spin_locked(spin_lock_t *lock) {
+    check_hw_size(spin_lock_t, 4);
+    uint lock_num = spin_lock_get_num(lock);
+    return 0 != (*(io_ro_32 *) (SIO_BASE + SIO_SPINLOCK_ST_OFFSET) & (1u << lock_num));
+}
+
+/*! \brief Release a spin lock safely
+ *  \ingroup hardware_sync
+ *
+ * This function will re-enable interrupts according to the parameters.
+ *
+ * \param lock Spinlock instance
+ * \param saved_irq Return value from the \ref spin_lock_blocking() function.
+ * \return interrupt status to be used when unlocking, to restore to original state
+ *
+ * \sa spin_lock_blocking()
+ */
+__force_inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) {
+    spin_unlock_unsafe(lock);
+    restore_interrupts(saved_irq);
+}
+
+/*! \brief Get the current core number
+ *  \ingroup hardware_sync
+ *
+ * \return The core number the call was made from
+ */
+__force_inline static uint get_core_num(void) {
+    return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET));
+}
+
+/*! \brief Initialise a spin lock
+ *  \ingroup hardware_sync
+ *
+ * The spin lock is initially unlocked
+ *
+ * \param lock_num The spin lock number
+ * \return The spin lock instance
+ */
+spin_lock_t *spin_lock_init(uint lock_num);
+
+/*! \brief Release all spin locks
+ *  \ingroup hardware_sync
+ */
+void spin_locks_reset(void);
+
+/*! \brief Return a spin lock number from the _striped_ range
+ *  \ingroup hardware_sync
+ *
+ * Returns a spin lock number in the range PICO_SPINLOCK_ID_STRIPED_FIRST to PICO_SPINLOCK_ID_STRIPED_LAST
+ * in a round robin fashion. This does not grant the caller exclusive access to the spin lock, so the caller
+ * must:
+ *
+ * -# Abide (with other callers) by the contract of only holding this spin lock briefly (and with IRQs disabled - the default via \ref spin_lock_blocking()),
+ * and not whilst holding other spin locks.
+ * -# Be OK with any contention caused by the - brief due to the above requirement - contention with other possible users of the spin lock.
+ *
+ * \return lock_num a spin lock number the caller may use (non exclusively)
+ * \see PICO_SPINLOCK_ID_STRIPED_FIRST
+ * \see PICO_SPINLOCK_ID_STRIPED_LAST
+ */
+uint next_striped_spin_lock_num(void);
+
+/*! \brief Mark a spin lock as used
+ *  \ingroup hardware_sync
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if the spin lock
+ * is already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param lock_num the spin lock number
+ */
+void spin_lock_claim(uint lock_num);
+
+/*! \brief Mark multiple spin locks as used
+ *  \ingroup hardware_sync
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if any of the spin locks
+ * are already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param lock_num_mask Bitfield of all required spin locks to claim (bit 0 == spin lock 0, bit 1 == spin lock 1 etc)
+ */
+void spin_lock_claim_mask(uint32_t lock_num_mask);
+
+/*! \brief Mark a spin lock as no longer used
+ *  \ingroup hardware_sync
+ *
+ * Method for cooperative claiming of hardware.
+ *
+ * \param lock_num the spin lock number to release
+ */
+void spin_lock_unclaim(uint lock_num);
+
+/*! \brief Claim a free spin lock
+ *  \ingroup hardware_sync
+ *
+ * \param required if true the function will panic if none are available
+ * \return the spin lock number or -1 if required was false, and none were free
+ */
+int spin_lock_claim_unused(bool required);
+
+/*! \brief Determine if a spin lock is claimed
+ *  \ingroup hardware_sync
+ *
+ * \param lock_num the spin lock number
+ * \return true if claimed, false otherwise
+ * \see spin_lock_claim
+ * \see spin_lock_claim_mask
+ */
+bool spin_lock_is_claimed(uint lock_num);
+
+#define remove_volatile_cast(t, x) ({__mem_fence_acquire(); (t)(x); })
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_sync/sync.c b/src/rp2_common/hardware_sync/sync.c
new file mode 100644
index 0000000..a15c8d6
--- /dev/null
+++ b/src/rp2_common/hardware_sync/sync.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/sync.h"
+#include "hardware/claim.h"
+
+static_assert(PICO_SPINLOCK_ID_STRIPED_LAST >= PICO_SPINLOCK_ID_STRIPED_FIRST, "");
+static uint8_t striped_spin_lock_num = PICO_SPINLOCK_ID_STRIPED_FIRST;
+static uint32_t claimed;
+
+static void check_lock_num(uint __unused lock_num) {
+    invalid_params_if(SYNC, lock_num >= 32);
+}
+
+void spin_locks_reset(void) {
+    for (uint i = 0; i < NUM_SPIN_LOCKS; i++) {
+        spin_unlock_unsafe(spin_lock_instance(i));
+    }
+}
+
+spin_lock_t *spin_lock_init(uint lock_num) {
+    assert(lock_num < NUM_SPIN_LOCKS);
+    spin_lock_t *lock = spin_lock_instance(lock_num);
+    spin_unlock_unsafe(lock);
+    return lock;
+}
+
+uint next_striped_spin_lock_num() {
+    uint rc = striped_spin_lock_num++;
+    if (striped_spin_lock_num > PICO_SPINLOCK_ID_STRIPED_LAST) {
+        striped_spin_lock_num = PICO_SPINLOCK_ID_STRIPED_FIRST;
+    }
+    return rc;
+}
+
+void spin_lock_claim(uint lock_num) {
+    check_lock_num(lock_num);
+    hw_claim_or_assert((uint8_t *) &claimed, lock_num, "Spinlock %d is already claimed");
+}
+
+void spin_lock_claim_mask(uint32_t mask) {
+    for(uint i = 0; mask; i++, mask >>= 1u) {
+        if (mask & 1u) spin_lock_claim(i);
+    }
+}
+
+void spin_lock_unclaim(uint lock_num) {
+    check_lock_num(lock_num);
+    spin_unlock_unsafe(spin_lock_instance(lock_num));
+    hw_claim_clear((uint8_t *) &claimed, lock_num);
+}
+
+int spin_lock_claim_unused(bool required) {
+    return hw_claim_unused_from_range((uint8_t*)&claimed, required, PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, PICO_SPINLOCK_ID_CLAIM_FREE_LAST, "No spinlocks are available");
+}
+
+bool spin_lock_is_claimed(uint lock_num) {
+    check_lock_num(lock_num);
+    return hw_is_claimed((uint8_t *) &claimed, lock_num);
+}
+
diff --git a/src/rp2_common/hardware_timer/CMakeLists.txt b/src/rp2_common/hardware_timer/CMakeLists.txt
new file mode 100644
index 0000000..358f74c
--- /dev/null
+++ b/src/rp2_common/hardware_timer/CMakeLists.txt
@@ -0,0 +1,2 @@
+pico_simple_hardware_target(timer)
+target_link_libraries(hardware_timer INTERFACE hardware_claim)
diff --git a/src/rp2_common/hardware_timer/include/hardware/timer.h b/src/rp2_common/hardware_timer/include/hardware/timer.h
new file mode 100644
index 0000000..1799cd0
--- /dev/null
+++ b/src/rp2_common/hardware_timer/include/hardware/timer.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_TIMER_H
+#define _HARDWARE_TIMER_H
+
+#include "pico.h"
+#include "hardware/structs/timer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file hardware/timer.h
+ *  \defgroup hardware_timer hardware_timer
+ *
+ * Low-level hardware timer API
+ *
+ * This API provides medium level access to the timer HW.
+ * See also \ref pico_time which provides higher levels functionality using the hardware timer.
+ *
+ * The timer peripheral on RP2040 supports the following features:
+ *  - single 64-bit counter, incrementing once per microsecond
+ *  - Latching two-stage read of counter, for race-free read over 32 bit bus
+ *  - Four alarms: match on the lower 32 bits of counter, IRQ on match.
+ *
+ * By default the timer uses a one microsecond reference that is generated in the Watchdog (see Section 4.8.2) which is derived
+ * from the clk_ref.
+ *
+ * The timer has 4 alarms, and can output a separate interrupt for each alarm. The alarms match on the lower 32 bits of the 64
+ * bit counter which means they can be fired a maximum of 2^32 microseconds into the future. This is equivalent to:
+ *  - 2^32 ÷ 10^6: ~4295 seconds
+ *  - 4295 ÷ 60: ~72 minutes
+ *
+ * The timer is expected to be used for short sleeps, if you want a longer alarm see the \ref hardware_rtc functions.
+ *
+ * \subsection timer_example Example
+ * \addtogroup hardware_timer
+ *
+ * \include hello_timer.c
+ *
+ * \see pico_time
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_TIMER, Enable/disable assertions in the timer module, type=bool, default=0, group=hardware_timer
+#ifndef PARAM_ASSERTIONS_ENABLED_TIMER
+#define PARAM_ASSERTIONS_ENABLED_TIMER 0
+#endif
+
+static inline void check_hardware_alarm_num_param(__unused uint alarm_num) {
+    invalid_params_if(TIMER, alarm_num >= NUM_TIMERS);
+}
+
+/*! \brief Return a 32 bit timestamp value in microseconds
+*  \ingroup hardware_timer
+*
+* Returns the low 32 bits of the hardware timer.
+* \note This value wraps roughly every 1 hour 11 minutes and 35 seconds.
+*
+* \return the 32 bit timestamp
+*/
+static inline uint32_t time_us_32(void) {
+    return timer_hw->timerawl;
+}
+
+/*! \brief Return the current 64 bit timestamp value in microseconds
+*  \ingroup hardware_timer
+*
+* Returns the full 64 bits of the hardware timer. The \ref pico_time and other functions rely on the fact that this
+* value monotonically increases from power up. As such it is expected that this value counts upwards and never wraps
+* (we apologize for introducing a potential year 5851444 bug).
+*
+* \return the 64 bit timestamp
+*/
+uint64_t time_us_64(void);
+
+/*! \brief Busy wait wasting cycles for the given (32 bit) number of microseconds
+ *  \ingroup hardware_timer
+ *
+ * \param delay_us delay amount in microseconds
+ */
+void busy_wait_us_32(uint32_t delay_us);
+
+/*! \brief Busy wait wasting cycles for the given (64 bit) number of microseconds
+ *  \ingroup hardware_timer
+ *
+ * \param delay_us delay amount in microseconds
+ */
+void busy_wait_us(uint64_t delay_us);
+
+/*! \brief Busy wait wasting cycles for the given number of milliseconds
+ *  \ingroup hardware_timer
+ *
+ * \param delay_ms delay amount in milliseconds
+ */
+void busy_wait_ms(uint32_t delay_ms);
+
+/*! \brief Busy wait wasting cycles until after the specified timestamp
+ *  \ingroup hardware_timer
+ *
+ * \param t Absolute time to wait until
+ */
+void busy_wait_until(absolute_time_t t);
+
+/*! \brief Check if the specified timestamp has been reached
+ *  \ingroup hardware_timer
+ *
+ * \param t Absolute time to compare against current time
+ * \return true if it is now after the specified timestamp
+ */
+static inline bool time_reached(absolute_time_t t) {
+    uint64_t target = to_us_since_boot(t);
+    uint32_t hi_target = (uint32_t)(target >> 32u);
+    uint32_t hi = timer_hw->timerawh;
+    return (hi >= hi_target && (timer_hw->timerawl >= (uint32_t) target || hi != hi_target));
+}
+
+/*! Callback function type for hardware alarms
+ *  \ingroup hardware_timer
+ *
+ * \param alarm_num the hardware alarm number
+ * \sa hardware_alarm_set_callback()
+ */
+typedef void (*hardware_alarm_callback_t)(uint alarm_num);
+
+/*! \brief cooperatively claim the use of this hardware alarm_num
+ *  \ingroup hardware_timer
+ *
+ * This method hard asserts if the hardware alarm is currently claimed.
+ *
+ * \param alarm_num the hardware alarm to claim
+ * \sa hardware_claiming
+ */
+void hardware_alarm_claim(uint alarm_num);
+
+/*! \brief cooperatively release the claim on use of this hardware alarm_num
+ *  \ingroup hardware_timer
+ *
+ * \param alarm_num the hardware alarm to unclaim
+ * \sa hardware_claiming
+ */
+void hardware_alarm_unclaim(uint alarm_num);
+
+/*! \brief Determine if a hardware alarm has been claimed
+ *  \ingroup hardware_timer
+ *
+ * \param alarm_num the hardware alarm number
+ * \return true if claimed, false otherwise
+ * \see hardware_alarm_claim
+ */
+bool hardware_alarm_is_claimed(uint alarm_num);
+
+/*! \brief Enable/Disable a callback for a hardware timer on this core
+ *  \ingroup hardware_timer
+ *
+ * This method enables/disables the alarm IRQ for the specified hardware alarm on the
+ * calling core, and set the specified callback to be associated with that alarm.
+ *
+ * This callback will be used for the timeout set via hardware_alarm_set_target
+ *
+ * \note This will install the handler on the current core if the IRQ handler isn't already set.
+ * Therefore the user has the opportunity to call this up from the core of their choice
+ *
+ * \param alarm_num the hardware alarm number
+ * \param callback the callback to install, or NULL to unset
+ *
+ * \sa hardware_alarm_set_target()
+ */
+void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback);
+
+/**
+ * \brief Set the current target for the specified hardware alarm
+ * \ingroup hardware_timer
+ *
+ * This will replace any existing target
+ *
+ * @param alarm_num the hardware alarm number
+ * @param t the target timestamp
+ * @return true if the target was "missed"; i.e. it was in the past, or occurred before a future hardware timeout could be set
+ */
+bool hardware_alarm_set_target(uint alarm_num, absolute_time_t t);
+
+/**
+ * \brief Cancel an existing target (if any) for a given hardware_alarm
+ * \ingroup hardware_timer
+ *
+ * @param alarm_num
+ */
+
+void hardware_alarm_cancel(uint alarm_num);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/src/rp2_common/hardware_timer/timer.c b/src/rp2_common/hardware_timer/timer.c
new file mode 100644
index 0000000..f13d249
--- /dev/null
+++ b/src/rp2_common/hardware_timer/timer.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/timer.h"
+#include "hardware/irq.h"
+#include "hardware/sync.h"
+#include "hardware/claim.h"
+
+check_hw_layout(timer_hw_t, ints, TIMER_INTS_OFFSET);
+
+static hardware_alarm_callback_t alarm_callbacks[NUM_TIMERS];
+static uint32_t target_hi[NUM_TIMERS];
+static uint8_t timer_callbacks_pending;
+
+static_assert(NUM_TIMERS <= 4, "");
+static uint8_t claimed;
+
+void hardware_alarm_claim(uint alarm_num) {
+    check_hardware_alarm_num_param(alarm_num);
+    hw_claim_or_assert(&claimed, alarm_num, "Hardware alarm %d already claimed");
+}
+
+void hardware_alarm_unclaim(uint alarm_num) {
+    check_hardware_alarm_num_param(alarm_num);
+    hw_claim_clear(&claimed, alarm_num);
+}
+
+bool hardware_alarm_is_claimed(uint alarm_num) {
+    check_hardware_alarm_num_param(alarm_num);
+    return hw_is_claimed(&claimed, alarm_num);
+}
+
+/// tag::time_us_64[]
+uint64_t time_us_64() {
+    // Need to make sure that the upper 32 bits of the timer
+    // don't change, so read that first
+    uint32_t hi = timer_hw->timerawh;
+    uint32_t lo;
+    do {
+        // Read the lower 32 bits
+        lo = timer_hw->timerawl;
+        // Now read the upper 32 bits again and
+        // check that it hasn't incremented. If it has loop around
+        // and read the lower 32 bits again to get an accurate value
+        uint32_t next_hi = timer_hw->timerawh;
+        if (hi == next_hi) break;
+        hi = next_hi;
+    } while (true);
+    return ((uint64_t) hi << 32u) | lo;
+}
+/// end::time_us_64[]
+
+/// \tag::busy_wait[]
+void busy_wait_us_32(uint32_t delay_us) {
+    if (0 <= (int32_t)delay_us) {
+        // we only allow 31 bits, otherwise we could have a race in the loop below with
+        // values very close to 2^32
+        uint32_t start = timer_hw->timerawl;
+        while (timer_hw->timerawl - start < delay_us) {
+            tight_loop_contents();
+        }
+    } else {
+        busy_wait_us(delay_us);
+    }
+}
+
+void busy_wait_us(uint64_t delay_us) {
+    uint64_t base = time_us_64();
+    uint64_t target = base + delay_us;
+    if (target < base) {
+        target = (uint64_t)-1;
+    }
+    absolute_time_t t;
+    update_us_since_boot(&t, target);
+    busy_wait_until(t);
+}
+
+void busy_wait_ms(uint32_t delay_ms)
+{
+    if (delay_ms <= 0x7fffffffu / 1000) {
+        busy_wait_us_32(delay_ms * 1000);
+    } else {
+        busy_wait_us(delay_ms * 1000ull);
+    }
+}
+
+void busy_wait_until(absolute_time_t t) {
+    uint64_t target = to_us_since_boot(t);
+    uint32_t hi_target = (uint32_t)(target >> 32u);
+    uint32_t hi = timer_hw->timerawh;
+    while (hi < hi_target) {
+        hi = timer_hw->timerawh;
+        tight_loop_contents();
+    }
+    while (hi == hi_target && timer_hw->timerawl < (uint32_t) target) {
+        hi = timer_hw->timerawh;
+        tight_loop_contents();
+    }
+}
+/// \end::busy_wait[]
+
+static inline uint harware_alarm_irq_number(uint alarm_num) {
+    return TIMER_IRQ_0 + alarm_num;
+}
+
+static void hardware_alarm_irq_handler(void) {
+    // Determine which timer this IRQ is for
+    uint32_t ipsr;
+    __asm volatile ("mrs %0, ipsr" : "=r" (ipsr)::);
+    uint alarm_num = (ipsr & 0x3fu) - 16 - TIMER_IRQ_0;
+    check_hardware_alarm_num_param(alarm_num);
+
+    hardware_alarm_callback_t callback = NULL;
+
+    spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER);
+    uint32_t save = spin_lock_blocking(lock);
+    // Clear the timer IRQ (inside lock, because we check whether we have handled the IRQ yet in alarm_set by looking at the interrupt status
+    timer_hw->intr = 1u << alarm_num;
+
+    // make sure the IRQ is still valid
+    if (timer_callbacks_pending & (1u << alarm_num)) {
+        // Now check whether we have a timer event to handle that isn't already obsolete (this could happen if we
+        // were already in the IRQ handler before someone else changed the timer setup
+        if (timer_hw->timerawh >= target_hi[alarm_num]) {
+            // we have reached the right high word as well as low word value
+            callback = alarm_callbacks[alarm_num];
+            timer_callbacks_pending &= (uint8_t)~(1u << alarm_num);
+        } else {
+            // try again in 2^32 us
+            timer_hw->alarm[alarm_num] = timer_hw->alarm[alarm_num]; // re-arm the timer
+        }
+    }
+
+    spin_unlock(lock, save);
+
+    if (callback) {
+        callback(alarm_num);
+    }
+}
+
+void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback) {
+    // todo check current core owner
+    //  note this should probably be subsumed by irq_set_exclusive_handler anyway, since that
+    //  should disallow IRQ handlers on both cores
+    check_hardware_alarm_num_param(alarm_num);
+    uint irq_num = harware_alarm_irq_number(alarm_num);
+    spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER);
+    uint32_t save = spin_lock_blocking(lock);
+    if (callback) {
+        if (hardware_alarm_irq_handler != irq_get_vtable_handler(irq_num)) {
+            // note that set_exclusive will silently allow you to set the handler to the same thing
+            // since it is idempotent, which means we don't need to worry about locking ourselves
+            irq_set_exclusive_handler(irq_num, hardware_alarm_irq_handler);
+            irq_set_enabled(irq_num, true);
+            // Enable interrupt in block and at processor
+            hw_set_bits(&timer_hw->inte, 1u << alarm_num);
+        }
+        alarm_callbacks[alarm_num] = callback;
+    } else {
+        alarm_callbacks[alarm_num] = NULL;
+        timer_callbacks_pending &= (uint8_t)~(1u << alarm_num);
+        irq_remove_handler(irq_num, hardware_alarm_irq_handler);
+        irq_set_enabled(irq_num, false);
+    }
+    spin_unlock(lock, save);
+}
+
+bool hardware_alarm_set_target(uint alarm_num, absolute_time_t target) {
+    bool missed;
+    uint64_t now = time_us_64();
+    uint64_t t = to_us_since_boot(target);
+    if (now >= t) {
+        missed = true;
+    } else {
+        missed = false;
+
+        // 1) actually set the hardware timer
+        spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER);
+        uint32_t save = spin_lock_blocking(lock);
+        uint8_t old_timer_callbacks_pending = timer_callbacks_pending;
+        timer_callbacks_pending |= (uint8_t)(1u << alarm_num);
+        timer_hw->intr = 1u << alarm_num; // clear any IRQ
+        timer_hw->alarm[alarm_num] = (uint32_t) t;
+        // Set the alarm. Writing time should arm it
+        target_hi[alarm_num] = (uint32_t)(t >> 32u);
+
+        // 2) check for races
+        if (!(timer_hw->armed & 1u << alarm_num)) {
+            // not armed, so has already fired .. IRQ must be pending (we are still under lock)
+            assert(timer_hw->ints & 1u << alarm_num);
+        } else {
+            if (time_us_64() >= t) {
+                // we are already at or past the right time; there is no point in us racing against the IRQ
+                // we are about to generate. note however that, if there was already a timer pending before,
+                // then we still let the IRQ fire, as whatever it was, is not handled by our setting missed=true here
+                missed = true;
+                if (timer_callbacks_pending != old_timer_callbacks_pending) {
+                    // disarm the timer
+                    timer_hw->armed = 1u << alarm_num;
+                    // clear the IRQ...
+                    timer_hw->intr = 1u << alarm_num;
+                    // ... including anything pending on the processor - perhaps unnecessary, but
+                    // our timer flag says we aren't expecting anything.
+                    irq_clear(harware_alarm_irq_number(alarm_num));
+                    // and clear our flag so that if the IRQ handler is already active (because it is on
+                    // the other core) it will also skip doing anything
+                    timer_callbacks_pending = old_timer_callbacks_pending;
+                }
+            }
+        }
+        spin_unlock(lock, save);
+        // note at this point any pending timer IRQ can likely run
+    }
+    return missed;
+}
+
+void hardware_alarm_cancel(uint alarm_num) {
+    check_hardware_alarm_num_param(alarm_num);
+
+    spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER);
+    uint32_t save = spin_lock_blocking(lock);
+    timer_hw->armed = 1u << alarm_num;
+    timer_callbacks_pending &= (uint8_t)~(1u << alarm_num);
+    spin_unlock(lock, save);
+}
+
+
diff --git a/src/rp2_common/hardware_uart/CMakeLists.txt b/src/rp2_common/hardware_uart/CMakeLists.txt
new file mode 100644
index 0000000..9fe65d5
--- /dev/null
+++ b/src/rp2_common/hardware_uart/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(uart)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_uart/include/hardware/uart.h b/src/rp2_common/hardware_uart/include/hardware/uart.h
new file mode 100644
index 0000000..bce0d2f
--- /dev/null
+++ b/src/rp2_common/hardware_uart/include/hardware/uart.h
@@ -0,0 +1,453 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_UART_H
+#define _HARDWARE_UART_H
+
+#include "pico.h"
+#include "hardware/structs/uart.h"
+#include "hardware/regs/dreq.h"
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_UART, Enable/disable assertions in the UART module, type=bool, default=0, group=hardware_uart
+#ifndef PARAM_ASSERTIONS_ENABLED_UART
+#define PARAM_ASSERTIONS_ENABLED_UART 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// PICO_CONFIG: PICO_UART_ENABLE_CRLF_SUPPORT, Enable/disable CR/LF translation support, type=bool, default=1, group=hardware_uart
+#ifndef PICO_UART_ENABLE_CRLF_SUPPORT
+#define PICO_UART_ENABLE_CRLF_SUPPORT 1
+#endif
+
+// PICO_CONFIG: PICO_UART_DEFAULT_CRLF, Enable/disable CR/LF translation on UART, type=bool, default=0, depends=PICO_UART_ENABLE_CRLF_SUPPORT, group=hardware_uart
+#ifndef PICO_UART_DEFAULT_CRLF
+#define PICO_UART_DEFAULT_CRLF 0
+#endif
+
+// PICO_CONFIG: PICO_DEFAULT_UART, Define the default UART used for printf etc, min=0, max=1, group=hardware_uart
+// PICO_CONFIG: PICO_DEFAULT_UART_TX_PIN, Define the default UART TX pin, min=0, max=29, group=hardware_uart
+// PICO_CONFIG: PICO_DEFAULT_UART_RX_PIN, Define the default UART RX pin, min=0, max=29, group=hardware_uart
+
+// PICO_CONFIG: PICO_DEFAULT_UART_BAUD_RATE, Define the default UART baudrate, max=921600, default=115200, group=hardware_uart
+#ifndef PICO_DEFAULT_UART_BAUD_RATE
+#define PICO_DEFAULT_UART_BAUD_RATE 115200   ///< Default baud rate
+#endif
+
+/** \file hardware/uart.h
+ *  \defgroup hardware_uart hardware_uart
+ *
+ * Hardware UART API
+ *
+ * RP2040 has 2 identical instances of a UART peripheral, based on the ARM PL011. Each UART can be connected to a number
+ * of GPIO pins as defined in the GPIO muxing.
+ *
+ * Only the TX, RX, RTS, and CTS signals are
+ * connected, meaning that the modem mode and IrDA mode of the PL011 are not supported.
+ *
+ * \subsection uart_example Example
+ * \addtogroup hardware_uart
+ *
+ *  \code
+ *  int main() {
+ *
+ *     // Initialise UART 0
+ *     uart_init(uart0, 115200);
+ *
+ *     // Set the GPIO pin mux to the UART - 0 is TX, 1 is RX
+ *     gpio_set_function(0, GPIO_FUNC_UART);
+ *     gpio_set_function(1, GPIO_FUNC_UART);
+ *
+ *     uart_puts(uart0, "Hello world!");
+ * }
+ * \endcode
+ */
+
+// Currently always a pointer to hw but it might not be in the future
+typedef struct uart_inst uart_inst_t;
+
+/** The UART identifiers for use in UART functions.
+ *
+ * e.g. uart_init(uart1, 48000)
+ *
+ *  \ingroup hardware_uart
+ * @{
+ */
+#define uart0 ((uart_inst_t * const)uart0_hw) ///< Identifier for UART instance 0
+#define uart1 ((uart_inst_t * const)uart1_hw) ///< Identifier for UART instance 1
+
+/** @} */
+
+#if !defined(PICO_DEFAULT_UART_INSTANCE) && defined(PICO_DEFAULT_UART)
+#define PICO_DEFAULT_UART_INSTANCE (__CONCAT(uart,PICO_DEFAULT_UART))
+#endif
+
+#ifdef PICO_DEFAULT_UART_INSTANCE
+#define uart_default PICO_DEFAULT_UART_INSTANCE
+#endif
+
+/*! \brief Convert UART instance to hardware instance number
+ *  \ingroup hardware_uart
+ *
+ * \param uart UART instance
+ * \return Number of UART, 0 or 1.
+ */
+static inline uint uart_get_index(uart_inst_t *uart) {
+    invalid_params_if(UART, uart != uart0 && uart != uart1);
+    return uart == uart1 ? 1 : 0;
+}
+
+static inline uart_inst_t *uart_get_instance(uint instance) {
+    static_assert(NUM_UARTS == 2, "");
+    invalid_params_if(UART, instance >= NUM_UARTS);
+    return instance ? uart1 : uart0;
+}
+
+static inline uart_hw_t *uart_get_hw(uart_inst_t *uart) {
+    uart_get_index(uart); // check it is a hw uart
+    return (uart_hw_t *)uart;
+}
+
+/** \brief UART Parity enumeration
+ *  \ingroup hardware_uart
+ */
+typedef enum {
+    UART_PARITY_NONE,
+    UART_PARITY_EVEN,
+    UART_PARITY_ODD
+} uart_parity_t;
+
+// ----------------------------------------------------------------------------
+// Setup
+
+/*! \brief Initialise a UART
+ *  \ingroup hardware_uart
+ *
+ * Put the UART into a known state, and enable it. Must be called before other
+ * functions.
+ *
+ * \note There is no guarantee that the baudrate requested will be possible, the nearest will be chosen,
+ * and this function will return the configured baud rate.
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param baudrate Baudrate of UART in Hz
+ * \return Actual set baudrate
+ */
+uint uart_init(uart_inst_t *uart, uint baudrate);
+
+/*! \brief DeInitialise a UART
+ *  \ingroup hardware_uart
+ *
+ * Disable the UART if it is no longer used. Must be reinitialised before
+ * being used again.
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ */
+void uart_deinit(uart_inst_t *uart);
+
+/*! \brief Set UART baud rate
+ *  \ingroup hardware_uart
+ *
+ * Set baud rate as close as possible to requested, and return actual rate selected.
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param baudrate Baudrate in Hz
+ * \return Actual set baudrate
+ */
+uint uart_set_baudrate(uart_inst_t *uart, uint baudrate);
+
+/*! \brief Set UART flow control CTS/RTS
+ *  \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param cts If true enable flow control of TX  by clear-to-send input
+ * \param rts If true enable assertion of request-to-send output by RX flow control
+ */
+static inline void uart_set_hw_flow(uart_inst_t *uart, bool cts, bool rts) {
+    hw_write_masked(&uart_get_hw(uart)->cr,
+                   (bool_to_bit(cts) << UART_UARTCR_CTSEN_LSB) | (bool_to_bit(rts) << UART_UARTCR_RTSEN_LSB),
+                   UART_UARTCR_RTSEN_BITS | UART_UARTCR_CTSEN_BITS);
+}
+
+/*! \brief Set UART data format
+ *  \ingroup hardware_uart
+ *
+ * Configure the data format (bits etc() for the UART
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param data_bits Number of bits of data. 5..8
+ * \param stop_bits Number of stop bits 1..2
+ * \param parity Parity option.
+ */
+static inline void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_bits, uart_parity_t parity) {
+    invalid_params_if(UART, data_bits < 5 || data_bits > 8);
+    invalid_params_if(UART, stop_bits != 1 && stop_bits != 2);
+    invalid_params_if(UART, parity != UART_PARITY_NONE && parity != UART_PARITY_EVEN && parity != UART_PARITY_ODD);
+    hw_write_masked(&uart_get_hw(uart)->lcr_h,
+                   ((data_bits - 5u) << UART_UARTLCR_H_WLEN_LSB) |
+                   ((stop_bits - 1u) << UART_UARTLCR_H_STP2_LSB) |
+                   (bool_to_bit(parity != UART_PARITY_NONE) << UART_UARTLCR_H_PEN_LSB) |
+                   (bool_to_bit(parity == UART_PARITY_EVEN) << UART_UARTLCR_H_EPS_LSB),
+                   UART_UARTLCR_H_WLEN_BITS |
+                   UART_UARTLCR_H_STP2_BITS |
+                   UART_UARTLCR_H_PEN_BITS |
+                   UART_UARTLCR_H_EPS_BITS);
+}
+
+/*! \brief Setup UART interrupts
+ *  \ingroup hardware_uart
+ *
+ * Enable the UART's interrupt output. An interrupt handler will need to be installed prior to calling
+ * this function.
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param rx_has_data If true an interrupt will be fired when the RX FIFO contains data.
+ * \param tx_needs_data If true an interrupt will be fired when the TX FIFO needs data.
+ */
+static inline void uart_set_irq_enables(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data) {
+    // Both UARTRXINTR (RX) and UARTRTINTR (RX timeout) interrupts are
+    // required for rx_has_data. RX asserts when >=4 characters are in the RX
+    // FIFO (for RXIFLSEL=0). RT asserts when there are >=1 characters and no
+    // more have been received for 32 bit periods.
+    uart_get_hw(uart)->imsc = (bool_to_bit(tx_needs_data) << UART_UARTIMSC_TXIM_LSB) |
+                              (bool_to_bit(rx_has_data) << UART_UARTIMSC_RXIM_LSB) |
+                              (bool_to_bit(rx_has_data) << UART_UARTIMSC_RTIM_LSB);
+    if (rx_has_data) {
+        // Set minimum threshold
+        hw_write_masked(&uart_get_hw(uart)->ifls, 0 << UART_UARTIFLS_RXIFLSEL_LSB,
+                        UART_UARTIFLS_RXIFLSEL_BITS);
+    }
+    if (tx_needs_data) {
+        // Set maximum threshold
+        hw_write_masked(&uart_get_hw(uart)->ifls, 0 << UART_UARTIFLS_TXIFLSEL_LSB,
+                        UART_UARTIFLS_TXIFLSEL_BITS);
+    }
+}
+
+/*! \brief Test if specific UART is enabled
+ *  \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \return true if the UART is enabled
+ */
+static inline bool uart_is_enabled(uart_inst_t *uart) {
+    return !!(uart_get_hw(uart)->cr & UART_UARTCR_UARTEN_BITS);
+}
+
+/*! \brief Enable/Disable the FIFOs on specified UART
+ *  \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param enabled true to enable FIFO (default), false to disable
+ */
+static inline void uart_set_fifo_enabled(uart_inst_t *uart, bool enabled) {
+    hw_write_masked(&uart_get_hw(uart)->lcr_h,
+                   (bool_to_bit(enabled) << UART_UARTLCR_H_FEN_LSB),
+                   UART_UARTLCR_H_FEN_BITS);
+}
+
+
+// ----------------------------------------------------------------------------
+// Generic input/output
+
+/*! \brief Determine if space is available in the TX FIFO
+ *  \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \return false if no space available, true otherwise
+ */
+static inline bool uart_is_writable(uart_inst_t *uart) {
+    return !(uart_get_hw(uart)->fr & UART_UARTFR_TXFF_BITS);
+}
+
+/*! \brief Wait for the UART TX fifo to be drained
+ *  \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ */
+static inline void uart_tx_wait_blocking(uart_inst_t *uart) {
+    while (uart_get_hw(uart)->fr & UART_UARTFR_BUSY_BITS) tight_loop_contents();
+}
+
+/*! \brief Determine whether data is waiting in the RX FIFO
+ *  \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \return 0 if no data available, otherwise the number of bytes, at least, that can be read
+ *
+ * \note HW limitations mean this function will return either 0 or 1.
+ */
+static inline bool uart_is_readable(uart_inst_t *uart) {
+    // PL011 doesn't expose levels directly, so return values are only 0 or 1
+    return !(uart_get_hw(uart)->fr & UART_UARTFR_RXFE_BITS);
+}
+
+/*! \brief  Write to the UART for transmission.
+ *  \ingroup hardware_uart
+ *
+ * This function will block until all the data has been sent to the UART
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param src The bytes to send
+ * \param len The number of bytes to send
+ */
+static inline void uart_write_blocking(uart_inst_t *uart, const uint8_t *src, size_t len) {
+    for (size_t i = 0; i < len; ++i) {
+        while (!uart_is_writable(uart))
+            tight_loop_contents();
+        uart_get_hw(uart)->dr = *src++;
+    }
+}
+
+/*! \brief  Read from the UART
+ *  \ingroup hardware_uart
+ *
+ * This function will block until all the data has been received from the UART
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param dst Buffer to accept received bytes
+ * \param len The number of bytes to receive.
+ */
+static inline void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t len) {
+    for (size_t i = 0; i < len; ++i) {
+        while (!uart_is_readable(uart))
+            tight_loop_contents();
+        *dst++ = (uint8_t) uart_get_hw(uart)->dr;
+    }
+}
+
+// ----------------------------------------------------------------------------
+// UART-specific operations and aliases
+
+/*! \brief  Write single character to UART for transmission.
+ *  \ingroup hardware_uart
+ *
+ * This function will block until the entire character has been sent
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param c The character  to send
+ */
+static inline void uart_putc_raw(uart_inst_t *uart, char c) {
+    uart_write_blocking(uart, (const uint8_t *) &c, 1);
+}
+
+/*! \brief  Write single character to UART for transmission, with optional CR/LF conversions
+ *  \ingroup hardware_uart
+ *
+ * This function will block until the character has been sent
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param c The character  to send
+ */
+static inline void uart_putc(uart_inst_t *uart, char c) {
+#if PICO_UART_ENABLE_CRLF_SUPPORT
+    extern short uart_char_to_line_feed[NUM_UARTS];
+    if (uart_char_to_line_feed[uart_get_index(uart)] == c)
+        uart_putc_raw(uart, '\r');
+#endif
+    uart_putc_raw(uart, c);
+}
+
+/*! \brief  Write string to UART for transmission, doing any CR/LF conversions
+ *  \ingroup hardware_uart
+ *
+ * This function will block until the entire string has been sent
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param s The null terminated string to send
+ */
+static inline void uart_puts(uart_inst_t *uart, const char *s) {
+#if PICO_UART_ENABLE_CRLF_SUPPORT
+    bool last_was_cr = false;
+    while (*s) {
+        // Don't add extra carriage returns if one is present
+        if (last_was_cr)
+            uart_putc_raw(uart, *s);
+        else
+            uart_putc(uart, *s);
+        last_was_cr = *s++ == '\r';
+    }
+#else
+    while (*s)
+        uart_putc(uart, *s++);
+#endif
+}
+
+/*! \brief  Read a single character to UART
+ *  \ingroup hardware_uart
+ *
+ * This function will block until the character has been read
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \return The character read.
+ */
+static inline char uart_getc(uart_inst_t *uart) {
+    char c;
+    uart_read_blocking(uart, (uint8_t *) &c, 1);
+    return c;
+}
+
+/*! \brief Assert a break condition on the UART transmission.
+ *  \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param en Assert break condition (TX held low) if true. Clear break condition if false.
+ */
+static inline void uart_set_break(uart_inst_t *uart, bool en) {
+    if (en)
+        hw_set_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_BRK_BITS);
+    else
+        hw_clear_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_BRK_BITS);
+}
+
+/*! \brief Set CR/LF conversion on UART
+ *  \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param translate If true, convert line feeds to carriage return on transmissions
+ */
+void uart_set_translate_crlf(uart_inst_t *uart, bool translate);
+
+/*! \brief Wait for the default UART's TX FIFO to be drained
+ *  \ingroup hardware_uart
+ */
+static inline void uart_default_tx_wait_blocking(void) {
+#ifdef uart_default
+    uart_tx_wait_blocking(uart_default);
+#else
+    assert(false);
+#endif
+}
+
+/*! \brief Wait for up to a certain number of microseconds for the RX FIFO to be non empty
+ *  \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param us the number of microseconds to wait at most (may be 0 for an instantaneous check)
+ * \return true if the RX FIFO became non empty before the timeout, false otherwise
+ */
+bool uart_is_readable_within_us(uart_inst_t *uart, uint32_t us);
+
+/*! \brief Return the DREQ to use for pacing transfers to/from a particular UART instance
+ *  \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param is_tx true for sending data to the UART instance, false for receiving data from the UART instance
+ */
+static inline uint uart_get_dreq(uart_inst_t *uart, bool is_tx) {
+    static_assert(DREQ_UART0_RX == DREQ_UART0_TX + 1, "");
+    static_assert(DREQ_UART1_RX == DREQ_UART1_TX + 1, "");
+    static_assert(DREQ_UART1_TX == DREQ_UART0_TX + 2, "");
+    return DREQ_UART0_TX + uart_get_index(uart) * 2 + !is_tx;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_uart/uart.c b/src/rp2_common/hardware_uart/uart.c
new file mode 100644
index 0000000..ba48e87
--- /dev/null
+++ b/src/rp2_common/hardware_uart/uart.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/address_mapped.h"
+#include "hardware/platform_defs.h"
+#include "hardware/uart.h"
+
+#include "hardware/structs/uart.h"
+#include "hardware/resets.h"
+#include "hardware/clocks.h"
+#include "hardware/timer.h"
+
+#include "pico/assert.h"
+#include "pico.h"
+
+check_hw_layout(uart_hw_t, fr, UART_UARTFR_OFFSET);
+check_hw_layout(uart_hw_t, dmacr, UART_UARTDMACR_OFFSET);
+
+#if PICO_UART_ENABLE_CRLF_SUPPORT
+short uart_char_to_line_feed[NUM_UARTS];
+#endif
+
+/// \tag::uart_reset[]
+static inline void uart_reset(uart_inst_t *uart) {
+    invalid_params_if(UART, uart != uart0 && uart != uart1);
+    reset_block(uart_get_index(uart) ? RESETS_RESET_UART1_BITS : RESETS_RESET_UART0_BITS);
+}
+
+static inline void uart_unreset(uart_inst_t *uart) {
+    invalid_params_if(UART, uart != uart0 && uart != uart1);
+    unreset_block_wait(uart_get_index(uart) ? RESETS_RESET_UART1_BITS : RESETS_RESET_UART0_BITS);
+}
+/// \end::uart_reset[]
+
+/// \tag::uart_init[]
+uint uart_init(uart_inst_t *uart, uint baudrate) {
+    invalid_params_if(UART, uart != uart0 && uart != uart1);
+
+    if (clock_get_hz(clk_peri) == 0)
+        return 0;
+
+    uart_reset(uart);
+    uart_unreset(uart);
+
+#if PICO_UART_ENABLE_CRLF_SUPPORT
+    uart_set_translate_crlf(uart, PICO_UART_DEFAULT_CRLF);
+#endif
+
+    // Any LCR writes need to take place before enabling the UART
+    uint baud = uart_set_baudrate(uart, baudrate);
+    uart_set_format(uart, 8, 1, UART_PARITY_NONE);
+
+    // Enable the UART, both TX and RX
+    uart_get_hw(uart)->cr = UART_UARTCR_UARTEN_BITS | UART_UARTCR_TXE_BITS | UART_UARTCR_RXE_BITS;
+    // Enable FIFOs
+    hw_set_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_FEN_BITS);
+    // Always enable DREQ signals -- no harm in this if DMA is not listening
+    uart_get_hw(uart)->dmacr = UART_UARTDMACR_TXDMAE_BITS | UART_UARTDMACR_RXDMAE_BITS;
+
+    return baud;
+}
+/// \end::uart_init[]
+
+void uart_deinit(uart_inst_t *uart) {
+    invalid_params_if(UART, uart != uart0 && uart != uart1);
+    uart_reset(uart);
+}
+
+/// \tag::uart_set_baudrate[]
+uint uart_set_baudrate(uart_inst_t *uart, uint baudrate) {
+    invalid_params_if(UART, baudrate == 0);
+    uint32_t baud_rate_div = (8 * clock_get_hz(clk_peri) / baudrate);
+    uint32_t baud_ibrd = baud_rate_div >> 7;
+    uint32_t baud_fbrd;
+
+    if (baud_ibrd == 0) {
+        baud_ibrd = 1;
+        baud_fbrd = 0;
+    } else if (baud_ibrd >= 65535) {
+        baud_ibrd = 65535;
+        baud_fbrd = 0;
+    }  else {
+        baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2;
+    }
+
+    // Load PL011's baud divisor registers
+    uart_get_hw(uart)->ibrd = baud_ibrd;
+    uart_get_hw(uart)->fbrd = baud_fbrd;
+
+    // PL011 needs a (dummy) line control register write to latch in the
+    // divisors. We don't want to actually change LCR contents here.
+    hw_set_bits(&uart_get_hw(uart)->lcr_h, 0);
+
+    // See datasheet
+    return (4 * clock_get_hz(clk_peri)) / (64 * baud_ibrd + baud_fbrd);
+}
+/// \end::uart_set_baudrate[]
+
+void uart_set_translate_crlf(uart_inst_t *uart, bool crlf) {
+#if PICO_UART_ENABLE_CRLF_SUPPORT
+    uart_char_to_line_feed[uart_get_index(uart)] = crlf ? '\n' : 0x100;
+#else
+    panic_unsupported();
+#endif
+}
+
+bool uart_is_readable_within_us(uart_inst_t *uart, uint32_t us) {
+    uint32_t t = time_us_32();
+    do {
+        if (uart_is_readable(uart)) return true;
+    } while ((time_us_32() - t) <= us);
+    return false;
+}
diff --git a/src/rp2_common/hardware_vreg/CMakeLists.txt b/src/rp2_common/hardware_vreg/CMakeLists.txt
new file mode 100644
index 0000000..9a5b150
--- /dev/null
+++ b/src/rp2_common/hardware_vreg/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(vreg)
diff --git a/src/rp2_common/hardware_vreg/include/hardware/vreg.h b/src/rp2_common/hardware_vreg/include/hardware/vreg.h
new file mode 100644
index 0000000..7b4e259
--- /dev/null
+++ b/src/rp2_common/hardware_vreg/include/hardware/vreg.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_VREG_H_
+#define _HARDWARE_VREG_H_
+
+#include "pico.h"
+#include "hardware/structs/vreg_and_chip_reset.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file vreg.h
+ *  \defgroup hardware_vreg hardware_vreg
+ *
+ * Voltage Regulation API
+ *
+ */
+
+/** Possible voltage values that can be applied to the regulator
+ */
+enum vreg_voltage {
+    VREG_VOLTAGE_0_85 = 0b0110,    ///< 0.85v
+    VREG_VOLTAGE_0_90 = 0b0111,    ///< 0.90v
+    VREG_VOLTAGE_0_95 = 0b1000,    ///< 0.95v
+    VREG_VOLTAGE_1_00 = 0b1001,    ///< 1.00v
+    VREG_VOLTAGE_1_05 = 0b1010,    ///< 1.05v
+    VREG_VOLTAGE_1_10 = 0b1011,    ///< 1.10v
+    VREG_VOLTAGE_1_15 = 0b1100,    ///< 1.15v
+    VREG_VOLTAGE_1_20 = 0b1101,    ///< 1.20v
+    VREG_VOLTAGE_1_25 = 0b1110,    ///< 1.25v
+    VREG_VOLTAGE_1_30 = 0b1111,    ///< 1.30v
+
+    VREG_VOLTAGE_MIN = VREG_VOLTAGE_0_85,      ///< Always the minimum possible voltage
+    VREG_VOLTAGE_DEFAULT = VREG_VOLTAGE_1_10,  ///< Default voltage on power up.
+    VREG_VOLTAGE_MAX = VREG_VOLTAGE_1_30,      ///< Always the maximum possible voltage
+};
+
+
+/*! \brief  Set voltage
+ *  \ingroup hardware_vreg
+ *
+ * \param voltage  The voltage (from enumeration \ref vreg_voltage) to apply to the voltage regulator
+ **/
+void vreg_set_voltage(enum vreg_voltage voltage);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/hardware_vreg/vreg.c b/src/rp2_common/hardware_vreg/vreg.c
new file mode 100644
index 0000000..501b0d4
--- /dev/null
+++ b/src/rp2_common/hardware_vreg/vreg.c
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+#include "hardware/vreg.h"
+
+void vreg_set_voltage(enum vreg_voltage voltage) {
+    hw_write_masked(&vreg_and_chip_reset_hw->vreg, ((uint)voltage) << VREG_AND_CHIP_RESET_VREG_VSEL_LSB, VREG_AND_CHIP_RESET_VREG_VSEL_BITS);
+}
diff --git a/src/rp2_common/hardware_watchdog/CMakeLists.txt b/src/rp2_common/hardware_watchdog/CMakeLists.txt
new file mode 100644
index 0000000..43a401b
--- /dev/null
+++ b/src/rp2_common/hardware_watchdog/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(watchdog)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h b/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h
new file mode 100644
index 0000000..747838b
--- /dev/null
+++ b/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_WATCHDOG_H
+#define _HARDWARE_WATCHDOG_H
+
+#include "pico.h"
+#include "hardware/structs/watchdog.h"
+
+/** \file hardware/watchdog.h
+ *  \defgroup hardware_watchdog hardware_watchdog
+ *
+ * Hardware Watchdog Timer API
+ *
+ * Supporting functions for the Pico hardware watchdog timer.
+ *
+ * The RP2040 has a built in HW watchdog Timer. This is a countdown timer that can restart parts of the chip if it reaches zero.
+ * For example, this can be used to restart the processor if the software running on it gets stuck in an infinite loop
+ * or similar. The programmer has to periodically write a value to the watchdog to stop it reaching zero.
+ *
+ * \subsection watchdog_example Example
+ * \addtogroup hardware_watchdog
+ * \include hello_watchdog.c
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Define actions to perform at watchdog timeout
+ *  \ingroup hardware_watchdog
+ *
+ * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \p delay_ms
+ * parameter will not be in microseconds. See the datasheet for more details.
+ *
+ * By default the SDK assumes a 12MHz XOSC and sets the \ref watchdog_start_tick appropriately.
+ *
+ * \param pc If Zero, a standard boot will be performed, if non-zero this is the program counter to jump to on reset.
+ * \param sp If \p pc is non-zero, this will be the stack pointer used.
+ * \param delay_ms Initial load value. Maximum value 0x7fffff, approximately 8.3s.
+ */
+void watchdog_reboot(uint32_t pc, uint32_t sp, uint32_t delay_ms);
+
+/*! \brief Start the watchdog tick
+ *  \ingroup hardware_watchdog
+ *
+ * \param cycles This needs to be a divider that when applied to the XOSC input, produces a 1MHz clock. So if the XOSC is
+ * 12MHz, this will need to be 12.
+ */
+void watchdog_start_tick(uint cycles);
+
+/*! \brief Reload the watchdog counter with the amount of time set in watchdog_enable
+ *  \ingroup hardware_watchdog
+ *
+ */
+void watchdog_update(void);
+
+/**
+ * \brief Enable the watchdog
+ * \ingroup hardware_watchdog
+ *
+ * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \p delay_ms
+ * parameter will not be in microseconds. See the datasheet for more details.
+ *
+ * By default the SDK assumes a 12MHz XOSC and sets the \ref watchdog_start_tick appropriately.
+ *
+ * This method sets a marker in the watchdog scratch register 4 that is checked by \ref watchdog_enable_caused_reboot.
+ * If the device is subsequently reset via a call to watchdog_reboot (including for example by dragging a UF2
+ * onto the RPI-RP2), then this value will be cleared, and so \ref watchdog_enable_caused_reboot will
+ * return false.
+ *
+ * \param delay_ms Number of milliseconds before watchdog will reboot without watchdog_update being called. Maximum of 0x7fffff, which is approximately 8.3 seconds
+ * \param pause_on_debug If the watchdog should be paused when the debugger is stepping through code
+ */
+void watchdog_enable(uint32_t delay_ms, bool pause_on_debug);
+
+/**
+ * \brief Did the watchdog cause the last reboot?
+ * \ingroup hardware_watchdog
+ *
+ * @return true If the watchdog timer or a watchdog force caused the last reboot
+ * @return false If there has been no watchdog reboot since the last power on reset. A power on reset is typically caused by a power cycle or the run pin (reset button) being toggled.
+ */
+bool watchdog_caused_reboot(void);
+
+/**
+ * \brief Did watchdog_enable cause the last reboot?
+ * \ingroup hardware_watchdog
+ *
+ * Perform additional checking along with \ref watchdog_caused_reboot to determine if a watchdog timeout initiated by
+ * \ref watchdog_enable caused the last reboot.
+ *
+ * This method checks for a special value in watchdog scratch register 4 placed there by \ref watchdog_enable.
+ * This would not be present if a watchdog reset is initiated by \ref watchdog_reboot or by the RP2040 bootrom
+ * (e.g. dragging a UF2 onto the RPI-RP2 drive).
+ *
+ * @return true If the watchdog timer or a watchdog force caused (see \reg watchdog_caused_reboot) the last reboot
+ *              and the watchdog reboot happened after \ref watchdog_enable was called
+ * @return false If there has been no watchdog reboot since the last power on reset, or the watchdog reboot was not caused
+ *               by a watchdog timeout after \ref watchdog_enable was called.
+ *               A power on reset is typically caused by a power cycle or the run pin (reset button) being toggled.
+ */
+bool watchdog_enable_caused_reboot(void);
+
+/**
+ * @brief Returns the number of microseconds before the watchdog will reboot the chip.
+ * \ingroup hardware_watchdog
+ *
+ * @return The number of microseconds before the watchdog will reboot the chip.
+ */
+uint32_t watchdog_get_count(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_watchdog/watchdog.c b/src/rp2_common/hardware_watchdog/watchdog.c
new file mode 100644
index 0000000..9545205
--- /dev/null
+++ b/src/rp2_common/hardware_watchdog/watchdog.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+
+#include "hardware/watchdog.h"
+#include "hardware/structs/watchdog.h"
+#include "hardware/structs/psm.h"
+
+/// \tag::watchdog_start_tick[]
+void watchdog_start_tick(uint cycles) {
+    // Important: This function also provides a tick reference to the timer
+    watchdog_hw->tick = cycles | WATCHDOG_TICK_ENABLE_BITS;
+}
+/// \end::watchdog_start_tick[]
+
+// Value to load when updating the watchdog
+
+// tag::watchdog_update[]
+static uint32_t load_value;
+
+void watchdog_update(void) {
+    watchdog_hw->load = load_value;
+}
+// end::watchdog_update[]
+
+uint32_t watchdog_get_count(void) {
+    return (watchdog_hw->ctrl & WATCHDOG_CTRL_TIME_BITS) / 2 ;
+}
+
+// tag::watchdog_enable[]
+// Helper function used by both watchdog_enable and watchdog_reboot
+void _watchdog_enable(uint32_t delay_ms, bool pause_on_debug) {
+    hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS);
+
+    // Reset everything apart from ROSC and XOSC
+    hw_set_bits(&psm_hw->wdsel, PSM_WDSEL_BITS & ~(PSM_WDSEL_ROSC_BITS | PSM_WDSEL_XOSC_BITS));
+
+    uint32_t dbg_bits = WATCHDOG_CTRL_PAUSE_DBG0_BITS |
+                        WATCHDOG_CTRL_PAUSE_DBG1_BITS |
+                        WATCHDOG_CTRL_PAUSE_JTAG_BITS;
+
+    if (pause_on_debug) {
+        hw_set_bits(&watchdog_hw->ctrl, dbg_bits);
+    } else {
+        hw_clear_bits(&watchdog_hw->ctrl, dbg_bits);
+    }
+
+    if (!delay_ms) {
+        hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_TRIGGER_BITS);
+    } else {
+        // Note, we have x2 here as the watchdog HW currently decrements twice per tick
+        load_value = delay_ms * 1000 * 2;
+
+        if (load_value > 0xffffffu)
+            load_value = 0xffffffu;
+
+        watchdog_update();
+
+        hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS);
+    }
+}
+// end::watchdog_enable[]
+
+#define WATCHDOG_NON_REBOOT_MAGIC 0x6ab73121
+
+void watchdog_enable(uint32_t delay_ms, bool pause_on_debug) {
+    // update scratch[4] to distinguish from magic used for reboot to specific address, or 0 used to reboot
+    // into regular flash path
+    watchdog_hw->scratch[4] = WATCHDOG_NON_REBOOT_MAGIC;
+    _watchdog_enable(delay_ms, pause_on_debug);
+}
+
+void watchdog_reboot(uint32_t pc, uint32_t sp, uint32_t delay_ms) {
+    check_hw_layout(watchdog_hw_t, scratch[7], WATCHDOG_SCRATCH7_OFFSET);
+
+    // Clear enable before setting up scratch registers
+    hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS);
+
+    if (pc) {
+        pc |= 1u; // thumb mode
+        watchdog_hw->scratch[4] = 0xb007c0d3;
+        watchdog_hw->scratch[5] = pc ^ -0xb007c0d3;
+        watchdog_hw->scratch[6] = sp;
+        watchdog_hw->scratch[7] = pc;
+//        printf("rebooting %08x/%08x in %dms...\n", (uint) pc, (uint) sp, (uint) delay_ms);
+    } else {
+        watchdog_hw->scratch[4] = 0;
+//        printf("rebooting (regular)) in %dms...\n", (uint) delay_ms);
+    }
+
+    // Don't pause watchdog for debug
+    _watchdog_enable(delay_ms, 0);
+}
+
+bool watchdog_caused_reboot(void) {
+    // If any reason bits are set this is true
+    return watchdog_hw->reason;
+}
+
+bool watchdog_enable_caused_reboot(void) {
+    return watchdog_hw->reason && watchdog_hw->scratch[4] == WATCHDOG_NON_REBOOT_MAGIC;
+}
\ No newline at end of file
diff --git a/src/rp2_common/hardware_xosc/CMakeLists.txt b/src/rp2_common/hardware_xosc/CMakeLists.txt
new file mode 100644
index 0000000..50e86c2
--- /dev/null
+++ b/src/rp2_common/hardware_xosc/CMakeLists.txt
@@ -0,0 +1 @@
+pico_simple_hardware_target(xosc)
\ No newline at end of file
diff --git a/src/rp2_common/hardware_xosc/include/hardware/xosc.h b/src/rp2_common/hardware_xosc/include/hardware/xosc.h
new file mode 100644
index 0000000..a5e33b0
--- /dev/null
+++ b/src/rp2_common/hardware_xosc/include/hardware/xosc.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_XOSC_H_
+#define _HARDWARE_XOSC_H_
+
+#include "pico.h"
+#include "hardware/structs/xosc.h"
+
+
+// Allow lengthening startup delay to accommodate slow-starting oscillators
+
+// PICO_CONFIG: PICO_XOSC_STARTUP_DELAY_MULTIPLIER, Multiplier to lengthen xosc startup delay to accommodate slow-starting oscillators, type=int, min=1, default=1, group=hardware_xosc
+#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER
+#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 1
+#endif
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file hardware/xosc.h
+ *  \defgroup hardware_xosc hardware_xosc
+ *
+ * Crystal Oscillator (XOSC) API
+ */
+
+/*! \brief  Initialise the crystal oscillator system
+ *  \ingroup hardware_xosc
+ *
+ * This function will block until the crystal oscillator has stabilised.
+ **/
+void xosc_init(void);
+
+/*! \brief  Disable the Crystal oscillator
+ *  \ingroup hardware_xosc
+ *
+ * Turns off the crystal oscillator source, and waits for it to become unstable
+ **/
+void xosc_disable(void);
+
+/*! \brief Set the crystal oscillator system to dormant
+ *  \ingroup hardware_xosc
+ *
+ * Turns off the crystal oscillator until it is woken by an interrupt. This will block and hence
+ * the entire system will stop, until an interrupt wakes it up. This function will
+ * continue to block until the oscillator becomes stable after its wakeup.
+ **/
+void xosc_dormant(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/hardware_xosc/xosc.c b/src/rp2_common/hardware_xosc/xosc.c
new file mode 100644
index 0000000..7a7055c
--- /dev/null
+++ b/src/rp2_common/hardware_xosc/xosc.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+
+// For MHZ definitions etc
+#include "hardware/clocks.h"
+
+#include "hardware/platform_defs.h"
+#include "hardware/regs/xosc.h"
+#include "hardware/xosc.h"
+
+#if XOSC_MHZ < 1 || XOSC_MHZ > 50
+#error XOSC_MHZ must be in the range 1-50
+#endif
+
+#define STARTUP_DELAY (((((XOSC_MHZ * MHZ) / 1000) + 128) / 256) * PICO_XOSC_STARTUP_DELAY_MULTIPLIER)
+
+// The DELAY field in xosc_hw->startup is 14 bits wide.
+#if STARTUP_DELAY >= (1 << 13)
+#error PICO_XOSC_STARTUP_DELAY_MULTIPLIER is too large: XOSC STARTUP.DELAY must be < 8192
+#endif
+
+void xosc_init(void) {
+    // Assumes 1-15 MHz input, checked above.
+    xosc_hw->ctrl = XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ;
+
+    // Set xosc startup delay
+    xosc_hw->startup = STARTUP_DELAY;
+
+    // Set the enable bit now that we have set freq range and startup delay
+    hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB);
+
+    // Wait for XOSC to be stable
+    while(!(xosc_hw->status & XOSC_STATUS_STABLE_BITS));
+}
+
+void xosc_disable(void) {
+    uint32_t tmp = xosc_hw->ctrl;
+    tmp &= (~XOSC_CTRL_ENABLE_BITS);
+    tmp |= (XOSC_CTRL_ENABLE_VALUE_DISABLE << XOSC_CTRL_ENABLE_LSB);
+    xosc_hw->ctrl = tmp;
+    // Wait for stable to go away
+    while(xosc_hw->status & XOSC_STATUS_STABLE_BITS);
+}
+
+void xosc_dormant(void) {
+    // WARNING: This stops the xosc until woken up by an irq
+    xosc_hw->dormant = XOSC_DORMANT_VALUE_DORMANT;
+    // Wait for it to become stable once woken up
+    while(!(xosc_hw->status & XOSC_STATUS_STABLE_BITS));
+}
diff --git a/src/rp2_common/pico_bit_ops/CMakeLists.txt b/src/rp2_common/pico_bit_ops/CMakeLists.txt
new file mode 100644
index 0000000..962c307
--- /dev/null
+++ b/src/rp2_common/pico_bit_ops/CMakeLists.txt
@@ -0,0 +1,48 @@
+if (NOT TARGET pico_bit_ops)
+    #shims for ROM functions for -lgcc functions  (listed below)
+    pico_add_impl_library(pico_bit_ops)
+
+    # no custom implementation; falls thru to compiler
+    pico_add_impl_library(pico_bit_ops_compiler)
+
+    # add alias "default" which is just pico.
+    add_library(pico_bit_ops_default INTERFACE)
+    target_link_libraries(pico_bit_ops_default INTERFACE pico_bit_ops_pico)
+
+    set(PICO_DEFAULT_BIT_OPS_IMPL pico_bit_ops_default)
+
+    pico_add_impl_library(pico_bit_ops_pico)
+    target_link_libraries(pico_bit_ops INTERFACE
+            $<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_BIT_OPS_IMPL>>,$<TARGET_PROPERTY:PICO_TARGET_BIT_OPS_IMPL>,${PICO_DEFAULT_BIT_OPS_IMPL}>)
+
+    target_sources(pico_bit_ops_pico INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/bit_ops_aeabi.S
+            )
+
+    target_link_libraries(pico_bit_ops_pico INTERFACE pico_bootrom pico_bit_ops_headers)
+
+    # gcc
+    pico_wrap_function(pico_bit_ops_pico __clzsi2)
+    pico_wrap_function(pico_bit_ops_pico __clzsi2)
+    pico_wrap_function(pico_bit_ops_pico __clzdi2)
+    pico_wrap_function(pico_bit_ops_pico __ctzsi2)
+    pico_wrap_function(pico_bit_ops_pico __ctzdi2)
+    pico_wrap_function(pico_bit_ops_pico __popcountsi2)
+    pico_wrap_function(pico_bit_ops_pico __popcountdi2)
+
+    # armclang
+    pico_wrap_function(pico_bit_ops_pico __clz)
+    pico_wrap_function(pico_bit_ops_pico __clzl)
+    pico_wrap_function(pico_bit_ops_pico __clzsi2)
+    pico_wrap_function(pico_bit_ops_pico __clzll)
+
+    macro(pico_set_bit_ops_implementation TARGET IMPL)
+        get_target_property(target_type ${TARGET} TYPE)
+        if ("EXECUTABLE" STREQUAL "${target_type}")
+            set_target_properties(${TARGET} PROPERTIES PICO_TARGET_BIT_OPS_IMPL "pico_bit_ops_${IMPL}")
+        else()
+            message(FATAL_ERROR "bit_ops implementation must be set on executable not library")
+        endif()
+    endmacro()
+    
+endif()
diff --git a/src/rp2_common/pico_bit_ops/bit_ops_aeabi.S b/src/rp2_common/pico_bit_ops/bit_ops_aeabi.S
new file mode 100644
index 0000000..eba839e
--- /dev/null
+++ b/src/rp2_common/pico_bit_ops/bit_ops_aeabi.S
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+#include "pico/asm_helper.S"
+#include "pico/bootrom.h"
+
+__pre_init __aeabi_bits_init, 00010
+
+.macro bits_section name
+#if PICO_BITS_IN_RAM
+.section RAM_SECTION_NAME(\name), "ax"
+#else
+.section SECTION_NAME(\name), "ax"
+#endif
+.endm
+
+.section .data.aeabi_bits_funcs
+.global aeabi_bits_funcs, aeabi_bits_funcs_end
+.equ BITS_FUNC_COUNT, 4
+.align 4
+aeabi_bits_funcs:
+    .word ROM_FUNC_POPCOUNT32
+    .word ROM_FUNC_CLZ32
+    .word ROM_FUNC_CTZ32
+    .word ROM_FUNC_REVERSE32
+aeabi_bits_funcs_end:
+
+.section .text
+.thumb_func
+__aeabi_bits_init:
+    ldr r0, =aeabi_bits_funcs
+    movs r1, #BITS_FUNC_COUNT
+    ldr r3, =rom_funcs_lookup
+    bx r3
+
+.equ POPCOUNT32, 0
+.equ CLZ32, 4
+.equ CTZ32, 8
+.equ REVERSE32, 12
+
+bits_section clzsi
+wrapper_func __clz
+wrapper_func __clzl
+wrapper_func __clzsi2
+    ldr r3, =aeabi_bits_funcs
+    ldr r3, [r3, #CLZ32]
+    bx r3
+
+bits_section ctzsi
+wrapper_func __ctzsi2
+    ldr r3, =aeabi_bits_funcs
+    ldr r3, [r3, #CTZ32]
+    bx r3
+
+bits_section popcountsi
+wrapper_func __popcountsi2
+    ldr r3, =aeabi_bits_funcs
+    ldr r3, [r3, #POPCOUNT32]
+    bx r3
+
+bits_section clzdi
+wrapper_func __clzll
+wrapper_func __clzdi2
+    ldr r3, =aeabi_bits_funcs
+    ldr r3, [r3, #CLZ32]
+    cmp r1, #0
+    bne 1f
+    push {lr}
+    blx r3
+    adds r0, #32
+    pop {pc}
+1:
+    mov r0, r1
+    bx r3
+
+bits_section ctzdi
+wrapper_func __ctzdi2
+    ldr r3, =aeabi_bits_funcs
+    ldr r3, [r3, #CTZ32]
+    cmp r0, #0
+    bne 1f
+    bx r3
+1:
+    push {lr}
+    mov r0, r1
+    blx r3
+    adds r0, #32
+    pop {pc}
+
+bits_section popcountdi
+wrapper_func __popcountdi2
+    ldr r3, =aeabi_bits_funcs
+    ldr r3, [r3, #POPCOUNT32]
+    push {r1, r3, lr}
+    blx r3
+    mov ip, r0
+    pop {r0, r3}
+    blx r3
+    mov r1, ip
+    add r0, r1
+    pop {pc}
+
+bits_section reverse32
+regular_func reverse32
+    ldr r3, =aeabi_bits_funcs
+    ldr r3, [r3, #REVERSE32]
+    bx r3
+
+bits_section __rev
+regular_func __rev
+regular_func __revl
+    ldr r3, =aeabi_bits_funcs
+    ldr r3, [r3, #REVERSE32]
+    bx r3
+
+bits_section __revll
+regular_func __revll
+    push {lr}
+    ldr r3, =aeabi_bits_funcs
+    ldr r3, [r3, #REVERSE32]
+    push {r1, r3}
+    blx r3
+    mov ip, r0 // reverse32 preserves ip
+    pop {r0, r3}
+    blx r3
+    mov r1, ip
+    pop {pc}
diff --git a/src/rp2_common/pico_bootrom/CMakeLists.txt b/src/rp2_common/pico_bootrom/CMakeLists.txt
new file mode 100644
index 0000000..58ea575
--- /dev/null
+++ b/src/rp2_common/pico_bootrom/CMakeLists.txt
@@ -0,0 +1,8 @@
+add_library(pico_bootrom INTERFACE)
+
+target_sources(pico_bootrom INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/bootrom.c
+        )
+
+target_include_directories(pico_bootrom INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+target_link_libraries(pico_bootrom INTERFACE pico_base_headers)
diff --git a/src/rp2_common/pico_bootrom/bootrom.c b/src/rp2_common/pico_bootrom/bootrom.c
new file mode 100644
index 0000000..af7d091
--- /dev/null
+++ b/src/rp2_common/pico_bootrom/bootrom.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/bootrom.h"
+
+/// \tag::table_lookup[]
+
+// Bootrom function: rom_table_lookup
+// Returns the 32 bit pointer into the ROM if found or NULL otherwise.
+typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code);
+
+// Convert a 16 bit pointer stored at the given rom address into a 32 bit pointer
+#define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)rom_address)
+
+void *rom_func_lookup(uint32_t code) {
+    return rom_func_lookup_inline(code);
+}
+
+void *rom_data_lookup(uint32_t code) {
+    rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18);
+    uint16_t *data_table = (uint16_t *) rom_hword_as_ptr(0x16);
+    return rom_table_lookup(data_table, code);
+}
+/// \end::table_lookup[]
+
+bool rom_funcs_lookup(uint32_t *table, unsigned int count) {
+    bool ok = true;
+    for (unsigned int i = 0; i < count; i++) {
+        table[i] = (uintptr_t) rom_func_lookup(table[i]);
+        if (!table[i]) ok = false;
+    }
+    return ok;
+}
diff --git a/src/rp2_common/pico_bootrom/include/pico/bootrom.h b/src/rp2_common/pico_bootrom/include/pico/bootrom.h
new file mode 100644
index 0000000..e557893
--- /dev/null
+++ b/src/rp2_common/pico_bootrom/include/pico/bootrom.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PLATFORM_BOOTROM_H
+#define _PLATFORM_BOOTROM_H
+
+#include "pico.h"
+
+/** \file bootrom.h
+ * \defgroup pico_bootrom pico_bootrom
+ * Access to functions and data in the RP2040 bootrom
+ *
+ * This header may be included by assembly code
+ */
+
+// ROM FUNCTIONS
+
+#define ROM_FUNC_POPCOUNT32             ROM_TABLE_CODE('P', '3')
+#define ROM_FUNC_REVERSE32              ROM_TABLE_CODE('R', '3')
+#define ROM_FUNC_CLZ32                  ROM_TABLE_CODE('L', '3')
+#define ROM_FUNC_CTZ32                  ROM_TABLE_CODE('T', '3')
+#define ROM_FUNC_MEMSET                 ROM_TABLE_CODE('M', 'S')
+#define ROM_FUNC_MEMSET4                ROM_TABLE_CODE('S', '4')
+#define ROM_FUNC_MEMCPY                 ROM_TABLE_CODE('M', 'C')
+#define ROM_FUNC_MEMCPY44               ROM_TABLE_CODE('C', '4')
+#define ROM_FUNC_RESET_USB_BOOT         ROM_TABLE_CODE('U', 'B')
+#define ROM_FUNC_CONNECT_INTERNAL_FLASH ROM_TABLE_CODE('I', 'F')
+#define ROM_FUNC_FLASH_EXIT_XIP         ROM_TABLE_CODE('E', 'X')
+#define ROM_FUNC_FLASH_RANGE_ERASE      ROM_TABLE_CODE('R', 'E')
+#define ROM_FUNC_FLASH_RANGE_PROGRAM    ROM_TABLE_CODE('R', 'P')
+#define ROM_FUNC_FLASH_FLUSH_CACHE      ROM_TABLE_CODE('F', 'C')
+#define ROM_FUNC_FLASH_ENTER_CMD_XIP    ROM_TABLE_CODE('C', 'X')
+
+/*! \brief Return a bootrom lookup code based on two ASCII characters
+ * \ingroup pico_bootrom
+ *
+ * These codes are uses to lookup data or function addresses in the bootrom
+ *
+ * \param c1 the first character
+ * \param c2 the second character
+ * \return the 'code' to use in rom_func_lookup() or rom_data_lookup()
+ */
+#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8))
+
+#ifndef __ASSEMBLER__
+
+// ROM FUNCTION SIGNATURES
+
+typedef uint32_t (*rom_popcount32_fn)(uint32_t);
+typedef uint32_t (*rom_reverse32_fn)(uint32_t);
+typedef uint32_t (*rom_clz32_fn)(uint32_t);
+typedef uint32_t (*rom_ctz32_fn)(uint32_t);
+typedef uint8_t *(*rom_memset_fn)(uint8_t *, uint8_t, uint32_t);
+typedef uint32_t *(*rom_memset4_fn)(uint32_t *, uint8_t, uint32_t);
+typedef uint32_t *(*rom_memcpy_fn)(uint8_t *, const uint8_t *, uint32_t);
+typedef uint32_t *(*rom_memcpy44_fn)(uint32_t *, const uint32_t *, uint32_t);
+typedef void __attribute__((noreturn)) (*rom_reset_usb_boot_fn)(uint32_t, uint32_t);
+typedef rom_reset_usb_boot_fn reset_usb_boot_fn; // kept for backwards compatibility
+typedef void (*rom_connect_internal_flash_fn)(void);
+typedef void (*rom_flash_exit_xip_fn)(void);
+typedef void (*rom_flash_range_erase_fn)(uint32_t, size_t, uint32_t, uint8_t);
+typedef void (*rom_flash_range_program_fn)(uint32_t, const uint8_t*, size_t);
+typedef void (*rom_flash_flush_cache_fn)(void);
+typedef void (*rom_flash_enter_cmd_xip_fn)(void);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Return a bootrom lookup code based on two ASCII characters
+ * \ingroup pico_bootrom
+ *
+ * These codes are uses to lookup data or function addresses in the bootrom
+ *
+ * \param c1 the first character
+ * \param c2 the second character
+ * \return the 'code' to use in rom_func_lookup() or rom_data_lookup()
+ */
+static inline uint32_t rom_table_code(uint8_t c1, uint8_t c2) {
+    return ROM_TABLE_CODE((uint32_t) c1, (uint32_t) c2);
+}
+
+/*!
+ * \brief Lookup a bootrom function by code
+ * \ingroup pico_bootrom
+ * \param code the code
+ * \return a pointer to the function, or NULL if the code does not match any bootrom function
+ */
+void *rom_func_lookup(uint32_t code);
+
+/*!
+ * \brief Lookup a bootrom address by code
+ * \ingroup pico_bootrom
+ * \param code the code
+ * \return a pointer to the data, or NULL if the code does not match any bootrom function
+ */
+void *rom_data_lookup(uint32_t code);
+
+/*!
+ * \brief Helper function to lookup the addresses of multiple bootrom functions
+ * \ingroup pico_bootrom
+ *
+ * This method looks up the 'codes' in the table, and convert each table entry to the looked up
+ * function pointer, if there is a function for that code in the bootrom.
+ *
+ * \param table an IN/OUT array, elements are codes on input, function pointers on success.
+ * \param count the number of elements in the table
+ * \return true if all the codes were found, and converted to function pointers, false otherwise
+ */
+bool rom_funcs_lookup(uint32_t *table, unsigned int count);
+
+// Bootrom function: rom_table_lookup
+// Returns the 32 bit pointer into the ROM if found or NULL otherwise.
+typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code);
+
+// Convert a 16 bit pointer stored at the given rom address into a 32 bit pointer
+#define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)rom_address)
+
+/*!
+ * \brief Lookup a bootrom function by code. This method is forceably inlined into the caller for FLASH/RAM sensitive code usage
+ * \ingroup pico_bootrom
+ * \param code the code
+ * \return a pointer to the function, or NULL if the code does not match any bootrom function
+ */
+static __force_inline void *rom_func_lookup_inline(uint32_t code) {
+    rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18);
+    uint16_t *func_table = (uint16_t *) rom_hword_as_ptr(0x14);
+    return rom_table_lookup(func_table, code);
+}
+
+/*!
+ * \brief Reboot the device into BOOTSEL mode
+ * \ingroup pico_bootrom
+ *
+ * This function reboots the device into the BOOTSEL mode ('usb boot").
+ *
+ * Facilities are provided to enable an "activity light" via GPIO attached LED for the USB Mass Storage Device,
+ * and to limit the USB interfaces exposed.
+ *
+ * \param usb_activity_gpio_pin_mask 0 No pins are used as per a cold boot. Otherwise a single bit set indicating which
+ *                               GPIO pin should be set to output and raised whenever there is mass storage activity
+ *                               from the host.
+ * \param disable_interface_mask value to control exposed interfaces
+ *  - 0 To enable both interfaces (as per a cold boot)
+ *  - 1 To disable the USB Mass Storage Interface
+ *  - 2 To disable the USB PICOBOOT Interface
+ */
+static inline void __attribute__((noreturn)) reset_usb_boot(uint32_t usb_activity_gpio_pin_mask,
+                                                            uint32_t disable_interface_mask) {
+    rom_reset_usb_boot_fn func = (rom_reset_usb_boot_fn) rom_func_lookup(ROM_FUNC_RESET_USB_BOOT);
+    func(usb_activity_gpio_pin_mask, disable_interface_mask);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !__ASSEMBLER__
+#endif
diff --git a/src/rp2_common/pico_bootrom/include/pico/bootrom/sf_table.h b/src/rp2_common/pico_bootrom/include/pico/bootrom/sf_table.h
new file mode 100644
index 0000000..4eb4b1c
--- /dev/null
+++ b/src/rp2_common/pico_bootrom/include/pico/bootrom/sf_table.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_SF_TABLE_H
+#define _PICO_SF_TABLE_H
+
+// NOTE THESE FUNCTION IMPLEMENTATIONS MATCH THE BEHAVIOR DESCRIBED IN THE BOOTROM SECTION OF THE RP2040 DATASHEET
+
+#define SF_TABLE_FADD               0x00
+#define SF_TABLE_FSUB               0x04
+#define SF_TABLE_FMUL               0x08
+#define SF_TABLE_FDIV               0x0c
+#define SF_TABLE_FCMP_FAST          0x10
+#define SF_TABLE_FCMP_FAST_FLAGS    0x14
+#define SF_TABLE_FSQRT              0x18
+#define SF_TABLE_FLOAT2INT          0x1c
+#define SF_TABLE_FLOAT2FIX          0x20
+#define SF_TABLE_FLOAT2UINT         0x24
+#define SF_TABLE_FLOAT2UFIX         0x28
+#define SF_TABLE_INT2FLOAT          0x2c
+#define SF_TABLE_FIX2FLOAT          0x30
+#define SF_TABLE_UINT2FLOAT         0x34
+#define SF_TABLE_UFIX2FLOAT         0x38
+#define SF_TABLE_FCOS               0x3c
+#define SF_TABLE_FSIN               0x40
+#define SF_TABLE_FTAN               0x44
+#define SF_TABLE_V3_FSINCOS         0x48
+#define SF_TABLE_FEXP               0x4c
+#define SF_TABLE_FLN                0x50
+
+#define SF_TABLE_V1_SIZE            0x54
+
+#define SF_TABLE_FCMP_BASIC         0x54
+#define SF_TABLE_FATAN2             0x58
+#define SF_TABLE_INT642FLOAT        0x5c
+#define SF_TABLE_FIX642FLOAT        0x60
+#define SF_TABLE_UINT642FLOAT       0x64
+#define SF_TABLE_UFIX642FLOAT       0x68
+#define SF_TABLE_FLOAT2INT64        0x6c
+#define SF_TABLE_FLOAT2FIX64        0x70
+#define SF_TABLE_FLOAT2UINT64       0x74
+#define SF_TABLE_FLOAT2UFIX64       0x78
+#define SF_TABLE_FLOAT2DOUBLE       0x7c
+
+#define SF_TABLE_V2_SIZE            0x80
+
+#endif
diff --git a/src/rp2_common/pico_bootsel_via_double_reset/CMakeLists.txt b/src/rp2_common/pico_bootsel_via_double_reset/CMakeLists.txt
new file mode 100644
index 0000000..17b4042
--- /dev/null
+++ b/src/rp2_common/pico_bootsel_via_double_reset/CMakeLists.txt
@@ -0,0 +1,10 @@
+pico_add_impl_library(pico_bootsel_via_double_reset)
+
+target_sources(pico_bootsel_via_double_reset INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/pico_bootsel_via_double_reset.c
+        )
+
+target_link_libraries(pico_bootsel_via_double_reset INTERFACE
+        pico_bootrom
+        pico_time
+        )
diff --git a/src/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c b/src/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c
new file mode 100644
index 0000000..d333ab2
--- /dev/null
+++ b/src/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+#include "pico/time.h"
+#include "pico/bootrom.h"
+#include "pico/binary_info.h"
+
+// PICO_CONFIG: PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS, Window of opportunity for a second press of a reset button to enter BOOTSEL mode (milliseconds), type=int, default=200, group=pico_bootsel_via_double_reset
+#ifndef PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS
+#define PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS 200
+#endif
+
+// PICO_CONFIG: PICO_BOOTSEL_VIA_DOUBLE_RESET_ACTIVITY_LED, Optionally define a pin to use as bootloader activity LED when BOOTSEL mode is entered via reset double tap, type=int, min=0, max=29, group=pico_bootsel_via_double_reset
+
+// PICO_CONFIG: PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK, Optionally disable either the mass storage interface (bit 0) or the PICOBOOT interface (bit 1) when entering BOOTSEL mode via double reset, type=int, min=0, max=3, default=0, group=pico_bootsel_via_double_reset
+#ifndef PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK
+#define PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK 0u
+#endif
+
+/** \defgroup pico_bootsel_via_double_reset pico_bootsel_via_double_reset
+ *
+ * When the 'pico_bootsel_via_double_reset' library is linked, a function is
+ * injected before main() which will detect when the system has been reset
+ * twice in quick succession, and enter the USB ROM bootloader (BOOTSEL mode)
+ * when this happens. This allows a double tap of a reset button on a
+ * development board to be used to enter the ROM bootloader, provided this
+ * library is always linked.
+ */
+
+#if !PICO_NO_BI_BOOTSEL_VIA_DOUBLE_RESET
+bi_decl(bi_program_feature("double reset -> BOOTSEL"));
+#endif
+
+// Doesn't make any sense for a RAM only binary
+#if !PICO_NO_FLASH
+static const uint32_t magic_token[] = {
+        0xf01681de, 0xbd729b29, 0xd359be7a,
+};
+
+static uint32_t __uninitialized_ram(magic_location)[count_of(magic_token)];
+
+/* Check for double reset and enter BOOTSEL mode if detected
+ *
+ * This function is registered to run automatically before main(). The
+ * algorithm is:
+ *
+ *   1. Check for magic token in memory; enter BOOTSEL mode if found.
+ *   2. Initialise that memory with that magic token.
+ *   3. Do nothing for a short while (few hundred ms).
+ *   4. Clear the magic token.
+ *   5. Continue with normal boot.
+ *
+ * Resetting the device twice quickly will interrupt step 3, leaving the token
+ * in place so that the second boot will go to the bootloader.
+ */
+static void __attribute__((constructor)) boot_double_tap_check(void) {
+    for (uint i = 0; i < count_of(magic_token); i++) {
+        if (magic_location[i] != magic_token[i]) {
+            // Arm, wait, then disarm and continue booting
+            for (i = 0; i < count_of(magic_token); i++) {
+                magic_location[i] = magic_token[i];
+            }
+            busy_wait_us(PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS * 1000);
+            magic_location[0] = 0;
+            return;
+        }
+    }
+    // Detected a double reset, so enter USB bootloader
+    magic_location[0] = 0;
+#ifdef PICO_BOOTSEL_VIA_DOUBLE_RESET_ACTIVITY_LED
+    const uint32_t led_mask = 1u << PICO_BOOTSEL_VIA_DOUBLE_RESET_ACTIVITY_LED;
+#else
+    const uint32_t led_mask = 0u;
+#endif
+    reset_usb_boot(
+        led_mask,
+        PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK
+    );
+}
+
+#endif
diff --git a/src/rp2_common/pico_cxx_options/CMakeLists.txt b/src/rp2_common/pico_cxx_options/CMakeLists.txt
new file mode 100644
index 0000000..4b20e3a
--- /dev/null
+++ b/src/rp2_common/pico_cxx_options/CMakeLists.txt
@@ -0,0 +1,23 @@
+if (NOT TARGET pico_cxx_options)
+    add_library(pico_cxx_options INTERFACE)
+
+    # PICO_CMAKE_CONFIG: PICO_CXX_ENABLE_EXCEPTIONS, Enabled CXX exception handling, type=bool, default=0, group=pico_cxx_options
+    # PICO_BUILD_DEFINE: PICO_CXX_ENABLE_EXCEPTIONS, value of CMake var PICO_CXX_ENABLE_EXCEPTIONS, type=string, default=0, group=pico_cxx_options
+    if (NOT PICO_CXX_ENABLE_EXCEPTIONS)
+        target_compile_definitions( pico_cxx_options INTERFACE PICO_CXX_ENABLE_EXCEPTIONS=0)
+        target_compile_options( pico_cxx_options INTERFACE $<$<COMPILE_LANGUAGE:CXX>:-fno-exceptions>)
+        target_compile_options( pico_cxx_options INTERFACE $<$<COMPILE_LANGUAGE:CXX>:-fno-unwind-tables>)
+    else()
+        target_compile_definitions( pico_cxx_options INTERFACE PICO_CXX_ENABLE_EXCEPTIONS=1)
+    endif()
+
+    # PICO_CMAKE_CONFIG: PICO_CXX_ENABLE_RTTI, Enabled CXX rtti, type=bool, default=0, group=pico_cxx_options
+    if (NOT PICO_CXX_ENABLE_RTTI)
+        target_compile_options( pico_cxx_options INTERFACE $<$<COMPILE_LANGUAGE:CXX>:-fno-rtti>)
+    endif()
+
+    # PICO_CMAKE_CONFIG: PICO_CXX_ENABLE_CXA_ATEXIT, Enabled cxa-atexit, type=bool, default=0, group=pico_cxx_options
+    if (NOT PICO_CXX_ENABLE_CXA_ATEXIT)
+        target_compile_options( pico_cxx_options INTERFACE $<$<COMPILE_LANGUAGE:CXX>:-fno-use-cxa-atexit>)
+    endif()
+endif()
diff --git a/src/rp2_common/pico_cxx_options/doc.h b/src/rp2_common/pico_cxx_options/doc.h
new file mode 100644
index 0000000..5d84e22
--- /dev/null
+++ b/src/rp2_common/pico_cxx_options/doc.h
@@ -0,0 +1,4 @@
+/**
+ * \defgroup pico_cxx_options pico_cxx_options
+ * \brief non-code library controlling C++ related compile options
+ */
diff --git a/src/rp2_common/pico_divider/CMakeLists.txt b/src/rp2_common/pico_divider/CMakeLists.txt
new file mode 100644
index 0000000..ceed042
--- /dev/null
+++ b/src/rp2_common/pico_divider/CMakeLists.txt
@@ -0,0 +1,47 @@
+if (NOT TARGET pico_divider)
+    # library to be depended on - we make this depend on particular implementations using per target generator expressions
+    pico_add_impl_library(pico_divider)
+
+    # no custom implementation; falls thru to compiler
+    pico_add_impl_library(pico_divider_compiler)
+
+    # add alias "default" which is just hardware.
+    add_library(pico_divider_default INTERFACE)
+    target_link_libraries(pico_divider_default INTERFACE pico_divider_hardware)
+
+    set(PICO_DEFAULT_DIVIDER_IMPL pico_divider_default)
+
+    target_link_libraries(pico_divider INTERFACE
+            $<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_DIVIDER_IMPL>>,$<TARGET_PROPERTY:PICO_TARGET_DIVIDER_IMPL>,${PICO_DEFAULT_DIVIDER_IMPL}>)
+
+    add_library(pico_divider_hardware_explicit INTERFACE)
+    target_sources(pico_divider_hardware_explicit INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/divider.S
+            )
+
+    target_link_libraries(pico_divider_hardware_explicit INTERFACE
+            pico_divider_headers
+            hardware_divider
+            hardware_regs
+            )
+
+    pico_add_impl_library(pico_divider_hardware)
+
+    target_link_libraries(pico_divider_hardware INTERFACE pico_divider_hardware_explicit)
+
+    pico_wrap_function(pico_divider_hardware __aeabi_idiv)
+    pico_wrap_function(pico_divider_hardware __aeabi_idivmod)
+    pico_wrap_function(pico_divider_hardware __aeabi_ldivmod)
+    pico_wrap_function(pico_divider_hardware __aeabi_uidiv)
+    pico_wrap_function(pico_divider_hardware __aeabi_uidivmod)
+    pico_wrap_function(pico_divider_hardware __aeabi_uldivmod)
+
+    macro(pico_set_divider_implementation TARGET IMPL)
+        get_target_property(target_type ${TARGET} TYPE)
+        if ("EXECUTABLE" STREQUAL "${target_type}")
+            set_target_properties(${TARGET} PROPERTIES PICO_TARGET_DIVIDER_IMPL "pico_divider_${IMPL}")
+        else()
+            message(FATAL_ERROR "divider implementation must be set on executable not library")
+        endif()
+    endmacro()
+endif()
diff --git a/src/rp2_common/pico_divider/divider.S b/src/rp2_common/pico_divider/divider.S
new file mode 100644
index 0000000..234c1a4
--- /dev/null
+++ b/src/rp2_common/pico_divider/divider.S
@@ -0,0 +1,882 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/regs/addressmap.h"
+#include "hardware/divider_helper.S"
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+// PICO_CONFIG: PICO_DIVIDER_DISABLE_INTERRUPTS, Disable interrupts around division such that divider state need not be saved/restored in exception handlers, default=0, group=pico_divider
+
+#include "pico/asm_helper.S"
+
+// PICO_CONFIG: PICO_DIVIDER_CALL_IDIV0, Whether 32 bit division by zero should call __aeabi_idiv0, default=1, group=pico_divider
+#ifndef PICO_DIVIDER_CALL_IDIV0
+#define PICO_DIVIDER_CALL_IDIV0 1
+#endif
+
+// PICO_CONFIG: PICO_DIVIDER_CALL_IDIV0, Whether 64 bit division by zero should call __aeabi_ldiv0, default=1, group=pico_divider
+#ifndef PICO_DIVIDER_CALL_LDIV0
+#define PICO_DIVIDER_CALL_LDIV0 1
+#endif
+
+// PICO_CONFIG: PICO_DIVIDER_IN_RAM, Whether divider functions should be placed in RAM, default=0, group=pico_divider
+.macro div_section name
+#if PICO_DIVIDER_IN_RAM
+.section RAM_SECTION_NAME(\name), "ax"
+#else
+.section SECTION_NAME(\name), "ax"
+#endif
+.endm
+
+@ wait 8-n cycles for the hardware divider
+.macro wait_div n
+.rept (8-\n) / 2
+  b 9f
+9:
+.endr
+.if (8-\n) % 2
+ nop
+.endif
+.endm
+
+#if (SIO_DIV_SDIVISOR_OFFSET != SIO_DIV_SDIVIDEND_OFFSET + 4) || (SIO_DIV_QUOTIENT_OFFSET != SIO_DIV_SDIVISOR_OFFSET + 4) || (SIO_DIV_REMAINDER_OFFSET != SIO_DIV_QUOTIENT_OFFSET + 4)
+#error register layout has changed - we rely on this order to make sure we save/restore in the right order
+#endif
+
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+.macro save_div_state_and_lr_64
+    push {r4, r5, r6, r7, lr}
+    ldr r6, =SIO_BASE
+1:
+    ldr r5, [r6, #SIO_DIV_CSR_OFFSET]
+    // wait for results as we can't save signed-ness of operation
+    lsrs r5, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY
+    bcc 1b
+    // note we must read quotient last, and since it isn't the last reg, we'll not use ldmia!
+    ldr r4, [r6, #SIO_DIV_UDIVIDEND_OFFSET]
+    ldr r5, [r6, #SIO_DIV_UDIVISOR_OFFSET]
+    ldr r7, [r6, #SIO_DIV_REMAINDER_OFFSET]
+    ldr r6, [r6, #SIO_DIV_QUOTIENT_OFFSET]
+.endm
+
+.macro restore_div_state_and_return_64
+    // writing sdividend (r4), sdivisor (r5), quotient (r6), remainder (r7) in that order
+    //
+    // it is worth considering what happens if we are interrupted
+    //
+    // after writing r4: we are DIRTY and !READY
+    //    ... interruptor using div will complete based on incorrect inputs, but dividend at least will be
+    //        saved/restored correctly and we'll restore the rest ourselves
+    // after writing r4, r5: we are DIRTY and !READY
+    //    ... interruptor using div will complete based on possibly wrongly signed inputs, but dividend, divisor
+    //        at least will be saved/restored correctly and and we'll restore the rest ourselves
+    // after writing r4, r5, r6: we are DIRTY and READY
+    //    ... interruptor using div will dividend, divisor, quotient registers as is (what we just restored ourselves),
+    //        and we'll restore the remainder after the fact
+
+    mov ip, r2
+    ldr r2, =SIO_BASE
+    // note we are not use STM not because it can be restarted due to interrupt which is harmless, more because this is 1 cycle IO space
+    // and so 4 reads is cheaper (and we don't have to adjust r2)
+    str r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET]
+    str r5, [r2, #SIO_DIV_UDIVISOR_OFFSET]
+    str r7, [r2, #SIO_DIV_REMAINDER_OFFSET]
+    str r6, [r2, #SIO_DIV_QUOTIENT_OFFSET]
+    mov r2, ip
+    pop {r4, r5, r6, r7, pc}
+.endm
+
+#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */
+
+// since idiv and idivmod only differ by a cycle, we'll make them the same!
+div_section WRAPPER_FUNC_NAME(__aeabi_idiv)
+.align 2
+wrapper_func __aeabi_idiv
+wrapper_func __aeabi_idivmod
+regular_func div_s32s32
+regular_func divmod_s32s32
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+    // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
+    ldr r2, =(SIO_BASE)
+    ldr r3, [r2, #SIO_DIV_CSR_OFFSET]
+    lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
+    bcs divmod_s32s32_savestate
+regular_func divmod_s32s32_unsafe
+#else
+// to avoid too much source code spaghetti with restoring interrupts, we make this the same as the other funcs
+// in the PICO_DIVIDER_DISABLE_INTERRUPTS case; i.e. it is not a faster function; this seems reasonable as there
+// are the hardware_divider functions that can be used instead anyway
+regular_func divmod_s32s32_unsafe
+    // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+    ldr r2, =(SIO_BASE)
+    mrs r3, PRIMASK
+    cpsid i
+#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */
+    str r0, [r2, #SIO_DIV_SDIVIDEND_OFFSET]
+    str r1, [r2, #SIO_DIV_SDIVISOR_OFFSET]
+    cmp r1, #0
+    beq 1f
+    wait_div 2
+    // return 64 bit value so we can efficiently return both (note read order is important since QUOTIENT must be read last)
+    ldr r1, [r2, #SIO_DIV_REMAINDER_OFFSET]
+    ldr r0, [r2, #SIO_DIV_QUOTIENT_OFFSET]
+#if PICO_DIVIDER_DISABLE_INTERRUPTS
+    msr PRIMASK, r3
+#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */
+    bx lr
+1:
+#if PICO_DIVIDER_DISABLE_INTERRUPTS
+    msr PRIMASK, r3
+#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */
+    push {r2, lr}
+    movs r1, #0x80
+    lsls r1, #24
+    asrs r2, r0, #31
+    eors r1, r2
+    cmp r0, #0
+    beq 1f
+    mvns r0, r1
+1:
+#if PICO_DIVIDER_CALL_IDIV0
+    bl __aeabi_idiv0
+#endif
+    movs r1, #0 // remainder 0
+    // need to restore saved r2 as it hold SIO ptr
+    pop {r2, pc}
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+.align 2
+regular_func divmod_s32s32_savestate
+    // note that we must be at least 2 cycles into division at this point,
+    // which we are because of the firty check before getting here (and of course the function call before that)
+    save_div_state_and_lr
+    bl divmod_s32s32_unsafe
+    restore_div_state_and_return
+#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */
+
+// since uidiv and uidivmod only differ by a cycle, we'll make them the same!
+div_section WRAPPER_FUNC_NAME(__aeabi_uidiv)
+regular_func div_u32u32
+regular_func divmod_u32u32
+wrapper_func __aeabi_uidiv
+wrapper_func __aeabi_uidivmod
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+    // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
+    ldr r2, =(SIO_BASE)
+    ldr r3, [r2, #SIO_DIV_CSR_OFFSET]
+    lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
+    bcs divmod_u32u32_savestate
+regular_func divmod_u32u32_unsafe
+#else
+// to avoid too much source code spaghetti with restoring interrupts, we make this the same as the other funcs
+// in the PICO_DIVIDER_DISABLE_INTERRUPTS case; i.e. it is not a faster function; this seems reasonable as there
+// are the hardware_divider functions that can be used instead anyway
+regular_func divmod_u32u32_unsafe
+    // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+    ldr r2, =(SIO_BASE)
+    mrs r3, PRIMASK
+    cpsid i
+#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */
+    str r0, [r2, #SIO_DIV_UDIVIDEND_OFFSET]
+    str r1, [r2, #SIO_DIV_UDIVISOR_OFFSET]
+    cmp r1, #0
+    beq 1f
+    wait_div 2
+    // return 64 bit value so we can efficiently return both (note read order is important since QUOTIENT must be read last)
+    ldr r1, [r2, #SIO_DIV_REMAINDER_OFFSET]
+    ldr r0, [r2, #SIO_DIV_QUOTIENT_OFFSET]
+#if PICO_DIVIDER_DISABLE_INTERRUPTS
+    msr PRIMASK, r3
+#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */
+    bx lr
+1:
+#if PICO_DIVIDER_DISABLE_INTERRUPTS
+    msr PRIMASK, r3
+#endif /* PICO_DIVIDER_DISABLE_INTERRUPTS */
+    push {r2, lr}
+    cmp r0, #0
+    beq 1f
+    movs r0, #0
+    mvns r0, r0
+1:
+#if PICO_DIVIDER_CALL_IDIV0
+    bl __aeabi_idiv0
+#endif
+    movs r1, #0 // remainder 0
+    // need to restore saved r2 as it hold SIO ptr
+    pop {r2, pc}
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+.align 2
+regular_func divmod_u32u32_savestate
+    save_div_state_and_lr
+    bl divmod_u32u32_unsafe
+    restore_div_state_and_return
+#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */
+
+div_section WRAPPER_FUNC_NAME(__aeabi_ldiv)
+
+.align 2
+wrapper_func __aeabi_ldivmod
+regular_func div_s64s64
+regular_func divmod_s64s64
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+    // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
+    mov ip, r2
+    ldr r2, =(SIO_BASE)
+    ldr r2, [r2, #SIO_DIV_CSR_OFFSET]
+    lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
+    mov r2, ip
+    bcs divmod_s64s64_savestate
+    b divmod_s64s64_unsafe
+.align 2
+divmod_s64s64_savestate:
+    save_div_state_and_lr_64
+    bl divmod_s64s64_unsafe
+    restore_div_state_and_return_64
+#else
+    // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+    push {r4, lr}
+    mrs r4, PRIMASK
+    cpsid i
+    bl divmod_s64s64_unsafe
+    msr PRIMASK, r4
+    pop {r4, pc}
+#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */
+
+.align 2
+wrapper_func __aeabi_uldivmod
+regular_func div_u64u64
+regular_func divmod_u64u64
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+    // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
+    mov ip, r2
+    ldr r2, =(SIO_BASE)
+    ldr r2, [r2, #SIO_DIV_CSR_OFFSET]
+    lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
+    mov r2, ip
+    bcs divmod_u64u64_savestate
+    b divmod_u64u64_unsafe
+.align 2
+regular_func divmod_u64u64_savestate
+    save_div_state_and_lr_64
+    bl divmod_u64u64_unsafe
+    restore_div_state_and_return_64
+#else
+    // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+    push {r4, lr}
+    mrs r4, PRIMASK
+    cpsid i
+    bl divmod_u64u64_unsafe
+    msr PRIMASK, r4
+    pop {r4, pc}
+#endif /* !PICO_DIVIDER_DISABLE_INTERRUPTS */
+
+.macro dneg lo,hi
+ mvns \hi,\hi
+ rsbs \lo,#0
+ bne l\@_1
+ adds \hi,#1
+l\@_1:
+.endm
+
+.align 2
+regular_func divmod_s64s64_unsafe
+ cmp r3,#0
+ blt 1f
+@ here x +ve
+ beq 2f                    @ could x be zero?
+3:
+ cmp r1,#0
+ bge divmod_u64u64_unsafe  @ both positive
+@ y -ve, x +ve
+ push {r14}
+ dneg r0,r1
+ bl divmod_u64u64_unsafe
+ dneg r0,r1
+ dneg r2,r3
+ pop {r15}
+
+2:
+ cmp r2,#0
+ bne 3b                    @ back if x not zero
+
+ cmp r0,#0                 @ y==0?
+ bne 4f
+ cmp r1,#0
+ beq 5f                    @ then pass 0 to __aeabi_ldiv0
+4:
+ movs r0,#0
+ lsrs r1,#31
+ lsls r1,#31               @ get sign bit
+ bne 5f                    @ y -ve? pass -2^63 to __aeabi_ldiv0
+ mvns r0,r0
+ lsrs r1,r0,#1             @ y +ve: pass 2^63-1 to __aeabi_ldiv0
+5:
+ push {r14}
+#if PICO_DIVIDER_CALL_LDIV0
+ bl __aeabi_ldiv0
+#endif
+ movs r2,#0                @ and return 0 for the remainder
+ movs r3,#0
+ pop {r15}
+
+1:
+@ here x -ve
+ push {r14}
+ cmp r1,#0
+ blt 1f
+@ y +ve, x -ve
+ dneg r2,r3
+ bl divmod_u64u64_unsafe
+ dneg r0,r1
+ pop {r15}
+
+1:
+@ y -ve, x -ve
+ dneg r0,r1
+ dneg r2,r3
+ bl divmod_u64u64_unsafe
+ dneg r2,r3
+ pop {r15}
+
+regular_func divmod_u64u64_unsafe
+ cmp r1,#0
+ bne y64                   @ y fits in 32 bits?
+ cmp r3,#0                 @ yes; and x?
+ bne 1f
+ cmp r2,#0
+ beq 2f                    @ x==0?
+ mov r12,r7
+ ldr r7,=#SIO_BASE
+ str r0,[r7,#SIO_DIV_UDIVIDEND_OFFSET]
+ str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET]
+ movs r1,#0
+ movs r3,#0
+ wait_div 2
+ ldr r2,[r7,#SIO_DIV_REMAINDER_OFFSET]
+ ldr r0,[r7,#SIO_DIV_QUOTIENT_OFFSET]
+ mov r7,r12
+ bx r14
+
+2:                         @ divide by 0 with y<2^32
+ cmp r0,#0                 @ y==0?
+ beq 3f                    @ then pass 0 to __aeabi_ldiv0
+udiv0:
+ ldr r0,=#0xffffffff
+ movs r1,r0                @ pass 2^64-1 to __aeabi_ldiv0
+3:
+ push {r14}
+#if PICO_DIVIDER_CALL_LDIV0
+ bl __aeabi_ldiv0
+#endif
+ movs r2,#0                @ and return 0 for the remainder
+ movs r3,#0
+ pop {r15}
+
+1:
+ movs r2,r0                @ x>y, so result is 0 remainder y
+ movs r3,r1
+ movs r0,#0
+ movs r1,#0
+ bx r14
+
+.ltorg
+
+@ here y occupies more than 32 bits
+@ split into cases acccording to the size of x
+y64:
+ cmp r3,#0
+ beq 1f
+ b y64_x48                 @ if x does not fit in 32 bits, go to 48- and 64-bit cases
+1:
+ lsrs r3,r2,#16
+ bne y64_x32               @ jump if x is 17..32 bits
+
+@ here x is at most 16 bits
+
+ cmp r2,#0
+ beq udiv0                 @ x==0? exit as with y!=0 case above
+ push {r7}
+ ldr r7,=#SIO_BASE
+ str r1,[r7,#SIO_DIV_UDIVIDEND_OFFSET]
+ str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET]
+ wait_div 4
+ push {r4, r5}
+ lsrs r4,r0,#16
+ ldr r3,[r7,#SIO_DIV_REMAINDER_OFFSET] @ r0=y0-q0*x; 0<=r0<x
+ ldr r1,[r7,#SIO_DIV_QUOTIENT_OFFSET]  @ q0=y0/x;
+ lsls r3,#16
+ orrs r3,r4
+ str r3,[r7,#SIO_DIV_UDIVIDEND_OFFSET] @ y1=(r0<<16)+(((ui32)y)>>16);
+ str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET]  @ must set divisor again, as we do not save/restore regs at all in IRQs if not dirty
+ wait_div 1
+ uxth r4,r0
+ ldr r3,[r7,#SIO_DIV_REMAINDER_OFFSET] @ r1=y1-q1*x; 0<=r1<x
+ ldr r5,[r7,#SIO_DIV_QUOTIENT_OFFSET]  @ q1=y1/x;
+ lsls r3,#16
+ orrs r3,r4
+ str r3,[r7,#SIO_DIV_UDIVIDEND_OFFSET] @ y1=(r0<<16)+(((ui32)y)>>16);
+ str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET]  @ must set divisor again, as we do not save/restore regs at all in IRQs if not dirty
+ wait_div 3
+ movs r3,#0
+ lsls r4,r5,#16             @ quotient=(q0<<32)+(q1<<16)+q2
+ lsrs r5,#16
+ ldr r2,[r7,#SIO_DIV_REMAINDER_OFFSET] @ r2=y2-q2*x; 0<=r2<x
+ ldr r0,[r7,#SIO_DIV_QUOTIENT_OFFSET]  @ q2=y2/x;
+ adds r0,r4
+ adcs r1,r5
+ pop {r4,r5,r7}
+ bx r14
+
+.ltorg
+
+y64_x32:
+@ here x is 17..32 bits
+ push {r4-r7,r14}
+ mov r12,r2                @ save x
+ movs r5,#0                @ xsh=0
+ lsrs r4,r2,#24
+ bne 1f
+ lsls r2,#8                @ if(x0<1U<<24) x0<<=8,xsh =8;
+ adds r5,#8
+1:
+ lsrs r4,r2,#28
+ bne 1f
+ lsls r2,#4                @ if(x0<1U<<28) x0<<=4,xsh+=4;
+ adds r5,#4
+1:
+ lsrs r4,r2,#30
+ bne 1f
+ lsls r2,#2                @ if(x0<1U<<30) x0<<=2,xsh+=2;
+ adds r5,#2
+1:
+ lsrs r4,r2,#31
+ bne 1f
+ lsls r2,#1                @ if(x0<1U<<31) x0<<=1,xsh+=1;
+ adds r5,#1
+1:
+@ now 2^31<=x0<2^32, 0<=xsh<16 (amount x is shifted in x0); number of quotient bits to be calculated qb=xsh+33 33<=qb<49
+ lsrs r4,r2,#15
+ adds r4,#1                @ x1=(x0>>15)+1; 2^16<x1<=2^17
+
+ ldr r7,=#SIO_BASE
+ str r4,[r7,#SIO_DIV_UDIVISOR_OFFSET]
+ ldr r4,=#0xffffffff
+ str r4,[r7,#SIO_DIV_UDIVIDEND_OFFSET]
+ lsrs r6,r1,#16
+ uxth r3,r2                @ x0l
+ wait_div 2
+ ldr r4,[r7,#SIO_DIV_QUOTIENT_OFFSET]  @ r=0xffffffffU/x1; 2^15<=r<2^16 r is a normalised reciprocal of x, guaranteed not an overestimate
+
+@ here
+@ r0:r1 y
+@ r2    x0
+@ r4    r
+@ r5    xsh
+@ r12   x
+
+ muls r6,r4
+ lsrs r6,#16               @ q=((ui32)(y>>48)*r)>>16;
+ lsls r7,r6,#13
+ mov r14,r7                @ quh=q0<<13
+
+ muls r3,r6                @ x0l*q
+ lsrs r7,r3,#15
+ lsls r3,#17               @ r3:r7 is (x0l*q)<<17
+ subs r0,r3
+ sbcs r1,r7                @ y-=(x0l*q)<<17
+
+ lsrs r3,r2,#16            @ x0h
+ muls r3,r6                @ q*x0h
+ adds r3,r3
+ subs r1,r3                @ y-=(x0h*q)<<17
+
+ lsrs r6,r1,#3
+ muls r6,r4
+ lsrs r6,#16               @ q=((ui32)(y>>35)*r)>>16;
+ add r14,r6                @ quh+=q1
+
+ uxth r3,r2                @ x0l
+ muls r3,r6                @ x0l*q
+ lsrs r7,r3,#28
+ lsls r3,#4                @ r3:r7 is (x0l*q)<<4
+ subs r0,r3
+ sbcs r1,r7                @ y-=(x0l*q)<<4
+
+ lsrs r3,r2,#16            @ x0h
+ muls r3,r6                @ x0h*q
+ lsrs r7,r3,#12
+ lsls r3,#20               @ r3:r7 is (x0h*q)<<4
+ subs r0,r3
+ sbcs r1,r7                @ y-=(x0h*q)<<4
+
+ lsrs r6,r0,#22
+ lsls r7,r1,#10
+ orrs r6,r7                @ y>>22
+ muls r6,r4
+ lsrs r6,#16               @ q=((ui32)(y>>22)*r)>>16;
+
+ cmp r5,#9
+ blt last0                 @ if(xsh<9) goto last0;
+
+@ on this path xsh>=9, which means x<2^23
+ lsrs r2,#9                @ x0>>9: this shift loses no bits
+@ the remainder y-x0*q is guaranteed less than a very small multiple of the remaining quotient
+@ bits (at most 6 bits) times x, and so fits in one word
+ muls r2,r6                @ x0*q
+ subs r0,r2                @ y-x0*q
+ lsls r7,r6,#13            @ qul=q<<13
+1:
+ lsrs r6,r0,#9
+ muls r6,r4
+ lsrs r6,#16               @ q=((ui32)(y>>9)*r)>>16;
+
+@ here
+@ r0 y
+@ r2 x0>>9
+@ r5 xsh
+@ r6 q
+@ r7 qul
+@ r12 x
+@ r14 quh
+
+ movs r3,#22
+ subs r3,r5                @ 22-xsh
+ lsrs r6,r3                @ q>>=22-xsh
+ lsrs r7,r3                @ qul>>=22-xsh
+ adds r7,r6                @ qul+=q
+ mov r4,r12
+ muls r6,r4                @ x*q
+ subs r2,r0,r6             @ y-=x*q
+ mov r0,r14                @ quh
+ adds r5,#4                @ xsh+4
+ adds r3,#6                @ 28-xsh
+ movs r1,r0
+ lsrs r1,r3
+ lsls r0,r5                @ r0:r1 is quh<<(4+xsh)
+ adds r0,r7
+ bcc 1f
+2:
+ adds r1,#1
+1:                         @ qu=((ui64)quh<<(4+xsh))+qul
+ cmp r2,r4
+ bhs 3f
+ movs r3,#0
+ pop {r4-r7,r15}
+
+.ltorg
+
+3:
+ subs r2,r4
+ adds r0,#1
+ bcc 1b
+ b 2b                      @ while(y>=x) y-=x,qu++;
+
+@ here:
+@ r0:r1 y
+@ r2 x0
+@ r4 r
+@ r5 xsh; xsh<9
+@ r6 q
+
+last0:
+ movs r7,#9
+ subs r7,r5                @ 9-xsh
+ lsrs r6,r7
+ mov r4,r12                @ x
+ uxth r2,r4
+ muls r2,r6                @ q*xlo
+ subs r0,r2
+ bcs 1f
+ subs r1,#1                @ y-=q*xlo
+1:
+ lsrs r2,r4,#16            @ xhi
+ muls r2,r6                @ q*xhi
+ lsrs r3,r2,#16
+ lsls r2,#16
+ subs r2,r0,r2
+ sbcs r1,r3                @ y-q*xhi
+ movs r3,r1                @ y now in r2:r3
+ mov r0,r14                @ quh
+ adds r5,#4                @ xsh+4
+ adds r7,#19               @ 28-xsh
+ movs r1,r0
+ lsrs r1,r7
+ lsls r0,r5                @ r0:r1 is quh<<(4+xsh)
+ adds r0,r6
+ bcc 1f
+ adds r1,#1                @ quh<<(xsh+4))+q
+1:
+ cmp r3,#0                 @ y>=2^32?
+ bne 3f
+ cmp r2,r4                 @ y>=x?
+ bhs 4f
+ pop {r4-r7,r15}
+
+3:
+ adds r0,#1                @ qu++
+ bcc 2f
+ adds r1,#1
+2:
+ subs r2,r4                @ y-=x
+ bcs 3b
+ subs r3,#1
+ bne 3b
+
+1:
+ cmp r2,r4
+ bhs 4f
+ pop {r4-r7,r15}
+
+4:
+ adds r0,#1                @ qu++
+ bcc 2f
+ adds r1,#1
+2:
+ subs r2,r4                @ y-=x
+ b 1b
+
+y64_x48:
+@ here x is 33..64 bits
+ push {r4-r7,r14}          @ save a copy of x
+ lsrs r4,r3,#16
+ beq 1f
+ b y64_x64                 @ jump if x is 49..64 bits
+1:
+ push {r2-r3}              @ save a copy of x
+@ here x is 33..48 bits
+ movs r5,#0                @ xsh=0
+ lsrs r4,r3,#8
+ bne 1f
+ lsls r3,#8
+ lsrs r6,r2,#24
+ orrs r3,r6
+ lsls r2,#8                @ if(x0<1U<<40) x0<<=8,xsh =8;
+ adds r5,#8
+1:
+ lsrs r4,r3,#12
+ bne 1f
+ lsls r3,#4
+ lsrs r6,r2,#28
+ orrs r3,r6
+ lsls r2,#4                @ if(x0<1U<<44) x0<<=4,xsh+=4;
+ adds r5,#4
+1:
+ lsrs r4,r3,#14
+ bne 1f
+ lsls r3,#2
+ lsrs r6,r2,#30
+ orrs r3,r6
+ lsls r2,#2                @ if(x0<1U<<46) x0<<=2,xsh+=2;
+ adds r5,#2
+1:
+ lsrs r4,r3,#15
+ bne 1f
+ adds r2,r2
+ adcs r3,r3                @ if(x0<1U<<47) x0<<=1,xsh+=1;
+ adds r5,#1
+1:
+@ now 2^47<=x0<2^48, 0<=xsh<16 (amount x is shifted in x0); number of quotient bits to be calculated qb=xsh+17 17<=qb<33
+ movs r4,r3
+ adds r7,r2,r2
+ adcs r4,r4
+ adds r4,#1                @ x1=(ui32)(x0>>31)+1; // 2^16<x1<=2^17
+
+ ldr r7,=#SIO_BASE
+ str r4,[r7,#SIO_DIV_UDIVISOR_OFFSET]
+ ldr r4,=#0xffffffff
+ str r4,[r7,#SIO_DIV_UDIVIDEND_OFFSET]
+ lsrs r6,r1,#16
+ wait_div 1
+ ldr r4,[r7,#SIO_DIV_QUOTIENT_OFFSET]  @ r=0xffffffffU/x1; 2^15<=r<2^16 r is a normalised reciprocal of x, guaranteed not an overestimate
+
+@ here
+@ r0:r1 y
+@ r2:r3 x0
+@ r4    r
+@ r5    xsh 0<=xsh<16
+
+ muls r6,r4
+ lsrs r6,#16               @ q=((ui32)(y>>48)*r)>>16;
+ lsls r7,r6,#13
+ mov r14,r7                @ save q<<13
+ uxth r7,r2                @ x0l
+ muls r7,r6
+ subs r0,r7
+ bcs 1f
+ subs r1,#1
+1:
+ subs r0,r7
+ bcs 1f
+ subs r1,#1
+1:
+ uxth r7,r3                @ x0h
+ muls r7,r6
+ subs r1,r7
+ subs r1,r7
+ lsrs r7,r2,#16            @ x0m
+ muls r7,r6
+ lsls r6,r7,#17
+ lsrs r7,#15
+ subs r0,r6
+ sbcs r1,r7                @ y-=((ui64)q*x0)<<1;
+
+ lsrs r6,r1,#3             @ y>>35
+ muls r6,r4
+ lsrs r6,#16               @ q=((ui32)(y>>35)*r)>>16;
+
+ cmp r5,#12
+ blt last1                 @ if(xsh<12) goto last1;
+
+ add r14,r6                @ qu<<13+q
+ lsrs r2,#12
+ lsls r7,r3,#20
+ orrs r2,r7
+ lsrs r3,#12               @ x0>>12
+
+ uxth r7,r2                @ x0l
+ muls r7,r6
+ subs r0,r7
+ bcs 1f
+ subs r1,#1
+1:
+ uxth r7,r3                @ x0h
+ muls r7,r6
+ subs r1,r7
+ lsrs r7,r2,#16            @ x0m
+ muls r7,r6
+ lsls r6,r7,#16
+ lsrs r7,#16
+ subs r0,r6
+ sbcs r1,r7                @ y-=((ui64)q*x0)>>12
+
+ lsrs r6,r0,#22
+ lsls r7,r1,#10
+ orrs r6,r7                @ y>>22
+ muls r6,r4
+ movs r7,#41
+ subs r7,r5
+ lsrs r6,r7                @ q=((ui32)(y>>22)*r)>>(16+25-xsh)
+
+ subs r5,#12
+ mov r7,r14
+ lsls r7,r5
+2:
+ adds r7,r6                @ qu=(qu<<(xsh-12))+q
+ pop {r4,r5}               @ recall x
+
+@ here
+@ r0:r1 y
+@ r4:r5 x
+@ r6 q
+@ r7 qu
+
+ uxth r2,r4
+ uxth r3,r5
+ muls r2,r6                @ xlo*q
+ muls r3,r6                @ xhi*q
+ subs r0,r2
+ sbcs r1,r3
+ lsrs r2,r4,#16
+ muls r2,r6
+ lsrs r3,r2,#16
+ lsls r2,#16               @ xm*q
+ subs r0,r2
+ sbcs r1,r3                @ y-=(ui64)q*x
+
+1:
+ movs r2,r0
+ movs r3,r1
+ adds r7,#1
+ subs r0,r4
+ sbcs r1,r5                @ while(y>=x) y-=x,qu++;
+ bhs 1b
+ subs r0,r7,#1             @ correction to qu
+ movs r1,#0
+ pop {r4-r7,r15}
+
+last1:
+@ r0:r1 y
+@ r2:r3 x0
+@ r5 xsh
+@ r6 q
+
+ movs r7,#12
+ subs r7,r5
+ lsrs r6,r7                @ q>>=12-xsh
+ mov r7,r14
+ lsrs r7,#13
+ lsls r7,r5
+ adds r7,r7                @ qu<<(xsh+1)
+ b 2b
+
+y64_x64:
+@ here x is 49..64 bits
+ movs r4,#0                @ q=0 if x>>32==0xffffffff
+ adds r5,r3,#1
+ beq 1f
+
+ ldr r7,=#SIO_BASE
+ str r5,[r7,#SIO_DIV_UDIVISOR_OFFSET]
+ str r1,[r7,#SIO_DIV_UDIVIDEND_OFFSET]
+ wait_div 0
+ ldr r4,[r7,#SIO_DIV_QUOTIENT_OFFSET] @ q=(ui32)(y>>32)/((x>>32)+1)
+1:
+ uxth r5,r2
+ uxth r6,r3
+ muls r5,r4
+ muls r6,r4
+ subs r0,r5
+ sbcs r1,r6
+ lsrs r5,r2,#16
+ lsrs r6,r3,#16
+ muls r5,r4
+ muls r6,r4
+ lsls r6,#16
+ lsrs r7,r5,#16
+ orrs r6,r7
+ lsls r5,#16
+ subs r0,r5
+ sbcs r1,r6                @   y-=(ui64)q*x
+
+ cmp r1,r3                 @   while(y>=x) y-=x,q++
+ bhs 1f
+3:
+ movs r2,r0
+ movs r3,r1
+ movs r0,r4
+ movs r1,#0
+ pop {r4-r7,r15}
+
+1:
+ bne 2f
+ cmp r0,r2
+ blo 3b
+2:
+ subs r0,r2
+ sbcs r1,r3
+ adds r4,#1
+ cmp r1,r3
+ blo 3b
+ b 1b
+
+div_section divmod_s64s64_rem
+regular_func divmod_s64s64_rem
+    push {r4, lr}
+    bl divmod_s64s64
+    ldr r4, [sp, #8]
+    stmia r4!, {r2,r3}
+    pop {r4, pc}
+
+div_section divmod_u64u64_rem
+regular_func divmod_u64u64_rem
+    push {r4, lr}
+    bl divmod_u64u64
+    ldr r4, [sp, #8]
+    stmia r4!, {r2,r3}
+    pop {r4, pc}
diff --git a/src/rp2_common/pico_double/CMakeLists.txt b/src/rp2_common/pico_double/CMakeLists.txt
new file mode 100644
index 0000000..efe1b63
--- /dev/null
+++ b/src/rp2_common/pico_double/CMakeLists.txt
@@ -0,0 +1,117 @@
+if (NOT TARGET pico_double)
+    # library to be depended on - we make this depend on particular implementations using per target generator expressions
+    pico_add_impl_library(pico_double)
+
+    # no custom implementation; falls thru to compiler
+    pico_add_impl_library(pico_double_compiler)
+
+    add_library(pico_double_headers INTERFACE)
+    target_include_directories(pico_double_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+    # add alias "default" which is just pico.
+    add_library(pico_double_default INTERFACE)
+    target_link_libraries(pico_double_default INTERFACE pico_double_pico)
+
+    set(PICO_DEFAULT_DOUBLE_IMPL pico_double_default)
+
+    target_link_libraries(pico_double INTERFACE
+            $<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_DOUBLE_IMPL>>,$<TARGET_PROPERTY:PICO_TARGET_DOUBLE_IMPL>,${PICO_DEFAULT_DOUBLE_IMPL}>)
+
+    pico_add_impl_library(pico_double_pico)
+    target_sources(pico_double_pico INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/double_aeabi.S
+            ${CMAKE_CURRENT_LIST_DIR}/double_init_rom.c
+            ${CMAKE_CURRENT_LIST_DIR}/double_math.c
+            ${CMAKE_CURRENT_LIST_DIR}/double_v1_rom_shim.S
+    )
+
+    target_link_libraries(pico_double_pico INTERFACE pico_bootrom pico_double_headers)
+
+    pico_add_impl_library(pico_double_none)
+    target_sources(pico_double_none INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/double_none.S
+            )
+
+    target_link_libraries(pico_double_none INTERFACE pico_double_headers)
+
+    target_compile_definitions(pico_double_none INTERFACE
+            PICO_PRINTF_SUPPORT_FLOAT=0 # printing floats/doubles won't work, so we can save space by removing it
+    )
+
+    function(wrap_double_functions TARGET)
+        pico_wrap_function(${TARGET} __aeabi_dadd)
+        pico_wrap_function(${TARGET} __aeabi_ddiv)
+        pico_wrap_function(${TARGET} __aeabi_dmul)
+        pico_wrap_function(${TARGET} __aeabi_drsub)
+        pico_wrap_function(${TARGET} __aeabi_dsub)
+        pico_wrap_function(${TARGET} __aeabi_cdcmpeq)
+        pico_wrap_function(${TARGET} __aeabi_cdrcmple)
+        pico_wrap_function(${TARGET} __aeabi_cdcmple)
+        pico_wrap_function(${TARGET} __aeabi_dcmpeq)
+        pico_wrap_function(${TARGET} __aeabi_dcmplt)
+        pico_wrap_function(${TARGET} __aeabi_dcmple)
+        pico_wrap_function(${TARGET} __aeabi_dcmpge)
+        pico_wrap_function(${TARGET} __aeabi_dcmpgt)
+        pico_wrap_function(${TARGET} __aeabi_dcmpun)
+        pico_wrap_function(${TARGET} __aeabi_i2d)
+        pico_wrap_function(${TARGET} __aeabi_l2d)
+        pico_wrap_function(${TARGET} __aeabi_ui2d)
+        pico_wrap_function(${TARGET} __aeabi_ul2d)
+        pico_wrap_function(${TARGET} __aeabi_d2iz)
+        pico_wrap_function(${TARGET} __aeabi_d2lz)
+        pico_wrap_function(${TARGET} __aeabi_d2uiz)
+        pico_wrap_function(${TARGET} __aeabi_d2ulz)
+        pico_wrap_function(${TARGET} __aeabi_d2f)
+        pico_wrap_function(${TARGET} sqrt)
+        pico_wrap_function(${TARGET} cos)
+        pico_wrap_function(${TARGET} sin)
+        pico_wrap_function(${TARGET} tan)
+        pico_wrap_function(${TARGET} atan2)
+        pico_wrap_function(${TARGET} exp)
+        pico_wrap_function(${TARGET} log)
+
+        pico_wrap_function(${TARGET} ldexp)
+        pico_wrap_function(${TARGET} copysign)
+        pico_wrap_function(${TARGET} trunc)
+        pico_wrap_function(${TARGET} floor)
+        pico_wrap_function(${TARGET} ceil)
+        pico_wrap_function(${TARGET} round)
+        pico_wrap_function(${TARGET} sincos) # gnu
+        pico_wrap_function(${TARGET} asin)
+        pico_wrap_function(${TARGET} acos)
+        pico_wrap_function(${TARGET} atan)
+        pico_wrap_function(${TARGET} sinh)
+        pico_wrap_function(${TARGET} cosh)
+        pico_wrap_function(${TARGET} tanh)
+        pico_wrap_function(${TARGET} asinh)
+        pico_wrap_function(${TARGET} acosh)
+        pico_wrap_function(${TARGET} atanh)
+        pico_wrap_function(${TARGET} exp2)
+        pico_wrap_function(${TARGET} log2)
+        pico_wrap_function(${TARGET} exp10)
+        pico_wrap_function(${TARGET} log10)
+        pico_wrap_function(${TARGET} pow)
+        pico_wrap_function(${TARGET} powint) #gnu
+        pico_wrap_function(${TARGET} hypot)
+        pico_wrap_function(${TARGET} cbrt)
+        pico_wrap_function(${TARGET} fmod)
+        pico_wrap_function(${TARGET} drem)
+        pico_wrap_function(${TARGET} remainder)
+        pico_wrap_function(${TARGET} remquo)
+        pico_wrap_function(${TARGET} expm1)
+        pico_wrap_function(${TARGET} log1p)
+        pico_wrap_function(${TARGET} fma)
+    endfunction()
+
+    wrap_double_functions(pico_double_pico)
+    wrap_double_functions(pico_double_none)
+
+    macro(pico_set_double_implementation TARGET IMPL)
+        get_target_property(target_type ${TARGET} TYPE)
+        if ("EXECUTABLE" STREQUAL "${target_type}")
+            set_target_properties(${TARGET} PROPERTIES PICO_TARGET_DOUBLE_IMPL "pico_double_${IMPL}")
+        else()
+            message(FATAL_ERROR "double implementation must be set on executable not library")
+        endif()
+    endmacro()
+endif()
diff --git a/src/rp2_common/pico_double/double_aeabi.S b/src/rp2_common/pico_double/double_aeabi.S
new file mode 100644
index 0000000..0c59738
--- /dev/null
+++ b/src/rp2_common/pico_double/double_aeabi.S
@@ -0,0 +1,849 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/asm_helper.S"
+#include "pico/bootrom/sf_table.h"
+#include "hardware/divider_helper.S"
+
+__pre_init __aeabi_double_init, 00020
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.macro double_section name
+#if PICO_DOUBLE_IN_RAM
+.section RAM_SECTION_NAME(\name), "ax"
+#else
+.section SECTION_NAME(\name), "ax"
+#endif
+.endm
+
+.macro _double_wrapper_func x
+    wrapper_func \x
+.endm
+
+.macro wrapper_func_d1 x
+   _double_wrapper_func \x
+#if PICO_DOUBLE_PROPAGATE_NANS
+    mov ip, lr
+    bl __check_nan_d1
+    mov lr, ip
+#endif
+.endm
+
+.macro wrapper_func_d2 x
+    _double_wrapper_func \x
+#if PICO_DOUBLE_PROPAGATE_NANS
+    mov ip, lr
+    bl __check_nan_d2
+    mov lr, ip
+#endif
+.endm
+
+.section .text
+
+#if PICO_DOUBLE_PROPAGATE_NANS
+.thumb_func
+__check_nan_d1:
+   movs r3, #1
+   lsls r3, #21
+   lsls r2, r1, #1
+   adds r2, r3
+   bhi 1f
+   bx lr
+1:
+   bx ip
+
+.thumb_func
+__check_nan_d2:
+   push {r0, r2}
+   movs r2, #1
+   lsls r2, #21
+   lsls r0, r1, #1
+   adds r0, r2
+   bhi 1f
+   lsls r0, r3, #1
+   adds r0, r2
+   bhi 2f
+   pop {r0, r2}
+   bx lr
+2:
+   pop {r0, r2}
+   mov r0, r2
+   mov r1, r3
+   bx ip
+1:
+   pop {r0, r2}
+   bx ip
+#endif
+
+.macro table_tail_call SF_TABLE_OFFSET
+    push {r3, r4}
+#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
+#ifndef NDEBUG
+    movs r3, #0
+    mov ip, r3
+#endif
+#endif
+    ldr r3, =sd_table
+    ldr r3, [r3, #\SF_TABLE_OFFSET]
+    str r3, [sp, #4]
+    pop {r3, pc}
+.endm
+
+.macro shimmable_table_tail_call SF_TABLE_OFFSET shim
+    push {r3, r4}
+    ldr r3, =sd_table
+    ldr r3, [r3, #\SF_TABLE_OFFSET]
+#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
+    mov ip, pc
+#endif
+    str r3, [sp, #4]
+    pop {r3, pc}
+#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
+.byte \SF_TABLE_OFFSET, 0xdf
+.word \shim
+#endif
+.endm
+
+.macro double_wrapper_section func
+double_section WRAPPER_FUNC_NAME(\func)
+.endm
+
+double_section push_r8_r11
+regular_func push_r8_r11
+ mov r4,r8
+ mov r5,r9
+ mov r6,r10
+ mov r7,r11
+ push {r4-r7}
+ bx r14
+
+double_section pop_r8_r11
+regular_func pop_r8_r11
+ pop {r4-r7}
+ mov r8,r4
+ mov r9,r5
+ mov r10,r6
+ mov r11,r7
+ bx r14
+
+// note generally each function is in a separate section unless there is fall thru or branching between them
+// note fadd, fsub, fmul, fdiv are so tiny and just defer to rom so are lumped together so they can share constant pool
+
+// note functions are word aligned except where they are an odd number of linear instructions
+
+// double FUNC_NAME(__aeabi_dadd)(double, double)         double-precision addition
+double_wrapper_section __aeabi_darithmetic
+// double FUNC_NAME(__aeabi_drsub)(double x, double y)    double-precision reverse subtraction, y - x
+
+// frsub first because it is the only one that needs alignment
+.align 2
+wrapper_func __aeabi_drsub
+    eors r0, r1
+    eors r1, r0
+    eors r0, r1
+    // fall thru
+
+// double FUNC_NAME(__aeabi_dsub)(double x, double y)     double-precision subtraction, x - y
+wrapper_func_d2 __aeabi_dsub
+#if PICO_DOUBLE_PROPAGATE_NANS
+    // we want to return nan for inf-inf or -inf - -inf, but without too much upfront cost
+    mov ip, r0
+    mov r0, r1
+    eors r0, r3
+    bmi 1f // different signs
+    mov r0, ip
+    push {r0-r3, lr}
+    bl 2f
+    b ddiv_dsub_nan_helper
+1:
+    mov r0, ip
+2:
+#endif
+   shimmable_table_tail_call SF_TABLE_FSUB dsub_shim
+
+wrapper_func_d2 __aeabi_dadd
+   shimmable_table_tail_call SF_TABLE_FADD dadd_shim
+
+// double FUNC_NAME(__aeabi_ddiv)(double n, double d)     double-precision division, n / d
+wrapper_func_d2 __aeabi_ddiv
+#if PICO_DOUBLE_PROPAGATE_NANS
+    push {r0-r3, lr}
+    bl 1f
+    b ddiv_dsub_nan_helper
+1:
+#endif
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+    // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
+    mov ip, r2
+    ldr r2, =(SIO_BASE)
+    ldr r2, [r2, #SIO_DIV_CSR_OFFSET]
+    lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
+    bcs ddiv_save_state
+    mov r2, ip
+#else
+    // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+    push {r4, lr}
+    mrs r4, PRIMASK
+    cpsid i
+    bl ddiv_shim_call
+    msr PRIMASK, r4
+    pop {r4, pc}
+#endif
+ddiv_shim_call:
+    shimmable_table_tail_call SF_TABLE_FDIV ddiv_shim
+
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+ddiv_save_state:
+    ldr r2, =(SIO_BASE)
+    save_div_state_and_lr
+    mov r2, ip
+    bl ddiv_shim_call
+    ldr r2, =(SIO_BASE)
+    restore_div_state_and_return
+#endif
+
+ddiv_dsub_nan_helper:
+#if PICO_DOUBLE_PROPAGATE_NANS
+    // check for infinite op infinite (or rather check for infinite result with both
+    // operands being infinite)
+    lsls r2, r1, #1
+    asrs r2, r2, #21
+    adds r2, #1
+    beq 2f
+    add sp, #16
+    pop {pc}
+2:
+    ldr r2, [sp, #4]
+    ldr r3, [sp, #12]
+    lsls r2, #1
+    asrs r2, r2, #21
+    lsls r3, #1
+    asrs r3, r3, #24
+    ands r2, r3
+    adds r2, #1
+    bne 3f
+    // infinite to nan
+    movs r2, #1
+    lsls r2, #19
+    orrs r1, r2
+3:
+    add sp, #16
+    pop {pc}
+#endif
+
+// double FUNC_NAME(__aeabi_dmul)(double, double)         double-precision multiplication
+wrapper_func_d2 __aeabi_dmul
+#if PICO_DOUBLE_PROPAGATE_NANS
+    push {r0-r3, lr}
+    bl 1f
+
+    // check for multiplication of infinite by zero (or rather check for infinite result with either
+    // operand 0)
+    lsls r3, r1, #1
+    asrs r3, r3, #21
+    adds r3, #1
+    beq 2f
+    add sp, #16
+    pop {pc}
+2:
+    ldr r2, [sp, #4]
+    ldr r3, [sp, #12]
+    ands r2, r3
+    bne 3f
+    // infinite to nan
+    movs r2, #1
+    lsls r2, #19
+    orrs r1, r2
+3:
+    add sp, #16
+    pop {pc}
+1:
+#endif
+   shimmable_table_tail_call SF_TABLE_FMUL dmul_shim
+
+// void FUNC_NAME(__aeabi_cdrcmple)(double, double)         reversed 3-way (<, =, ?>) compare [1], result in PSR ZC flags
+double_wrapper_section __aeabi_cdcmple
+
+wrapper_func __aeabi_cdrcmple
+ push {r0-r7,r14}
+    eors r0, r2
+    eors r2, r0
+    eors r0, r2
+    eors r1, r3
+    eors r3, r1
+    eors r1, r3
+    b __aeabi_dfcmple_guts
+
+// NOTE these share an implementation as we have no excepting NaNs.
+// void FUNC_NAME(__aeabi_cdcmple)(double, double)         3-way (<, =, ?>) compare [1], result in PSR ZC flags
+// void FUNC_NAME(__aeabi_cdcmpeq)(double, double)         non-excepting equality comparison [1], result in PSR ZC flags
+@ compare r0:r1 against r2:r3, returning -1/0/1 for <, =, >
+@ also set flags accordingly
+.align 2
+wrapper_func __aeabi_cdcmple
+wrapper_func __aeabi_cdcmpeq
+ push {r0-r7,r14}
+__aeabi_dfcmple_guts:
+ ldr r7,=#0x7ff                @ flush NaNs and denormals
+ lsls r4,r1,#1
+ lsrs r4,#21
+ beq 1f
+ cmp r4,r7
+ bne 2f
+ lsls r4, r1, #12
+ bhi 7f
+1:
+ movs r0,#0
+ lsrs r1,#20
+ lsls r1,#20
+2:
+ lsls r4,r3,#1
+ lsrs r4,#21
+ beq 1f
+ cmp r4,r7
+ bne 2f
+ lsls r4, r3, #12
+ bhi 7f
+1:
+ movs r2,#0
+ lsrs r3,#20
+ lsls r3,#20
+2:
+ movs r6,#1
+ eors r3,r1
+ bmi 4f                        @ opposite signs? then can proceed on basis of sign of x
+ eors r3,r1                    @ restore r3
+ bpl 2f
+ cmp r3,r1
+ bne 7f
+1:
+ cmp r2,r0
+7:
+ pop {r0-r7,r15}
+2:
+ cmp r1,r3
+ bne 7b
+1:
+ cmp r0,r2
+ pop {r0-r7,r15}
+4:
+ orrs r3,r1                    @ make -0==+0
+ adds r3,r3
+ orrs r3,r0
+ orrs r3,r2
+ beq 7b
+ mvns r1, r1     @ carry inverse of r1 sign
+ adds r1, r1
+ pop {r0-r7,r15}
+
+
+// int FUNC_NAME(__aeabi_dcmpeq)(double, double)         result (1, 0) denotes (=, ?<>) [2], use for C == and !=
+double_wrapper_section __aeabi_dcmpeq
+.align 2
+wrapper_func __aeabi_dcmpeq
+    push {lr}
+    bl __aeabi_cdcmpeq
+    beq 1f
+    movs r0, #0
+    pop {pc}
+1:
+    movs r0, #1
+    pop {pc}
+
+// int FUNC_NAME(__aeabi_dcmplt)(double, double)         result (1, 0) denotes (<, ?>=) [2], use for C <
+double_wrapper_section __aeabi_dcmplt
+.align 2
+wrapper_func __aeabi_dcmplt
+    push {lr}
+    bl __aeabi_cdcmple
+    sbcs r0, r0
+    pop {pc}
+
+// int FUNC_NAME(__aeabi_dcmple)(double, double)         result (1, 0) denotes (<=, ?>) [2], use for C <=
+double_wrapper_section __aeabi_dcmple
+.align 2
+wrapper_func __aeabi_dcmple
+    push {lr}
+    bl __aeabi_cdcmple
+    bls 1f
+    movs r0, #0
+    pop {pc}
+1:
+    movs r0, #1
+    pop {pc}
+
+// int FUNC_NAME(__aeabi_dcmpge)(double, double)         result (1, 0) denotes (>=, ?<) [2], use for C >=
+double_wrapper_section __aeabi_dcmpge
+.align 2
+wrapper_func __aeabi_dcmpge
+    push {lr}
+    // because of NaNs it is better to reverse the args than the result
+    bl __aeabi_cdrcmple
+    bls 1f
+    movs r0, #0
+    pop {pc}
+1:
+    movs r0, #1
+    pop {pc}
+
+// int FUNC_NAME(__aeabi_dcmpgt)(double, double)         result (1, 0) denotes (>, ?<=) [2], use for C >
+double_wrapper_section __aeabi_dcmpgt
+wrapper_func __aeabi_dcmpgt
+    push {lr}
+    // because of NaNs it is better to reverse the args than the result
+    bl __aeabi_cdrcmple
+    sbcs r0, r0
+    pop {pc}
+
+// int FUNC_NAME(__aeabi_dcmpun)(double, double)         result (1, 0) denotes (?, <=>) [2], use for C99 isunordered()
+double_wrapper_section __aeabi_dcmpun
+wrapper_func __aeabi_dcmpun
+   movs r0, #1
+   lsls r0, #21
+   lsls r2, r1, #1
+   adds r2, r0
+   bhi 1f
+   lsls r2, r3, #1
+   adds r2, r0
+   bhi 1f
+   movs r0, #0
+   bx lr
+1:
+   movs r0, #1
+   bx lr
+
+    movs r0, #0
+    bx lr
+
+// double FUNC_NAME(__aeabi_ui2d)(unsigned)             unsigned to double (double precision) conversion
+double_wrapper_section __aeabi_ui2d
+    shimmable_table_tail_call SF_TABLE_UINT2FLOAT uint2double_shim
+
+double_wrapper_section __aeabi_i2d
+
+wrapper_func __aeabi_ui2d
+    movs r1, #0
+    cmp r0, #0
+    bne 2f
+1:
+    bx lr
+// double FUNC_NAME(__aeabi_i2d)(int)                     integer to double (double precision) conversion
+wrapper_func __aeabi_i2d
+    asrs r1, r0, #31
+    eors r0, r1
+    subs r0, r1
+    beq 1b
+    lsls r1, #31
+2:
+    push {r0, r1, r4, lr}
+    ldr r3, =sf_clz_func
+    ldr r3, [r3]
+    blx r3
+    pop {r2, r3}
+    adds r4, r0, #1
+    lsls r2, r4
+    lsls r0, r2, #20
+    lsrs r2, #12
+    ldr r1,=#1055
+    subs r1, r4
+    lsls r1, #20
+    orrs r1, r3
+    orrs r1, r2
+    pop {r4, pc}
+
+// int FUNC_NAME(__aeabi_d2iz)(double)                     double (double precision) to integer C-style conversion [3]
+double_wrapper_section __aeabi_d2iz
+wrapper_func __aeabi_d2iz
+regular_func double2int_z
+    push {r4, lr}
+    lsls r4, r1, #1
+    lsrs r2, r4, #21
+    movs r3, #0x80
+    adds r2, r3
+    lsls r3, #3
+    subs r2, r3
+    lsls r3, #21
+    cmp r2, #126
+    ble 1f
+    subs r2, #158
+    bge 2f
+    asrs r4, r1, #31
+    lsls r1, #12
+    lsrs r1, #1
+    orrs r1, r3
+    negs r2, r2
+    lsrs r1, r2
+    lsls r4, #1
+    adds r4, #1
+    adds r2, #21
+    cmp r2, #32
+    bge 3f
+    lsrs r0, r2
+    orrs r0, r1
+    muls r0, r4
+    pop {r4, pc}
+1:
+    movs r0, #0
+    pop {r4, pc}
+3:
+    mov r0, r1
+    muls r0, r4
+    pop {r4, pc}
+2:
+    // overflow
+    lsrs r0, r1, #31
+    adds r0, r3
+    subs r0, #1
+    pop {r4, pc}
+
+double_section double2int
+regular_func double2int
+    shimmable_table_tail_call SF_TABLE_FLOAT2INT double2int_shim
+
+// unsigned FUNC_NAME(__aeabi_d2uiz)(double)             double (double precision) to unsigned C-style conversion [3]
+double_wrapper_section __aeabi_d2uiz
+wrapper_func __aeabi_d2uiz
+regular_func double2uint
+    shimmable_table_tail_call SF_TABLE_FLOAT2UINT double2uint_shim
+
+double_section fix2double
+regular_func fix2double
+    shimmable_table_tail_call SF_TABLE_FIX2FLOAT fix2double_shim
+
+double_section ufix2double
+regular_func ufix2double
+    shimmable_table_tail_call SF_TABLE_UFIX2FLOAT ufix2double_shim
+
+double_section fix642double
+regular_func fix642double
+    shimmable_table_tail_call SF_TABLE_FIX642FLOAT fix642double_shim
+
+double_section ufix2double
+regular_func ufix642double
+    shimmable_table_tail_call SF_TABLE_UFIX642FLOAT ufix642double_shim
+
+// double FUNC_NAME(__aeabi_l2d)(long long)             long long to double (double precision) conversion
+double_wrapper_section __aeabi_l2d
+wrapper_func __aeabi_l2d
+    shimmable_table_tail_call SF_TABLE_INT642FLOAT int642double_shim
+
+// double FUNC_NAME(__aeabi_l2f)(long long)             long long to double (double precision) conversion
+double_wrapper_section __aeabi_ul2d
+wrapper_func __aeabi_ul2d
+    shimmable_table_tail_call SF_TABLE_UINT642FLOAT uint642double_shim
+
+// long long FUNC_NAME(__aeabi_d2lz)(double)             double (double precision) to long long C-style conversion [3]
+double_wrapper_section __aeabi_d2lz
+wrapper_func __aeabi_d2lz
+regular_func double2int64_z
+    cmn r1, r1
+    bcc double2int64
+    push {lr}
+    lsls r1, #1
+    lsrs r1, #1
+    movs r2, #0
+    bl double2ufix64
+    cmp r1, #0
+    bmi 1f
+    movs r2, #0
+    rsbs r0, #0
+    sbcs r2, r1
+    mov r1, r2
+    pop {pc}
+1:
+    movs r1, #128
+    lsls r1, #24
+    movs r0, #0
+    pop {pc}
+
+double_section double2int64
+regular_func double2int64
+    shimmable_table_tail_call SF_TABLE_FLOAT2INT64 double2int64_shim
+
+// unsigned long long FUNC_NAME(__aeabi_d2ulz)(double)     double to unsigned long long C-style conversion [3]
+double_wrapper_section __aeabi_d2ulz
+wrapper_func __aeabi_d2ulz
+    shimmable_table_tail_call SF_TABLE_FLOAT2UINT64 double2uint64_shim
+
+double_section double2fix64
+regular_func double2fix64
+    shimmable_table_tail_call SF_TABLE_FLOAT2FIX64 double2fix64_shim
+
+double_section double2ufix64
+regular_func double2ufix64
+    shimmable_table_tail_call SF_TABLE_FLOAT2UFIX64 double2ufix64_shim
+
+double_section double2fix
+regular_func double2fix
+    shimmable_table_tail_call SF_TABLE_FLOAT2FIX double2fix_shim
+
+double_section double2ufix
+regular_func double2ufix
+    shimmable_table_tail_call SF_TABLE_FLOAT2UFIX double2ufix_shim
+
+double_wrapper_section __aeabi_d2f
+1:
+#if PICO_DOUBLE_PROPAGATE_NANS
+    // copy sign bit and 23 NAN id bits into sign bit and significant id bits, also set high id bit
+
+    lsrs r0, #30
+    lsls r2, r1, #12
+    lsrs r2, #9
+    asrs r1, #22
+    lsls r1, #22
+    orrs r0, r1
+    orrs r0, r2
+    bx lr
+#endif
+wrapper_func __aeabi_d2f
+#if PICO_DOUBLE_PROPAGATE_NANS
+    movs r3, #1
+    lsls r3, #21
+    lsls r2, r1, #1
+    adds r2, r3
+    bhi 1b
+#endif
+    // note double->float in double table at same index as float->double in double table
+    shimmable_table_tail_call SF_TABLE_FLOAT2DOUBLE double2float_shim
+
+double_wrapper_section srqt
+wrapper_func_d1 sqrt
+    shimmable_table_tail_call SF_TABLE_FSQRT dsqrt_shim
+
+double_wrapper_section sincostan_remainder
+regular_func sincostan_remainder
+    ldr r2, =0x54442D18 // 2 * M_PI
+    ldr r3, =0x401921FB
+    push {lr}
+    // note remainder only uses the divider thru integer divider functions
+    // which save and restore themselves
+    bl remainder
+    pop {pc}
+
+double_wrapper_section cos
+#don't use _d1 as we're doing a range check anyway and infinites/nans are bigger than 1024
+wrapper_func cos
+    // rom version only works for -1024 < angle < 1024
+    lsls r2, r1, #2
+    bcc 1f
+    lsrs r2, #22
+    cmp r2, #9
+    bge 2f
+1:
+    shimmable_table_tail_call SF_TABLE_FCOS dcos_shim
+2:
+#if PICO_DOUBLE_PROPAGATE_NANS
+    lsls r2, r1, #1
+    asrs r2, #21
+    adds r2, #1
+    bne 3f
+    // infinite to nan
+    movs r2, #1
+    lsls r2, #19
+    orrs r1, r2
+    bx lr
+3:
+#endif
+    push {lr}
+    bl sincostan_remainder
+    pop {r2}
+    mov lr, r2
+    b 1b
+
+double_wrapper_section sin
+#don't use _d1 as we're doing a range check anyway and infinites/nans are bigger than 1024
+wrapper_func sin
+    // rom version only works for -1024 < angle < 1024
+    lsls r2, r1, #2
+    bcc 1f
+    lsrs r2, #22
+    cmp r2, #9
+    bge 2f
+1:
+    shimmable_table_tail_call SF_TABLE_FSIN dsin_shim
+2:
+#if PICO_DOUBLE_PROPAGATE_NANS
+    lsls r2, r1, #1
+    asrs r2, #21
+    adds r2, #1
+    bne 3f
+    // infinite to nan
+    movs r2, #1
+    lsls r2, #19
+    orrs r1, r2
+    bx lr
+3:
+#endif
+    push {lr}
+    bl sincostan_remainder
+    pop {r2}
+    mov lr, r2
+    b 1b
+
+double_wrapper_section sincos
+    // out of line remainder code for abs(angle)>=1024
+2:
+#if PICO_DOUBLE_PROPAGATE_NANS
+    lsls r2, r1, #1
+    asrs r2, #21
+    adds r2, #1
+    bne 3f
+    // infinite to nan
+    movs r2, #1
+    lsls r2, #19
+    orrs r1, r2
+    pop {r4-r5}
+    stmia r4!, {r0, r1}
+    stmia r5!, {r0, r1}
+    pop {r4, r5, pc}
+3:
+#endif
+    push {lr}
+    bl sincostan_remainder
+    pop {r2}
+    mov lr, r2
+    b 1f // continue with sincos
+
+wrapper_func sincos
+    push {r2-r5, lr}
+    // rom version only works for -1024 < angle < 1024
+    lsls r2, r1, #2
+    bcc 1f
+    lsrs r2, #22
+    cmp r2, #9
+    bge 2b
+1:
+    bl 2f // call the shim
+    pop {r4-r5}
+    stmia r4!, {r0, r1}
+    stmia r5!, {r2, r3}
+    pop {r4, r5, pc}
+
+2:
+    shimmable_table_tail_call SF_TABLE_V3_FSINCOS sincos_shim_bootstrap
+
+.thumb_func
+sincos_shim_bootstrap:
+    push {r2, r3, r4}
+    movs r3, #0x13
+    ldrb r3, [r3]
+#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
+    cmp r3, #1
+    bne 1f
+    ldr r3, =dsincos_shim
+    b 2f
+#endif
+1:
+    ldr r3, =dsincos_shim_v2
+2:
+    ldr r2, =sd_table
+    str r3, [r2, #SF_TABLE_V3_FSINCOS]
+    str r3, [sp, #8]
+    pop {r2, r3, pc}
+.thumb_func
+dsincos_shim_v2:
+     push {r4-r7,r14}
+     bl push_r8_r11
+     bl v2_rom_dsincos_internal
+     mov r12,r0                    @ save ε
+     bl v2_rom_dcos_finish
+     push {r0,r1}
+     mov r0,r12
+     bl v2_rom_dsin_finish
+     pop {r2,r3}
+     bl pop_r8_r11
+     pop {r4-r7,r15}
+.thumb_func
+v2_rom_dsincos_internal:
+    push {r0, lr}
+    ldr r0, =0x3855
+    str r0, [sp, #4]
+    pop {r0, pc}
+.thumb_func
+v2_rom_dcos_finish:
+    push {r0, r1}
+    ldr r0, =0x389d
+    str r0, [sp, #4]
+    pop {r0, pc}
+.thumb_func
+v2_rom_dsin_finish:
+    push {r0, r1}
+    ldr r0, =0x38d9
+    str r0, [sp, #4]
+    pop {r0, pc}
+
+double_wrapper_section tan
+#don't use _d1 as we're doing a range check anyway and infinites/nans are bigger than 1024
+wrapper_func tan
+    // rom version only works for -1024 < angle < 1024
+    lsls r2, r1, #2
+    bcc dtan_in_range
+    lsrs r2, #22
+    cmp r2, #9
+    bge dtan_angle_out_of_range
+dtan_in_range:
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+    // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
+    mov ip, r2
+    ldr r2, =(SIO_BASE)
+    ldr r2, [r2, #SIO_DIV_CSR_OFFSET]
+    lsrs r2, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
+    bcs dtan_save_state
+    mov r2, ip
+#else
+    // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+    push {r4, lr}
+    mrs r4, PRIMASK
+    cpsid i
+    bl dtan_shim_call
+    msr PRIMASK, r4
+    pop {r4, pc}
+#endif
+dtan_shim_call:
+    shimmable_table_tail_call SF_TABLE_FTAN dtan_shim
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+dtan_save_state:
+    ldr r2, =(SIO_BASE)
+    save_div_state_and_lr
+    mov r2, ip
+    bl dtan_shim_call
+    ldr r2, =(SIO_BASE)
+    restore_div_state_and_return
+#endif
+dtan_angle_out_of_range:
+#if PICO_DOUBLE_PROPAGATE_NANS
+    lsls r2, r1, #1
+    asrs r2, #21
+    adds r2, #1
+    bne 3f
+    // infinite to nan
+    movs r2, #1
+    lsls r2, #19
+    orrs r1, r2
+    bx lr
+3:
+#endif
+    push {lr}
+    bl sincostan_remainder
+    pop {r2}
+    mov lr, r2
+    b dtan_in_range
+
+double_wrapper_section atan2
+wrapper_func_d2 atan2
+    shimmable_table_tail_call SF_TABLE_FATAN2 datan2_shim
+
+double_wrapper_section exp
+wrapper_func_d1 exp
+    shimmable_table_tail_call SF_TABLE_FEXP dexp_shim
+
+double_wrapper_section log
+wrapper_func_d1 log
+    shimmable_table_tail_call SF_TABLE_FLN dln_shim
+
diff --git a/src/rp2_common/pico_double/double_init_rom.c b/src/rp2_common/pico_double/double_init_rom.c
new file mode 100644
index 0000000..af6f6a2
--- /dev/null
+++ b/src/rp2_common/pico_double/double_init_rom.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+#include "pico/bootrom.h"
+#include "pico/bootrom/sf_table.h"
+
+// NOTE THIS FUNCTION TABLE IS NOT PUBLIC OR NECESSARILY COMPLETE...
+// IT IS ***NOT*** SAFE TO CALL THESE FUNCTION POINTERS FROM ARBITRARY CODE
+uint32_t sd_table[SF_TABLE_V2_SIZE / 2];
+
+#if !(PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED)
+static __attribute__((noreturn)) void missing_double_func_shim(void) {
+    panic("missing double function");
+}
+#endif
+extern void double_table_shim_on_use_helper(void);
+
+void __attribute__((weak)) *sf_clz_func;
+
+void __aeabi_double_init(void) {
+    int rom_version = rp2040_rom_version();
+#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
+    if (rom_version == 1) {
+
+        // this is a little tricky.. we only want to pull in a shim if the corresponding function
+        // is called. to that end we include a SVC instruction with the table offset as the call number
+        // followed by the shim function pointer inside the actual wrapper function. that way if the wrapper
+        // function is garbage collected, so is the shim function.
+        //
+        // double_table_shim_on_use_helper expects this SVC instruction in the calling code soon after the address
+        // pointed to by IP and patches the double_table entry with the real shim the first time the function is called.
+        for(uint i=0; i<SF_TABLE_V2_SIZE/4; i++) {
+            sd_table[i] = (uintptr_t)double_table_shim_on_use_helper;
+        }
+    }
+#else
+    if (rom_version == 1) {
+        // opting for soft failure for now - you'll get a panic at runtime if you call any of the missing methods
+        for(uint i=0;i<SF_TABLE_V2_SIZE/4;i++) {
+            sd_table[i] = (uintptr_t)missing_double_func_shim;
+        }
+    }
+#endif
+    if (rom_version >= 2) {
+        void *rom_table = rom_data_lookup(rom_table_code('S', 'D'));
+        assert(*((uint8_t *)(((void *)rom_data_lookup(rom_table_code('S', 'F')))-2)) * 4 >= SF_TABLE_V2_SIZE);
+        memcpy(&sd_table, rom_table, SF_TABLE_V2_SIZE);
+        if (rom_version == 2) {
+#ifndef NDEBUG
+            if (*(uint16_t *)0x3854 != 0xb500 || // this is dsincos(_internal)
+
+                *(uint16_t *)0x38d8 != 0x4649 || // this is dsin_finish
+                *(uint16_t *)0x389c != 0x4659  // this is dcos_finish
+                    ) {
+                panic(NULL);
+            }
+#endif
+        }
+    }
+    if (rom_version < 3) {
+        // we use the unused entry for SINCOS
+        sd_table[SF_TABLE_V3_FSINCOS / 4] = (uintptr_t) double_table_shim_on_use_helper;
+    }
+
+    sf_clz_func = rom_func_lookup(ROM_FUNC_CLZ32);
+}
diff --git a/src/rp2_common/pico_double/double_math.c b/src/rp2_common/pico_double/double_math.c
new file mode 100644
index 0000000..6c35ded
--- /dev/null
+++ b/src/rp2_common/pico_double/double_math.c
@@ -0,0 +1,626 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <math.h>
+#include "pico/types.h"
+#include "pico/double.h"
+#include "pico/platform.h"
+
+// opened a separate issue https://github.com/raspberrypi/pico-sdk/issues/166 to deal with these warnings if at all
+_Pragma("GCC diagnostic push")
+_Pragma("GCC diagnostic ignored \"-Wconversion\"")
+_Pragma("GCC diagnostic ignored \"-Wsign-conversion\"")
+
+typedef uint64_t ui64;
+typedef uint32_t ui32;
+typedef int64_t i64;
+
+#define PINF ( HUGE_VAL)
+#define MINF (-HUGE_VAL)
+#define PZERO (+0.0)
+#define MZERO (-0.0)
+
+
+#define PI       3.14159265358979323846
+#define LOG2     0.69314718055994530941
+// Unfortunately in double precision ln(10) is very close to half-way between to representable numbers
+#define LOG10    2.30258509299404568401
+#define LOG2E    1.44269504088896340737
+#define LOG10E   0.43429448190325182765
+#define ONETHIRD 0.33333333333333333333
+
+#define PIf       3.14159265358979323846f
+#define LOG2f     0.69314718055994530941f
+#define LOG2Ef    1.44269504088896340737f
+#define LOG10Ef   0.43429448190325182765f
+#define ONETHIRDf 0.33333333333333333333f
+
+#define DUNPACK(x,e,m) e=((x)>>52)&0x7ff,m=((x)&0x000fffffffffffffULL)|0x0010000000000000ULL
+#define DUNPACKS(x,s,e,m) s=((x)>>63),DUNPACK((x),(e),(m))
+
+typedef union {
+    double d;
+    ui64 ix;
+} double_ui64;
+
+static inline double ui642double(ui64 ix) {
+    double_ui64 tmp;
+    tmp.ix = ix;
+    return tmp.d;
+}
+
+static inline ui64 double2ui64(double d) {
+    double_ui64 tmp;
+    tmp.d = d;
+    return tmp.ix;
+}
+
+static inline bool disnan(double x) {
+    ui64 ix= double2ui64(x);
+    // checks the top bit of the low 32 bit of the NAN, but it I think that is ok
+    return ((uint32_t)(ix >> 31)) > 0xffe00000u;
+}
+
+#if PICO_DOUBLE_PROPAGATE_NANS
+#define check_nan_d1(x) if (disnan((x))) return (x)
+#define check_nan_d2(x,y) if (disnan((x))) return (x); else if (disnan((y))) return (y);
+#else
+#define check_nan_d1(x) ((void)0)
+#define check_nan_d2(x,y) ((void)0)
+#endif
+
+static inline int dgetsignexp(double x) {
+    ui64 ix=double2ui64(x);
+    return (ix>>52)&0xfff;
+}
+
+static inline int dgetexp(double x) {
+    ui64 ix=double2ui64(x);
+    return (ix>>52)&0x7ff;
+}
+
+static inline double dldexp(double x,int de) {
+    ui64 ix=double2ui64(x),iy;
+    int e;
+    e=dgetexp(x);
+    if(e==0||e==0x7ff) return x;
+    e+=de;
+    if(e<=0) iy=ix&0x8000000000000000ULL; // signed zero for underflow
+    else if(e>=0x7ff) iy=(ix&0x8000000000000000ULL)|0x7ff0000000000000ULL; // signed infinity on overflow
+    else iy=ix+((ui64)de<<52);
+    return ui642double(iy);
+}
+
+double WRAPPER_FUNC(ldexp)(double x, int de) {
+    check_nan_d1(x);
+    return dldexp(x, de);
+}
+
+
+static inline double dcopysign(double x,double y) {
+    ui64 ix=double2ui64(x),iy=double2ui64(y);
+    ix=((ix&0x7fffffffffffffffULL)|(iy&0x8000000000000000ULL));
+    return ui642double(ix);
+}
+
+double WRAPPER_FUNC(copysign)(double x, double y) {
+    check_nan_d2(x,y);
+    return dcopysign(x, y);
+}
+static inline int diszero(double x)  { return dgetexp    (x)==0; }
+static inline int dispzero(double x) { return dgetsignexp(x)==0; }
+static inline int dismzero(double x) { return dgetsignexp(x)==0x800; }
+static inline int disinf(double x)   { return dgetexp    (x)==0x7ff; }
+static inline int dispinf(double x)  { return dgetsignexp(x)==0x7ff; }
+static inline int disminf(double x)  { return dgetsignexp(x)==0xfff; }
+
+static inline int disint(double x) {
+    ui64 ix=double2ui64(x),m;
+    int e=dgetexp(x);
+    if(e==0) return 1;       // 0 is an integer
+    e-=0x3ff;                // remove exponent bias
+    if(e<0) return 0;        // |x|<1
+    e=52-e;                  // bit position in mantissa with significance 1
+    if(e<=0) return 1;       // |x| large, so must be an integer
+    m=(1ULL<<e)-1;           // mask for bits of significance <1
+    if(ix&m) return 0;       // not an integer
+    return 1;
+}
+
+static inline int disoddint(double x) {
+    ui64 ix=double2ui64(x),m;
+    int e=dgetexp(x);
+    e-=0x3ff;                // remove exponent bias
+    if(e<0) return 0;        // |x|<1; 0 is not odd
+    e=52-e;                  // bit position in mantissa with significance 1
+    if(e<0) return 0;        // |x| large, so must be even
+    m=(1ULL<<e)-1;           // mask for bits of significance <1 (if any)
+    if(ix&m) return 0;       // not an integer
+    if(e==52) return 1;      // value is exactly 1
+    return (ix>>e)&1;
+}
+
+static inline int disstrictneg(double x) {
+    ui64 ix=double2ui64(x);
+    if(diszero(x)) return 0;
+    return ix>>63;
+}
+
+static inline int disneg(double x) {
+    ui64 ix=double2ui64(x);
+    return ix>>63;
+}
+
+static inline double dneg(double x) {
+    ui64 ix=double2ui64(x);
+    ix^=0x8000000000000000ULL;
+    return ui642double(ix);
+}
+
+static inline int dispo2(double x) {
+    ui64 ix=double2ui64(x);
+    if(diszero(x)) return 0;
+    if(disinf(x)) return 0;
+    ix&=0x000fffffffffffffULL;
+    return ix==0;
+}
+
+static inline double dnan_or(double x) {
+#if PICO_DOUBLE_PROPAGATE_NANS
+    return NAN;
+#else
+    return x;
+#endif
+}
+
+double WRAPPER_FUNC(trunc)(double x) {
+    check_nan_d1(x);
+    ui64 ix=double2ui64(x),m;
+    int e=dgetexp(x);
+    e-=0x3ff;                // remove exponent bias
+    if(e<0) {                // |x|<1
+        ix&=0x8000000000000000ULL;
+        return ui642double(ix);
+    }
+    e=52-e;                  // bit position in mantissa with significance 1
+    if(e<=0) return x;       // |x| large, so must be an integer
+    m=(1ULL<<e)-1;           // mask for bits of significance <1
+    ix&=~m;
+    return ui642double(ix);
+}
+
+double WRAPPER_FUNC(round)(double x) {
+    check_nan_d1(x);
+    ui64 ix=double2ui64(x),m;
+    int e=dgetexp(x);
+    e-=0x3ff;                // remove exponent bias
+    if(e<-1) {               // |x|<0.5
+        ix&=0x8000000000000000ULL;
+        return ui642double(ix);
+    }
+    if(e==-1) {              // 0.5<=|x|<1
+        ix&=0x8000000000000000ULL;
+        ix|=0x3ff0000000000000ULL;        // ±1
+        return ui642double(ix);
+    }
+    e=52-e;                  // bit position in mantissa with significance 1, <=52
+    if(e<=0) return x;       // |x| large, so must be an integer
+    m=1ULL<<(e-1);           // mask for bit of significance 0.5
+    ix+=m;
+    m=m+m-1;                 // mask for bits of significance <1
+    ix&=~m;
+    return ui642double(ix);
+}
+
+double WRAPPER_FUNC(floor)(double x) {
+    check_nan_d1(x);
+    ui64 ix=double2ui64(x),m;
+    int e=dgetexp(x);
+    if(e==0) {               // x==0
+        ix&=0x8000000000000000ULL;
+        return ui642double(ix);
+    }
+    e-=0x3ff;                // remove exponent bias
+    if(e<0) {                // |x|<1, not zero
+        if(disneg(x)) return -1;
+        return PZERO;
+    }
+    e=52-e;                  // bit position in mantissa with significance 1
+    if(e<=0) return x;       // |x| large, so must be an integer
+    m=(1ULL<<e)-1;           // mask for bit of significance <1
+    if(disneg(x)) ix+=m;     // add 1-ε to magnitude if negative
+    ix&=~m;                  // truncate
+    return ui642double(ix);
+}
+
+double WRAPPER_FUNC(ceil)(double x) {
+    check_nan_d1(x);
+    ui64 ix=double2ui64(x),m;
+    int e=dgetexp(x);
+    if(e==0) {               // x==0
+        ix&=0x8000000000000000ULL;
+        return ui642double(ix);
+    }
+    e-=0x3ff;                 // remove exponent bias
+    if(e<0) {                // |x|<1, not zero
+        if(disneg(x)) return MZERO;
+        return 1;
+    }
+    e=52-e;                  // bit position in mantissa with significance 1
+    if(e<=0) return x;       // |x| large, so must be an integer
+    m=(1ULL<<e)-1;           // mask for bit of significance <1
+    if(!disneg(x)) ix+=m;    // add 1-ε to magnitude if positive
+    ix&=~m;                  // truncate
+    return ui642double(ix);
+}
+
+double WRAPPER_FUNC(asin)(double x) {
+    check_nan_d1(x);
+    double u;
+    u=(1-x)*(1+x);
+    if(disstrictneg(u)) return dnan_or(PINF);
+    return atan2(x,sqrt(u));
+}
+
+double WRAPPER_FUNC(acos)(double x) {
+    check_nan_d1(x);
+    double u;
+    u=(1-x)*(1+x);
+    if(disstrictneg(u)) return dnan_or(PINF);
+    return atan2(sqrt(u),x);
+}
+
+double WRAPPER_FUNC(atan)(double x) {
+    check_nan_d1(x);
+    if(dispinf(x)) return  PI/2;
+    if(disminf(x)) return -PI/2;
+    return atan2(x,1);
+}
+
+double WRAPPER_FUNC(sinh)(double x) {
+    check_nan_d1(x);
+    return dldexp((exp(x)-exp(dneg(x))),-1);
+}
+
+double WRAPPER_FUNC(cosh)(double x) {
+    check_nan_d1(x);
+    return dldexp((exp(x)+exp(dneg(x))),-1);
+}
+
+double WRAPPER_FUNC(tanh)(double x) {
+    check_nan_d1(x);
+    double u;
+    int e;
+    e=dgetexp(x);
+    if(e>=5+0x3ff) {             // |x|>=32?
+        if(!disneg(x)) return  1;  // 1 << exp 2x; avoid generating infinities later
+        else           return -1;  // 1 >> exp 2x
+    }
+    u=exp(dldexp(x,1));
+    return (u-1)/(u+1);
+}
+
+double WRAPPER_FUNC(asinh)(double x) {
+    check_nan_d1(x);
+    int e;
+    e=dgetexp(x);
+    if(e>=32+0x3ff) {                                // |x|>=2^32?
+        if(!disneg(x)) return      log(     x )+LOG2;  // 1/x^2 << 1
+        else           return dneg(log(dneg(x))+LOG2); // 1/x^2 << 1
+    }
+    if(x>0) return      log(sqrt(x*x+1)+x);
+    else    return dneg(log(sqrt(x*x+1)-x));
+}
+
+double WRAPPER_FUNC(acosh)(double x) {
+    check_nan_d1(x);
+    int e;
+    if(disneg(x)) x=dneg(x);
+    e=dgetexp(x);
+    if(e>=32+0x3ff) return log(x)+LOG2;           // |x|>=2^32?
+    return log(sqrt((x-1)*(x+1))+x);
+}
+
+double WRAPPER_FUNC(atanh)(double x) {
+    check_nan_d1(x);
+    return dldexp(log((1+x)/(1-x)),-1);
+}
+
+double WRAPPER_FUNC(exp2)(double x) {
+    check_nan_d1(x);
+    int e;
+    // extra check for disminf as this catches -Nan, and x<=-4096 doesn't.
+    if (disminf(x) || x<=-4096) return 0;    // easily underflows
+    else if (x>=4096)           return PINF; // easily overflows
+    e=(int)round(x);
+    x-=e;
+    return dldexp(exp(x*LOG2),e);
+}
+double WRAPPER_FUNC(log2)(double x) { check_nan_d1(x); return log(x)*LOG2E;  }
+double WRAPPER_FUNC(exp10)(double x) { check_nan_d1(x); return pow(10,x); }
+double WRAPPER_FUNC(log10)(double x) { check_nan_d1(x); return log(x)*LOG10E; }
+
+// todo these are marked as lofi
+double WRAPPER_FUNC(expm1(double x) { check_nan_d1(x); return exp)(x)-1; }
+double WRAPPER_FUNC(log1p(double x) { check_nan_d1(x); return log)(1+x); }
+double WRAPPER_FUNC(fma)(double x,double y,double z) { check_nan_d1(x); return x*y+z; }
+
+// general power, x>0, finite
+static double dpow_1(double x,double y) {
+    int a,b,c;
+    double t,rt,u,v,v0,v1,w,ry;
+    a=dgetexp(x)-0x3ff;
+    u=log2(dldexp(x,-a)); // now log_2 x = a+u
+    if(u>0.5) u-=1,a++;              // |u|<=~0.5
+    if(a==0) return exp2(u*y);
+    // here |log_2 x| >~0.5
+    if(y>= 4096) { // then easily over/underflows
+        if(a<0) return 0;
+        return PINF;
+    }
+    if(y<=-4096) { // then easily over/underflows
+        if(a<0) return PINF;
+        return 0;
+    }
+    ry=round(y);
+    v=y-ry;
+    v0=dldexp(round(ldexp(v,26)),-26);
+    v1=v-v0;
+    b=(int)ry; // guaranteed to fit in an int; y=b+v0+v1
+    // now the result is exp2( (a+u) * (b+v0+v1) )
+    c=a*b;      // integer
+    t=a*v0;
+    rt=round(t);
+    c+=(int)rt;
+    w=t-rt;
+    t=a*v1;
+    w+=t;
+    t=u*b;
+    rt=round(t);
+    c+=(int)rt;
+    w+=t-rt;
+    w+=u*v;
+    return dldexp(exp2(w),c);
+}
+
+static double dpow_int2(double x,int y) {
+    double u;
+    if(y==1) return x;
+    u=dpow_int2(x,y/2);
+    u*=u;
+    if(y&1) u*=x;
+    return u;
+}
+
+// for the case where x not zero or infinity, y small and not zero
+static inline double dpowint_1(double x,int y) {
+    if(y<0) x=1/x,y=-y;
+    return dpow_int2(x,y);
+}
+
+// for the case where x not zero or infinity
+static double dpowint_0(double x,int y) {
+    int e;
+    if(disneg(x)) {
+        if(disoddint(y)) return dneg(dpowint_0(dneg(x),y));
+        else             return      dpowint_0(dneg(x),y);
+    }
+    if(dispo2(x)) {
+        e=dgetexp(x)-0x3ff;
+        if(y>=2048) y= 2047;  // avoid overflow
+        if(y<-2048) y=-2048;
+        y*=e;
+        return dldexp(1,y);
+    }
+    if(y==0) return 1;
+    if(y>=-32&&y<=32) return dpowint_1(x,y);
+    return dpow_1(x,y);
+}
+
+double WRAPPER_FUNC(powint)(double x,int y) {
+    _Pragma("GCC diagnostic push")
+    _Pragma("GCC diagnostic ignored \"-Wfloat-equal\"")
+    if(x==1.0||y==0) return 1;
+    _Pragma("GCC diagnostic pop")
+    check_nan_d1(x);
+    if(diszero(x)) {
+        if(y>0) {
+            if(y&1) return x;
+            else    return 0;
+        }
+        if((y&1)) return dcopysign(PINF,x);
+        return PINF;
+    }
+    if(dispinf(x)) {
+        if(y<0) return 0;
+        else    return PINF;
+    }
+    if(disminf(x)) {
+        if(y>0) {
+            if((y&1)) return MINF;
+            else      return PINF;
+        }
+        if((y&1)) return MZERO;
+        else      return PZERO;
+    }
+    return dpowint_0(x,y);
+}
+
+// for the case where y is guaranteed a finite integer, x not zero or infinity
+static double dpow_0(double x,double y) {
+    int e,p;
+    if(disneg(x)) {
+        if(disoddint(y)) return dneg(dpow_0(dneg(x),y));
+        else             return      dpow_0(dneg(x),y);
+    }
+    p=(int)y;
+    if(dispo2(x)) {
+        e=dgetexp(x)-0x3ff;
+        if(p>=2048) p= 2047;  // avoid overflow
+        if(p<-2048) p=-2048;
+        p*=e;
+        return dldexp(1,p);
+    }
+    if(p==0) return 1;
+    if(p>=-32&&p<=32) return dpowint_1(x,p);
+    return dpow_1(x,y);
+}
+
+double WRAPPER_FUNC(pow)(double x,double y) {
+    _Pragma("GCC diagnostic push")
+    _Pragma("GCC diagnostic ignored \"-Wfloat-equal\"")
+
+    if(x==1.0||diszero(y)) return 1;
+    check_nan_d2(x, y);
+    if(x==-1.0&&disinf(y)) return 1;
+    _Pragma("GCC diagnostic pop")
+
+    if(diszero(x)) {
+        if(!disneg(y)) {
+            if(disoddint(y)) return x;
+            else             return 0;
+        }
+        if(disoddint(y)) return dcopysign(PINF,x);
+        return PINF;
+    }
+    if(dispinf(x)) {
+        if(disneg(y)) return 0;
+        else          return PINF;
+    }
+    if(disminf(x)) {
+        if(!disneg(y)) {
+            if(disoddint(y)) return MINF;
+            else             return PINF;
+        }
+        if(disoddint(y)) return MZERO;
+        else             return PZERO;
+    }
+    if(dispinf(y)) {
+        if(dgetexp(x)<0x3ff) return PZERO;
+        else                 return PINF;
+    }
+    if(disminf(y)) {
+        if(dgetexp(x)<0x3ff) return PINF;
+        else                 return PZERO;
+    }
+    if(disint(y)) return dpow_0(x,y);
+    if(disneg(x)) return PINF;
+    return dpow_1(x,y);
+}
+
+double WRAPPER_FUNC(hypot)(double x,double y) {
+    check_nan_d2(x, y);
+    int ex,ey;
+    ex=dgetexp(x); ey=dgetexp(y);
+    if(ex>=0x3ff+400||ey>=0x3ff+400) { // overflow, or nearly so
+        x=dldexp(x,-600),y=dldexp(y,-600);
+        return dldexp(sqrt(x*x+y*y), 600);
+    }
+    else if(ex<=0x3ff-400&&ey<=0x3ff-400) { // underflow, or nearly so
+        x=dldexp(x, 600),y=dldexp(y, 600);
+        return dldexp(sqrt(x*x+y*y),-600);
+    }
+    return sqrt(x*x+y*y);
+}
+
+double WRAPPER_FUNC(cbrt)(double x) {
+    check_nan_d1(x);
+    int e;
+    if(disneg(x)) return dneg(cbrt(dneg(x)));
+    if(diszero(x)) return dcopysign(PZERO,x);
+    e=dgetexp(x)-0x3ff;
+    e=(e*0x5555+0x8000)>>16;  // ~e/3, rounded
+    x=dldexp(x,-e*3);
+    x=exp(log(x)*ONETHIRD);
+    return dldexp(x,e);
+}
+
+// reduces mx*2^e modulo my, returning bottom bits of quotient at *pquo
+// 2^52<=|mx|,my<2^53, e>=0; 0<=result<my
+static i64 drem_0(i64 mx,i64 my,int e,int*pquo) {
+    int quo=0,q,r=0,s;
+    if(e>0) {
+        r=0xffffffffU/(ui32)(my>>36);  // reciprocal estimate Q16
+    }
+    while(e>0) {
+        s=e; if(s>12) s=12;    // gain up to 12 bits on each iteration
+        q=(mx>>38)*r;          // Q30
+        q=((q>>(29-s))+1)>>1;  // Q(s), rounded
+        mx=(mx<<s)-my*q;
+        quo=(quo<<s)+q;
+        e-=s;
+    }
+    if(mx>=my) mx-=my,quo++; // when e==0 mx can be nearly as big as 2my
+    if(mx>=my) mx-=my,quo++;
+    if(mx<0) mx+=my,quo--;
+    if(mx<0) mx+=my,quo--;
+    if(pquo) *pquo=quo;
+    return mx;
+}
+
+double WRAPPER_FUNC(fmod)(double x,double y) {
+    check_nan_d2(x, y);
+    ui64 ix=double2ui64(x),iy=double2ui64(y);
+    int sx,ex,ey;
+    i64 mx,my;
+    DUNPACKS(ix,sx,ex,mx);
+    DUNPACK(iy,ey,my);
+    if(ex==0x7ff) return dnan_or(PINF);
+    if(ey==0) return PINF;
+    if(ex==0) {
+        if(!disneg(x)) return PZERO;
+        return MZERO;
+    }
+    if(ex<ey) return x;  // |x|<|y|, including case x=±0
+    mx=drem_0(mx,my,ex-ey,0);
+    if(sx) mx=-mx;
+    return fix642double(mx,0x3ff-ey+52);
+}
+
+double WRAPPER_FUNC(remquo)(double x,double y,int*quo) {
+    check_nan_d2(x, y);
+    ui64 ix=double2ui64(x),iy=double2ui64(y);
+    int sx,sy,ex,ey,q;
+    i64 mx,my;
+    DUNPACKS(ix,sx,ex,mx);
+    DUNPACKS(iy,sy,ey,my);
+    if(quo) *quo=0;
+    if(ex==0x7ff) return PINF;
+    if(ey==0)     return PINF;
+    if(ex==0)     return PZERO;
+    if(ey==0x7ff) return x;
+    if(ex<ey-1)   return x;  // |x|<|y|/2
+    if(ex==ey-1) {
+        if(mx<=my) return x;   // |x|<=|y|/2, even quotient
+        // here |y|/2<|x|<|y|
+        if(!sx) { // x>|y|/2
+            mx-=my+my;
+            ey--;
+            q=1;
+        } else { // x<-|y|/2
+            mx=my+my-mx;
+            ey--;
+            q=-1;
+        }
+    }
+    else {
+        if(sx) mx=-mx;
+        mx=drem_0(mx,my,ex-ey,&q);
+        if(mx+mx>my || (mx+mx==my&&(q&1)) ) { // |x|>|y|/2, or equality and an odd quotient?
+            mx-=my;
+            q++;
+        }
+    }
+    if(sy) q=-q;
+    if(quo) *quo=q;
+    return fix642double(mx,0x3ff-ey+52);
+}
+
+double WRAPPER_FUNC(drem)(double x,double y) { check_nan_d2(x, y); return remquo(x,y,0); }
+
+double WRAPPER_FUNC(remainder)(double x,double y) { check_nan_d2(x, y); return remquo(x,y,0); }
+
+_Pragma("GCC diagnostic pop") // conversion
\ No newline at end of file
diff --git a/src/rp2_common/pico_double/double_none.S b/src/rp2_common/pico_double/double_none.S
new file mode 100644
index 0000000..feded31
--- /dev/null
+++ b/src/rp2_common/pico_double/double_none.S
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/asm_helper.S"
+#include "pico/bootrom/sf_table.h"
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+    wrapper_func __aeabi_dadd
+    wrapper_func __aeabi_ddiv
+    wrapper_func __aeabi_dmul
+    wrapper_func __aeabi_drsub
+    wrapper_func __aeabi_dsub
+    wrapper_func __aeabi_cdcmpeq
+    wrapper_func __aeabi_cdrcmple
+    wrapper_func __aeabi_cdcmple
+    wrapper_func __aeabi_dcmpeq
+    wrapper_func __aeabi_dcmplt
+    wrapper_func __aeabi_dcmple
+    wrapper_func __aeabi_dcmpge
+    wrapper_func __aeabi_dcmpgt
+    wrapper_func __aeabi_dcmpun
+    wrapper_func __aeabi_i2d
+    wrapper_func __aeabi_l2d
+    wrapper_func __aeabi_ui2d
+    wrapper_func __aeabi_ul2d
+    wrapper_func __aeabi_d2iz
+    wrapper_func __aeabi_d2lz
+    wrapper_func __aeabi_d2uiz
+    wrapper_func __aeabi_d2ulz
+    wrapper_func __aeabi_d2f
+    wrapper_func sqrt
+    wrapper_func cos
+    wrapper_func sin
+    wrapper_func tan
+    wrapper_func atan2
+    wrapper_func exp
+    wrapper_func log
+
+    wrapper_func ldexp
+    wrapper_func copysign
+    wrapper_func trunc
+    wrapper_func floor
+    wrapper_func ceil
+    wrapper_func round
+    wrapper_func sincos
+    wrapper_func asin
+    wrapper_func acos
+    wrapper_func atan
+    wrapper_func sinh
+    wrapper_func cosh
+    wrapper_func tanh
+    wrapper_func asinh
+    wrapper_func acosh
+    wrapper_func atanh
+    wrapper_func exp2
+    wrapper_func log2
+    wrapper_func exp10
+    wrapper_func log10
+    wrapper_func pow
+    wrapper_func powint
+    wrapper_func hypot
+    wrapper_func cbrt
+    wrapper_func fmod
+    wrapper_func drem
+    wrapper_func remainder
+    wrapper_func remquo
+    wrapper_func expm1
+    wrapper_func log1p
+    wrapper_func fma
+
+    push {lr}       // keep stack trace sane
+    ldr r0, =str
+    bl panic
+
+str:
+    .asciz "double support is disabled"
\ No newline at end of file
diff --git a/src/rp2_common/pico_double/double_v1_rom_shim.S b/src/rp2_common/pico_double/double_v1_rom_shim.S
new file mode 100644
index 0000000..7a14ca4
--- /dev/null
+++ b/src/rp2_common/pico_double/double_v1_rom_shim.S
@@ -0,0 +1,2184 @@
+/**
+ * Copyright (c) 2020 Mark Owen https://www.quinapalus.com .
+ *
+ * Raspberry Pi (Trading) Ltd (Licensor) hereby grants to you a non-exclusive license to use the software solely on a
+ * Raspberry Pi Pico device. No other use is permitted under the terms of this license.
+ *
+ * This software is also available from the copyright owner under GPLv2 licence.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "pico/asm_helper.S"
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.macro double_section name
+// todo separate flag for shims?
+#if PICO_DOUBLE_IN_RAM
+.section RAM_SECTION_NAME(\name), "ax"
+#else
+.section SECTION_NAME(\name), "ax"
+#endif
+.endm
+
+double_section double_table_shim_on_use_helper
+regular_func double_table_shim_on_use_helper
+    push {r0-r2, lr}
+    mov r0, ip
+#ifndef NDEBUG
+    // sanity check to make sure we weren't called by non (shimmable_) table_tail_call macro
+    cmp r0, #0
+    bne 1f
+    bkpt #0
+#endif
+1:
+    ldrh r1, [r0]
+    lsrs r2, r1, #8
+    adds r0, #2
+    cmp r2, #0xdf
+    bne 1b
+    uxtb r1, r1 // r1 holds table offset
+    lsrs r2, r0, #2
+    bcc 1f
+    // unaligned
+    ldrh r2, [r0, #0]
+    ldrh r0, [r0, #2]
+    lsls r0, #16
+    orrs r0, r2
+    b 2f
+1:
+    ldr r0, [r0]
+2:
+    ldr r2, =sd_table
+    str r0, [r2, r1]
+    str r0, [sp, #12]
+    pop {r0-r2, pc}
+
+#if PICO_DOUBLE_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
+// Note that the V1 ROM has no double support, so this is basically the identical
+// library, and shim inter-function calls do not bother to redirect back thru the
+// wrapper functions
+
+.equ use_hw_div,1
+.equ IOPORT       ,0xd0000000
+.equ DIV_UDIVIDEND,0x00000060
+.equ DIV_UDIVISOR ,0x00000064
+.equ DIV_QUOTIENT ,0x00000070
+.equ DIV_CSR      ,0x00000078
+
+@ Notation:
+@ rx:ry means the concatenation of rx and ry with rx having the less significant bits
+
+.equ debug,0
+.macro mdump k
+.if debug
+ push {r0-r3}
+ push {r14}
+ push {r0-r3}
+ bl osp
+ movs r0,#\k
+ bl o1ch
+ pop {r0-r3}
+ bl dump
+ bl osp
+ bl osp
+ ldr r0,[r13]
+ bl o8hex                      @ r14
+ bl onl
+ pop {r0}
+ mov r14,r0
+ pop {r0-r3}
+.endif
+.endm
+
+
+@ IEEE double in ra:rb ->
+@ mantissa in ra:rb 12Q52 (53 significant bits) with implied 1 set
+@ exponent in re
+@ sign in rs
+@ trashes rt
+.macro mdunpack ra,rb,re,rs,rt
+ lsrs \re,\rb,#20              @ extract sign and exponent
+ subs \rs,\re,#1
+ lsls \rs,#20
+ subs \rb,\rs                  @ clear sign and exponent in mantissa; insert implied 1
+ lsrs \rs,\re,#11              @ sign
+ lsls \re,#21
+ lsrs \re,#21                  @ exponent
+ beq l\@_1                     @ zero exponent?
+ adds \rt,\re,#1
+ lsrs \rt,#11
+ beq l\@_2                     @ exponent != 0x7ff? then done
+l\@_1:
+ movs \ra,#0
+ movs \rb,#1
+ lsls \rb,#20
+ subs \re,#128
+ lsls \re,#12
+l\@_2:
+.endm
+
+@ IEEE double in ra:rb ->
+@ signed mantissa in ra:rb 12Q52 (53 significant bits) with implied 1
+@ exponent in re
+@ trashes rt0 and rt1
+@ +zero, +denormal -> exponent=-0x80000
+@ -zero, -denormal -> exponent=-0x80000
+@ +Inf, +NaN -> exponent=+0x77f000
+@ -Inf, -NaN -> exponent=+0x77e000
+.macro mdunpacks ra,rb,re,rt0,rt1
+ lsrs \re,\rb,#20              @ extract sign and exponent
+ lsrs \rt1,\rb,#31             @ sign only
+ subs \rt0,\re,#1
+ lsls \rt0,#20
+ subs \rb,\rt0                 @ clear sign and exponent in mantissa; insert implied 1
+ lsls \re,#21
+ bcc l\@_1                     @ skip on positive
+ mvns \rb,\rb                  @ negate mantissa
+ rsbs \ra,#0
+ bcc l\@_1
+ adds \rb,#1
+l\@_1:
+ lsrs \re,#21
+ beq l\@_2                     @ zero exponent?
+ adds \rt0,\re,#1
+ lsrs \rt0,#11
+ beq l\@_3                     @ exponent != 0x7ff? then done
+ subs \re,\rt1
+l\@_2:
+ movs \ra,#0
+ lsls \rt1,#1                  @ +ve: 0  -ve: 2
+ adds \rb,\rt1,#1              @ +ve: 1  -ve: 3
+ lsls \rb,#30                  @ create +/-1 mantissa
+ asrs \rb,#10
+ subs \re,#128
+ lsls \re,#12
+l\@_3:
+.endm
+
+double_section WRAPPER_FUNC_NAME(__aeabi_dsub)
+
+# frsub first because it is the only one that needs alignment
+regular_func drsub_shim
+    push {r0-r3}
+    pop {r0-r1}
+    pop {r2-r3}
+    // fall thru
+
+regular_func dsub_shim
+ push {r4-r7,r14}
+ movs r4,#1
+ lsls r4,#31
+ eors r3,r4                    @ flip sign on second argument
+ b da_entry                    @ continue in dadd
+
+.align 2
+double_section dadd_shim
+regular_func dadd_shim
+ push {r4-r7,r14}
+da_entry:
+ mdunpacks r0,r1,r4,r6,r7
+ mdunpacks r2,r3,r5,r6,r7
+ subs r7,r5,r4                 @ ye-xe
+ subs r6,r4,r5                 @ xe-ye
+ bmi da_ygtx
+@ here xe>=ye: need to shift y down r6 places
+ mov r12,r4                    @ save exponent
+ cmp r6,#32
+ bge da_xrgty                  @ xe rather greater than ye?
+ adds r7,#32
+ movs r4,r2
+ lsls r4,r4,r7                 @ rounding bit + sticky bits
+da_xgty0:
+ movs r5,r3
+ lsls r5,r5,r7
+ lsrs r2,r6
+ asrs r3,r6
+ orrs r2,r5
+da_add:
+ adds r0,r2
+ adcs r1,r3
+da_pack:
+@ here unnormalised signed result (possibly 0) is in r0:r1 with exponent r12, rounding + sticky bits in r4
+@ Note that if a large normalisation shift is required then the arguments were close in magnitude and so we
+@ cannot have not gone via the xrgty/yrgtx paths. There will therefore always be enough high bits in r4
+@ to provide a correct continuation of the exact result.
+@ now pack result back up
+ lsrs r3,r1,#31                @ get sign bit
+ beq 1f                        @ skip on positive
+ mvns r1,r1                    @ negate mantissa
+ mvns r0,r0
+ movs r2,#0
+ rsbs r4,#0
+ adcs r0,r2
+ adcs r1,r2
+1:
+ mov r2,r12                    @ get exponent
+ lsrs r5,r1,#21
+ bne da_0                      @ shift down required?
+ lsrs r5,r1,#20
+ bne da_1                      @ normalised?
+ cmp r0,#0
+ beq da_5                      @ could mantissa be zero?
+da_2:
+ adds r4,r4
+ adcs r0,r0
+ adcs r1,r1
+ subs r2,#1                    @ adjust exponent
+ lsrs r5,r1,#20
+ beq da_2
+da_1:
+ lsls r4,#1                    @ check rounding bit
+ bcc da_3
+da_4:
+ adds r0,#1                    @ round up
+ bcc 2f
+ adds r1,#1
+2:
+ cmp r4,#0                     @ sticky bits zero?
+ bne da_3
+ lsrs r0,#1                    @ round to even
+ lsls r0,#1
+da_3:
+ subs r2,#1
+ bmi da_6
+ adds r4,r2,#2                 @ check if exponent is overflowing
+ lsrs r4,#11
+ bne da_7
+ lsls r2,#20                   @ pack exponent and sign
+ add r1,r2
+ lsls r3,#31
+ add r1,r3
+ pop {r4-r7,r15}
+
+da_7:
+@ here exponent overflow: return signed infinity
+ lsls r1,r3,#31
+ ldr r3,=#0x7ff00000
+ orrs r1,r3
+ b 1f
+da_6:
+@ here exponent underflow: return signed zero
+ lsls r1,r3,#31
+1:
+ movs r0,#0
+ pop {r4-r7,r15}
+
+da_5:
+@ here mantissa could be zero
+ cmp r1,#0
+ bne da_2
+ cmp r4,#0
+ bne da_2
+@ inputs must have been of identical magnitude and opposite sign, so return +0
+ pop {r4-r7,r15}
+
+da_0:
+@ here a shift down by one place is required for normalisation
+ adds r2,#1                    @ adjust exponent
+ lsls r6,r0,#31                @ save rounding bit
+ lsrs r0,#1
+ lsls r5,r1,#31
+ orrs r0,r5
+ lsrs r1,#1
+ cmp r6,#0
+ beq da_3
+ b da_4
+
+da_xrgty:                      @ xe>ye and shift>=32 places
+ cmp r6,#60
+ bge da_xmgty                  @ xe much greater than ye?
+ subs r6,#32
+ adds r7,#64
+
+ movs r4,r2
+ lsls r4,r4,r7                 @ these would be shifted off the bottom of the sticky bits
+ beq 1f
+ movs r4,#1
+1:
+ lsrs r2,r2,r6
+ orrs r4,r2
+ movs r2,r3
+ lsls r3,r3,r7
+ orrs r4,r3
+ asrs r3,r2,#31                @ propagate sign bit
+ b da_xgty0
+
+da_ygtx:
+@ here ye>xe: need to shift x down r7 places
+ mov r12,r5                    @ save exponent
+ cmp r7,#32
+ bge da_yrgtx                  @ ye rather greater than xe?
+ adds r6,#32
+ movs r4,r0
+ lsls r4,r4,r6                 @ rounding bit + sticky bits
+da_ygtx0:
+ movs r5,r1
+ lsls r5,r5,r6
+ lsrs r0,r7
+ asrs r1,r7
+ orrs r0,r5
+ b da_add
+
+da_yrgtx:
+ cmp r7,#60
+ bge da_ymgtx                  @ ye much greater than xe?
+ subs r7,#32
+ adds r6,#64
+
+ movs r4,r0
+ lsls r4,r4,r6                 @ these would be shifted off the bottom of the sticky bits
+ beq 1f
+ movs r4,#1
+1:
+ lsrs r0,r0,r7
+ orrs r4,r0
+ movs r0,r1
+ lsls r1,r1,r6
+ orrs r4,r1
+ asrs r1,r0,#31                @ propagate sign bit
+ b da_ygtx0
+
+da_ymgtx:                      @ result is just y
+ movs r0,r2
+ movs r1,r3
+da_xmgty:                      @ result is just x
+ movs r4,#0                    @ clear sticky bits
+ b da_pack
+
+.ltorg
+
+@ equivalent of UMULL
+@ needs five temporary registers
+@ can have rt3==rx, in which case rx trashed
+@ can have rt4==ry, in which case ry trashed
+@ can have rzl==rx
+@ can have rzh==ry
+@ can have rzl,rzh==rt3,rt4
+.macro mul32_32_64 rx,ry,rzl,rzh,rt0,rt1,rt2,rt3,rt4
+                               @   t0   t1   t2   t3   t4
+                               @                  (x)  (y)
+ uxth \rt0,\rx                 @   xl
+ uxth \rt1,\ry                 @        yl
+ muls \rt0,\rt1                @  xlyl=L
+ lsrs \rt2,\rx,#16             @             xh
+ muls \rt1,\rt2                @       xhyl=M0
+ lsrs \rt4,\ry,#16             @                       yh
+ muls \rt2,\rt4                @           xhyh=H
+ uxth \rt3,\rx                 @                   xl
+ muls \rt3,\rt4                @                  xlyh=M1
+ adds \rt1,\rt3                @      M0+M1=M
+ bcc l\@_1                     @ addition of the two cross terms can overflow, so add carry into H
+ movs \rt3,#1                  @                   1
+ lsls \rt3,#16                 @                0x10000
+ adds \rt2,\rt3                @             H'
+l\@_1:
+                               @   t0   t1   t2   t3   t4
+                               @                 (zl) (zh)
+ lsls \rzl,\rt1,#16            @                  ML
+ lsrs \rzh,\rt1,#16            @                       MH
+ adds \rzl,\rt0                @                  ZL
+ adcs \rzh,\rt2                @                       ZH
+.endm
+
+@ SUMULL: x signed, y unsigned
+@ in table below ¯ means signed variable
+@ needs five temporary registers
+@ can have rt3==rx, in which case rx trashed
+@ can have rt4==ry, in which case ry trashed
+@ can have rzl==rx
+@ can have rzh==ry
+@ can have rzl,rzh==rt3,rt4
+.macro muls32_32_64 rx,ry,rzl,rzh,rt0,rt1,rt2,rt3,rt4
+                               @   t0   t1   t2   t3   t4
+                               @                 ¯(x)  (y)
+ uxth \rt0,\rx                 @   xl
+ uxth \rt1,\ry                 @        yl
+ muls \rt0,\rt1                @  xlyl=L
+ asrs \rt2,\rx,#16             @            ¯xh
+ muls \rt1,\rt2                @      ¯xhyl=M0
+ lsrs \rt4,\ry,#16             @                       yh
+ muls \rt2,\rt4                @          ¯xhyh=H
+ uxth \rt3,\rx                 @                   xl
+ muls \rt3,\rt4                @                 xlyh=M1
+ asrs \rt4,\rt1,#31            @                      M0sx   (M1 sign extension is zero)
+ adds \rt1,\rt3                @      M0+M1=M
+ movs \rt3,#0                  @                    0
+ adcs \rt4,\rt3                @                      ¯Msx
+ lsls \rt4,#16                 @                    ¯Msx<<16
+ adds \rt2,\rt4                @             H'
+
+                               @   t0   t1   t2   t3   t4
+                               @                 (zl) (zh)
+ lsls \rzl,\rt1,#16            @                  M~
+ lsrs \rzh,\rt1,#16            @                       M~
+ adds \rzl,\rt0                @                  ZL
+ adcs \rzh,\rt2                @                      ¯ZH
+.endm
+
+@ SSMULL: x signed, y signed
+@ in table below ¯ means signed variable
+@ needs five temporary registers
+@ can have rt3==rx, in which case rx trashed
+@ can have rt4==ry, in which case ry trashed
+@ can have rzl==rx
+@ can have rzh==ry
+@ can have rzl,rzh==rt3,rt4
+.macro muls32_s32_64 rx,ry,rzl,rzh,rt0,rt1,rt2,rt3,rt4
+                               @   t0   t1   t2   t3   t4
+                               @                 ¯(x)  (y)
+ uxth \rt0,\rx                 @   xl
+ uxth \rt1,\ry                 @        yl
+ muls \rt0,\rt1                @  xlyl=L
+ asrs \rt2,\rx,#16             @            ¯xh
+ muls \rt1,\rt2                @      ¯xhyl=M0
+ asrs \rt4,\ry,#16             @                      ¯yh
+ muls \rt2,\rt4                @          ¯xhyh=H
+ uxth \rt3,\rx                 @                   xl
+ muls \rt3,\rt4                @                ¯xlyh=M1
+ adds \rt1,\rt3                @     ¯M0+M1=M
+ asrs \rt3,\rt1,#31            @                  Msx
+ bvc l\@_1                     @
+ mvns \rt3,\rt3                @                 ¯Msx        flip sign extension bits if overflow
+l\@_1:
+ lsls \rt3,#16                 @                    ¯Msx<<16
+ adds \rt2,\rt3                @             H'
+
+                               @   t0   t1   t2   t3   t4
+                               @                 (zl) (zh)
+ lsls \rzl,\rt1,#16            @                  M~
+ lsrs \rzh,\rt1,#16            @                       M~
+ adds \rzl,\rt0                @                  ZL
+ adcs \rzh,\rt2                @                      ¯ZH
+.endm
+
+@ can have rt2==rx, in which case rx trashed
+@ can have rzl==rx
+@ can have rzh==rt1
+.macro square32_64 rx,rzl,rzh,rt0,rt1,rt2
+                               @   t0   t1   t2   zl   zh
+ uxth \rt0,\rx                 @   xl
+ muls \rt0,\rt0                @ xlxl=L
+ uxth \rt1,\rx                 @        xl
+ lsrs \rt2,\rx,#16             @             xh
+ muls \rt1,\rt2                @      xlxh=M
+ muls \rt2,\rt2                @           xhxh=H
+ lsls \rzl,\rt1,#17            @                  ML
+ lsrs \rzh,\rt1,#15            @                       MH
+ adds \rzl,\rt0                @                  ZL
+ adcs \rzh,\rt2                @                       ZH
+.endm
+
+double_section dmul_shim
+ regular_func dmul_shim
+ push {r4-r7,r14}
+ mdunpack r0,r1,r4,r6,r5
+ mov r12,r4
+ mdunpack r2,r3,r4,r7,r5
+ eors r7,r6                    @ sign of result
+ add r4,r12                    @ exponent of result
+ push {r0-r2,r4,r7}
+
+@ accumulate full product in r12:r5:r6:r7
+ mul32_32_64 r0,r2, r0,r5, r4,r6,r7,r0,r5    @ XL*YL
+ mov r12,r0                    @ save LL bits
+
+ mul32_32_64 r1,r3, r6,r7, r0,r2,r4,r6,r7    @ XH*YH
+
+ pop {r0}                      @ XL
+ mul32_32_64 r0,r3, r0,r3, r1,r2,r4,r0,r3    @ XL*YH
+ adds r5,r0
+ adcs r6,r3
+ movs r0,#0
+ adcs r7,r0
+
+ pop {r1,r2}                   @ XH,YL
+ mul32_32_64 r1,r2, r1,r2, r0,r3,r4, r1,r2   @ XH*YL
+ adds r5,r1
+ adcs r6,r2
+ movs r0,#0
+ adcs r7,r0
+
+@ here r5:r6:r7 holds the product [1..4) in Q(104-32)=Q72, with extra LSBs in r12
+ pop {r3,r4}                   @ exponent in r3, sign in r4
+ lsls r1,r7,#11
+ lsrs r2,r6,#21
+ orrs r1,r2
+ lsls r0,r6,#11
+ lsrs r2,r5,#21
+ orrs r0,r2
+ lsls r5,#11                   @ now r5:r0:r1 Q83=Q(51+32), extra LSBs in r12
+ lsrs r2,r1,#20
+ bne 1f                        @ skip if in range [2..4)
+ adds r5,r5                    @ shift up so always [2..4) Q83, i.e. [1..2) Q84=Q(52+32)
+ adcs r0,r0
+ adcs r1,r1
+ subs r3,#1                    @ correct exponent
+1:
+ ldr r6,=#0x3ff
+ subs r3,r6                    @ correct for exponent bias
+ lsls r6,#1                    @ 0x7fe
+ cmp r3,r6
+ bhs dm_0                      @ exponent over- or underflow
+ lsls r5,#1                    @ rounding bit to carry
+ bcc 1f                        @ result is correctly rounded
+ adds r0,#1
+ movs r6,#0
+ adcs r1,r6                    @ round up
+ mov r6,r12                    @ remaining sticky bits
+ orrs r5,r6
+ bne 1f                        @ some sticky bits set?
+ lsrs r0,#1
+ lsls r0,#1                    @ round to even
+1:
+ lsls r3,#20
+ adds r1,r3
+dm_2:
+ lsls r4,#31
+ add r1,r4
+ pop {r4-r7,r15}
+
+@ here for exponent over- or underflow
+dm_0:
+ bge dm_1                      @ overflow?
+ adds r3,#1                    @ would-be zero exponent?
+ bne 1f
+ adds r0,#1
+ bne 1f                        @ all-ones mantissa?
+ adds r1,#1
+ lsrs r7,r1,#21
+ beq 1f
+ lsrs r1,#1
+ b dm_2
+1:
+ lsls r1,r4,#31
+ movs r0,#0
+ pop {r4-r7,r15}
+
+@ here for exponent overflow
+dm_1:
+ adds r6,#1                    @ 0x7ff
+ lsls r1,r6,#20
+ movs r0,#0
+ b dm_2
+
+.ltorg
+
+@ Approach to division y/x is as follows.
+@
+@ First generate u1, an approximation to 1/x to about 29 bits. Multiply this by the top
+@ 32 bits of y to generate a0, a first approximation to the result (good to 28 bits or so).
+@ Calculate the exact remainder r0=y-a0*x, which will be about 0. Calculate a correction
+@ d0=r0*u1, and then write a1=a0+d0. If near a rounding boundary, compute the exact
+@ remainder r1=y-a1*x (which can be done using r0 as a basis) to determine whether to
+@ round up or down.
+@
+@ The calculation of 1/x is as given in dreciptest.c. That code verifies exhaustively
+@ that | u1*x-1 | < 10*2^-32.
+@
+@ More precisely:
+@
+@ x0=(q16)x;
+@ x1=(q30)x;
+@ y0=(q31)y;
+@ u0=(q15~)"(0xffffffffU/(unsigned int)roundq(x/x_ulp))/powq(2,16)"(x0); // q15 approximation to 1/x; "~" denotes rounding rather than truncation
+@ v=(q30)(u0*x1-1);
+@ u1=(q30)u0-(q30~)(u0*v);
+@
+@ a0=(q30)(u1*y0);
+@ r0=(q82)y-a0*x;
+@ r0x=(q57)r0;
+@ d0=r0x*u1;
+@ a1=d0+a0;
+@
+@ Error analysis
+@
+@ Use Greek letters to represent the errors introduced by rounding and truncation.
+@
+@               r₀ = y - a₀x
+@                  = y - [ u₁ ( y - α ) - β ] x    where 0 ≤ α < 2^-31, 0 ≤ β < 2^-30
+@                  = y ( 1 - u₁x ) + ( u₁α + β ) x
+@
+@     Hence
+@
+@       | r₀ / x | < 2 * 10*2^-32 + 2^-31 + 2^-30
+@                  = 26*2^-32
+@
+@               r₁ = y - a₁x
+@                  = y - a₀x - d₀x
+@                  = r₀ - d₀x
+@                  = r₀ - u₁ ( r₀ - γ ) x    where 0 ≤ γ < 2^-57
+@                  = r₀ ( 1 - u₁x ) + u₁γx
+@
+@     Hence
+@
+@       | r₁ / x | < 26*2^-32 * 10*2^-32 + 2^-57
+@                  = (260+128)*2^-64
+@                  < 2^-55
+@
+@ Empirically it seems to be nearly twice as good as this.
+@
+@ To determine correctly whether the exact remainder calculation can be skipped we need a result
+@ accurate to < 0.25ulp. In the case where x>y the quotient will be shifted up one place for normalisation
+@ and so 1ulp is 2^-53 and so the calculation above suffices.
+
+double_section ddiv_shim
+ regular_func ddiv_shim
+ push {r4-r7,r14}
+ddiv0:                         @ entry point from dtan
+ mdunpack r2,r3,r4,r7,r6       @ unpack divisor
+
+.if use_hw_div
+
+ movs r5,#IOPORT>>24
+ lsls r5,#24
+ movs r6,#0
+ mvns r6,r6
+ str r6,[r5,#DIV_UDIVIDEND]
+ lsrs r6,r3,#4                 @ x0=(q16)x
+ str r6,[r5,#DIV_UDIVISOR]
+@ if there are not enough cycles from now to the read of the quotient for
+@ the divider to do its stuff we need a busy-wait here
+
+.endif
+
+@ unpack dividend by hand to save on register use
+ lsrs r6,r1,#31
+ adds r6,r7
+ mov r12,r6                    @ result sign in r12b0; r12b1 trashed
+ lsls r1,#1
+ lsrs r7,r1,#21                @ exponent
+ beq 1f                        @ zero exponent?
+ adds r6,r7,#1
+ lsrs r6,#11
+ beq 2f                        @ exponent != 0x7ff? then done
+1:
+ movs r0,#0
+ movs r1,#0
+ subs r7,#64                   @ less drastic fiddling of exponents to get 0/0, Inf/Inf correct
+ lsls r7,#12
+2:
+ subs r6,r7,r4
+ lsls r6,#2
+ add r12,r12,r6                @ (signed) exponent in r12[31..8]
+ subs r7,#1                    @ implied 1
+ lsls r7,#21
+ subs r1,r7
+ lsrs r1,#1
+
+.if use_hw_div
+
+ ldr r6,[r5,#DIV_QUOTIENT]
+ adds r6,#1
+ lsrs r6,#1
+
+.else
+
+@ this is not beautiful; could be replaced by better code that uses knowledge of divisor range
+ push {r0-r3}
+ movs r0,#0
+ mvns r0,r0
+ lsrs r1,r3,#4                 @ x0=(q16)x
+ bl __aeabi_uidiv              @ !!! this could (but apparently does not) trash R12
+ adds r6,r0,#1
+ lsrs r6,#1
+ pop {r0-r3}
+
+.endif
+
+@ here
+@ r0:r1 y mantissa
+@ r2:r3 x mantissa
+@ r6    u0, first approximation to 1/x Q15
+@ r12: result sign, exponent
+
+ lsls r4,r3,#10
+ lsrs r5,r2,#22
+ orrs r5,r4                    @ x1=(q30)x
+ muls r5,r6                    @ u0*x1 Q45
+ asrs r5,#15                   @ v=u0*x1-1 Q30
+ muls r5,r6                    @ u0*v Q45
+ asrs r5,#14
+ adds r5,#1
+ asrs r5,#1                    @ round u0*v to Q30
+ lsls r6,#15
+ subs r6,r5                    @ u1 Q30
+
+@ here
+@ r0:r1 y mantissa
+@ r2:r3 x mantissa
+@ r6    u1, second approximation to 1/x Q30
+@ r12: result sign, exponent
+
+ push {r2,r3}
+ lsls r4,r1,#11
+ lsrs r5,r0,#21
+ orrs r4,r5                    @ y0=(q31)y
+ mul32_32_64 r4,r6, r4,r5, r2,r3,r7,r4,r5  @ y0*u1 Q61
+ adds r4,r4
+ adcs r5,r5                    @ a0=(q30)(y0*u1)
+
+@ here
+@ r0:r1 y mantissa
+@ r5    a0, first approximation to y/x Q30
+@ r6    u1, second approximation to 1/x Q30
+@ r12   result sign, exponent
+
+ ldr r2,[r13,#0]               @ xL
+ mul32_32_64 r2,r5, r2,r3, r1,r4,r7,r2,r3  @ xL*a0
+ ldr r4,[r13,#4]               @ xH
+ muls r4,r5                    @ xH*a0
+ adds r3,r4                    @ r2:r3 now x*a0 Q82
+ lsrs r2,#25
+ lsls r1,r3,#7
+ orrs r2,r1                    @ r2 now x*a0 Q57; r7:r2 is x*a0 Q89
+ lsls r4,r0,#5                 @ y Q57
+ subs r0,r4,r2                 @ r0x=y-x*a0 Q57 (signed)
+
+@ here
+@ r0  r0x Q57
+@ r5  a0, first approximation to y/x Q30
+@ r4  yL  Q57
+@ r6  u1 Q30
+@ r12 result sign, exponent
+
+ muls32_32_64 r0,r6, r7,r6, r1,r2,r3, r7,r6   @ r7:r6 r0x*u1 Q87
+ asrs r3,r6,#25
+ adds r5,r3
+ lsls r3,r6,#7                 @ r3:r5 a1 Q62 (but bottom 7 bits are zero so 55 bits of precision after binary point)
+@ here we could recover another 7 bits of precision (but not accuracy) from the top of r7
+@ but these bits are thrown away in the rounding and conversion to Q52 below
+
+@ here
+@ r3:r5  a1 Q62 candidate quotient [0.5,2) or so
+@ r4     yL Q57
+@ r12    result sign, exponent
+
+ movs r6,#0
+ adds r3,#128                  @ for initial rounding to Q53
+ adcs r5,r5,r6
+ lsrs  r1,r5,#30
+ bne dd_0
+@ here candidate quotient a1 is in range [0.5,1)
+@ so 30 significant bits in r5
+
+ lsls r4,#1                    @ y now Q58
+ lsrs r1,r5,#9                 @ to Q52
+ lsls r0,r5,#23
+ lsrs r3,#9                    @ 0.5ulp-significance bit in carry: if this is 1 we may need to correct result
+ orrs r0,r3
+ bcs dd_1
+ b dd_2
+dd_0:
+@ here candidate quotient a1 is in range [1,2)
+@ so 31 significant bits in r5
+
+ movs r2,#4
+ add r12,r12,r2                @ fix exponent; r3:r5 now effectively Q61
+ adds r3,#128                  @ complete rounding to Q53
+ adcs r5,r5,r6
+ lsrs r1,r5,#10
+ lsls r0,r5,#22
+ lsrs r3,#10                   @ 0.5ulp-significance bit in carry: if this is 1 we may need to correct result
+ orrs r0,r3
+ bcc dd_2
+dd_1:
+
+@ here
+@ r0:r1  rounded result Q53 [0.5,1) or Q52 [1,2), but may not be correctly rounded-to-nearest
+@ r4     yL Q58 or Q57
+@ r12    result sign, exponent
+@ carry set
+
+ adcs r0,r0,r0
+ adcs r1,r1,r1                 @ z Q53 with 1 in LSB
+ lsls r4,#16                   @ Q105-32=Q73
+ ldr r2,[r13,#0]               @ xL Q52
+ ldr r3,[r13,#4]               @ xH Q20
+
+ movs r5,r1                    @ zH Q21
+ muls r5,r2                    @ zH*xL Q73
+ subs r4,r5
+ muls r3,r0                    @ zL*xH Q73
+ subs r4,r3
+ mul32_32_64 r2,r0, r2,r3, r5,r6,r7,r2,r3  @ xL*zL
+ rsbs r2,#0                    @ borrow from low half?
+ sbcs r4,r3                    @ y-xz Q73 (remainder bits 52..73)
+
+ cmp r4,#0
+
+ bmi 1f
+ movs r2,#0                    @ round up
+ adds r0,#1
+ adcs r1,r2
+1:
+ lsrs r0,#1                    @ shift back down to Q52
+ lsls r2,r1,#31
+ orrs r0,r2
+ lsrs r1,#1
+dd_2:
+ add r13,#8
+ mov r2,r12
+ lsls r7,r2,#31                @ result sign
+ asrs r2,#2                    @ result exponent
+ ldr r3,=#0x3fd
+ adds r2,r3
+ ldr r3,=#0x7fe
+ cmp r2,r3
+ bhs dd_3                      @ over- or underflow?
+ lsls r2,#20
+ adds r1,r2                    @ pack exponent
+dd_5:
+ adds r1,r7                    @ pack sign
+ pop {r4-r7,r15}
+
+dd_3:
+ movs r0,#0
+ cmp r2,#0
+ bgt dd_4                      @ overflow?
+ movs r1,r7
+ pop {r4-r7,r15}
+
+dd_4:
+ adds r3,#1                    @ 0x7ff
+ lsls r1,r3,#20
+ b dd_5
+
+.section SECTION_NAME(dsqrt_shim)
+/*
+Approach to square root x=sqrt(y) is as follows.
+
+First generate a3, an approximation to 1/sqrt(y) to about 30 bits. Multiply this by y
+to give a4~sqrt(y) to about 28 bits and a remainder r4=y-a4^2. Then, because
+d sqrt(y) / dy = 1 / (2 sqrt(y)) let d4=r4*a3/2 and then the value a5=a4+d4 is
+a better approximation to sqrt(y). If this is near a rounding boundary we
+compute an exact remainder y-a5*a5 to decide whether to round up or down.
+
+The calculation of a3 and a4 is as given in dsqrttest.c. That code verifies exhaustively
+that | 1 - a3a4 | < 10*2^-32, | r4 | < 40*2^-32 and | r4/y | < 20*2^-32.
+
+More precisely, with "y" representing y truncated to 30 binary places:
+
+u=(q3)y;                          // 24-entry table
+a0=(q8~)"1/sqrtq(x+x_ulp/2)"(u);  // first approximation from table
+p0=(q16)(a0*a0) * (q16)y;
+r0=(q20)(p0-1);
+dy0=(q15)(r0*a0);                 // Newton-Raphson correction term
+a1=(q16)a0-dy0/2;                 // good to ~9 bits
+
+p1=(q19)(a1*a1)*(q19)y;
+r1=(q23)(p1-1);
+dy1=(q15~)(r1*a1);                // second Newton-Raphson correction
+a2x=(q16)a1-dy1/2;                // good to ~16 bits
+a2=a2x-a2x/1t16;                  // prevent overflow of a2*a2 in 32 bits
+
+p2=(a2*a2)*(q30)y;                // Q62
+r2=(q36)(p2-1+1t-31);
+dy2=(q30)(r2*a2);                 // Q52->Q30
+a3=(q31)a2-dy2/2;                 // good to about 30 bits
+a4=(q30)(a3*(q30)y+1t-31);        // good to about 28 bits
+
+Error analysis
+
+          r₄ = y - a₄²
+          d₄ = 1/2 a₃r₄
+          a₅ = a₄ + d₄
+          r₅ = y - a₅²
+             = y - ( a₄ + d₄ )²
+             = y - a₄² - a₃a₄r₄ - 1/4 a₃²r₄²
+             = r₄ - a₃a₄r₄ - 1/4 a₃²r₄²
+
+      | r₅ | < | r₄ | | 1 - a₃a₄ | + 1/4 r₄²
+
+          a₅ = √y √( 1 - r₅/y )
+             = √y ( 1 - 1/2 r₅/y + ... )
+
+So to first order (second order being very tiny)
+
+     √y - a₅ = 1/2 r₅/y
+
+and
+
+ | √y - a₅ | < 1/2 ( | r₄/y | | 1 - a₃a₄ | + 1/4 r₄²/y )
+
+From dsqrttest.c (conservatively):
+
+             < 1/2 ( 20*2^-32 * 10*2^-32 + 1/4 * 40*2^-32*20*2^-32 )
+             = 1/2 ( 200 + 200 ) * 2^-64
+             < 2^-56
+
+Empirically we see about 1ulp worst-case error including rounding at Q57.
+
+To determine correctly whether the exact remainder calculation can be skipped we need a result
+accurate to < 0.25ulp at Q52, or 2^-54.
+*/
+
+dq_2:
+ bge dq_3                      @ +Inf?
+ movs r1,#0
+ b dq_4
+
+dq_0:
+ lsrs r1,#31
+ lsls r1,#31                   @ preserve sign bit
+ lsrs r2,#21                   @ extract exponent
+ beq dq_4                      @ -0? return it
+ asrs r1,#11                   @ make -Inf
+ b dq_4
+
+dq_3:
+ ldr r1,=#0x7ff
+ lsls r1,#20                   @ return +Inf
+dq_4:
+ movs r0,#0
+dq_1:
+ bx r14
+
+.align 2
+regular_func dsqrt_shim
+ lsls r2,r1,#1
+ bcs dq_0                      @ negative?
+ lsrs r2,#21                   @ extract exponent
+ subs r2,#1
+ ldr r3,=#0x7fe
+ cmp r2,r3
+ bhs dq_2                      @ catches 0 and +Inf
+ push {r4-r7,r14}
+ lsls r4,r2,#20
+ subs r1,r4                    @ insert implied 1
+ lsrs r2,#1
+ bcc 1f                        @ even exponent? skip
+ adds r0,r0,r0                 @ odd exponent: shift up mantissa
+ adcs r1,r1,r1
+1:
+ lsrs r3,#2
+ adds r2,r3
+ lsls r2,#20
+ mov r12,r2                    @ save result exponent
+
+@ here
+@ r0:r1  y mantissa Q52 [1,4)
+@ r12    result exponent
+
+ adr r4,drsqrtapp-8            @ first eight table entries are never accessed because of the mantissa's leading 1
+ lsrs r2,r1,#17                @ y Q3
+ ldrb r2,[r4,r2]               @ initial approximation to reciprocal square root a0 Q8
+ lsrs r3,r1,#4                 @ first Newton-Raphson iteration
+ muls r3,r2
+ muls r3,r2                    @  i32 p0=a0*a0*(y>>14);          // Q32
+ asrs r3,r3,#12                @  i32 r0=p0>>12;                 // Q20
+ muls r3,r2
+ asrs r3,#13                   @  i32 dy0=(r0*a0)>>13;           // Q15
+ lsls r2,#8
+ subs r2,r3                    @  i32 a1=(a0<<8)-dy0;         // Q16
+
+ movs r3,r2
+ muls r3,r3
+ lsrs r3,#13
+ lsrs r4,r1,#1
+ muls r3,r4                    @  i32 p1=((a1*a1)>>11)*(y>>11);  // Q19*Q19=Q38
+ asrs r3,#15                   @  i32 r1=p1>>15;                 // Q23
+ muls r3,r2
+ asrs r3,#23
+ adds r3,#1
+ asrs r3,#1                    @  i32 dy1=(r1*a1+(1<<23))>>24;   // Q23*Q16=Q39; Q15
+ subs r2,r3                    @  i32 a2=a1-dy1;                 // Q16
+ lsrs r3,r2,#16
+ subs r2,r3                    @  if(a2>=0x10000) a2=0xffff; to prevent overflow of a2*a2
+
+@ here
+@ r0:r1 y mantissa
+@ r2    a2 ~ 1/sqrt(y) Q16
+@ r12   result exponent
+
+ movs r3,r2
+ muls r3,r3
+ lsls r1,#10
+ lsrs r4,r0,#22
+ orrs r1,r4                    @ y Q30
+ mul32_32_64 r1,r3, r4,r3, r5,r6,r7,r4,r3   @  i64 p2=(ui64)(a2*a2)*(ui64)y;  // Q62 r4:r3
+ lsls r5,r3,#6
+ lsrs r4,#26
+ orrs r4,r5
+ adds r4,#0x20                 @  i32 r2=(p2>>26)+0x20;          // Q36 r4
+ uxth r5,r4
+ muls r5,r2
+ asrs r4,#16
+ muls r4,r2
+ lsrs r5,#16
+ adds r4,r5
+ asrs r4,#6                    @ i32 dy2=((i64)r2*(i64)a2)>>22; // Q36*Q16=Q52; Q30
+ lsls r2,#15
+ subs r2,r4
+
+@ here
+@ r0    y low bits
+@ r1    y Q30
+@ r2    a3 ~ 1/sqrt(y) Q31
+@ r12   result exponent
+
+ mul32_32_64 r2,r1, r3,r4, r5,r6,r7,r3,r4
+ adds r3,r3,r3
+ adcs r4,r4,r4
+ adds r3,r3,r3
+ movs r3,#0
+ adcs r3,r4                    @ ui32 a4=((ui64)a3*(ui64)y+(1U<<31))>>31; // Q30
+
+@ here
+@ r0    y low bits
+@ r1    y Q30
+@ r2    a3 Q31 ~ 1/sqrt(y)
+@ r3    a4 Q30 ~ sqrt(y)
+@ r12   result exponent
+
+ square32_64 r3, r4,r5, r6,r5,r7
+ lsls r6,r0,#8
+ lsrs r7,r1,#2
+ subs r6,r4
+ sbcs r7,r5                    @ r4=(q60)y-a4*a4
+
+@ by exhaustive testing, r4 = fffffffc0e134fdc .. 00000003c2bf539c Q60
+
+ lsls r5,r7,#29
+ lsrs r6,#3
+ adcs r6,r5                    @ r4 Q57 with rounding
+ muls32_32_64 r6,r2, r6,r2, r4,r5,r7,r6,r2    @ d4=a3*r4/2 Q89
+@ r4+d4 is correct to 1ULP at Q57, tested on ~9bn cases including all extreme values of r4 for each possible y Q30
+
+ adds r2,#8
+ asrs r2,#5                    @ d4 Q52, rounded to Q53 with spare bit in carry
+
+@ here
+@ r0    y low bits
+@ r1    y Q30
+@ r2    d4 Q52, rounded to Q53
+@ C flag contains d4_b53
+@ r3    a4 Q30
+
+ bcs dq_5
+
+ lsrs r5,r3,#10                @ a4 Q52
+ lsls r4,r3,#22
+
+ asrs r1,r2,#31
+ adds r0,r2,r4
+ adcs r1,r5                    @ a4+d4
+
+ add r1,r12                    @ pack exponent
+ pop {r4-r7,r15}
+
+.ltorg
+
+
+@ round(sqrt(2^22./[68:8:252]))
+drsqrtapp:
+.byte 0xf8,0xeb,0xdf,0xd6,0xcd,0xc5,0xbe,0xb8
+.byte 0xb2,0xad,0xa8,0xa4,0xa0,0x9c,0x99,0x95
+.byte 0x92,0x8f,0x8d,0x8a,0x88,0x85,0x83,0x81
+
+dq_5:
+@ here we are near a rounding boundary, C is set
+ adcs r2,r2,r2                 @ d4 Q53+1ulp
+ lsrs r5,r3,#9
+ lsls r4,r3,#23                @ r4:r5 a4 Q53
+ asrs r1,r2,#31
+ adds r4,r2,r4
+ adcs r5,r1                    @ r4:r5 a5=a4+d4 Q53+1ulp
+ movs r3,r5
+ muls r3,r4
+ square32_64 r4,r1,r2,r6,r2,r7
+ adds r2,r3
+ adds r2,r3                    @ r1:r2 a5^2 Q106
+ lsls r0,#22                   @ y Q84
+
+ rsbs r1,#0
+ sbcs r0,r2                    @ remainder y-a5^2
+ bmi 1f                        @ y<a5^2: no need to increment a5
+ movs r3,#0
+ adds r4,#1
+ adcs r5,r3                    @ bump a5 if over rounding boundary
+1:
+ lsrs r0,r4,#1
+ lsrs r1,r5,#1
+ lsls r5,#31
+ orrs r0,r5
+ add r1,r12
+ pop {r4-r7,r15}
+
+@ "scientific" functions start here
+
+@ double-length CORDIC rotation step
+
+@ r0:r1   ω
+@ r6      32-i (complementary shift)
+@ r7      i (shift)
+@ r8:r9   x
+@ r10:r11 y
+@ r12     coefficient pointer
+
+@ an option in rotation mode would be to compute the sequence of σ values
+@ in one pass, rotate the initial vector by the residual ω and then run a
+@ second pass to compute the final x and y. This would relieve pressure
+@ on registers and hence possibly be faster. The same trick does not work
+@ in vectoring mode (but perhaps one could work to single precision in
+@ a first pass and then double precision in a second pass?).
+
+double_section dcordic_vec_step
+ regular_func dcordic_vec_step
+ mov r2,r12
+ ldmia r2!,{r3,r4}
+ mov r12,r2
+ mov r2,r11
+ cmp r2,#0
+ blt 1f
+ b 2f
+
+double_section dcordic_rot_step
+ regular_func dcordic_rot_step
+ mov r2,r12
+ ldmia r2!,{r3,r4}
+ mov r12,r2
+ cmp r1,#0
+ bge 1f
+2:
+@ ω<0 / y>=0
+@ ω+=dω
+@ x+=y>>i, y-=x>>i
+ adds r0,r3
+ adcs r1,r4
+
+ mov r3,r11
+ asrs r3,r7
+ mov r4,r11
+ lsls r4,r6
+ mov r2,r10
+ lsrs r2,r7
+ orrs r2,r4                    @ r2:r3 y>>i, rounding in carry
+ mov r4,r8
+ mov r5,r9                     @ r4:r5 x
+ adcs r2,r4
+ adcs r3,r5                    @ r2:r3 x+(y>>i)
+ mov r8,r2
+ mov r9,r3
+
+ mov r3,r5
+ lsls r3,r6
+ asrs r5,r7
+ lsrs r4,r7
+ orrs r4,r3                    @ r4:r5 x>>i, rounding in carry
+ mov r2,r10
+ mov r3,r11
+ sbcs r2,r4
+ sbcs r3,r5                    @ r2:r3 y-(x>>i)
+ mov r10,r2
+ mov r11,r3
+ bx r14
+
+
+@ ω>0 / y<0
+@ ω-=dω
+@ x-=y>>i, y+=x>>i
+1:
+ subs r0,r3
+ sbcs r1,r4
+
+ mov r3,r9
+ asrs r3,r7
+ mov r4,r9
+ lsls r4,r6
+ mov r2,r8
+ lsrs r2,r7
+ orrs r2,r4                    @ r2:r3 x>>i, rounding in carry
+ mov r4,r10
+ mov r5,r11                    @ r4:r5 y
+ adcs r2,r4
+ adcs r3,r5                    @ r2:r3 y+(x>>i)
+ mov r10,r2
+ mov r11,r3
+
+ mov r3,r5
+ lsls r3,r6
+ asrs r5,r7
+ lsrs r4,r7
+ orrs r4,r3                    @ r4:r5 y>>i, rounding in carry
+ mov r2,r8
+ mov r3,r9
+ sbcs r2,r4
+ sbcs r3,r5                    @ r2:r3 x-(y>>i)
+ mov r8,r2
+ mov r9,r3
+ bx r14
+
+@ convert packed double in r0:r1 to signed/unsigned 32/64-bit integer/fixed-point value in r0:r1 [with r2 places after point], with rounding towards -Inf
+@ fixed-point versions only work with reasonable values in r2 because of the way dunpacks works
+
+double_section double2int_shim
+ regular_func double2int_shim
+ movs r2,#0                    @ and fall through
+regular_func double2fix_shim
+ push {r14}
+ adds r2,#32
+ bl double2fix64_shim
+ movs r0,r1
+ pop {r15}
+
+double_section double2uint_shim
+ regular_func double2uint_shim
+ movs r2,#0                    @ and fall through
+regular_func double2ufix_shim
+ push {r14}
+ adds r2,#32
+ bl double2ufix64_shim
+ movs r0,r1
+ pop {r15}
+
+double_section double2int64_shim
+ regular_func double2int64_shim
+ movs r2,#0                    @ and fall through
+regular_func double2fix64_shim
+ push {r14}
+ bl d2fix
+
+ asrs r2,r1,#31
+ cmp r2,r3
+ bne 1f                        @ sign extension bits fail to match sign of result?
+ pop {r15}
+1:
+ mvns r0,r3
+ movs r1,#1
+ lsls r1,#31
+ eors r1,r1,r0                 @ generate extreme fixed-point values
+ pop {r15}
+
+double_section double2uint64_shim 
+ regular_func double2uint64_shim
+ movs r2,#0                    @ and fall through
+regular_func double2ufix64_shim
+ asrs r3,r1,#20                @ negative? return 0
+ bmi ret_dzero
+@ and fall through
+
+@ convert double in r0:r1 to signed fixed point in r0:r1:r3, r2 places after point, rounding towards -Inf
+@ result clamped so that r3 can only be 0 or -1
+@ trashes r12
+.thumb_func
+d2fix:
+ push {r4,r14}
+ mov r12,r2
+ bl dunpacks
+ asrs r4,r2,#16
+ adds r4,#1
+ bge 1f
+ movs r1,#0                    @ -0 -> +0
+1:
+ asrs r3,r1,#31
+ ldr r4, =d2fix_a
+ bx r4
+ 
+ret_dzero:
+ movs r0,#0
+ movs r1,#0
+ bx r14
+ 
+.weak d2fix_a // weak because it exists in float code too
+regular_func d2fix_a
+@ here
+@ r0:r1 two's complement mantissa
+@ r2    unbaised exponent
+@ r3    mantissa sign extension bits
+ add r2,r12                    @ exponent plus offset for required binary point position
+ subs r2,#52                   @ required shift
+ bmi 1f                        @ shift down?
+@ here a shift up by r2 places
+ cmp r2,#12                    @ will clamp?
+ bge 2f
+ movs r4,r0
+ lsls r1,r2
+ lsls r0,r2
+ rsbs r2,#0
+ adds r2,#32                   @ complementary shift
+ lsrs r4,r2
+ orrs r1,r4
+ pop {r4,r15}
+2:
+ mvns r0,r3
+ mvns r1,r3                    @ overflow: clamp to extreme fixed-point values
+ pop {r4,r15}
+1:
+@ here a shift down by -r2 places
+ adds r2,#32
+ bmi 1f                        @ long shift?
+ mov r4,r1
+ lsls r4,r2
+ rsbs r2,#0
+ adds r2,#32                   @ complementary shift
+ asrs r1,r2
+ lsrs r0,r2
+ orrs r0,r4
+ pop {r4,r15}
+1:
+@ here a long shift down
+ movs r0,r1
+ asrs r1,#31                   @ shift down 32 places
+ adds r2,#32
+ bmi 1f                        @ very long shift?
+ rsbs r2,#0
+ adds r2,#32
+ asrs r0,r2
+ pop {r4,r15}
+1:
+ movs r0,r3                    @ result very near zero: use sign extension bits
+ movs r1,r3
+ pop {r4,r15}
+
+double_section double2float_shim
+ regular_func double2float_shim
+ lsls r2,r1,#1
+ lsrs r2,#21                   @ exponent
+ ldr r3,=#0x3ff-0x7f
+ subs r2,r3                    @ fix exponent bias
+ ble 1f                        @ underflow or zero
+ cmp r2,#0xff
+ bge 2f                        @ overflow or infinity
+ lsls r2,#23                   @ position exponent of result
+ lsrs r3,r1,#31
+ lsls r3,#31
+ orrs r2,r3                    @ insert sign
+ lsls r3,r0,#3                 @ rounding bits
+ lsrs r0,#29
+ lsls r1,#12
+ lsrs r1,#9
+ orrs r0,r1                    @ assemble mantissa
+ orrs r0,r2                    @ insert exponent and sign
+ lsls r3,#1
+ bcc 3f                        @ no rounding
+ beq 4f                        @ all sticky bits 0?
+5:
+ adds r0,#1
+3:
+ bx r14
+4:
+ lsrs r3,r0,#1                 @ odd? then round up
+ bcs 5b
+ bx r14
+1:
+ beq 6f                        @ check case where value is just less than smallest normal
+7:
+ lsrs r0,r1,#31
+ lsls r0,#31
+ bx r14
+6:
+ lsls r2,r1,#12                @ 20 1:s at top of mantissa?
+ asrs r2,#12
+ adds r2,#1
+ bne 7b
+ lsrs r2,r0,#29                @ and 3 more 1:s?
+ cmp r2,#7
+ bne 7b
+ movs r2,#1                    @ return smallest normal with correct sign
+ b 8f
+2:
+ movs r2,#0xff
+8:
+ lsrs r0,r1,#31                @ return signed infinity
+ lsls r0,#8
+ adds r0,r2
+ lsls r0,#23
+ bx r14
+
+double_section x2double_shims
+@ convert signed/unsigned 32/64-bit integer/fixed-point value in r0:r1 [with r2 places after point] to packed double in r0:r1, with rounding
+
+.align 2
+regular_func uint2double_shim
+ movs r1,#0                    @ and fall through
+regular_func ufix2double_shim
+ movs r2,r1
+ movs r1,#0
+ b ufix642double_shim
+
+.align 2
+regular_func int2double_shim
+ movs r1,#0                    @ and fall through
+regular_func fix2double_shim
+ movs r2,r1
+ asrs r1,r0,#31                @ sign extend
+ b fix642double_shim
+
+.align 2
+regular_func uint642double_shim
+ movs r2,#0                    @ and fall through
+regular_func ufix642double_shim
+ movs r3,#0
+ b uf2d
+
+.align 2
+regular_func int642double_shim
+ movs r2,#0                    @ and fall through
+regular_func fix642double_shim
+ asrs r3,r1,#31                @ sign bit across all bits
+ eors r0,r3
+ eors r1,r3
+ subs r0,r3
+ sbcs r1,r3
+uf2d:
+ push {r4,r5,r14}
+ ldr r4,=#0x432
+ subs r2,r4,r2                 @ form biased exponent
+@ here
+@ r0:r1 unnormalised mantissa
+@ r2 -Q (will become exponent)
+@ r3 sign across all bits
+ cmp r1,#0
+ bne 1f                        @ short normalising shift?
+ movs r1,r0
+ beq 2f                        @ zero? return it
+ movs r0,#0
+ subs r2,#32                   @ fix exponent
+1:
+ asrs r4,r1,#21
+ bne 3f                        @ will need shift down (and rounding?)
+ bcs 4f                        @ normalised already?
+5:
+ subs r2,#1
+ adds r0,r0                    @ shift up
+ adcs r1,r1
+ lsrs r4,r1,#21
+ bcc 5b
+4:
+ ldr r4,=#0x7fe
+ cmp r2,r4
+ bhs 6f                        @ over/underflow? return signed zero/infinity
+7:
+ lsls r2,#20                   @ pack and return
+ adds r1,r2
+ lsls r3,#31
+ adds r1,r3
+2:
+ pop {r4,r5,r15}
+6:                             @ return signed zero/infinity according to unclamped exponent in r2
+ mvns r2,r2
+ lsrs r2,#21
+ movs r0,#0
+ movs r1,#0
+ b 7b
+
+3:
+@ here we need to shift down to normalise and possibly round
+ bmi 1f                        @ already normalised to Q63?
+2:
+ subs r2,#1
+ adds r0,r0                    @ shift up
+ adcs r1,r1
+ bpl 2b
+1:
+@ here we have a 1 in b63 of r0:r1
+ adds r2,#11                   @ correct exponent for subsequent shift down
+ lsls r4,r0,#21                @ save bits for rounding
+ lsrs r0,#11
+ lsls r5,r1,#21
+ orrs r0,r5
+ lsrs r1,#11
+ lsls r4,#1
+ beq 1f                        @ sticky bits are zero?
+8:
+ movs r4,#0
+ adcs r0,r4
+ adcs r1,r4
+ b 4b
+1:
+ bcc 4b                        @ sticky bits are zero but not on rounding boundary
+ lsrs r4,r0,#1                 @ increment if odd (force round to even)
+ b 8b
+
+
+.ltorg
+
+double_section dunpacks
+ regular_func dunpacks
+ mdunpacks r0,r1,r2,r3,r4
+ ldr r3,=#0x3ff
+ subs r2,r3                    @ exponent without offset
+ bx r14
+
+@ r0:r1  signed mantissa Q52
+@ r2     unbiased exponent < 10 (i.e., |x|<2^10)
+@ r4     pointer to:
+@          - divisor reciprocal approximation r=1/d Q15
+@          - divisor d Q62  0..20
+@          - divisor d Q62 21..41
+@          - divisor d Q62 42..62
+@ returns:
+@ r0:r1  reduced result y Q62, -0.6 d < y < 0.6 d (better in practice)
+@ r2     quotient q (number of reductions)
+@ if exponent >=10, returns r0:r1=0, r2=1024*mantissa sign
+@ designed to work for 0.5<d<2, in particular d=ln2 (~0.7) and d=π/2 (~1.6)
+double_section dreduce
+ regular_func dreduce
+ adds r2,#2                    @ e+2
+ bmi 1f                        @ |x|<0.25, too small to need adjustment
+ cmp r2,#12
+ bge 4f
+2:
+ movs r5,#17
+ subs r5,r2                    @ 15-e
+ movs r3,r1                    @ Q20
+ asrs r3,r5                    @ x Q5
+ adds r2,#8                    @ e+10
+ adds r5,#7                    @ 22-e = 32-(e+10)
+ movs r6,r0
+ lsrs r6,r5
+ lsls r0,r2
+ lsls r1,r2
+ orrs r1,r6                    @ r0:r1 x Q62
+ ldmia r4,{r4-r7}
+ muls r3,r4                    @ rx Q20
+ asrs r2,r3,#20
+ movs r3,#0
+ adcs r2,r3                    @ rx Q0 rounded = q; for e.g. r=1.5 |q|<1.5*2^10
+ muls r5,r2                    @ qd in pieces: L Q62
+ muls r6,r2                    @               M Q41
+ muls r7,r2                    @               H Q20
+ lsls r7,#10
+ asrs r4,r6,#11
+ lsls r6,#21
+ adds r6,r5
+ adcs r7,r4
+ asrs r5,#31
+ adds r7,r5                    @ r6:r7 qd Q62
+ subs r0,r6
+ sbcs r1,r7                    @ remainder Q62
+ bx r14
+4:
+ movs r2,#12                   @ overflow: clamp to +/-1024
+ movs r0,#0
+ asrs r1,#31
+ lsls r1,#1
+ adds r1,#1
+ lsls r1,#20
+ b 2b
+
+1:
+ lsls r1,#8
+ lsrs r3,r0,#24
+ orrs r1,r3
+ lsls r0,#8                    @ r0:r1 Q60, to be shifted down -r2 places
+ rsbs r3,r2,#0
+ adds r2,#32                   @ shift down in r3, complementary shift in r2
+ bmi 1f                        @ long shift?
+2:
+ movs r4,r1
+ asrs r1,r3
+ lsls r4,r2
+ lsrs r0,r3
+ orrs r0,r4
+ movs r2,#0                    @ rounding
+ adcs r0,r2
+ adcs r1,r2
+ bx r14
+
+1:
+ movs r0,r1                    @ down 32 places
+ asrs r1,#31
+ subs r3,#32
+ adds r2,#32
+ bpl 2b
+ movs r0,#0                    @ very long shift? return 0
+ movs r1,#0
+ movs r2,#0
+ bx r14
+
+double_section dtan_shim
+ regular_func dtan_shim
+ push {r4-r7,r14}
+ bl push_r8_r11
+ bl dsincos_internal
+ mov r12,r0                    @ save ε
+ bl dcos_finish
+ push {r0,r1}
+ mov r0,r12
+ bl dsin_finish
+ pop {r2,r3}
+ bl pop_r8_r11
+ b ddiv0                       @ compute sin θ/cos θ
+
+double_section dcos_shim
+ regular_func dcos_shim
+ push {r4-r7,r14}
+ bl push_r8_r11
+ bl dsincos_internal
+ bl dcos_finish
+ b 1f
+
+double_section dsin_shim
+ regular_func dsin_shim
+ push {r4-r7,r14}
+ bl push_r8_r11
+ bl dsincos_internal
+ bl dsin_finish
+1:
+ bl pop_r8_r11
+ pop {r4-r7,r15}
+
+double_section dsincos_shim
+
+ @ Note that this function returns in r0-r3
+ regular_func dsincos_shim
+
+ push {r4-r7,r14}
+ bl push_r8_r11
+ bl dsincos_internal
+ mov r12,r0                    @ save ε
+ bl dcos_finish
+ push {r0,r1}
+ mov r0,r12
+ bl dsin_finish
+ pop {r2,r3}
+ bl pop_r8_r11
+ pop {r4-r7,r15}
+
+double_section dtrig_guts
+
+@ unpack double θ in r0:r1, range reduce and calculate ε, cos α and sin α such that
+@ θ=α+ε and |ε|≤2^-32
+@ on return:
+@ r0:r1   ε (residual ω, where θ=α+ε) Q62, |ε|≤2^-32 (so fits in r0)
+@ r8:r9   cos α Q62
+@ r10:r11 sin α Q62
+.align 2
+.thumb_func
+dsincos_internal:
+ push {r14}
+ bl dunpacks
+ adr r4,dreddata0
+ bl dreduce
+
+ movs r4,#0
+ ldr r5,=#0x9df04dbb           @ this value compensates for the non-unity scaling of the CORDIC rotations
+ ldr r6,=#0x36f656c5
+ lsls r2,#31
+ bcc 1f
+@ quadrant 2 or 3
+ mvns r6,r6
+ rsbs r5,r5,#0
+ adcs r6,r4
+1:
+ lsls r2,#1
+ bcs 1f
+@ even quadrant
+ mov r10,r4
+ mov r11,r4
+ mov r8,r5
+ mov r9,r6
+ b 2f
+1:
+@ odd quadrant
+ mov r8,r4
+ mov r9,r4
+ mov r10,r5
+ mov r11,r6
+2:
+ adr r4,dtab_cc
+ mov r12,r4
+ movs r7,#1
+ movs r6,#31
+1:
+ bl dcordic_rot_step
+ adds r7,#1
+ subs r6,#1
+ cmp r7,#33
+ bne 1b
+ pop {r15}
+
+dcos_finish:
+@ here
+@ r0:r1   ε (residual ω, where θ=α+ε) Q62, |ε|≤2^-32 (so fits in r0)
+@ r8:r9   cos α Q62
+@ r10:r11 sin α Q62
+@ and we wish to calculate cos θ=cos(α+ε)~cos α - ε sin α
+ mov r1,r11
+@ mov r2,r10
+@ lsrs r2,#31
+@ adds r1,r2                    @ rounding improves accuracy very slightly
+ muls32_s32_64 r0,r1, r2,r3, r4,r5,r6,r2,r3
+@ r2:r3   ε sin α Q(62+62-32)=Q92
+ mov r0,r8
+ mov r1,r9
+ lsls r5,r3,#2
+ asrs r3,r3,#30
+ lsrs r2,r2,#30
+ orrs r2,r5
+ sbcs r0,r2                    @ include rounding
+ sbcs r1,r3
+ movs r2,#62
+ b fix642double_shim
+
+dsin_finish:
+@ here
+@ r0:r1   ε (residual ω, where θ=α+ε) Q62, |ε|≤2^-32 (so fits in r0)
+@ r8:r9   cos α Q62
+@ r10:r11 sin α Q62
+@ and we wish to calculate sin θ=sin(α+ε)~sin α + ε cos α
+ mov r1,r9
+ muls32_s32_64 r0,r1, r2,r3, r4,r5,r6,r2,r3
+@ r2:r3   ε cos α Q(62+62-32)=Q92
+ mov r0,r10
+ mov r1,r11
+ lsls r5,r3,#2
+ asrs r3,r3,#30
+ lsrs r2,r2,#30
+ orrs r2,r5
+ adcs r0,r2                    @ include rounding
+ adcs r1,r3
+ movs r2,#62
+ b fix642double_shim
+
+.ltorg
+.align 2
+dreddata0:
+.word 0x0000517d               @ 2/π Q15
+.word 0x0014611A               @ π/2 Q62=6487ED5110B4611A split into 21-bit pieces
+.word 0x000A8885
+.word 0x001921FB
+
+
+.align 2
+regular_func datan2_shim
+@ r0:r1 y
+@ r2:r3 x
+ push {r4-r7,r14}
+ bl push_r8_r11
+ ldr r5,=#0x7ff00000
+ movs r4,r1
+ ands r4,r5                    @ y==0?
+ beq 1f
+ cmp r4,r5                     @ or Inf/NaN?
+ bne 2f
+1:
+ lsrs r1,#20                   @ flush
+ lsls r1,#20
+ movs r0,#0
+2:
+ movs r4,r3
+ ands r4,r5                    @ x==0?
+ beq 1f
+ cmp r4,r5                     @ or Inf/NaN?
+ bne 2f
+1:
+ lsrs r3,#20                   @ flush
+ lsls r3,#20
+ movs r2,#0
+2:
+ movs r6,#0                    @ quadrant offset
+ lsls r5,#11                   @ constant 0x80000000
+ cmp r3,#0
+ bpl 1f                        @ skip if x positive
+ movs r6,#2
+ eors r3,r5
+ eors r1,r5
+ bmi 1f                        @ quadrant offset=+2 if y was positive
+ rsbs r6,#0                    @ quadrant offset=-2 if y was negative
+1:
+@ now in quadrant 0 or 3
+ adds r7,r1,r5                 @ r7=-r1
+ bpl 1f
+@ y>=0: in quadrant 0
+ cmp r1,r3
+ ble 2f                        @ y<~x so 0≤θ<~π/4: skip
+ adds r6,#1
+ eors r1,r5                    @ negate x
+ b 3f                          @ and exchange x and y = rotate by -π/2
+1:
+ cmp r3,r7
+ bge 2f                        @ -y<~x so -π/4<~θ≤0: skip
+ subs r6,#1
+ eors r3,r5                    @ negate y and ...
+3:
+ movs r7,r0                    @ exchange x and y
+ movs r0,r2
+ movs r2,r7
+ movs r7,r1
+ movs r1,r3
+ movs r3,r7
+2:
+@ here -π/4<~θ<~π/4
+@ r6 has quadrant offset
+ push {r6}
+ cmp r2,#0
+ bne 1f
+ cmp r3,#0
+ beq 10f                       @ x==0 going into division?
+ lsls r4,r3,#1
+ asrs r4,#21
+ adds r4,#1
+ bne 1f                        @ x==Inf going into division?
+ lsls r4,r1,#1
+ asrs r4,#21
+ adds r4,#1                    @ y also ±Inf?
+ bne 10f
+ subs r1,#1                    @ make them both just finite
+ subs r3,#1
+ b 1f
+
+10:
+ movs r0,#0
+ movs r1,#0
+ b 12f
+
+1:
+ bl ddiv_shim
+ movs r2,#62
+ bl double2fix64_shim
+@ r0:r1 y/x
+ mov r10,r0
+ mov r11,r1
+ movs r0,#0                    @ ω=0
+ movs r1,#0
+ mov r8,r0
+ movs r2,#1
+ lsls r2,#30
+ mov r9,r2                     @ x=1
+
+ adr r4,dtab_cc
+ mov r12,r4
+ movs r7,#1
+ movs r6,#31
+1:
+ bl dcordic_vec_step
+ adds r7,#1
+ subs r6,#1
+ cmp r7,#33
+ bne 1b
+@ r0:r1   atan(y/x) Q62
+@ r8:r9   x residual Q62
+@ r10:r11 y residual Q62
+ mov r2,r9
+ mov r3,r10
+ subs r2,#12                   @ this makes atan(0)==0
+@ the following is basically a division residual y/x ~ atan(residual y/x)
+ movs r4,#1
+ lsls r4,#29
+ movs r7,#0
+2:
+ lsrs r2,#1
+ movs r3,r3                    @ preserve carry
+ bmi 1f
+ sbcs r3,r2
+ adds r0,r4
+ adcs r1,r7
+ lsrs r4,#1
+ bne 2b
+ b 3f
+1:
+ adcs r3,r2
+ subs r0,r4
+ sbcs r1,r7
+ lsrs r4,#1
+ bne 2b
+3:
+ lsls r6,r1,#31
+ asrs r1,#1
+ lsrs r0,#1
+ orrs r0,r6                    @ Q61
+
+12:
+ pop {r6}
+
+ cmp r6,#0
+ beq 1f
+ ldr r4,=#0x885A308D           @ π/2 Q61
+ ldr r5,=#0x3243F6A8
+ bpl 2f
+ mvns r4,r4                    @ negative quadrant offset
+ mvns r5,r5
+2:
+ lsls r6,#31
+ bne 2f                        @ skip if quadrant offset is ±1
+ adds r0,r4
+ adcs r1,r5
+2:
+ adds r0,r4
+ adcs r1,r5
+1:
+ movs r2,#61
+ bl fix642double_shim
+
+ bl pop_r8_r11
+ pop {r4-r7,r15}
+
+.ltorg
+
+dtab_cc:
+.word 0x61bb4f69, 0x1dac6705   @ atan 2^-1 Q62
+.word 0x96406eb1, 0x0fadbafc   @ atan 2^-2 Q62
+.word 0xab0bdb72, 0x07f56ea6   @ atan 2^-3 Q62
+.word 0xe59fbd39, 0x03feab76   @ atan 2^-4 Q62
+.word 0xba97624b, 0x01ffd55b   @ atan 2^-5 Q62
+.word 0xdddb94d6, 0x00fffaaa   @ atan 2^-6 Q62
+.word 0x56eeea5d, 0x007fff55   @ atan 2^-7 Q62
+.word 0xaab7776e, 0x003fffea   @ atan 2^-8 Q62
+.word 0x5555bbbc, 0x001ffffd   @ atan 2^-9 Q62
+.word 0xaaaaadde, 0x000fffff   @ atan 2^-10 Q62
+.word 0xf555556f, 0x0007ffff   @ atan 2^-11 Q62
+.word 0xfeaaaaab, 0x0003ffff   @ atan 2^-12 Q62
+.word 0xffd55555, 0x0001ffff   @ atan 2^-13 Q62
+.word 0xfffaaaab, 0x0000ffff   @ atan 2^-14 Q62
+.word 0xffff5555, 0x00007fff   @ atan 2^-15 Q62
+.word 0xffffeaab, 0x00003fff   @ atan 2^-16 Q62
+.word 0xfffffd55, 0x00001fff   @ atan 2^-17 Q62
+.word 0xffffffab, 0x00000fff   @ atan 2^-18 Q62
+.word 0xfffffff5, 0x000007ff   @ atan 2^-19 Q62
+.word 0xffffffff, 0x000003ff   @ atan 2^-20 Q62
+.word 0x00000000, 0x00000200   @ atan 2^-21 Q62 @ consider optimising these
+.word 0x00000000, 0x00000100   @ atan 2^-22 Q62
+.word 0x00000000, 0x00000080   @ atan 2^-23 Q62
+.word 0x00000000, 0x00000040   @ atan 2^-24 Q62
+.word 0x00000000, 0x00000020   @ atan 2^-25 Q62
+.word 0x00000000, 0x00000010   @ atan 2^-26 Q62
+.word 0x00000000, 0x00000008   @ atan 2^-27 Q62
+.word 0x00000000, 0x00000004   @ atan 2^-28 Q62
+.word 0x00000000, 0x00000002   @ atan 2^-29 Q62
+.word 0x00000000, 0x00000001   @ atan 2^-30 Q62
+.word 0x80000000, 0x00000000   @ atan 2^-31 Q62
+.word 0x40000000, 0x00000000   @ atan 2^-32 Q62
+
+double_section dexp_guts
+regular_func dexp_shim
+ push {r4-r7,r14}
+ bl dunpacks
+ adr r4,dreddata1
+ bl dreduce
+ cmp r1,#0
+ bge 1f
+ ldr r4,=#0xF473DE6B
+ ldr r5,=#0x2C5C85FD           @ ln2 Q62
+ adds r0,r4
+ adcs r1,r5
+ subs r2,#1
+1:
+ push {r2}
+ movs r7,#1                    @ shift
+ adr r6,dtab_exp
+ movs r2,#0
+ movs r3,#1
+ lsls r3,#30                   @ x=1 Q62
+
+3:
+ ldmia r6!,{r4,r5}
+ mov r12,r6
+ subs r0,r4
+ sbcs r1,r5
+ bmi 1f
+
+ rsbs r6,r7,#0
+ adds r6,#32                   @ complementary shift
+ movs r5,r3
+ asrs r5,r7
+ movs r4,r3
+ lsls r4,r6
+ movs r6,r2
+ lsrs r6,r7                    @ rounding bit in carry
+ orrs r4,r6
+ adcs r2,r4
+ adcs r3,r5                    @ x+=x>>i
+ b 2f
+
+1:
+ adds r0,r4                    @ restore argument
+ adcs r1,r5
+2:
+ mov r6,r12
+ adds r7,#1
+ cmp r7,#33
+ bne 3b
+
+@ here
+@ r0:r1   ε (residual x, where x=a+ε) Q62, |ε|≤2^-32 (so fits in r0)
+@ r2:r3   exp a Q62
+@ and we wish to calculate exp x=exp a exp ε~(exp a)(1+ε)
+ muls32_32_64 r0,r3, r4,r1, r5,r6,r7,r4,r1
+@ r4:r1 ε exp a Q(62+62-32)=Q92
+ lsrs r4,#30
+ lsls r0,r1,#2
+ orrs r0,r4
+ asrs r1,#30
+ adds r0,r2
+ adcs r1,r3
+
+ pop {r2}
+ rsbs r2,#0
+ adds r2,#62
+ bl fix642double_shim                 @ in principle we can pack faster than this because we know the exponent
+ pop {r4-r7,r15}
+
+.ltorg
+
+.align 2
+regular_func dln_shim
+ push {r4-r7,r14}
+ lsls r7,r1,#1
+ bcs 5f                        @ <0 ...
+ asrs r7,#21
+ beq 5f                        @ ... or =0? return -Inf
+ adds r7,#1
+ beq 6f                        @ Inf/NaN? return +Inf
+ bl dunpacks
+ push {r2}
+ lsls r1,#9
+ lsrs r2,r0,#23
+ orrs r1,r2
+ lsls r0,#9
+@ r0:r1 m Q61 = m/2 Q62 0.5≤m/2<1
+
+ movs r7,#1                    @ shift
+ adr r6,dtab_exp
+ mov r12,r6
+ movs r2,#0
+ movs r3,#0                    @ y=0 Q62
+
+3:
+ rsbs r6,r7,#0
+ adds r6,#32                   @ complementary shift
+ movs r5,r1
+ asrs r5,r7
+ movs r4,r1
+ lsls r4,r6
+ movs r6,r0
+ lsrs r6,r7
+ orrs r4,r6                    @ x>>i, rounding bit in carry
+ adcs r4,r0
+ adcs r5,r1                    @ x+(x>>i)
+
+ lsrs r6,r5,#30
+ bne 1f                        @ x+(x>>i)>1?
+ movs r0,r4
+ movs r1,r5                    @ x+=x>>i
+ mov r6,r12
+ ldmia r6!,{r4,r5}
+ subs r2,r4
+ sbcs r3,r5
+
+1:
+ movs r4,#8
+ add r12,r4
+ adds r7,#1
+ cmp r7,#33
+ bne 3b
+@ here:
+@ r0:r1 residual x, nearly 1 Q62
+@ r2:r3 y ~ ln m/2 = ln m - ln2 Q62
+@ result is y + ln2 + ln x ~ y + ln2 + (x-1)
+ lsls r1,#2
+ asrs r1,#2                    @ x-1
+ adds r2,r0
+ adcs r3,r1
+
+ pop {r7}
+@ here:
+@ r2:r3 ln m/2 = ln m - ln2 Q62
+@ r7    unbiased exponent
+
+ adr r4,dreddata1+4
+ ldmia r4,{r0,r1,r4}
+ adds r7,#1
+ muls r0,r7                    @ Q62
+ muls r1,r7                    @ Q41
+ muls r4,r7                    @ Q20
+ lsls r7,r1,#21
+ asrs r1,#11
+ asrs r5,r1,#31
+ adds r0,r7
+ adcs r1,r5
+ lsls r7,r4,#10
+ asrs r4,#22
+ asrs r5,r1,#31
+ adds r1,r7
+ adcs r4,r5
+@ r0:r1:r4 exponent*ln2 Q62
+ asrs r5,r3,#31
+ adds r0,r2
+ adcs r1,r3
+ adcs r4,r5
+@ r0:r1:r4 result Q62
+ movs r2,#62
+1:
+ asrs r5,r1,#31
+ cmp r4,r5
+ beq 2f                        @ r4 a sign extension of r1?
+ lsrs r0,#4                    @ no: shift down 4 places and try again
+ lsls r6,r1,#28
+ orrs r0,r6
+ lsrs r1,#4
+ lsls r6,r4,#28
+ orrs r1,r6
+ asrs r4,#4
+ subs r2,#4
+ b 1b
+2:
+ bl fix642double_shim
+ pop {r4-r7,r15}
+
+5:
+ ldr r1,=#0xfff00000
+ movs r0,#0
+ pop {r4-r7,r15}
+
+6:
+ ldr r1,=#0x7ff00000
+ movs r0,#0
+ pop {r4-r7,r15}
+
+.ltorg
+
+.align 2
+dreddata1:
+.word 0x0000B8AA               @ 1/ln2 Q15
+.word 0x0013DE6B               @ ln2 Q62 Q62=2C5C85FDF473DE6B split into 21-bit pieces
+.word 0x000FEFA3
+.word 0x000B1721
+
+dtab_exp:
+.word 0xbf984bf3, 0x19f323ec   @ log 1+2^-1 Q62
+.word 0xcd4d10d6, 0x0e47fbe3   @ log 1+2^-2 Q62
+.word 0x8abcb97a, 0x0789c1db   @ log 1+2^-3 Q62
+.word 0x022c54cc, 0x03e14618   @ log 1+2^-4 Q62
+.word 0xe7833005, 0x01f829b0   @ log 1+2^-5 Q62
+.word 0x87e01f1e, 0x00fe0545   @ log 1+2^-6 Q62
+.word 0xac419e24, 0x007f80a9   @ log 1+2^-7 Q62
+.word 0x45621781, 0x003fe015   @ log 1+2^-8 Q62
+.word 0xa9ab10e6, 0x001ff802   @ log 1+2^-9 Q62
+.word 0x55455888, 0x000ffe00   @ log 1+2^-10 Q62
+.word 0x0aa9aac4, 0x0007ff80   @ log 1+2^-11 Q62
+.word 0x01554556, 0x0003ffe0   @ log 1+2^-12 Q62
+.word 0x002aa9ab, 0x0001fff8   @ log 1+2^-13 Q62
+.word 0x00055545, 0x0000fffe   @ log 1+2^-14 Q62
+.word 0x8000aaaa, 0x00007fff   @ log 1+2^-15 Q62
+.word 0xe0001555, 0x00003fff   @ log 1+2^-16 Q62
+.word 0xf80002ab, 0x00001fff   @ log 1+2^-17 Q62
+.word 0xfe000055, 0x00000fff   @ log 1+2^-18 Q62
+.word 0xff80000b, 0x000007ff   @ log 1+2^-19 Q62
+.word 0xffe00001, 0x000003ff   @ log 1+2^-20 Q62
+.word 0xfff80000, 0x000001ff   @ log 1+2^-21 Q62
+.word 0xfffe0000, 0x000000ff   @ log 1+2^-22 Q62
+.word 0xffff8000, 0x0000007f   @ log 1+2^-23 Q62
+.word 0xffffe000, 0x0000003f   @ log 1+2^-24 Q62
+.word 0xfffff800, 0x0000001f   @ log 1+2^-25 Q62
+.word 0xfffffe00, 0x0000000f   @ log 1+2^-26 Q62
+.word 0xffffff80, 0x00000007   @ log 1+2^-27 Q62
+.word 0xffffffe0, 0x00000003   @ log 1+2^-28 Q62
+.word 0xfffffff8, 0x00000001   @ log 1+2^-29 Q62
+.word 0xfffffffe, 0x00000000   @ log 1+2^-30 Q62
+.word 0x80000000, 0x00000000   @ log 1+2^-31 Q62
+.word 0x40000000, 0x00000000   @ log 1+2^-32 Q62
+
+
+#endif
diff --git a/src/rp2_common/pico_double/include/pico/double.h b/src/rp2_common/pico_double/include/pico/double.h
new file mode 100644
index 0000000..0893233
--- /dev/null
+++ b/src/rp2_common/pico_double/include/pico/double.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_DOUBLE_H
+#define _PICO_DOUBLE_H
+
+#include <math.h>
+#include "pico/types.h"
+#include "pico/bootrom/sf_table.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file double.h
+*  \defgroup pico_double pico_double
+*
+* Optimized double-precision floating point functions
+*
+* (Replacement) optimized implementations are provided of the following compiler built-ins
+* and math library functions:
+*
+* - __aeabi_dadd, __aeabi_ddiv, __aeabi_dmul, __aeabi_drsub, __aeabi_dsub, __aeabi_cdcmpeq, __aeabi_cdrcmple, __aeabi_cdcmple, __aeabi_dcmpeq, __aeabi_dcmplt, __aeabi_dcmple, __aeabi_dcmpge, __aeabi_dcmpgt, __aeabi_dcmpun, __aeabi_i2d, __aeabi_l2d, __aeabi_ui2d, __aeabi_ul2d, __aeabi_d2iz, __aeabi_d2lz, __aeabi_d2uiz, __aeabi_d2ulz, __aeabi_d2f
+* - sqrt, cos, sin, tan, atan2, exp, log, ldexp, copysign, trunc, floor, ceil, round, asin, acos, atan, sinh, cosh, tanh, asinh, acosh, atanh, exp2, log2, exp10, log10, pow,, hypot, cbrt, fmod, drem, remainder, remquo, expm1, log1p, fma
+* - powint, sincos (GNU extensions)
+*
+* The following additional optimized functions are also provided:
+*
+* - fix2double, ufix2double, fix642double, ufix642double, double2fix, double2ufix, double2fix64, double2ufix64, double2int, double2int64, double2int_z, double2int64_z
+*/
+
+double fix2double(int32_t m, int e);
+double ufix2double(uint32_t m, int e);
+double fix642double(int64_t m, int e);
+double ufix642double(uint64_t m, int e);
+
+// These methods round towards -Infinity.
+int32_t double2fix(double f, int e);
+uint32_t double2ufix(double f, int e);
+int64_t double2fix64(double f, int e);
+uint64_t double2ufix64(double f, int e);
+int32_t double2int(double f);
+int64_t double2int64(double f);
+
+// These methods round towards 0.
+int32_t double2int_z(double f);
+int64_t double2int64_z(double f);
+
+double exp10(double x);
+void sincos(double x, double *sinx, double *cosx);
+double powint(double x, int y);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_fix/CMakeLists.txt b/src/rp2_common/pico_fix/CMakeLists.txt
new file mode 100644
index 0000000..81a9eaa
--- /dev/null
+++ b/src/rp2_common/pico_fix/CMakeLists.txt
@@ -0,0 +1 @@
+pico_add_subdirectory(rp2040_usb_device_enumeration)
\ No newline at end of file
diff --git a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt
new file mode 100644
index 0000000..18fdc28
--- /dev/null
+++ b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt
@@ -0,0 +1,9 @@
+pico_add_impl_library(pico_fix_rp2040_usb_device_enumeration)
+
+target_sources(pico_fix_rp2040_usb_device_enumeration INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/rp2040_usb_device_enumeration.c
+        )
+
+target_include_directories(pico_fix_rp2040_usb_device_enumeration INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+target_link_libraries(pico_fix_rp2040_usb_device_enumeration INTERFACE hardware_structs pico_time)
\ No newline at end of file
diff --git a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/include/pico/fix/rp2040_usb_device_enumeration.h b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/include/pico/fix/rp2040_usb_device_enumeration.h
new file mode 100644
index 0000000..49f115e
--- /dev/null
+++ b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/include/pico/fix/rp2040_usb_device_enumeration.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_FIX_RP2040_USB_DEVICE_ENUMERATION_H
+#define _PICO_FIX_RP2040_USB_DEVICE_ENUMERATION_H
+
+/*! \brief Perform a brute force workaround for USB device enumeration issue
+ * \ingroup pico_fix
+ *
+ * This method should be called during the IRQ handler for a bus reset
+ */
+void rp2040_usb_device_enumeration_fix(void);
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c
new file mode 100644
index 0000000..e1073ca
--- /dev/null
+++ b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+#include "pico/time.h"
+#include "hardware/structs/usb.h"
+#include "hardware/gpio.h"
+#include "hardware/structs/iobank0.h"
+#include "hardware/structs/padsbank0.h"
+#include "pico/fix/rp2040_usb_device_enumeration.h"
+
+#define LS_SE0 0b00
+#define LS_J   0b01
+#define LS_K   0b10
+#define LS_SE1 0b11
+
+static void hw_enumeration_fix_wait_se0(void);
+static void hw_enumeration_fix_force_ls_j(void);
+static void hw_enumeration_fix_finish(void);
+
+void rp2040_usb_device_enumeration_fix(void) {
+#if PICO_RP2040_B0_SUPPORTED || PICO_RP2040_B1_SUPPORTED
+    // Actually check for B0/B1 h/w
+    if (rp2040_chip_version() == 1) {
+        // After coming out of reset, the hardware expects 800us of LS_J (linestate J) time
+        // before it will move to the connected state. However on a hub that broadcasts packets
+        // for other devices this isn't the case. The plan here is to wait for the end of the bus
+        // reset, force an LS_J for 1ms and then switch control back to the USB phy. Unfortunately
+        // this requires us to use GPIO15 as there is no other way to force the input path.
+        // We only need to force DP as DM can be left at zero. It will be gated off by GPIO
+        // logic if it isn't func selected.
+
+        // Wait SE0 phase will call force ls_j phase which will call finish phase
+        hw_enumeration_fix_wait_se0();
+    }
+#endif
+}
+
+static inline uint8_t hw_line_state(void) {
+    return (usb_hw->sie_status & USB_SIE_STATUS_LINE_STATE_BITS) >> USB_SIE_STATUS_LINE_STATE_LSB;
+}
+
+int64_t hw_enumeration_fix_wait_se0_callback(__unused alarm_id_t id, __unused void *user_data) {
+    if (hw_line_state() == LS_SE0) {
+        // Come back in 1ms and check again
+        return 1000;
+    } else {
+        // Now force LS_J (next stage of fix)
+        hw_enumeration_fix_force_ls_j();
+        // No more repeats
+        return 0;
+    }
+}
+
+static inline void hw_enumeration_fix_busy_wait_se0(void) {
+    while (hw_line_state() == LS_SE0) tight_loop_contents();
+    // Now force LS_J (next stage of fix)
+    hw_enumeration_fix_force_ls_j();
+}
+
+static void hw_enumeration_fix_wait_se0(void) {
+    // Wait for SE0 to end (i.e. the host to stop resetting). This reset can last quite long.
+    // 10-15ms so we are going to set a timer callback.
+
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+    if (add_alarm_in_ms(1, hw_enumeration_fix_wait_se0_callback, NULL, true) >= 0) {
+        // hw_enumeration_fix_wait_se0_callback will be called in 1ms to check if se0 has finished
+        // (and will poll every 1ms from there)
+        return;
+    }
+#endif
+    // if timer pool disabled, or no timer available, have to busy wait.
+    hw_enumeration_fix_busy_wait_se0();
+}
+
+int64_t hw_enumeration_fix_force_ls_j_done(__unused alarm_id_t id, __unused void *user_data) {
+    hw_enumeration_fix_finish();
+    return 0;
+}
+
+static uint32_t gpio_ctrl_prev = 0;
+static uint32_t pad_ctrl_prev = 0;
+static const uint dp = 15;
+static const uint dm = 16;
+
+static void hw_enumeration_fix_force_ls_j(void) {
+    // DM must be 0 for this to work. This is true if it is selected
+    // to any other function. fn 8 on this pin is only for debug so shouldn't
+    // be selected
+    if (gpio_get_function(dm) == 8) {
+        panic("Not expecting DM to be function 8");
+    }
+
+    // Before changing any pin state, take a copy of the current gpio control register
+    gpio_ctrl_prev = iobank0_hw->io[dp].ctrl;
+    // Also take a copy of the pads register
+    pad_ctrl_prev = padsbank0_hw->io[dp];
+
+    // Enable bus keep and force pin to tristate, so USB DP muxing doesn't affect
+    // pin state
+    gpio_set_pulls(dp, true, true);
+    gpio_set_oeover(dp, GPIO_OVERRIDE_LOW);
+    // Select function 8 (USB debug muxing) without disturbing other controls
+    hw_write_masked(&iobank0_hw->io[dp].ctrl,
+        8 << IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB, IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS);
+
+    // J state is a differential 1 for a full speed device so
+    // DP = 1 and DM = 0. Don't actually need to set DM low as it
+    // is already gated assuming it isn't funcseld.
+    gpio_set_inover(dp, GPIO_OVERRIDE_HIGH);
+
+    // Force PHY pull up to stay before switching away from the phy
+    hw_set_alias(usb_hw)->phy_direct = USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS;
+    hw_set_alias(usb_hw)->phy_direct_override = USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS;
+
+    // Switch to GPIO phy with LS_J forced
+    usb_hw->muxing = USB_USB_MUXING_TO_DIGITAL_PAD_BITS | USB_USB_MUXING_SOFTCON_BITS;
+
+    // LS_J is now forced but while loop here just to check
+    hard_assert(hw_line_state() == LS_J); // "LS_J not forced!"
+
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+    if (add_alarm_in_ms(1, hw_enumeration_fix_force_ls_j_done, NULL, true) >= 0) {
+        // hw_enumeration_fix_force_ls_j_done will be called in 1ms
+        return;
+    }
+#endif
+    // if timer pool disabled, or no timer available, have to busy wait.
+    busy_wait_us(1000);
+    hw_enumeration_fix_finish();
+}
+
+static void hw_enumeration_fix_finish(void) {
+    // Should think we are connected now
+    while (!(usb_hw->sie_status & USB_SIE_STATUS_CONNECTED_BITS)) tight_loop_contents();
+
+    // Switch back to USB phy
+    usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS;
+
+    // Get rid of DP pullup override
+    hw_clear_alias(usb_hw)->phy_direct_override = USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS;
+
+    // Finally, restore the gpio ctrl value back to GPIO15
+    iobank0_hw->io[dp].ctrl = gpio_ctrl_prev;
+    // Restore the pad ctrl value
+    padsbank0_hw->io[dp] = pad_ctrl_prev;
+}
diff --git a/src/rp2_common/pico_float/CMakeLists.txt b/src/rp2_common/pico_float/CMakeLists.txt
new file mode 100644
index 0000000..3543b03
--- /dev/null
+++ b/src/rp2_common/pico_float/CMakeLists.txt
@@ -0,0 +1,113 @@
+if (NOT TARGET pico_float)
+    # library to be depended on - we make this depend on particular implementations using per target generator expressions
+    pico_add_impl_library(pico_float)
+
+    # no custom implementation; falls thru to compiler
+    pico_add_impl_library(pico_float_compiler)
+
+    add_library(pico_float_headers INTERFACE)
+    target_include_directories(pico_float_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+    # add alias "default" which is just rom.
+    add_library(pico_float_default INTERFACE)
+    target_link_libraries(pico_float_default INTERFACE pico_float_pico)
+
+    set(PICO_DEFAULT_FLOAT_IMPL pico_float_default)
+
+    target_link_libraries(pico_float INTERFACE
+            $<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_FLOAT_IMPL>>,$<TARGET_PROPERTY:PICO_TARGET_FLOAT_IMPL>,${PICO_DEFAULT_FLOAT_IMPL}>)
+
+    pico_add_impl_library(pico_float_pico)
+    target_sources(pico_float_pico INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/float_aeabi.S
+            ${CMAKE_CURRENT_LIST_DIR}/float_init_rom.c
+            ${CMAKE_CURRENT_LIST_DIR}/float_math.c
+            ${CMAKE_CURRENT_LIST_DIR}/float_v1_rom_shim.S
+    )
+
+    target_link_libraries(pico_float_pico INTERFACE pico_bootrom pico_float_headers)
+
+    pico_add_impl_library(pico_float_none)
+    target_sources(pico_float_none INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/float_none.S
+            )
+
+    target_link_libraries(pico_float_none INTERFACE pico_float_headers)
+
+    function(wrap_float_functions TARGET)
+        pico_wrap_function(${TARGET} __aeabi_fadd)
+        pico_wrap_function(${TARGET} __aeabi_fdiv)
+        pico_wrap_function(${TARGET} __aeabi_fmul)
+        pico_wrap_function(${TARGET} __aeabi_frsub)
+        pico_wrap_function(${TARGET} __aeabi_fsub)
+        pico_wrap_function(${TARGET} __aeabi_cfcmpeq)
+        pico_wrap_function(${TARGET} __aeabi_cfrcmple)
+        pico_wrap_function(${TARGET} __aeabi_cfcmple)
+        pico_wrap_function(${TARGET} __aeabi_fcmpeq)
+        pico_wrap_function(${TARGET} __aeabi_fcmplt)
+        pico_wrap_function(${TARGET} __aeabi_fcmple)
+        pico_wrap_function(${TARGET} __aeabi_fcmpge)
+        pico_wrap_function(${TARGET} __aeabi_fcmpgt)
+        pico_wrap_function(${TARGET} __aeabi_fcmpun)
+        pico_wrap_function(${TARGET} __aeabi_i2f)
+        pico_wrap_function(${TARGET} __aeabi_l2f)
+        pico_wrap_function(${TARGET} __aeabi_ui2f)
+        pico_wrap_function(${TARGET} __aeabi_ul2f)
+        pico_wrap_function(${TARGET} __aeabi_f2iz)
+        pico_wrap_function(${TARGET} __aeabi_f2lz)
+        pico_wrap_function(${TARGET} __aeabi_f2uiz)
+        pico_wrap_function(${TARGET} __aeabi_f2ulz)
+        pico_wrap_function(${TARGET} __aeabi_f2d)
+        pico_wrap_function(${TARGET} sqrtf)
+        pico_wrap_function(${TARGET} cosf)
+        pico_wrap_function(${TARGET} sinf)
+        pico_wrap_function(${TARGET} tanf)
+        pico_wrap_function(${TARGET} atan2f)
+        pico_wrap_function(${TARGET} expf)
+        pico_wrap_function(${TARGET} logf)
+
+        pico_wrap_function(${TARGET} ldexpf)
+        pico_wrap_function(${TARGET} copysignf)
+        pico_wrap_function(${TARGET} truncf)
+        pico_wrap_function(${TARGET} floorf)
+        pico_wrap_function(${TARGET} ceilf)
+        pico_wrap_function(${TARGET} roundf)
+        pico_wrap_function(${TARGET} sincosf) # gnu
+        pico_wrap_function(${TARGET} asinf)
+        pico_wrap_function(${TARGET} acosf)
+        pico_wrap_function(${TARGET} atanf)
+        pico_wrap_function(${TARGET} sinhf)
+        pico_wrap_function(${TARGET} coshf)
+        pico_wrap_function(${TARGET} tanhf)
+        pico_wrap_function(${TARGET} asinhf)
+        pico_wrap_function(${TARGET} acoshf)
+        pico_wrap_function(${TARGET} atanhf)
+        pico_wrap_function(${TARGET} exp2f)
+        pico_wrap_function(${TARGET} log2f)
+        pico_wrap_function(${TARGET} exp10f)
+        pico_wrap_function(${TARGET} log10f)
+        pico_wrap_function(${TARGET} powf)
+        pico_wrap_function(${TARGET} powintf) #gnu
+        pico_wrap_function(${TARGET} hypotf)
+        pico_wrap_function(${TARGET} cbrtf)
+        pico_wrap_function(${TARGET} fmodf)
+        pico_wrap_function(${TARGET} dremf)
+        pico_wrap_function(${TARGET} remainderf)
+        pico_wrap_function(${TARGET} remquof)
+        pico_wrap_function(${TARGET} expm1f)
+        pico_wrap_function(${TARGET} log1pf)
+        pico_wrap_function(${TARGET} fmaf)
+    endfunction()
+
+    wrap_float_functions(pico_float_pico)
+    wrap_float_functions(pico_float_none)
+
+    macro(pico_set_float_implementation TARGET IMPL)
+        get_target_property(target_type ${TARGET} TYPE)
+        if ("EXECUTABLE" STREQUAL "${target_type}")
+            set_target_properties(${TARGET} PROPERTIES PICO_TARGET_FLOAT_IMPL "pico_float_${IMPL}")
+        else()
+            message(FATAL_ERROR "float implementation must be set on executable not library")
+        endif()
+    endmacro()
+endif()
diff --git a/src/rp2_common/pico_float/float_aeabi.S b/src/rp2_common/pico_float/float_aeabi.S
new file mode 100644
index 0000000..db393df
--- /dev/null
+++ b/src/rp2_common/pico_float/float_aeabi.S
@@ -0,0 +1,771 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/asm_helper.S"
+#include "pico/bootrom/sf_table.h"
+#include "hardware/divider_helper.S"
+
+__pre_init __aeabi_float_init, 00020
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.macro float_section name
+#if PICO_FLOAT_IN_RAM
+.section RAM_SECTION_NAME(\name), "ax"
+#else
+.section SECTION_NAME(\name), "ax"
+#endif
+.endm
+
+.macro float_wrapper_section func
+float_section WRAPPER_FUNC_NAME(\func)
+.endm
+
+.macro _float_wrapper_func x
+    wrapper_func \x
+.endm
+
+.macro wrapper_func_f1 x
+   _float_wrapper_func \x
+#if PICO_FLOAT_PROPAGATE_NANS
+    mov ip, lr
+    bl __check_nan_f1
+    mov lr, ip
+#endif
+.endm
+
+.macro wrapper_func_f2 x
+   _float_wrapper_func \x
+#if PICO_FLOAT_PROPAGATE_NANS
+    mov ip, lr
+    bl __check_nan_f2
+    mov lr, ip
+#endif
+.endm
+
+.section .text
+
+#if PICO_FLOAT_PROPAGATE_NANS
+.thumb_func
+__check_nan_f1:
+   movs r3, #1
+   lsls r3, #24
+   lsls r2, r0, #1
+   adds r2, r3
+   bhi 1f
+   bx lr
+1:
+   bx ip
+
+.thumb_func
+__check_nan_f2:
+   movs r3, #1
+   lsls r3, #24
+   lsls r2, r0, #1
+   adds r2, r3
+   bhi 1f
+   lsls r2, r1, #1
+   adds r2, r3
+   bhi 2f
+   bx lr
+2:
+   mov r0, r1
+1:
+   bx ip
+#endif
+
+.macro table_tail_call SF_TABLE_OFFSET
+#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
+#ifndef NDEBUG
+    movs r3, #0
+    mov ip, r3
+#endif
+#endif
+    ldr r3, =sf_table
+    ldr r3, [r3, #\SF_TABLE_OFFSET]
+    bx r3
+.endm
+
+.macro shimmable_table_tail_call SF_TABLE_OFFSET shim
+    ldr r3, =sf_table
+    ldr r3, [r3, #\SF_TABLE_OFFSET]
+#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
+    mov ip, pc
+#endif
+    bx r3
+#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
+.byte \SF_TABLE_OFFSET, 0xdf
+.word \shim
+#endif
+.endm
+
+
+// note generally each function is in a separate section unless there is fall thru or branching between them
+// note fadd, fsub, fmul, fdiv are so tiny and just defer to rom so are lumped together so they can share constant pool
+
+// note functions are word aligned except where they are an odd number of linear instructions
+
+// float FUNC_NAME(__aeabi_fadd)(float, float)         single-precision addition
+float_wrapper_section __aeabi_farithmetic
+// float FUNC_NAME(__aeabi_frsub)(float x, float y)    single-precision reverse subtraction, y - x
+
+// frsub first because it is the only one that needs alignment
+.align 2
+wrapper_func __aeabi_frsub
+    eors r0, r1
+    eors r1, r0
+    eors r0, r1
+    // fall thru
+
+// float FUNC_NAME(__aeabi_fsub)(float x, float y)     single-precision subtraction, x - y
+wrapper_func_f2 __aeabi_fsub
+#if PICO_FLOAT_PROPAGATE_NANS
+    // we want to return nan for inf-inf or -inf - -inf, but without too much upfront cost
+    mov r2, r0
+    eors r2, r1
+    bmi 1f // different signs
+    push {r0, r1, lr}
+    bl 1f
+    b fdiv_fsub_nan_helper
+1:
+#endif
+    table_tail_call SF_TABLE_FSUB
+
+wrapper_func_f2 __aeabi_fadd
+    table_tail_call SF_TABLE_FADD
+
+// float FUNC_NAME(__aeabi_fdiv)(float n, float d)     single-precision division, n / d
+wrapper_func_f2 __aeabi_fdiv
+#if PICO_FLOAT_PROPAGATE_NANS
+    push {r0, r1, lr}
+    bl 1f
+    b fdiv_fsub_nan_helper
+1:
+#endif
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+    // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
+    ldr r2, =(SIO_BASE)
+    ldr r3, [r2, #SIO_DIV_CSR_OFFSET]
+    lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
+    bcs fdiv_save_state
+#else
+    // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+    push {r4, lr}
+    mrs r4, PRIMASK
+    cpsid i
+    bl fdiv_shim_call
+    msr PRIMASK, r4
+    pop {r4, pc}
+#endif
+fdiv_shim_call:
+    table_tail_call SF_TABLE_FDIV
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+fdiv_save_state:
+    save_div_state_and_lr
+    bl fdiv_shim_call
+    ldr r2, =(SIO_BASE)
+    restore_div_state_and_return
+#endif
+
+fdiv_fsub_nan_helper:
+#if PICO_FLOAT_PROPAGATE_NANS
+    pop {r1, r2}
+
+    // check for infinite op infinite (or rather check for infinite result with both
+    // operands being infinite)
+    lsls r3, r0, #1
+    asrs r3, r3, #24
+    adds r3, #1
+    beq 2f
+    pop {pc}
+2:
+    lsls r1, #1
+    asrs r1, r1, #24
+    lsls r2, #1
+    asrs r2, r2, #24
+    ands r1, r2
+    adds r1, #1
+    bne 3f
+    // infinite to nan
+    movs r1, #1
+    lsls r1, #22
+    orrs r0, r1
+3:
+    pop {pc}
+#endif
+
+// float FUNC_NAME(__aeabi_fmul)(float, float)         single-precision multiplication
+wrapper_func_f2 __aeabi_fmul
+#if PICO_FLOAT_PROPAGATE_NANS
+    push {r0, r1, lr}
+    bl 1f
+    pop {r1, r2}
+
+    // check for multiplication of infinite by zero (or rather check for infinite result with either
+    // operand 0)
+    lsls r3, r0, #1
+    asrs r3, r3, #24
+    adds r3, #1
+    beq 2f
+    pop {pc}
+2:
+    ands r1, r2
+    bne 3f
+    // infinite to nan
+    movs r1, #1
+    lsls r1, #22
+    orrs r0, r1
+3:
+    pop {pc}
+1:
+#endif
+    table_tail_call SF_TABLE_FMUL
+
+// void FUNC_NAME(__aeabi_cfrcmple)(float, float)         reversed 3-way (<, =, ?>) compare [1], result in PSR ZC flags
+float_wrapper_section __aeabi_cfcmple
+.align 2
+wrapper_func __aeabi_cfrcmple
+    push {r0-r2, lr}
+    eors r0, r1
+    eors r1, r0
+    eors r0, r1
+    b __aeabi_cfcmple_guts
+
+// NOTE these share an implementation as we have no excepting NaNs.
+// void FUNC_NAME(__aeabi_cfcmple)(float, float)         3-way (<, =, ?>) compare [1], result in PSR ZC flags
+// void FUNC_NAME(__aeabi_cfcmpeq)(float, float)         non-excepting equality comparison [1], result in PSR ZC flags
+.align 2
+wrapper_func __aeabi_cfcmple
+wrapper_func __aeabi_cfcmpeq
+    push {r0-r2, lr}
+
+__aeabi_cfcmple_guts:
+    lsls r2,r0,#1
+    lsrs r2,#24
+    beq 1f
+    cmp r2,#0xff
+    bne 2f
+    lsls r2, r0, #9
+    bhi 3f
+1:
+    lsrs r0,#23     @ clear mantissa if denormal or infinite
+    lsls r0,#23
+2:
+    lsls r2,r1,#1
+    lsrs r2,#24
+    beq 1f
+    cmp r2,#0xff
+    bne 2f
+    lsls r2, r1, #9
+    bhi 3f
+1:
+    lsrs r1,#23     @ clear mantissa if denormal or infinite
+    lsls r1,#23
+2:
+    movs r2,#1      @ initialise result
+    eors r1,r0
+    bmi 2f          @ opposite signs? then can proceed on basis of sign of x
+    eors r1,r0      @ restore y
+    bpl 1f
+    cmp r1,r0
+    pop {r0-r2, pc}
+1:
+    cmp r0,r1
+    pop {r0-r2, pc}
+2:
+    orrs r1, r0     @ handle 0/-0
+    adds r1, r1     @ note this always sets C
+    beq 3f
+    mvns r0, r0     @ carry inverse of r0 sign
+    adds r0, r0
+3:
+    pop {r0-r2, pc}
+
+
+// int FUNC_NAME(__aeabi_fcmpeq)(float, float)         result (1, 0) denotes (=, ?<>) [2], use for C == and !=
+float_wrapper_section __aeabi_fcmpeq
+.align 2
+wrapper_func __aeabi_fcmpeq
+    push {lr}
+    bl __aeabi_cfcmpeq
+    beq 1f
+    movs r0, #0
+    pop {pc}
+1:
+    movs r0, #1
+    pop {pc}
+
+// int FUNC_NAME(__aeabi_fcmplt)(float, float)         result (1, 0) denotes (<, ?>=) [2], use for C <
+float_wrapper_section __aeabi_fcmplt
+.align 2
+wrapper_func __aeabi_fcmplt
+    push {lr}
+    bl __aeabi_cfcmple
+    sbcs r0, r0
+    pop {pc}
+
+// int FUNC_NAME(__aeabi_fcmple)(float, float)         result (1, 0) denotes (<=, ?>) [2], use for C <=
+float_wrapper_section __aeabi_fcmple
+.align 2
+wrapper_func __aeabi_fcmple
+    push {lr}
+    bl __aeabi_cfcmple
+    bls 1f
+    movs r0, #0
+    pop {pc}
+1:
+    movs r0, #1
+    pop {pc}
+
+// int FUNC_NAME(__aeabi_fcmpge)(float, float)         result (1, 0) denotes (>=, ?<) [2], use for C >=
+float_wrapper_section __aeabi_fcmpge
+.align 2
+wrapper_func __aeabi_fcmpge
+    push {lr}
+    // because of NaNs it is better to reverse the args than the result
+    bl __aeabi_cfrcmple
+    bls 1f
+    movs r0, #0
+    pop {pc}
+1:
+    movs r0, #1
+    pop {pc}
+
+// int FUNC_NAME(__aeabi_fcmpgt)(float, float)         result (1, 0) denotes (>, ?<=) [2], use for C >
+float_wrapper_section __aeabi_fcmpgt
+wrapper_func __aeabi_fcmpgt
+    push {lr}
+    // because of NaNs it is better to reverse the args than the result
+    bl __aeabi_cfrcmple
+    sbcs r0, r0
+    pop {pc}
+
+// int FUNC_NAME(__aeabi_fcmpun)(float, float)         result (1, 0) denotes (?, <=>) [2], use for C99 isunordered()
+float_wrapper_section __aeabi_fcmpun
+wrapper_func __aeabi_fcmpun
+   movs r3, #1
+   lsls r3, #24
+   lsls r2, r0, #1
+   adds r2, r3
+   bhi 1f
+   lsls r2, r1, #1
+   adds r2, r3
+   bhi 1f
+   movs r0, #0
+   bx lr
+1:
+   movs r0, #1
+   bx lr
+
+
+// float FUNC_NAME(__aeabi_ui2f)(unsigned)             unsigned to float (single precision) conversion
+float_wrapper_section __aeabi_ui2f
+wrapper_func __aeabi_ui2f
+        subs r1, r1
+        cmp r0, #0
+        bne __aeabi_i2f_main
+        mov r0, r1
+        bx lr
+
+float_wrapper_section __aeabi_i2f
+// float FUNC_NAME(__aeabi_i2f)(int)                     integer to float (single precision) conversion
+wrapper_func __aeabi_i2f
+        lsrs r1, r0, #31
+        lsls r1, #31
+        bpl 1f
+        rsbs r0, #0
+1:
+        cmp r0, #0
+        beq 7f
+__aeabi_i2f_main:
+
+        mov ip, lr
+        push {r0, r1}
+        ldr r3, =sf_clz_func
+        ldr r3, [r3]
+        blx r3
+        pop {r1, r2}
+        lsls r1, r0
+        subs r0, #158
+        rsbs r0, #0
+
+        adds r1,#0x80  @ rounding
+        bcs 5f         @ tripped carry? then have leading 1 in C as required (and result is even so can ignore sticky bits)
+
+        lsls r3,r1,#24 @ check bottom 8 bits of r1
+        beq 6f         @ in rounding-tie case?
+        lsls r1,#1     @ remove leading 1
+3:
+        lsrs r1,#9     @ align mantissa
+        lsls r0,#23    @ align exponent
+        orrs r0,r2     @ assemble exponent and mantissa
+4:
+        orrs r0,r1     @ apply sign
+1:
+        bx ip
+5:
+        adds r0,#1     @ correct exponent offset
+        b 3b
+6:
+        lsrs r1,#9     @ ensure even result
+        lsls r1,#10
+        b 3b
+7:
+        bx lr
+
+
+// int FUNC_NAME(__aeabi_f2iz)(float)                     float (single precision) to integer C-style conversion [3]
+float_wrapper_section __aeabi_f2iz
+wrapper_func __aeabi_f2iz
+regular_func float2int_z
+    lsls r1, r0, #1
+    lsrs r2, r1, #24
+    movs r3, #0x80
+    lsls r3, #24
+    cmp r2, #126
+    ble 1f
+    subs r2, #158
+    bge 2f
+    asrs r1, r0, #31
+    lsls r0, #9
+    lsrs r0, #1
+    orrs r0, r3
+    negs r2, r2
+    lsrs r0, r2
+    lsls r1, #1
+    adds r1, #1
+    muls r0, r1
+    bx lr
+1:
+    movs r0, #0
+    bx lr
+2:
+    lsrs r0, #31
+    adds r0, r3
+    subs r0, #1
+    bx lr
+
+    cmn r0, r0
+    bcc float2int
+    push {lr}
+    lsls r0, #1
+    lsrs r0, #1
+    movs r1, #0
+    bl __aeabi_f2uiz
+    cmp r0, #0
+    bmi 1f
+    rsbs r0, #0
+    pop {pc}
+1:
+    movs r0, #128
+    lsls r0, #24
+    pop {pc}
+
+float_section float2int
+regular_func float2int
+    shimmable_table_tail_call SF_TABLE_FLOAT2INT float2int_shim
+
+float_section float2fix
+regular_func float2fix
+    shimmable_table_tail_call SF_TABLE_FLOAT2FIX float2fix_shim
+
+float_section float2ufix
+regular_func float2ufix
+    table_tail_call SF_TABLE_FLOAT2UFIX
+
+// unsigned FUNC_NAME(__aeabi_f2uiz)(float)             float (single precision) to unsigned C-style conversion [3]
+float_wrapper_section __aeabi_f2uiz
+wrapper_func __aeabi_f2uiz
+    table_tail_call SF_TABLE_FLOAT2UINT
+
+float_section fix2float
+regular_func fix2float
+    table_tail_call SF_TABLE_FIX2FLOAT
+
+float_section ufix2float
+regular_func ufix2float
+    table_tail_call SF_TABLE_UFIX2FLOAT
+
+float_section fix642float
+regular_func fix642float
+    shimmable_table_tail_call SF_TABLE_FIX642FLOAT fix642float_shim
+
+float_section ufix642float
+regular_func ufix642float
+    shimmable_table_tail_call SF_TABLE_UFIX642FLOAT ufix642float_shim
+
+// float FUNC_NAME(__aeabi_l2f)(long long)             long long to float (single precision) conversion
+float_wrapper_section __aeabi_l2f
+1:
+    ldr r2, =__aeabi_i2f
+    bx r2
+wrapper_func __aeabi_l2f
+    asrs r2, r0, #31
+    cmp r1, r2
+    beq 1b
+    shimmable_table_tail_call SF_TABLE_INT642FLOAT int642float_shim
+
+// float FUNC_NAME(__aeabi_l2f)(long long)             long long to float (single precision) conversion
+float_wrapper_section __aeabi_ul2f
+1:
+    ldr r2, =__aeabi_ui2f
+    bx r2
+wrapper_func __aeabi_ul2f
+    cmp r1, #0
+    beq 1b
+    shimmable_table_tail_call SF_TABLE_UINT642FLOAT uint642float_shim
+
+// long long FUNC_NAME(__aeabi_f2lz)(float)             float (single precision) to long long C-style conversion [3]
+float_wrapper_section __aeabi_f2lz
+wrapper_func __aeabi_f2lz
+regular_func float2int64_z
+    cmn r0, r0
+    bcc float2int64
+    push {lr}
+    lsls r0, #1
+    lsrs r0, #1
+    movs r1, #0
+    bl float2ufix64
+    cmp r1, #0
+    bmi 1f
+    movs r2, #0
+    rsbs r0, #0
+    sbcs r2, r1
+    mov r1, r2
+    pop {pc}
+1:
+    movs r1, #128
+    lsls r1, #24
+    movs r0, #0
+    pop {pc}
+
+float_section float2int64
+regular_func float2int64
+    shimmable_table_tail_call SF_TABLE_FLOAT2INT64 float2int64_shim
+
+float_section float2fix64
+regular_func float2fix64
+    shimmable_table_tail_call SF_TABLE_FLOAT2FIX64 float2fix64_shim
+
+// unsigned long long FUNC_NAME(__aeabi_f2ulz)(float)     float to unsigned long long C-style conversion [3]
+float_wrapper_section __aeabi_f2ulz
+wrapper_func __aeabi_f2ulz
+    shimmable_table_tail_call SF_TABLE_FLOAT2UINT64 float2uint64_shim
+
+float_section float2ufix64
+regular_func float2ufix64
+    shimmable_table_tail_call SF_TABLE_FLOAT2UFIX64 float2ufix64_shim
+
+float_wrapper_section __aeabi_f2d
+1:
+#if PICO_FLOAT_PROPAGATE_NANS
+    // copy sign bit and 25 NAN id bits into sign bit and significant ID bits, also setting the high id bit
+    asrs r1, r0, #3
+    movs r2, #0xf
+    lsls r2, #27
+    orrs r1, r2
+    lsls r0, #25
+    bx lr
+#endif
+wrapper_func __aeabi_f2d
+#if PICO_FLOAT_PROPAGATE_NANS
+    movs r3, #1
+    lsls r3, #24
+    lsls r2, r0, #1
+    adds r2, r3
+    bhi 1b
+#endif
+    shimmable_table_tail_call SF_TABLE_FLOAT2DOUBLE float2double_shim
+
+float_wrapper_section srqtf
+wrapper_func_f1 sqrtf
+#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
+    // check for negative
+    asrs r1, r0, #23
+    bmi 1f
+#endif
+    table_tail_call SF_TABLE_FSQRT
+#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
+1:
+    mvns r0, r1
+    cmp r0, #255
+    bne 2f
+    // -0 or -Denormal return -0 (0x80000000)
+    lsls r0, #31
+    bx lr
+2:
+    // return -Inf (0xff800000)
+    asrs r0, r1, #31
+    lsls r0, #23
+    bx lr
+#endif
+
+float_wrapper_section cosf
+// note we don't use _f1 since we do an infinity/nan check for outside of range
+wrapper_func cosf
+    // rom version only works for -128 < angle < 128
+    lsls r1, r0, #1
+    lsrs r1, #24
+    cmp r1, #127 + 7
+    bge 1f
+2:
+    table_tail_call SF_TABLE_FCOS
+1:
+#if PICO_FLOAT_PROPAGATE_NANS
+    // also check for infinites
+    cmp r1, #255
+    bne 3f
+    // infinite to nan
+    movs r1, #1
+    lsls r1, #22
+    orrs r0, r1
+    bx lr
+3:
+#endif
+    ldr r1, =0x40c90fdb // 2 * M_PI
+    push {lr}
+    bl remainderf
+    pop {r1}
+    mov lr, r1
+    b 2b
+
+float_wrapper_section sinf
+// note we don't use _f1 since we do an infinity/nan check for outside of range
+wrapper_func sinf
+    // rom version only works for -128 < angle < 128
+    lsls r1, r0, #1
+    lsrs r1, #24
+    cmp r1, #127 + 7
+    bge 1f
+2:
+    table_tail_call SF_TABLE_FSIN
+1:
+#if PICO_FLOAT_PROPAGATE_NANS
+    // also check for infinites
+    cmp r1, #255
+    bne 3f
+    // infinite to nan
+    movs r1, #1
+    lsls r1, #22
+    orrs r0, r1
+    bx lr
+3:
+#endif
+    ldr r1, =0x40c90fdb // 2 * M_PI
+    push {lr}
+    bl remainderf
+    pop {r1}
+    mov lr, r1
+    b 2b
+
+float_wrapper_section sincosf
+// note we don't use _f1 since we do an infinity/nan check for outside of range
+wrapper_func sincosf
+    push {r1, r2, lr}
+    // rom version only works for -128 < angle < 128
+    lsls r3, r0, #1
+    lsrs r3, #24
+    cmp r3, #127 + 7
+    bge 3f
+2:
+    ldr r3, =sf_table
+    ldr r3, [r3, #SF_TABLE_FSIN]
+    blx r3
+    pop {r2, r3}
+    str r0, [r2]
+    str r1, [r3]
+    pop {pc}
+#if PICO_FLOAT_PROPAGATE_NANS
+.align 2
+    pop {pc}
+#endif
+3:
+#if PICO_FLOAT_PROPAGATE_NANS
+    // also check for infinites
+    cmp r3, #255
+    bne 4f
+    // infinite to nan
+    movs r3, #1
+    lsls r3, #22
+    orrs r0, r3
+    str r0, [r1]
+    str r0, [r2]
+    add sp, #12
+    bx lr
+4:
+#endif
+    ldr r1, =0x40c90fdb // 2 * M_PI
+    push {lr}
+    bl remainderf
+    pop {r1}
+    mov lr, r1
+    b 2b
+
+float_wrapper_section tanf
+// note we don't use _f1 since we do an infinity/nan check for outside of range
+wrapper_func tanf
+    // rom version only works for -128 < angle < 128
+    lsls r1, r0, #1
+    lsrs r1, #24
+    cmp r1, #127 + 7
+    bge ftan_out_of_range
+ftan_in_range:
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+    // to support IRQ usage (or context switch) we must save/restore divider state around call if state is dirty
+    ldr r2, =(SIO_BASE)
+    ldr r3, [r2, #SIO_DIV_CSR_OFFSET]
+    lsrs r3, #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
+    bcs ftan_save_state
+#else
+    // to avoid worrying about IRQs (or context switches), simply disable interrupts around call
+    push {r4, lr}
+    mrs r4, PRIMASK
+    cpsid i
+    bl ftan_shim_call
+    msr PRIMASK, r4
+    pop {r4, pc}
+#endif
+ftan_shim_call:
+    table_tail_call SF_TABLE_FTAN
+#if !PICO_DIVIDER_DISABLE_INTERRUPTS
+ftan_save_state:
+    save_div_state_and_lr
+    bl ftan_shim_call
+    ldr r2, =(SIO_BASE)
+    restore_div_state_and_return
+#endif
+ftan_out_of_range:
+#if PICO_FLOAT_PROPAGATE_NANS
+    // also check for infinites
+    cmp r1, #255
+    bne 3f
+    // infinite to nan
+    movs r1, #1
+    lsls r1, #22
+    orrs r0, r1
+    bx lr
+3:
+#endif
+    ldr r1, =0x40c90fdb // 2 * M_PI
+    push {lr}
+    bl remainderf
+    pop {r1}
+    mov lr, r1
+    b ftan_in_range
+
+float_wrapper_section atan2f
+wrapper_func_f2 atan2f
+    shimmable_table_tail_call SF_TABLE_FATAN2 fatan2_shim
+
+float_wrapper_section expf
+wrapper_func_f1 expf
+    table_tail_call SF_TABLE_FEXP
+
+float_wrapper_section logf
+wrapper_func_f1 logf
+    table_tail_call SF_TABLE_FLN
diff --git a/src/rp2_common/pico_float/float_init_rom.c b/src/rp2_common/pico_float/float_init_rom.c
new file mode 100644
index 0000000..646c0e9
--- /dev/null
+++ b/src/rp2_common/pico_float/float_init_rom.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+#include "pico/bootrom.h"
+#include "pico/bootrom/sf_table.h"
+
+// NOTE THIS FUNCTION TABLE IS NOT PUBLIC OR NECESSARILY COMPLETE...
+// IT IS ***NOT*** SAFE TO CALL THESE FUNCTION POINTERS FROM ARBITRARY CODE
+uint32_t sf_table[SF_TABLE_V2_SIZE / 2];
+void __attribute__((weak)) *sf_clz_func;
+
+#if !(PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED)
+static __attribute__((noreturn)) void missing_float_func_shim(void) {
+    panic("");
+}
+#endif
+
+void __aeabi_float_init(void) {
+    int rom_version = rp2040_rom_version();
+    void *rom_table = rom_data_lookup(rom_table_code('S', 'F'));
+#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
+    if (rom_version == 1) {
+        memcpy(&sf_table, rom_table, SF_TABLE_V1_SIZE);
+        extern void float_table_shim_on_use_helper(void);
+        // todo replace NDEBUG with a more exclusive assertion guard
+#ifndef NDEBUG
+        if (*(uint16_t *)0x29ee != 0x0fc4 || // this is packx
+            *(uint16_t *)0x29c0 != 0x0dc2 || // this is upackx
+            *(uint16_t *)0x2b96 != 0xb5c0 || // this is cordic_vec
+            *(uint16_t *)0x2b18 != 0x2500 || // this is packretns
+            *(uint16_t *)0x2acc != 0xb510 || // this is float2fix
+            *(uint32_t *)0x2cfc != 0x6487ed51 // pi_q29
+        ) {
+            panic("");
+        }
+#endif
+
+        // this is a little tricky.. we only want to pull in a shim if the corresponding function
+        // is called. to that end we include a SVC instruction with the table offset as the call number
+        // followed by the shim function pointer inside the actual wrapper function. that way if the wrapper
+        // function is garbage collected, so is the shim function.
+        //
+        // float_table_shim_on_use_helper expects this SVC instruction in the calling code soon after the address
+        // pointed to by IP and patches the float_table entry with the real shim the first time the function is called.
+
+        for(uint i=SF_TABLE_V1_SIZE/4; i<SF_TABLE_V2_SIZE/4; i++) {
+            sf_table[i] = (uintptr_t)float_table_shim_on_use_helper;
+        }
+        // we shim these for -0 and -denormal handling
+        sf_table[SF_TABLE_FLOAT2INT/4] = sf_table[SF_TABLE_FLOAT2FIX/4] = (uintptr_t)float_table_shim_on_use_helper;
+    }
+#else
+    if (rom_version == 1) {
+        memcpy(&sf_table, rom_table, SF_TABLE_V1_SIZE);
+        // opting for soft failure for now - you'll get a panic at runtime if you call any of the missing methods
+        for(uint i=0;i<SF_TABLE_V2_SIZE/4;i++) {
+            if (!sf_table[i]) sf_table[i] = (uintptr_t)missing_float_func_shim;
+        }
+    }
+#endif
+    if (rom_version >= 2) {
+        assert(*((uint8_t *)(rom_table-2)) * 4 >= SF_TABLE_V2_SIZE);
+        memcpy(&sf_table, rom_table, SF_TABLE_V2_SIZE);
+    }
+    sf_clz_func = rom_func_lookup(ROM_FUNC_CLZ32);
+}
diff --git a/src/rp2_common/pico_float/float_math.c b/src/rp2_common/pico_float/float_math.c
new file mode 100644
index 0000000..a48a2d7
--- /dev/null
+++ b/src/rp2_common/pico_float/float_math.c
@@ -0,0 +1,584 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/types.h"
+#include "pico/float.h"
+#include "pico/platform.h"
+
+// opened a separate issue https://github.com/raspberrypi/pico-sdk/issues/166 to deal with these warnings if at all
+_Pragma("GCC diagnostic push")
+_Pragma("GCC diagnostic ignored \"-Wconversion\"")
+_Pragma("GCC diagnostic ignored \"-Wsign-conversion\"")
+
+typedef uint32_t ui32;
+typedef int32_t i32;
+
+#define FPINF ( HUGE_VALF)
+#define FMINF (-HUGE_VALF)
+#define NANF ((float)NAN)
+#define PZERO (+0.0)
+#define MZERO (-0.0)
+
+#define PI       3.14159265358979323846
+#define LOG2     0.69314718055994530941
+// Unfortunately in double precision ln(10) is very close to half-way between to representable numbers
+#define LOG10    2.30258509299404568401
+#define LOG2E    1.44269504088896340737
+#define LOG10E   0.43429448190325182765
+#define ONETHIRD 0.33333333333333333333
+
+#define PIf       3.14159265358979323846f
+#define LOG2f     0.69314718055994530941f
+#define LOG2Ef    1.44269504088896340737f
+#define LOG10Ef   0.43429448190325182765f
+#define ONETHIRDf 0.33333333333333333333f
+
+#define FUNPACK(x,e,m) e=((x)>>23)&0xff,m=((x)&0x007fffff)|0x00800000
+#define FUNPACKS(x,s,e,m) s=((x)>>31),FUNPACK((x),(e),(m))
+
+typedef union {
+    float f;
+    ui32 ix;
+} float_ui32;
+
+static inline float ui322float(ui32 ix) {
+    float_ui32 tmp;
+    tmp.ix = ix;
+    return tmp.f;
+}
+
+static inline ui32 float2ui32(float f) {
+    float_ui32 tmp;
+    tmp.f = f;
+    return tmp.ix;
+}
+
+static inline bool fisnan(float x) {
+    ui32 ix=float2ui32(x);
+    return ix * 2 > 0xff000000u;
+}
+
+#if PICO_FLOAT_PROPAGATE_NANS
+#define check_nan_f1(x) if (fisnan((x))) return (x)
+#define check_nan_f2(x,y) if (fisnan((x))) return (x); else if (fisnan((y))) return (y);
+#else
+#define check_nan_f1(x) ((void)0)
+#define check_nan_f2(x,y) ((void)0)
+#endif
+
+static inline int fgetsignexp(float x) {
+    ui32 ix=float2ui32(x);
+    return (ix>>23)&0x1ff;
+}
+
+static inline int fgetexp(float x) {
+    ui32 ix=float2ui32(x);
+    return (ix>>23)&0xff;
+}
+
+static inline float fldexp(float x,int de) {
+    ui32 ix=float2ui32(x),iy;
+    int e;
+    e=fgetexp(x);
+    if(e==0||e==0xff) return x;
+    e+=de;
+    if(e<=0) iy=ix&0x80000000; // signed zero for underflow
+    else if(e>=0xff) iy=(ix&0x80000000)|0x7f800000ULL; // signed infinity on overflow
+    else iy=ix+((ui32)de<<23);
+    return ui322float(iy);
+}
+
+float WRAPPER_FUNC(ldexpf)(float x, int de) {
+    check_nan_f1(x);
+    return fldexp(x, de);
+}
+
+static inline float fcopysign(float x,float y) {
+    ui32 ix=float2ui32(x),iy=float2ui32(y);
+    ix=((ix&0x7fffffff)|(iy&0x80000000));
+    return ui322float(ix);
+}
+
+float WRAPPER_FUNC(copysignf)(float x, float y) {
+    check_nan_f2(x,y);
+    return fcopysign(x, y);
+}
+
+static inline int fiszero(float x)  { return fgetexp    (x)==0; }
+static inline int fispzero(float x) { return fgetsignexp(x)==0; }
+static inline int fismzero(float x) { return fgetsignexp(x)==0x100; }
+static inline int fisinf(float x)   { return fgetexp    (x)==0xff; }
+static inline int fispinf(float x)  { return fgetsignexp(x)==0xff; }
+static inline int fisminf(float x)  { return fgetsignexp(x)==0x1ff; }
+
+static inline int fisint(float x) {
+    ui32 ix=float2ui32(x),m;
+    int e=fgetexp(x);
+    if(e==0) return 1;       // 0 is an integer
+    e-=0x7f;                 // remove exponent bias
+    if(e<0) return 0;        // |x|<1
+    e=23-e;                  // bit position in mantissa with significance 1
+    if(e<=0) return 1;       // |x| large, so must be an integer
+    m=(1<<e)-1;              // mask for bits of significance <1
+    if(ix&m) return 0;       // not an integer
+    return 1;
+}
+
+static inline int fisoddint(float x) {
+    ui32 ix=float2ui32(x),m;
+    int e=fgetexp(x);
+    e-=0x7f;                 // remove exponent bias
+    if(e<0) return 0;        // |x|<1; 0 is not odd
+    e=23-e;                  // bit position in mantissa with significance 1
+    if(e<0) return 0;        // |x| large, so must be even
+    m=(1<<e)-1;              // mask for bits of significance <1 (if any)
+    if(ix&m) return 0;       // not an integer
+    if(e==23) return 1;      // value is exactly 1
+    return (ix>>e)&1;
+}
+
+static inline int fisstrictneg(float x) {
+    ui32 ix=float2ui32(x);
+    if(fiszero(x)) return 0;
+    return ix>>31;
+}
+
+static inline int fisneg(float x) {
+    ui32 ix=float2ui32(x);
+    return ix>>31;
+}
+
+static inline float fneg(float x) {
+    ui32 ix=float2ui32(x);
+    ix^=0x80000000;
+    return ui322float(ix);
+}
+
+static inline int fispo2(float x) {
+    ui32 ix=float2ui32(x);
+    if(fiszero(x)) return 0;
+    if(fisinf(x)) return 0;
+    ix&=0x007fffff;
+    return ix==0;
+}
+
+static inline float fnan_or(float x) {
+#if PICO_FLOAT_PROPAGATE_NANS
+    return NANF;
+#else
+    return x;
+#endif
+}
+
+float WRAPPER_FUNC(truncf)(float x) {
+    check_nan_f1(x);
+    ui32 ix=float2ui32(x),m;
+    int e=fgetexp(x);
+    e-=0x7f;                 // remove exponent bias
+    if(e<0) {                // |x|<1
+        ix&=0x80000000;
+        return ui322float(ix);
+    }
+    e=23-e;                  // bit position in mantissa with significance 1
+    if(e<=0) return x;       // |x| large, so must be an integer
+    m=(1<<e)-1;              // mask for bits of significance <1
+    ix&=~m;
+    return ui322float(ix);
+}
+
+float WRAPPER_FUNC(roundf)(float x) {
+    check_nan_f1(x);
+    ui32 ix=float2ui32(x),m;
+    int e=fgetexp(x);
+    e-=0x7f;                 // remove exponent bias
+    if(e<-1) {               // |x|<0.5
+        ix&=0x80000000;
+        return ui322float(ix);
+    }
+    if(e==-1) {              // 0.5<=|x|<1
+        ix&=0x80000000;
+        ix|=0x3f800000;        // ±1
+        return ui322float(ix);
+    }
+    e=23-e;                  // bit position in mantissa with significance 1, <=23
+    if(e<=0) return x;       // |x| large, so must be an integer
+    m=1<<(e-1);              // mask for bit of significance 0.5
+    ix+=m;
+    m=m+m-1;                 // mask for bits of significance <1
+    ix&=~m;
+    return ui322float(ix);
+}
+
+float WRAPPER_FUNC(floorf)(float x) {
+    check_nan_f1(x);
+    ui32 ix=float2ui32(x),m;
+    int e=fgetexp(x);
+    if(e==0) {       // x==0
+        ix&=0x80000000;
+        return ui322float(ix);
+    }
+    e-=0x7f;                 // remove exponent bias
+    if(e<0) {                // |x|<1, not zero
+        if(fisneg(x)) return -1;
+        return PZERO;
+    }
+    e=23-e;                  // bit position in mantissa with significance 1
+    if(e<=0) return x;       // |x| large, so must be an integer
+    m=(1<<e)-1;              // mask for bit of significance <1
+    if(fisneg(x)) ix+=m;     // add 1-ε to magnitude if negative
+    ix&=~m;                  // truncate
+    return ui322float(ix);
+}
+
+float WRAPPER_FUNC(ceilf)(float x) {
+    check_nan_f1(x);
+    ui32 ix=float2ui32(x),m;
+    int e=fgetexp(x);
+    if(e==0) {       // x==0
+        ix&=0x80000000;
+        return ui322float(ix);
+    }
+    e-=0x7f;                 // remove exponent bias
+    if(e<0) {                // |x|<1, not zero
+        if(fisneg(x)) return MZERO;
+        return 1;
+    }
+    e=23-e;                  // bit position in mantissa with significance 1
+    if(e<=0) return x;       // |x| large, so must be an integer
+    m=(1<<e)-1;              // mask for bit of significance <1
+    if(!fisneg(x)) ix+=m;    // add 1-ε to magnitude if positive
+    ix&=~m;                  // truncate
+    return ui322float(ix);
+}
+
+float WRAPPER_FUNC(asinf)(float x) {
+    check_nan_f1(x);
+    float u;
+    u=(1.0f-x)*(1.0f+x);
+    if(fisstrictneg(u)) return fnan_or(FPINF);
+    return atan2f(x,sqrtf(u));
+}
+
+float WRAPPER_FUNC(acosf)(float x) {
+    check_nan_f1(x);
+    float u;
+    u=(1.0f-x)*(1.0f+x);
+    if(fisstrictneg(u)) return fnan_or(FPINF);
+    return atan2f(sqrtf(u),x);
+}
+
+float WRAPPER_FUNC(atanf)(float x) {
+    check_nan_f1(x);
+    if(fispinf(x)) return (float)( PIf/2);
+    if(fisminf(x)) return (float)(-PIf/2);
+    return atan2f(x,1.0f);
+}
+
+float WRAPPER_FUNC(sinhf)(float x) {
+    check_nan_f1(x);
+    return fldexp((expf(x)-expf(fneg(x))),-1);
+}
+
+float WRAPPER_FUNC(coshf)(float x) {
+    check_nan_f1(x);
+    return fldexp((expf(x)+expf(fneg(x))),-1);
+}
+
+float WRAPPER_FUNC(tanhf)(float x) {
+    check_nan_f1(x);
+    float u;
+    int e;
+    e=fgetexp(x);
+    if(e>=4+0x7f) {             // |x|>=16?
+        if(!fisneg(x)) return  1;  // 1 << exp 2x; avoid generating infinities later
+        else           return -1;  // 1 >> exp 2x
+    }
+    u=expf(fldexp(x,1));
+    return (u-1.0f)/(u+1.0f);
+}
+
+float WRAPPER_FUNC(asinhf)(float x) {
+    check_nan_f1(x);
+    int e;
+    e=fgetexp(x);
+    if(e>=16+0x7f) {                                   // |x|>=2^16?
+        if(!fisneg(x)) return      logf(     x )+LOG2f;  // 1/x^2 << 1
+        else           return fneg(logf(fneg(x))+LOG2f); // 1/x^2 << 1
+    }
+    if(x>0) return      (float)log(sqrt((double)x*(double)x+1.0)+(double)x);
+    else    return fneg((float)log(sqrt((double)x*(double)x+1.0)-(double)x));
+}
+
+float WRAPPER_FUNC(acoshf)(float x) {
+    check_nan_f1(x);
+    int e;
+    if(fisneg(x)) x=fneg(x);
+    e=fgetexp(x);
+    if(e>=16+0x7f) return logf(x)+LOG2f;           // |x|>=2^16?
+    return (float)log(sqrt(((double)x+1.0)*((double)x-1.0))+(double)x);
+}
+
+float WRAPPER_FUNC(atanhf)(float x) {
+    check_nan_f1(x);
+    return fldexp(logf((1.0f+x)/(1.0f-x)),-1);
+}
+
+float WRAPPER_FUNC(exp2f)(float x) { check_nan_f1(x); return (float)exp((double)x*LOG2); }
+float WRAPPER_FUNC(log2f)(float x) { check_nan_f1(x); return logf(x)*LOG2Ef;  }
+float WRAPPER_FUNC(exp10f)(float x) { check_nan_f1(x); return (float)exp((double)x*LOG10); }
+float WRAPPER_FUNC(log10f)(float x) { check_nan_f1(x); return logf(x)*LOG10Ef; }
+
+float WRAPPER_FUNC(expm1f)(float x) { check_nan_f1(x); return (float)(exp((double)x)-1); }
+float WRAPPER_FUNC(log1pf)(float x) { check_nan_f1(x); return (float)(log(1+(double)x)); }
+float WRAPPER_FUNC(fmaf)(float x,float y,float z) {
+    check_nan_f2(x,y);
+    check_nan_f1(z);
+    return (float)((double)x*(double)y+(double)z);
+} // has double rounding so not exact
+
+// general power, x>0
+static inline float fpow_1(float x,float y) {
+    return (float)exp(log((double)x)*(double)y); // using double-precision intermediates for better accuracy
+}
+
+static float fpow_int2(float x,int y) {
+    float u;
+    if(y==1) return x;
+    u=fpow_int2(x,y/2);
+    u*=u;
+    if(y&1) u*=x;
+    return u;
+}
+
+// for the case where x not zero or infinity, y small and not zero
+static inline float fpowint_1(float x,int y) {
+    if(y<0) x=1.0f/x,y=-y;
+    return fpow_int2(x,y);
+}
+
+// for the case where x not zero or infinity
+static float fpowint_0(float x,int y) {
+    int e;
+    if(fisneg(x)) {
+        if(fisoddint(y)) return fneg(fpowint_0(fneg(x),y));
+        else             return      fpowint_0(fneg(x),y);
+    }
+    if(fispo2(x)) {
+        e=fgetexp(x)-0x7f;
+        if(y>=256) y= 255;  // avoid overflow
+        if(y<-256) y=-256;
+        y*=e;
+        return fldexp(1,y);
+    }
+    if(y==0) return 1;
+    if(y>=-32&&y<=32) return fpowint_1(x,y);
+    return fpow_1(x,y);
+}
+
+float WRAPPER_FUNC(powintf)(float x,int y) {
+    _Pragma("GCC diagnostic push")
+    _Pragma("GCC diagnostic ignored \"-Wfloat-equal\"")
+    if(x==1.0f||y==0) return 1;
+    if(x==0.0f) {
+        if(y>0) {
+            if(y&1) return x;
+            else    return 0;
+        }
+        if((y&1)) return fcopysign(FPINF,x);
+        return FPINF;
+    }
+    _Pragma("GCC diagnostic pop")
+    check_nan_f1(x);
+    if(fispinf(x)) {
+        if(y<0) return 0;
+        else    return FPINF;
+    }
+    if(fisminf(x)) {
+        if(y>0) {
+            if((y&1)) return FMINF;
+            else      return FPINF;
+        }
+        if((y&1)) return MZERO;
+        else      return PZERO;
+    }
+    return fpowint_0(x,y);
+}
+
+// for the case where y is guaranteed a finite integer, x not zero or infinity
+static float fpow_0(float x,float y) {
+    int e,p;
+    if(fisneg(x)) {
+        if(fisoddint(y)) return fneg(fpow_0(fneg(x),y));
+        else             return      fpow_0(fneg(x),y);
+    }
+    p=(int)y;
+    if(fispo2(x)) {
+        e=fgetexp(x)-0x7f;
+        if(p>=256) p= 255;  // avoid overflow
+        if(p<-256) p=-256;
+        p*=e;
+        return fldexp(1,p);
+    }
+    if(p==0) return 1;
+    if(p>=-32&&p<=32) return fpowint_1(x,p);
+    return fpow_1(x,y);
+}
+
+float WRAPPER_FUNC(powf)(float x,float y) {
+    _Pragma("GCC diagnostic push")
+    _Pragma("GCC diagnostic ignored \"-Wfloat-equal\"")
+    if(x==1.0f||fiszero(y)) return 1;
+    check_nan_f2(x,y);
+    if(x==-1.0f&&fisinf(y)) return 1;
+    _Pragma("GCC diagnostic pop")
+    if(fiszero(x)) {
+        if(!fisneg(y)) {
+            if(fisoddint(y)) return x;
+            else             return 0;
+        }
+        if(fisoddint(y)) return fcopysign(FPINF,x);
+        return FPINF;
+    }
+    if(fispinf(x)) {
+        if(fisneg(y)) return 0;
+        else          return FPINF;
+    }
+    if(fisminf(x)) {
+        if(!fisneg(y)) {
+            if(fisoddint(y)) return FMINF;
+            else             return FPINF;
+        }
+        if(fisoddint(y)) return MZERO;
+        else             return PZERO;
+    }
+    if(fispinf(y)) {
+        if(fgetexp(x)<0x7f) return PZERO;
+        else                return FPINF;
+    }
+    if(fisminf(y)) {
+        if(fgetexp(x)<0x7f) return FPINF;
+        else                return PZERO;
+    }
+    if(fisint(y)) return fpow_0(x,y);
+    if(fisneg(x)) return FPINF;
+    return fpow_1(x,y);
+}
+
+float WRAPPER_FUNC(hypotf)(float x,float y) {
+    check_nan_f2(x,y);
+    int ex,ey;
+    ex=fgetexp(x); ey=fgetexp(y);
+    if(ex>=0x7f+50||ey>=0x7f+50) { // overflow, or nearly so
+        x=fldexp(x,-70),y=fldexp(y,-70);
+        return fldexp(sqrtf(x*x+y*y), 70);
+    }
+    else if(ex<=0x7f-50&&ey<=0x7f-50) { // underflow, or nearly so
+        x=fldexp(x, 70),y=fldexp(y, 70);
+        return fldexp(sqrtf(x*x+y*y),-70);
+    }
+    return sqrtf(x*x+y*y);
+}
+
+float WRAPPER_FUNC(cbrtf)(float x) {
+    check_nan_f1(x);
+    int e;
+    if(fisneg(x)) return fneg(cbrtf(fneg(x)));
+    if(fiszero(x)) return fcopysign(PZERO,x);
+    e=fgetexp(x)-0x7f;
+    e=(e*0x5555+0x8000)>>16;  // ~e/3, rounded
+    x=fldexp(x,-e*3);
+    x=expf(logf(x)*ONETHIRDf);
+    return fldexp(x,e);
+}
+
+// reduces mx*2^e modulo my, returning bottom bits of quotient at *pquo
+// 2^23<=|mx|,my<2^24, e>=0; 0<=result<my
+static i32 frem_0(i32 mx,i32 my,int e,int*pquo) {
+    int quo=0,q,r=0,s;
+    if(e>0) {
+        r=0xffffffffU/(ui32)(my>>7);  // reciprocal estimate Q16
+    }
+    while(e>0) {
+        s=e; if(s>12) s=12;    // gain up to 12 bits on each iteration
+        q=(mx>>9)*r;           // Q30
+        q=((q>>(29-s))+1)>>1;  // Q(s), rounded
+        mx=(mx<<s)-my*q;
+        quo=(quo<<s)+q;
+        e-=s;
+    }
+    if(mx>=my) mx-=my,quo++; // when e==0 mx can be nearly as big as 2my
+    if(mx>=my) mx-=my,quo++;
+    if(mx<0) mx+=my,quo--;
+    if(mx<0) mx+=my,quo--;
+    if(pquo) *pquo=quo;
+    return mx;
+}
+
+float WRAPPER_FUNC(fmodf)(float x,float y) {
+    check_nan_f2(x,y);
+    ui32 ix=float2ui32(x),iy=float2ui32(y);
+    int sx,ex,ey;
+    i32 mx,my;
+    FUNPACKS(ix,sx,ex,mx);
+    FUNPACK(iy,ey,my);
+    if(ex==0xff) {
+        return fnan_or(FPINF);
+    }
+    if(ey==0) return FPINF;
+    if(ex==0) {
+        if(!fisneg(x)) return PZERO;
+        return MZERO;
+    }
+    if(ex<ey) return x;  // |x|<|y|, including case x=±0
+    mx=frem_0(mx,my,ex-ey,0);
+    if(sx) mx=-mx;
+    return fix2float(mx,0x7f-ey+23);
+}
+
+float WRAPPER_FUNC(remquof)(float x,float y,int*quo) {
+    check_nan_f2(x,y);
+    ui32 ix=float2ui32(x),iy=float2ui32(y);
+    int sx,sy,ex,ey,q;
+    i32 mx,my;
+    FUNPACKS(ix,sx,ex,mx);
+    FUNPACKS(iy,sy,ey,my);
+    if(quo) *quo=0;
+    if(ex==0xff) return FPINF;
+    if(ey==0)    return FPINF;
+    if(ex==0)    return PZERO;
+    if(ey==0xff) return x;
+    if(ex<ey-1)  return x;  // |x|<|y|/2
+    if(ex==ey-1) {
+        if(mx<=my) return x;  // |x|<=|y|/2, even quotient
+        // here |y|/2<|x|<|y|
+        if(!sx) { // x>|y|/2
+            mx-=my+my;
+            ey--;
+            q=1;
+        } else { // x<-|y|/2
+            mx=my+my-mx;
+            ey--;
+            q=-1;
+        }
+    }
+    else {
+        if(sx) mx=-mx;
+        mx=frem_0(mx,my,ex-ey,&q);
+        if(mx+mx>my || (mx+mx==my&&(q&1)) ) { // |x|>|y|/2, or equality and an odd quotient?
+            mx-=my;
+            q++;
+        }
+    }
+    if(sy) q=-q;
+    if(quo) *quo=q;
+    return fix2float(mx,0x7f-ey+23);
+}
+
+float WRAPPER_FUNC(dremf)(float x,float y) { check_nan_f2(x,y); return remquof(x,y,0); }
+
+float WRAPPER_FUNC(remainderf)(float x,float y) { check_nan_f2(x,y); return remquof(x,y,0); }
+
+_Pragma("GCC diagnostic pop") // conversion
\ No newline at end of file
diff --git a/src/rp2_common/pico_float/float_none.S b/src/rp2_common/pico_float/float_none.S
new file mode 100644
index 0000000..55baf29
--- /dev/null
+++ b/src/rp2_common/pico_float/float_none.S
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/asm_helper.S"
+#include "pico/bootrom/sf_table.h"
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+wrapper_func __aeabi_fadd
+wrapper_func __aeabi_fdiv
+wrapper_func __aeabi_fmul
+wrapper_func __aeabi_frsub
+wrapper_func __aeabi_fsub
+wrapper_func __aeabi_cfcmpeq
+wrapper_func __aeabi_cfrcmple
+wrapper_func __aeabi_cfcmple
+wrapper_func __aeabi_fcmpeq
+wrapper_func __aeabi_fcmplt
+wrapper_func __aeabi_fcmple
+wrapper_func __aeabi_fcmpge
+wrapper_func __aeabi_fcmpgt
+wrapper_func __aeabi_fcmpun
+wrapper_func __aeabi_i2f
+wrapper_func __aeabi_l2f
+wrapper_func __aeabi_ui2f
+wrapper_func __aeabi_ul2f
+wrapper_func __aeabi_i2f
+wrapper_func __aeabi_f2iz
+wrapper_func __aeabi_f2lz
+wrapper_func __aeabi_f2uiz
+wrapper_func __aeabi_f2ulz
+wrapper_func __aeabi_f2d
+wrapper_func sqrtf
+wrapper_func cosf
+wrapper_func sinf
+wrapper_func tanf
+wrapper_func atan2f
+wrapper_func expf
+wrapper_func logf
+wrapper_func ldexpf
+wrapper_func copysignf
+wrapper_func truncf
+wrapper_func floorf
+wrapper_func ceilf
+wrapper_func roundf
+wrapper_func sincosf
+wrapper_func asinf
+wrapper_func acosf
+wrapper_func atanf
+wrapper_func sinhf
+wrapper_func coshf
+wrapper_func tanhf
+wrapper_func asinhf
+wrapper_func acoshf
+wrapper_func atanhf
+wrapper_func exp2f
+wrapper_func log2f
+wrapper_func exp10f
+wrapper_func log10f
+wrapper_func powf
+wrapper_func powintf
+wrapper_func hypotf
+wrapper_func cbrtf
+wrapper_func fmodf
+wrapper_func dremf
+wrapper_func remainderf
+wrapper_func remquof
+wrapper_func expm1f
+wrapper_func log1pf
+wrapper_func fmaf
+    push {lr}       // keep stack trace sane
+    ldr r0, =str
+    bl panic
+
+str:
+    .asciz "float support is disabled"
\ No newline at end of file
diff --git a/src/rp2_common/pico_float/float_v1_rom_shim.S b/src/rp2_common/pico_float/float_v1_rom_shim.S
new file mode 100644
index 0000000..d7541a4
--- /dev/null
+++ b/src/rp2_common/pico_float/float_v1_rom_shim.S
@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/asm_helper.S"
+
+#if PICO_FLOAT_SUPPORT_ROM_V1 && PICO_RP2040_B0_SUPPORTED
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+#ifndef PICO_FLOAT_IN_RAM
+#define PICO_FLOAT_IN_RAM 0
+#endif
+
+.macro float_section name
+// todo separate flag for shims?
+#if PICO_FLOAT_IN_RAM
+.section RAM_SECTION_NAME(\name), "ax"
+#else
+.section SECTION_NAME(\name), "ax"
+#endif
+.endm
+
+float_section float_table_shim_on_use_helper
+regular_func float_table_shim_on_use_helper
+    push {r0-r2, lr}
+    mov r0, ip
+#ifndef NDEBUG
+    // sanity check to make sure we weren't called by non (shimmable_) table_tail_call macro
+    cmp r0, #0
+    bne 1f
+    bkpt #0
+#endif
+1:
+    ldrh r1, [r0]
+    lsrs r2, r1, #8
+    adds r0, #2
+    cmp r2, #0xdf
+    bne 1b
+    uxtb r1, r1 // r1 holds table offset
+    lsrs r2, r0, #2
+    bcc 1f
+    // unaligned
+    ldrh r2, [r0, #0]
+    ldrh r0, [r0, #2]
+    lsls r0, #16
+    orrs r0, r2
+    b 2f
+1:
+    ldr r0, [r0]
+2:
+    ldr r2, =sf_table
+    str r0, [r2, r1]
+    str r0, [sp, #12]
+    pop {r0-r2, pc}
+
+float_section 642float_shims
+
+@ convert uint64 to float, rounding
+regular_func uint642float_shim
+ movs r2,#0       @ fall through
+
+@ convert unsigned 64-bit fix to float, rounding; number of r0:r1 bits after point in r2
+regular_func ufix642float_shim
+ push {r4,r5,r14}
+ cmp r1,#0
+ bpl 3f          @ positive? we can use signed code
+ lsls r5,r1,#31  @ contribution to sticky bits
+ orrs r5,r0
+ lsrs r0,r1,#1
+ subs r2,#1
+ b 4f
+
+@ convert int64 to float, rounding
+regular_func int642float_shim
+ movs r2,#0       @ fall through
+
+@ convert signed 64-bit fix to float, rounding; number of r0:r1 bits after point in r2
+regular_func fix642float_shim
+ push {r4,r5,r14}
+3:
+ movs r5,r0
+ orrs r5,r1
+ beq ret_pop45   @ zero? return +0
+ asrs r5,r1,#31  @ sign bits
+2:
+ asrs r4,r1,#24  @ try shifting 7 bits at a time
+ cmp r4,r5
+ bne 1f          @ next shift will overflow?
+ lsls r1,#7
+ lsrs r4,r0,#25
+ orrs r1,r4
+ lsls r0,#7
+ adds r2,#7
+ b 2b
+1:
+ movs r5,r0
+ movs r0,r1
+4:
+ rsbs r2,#0
+ adds r2,#32+29
+
+ // bl packx
+ ldr r1, =0x29ef // packx
+ blx r1
+ret_pop45:
+ pop {r4,r5,r15}
+
+float_section fatan2_shim
+regular_func fatan2_shim
+ push {r4,r5,r14}
+
+ ldr r4, =0x29c1 // unpackx
+ mov ip, r4
+@ unpack arguments and shift one down to have common exponent
+ blx ip
+ mov r4,r0
+ mov r0,r1
+ mov r1,r4
+ mov r4,r2
+ mov r2,r3
+ mov r3,r4
+ blx ip
+ lsls r0,r0,#5  @ Q28
+ lsls r1,r1,#5  @ Q28
+ adds r4,r2,r3  @ this is -760 if both arguments are 0 and at least -380-126=-506 otherwise
+ asrs r4,#9
+ adds r4,#1
+ bmi 2f         @ force y to 0 proper, so result will be zero
+ subs r4,r2,r3  @ calculate shift
+ bge 1f         @ ex>=ey?
+ rsbs r4,#0     @ make shift positive
+ asrs r0,r4
+ cmp r4,#28
+ blo 3f
+ asrs r0,#31
+ b 3f
+1:
+ asrs r1,r4
+ cmp r4,#28
+ blo 3f
+2:
+@ here |x|>>|y| or both x and y are ±0
+ cmp r0,#0
+ bge 4f         @ x positive, return signed 0
+ ldr r3, =0x2cfc         @ &pi_q29, circular coefficients
+ ldr r0,[r3]    @ x negative, return +/- pi
+ asrs r1,#31
+ eors r0,r1
+ b 7f
+4:
+ asrs r0,r1,#31
+ b 7f
+3:
+ movs r2,#0              @ initial angle
+ ldr r3, =0x2cfc         @ &pi_q29, circular coefficients
+ cmp r0,#0               @ x negative
+ bge 5f
+ rsbs r0,#0              @ rotate to 1st/4th quadrants
+ rsbs r1,#0
+ ldr r2,[r3]             @ pi Q29
+5:
+ movs r4,#1              @ m=1
+ ldr r5, =0x2b97         @ cordic_vec
+ blx r5                  @ also produces magnitude (with scaling factor 1.646760119), which is discarded
+ mov r0,r2               @ result here is -pi/2..3pi/2 Q29
+@ asrs r2,#29
+@ subs r0,r2
+ ldr r3, =0x2cfc         @ &pi_q29, circular coefficients
+ ldr r2,[r3]             @ pi Q29
+ adds r4,r0,r2           @ attempt to fix -3pi/2..-pi case
+ bcs 6f                  @ -pi/2..0? leave result as is
+ subs r4,r0,r2           @ <pi? leave as is
+ bmi 6f
+ subs r0,r4,r2           @ >pi: take off 2pi
+6:
+ subs r0,#1              @ fiddle factor so atan2(0,1)==0
+7:
+ movs r2,#0              @ exponent for pack
+ ldr r3, =0x2b19
+ bx r3
+
+float_section float232_shims
+
+regular_func float2int_shim
+     movs r1,#0                    @ fall through
+regular_func float2fix_shim
+     // check for -0 or -denormal upfront
+     asrs r2, r0, #23
+     adds r2, #128
+     adds r2, #128
+     beq 1f
+     // call original
+     ldr r2, =0x2acd
+     bx r2
+     1:
+     movs r0, #0
+     bx lr
+
+float_section float264_shims
+
+regular_func float2int64_shim
+ movs r1,#0                    @ and fall through
+regular_func float2fix64_shim
+ push {r14}
+ bl f2fix
+ b d2f64_a
+
+regular_func float2uint64_shim
+ movs r1,#0                    @ and fall through
+regular_func float2ufix64_shim
+ asrs r3,r0,#23                @ negative? return 0
+ bmi ret_dzero
+@ and fall through
+
+@ convert float in r0 to signed fixed point in r0:r1:r3, r1 places after point, rounding towards -Inf
+@ result clamped so that r3 can only be 0 or -1
+@ trashes r12
+.thumb_func
+f2fix:
+ push {r4,r14}
+ mov r12,r1
+ asrs r3,r0,#31
+ lsls r0,#1
+ lsrs r2,r0,#24
+ beq 1f                        @ zero?
+ cmp r2,#0xff                  @ Inf?
+ beq 2f
+ subs r1,r2,#1
+ subs r2,#0x7f                 @ remove exponent bias
+ lsls r1,#24
+ subs r0,r1                    @ insert implied 1
+ eors r0,r3
+ subs r0,r3                    @ top two's complement
+ asrs r1,r0,#4                 @ convert to double format
+ lsls r0,#28
+ ldr r4, =d2fix_a
+ bx r4
+1:
+ movs r0,#0
+ movs r1,r0
+ movs r3,r0
+ pop {r4,r15}
+2:
+ mvns r0,r3                    @ return max/min value
+ mvns r1,r3
+ pop {r4,r15}
+
+ret_dzero:
+ movs r0,#0
+ movs r1,#0
+ bx r14
+
+float_section d2fix_a_float
+
+.weak d2fix_a // weak because it exists in float shims too
+.thumb_func
+d2fix_a:
+@ here
+@ r0:r1 two's complement mantissa
+@ r2    unbaised exponent
+@ r3    mantissa sign extension bits
+ add r2,r12                    @ exponent plus offset for required binary point position
+ subs r2,#52                   @ required shift
+ bmi 1f                        @ shift down?
+@ here a shift up by r2 places
+ cmp r2,#12                    @ will clamp?
+ bge 2f
+ movs r4,r0
+ lsls r1,r2
+ lsls r0,r2
+ rsbs r2,#0
+ adds r2,#32                   @ complementary shift
+ lsrs r4,r2
+ orrs r1,r4
+ pop {r4,r15}
+2:
+ mvns r0,r3
+ mvns r1,r3                    @ overflow: clamp to extreme fixed-point values
+ pop {r4,r15}
+1:
+@ here a shift down by -r2 places
+ adds r2,#32
+ bmi 1f                        @ long shift?
+ mov r4,r1
+ lsls r4,r2
+ rsbs r2,#0
+ adds r2,#32                   @ complementary shift
+ asrs r1,r2
+ lsrs r0,r2
+ orrs r0,r4
+ pop {r4,r15}
+1:
+@ here a long shift down
+ movs r0,r1
+ asrs r1,#31                   @ shift down 32 places
+ adds r2,#32
+ bmi 1f                        @ very long shift?
+ rsbs r2,#0
+ adds r2,#32
+ asrs r0,r2
+ pop {r4,r15}
+1:
+ movs r0,r3                    @ result very near zero: use sign extension bits
+ movs r1,r3
+ pop {r4,r15}
+d2f64_a:
+ asrs r2,r1,#31
+ cmp r2,r3
+ bne 1f                        @ sign extension bits fail to match sign of result?
+ pop {r15}
+1:
+ mvns r0,r3
+ movs r1,#1
+ lsls r1,#31
+ eors r1,r1,r0                 @ generate extreme fixed-point values
+ pop {r15}
+
+float_section float2double_shim
+regular_func float2double_shim
+ lsrs r3,r0,#31                @ sign bit
+ lsls r3,#31
+ lsls r1,r0,#1
+ lsrs r2,r1,#24                @ exponent
+ beq 1f                        @ zero?
+ cmp r2,#0xff                  @ Inf?
+ beq 2f
+ lsrs r1,#4                    @ exponent and top 20 bits of mantissa
+ ldr r2,=#(0x3ff-0x7f)<<20     @ difference in exponent offsets
+ adds r1,r2
+ orrs r1,r3
+ lsls r0,#29                   @ bottom 3 bits of mantissa
+ bx r14
+1:
+ movs r1,r3                    @ return signed zero
+3:
+ movs r0,#0
+ bx r14
+2:
+ ldr r1,=#0x7ff00000           @ return signed infinity
+ adds r1,r3
+ b 3b
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_float/include/pico/float.h b/src/rp2_common/pico_float/include/pico/float.h
new file mode 100644
index 0000000..8b06ea8
--- /dev/null
+++ b/src/rp2_common/pico_float/include/pico/float.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_FLOAT_H
+#define _PICO_FLOAT_H
+
+#include <math.h>
+#include <float.h>
+#include "pico/types.h"
+#include "pico/bootrom/sf_table.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file float.h
+* \defgroup pico_float pico_float
+*
+* Optimized single-precision floating point functions
+*
+* (Replacement) optimized implementations are provided of the following compiler built-ins
+* and math library functions:
+*
+* - __aeabi_fadd, __aeabi_fdiv, __aeabi_fmul, __aeabi_frsub, __aeabi_fsub, __aeabi_cfcmpeq, __aeabi_cfrcmple, __aeabi_cfcmple, __aeabi_fcmpeq, __aeabi_fcmplt, __aeabi_fcmple, __aeabi_fcmpge, __aeabi_fcmpgt, __aeabi_fcmpun, __aeabi_i2f, __aeabi_l2f, __aeabi_ui2f, __aeabi_ul2f, __aeabi_f2iz, __aeabi_f2lz, __aeabi_f2uiz, __aeabi_f2ulz, __aeabi_f2d, sqrtf, cosf, sinf, tanf, atan2f, expf, logf
+* - ldexpf, copysignf, truncf, floorf, ceilf, roundf, asinf, acosf, atanf, sinhf, coshf, tanhf, asinhf, acoshf, atanhf, exp2f, log2f, exp10f, log10f, powf, hypotf, cbrtf, fmodf, dremf, remainderf, remquof, expm1f, log1pf, fmaf
+* - powintf, sincosf (GNU extensions)
+*
+* The following additional optimized functions are also provided:
+*
+* - fix2float, ufix2float, fix642float, ufix642float, float2fix, float2ufix, float2fix64, float2ufix64, float2int, float2int64, float2int_z, float2int64_z
+*/
+
+float fix2float(int32_t m, int e);
+float ufix2float(uint32_t m, int e);
+float fix642float(int64_t m, int e);
+float ufix642float(uint64_t m, int e);
+
+// These methods round towards -Infinity.
+int32_t float2fix(float f, int e);
+uint32_t float2ufix(float f, int e);
+int64_t float2fix64(float f, int e);
+uint64_t float2ufix64(float f, int e);
+int32_t float2int(float f);
+int64_t float2int64(float f);
+
+// These methods round towards 0.
+int32_t float2int_z(float f);
+int64_t float2int64_z(float f);
+
+float exp10f(float x);
+void sincosf(float x, float *sinx, float *cosx);
+float powintf(float x, int y);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_int64_ops/CMakeLists.txt b/src/rp2_common/pico_int64_ops/CMakeLists.txt
new file mode 100644
index 0000000..73e7d17
--- /dev/null
+++ b/src/rp2_common/pico_int64_ops/CMakeLists.txt
@@ -0,0 +1,35 @@
+if (NOT TARGET pico_int64_ops)
+
+    #shims for ROM functions for -lgcc functions  (listed below)
+    pico_add_impl_library(pico_int64_ops)
+
+    # no custom implementation; falls thru to compiler
+    pico_add_impl_library(pico_int64_ops_compiler)
+
+    # add alias "default" which is just pico.
+    add_library(pico_int64_ops_default INTERFACE)
+    target_link_libraries(pico_int64_ops_default INTERFACE pico_int64_ops_pico)
+
+    set(PICO_DEFAULT_INT64_OPS_IMPL pico_int64_ops_default)
+
+    target_link_libraries(pico_int64_ops INTERFACE
+            $<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_INT64_OPS_IMPL>>,$<TARGET_PROPERTY:PICO_TARGET_INT64_OPS_IMPL>,${PICO_DEFAULT_INT64_OPS_IMPL}>)
+
+    pico_add_impl_library(pico_int64_ops_pico)
+    target_include_directories(pico_int64_ops_pico INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+    target_sources(pico_int64_ops_pico INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/pico_int64_ops_aeabi.S
+    )
+
+    pico_wrap_function(pico_int64_ops_pico __aeabi_lmul)
+
+    macro(pico_set_int64_ops_implementation TARGET IMPL)
+        get_target_property(target_type ${TARGET} TYPE)
+        if ("EXECUTABLE" STREQUAL "${target_type}")
+            set_target_properties(${TARGET} PROPERTIES PICO_TARGET_INT64_OPS_IMPL "pico_int64_ops_${IMPL}")
+        else()
+            message(FATAL_ERROR "int64_ops implementation must be set on executable not library")
+        endif()
+    endmacro()
+endif()
\ No newline at end of file
diff --git a/src/rp2_common/pico_int64_ops/include/pico/int64_ops.h b/src/rp2_common/pico_int64_ops/include/pico/int64_ops.h
new file mode 100644
index 0000000..db3213e
--- /dev/null
+++ b/src/rp2_common/pico_int64_ops/include/pico/int64_ops.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_INT64_H
+#define _PICO_INT64_H
+
+#include "pico/types.h"
+
+/** \file int64_ops.h
+ *  \defgroup pico_int64_ops pico_int64_ops
+ *
+ * Optimized replacement implementations of the compiler built-in 64 bit multiplication
+ *
+ * This library does not provide any additional functions
+*/
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S b/src/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S
new file mode 100644
index 0000000..0dbc67c
--- /dev/null
+++ b/src/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+#include "pico/asm_helper.S"
+
+#if PICO_INT64_OPS_IN_RAM
+.section RAM_SECTION_NAME(__aeabi_lmul)
+#else
+.section SECTION_NAME(__aeabi_lmul)
+#endif
+wrapper_func __aeabi_lmul
+    muls   r1, r2
+    muls   r3, r0
+    adds   r1, r3
+    mov    r12, r1
+    lsrs   r1, r2, #16
+    uxth   r3, r0
+    muls   r3, r1
+    push   {r4}
+    lsrs   r4, r0, #16
+    muls   r1, r4
+    uxth   r2, r2
+    uxth   r0, r0
+    muls   r0, r2
+    muls   r2, r4
+    lsls   r4, r3, #16
+    lsrs   r3, #16
+    adds   r0, r4
+    pop    {r4}
+    adcs   r1, r3
+    lsls   r3, r2, #16
+    lsrs   r2, #16
+    adds   r0, r3
+    adcs   r1, r2
+    add    r1, r12
+    bx lr
+
diff --git a/src/rp2_common/pico_malloc/CMakeLists.txt b/src/rp2_common/pico_malloc/CMakeLists.txt
new file mode 100644
index 0000000..deeb30f
--- /dev/null
+++ b/src/rp2_common/pico_malloc/CMakeLists.txt
@@ -0,0 +1,16 @@
+if (NOT TARGET pico_malloc)
+    #shims for ROM functions for -lgcc functions  (listed below)
+    pico_add_impl_library(pico_malloc)
+
+    target_sources(pico_malloc INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/pico_malloc.c
+            )
+
+    target_include_directories(pico_malloc INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+    pico_wrap_function(pico_malloc malloc)
+    pico_wrap_function(pico_malloc calloc)
+    pico_wrap_function(pico_malloc free)
+
+    target_link_libraries(pico_malloc INTERFACE pico_sync)
+endif()
diff --git a/src/rp2_common/pico_malloc/include/pico/malloc.h b/src/rp2_common/pico_malloc/include/pico/malloc.h
new file mode 100644
index 0000000..b4ae2b6
--- /dev/null
+++ b/src/rp2_common/pico_malloc/include/pico/malloc.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_MALLOC_H
+#define _PICO_MALLOC_H
+
+/** \file malloc.h
+*  \defgroup pico_malloc pico_malloc
+*
+* Multi-core safety for malloc, calloc and free
+*
+* This library does not provide any additional functions
+*/
+
+// PICO_CONFIG: PICO_USE_MALLOC_MUTEX, Whether to protect malloc etc with a mutex, type=bool, default=1 with pico_multicore, 0 otherwise, group=pico_malloc
+#if LIB_PICO_MULTICORE && !defined(PICO_USE_MALLOC_MUTEX)
+#define PICO_USE_MALLOC_MUTEX 1
+#endif
+
+// PICO_CONFIG: PICO_MALLOC_PANIC, Enable/disable panic when an allocation failure occurs, type=bool, default=1, group=pico_malloc
+#ifndef PICO_MALLOC_PANIC
+#define PICO_MALLOC_PANIC 1
+#endif
+
+// PICO_CONFIG: PICO_DEBUG_MALLOC, Enable/disable debug printf from malloc, type=bool, default=0, group=pico_malloc
+#ifndef PICO_DEBUG_MALLOC
+#define PICO_DEBUG_MALLOC 0
+#endif
+
+// PICO_CONFIG: PICO_DEBUG_MALLOC_LOW_WATER, Define the lower bound for allocation addresses to be printed by PICO_DEBUG_MALLOC, min=0, default=0, group=pico_malloc
+#ifndef PICO_DEBUG_MALLOC_LOW_WATER
+#define PICO_DEBUG_MALLOC_LOW_WATER 0
+#endif
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_malloc/pico_malloc.c b/src/rp2_common/pico_malloc/pico_malloc.c
new file mode 100644
index 0000000..4928a8e
--- /dev/null
+++ b/src/rp2_common/pico_malloc/pico_malloc.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pico.h"
+#include "pico/malloc.h"
+
+#if PICO_USE_MALLOC_MUTEX
+#include "pico/mutex.h"
+auto_init_mutex(malloc_mutex);
+#endif
+
+extern void *__real_malloc(size_t size);
+extern void *__real_calloc(size_t count, size_t size);
+extern void __real_free(void *mem);
+
+extern char __StackLimit; /* Set by linker.  */
+
+static inline void check_alloc(__unused void *mem, __unused uint size) {
+#if PICO_MALLOC_PANIC
+    if (!mem || (((char *)mem) + size) > &__StackLimit) {
+        panic("Out of memory");
+    }
+#endif
+}
+
+void *__wrap_malloc(size_t size) {
+#if PICO_USE_MALLOC_MUTEX
+    mutex_enter_blocking(&malloc_mutex);
+#endif
+    void *rc = __real_malloc(size);
+#if PICO_USE_MALLOC_MUTEX
+    mutex_exit(&malloc_mutex);
+#endif
+#if PICO_DEBUG_MALLOC
+    if (!rc || ((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) {
+        printf("malloc %d %p->%p\n", (uint) size, rc, ((uint8_t *) rc) + size);
+    }
+#endif
+    check_alloc(rc, size);
+    return rc;
+}
+
+void *__wrap_calloc(size_t count, size_t size) {
+#if PICO_USE_MALLOC_MUTEX
+    mutex_enter_blocking(&malloc_mutex);
+#endif
+    void *rc = __real_calloc(count, size);
+#if PICO_USE_MALLOC_MUTEX
+    mutex_exit(&malloc_mutex);
+#endif
+#if PICO_DEBUG_MALLOC
+    if (!rc || ((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) {
+        printf("calloc %d %p->%p\n", (uint) (count * size), rc, ((uint8_t *) rc) + size);
+    }
+#endif
+    check_alloc(rc, size);
+    return rc;
+}
+
+void __wrap_free(void *mem) {
+#if PICO_USE_MALLOC_MUTEX
+    mutex_enter_blocking(&malloc_mutex);
+#endif
+    __real_free(mem);
+#if PICO_USE_MALLOC_MUTEX
+    mutex_exit(&malloc_mutex);
+#endif
+}
diff --git a/src/rp2_common/pico_mem_ops/CMakeLists.txt b/src/rp2_common/pico_mem_ops/CMakeLists.txt
new file mode 100644
index 0000000..997bb20
--- /dev/null
+++ b/src/rp2_common/pico_mem_ops/CMakeLists.txt
@@ -0,0 +1,42 @@
+if (NOT TARGET pico_mem_ops)
+    #shims for ROM functions for -lgcc functions  (listed below)
+    pico_add_impl_library(pico_mem_ops)
+
+    # no custom implementation; falls thru to compiler
+    pico_add_impl_library(pico_mem_ops_compiler)
+
+    # add alias "default" which is just pico.
+    add_library(pico_mem_ops_default INTERFACE)
+    target_link_libraries(pico_mem_ops_default INTERFACE pico_mem_ops_pico)
+
+    set(PICO_DEFAULT_MEM_OPS_IMPL pico_mem_ops_default)
+
+    pico_add_impl_library(pico_mem_ops_pico)
+    target_link_libraries(pico_mem_ops INTERFACE
+            $<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_MEM_OPS_IMPL>>,$<TARGET_PROPERTY:PICO_TARGET_MEM_OPS_IMPL>,${PICO_DEFAULT_MEM_OPS_IMPL}>)
+
+    target_sources(pico_mem_ops_pico INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/mem_ops_aeabi.S
+            )
+
+
+    target_link_libraries(pico_mem_ops INTERFACE pico_bootrom)
+
+    pico_wrap_function(pico_mem_ops_pico memcpy)
+    pico_wrap_function(pico_mem_ops_pico memset)
+    pico_wrap_function(pico_mem_ops_pico __aeabi_memcpy)
+    pico_wrap_function(pico_mem_ops_pico __aeabi_memset)
+    pico_wrap_function(pico_mem_ops_pico __aeabi_memcpy4)
+    pico_wrap_function(pico_mem_ops_pico __aeabi_memset4)
+    pico_wrap_function(pico_mem_ops_pico __aeabi_memcpy8)
+    pico_wrap_function(pico_mem_ops_pico __aeabi_memset8)
+
+    macro(pico_set_mem_ops_implementation TARGET IMPL)
+        get_target_property(target_type ${TARGET} TYPE)
+        if ("EXECUTABLE" STREQUAL "${target_type}")
+            set_target_properties(${TARGET} PROPERTIES PICO_TARGET_MEM_OPS_IMPL "pico_mem_ops_${IMPL}")
+        else()
+            message(FATAL_ERROR "mem_ops implementation must be set on executable not library")
+        endif()
+    endmacro()
+endif()
diff --git a/src/rp2_common/pico_mem_ops/include/pico/mem_ops.h b/src/rp2_common/pico_mem_ops/include/pico/mem_ops.h
new file mode 100644
index 0000000..0c224fb
--- /dev/null
+++ b/src/rp2_common/pico_mem_ops/include/pico/mem_ops.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_MEMORY_H
+#define _PICO_MEMORY_H
+
+#include "pico/types.h"
+
+/** \file mem_ops.h
+ *  \defgroup pico_mem_ops pico_mem_ops
+ *
+ * Provides optimized replacement implementations of the compiler built-in memcpy, memset and related functions:
+ *
+ * - memset, memcpy
+ * - __aeabi_memset, __aeabi_memset4, __aeabi_memset8, __aeabi_memcpy, __aeabi_memcpy4, __aeabi_memcpy8
+ *
+ * This library does not provide any additional functions
+ */
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_mem_ops/mem_ops.c b/src/rp2_common/pico_mem_ops/mem_ops.c
new file mode 100644
index 0000000..4047d23
--- /dev/null
+++ b/src/rp2_common/pico_mem_ops/mem_ops.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/mem_ops.h"
diff --git a/src/rp2_common/pico_mem_ops/mem_ops_aeabi.S b/src/rp2_common/pico_mem_ops/mem_ops_aeabi.S
new file mode 100644
index 0000000..8540905
--- /dev/null
+++ b/src/rp2_common/pico_mem_ops/mem_ops_aeabi.S
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+#include "pico/asm_helper.S"
+#include "pico/bootrom.h"
+
+__pre_init __aeabi_mem_init, 00001
+
+.macro mem_section name
+#if PICO_MEM_IN_RAM
+.section RAM_SECTION_NAME(\name), "ax"
+#else
+.section SECTION_NAME(\name), "ax"
+#endif
+.endm
+
+.equ MEMSET, 0
+.equ MEMCPY, 4
+.equ MEMSET4, 8
+.equ MEMCPY4, 12
+.equ MEM_FUNC_COUNT, 4
+
+# NOTE: All code sections are placed in RAM (at the expense of some veneer cost for calls from flash) because
+#       otherwise code using basic c division operators will require XIP flash access.
+
+.section .data.aeabi_mem_funcs
+.global aeabi_mem_funcs, aeabi_mem_funcs_end
+
+.align 2
+aeabi_mem_funcs:
+    .word ROM_FUNC_MEMSET
+    .word ROM_FUNC_MEMCPY
+    .word ROM_FUNC_MEMSET4
+    .word ROM_FUNC_MEMCPY44
+aeabi_mem_funcs_end:
+
+.section .text
+regular_func __aeabi_mem_init
+    ldr r0, =aeabi_mem_funcs
+    movs r1, #MEM_FUNC_COUNT
+    ldr r3, =rom_funcs_lookup
+    bx r3
+
+# lump them both together because likely both to be used, in which case doing so saves 1 word
+# and it only costs 1 word if not
+
+// Note from Run-time ABI for the ARM architecture 4.3.4:
+// If there is an attached device with efficient memory copying or clearing operations
+// (such as a DMA engine), its device supplement specifies whether it may be used in
+// implementations of these functions and what effect such use has on the device’s state.
+
+mem_section aeabi_memset_memcpy
+
+wrapper_func __aeabi_memset
+    // 2nd/3rd args are reversed
+    eors r2, r1
+    eors r1, r2
+    eors r2, r1
+    ldr r3, =aeabi_mem_funcs
+    ldr r3, [r3, #MEMSET]
+    bx r3
+
+wrapper_func __aeabi_memset4
+wrapper_func __aeabi_memset8
+    // 2nd/3rd args are reversed
+    eors r2, r1
+    eors r1, r2
+    eors r2, r1
+    ldr r3, =aeabi_mem_funcs
+    ldr r3, [r3, #MEMSET4]
+    bx r3
+
+wrapper_func __aeabi_memcpy4
+wrapper_func __aeabi_memcpy8
+    ldr r3, =aeabi_mem_funcs
+    ldr r3, [r3, #MEMCPY4]
+    bx r3
+
+mem_section memset
+
+wrapper_func memset
+    ldr r3, =aeabi_mem_funcs
+    ldr r3, [r3, #MEMSET]
+    bx r3
+
+mem_section memcpy
+wrapper_func __aeabi_memcpy
+wrapper_func memcpy
+    ldr r3, =aeabi_mem_funcs
+    ldr r3, [r3, #MEMCPY]
+    bx r3
+
diff --git a/src/rp2_common/pico_multicore/CMakeLists.txt b/src/rp2_common/pico_multicore/CMakeLists.txt
new file mode 100644
index 0000000..2401061
--- /dev/null
+++ b/src/rp2_common/pico_multicore/CMakeLists.txt
@@ -0,0 +1,13 @@
+if (NOT TARGET pico_multicore)
+    pico_add_impl_library(pico_multicore)
+
+    target_sources(pico_multicore INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/multicore.c)
+
+    target_include_directories(pico_multicore INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+    target_link_libraries(pico_multicore INTERFACE pico_sync hardware_irq)
+endif()
+
+
+
diff --git a/src/rp2_common/pico_multicore/include/pico/multicore.h b/src/rp2_common/pico_multicore/include/pico/multicore.h
new file mode 100644
index 0000000..6f12f41
--- /dev/null
+++ b/src/rp2_common/pico_multicore/include/pico/multicore.h
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_MULTICORE_H
+#define _PICO_MULTICORE_H
+
+#include "pico/types.h"
+#include "pico/sync.h"
+#include "hardware/structs/sio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file multicore.h
+ *  \defgroup pico_multicore pico_multicore
+ * Adds support for running code on the second processor core (core 1)
+ *
+ * \subsection multicore_example Example
+ * \addtogroup pico_multicore
+ * \include multicore.c
+*/
+
+// PICO_CONFIG: PICO_CORE1_STACK_SIZE, Stack size for core 1, min=0x100, max=0x10000, default=PICO_STACK_SIZE (0x800), group=pico_multicore
+#ifndef PICO_CORE1_STACK_SIZE
+#ifdef PICO_STACK_SIZE
+#define PICO_CORE1_STACK_SIZE PICO_STACK_SIZE
+#else
+#define PICO_CORE1_STACK_SIZE 0x800
+#endif
+#endif
+
+/*! \brief  Reset core 1
+ *  \ingroup pico_multicore
+ *
+ * This function can be used to reset core 1 into its initial state (ready for launching code against via \ref multicore_launch_core1 and similar methods)
+ *
+ * \note this function should only be called from core 0
+ */
+void multicore_reset_core1(void);
+
+/*! \brief  Run code on core 1
+ *  \ingroup pico_multicore
+ *
+ * Wake up (a previously reset) core 1 and enter the given function on core 1 using the default core 1 stack (below core 0 stack).
+ *
+ * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1
+ *
+ * core 1 will use the same vector table as core 0
+ *
+ * \param entry Function entry point
+ * \see multicore_reset_core1
+ */
+void multicore_launch_core1(void (*entry)(void));
+
+/*! \brief  Launch code on core 1 with stack
+ *  \ingroup pico_multicore
+ *
+ * Wake up (a previously reset) core 1 and enter the given function on core 1 using the passed stack for core 1
+ *
+ * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1
+ *
+ * core 1 will use the same vector table as core 0
+ *
+ * \param entry Function entry point
+ * \param stack_bottom The bottom (lowest address) of the stack
+ * \param stack_size_bytes The size of the stack in bytes (must be a multiple of 4)
+ * \see multicore_reset_core1
+ */
+void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes);
+
+/*! \brief  Launch code on core 1 with no stack protection
+ *  \ingroup pico_multicore
+ *
+ * Wake up (a previously reset) core 1 and start it executing with a specific entry point, stack pointer
+ * and vector table.
+ *
+ * This is a low level function that does not provide a stack guard even if USE_STACK_GUARDS is defined
+ *
+ * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1
+ *
+ * \param entry Function entry point
+ * \param sp Pointer to the top of the core 1 stack
+ * \param vector_table address of the vector table to use for core 1
+ * \see multicore_reset_core1
+ */
+void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table);
+
+/*!
+ * \defgroup multicore_fifo fifo
+ * \ingroup pico_multicore
+ * \brief Functions for the inter-core FIFOs
+ *
+ * The RP2040 contains two FIFOs for passing data, messages or ordered events between the two cores. Each FIFO is 32 bits
+ * wide, and 8 entries deep. One of the FIFOs can only be written by core 0, and read by core 1. The other can only be written
+ * by core 1, and read by core 0.
+ *
+ * \note The inter-core FIFOs are a very precious resource and are frequently used for SDK functionality (e.g. during
+ * core 1 launch or by the \ref multicore_lockout functions). Additionally they are often required for the exclusive use
+ * of an RTOS (e.g. FreeRTOS SMP). For these reasons it is suggested that you do not use the FIFO for your own purposes
+ * unless none of the above concerns apply; the majority of cases for transferring data between cores can be eqaully
+ * well handled  by using a \ref queue
+ */
+
+/*! \brief Check the read FIFO to see if there is data available (sent by the other core)
+ *  \ingroup multicore_fifo
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ * \return true if the FIFO has data in it, false otherwise
+ */
+static inline bool multicore_fifo_rvalid(void) {
+    return !!(sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS);
+}
+
+/*! \brief Check the write FIFO to see if it has space for more data
+ *  \ingroup multicore_fifo
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ *  @return true if the FIFO has room for more data, false otherwise
+ */
+static inline bool multicore_fifo_wready(void) {
+    return !!(sio_hw->fifo_st & SIO_FIFO_ST_RDY_BITS);
+}
+
+/*! \brief Push data on to the write FIFO (data to the other core).
+ *  \ingroup multicore_fifo
+ *
+ * This function will block until there is space for the data to be sent.
+ * Use multicore_fifo_wready() to check if it is possible to write to the
+ * FIFO if you don't want to block.
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ * \param data A 32 bit value to push on to the FIFO
+ */
+void multicore_fifo_push_blocking(uint32_t data);
+
+/*! \brief Push data on to the write FIFO (data to the other core) with timeout.
+ *  \ingroup multicore_fifo
+ *
+ * This function will block until there is space for the data to be sent
+ * or the timeout is reached
+ *
+ * \param data A 32 bit value to push on to the FIFO
+ * \param timeout_us the timeout in microseconds
+ * \return true if the data was pushed, false if the timeout occurred before data could be pushed
+ */
+bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us);
+
+/*! \brief Pop data from the read FIFO (data from the other core).
+ *  \ingroup multicore_fifo
+ *
+ * This function will block until there is data ready to be read
+ * Use multicore_fifo_rvalid() to check if data is ready to be read if you don't
+ * want to block.
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ * \return 32 bit data from the read FIFO.
+ */
+uint32_t multicore_fifo_pop_blocking(void);
+
+/*! \brief Pop data from the read FIFO (data from the other core) with timeout.
+ *  \ingroup multicore_fifo
+ *
+ * This function will block until there is data ready to be read or the timeout is reached
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ * \param timeout_us the timeout in microseconds
+ * \param out the location to store the popped data if available
+ * \return true if the data was popped and a value copied into `out`, false if the timeout occurred before data could be popped
+ */
+bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out);
+
+/*! \brief Discard any data in the read FIFO
+ *  \ingroup multicore_fifo
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ */
+static inline void multicore_fifo_drain(void) {
+    while (multicore_fifo_rvalid())
+        (void) sio_hw->fifo_rd;
+}
+
+/*! \brief Clear FIFO interrupt
+ *  \ingroup multicore_fifo
+ *
+ * Note that this only clears an interrupt that was caused by the ROE or WOF flags.
+ * To clear the VLD flag you need to use one of the 'pop' or 'drain' functions.
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ * \see multicore_fifo_get_status
+*/
+static inline void multicore_fifo_clear_irq(void) {
+    // Write any value to clear the error flags
+    sio_hw->fifo_st = 0xff;
+}
+
+/*! \brief Get FIFO statuses
+ *  \ingroup multicore_fifo
+ *
+ * \return The statuses as a bitfield
+ *
+ * Bit | Description
+ * ----|------------
+ * 3 | Sticky flag indicating the RX FIFO was read when empty (ROE). This read was ignored by the FIFO.
+ * 2 | Sticky flag indicating the TX FIFO was written when full (WOF). This write was ignored by the FIFO.
+ * 1 | Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR is ready for more data)
+ * 0 | Value is 1 if this core’s RX FIFO is not empty (i.e. if FIFO_RD is valid)
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+*/
+static inline uint32_t multicore_fifo_get_status(void) {
+    return sio_hw->fifo_st;
+}
+
+/*!
+ * \defgroup multicore_lockout lockout
+ * \ingroup pico_multicore
+ * \brief Functions to enable one core to force the other core to pause execution in a known state.
+ *
+ * Sometimes it is useful to enter a critical section on both cores at once. On a single
+ * core system a critical section can trivially be entered by disabling interrupts, however on a multi-core
+ * system that is not sufficient, and unless the other core is polling in some way, then it will need to be interrupted
+ * in order to cooperatively enter a blocked state.
+ *
+ * These "lockout" functions use the inter core FIFOs to cause an interrupt on one core from the other, and manage
+ * waiting for the other core to enter the "locked out" state.
+ *
+ * The usage is that the "victim" core ... i.e the core that can be "locked out" by the other core calls
+ * \ref multicore_lockout_victim_init to hook the FIFO interrupt. Note that either or both cores may do this.
+ *
+ * \note When "locked out" the victim core is paused (it is actually executing a tight loop with code in RAM) and has interrupts disabled.
+ * This makes the lockout functions suitable for use by code that wants to write to flash (at which point no code may be executing
+ * from flash)
+ *
+ * The core which wishes to lockout the other core calls \ref multicore_lockout_start_blocking or
+ * \ref multicore_lockout_start_timeout_us to interrupt the other "victim" core and wait for it to be in a
+ * "locked out" state. Once the lockout is no longer needed it calls \ref multicore_lockout_end_blocking or
+ * \ref multicore_lockout_end_timeout_us to release the lockout and wait for confirmation.
+ *
+ * \note Because multicore lockout uses the intercore FIFOs, the FIFOs <b>cannot</b> be used for any other purpose
+ */
+
+/*! \brief Initialize the current core such that it can be a "victim" of lockout (i.e. forced to pause in a known state by the other core)
+ *  \ingroup multicore_lockout
+ *
+ * This code hooks the intercore FIFO IRQ, and the FIFO may not be used for any other purpose after this.
+ */
+void multicore_lockout_victim_init(void);
+
+/*! \brief Request the other core to pause in a known state and wait for it to do so
+ *  \ingroup multicore_lockout
+ *
+ * The other (victim) core must have previously executed \ref multicore_lockout_victim_init()
+ *
+ * \note multicore_lockout_start_ functions are not nestable, and must be paired with a call to a corresponding
+ * \ref multicore_lockout_end_blocking
+ */
+void multicore_lockout_start_blocking(void);
+
+/*! \brief Request the other core to pause in a known state and wait up to a time limit for it to do so
+ *  \ingroup multicore_lockout
+ *
+ * The other core must have previously executed \ref multicore_lockout_victim_init()
+ *
+ * \note multicore_lockout_start_ functions are not nestable, and must be paired with a call to a corresponding
+ * \ref multicore_lockout_end_blocking
+ *
+ * \param timeout_us the timeout in microseconds
+ * \return true if the other core entered the locked out state within the timeout, false otherwise
+ */
+bool multicore_lockout_start_timeout_us(uint64_t timeout_us);
+
+/*! \brief Release the other core from a locked out state amd wait for it to acknowledge
+ *  \ingroup multicore_lockout
+ *
+ * \note The other core must previously have been "locked out" by calling a `multicore_lockout_start_` function
+ * from this core
+ */
+void multicore_lockout_end_blocking(void);
+
+/*! \brief Release the other core from a locked out state amd wait up to a time limit for it to acknowledge
+ *  \ingroup multicore_lockout
+ *
+ * The other core must previously have been "locked out" by calling a `multicore_lockout_start_` function
+ * from this core
+ *
+ * \note be very careful using small timeout values, as a timeout here will leave the "lockout" functionality
+ * in a bad state. It is probably preferable to use \ref multicore_lockout_end_blocking anyway as if you have
+ * already waited for the victim core to enter the lockout state, then the victim core will be ready to exit
+ * the lockout state very quickly.
+ *
+ * \param timeout_us the timeout in microseconds
+ * \return true if the other core successfully exited locked out state within the timeout, false otherwise
+ */
+bool multicore_lockout_end_timeout_us(uint64_t timeout_us);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/src/rp2_common/pico_multicore/multicore.c b/src/rp2_common/pico_multicore/multicore.c
new file mode 100644
index 0000000..121b4fb
--- /dev/null
+++ b/src/rp2_common/pico_multicore/multicore.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/multicore.h"
+#include "hardware/sync.h"
+#include "hardware/irq.h"
+#include "hardware/structs/scb.h"
+#include "hardware/structs/sio.h"
+#include "hardware/regs/psm.h"
+#include "hardware/claim.h"
+#if PICO_USE_STACK_GUARDS
+#include "pico/runtime.h"
+#endif
+
+static inline void multicore_fifo_push_blocking_inline(uint32_t data) {
+    // We wait for the fifo to have some space
+    while (!multicore_fifo_wready())
+        tight_loop_contents();
+
+    sio_hw->fifo_wr = data;
+
+    // Fire off an event to the other core
+    __sev();
+}
+
+void multicore_fifo_push_blocking(uint32_t data) {
+    multicore_fifo_push_blocking_inline(data);
+}
+
+bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us) {
+    absolute_time_t end_time = make_timeout_time_us(timeout_us);
+    // We wait for the fifo to have some space
+    while (!multicore_fifo_wready()) {
+        tight_loop_contents();
+        if (time_reached(end_time)) return false;
+    }
+
+    sio_hw->fifo_wr = data;
+
+    // Fire off an event to the other core
+    __sev();
+    return true;
+}
+
+static inline uint32_t multicore_fifo_pop_blocking_inline(void) {
+    // If nothing there yet, we wait for an event first,
+    // to try and avoid too much busy waiting
+    while (!multicore_fifo_rvalid())
+        __wfe();
+
+    return sio_hw->fifo_rd;
+}
+
+uint32_t multicore_fifo_pop_blocking() {
+    return multicore_fifo_pop_blocking_inline();
+}
+
+bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out) {
+    absolute_time_t end_time = make_timeout_time_us(timeout_us);
+    // If nothing there yet, we wait for an event first,
+    // to try and avoid too much busy waiting
+    while (!multicore_fifo_rvalid()) {
+        __wfe();
+        if (time_reached(end_time)) return false;
+    }
+
+    *out = sio_hw->fifo_rd;
+    return true;
+}
+
+// Default stack for core1 ... if multicore_launch_core1 is not included then .stack1 section will be garbage collected
+static uint32_t __attribute__((section(".stack1"))) core1_stack[PICO_CORE1_STACK_SIZE / sizeof(uint32_t)];
+
+static void __attribute__ ((naked)) core1_trampoline(void) {
+    __asm("pop {r0, r1, pc}");
+}
+
+int core1_wrapper(int (*entry)(void), void *stack_base) {
+#if PICO_USE_STACK_GUARDS
+    // install core1 stack guard
+    runtime_install_stack_guard(stack_base);
+#else
+    __unused void *ignore = stack_base;
+#endif
+    irq_init_priorities();
+    return (*entry)();
+}
+
+void multicore_reset_core1() {
+    // Use atomic aliases just in case core 1 is also manipulating some PSM state
+    io_rw_32 *power_off = (io_rw_32 *) (PSM_BASE + PSM_FRCE_OFF_OFFSET);
+    io_rw_32 *power_off_set = hw_set_alias(power_off);
+    io_rw_32 *power_off_clr = hw_clear_alias(power_off);
+
+    // Hard-reset core 1.
+    // Reading back confirms the core 1 reset is in the correct state, but also
+    // forces APB IO bridges to fence on any internal store buffering
+    *power_off_set = PSM_FRCE_OFF_PROC1_BITS;
+    while (!(*power_off & PSM_FRCE_OFF_PROC1_BITS)) tight_loop_contents();
+
+    // Bring core 1 back out of reset. It will drain its own mailbox FIFO, then push
+    // a 0 to our mailbox to tell us it has done this.
+    *power_off_clr = PSM_FRCE_OFF_PROC1_BITS;
+}
+
+void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes) {
+    assert(!(stack_size_bytes & 3u));
+    uint32_t *stack_ptr = stack_bottom + stack_size_bytes / sizeof(uint32_t);
+    // push 2 values onto top of stack for core1_trampoline
+    stack_ptr -= 3;
+    stack_ptr[0] = (uintptr_t) entry;
+    stack_ptr[1] = (uintptr_t) stack_bottom;
+    stack_ptr[2] = (uintptr_t) core1_wrapper;
+    multicore_launch_core1_raw(core1_trampoline, stack_ptr, scb_hw->vtor);
+}
+
+void multicore_launch_core1(void (*entry)(void)) {
+    extern uint32_t __StackOneBottom;
+    uint32_t *stack_limit = (uint32_t *) &__StackOneBottom;
+    // hack to reference core1_stack although that pointer is wrong.... core1_stack should always be <= stack_limit, if not boom!
+    uint32_t *stack = core1_stack <= stack_limit ? stack_limit : (uint32_t *) -1;
+    multicore_launch_core1_with_stack(entry, stack, sizeof(core1_stack));
+}
+
+void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table) {
+    // Allow for the fact that the caller may have already enabled the FIFO IRQ for their
+    // own purposes (expecting FIFO content after core 1 is launched). We must disable
+    // the IRQ during the handshake, then restore afterwards.
+    bool enabled = irq_is_enabled(SIO_IRQ_PROC0);
+    irq_set_enabled(SIO_IRQ_PROC0, false);
+
+    // Values to be sent in order over the FIFO from core 0 to core 1
+    //
+    // vector_table is value for VTOR register
+    // sp is initial stack pointer (SP)
+    // entry is the initial program counter (PC) (don't forget to set the thumb bit!)
+    const uint32_t cmd_sequence[] =
+            {0, 0, 1, (uintptr_t) vector_table, (uintptr_t) sp, (uintptr_t) entry};
+
+    uint seq = 0;
+    do {
+        uint cmd = cmd_sequence[seq];
+        // Always drain the READ FIFO (from core 1) before sending a 0
+        if (!cmd) {
+            multicore_fifo_drain();
+            // Execute a SEV as core 1 may be waiting for FIFO space via WFE
+            __sev();
+        }
+        multicore_fifo_push_blocking(cmd);
+        uint32_t response = multicore_fifo_pop_blocking();
+        // Move to next state on correct response (echo-d value) otherwise start over
+        seq = cmd == response ? seq + 1 : 0;
+    } while (seq < count_of(cmd_sequence));
+
+    irq_set_enabled(SIO_IRQ_PROC0, enabled);
+}
+
+#define LOCKOUT_MAGIC_START 0x73a8831eu
+#define LOCKOUT_MAGIC_END (~LOCKOUT_MAGIC_START)
+
+static_assert(SIO_IRQ_PROC1 == SIO_IRQ_PROC0 + 1, "");
+
+static mutex_t lockout_mutex;
+static bool lockout_in_progress;
+
+// note this method is in RAM because lockout is used when writing to flash
+// it only makes inline calls
+static void __isr __not_in_flash_func(multicore_lockout_handler)(void) {
+    multicore_fifo_clear_irq();
+    while (multicore_fifo_rvalid()) {
+        if (sio_hw->fifo_rd == LOCKOUT_MAGIC_START) {
+            uint32_t save = save_and_disable_interrupts();
+            multicore_fifo_push_blocking_inline(LOCKOUT_MAGIC_START);
+            while (multicore_fifo_pop_blocking_inline() != LOCKOUT_MAGIC_END) {
+                tight_loop_contents(); // not tight but endless potentially
+            }
+            restore_interrupts(save);
+            multicore_fifo_push_blocking_inline(LOCKOUT_MAGIC_END);
+        }
+    }
+}
+
+static void check_lockout_mutex_init(void) {
+    // use known available lock - we only need it briefly
+    uint32_t save = hw_claim_lock();
+    if (!mutex_is_initialized(&lockout_mutex)) {
+        mutex_init(&lockout_mutex);
+    }
+    hw_claim_unlock(save);
+}
+
+void multicore_lockout_victim_init() {
+    check_lockout_mutex_init();
+    uint core_num = get_core_num();
+    irq_set_exclusive_handler(SIO_IRQ_PROC0 + core_num, multicore_lockout_handler);
+    irq_set_enabled(SIO_IRQ_PROC0 + core_num, true);
+}
+
+static bool multicore_lockout_handshake(uint32_t magic, absolute_time_t until) {
+    uint irq_num = SIO_IRQ_PROC0 + get_core_num();
+    bool enabled = irq_is_enabled(irq_num);
+    if (enabled) irq_set_enabled(irq_num, false);
+    bool rc = false;
+    do {
+        int64_t next_timeout_us = absolute_time_diff_us(get_absolute_time(), until);
+        if (next_timeout_us < 0) {
+            break;
+        }
+        multicore_fifo_push_timeout_us(magic, (uint64_t)next_timeout_us);
+        next_timeout_us = absolute_time_diff_us(get_absolute_time(), until);
+        if (next_timeout_us < 0) {
+            break;
+        }
+        uint32_t word = 0;
+        if (!multicore_fifo_pop_timeout_us((uint64_t)next_timeout_us, &word)) {
+            break;
+        }
+        if (word == magic) {
+            rc = true;
+        }
+    } while (!rc);
+    if (enabled) irq_set_enabled(irq_num, true);
+    return rc;
+}
+
+static bool multicore_lockout_start_block_until(absolute_time_t until) {
+    check_lockout_mutex_init();
+    if (!mutex_enter_block_until(&lockout_mutex, until)) {
+        return false;
+    }
+    hard_assert(!lockout_in_progress);
+    bool rc = multicore_lockout_handshake(LOCKOUT_MAGIC_START, until);
+    lockout_in_progress = rc;
+    mutex_exit(&lockout_mutex);
+    return rc;
+}
+
+bool multicore_lockout_start_timeout_us(uint64_t timeout_us) {
+    return multicore_lockout_start_block_until(make_timeout_time_us(timeout_us));
+}
+
+void multicore_lockout_start_blocking() {
+    multicore_lockout_start_block_until(at_the_end_of_time);
+}
+
+static bool multicore_lockout_end_block_until(absolute_time_t until) {
+    assert(mutex_is_initialized(&lockout_mutex));
+    if (!mutex_enter_block_until(&lockout_mutex, until)) {
+        return false;
+    }
+    assert(lockout_in_progress);
+    bool rc = multicore_lockout_handshake(LOCKOUT_MAGIC_END, until);
+    if (rc) {
+        lockout_in_progress = false;
+    }
+    mutex_exit(&lockout_mutex);
+    return rc;
+}
+
+bool multicore_lockout_end_timeout_us(uint64_t timeout_us) {
+    return multicore_lockout_end_block_until(make_timeout_time_us(timeout_us));
+}
+
+void multicore_lockout_end_blocking() {
+    multicore_lockout_end_block_until(at_the_end_of_time);
+}
diff --git a/src/rp2_common/pico_platform/CMakeLists.txt b/src/rp2_common/pico_platform/CMakeLists.txt
new file mode 100644
index 0000000..8a6f1d2
--- /dev/null
+++ b/src/rp2_common/pico_platform/CMakeLists.txt
@@ -0,0 +1,25 @@
+if (NOT TARGET pico_platform_headers)
+    add_library(pico_platform_headers INTERFACE)
+
+    target_compile_definitions(pico_platform_headers INTERFACE
+            PICO_NO_HARDWARE=0
+            PICO_ON_DEVICE=1
+            PICO_BUILD=1
+    )
+
+    target_include_directories(pico_platform_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+    target_link_libraries(pico_platform_headers INTERFACE hardware_regs)
+endif()
+
+if (NOT TARGET pico_platform)
+    pico_add_impl_library(pico_platform)
+    target_sources(pico_platform INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/platform.c)
+
+    target_link_libraries(pico_platform INTERFACE pico_platform_headers)
+endif()
+
+function(pico_add_platform_library TARGET)
+    target_link_libraries(pico_platform INTERFACE ${TARGET})
+endfunction()
\ No newline at end of file
diff --git a/src/rp2_common/pico_platform/include/pico/asm_helper.S b/src/rp2_common/pico_platform/include/pico/asm_helper.S
new file mode 100644
index 0000000..3e01c66
--- /dev/null
+++ b/src/rp2_common/pico_platform/include/pico/asm_helper.S
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+
+// do not put align in here as it is used mid function sometimes
+.macro regular_func x
+.global \x
+.type \x,%function
+.thumb_func
+\x:
+.endm
+
+.macro regular_func_with_section x
+.section .text.\x
+regular_func \x
+.endm
+
+// do not put align in here as it is used mid function sometimes
+.macro wrapper_func x
+regular_func WRAPPER_FUNC_NAME(\x)
+.endm
+
+.macro __pre_init func, priority_string
+.section .preinit_array.\priority_string
+.align 2
+.word \func
+.endm
+
diff --git a/src/rp2_common/pico_platform/include/pico/platform.h b/src/rp2_common/pico_platform/include/pico/platform.h
new file mode 100644
index 0000000..ee1d360
--- /dev/null
+++ b/src/rp2_common/pico_platform/include/pico/platform.h
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_PLATFORM_H_
+#define _PICO_PLATFORM_H_
+
+/** \file platform.h
+ *  \defgroup pico_platform pico_platform
+ *
+ * Macros and definitions (and functions when included by non assembly code) for the RP2 family device / architecture
+ * to provide a common abstraction over low level compiler / platform specifics.
+ *
+ * This header may be included by assembly code
+ */
+
+#include "hardware/platform_defs.h"
+
+// Marker for builds targeting the RP2040
+#define PICO_RP2040 1
+
+// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_platform
+#ifndef PICO_STACK_SIZE
+#define PICO_STACK_SIZE _u(0x800)
+#endif
+
+// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_platform
+#ifndef PICO_HEAP_SIZE
+#define PICO_HEAP_SIZE _u(0x800)
+#endif
+
+// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_platform
+#ifndef PICO_NO_RAM_VECTOR_TABLE
+#define PICO_NO_RAM_VECTOR_TABLE 0
+#endif
+
+// PICO_CONFIG: PICO_RP2040_B0_SUPPORTED, Whether to include any specific software support for RP2040 B0 revision, type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 1
+#endif
+
+// PICO_CONFIG: PICO_FLOAT_SUPPORT_ROM_V1, Include float support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#define PICO_FLOAT_SUPPORT_ROM_V1 1
+#endif
+
+// PICO_CONFIG: PICO_DOUBLE_SUPPORT_ROM_V1, Include double support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
+#define PICO_DOUBLE_SUPPORT_ROM_V1 1
+#endif
+
+
+// PICO_CONFIG: PICO_RP2040_B1_SUPPORTED, Whether to include any specific software support for RP2040 B1 revision, type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_RP2040_B1_SUPPORTED
+#define PICO_RP2040_B1_SUPPORTED 1
+#endif
+
+// PICO_CONFIG: PICO_RP2040_B2_SUPPORTED, Whether to include any specific software support for RP2040 B2 revision, type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_RP2040_B2_SUPPORTED
+#define PICO_RP2040_B2_SUPPORTED 1
+#endif
+
+// --- remainder of file is not included by assembly code ---
+
+#ifndef __ASSEMBLER__
+
+#include <sys/cdefs.h>
+#include "pico/types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Marker for an interrupt handler
+ *  \ingroup pico_platform
+ * For example an IRQ handler function called my_interrupt_handler:
+ *
+ *     void __isr my_interrupt_handler(void) {
+ */
+#define __isr
+
+/*! \brief Section attribute macro for placement in RAM after the `.data` section
+ *  \ingroup pico_platform
+ *
+ * For example a 400 element `uint32_t` array placed after the .data section
+ *
+ *     uint32_t __after_data("my_group_name") a_big_array[400];
+ *
+ * The section attribute is `.after_data.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ *              garbage-collected independently
+ */
+#define __after_data(group) __attribute__((section(".after_data." group)))
+
+/*! \brief Section attribute macro for placement not in flash (i.e in RAM)
+ *  \ingroup pico_platform
+ *
+ * For example a 3 element `uint32_t` array placed in RAM (even though it is `static const`)
+ *
+ *     static const uint32_t __not_in_flash("my_group_name") an_array[3];
+ *
+ * The section attribute is `.time_critical.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ *              garbage-collected independently
+ */
+#define __not_in_flash(group) __attribute__((section(".time_critical." group)))
+
+/*! \brief Section attribute macro for placement in the SRAM bank 4 (known as "scratch X")
+ *  \ingroup pico_platform
+ *
+ * Scratch X is commonly used for critical data and functions accessed only by one core (when only
+ * one core is accessing the RAM bank, there is no opportunity for stalls)
+ *
+ * For example a `uint32_t` variable placed in "scratch X"
+ *
+ *     uint32_t __scratch_x("my_group_name") foo = 23;
+ *
+ * The section attribute is `.scratch_x.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ *              garbage-collected independently
+ */
+#define __scratch_x(group) __attribute__((section(".scratch_x." group)))
+
+/*! \brief Section attribute macro for placement in the SRAM bank 5 (known as "scratch Y")
+ *  \ingroup pico_platform
+ *
+ * Scratch Y is commonly used for critical data and functions accessed only by one core (when only
+ * one core is accessing the RAM bank, there is no opportunity for stalls)
+ *
+ * For example a `uint32_t` variable placed in "scratch Y"
+ *
+ *     uint32_t __scratch_y("my_group_name") foo = 23;
+ *
+ * The section attribute is `.scratch_y.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ *              garbage-collected independently
+ */
+#define __scratch_y(group) __attribute__((section(".scratch_y." group)))
+
+/*! \brief Section attribute macro for data that is to be left uninitialized
+ *  \ingroup pico_platform
+ *
+ * Data marked this way will retain its value across a reset (normally uninitialized data - in the .bss
+ * section) is initialized to zero during runtime initialization
+ *
+ * For example a `uint32_t` foo that will retain its value if the program is restarted by reset.
+ *
+ *     uint32_t __uninitialized_ram("my_group_name") foo;
+ *
+ * The section attribute is `.uninitialized_ram.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ *              garbage-collected independently
+ */
+#define __uninitialized_ram(group) __attribute__((section(".uninitialized_ram." #group))) group
+
+/*! \brief Section attribute macro for placement in flash even in a COPY_TO_RAM binary
+ *  \ingroup pico_platform
+ *
+ * For example a `uint32_t` variable explicitly placed in flash (it will hard fault if you attempt to write it!)
+ *
+ *     uint32_t __in_flash("my_group_name") foo = 23;
+ *
+ * The section attribute is `.flashdata.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ *              garbage-collected independently
+ */
+#define __in_flash(group) __attribute__((section(".flashdata" group)))
+
+/*! \brief Indicates a function should not be stored in flash
+ *  \ingroup pico_platform
+ *
+ * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined
+ * into a flash function by the compiler)
+ *
+ * For example a function called my_func taking an int parameter:
+ *
+ *     void __not_in_flash_func(my_func)(int some_arg) {
+ *
+ * The function is placed in the `.time_critical.<func_name>` linker section
+ *
+ * \see __no_inline_not_in_flash_func
+ */
+#define __not_in_flash_func(func_name) __not_in_flash(__STRING(func_name)) func_name
+
+/*! \brief Indicates a function is time/latency critical and should not run from flash
+ *  \ingroup pico_platform
+ *
+ * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined
+ * into a flash function by the compiler) to avoid possible flash latency. Currently this macro is identical
+ * in implementation to `__not_in_flash_func`, however the semantics are distinct and a `__time_critical_func`
+ * may in the future be treated more specially to reduce the overhead when calling such function from a flash
+ * function.
+ *
+ * For example a function called my_func taking an int parameter:
+ *
+ *     void __time_critical(my_func)(int some_arg) {
+ *
+ * The function is placed in the `.time_critical.<func_name>` linker section
+ *
+ * \see __not_in_flash_func
+ */
+#define __time_critical_func(func_name) __not_in_flash_func(func_name)
+
+/*! \brief Indicate a function should not be stored in flash and should not be inlined
+ *  \ingroup pico_platform
+ *
+ * Decorates a function name, such that the function will execute from RAM, explicitly marking it as
+ * noinline to prevent it being inlined into a flash function by the compiler
+ *
+ * For example a function called my_func taking an int parameter:
+ *
+ *     void __no_inline_not_in_flash_func(my_func)(int some_arg) {
+ *
+ * The function is placed in the `.time_critical.<func_name>` linker section
+ */
+#define __no_inline_not_in_flash_func(func_name) __noinline __not_in_flash_func(func_name)
+
+#define __packed_aligned __packed __aligned(4)
+
+/*! \brief Attribute to force inlining of a function regardless of optimization level
+ *  \ingroup pico_platform
+ *
+ *  For example my_function here will always be inlined:
+ *
+ *      int __force_inline my_function(int x) {
+ *
+ */
+#if defined(__GNUC__) && __GNUC__ <= 7
+#define __force_inline inline __always_inline
+#else
+#define __force_inline __always_inline
+#endif
+
+/*! \brief Macro to determine the number of elements in an array
+ *  \ingroup pico_platform
+ */
+#ifndef count_of
+#define count_of(a) (sizeof(a)/sizeof((a)[0]))
+#endif
+
+/*! \brief Macro to return the maximum of two comparable values
+ *  \ingroup pico_platform
+ */
+#ifndef MAX
+#define MAX(a, b) ((a)>(b)?(a):(b))
+#endif
+
+/*! \brief Macro to return the minimum of two comparable values
+ *  \ingroup pico_platform
+ */
+#ifndef MIN
+#define MIN(a, b) ((b)>(a)?(a):(b))
+#endif
+
+/*! \brief Execute a breakpoint instruction
+ *  \ingroup pico_platform
+ */
+static inline void __breakpoint(void) {
+    __asm__("bkpt #0");
+}
+
+/*! \brief Ensure that the compiler does not move memory access across this method call
+ *  \ingroup pico_platform
+ *
+ *  For example in the following code:
+ *
+ *      *some_memory_location = var_a;
+ *      __compiler_memory_barrier();
+ *      uint32_t var_b = *some_other_memory_location
+ *
+ * The compiler will not move the load from `some_other_memory_location` above the memory barrier (which it otherwise
+ * might - even above the memory store!)
+ */
+__force_inline static void __compiler_memory_barrier(void) {
+    __asm__ volatile ("" : : : "memory");
+}
+
+/*! \brief Macro for converting memory addresses to 32 bit addresses suitable for DMA
+ *  \ingroup pico_platform
+ *
+ *  This is just a cast to `uintptr_t` on the RP2040, however you may want to use this when developing code
+ *  that also runs in "host" mode. If the host mode is 64 bit and you are embedding data pointers
+ *  in other data (e.g. DMA chaining), then there is a need in "host" mode to convert a 64 bit native
+ *  pointer to a 32 bit value for storage, which can be done using this macro.
+ */
+#define host_safe_hw_ptr(x) ((uintptr_t)(x))
+#define native_safe_hw_ptr(x) host_safe_hw_ptr(x)
+
+
+/*! \brief Panics with the message "Unsupported"
+ *  \ingroup pico_platform
+ *  \see panic
+ */
+void __attribute__((noreturn)) panic_unsupported(void);
+
+/*! \brief Displays a panic message and halts execution
+ *  \ingroup pico_platform
+ *
+ * An attempt is made to output the message to all registered STDOUT drivers
+ * after which this method executes a BKPT instruction.
+ *
+ * @param fmt format string (printf-like)
+ * @param ...  printf-like arguments
+ */
+void __attribute__((noreturn)) panic(const char *fmt, ...);
+
+// PICO_CONFIG: PICO_NO_FPGA_CHECK, Remove the FPGA platform check for small code size reduction, type=bool, default=0, advanced=true, group=pico_runtime
+#ifndef PICO_NO_FPGA_CHECK
+#define PICO_NO_FPGA_CHECK 0
+#endif
+
+#if PICO_NO_FPGA_CHECK
+static inline bool running_on_fpga(void) {return false;}
+#else
+bool running_on_fpga(void);
+#endif
+
+/*! \brief Returns the RP2040 chip revision number
+ *  \ingroup pico_platform
+ * @return the RP2040 chip revision number (1 for B0/B1, 2 for B2)
+ */
+uint8_t rp2040_chip_version(void);
+
+/*! \brief Returns the RP2040 rom version number
+ *  \ingroup pico_platform
+ * @return the RP2040 rom version number (1 for RP2040-B0, 2 for RP2040-B1, 3 for RP2040-B2)
+ */
+static inline uint8_t rp2040_rom_version(void) {
+    return *(uint8_t*)0x13;
+}
+
+/*! \brief No-op function for the body of tight loops
+ *  \ingroup pico_platform
+ *
+ * Np-op function intended to be called by any tight hardware polling loop. Using this ubiquitously
+ * makes it much easier to find tight loops, but also in the future \#ifdef-ed support for lockup
+ * debugging might be added
+ */
+static __force_inline void tight_loop_contents(void) {}
+
+/*! \brief Multiply two integers using an assembly `MUL` instruction
+ *  \ingroup pico_platform
+ *
+ * This multiplies a by b using multiply instruction using the ARM mul instruction regardless of values (the compiler
+ * might otherwise choose to perform shifts/adds), i.e. this is a 1 cycle operation.
+ *
+ * \param a the first operand
+ * \param b the second operand
+ * \return a * b
+ */
+__force_inline static int32_t __mul_instruction(int32_t a, int32_t b) {
+    asm ("mul %0, %1" : "+l" (a) : "l" (b) : );
+    return a;
+}
+
+/*! \brief multiply two integer values using the fastest method possible
+ *  \ingroup pico_platform
+ *
+ * Efficiently multiplies value a by possibly constant value b.
+ *
+ * If b is known to be constant and not zero or a power of 2, then a mul instruction is used rather than gcc's default
+ * which is often a slow combination of shifts and adds. If b is a power of 2 then a single shift is of course preferable
+ * and will be used
+ *
+ * \param a the first operand
+ * \param b the second operand
+ * \return a * b
+ */
+#define __fast_mul(a, b) __builtin_choose_expr(__builtin_constant_p(b) && !__builtin_constant_p(a), \
+(__builtin_popcount(b) >= 2 ? __mul_instruction(a,b) : (a)*(b)), \
+(a)*(b))
+
+/*! \brief Utility macro to assert two types are equivalent.
+ *  \ingroup pico_platform
+ *
+ *  This macro can be useful in other macros along with `typeof` to assert that two parameters are of equivalent type
+ *  (or that a single parameter is of an expected type)
+ */
+#define __check_type_compatible(type_a, type_b) static_assert(__builtin_types_compatible_p(type_a, type_b), __STRING(type_a) " is not compatible with " __STRING(type_b));
+
+/*! \brief Get the current exception level on this core
+ *  \ingroup pico_platform
+ *
+ * \return the exception number if the CPU is handling an exception, or 0 otherwise
+ */
+uint __get_current_exception(void);
+
+#define WRAPPER_FUNC(x) __wrap_ ## x
+#define REAL_FUNC(x) __real_ ## x
+
+#ifdef __cplusplus
+}
+#endif
+
+#else // __ASSEMBLER__
+
+#define WRAPPER_FUNC_NAME(x) __wrap_##x
+#define SECTION_NAME(x) .text.##x
+#define RAM_SECTION_NAME(x) .time_critical.##x
+
+#endif // !__ASSEMBLER__
+
+#endif
diff --git a/src/rp2_common/pico_platform/platform.c b/src/rp2_common/pico_platform/platform.c
new file mode 100644
index 0000000..9bbcf26
--- /dev/null
+++ b/src/rp2_common/pico_platform/platform.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+#include "hardware/address_mapped.h"
+#include "hardware/regs/tbman.h"
+#include "hardware/regs/sysinfo.h"
+
+// Note we leave the FPGA check in by default so that we can run bug repro
+// binaries coming in from the wild on the FPGA platform. It takes up around
+// 48 bytes if you include all the calls, so you can pass PICO_NO_FPGA_CHECK=1
+// to remove it. The FPGA check is used to skip initialisation of hardware
+// (mainly clock generators and oscillators) that aren't present on FPGA.
+
+#if !PICO_NO_FPGA_CHECK
+// Inline stub provided in header if this code is unused (so folding can be
+// done in each TU instead of relying on LTO)
+bool running_on_fpga() {
+    return !!((*(io_ro_32 *)TBMAN_BASE) & TBMAN_PLATFORM_FPGA_BITS);
+}
+#endif
+
+#define MANUFACTURER_RPI 0x927
+#define PART_RP2 0x2
+
+uint8_t rp2040_chip_version() {
+    // First register of sysinfo is chip id
+    uint32_t chip_id = *((io_ro_32*)(SYSINFO_BASE + SYSINFO_CHIP_ID_OFFSET));
+    uint32_t __unused manufacturer = chip_id & SYSINFO_CHIP_ID_MANUFACTURER_BITS;
+    uint32_t __unused part = (chip_id & SYSINFO_CHIP_ID_PART_BITS) >> SYSINFO_CHIP_ID_PART_LSB;
+    assert(manufacturer == MANUFACTURER_RPI);
+    assert(part == PART_RP2);
+    // Version 1 == B0/B1
+    uint version = (chip_id & SYSINFO_CHIP_ID_REVISION_BITS) >> SYSINFO_CHIP_ID_REVISION_LSB;
+    return (uint8_t)version;
+}
\ No newline at end of file
diff --git a/src/rp2_common/pico_printf/CMakeLists.txt b/src/rp2_common/pico_printf/CMakeLists.txt
new file mode 100644
index 0000000..989dcd1
--- /dev/null
+++ b/src/rp2_common/pico_printf/CMakeLists.txt
@@ -0,0 +1,52 @@
+if (NOT TARGET pico_printf)
+    # library to be depended on - we make this depend on particular implementations using per target generator expressions
+    pico_add_impl_library(pico_printf)
+
+    # no custom implementation; falls thru to compiler
+    pico_add_impl_library(pico_printf_compiler)
+
+    add_library(pico_printf_headers INTERFACE)
+    target_include_directories(pico_printf_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+    # add alias "default" which is just pico.
+    add_library(pico_printf_default INTERFACE)
+    target_link_libraries(pico_printf_default INTERFACE pico_printf_pico)
+
+    set(PICO_DEFAULT_PRINTF_IMPL pico_printf_default)
+
+    target_link_libraries(pico_printf INTERFACE
+            $<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_PRINTF_IMPL>>,$<TARGET_PROPERTY:PICO_TARGET_PRINTF_IMPL>,${PICO_DEFAULT_PRINTF_IMPL}>)
+
+    pico_add_impl_library(pico_printf_pico)
+    target_sources(pico_printf_pico INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/printf.c
+    )
+
+    target_link_libraries(pico_printf_pico INTERFACE pico_printf_headers)
+
+    pico_add_impl_library(pico_printf_none)
+    target_sources(pico_printf_none INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/printf_none.S
+    )
+
+    target_link_libraries(pico_printf_none INTERFACE pico_printf_headers)
+
+    function(wrap_printf_functions TARGET)
+        # note that printf and vprintf are in pico_stdio so we can provide thread safety
+        pico_wrap_function(${TARGET} sprintf)
+        pico_wrap_function(${TARGET} snprintf)
+        pico_wrap_function(${TARGET} vsnprintf)
+    endfunction()
+
+    wrap_printf_functions(pico_printf_pico)
+    wrap_printf_functions(pico_printf_none)
+
+    macro(pico_set_printf_implementation TARGET IMPL)
+        get_target_property(target_type ${TARGET} TYPE)
+        if ("EXECUTABLE" STREQUAL "${target_type}")
+            set_target_properties(${TARGET} PROPERTIES PICO_TARGET_PRINTF_IMPL "pico_printf_${IMPL}")
+        else()
+            message(FATAL_ERROR "printf implementation must be set on executable not library")
+        endif()
+    endmacro()
+endif()
diff --git a/src/rp2_common/pico_printf/include/pico/printf.h b/src/rp2_common/pico_printf/include/pico/printf.h
new file mode 100644
index 0000000..25cea48
--- /dev/null
+++ b/src/rp2_common/pico_printf/include/pico/printf.h
@@ -0,0 +1,93 @@
+///////////////////////////////////////////////////////////////////////////////
+// \author (c) Marco Paland (info@paland.com)
+//             2014-2019, PALANDesign Hannover, Germany
+//
+// \license The MIT License (MIT)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+// 
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+// 
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+// \brief Tiny printf, sprintf and snprintf implementation, optimized for speed on
+//        embedded systems with a very limited resources.
+//        Use this instead of bloated standard/newlib printf.
+//        These routines are thread safe and reentrant.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#ifndef PICO_PRINTF_H_
+#define PICO_PRINTF_H_
+
+/** \file printf.h
+ *  \defgroup pico_printf pico_printf
+ *
+ * Compact replacement for printf by Marco Paland (info@paland.com)
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "pico.h"
+#include <stdio.h>
+#include <stdarg.h>
+
+// PICO_CONFIG: PICO_PRINTF_ALWAYS_INCLUDED, Whether to always include printf code even if only called weakly (by panic), type=bool, default=1 in debug build 0 otherwise, group=pico_printf
+#ifndef PICO_PRINTF_ALWAYS_INCLUDED
+#ifndef NDEBUG
+#define PICO_PRINTF_ALWAYS_INCLUDED 1
+#else
+#define PICO_PRINTF_ALWAYS_INCLUDED 0
+#endif
+#endif
+
+#if LIB_PICO_PRINTF_PICO
+// weak raw printf may be a puts if printf has not been called,
+// so that we can support gc of printf when it isn't called
+//
+// it is called raw to distinguish it from the regular printf which
+// is in stdio.c and does mutex protection
+#if !PICO_PRINTF_ALWAYS_INCLUDED
+bool __printflike(1, 0) weak_raw_printf(const char *fmt, ...);
+bool weak_raw_vprintf(const char *fmt, va_list args);
+#else
+#define weak_raw_printf(...) ({printf(__VA_ARGS__); true;})
+#define weak_raw_vprintf(fmt,va) ({vprintf(fmt,va); true;})
+#endif
+
+/**
+ * printf with output function
+ * You may use this as dynamic alternative to printf() with its fixed _putchar() output
+ * \param out An output function which takes one character and an argument pointer
+ * \param arg An argument pointer for user data passed to output function
+ * \param format A string that specifies the format of the output
+ * \return The number of characters that are sent to the output function, not counting the terminating null character
+ */
+int vfctprintf(void (*out)(char character, void *arg), void *arg, const char *format, va_list va);
+
+#else
+
+#define weak_raw_printf(...) ({printf(__VA_ARGS__); true;})
+#define weak_raw_vprintf(fmt,va) ({vprintf(fmt,va); true;})
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // _PRINTF_H_
diff --git a/src/rp2_common/pico_printf/printf.c b/src/rp2_common/pico_printf/printf.c
new file mode 100644
index 0000000..2594c57
--- /dev/null
+++ b/src/rp2_common/pico_printf/printf.c
@@ -0,0 +1,942 @@
+///////////////////////////////////////////////////////////////////////////////
+// \author (c) Marco Paland (info@paland.com)
+//             2014-2019, PALANDesign Hannover, Germany
+//
+// \license The MIT License (MIT)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+// \brief Tiny printf, sprintf and (v)snprintf implementation, optimized for speed on
+//        embedded systems with a very limited resources. These routines are thread
+//        safe and reentrant!
+//        Use this instead of the bloated standard/newlib printf cause these use
+//        malloc for printf (and may not be thread safe).
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+
+#include "pico/platform.h"
+#include "pico/printf.h"
+
+// PICO_CONFIG: PICO_PRINTF_NTOA_BUFFER_SIZE, Define printf ntoa buffer size, min=0, max=128, default=32, group=pico_printf
+// 'ntoa' conversion buffer size, this must be big enough to hold one converted
+// numeric number including padded zeros (dynamically created on stack)
+#ifndef PICO_PRINTF_NTOA_BUFFER_SIZE
+#define PICO_PRINTF_NTOA_BUFFER_SIZE    32U
+#endif
+
+// PICO_CONFIG: PICO_PRINTF_FTOA_BUFFER_SIZE, Define printf ftoa buffer size, min=0, max=128, default=32, group=pico_printf
+// 'ftoa' conversion buffer size, this must be big enough to hold one converted
+// float number including padded zeros (dynamically created on stack)
+#ifndef PICO_PRINTF_FTOA_BUFFER_SIZE
+#define PICO_PRINTF_FTOA_BUFFER_SIZE    32U
+#endif
+
+// PICO_CONFIG: PICO_PRINTF_SUPPORT_FLOAT, Enable floating point printing, type=bool, default=1, group=pico_printf
+// support for the floating point type (%f)
+#ifndef PICO_PRINTF_SUPPORT_FLOAT
+#define PICO_PRINTF_SUPPORT_FLOAT 1
+#endif
+
+// PICO_CONFIG: PICO_PRINTF_SUPPORT_EXPONENTIAL, Enable exponential floating point printing, type=bool, default=1, group=pico_printf
+// support for exponential floating point notation (%e/%g)
+#ifndef PICO_PRINTF_SUPPORT_EXPONENTIAL
+#define PICO_PRINTF_SUPPORT_EXPONENTIAL 1
+#endif
+
+// PICO_CONFIG: PICO_PRINTF_DEFAULT_FLOAT_PRECISION, Define default floating point precision, min=1, max=16, default=6, group=pico_printf
+#ifndef PICO_PRINTF_DEFAULT_FLOAT_PRECISION
+#define PICO_PRINTF_DEFAULT_FLOAT_PRECISION  6U
+#endif
+
+// PICO_CONFIG: PICO_PRINTF_MAX_FLOAT, Define the largest float suitable to print with %f, min=1, max=1e9, default=1e9, group=pico_printf
+#ifndef PICO_PRINTF_MAX_FLOAT
+#define PICO_PRINTF_MAX_FLOAT  1e9
+#endif
+
+// PICO_CONFIG: PICO_PRINTF_SUPPORT_LONG_LONG, Enable support for long long types (%llu or %p), type=bool, default=1, group=pico_printf
+#ifndef PICO_PRINTF_SUPPORT_LONG_LONG
+#define PICO_PRINTF_SUPPORT_LONG_LONG 1
+#endif
+
+// PICO_CONFIG: PICO_PRINTF_SUPPORT_PTRDIFF_T, Enable support for the ptrdiff_t type (%t), type=bool, default=1, group=pico_printf
+// ptrdiff_t is normally defined in <stddef.h> as long or long long type
+#ifndef PICO_PRINTF_SUPPORT_PTRDIFF_T
+#define PICO_PRINTF_SUPPORT_PTRDIFF_T 1
+#endif
+
+///////////////////////////////////////////////////////////////////////////////
+
+// internal flag definitions
+#define FLAGS_ZEROPAD   (1U <<  0U)
+#define FLAGS_LEFT      (1U <<  1U)
+#define FLAGS_PLUS      (1U <<  2U)
+#define FLAGS_SPACE     (1U <<  3U)
+#define FLAGS_HASH      (1U <<  4U)
+#define FLAGS_UPPERCASE (1U <<  5U)
+#define FLAGS_CHAR      (1U <<  6U)
+#define FLAGS_SHORT     (1U <<  7U)
+#define FLAGS_LONG      (1U <<  8U)
+#define FLAGS_LONG_LONG (1U <<  9U)
+#define FLAGS_PRECISION (1U << 10U)
+#define FLAGS_ADAPT_EXP (1U << 11U)
+
+// import float.h for DBL_MAX
+#if PICO_PRINTF_SUPPORT_FLOAT
+
+#include <float.h>
+
+#endif
+
+/**
+ * Output a character to a custom device like UART, used by the printf() function
+ * This function is declared here only. You have to write your custom implementation somewhere
+ * \param character Character to output
+ */
+static void _putchar(char character) {
+    putchar(character);
+}
+
+// output function type
+typedef void (*out_fct_type)(char character, void *buffer, size_t idx, size_t maxlen);
+
+#if !PICO_PRINTF_ALWAYS_INCLUDED
+// we don't have a way to specify a truly weak symbol reference (the linker will always include targets in a single link step,
+// so we make a function pointer that is initialized on the first printf called... if printf is not included in the binary
+// (or has never been called - we can't tell) then this will be null. the assumption is that if you are using printf
+// you are likely to have printed something.
+static int (*lazy_vsnprintf)(out_fct_type out, char *buffer, const size_t maxlen, const char *format, va_list va);
+#endif
+
+// wrapper (used as buffer) for output function type
+typedef struct {
+    void (*fct)(char character, void *arg);
+    void *arg;
+} out_fct_wrap_type;
+
+// internal buffer output
+static inline void _out_buffer(char character, void *buffer, size_t idx, size_t maxlen) {
+    if (idx < maxlen) {
+        ((char *) buffer)[idx] = character;
+    }
+}
+
+// internal null output
+static inline void _out_null(char character, void *buffer, size_t idx, size_t maxlen) {
+    (void) character;
+    (void) buffer;
+    (void) idx;
+    (void) maxlen;
+}
+
+// internal _putchar wrapper
+static inline void _out_char(char character, void *buffer, size_t idx, size_t maxlen) {
+    (void) buffer;
+    (void) idx;
+    (void) maxlen;
+    if (character) {
+        _putchar(character);
+    }
+}
+
+
+// internal output function wrapper
+static inline void _out_fct(char character, void *buffer, size_t idx, size_t maxlen) {
+    (void) idx;
+    (void) maxlen;
+    if (character) {
+        // buffer is the output fct pointer
+        ((out_fct_wrap_type *) buffer)->fct(character, ((out_fct_wrap_type *) buffer)->arg);
+    }
+}
+
+
+// internal secure strlen
+// \return The length of the string (excluding the terminating 0) limited by 'maxsize'
+static inline unsigned int _strnlen_s(const char *str, size_t maxsize) {
+    const char *s;
+    for (s = str; *s && maxsize--; ++s);
+    return (unsigned int) (s - str);
+}
+
+
+// internal test if char is a digit (0-9)
+// \return true if char is a digit
+static inline bool _is_digit(char ch) {
+    return (ch >= '0') && (ch <= '9');
+}
+
+
+// internal ASCII string to unsigned int conversion
+static unsigned int _atoi(const char **str) {
+    unsigned int i = 0U;
+    while (_is_digit(**str)) {
+        i = i * 10U + (unsigned int) (*((*str)++) - '0');
+    }
+    return i;
+}
+
+
+// output the specified string in reverse, taking care of any zero-padding
+static size_t _out_rev(out_fct_type out, char *buffer, size_t idx, size_t maxlen, const char *buf, size_t len,
+                       unsigned int width, unsigned int flags) {
+    const size_t start_idx = idx;
+
+    // pad spaces up to given width
+    if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) {
+        for (size_t i = len; i < width; i++) {
+            out(' ', buffer, idx++, maxlen);
+        }
+    }
+
+    // reverse string
+    while (len) {
+        out(buf[--len], buffer, idx++, maxlen);
+    }
+
+    // append pad spaces up to given width
+    if (flags & FLAGS_LEFT) {
+        while (idx - start_idx < width) {
+            out(' ', buffer, idx++, maxlen);
+        }
+    }
+
+    return idx;
+}
+
+
+// internal itoa format
+static size_t _ntoa_format(out_fct_type out, char *buffer, size_t idx, size_t maxlen, char *buf, size_t len,
+                           bool negative, unsigned int base, unsigned int prec, unsigned int width,
+                           unsigned int flags) {
+    // pad leading zeros
+    if (!(flags & FLAGS_LEFT)) {
+        if (width && (flags & FLAGS_ZEROPAD) && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) {
+            width--;
+        }
+        while ((len < prec) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) {
+            buf[len++] = '0';
+        }
+        while ((flags & FLAGS_ZEROPAD) && (len < width) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) {
+            buf[len++] = '0';
+        }
+    }
+
+    // handle hash
+    if (flags & FLAGS_HASH) {
+        if (!(flags & FLAGS_PRECISION) && len && ((len == prec) || (len == width))) {
+            len--;
+            if (len && (base == 16U)) {
+                len--;
+            }
+        }
+        if ((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) {
+            buf[len++] = 'x';
+        } else if ((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) {
+            buf[len++] = 'X';
+        } else if ((base == 2U) && (len < PICO_PRINTF_NTOA_BUFFER_SIZE)) {
+            buf[len++] = 'b';
+        }
+        if (len < PICO_PRINTF_NTOA_BUFFER_SIZE) {
+            buf[len++] = '0';
+        }
+    }
+
+    if (len < PICO_PRINTF_NTOA_BUFFER_SIZE) {
+        if (negative) {
+            buf[len++] = '-';
+        } else if (flags & FLAGS_PLUS) {
+            buf[len++] = '+';  // ignore the space if the '+' exists
+        } else if (flags & FLAGS_SPACE) {
+            buf[len++] = ' ';
+        }
+    }
+
+    return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags);
+}
+
+
+// internal itoa for 'long' type
+static size_t _ntoa_long(out_fct_type out, char *buffer, size_t idx, size_t maxlen, unsigned long value, bool negative,
+                         unsigned long base, unsigned int prec, unsigned int width, unsigned int flags) {
+    char buf[PICO_PRINTF_NTOA_BUFFER_SIZE];
+    size_t len = 0U;
+
+    // no hash for 0 values
+    if (!value) {
+        flags &= ~FLAGS_HASH;
+    }
+
+    // write if precision != 0 and value is != 0
+    if (!(flags & FLAGS_PRECISION) || value) {
+        do {
+            const char digit = (char) (value % base);
+            buf[len++] = (char)(digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10);
+            value /= base;
+        } while (value && (len < PICO_PRINTF_NTOA_BUFFER_SIZE));
+    }
+
+    return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int) base, prec, width, flags);
+}
+
+
+// internal itoa for 'long long' type
+#if PICO_PRINTF_SUPPORT_LONG_LONG
+
+static size_t _ntoa_long_long(out_fct_type out, char *buffer, size_t idx, size_t maxlen, unsigned long long value,
+                              bool negative, unsigned long long base, unsigned int prec, unsigned int width,
+                              unsigned int flags) {
+    char buf[PICO_PRINTF_NTOA_BUFFER_SIZE];
+    size_t len = 0U;
+
+    // no hash for 0 values
+    if (!value) {
+        flags &= ~FLAGS_HASH;
+    }
+
+    // write if precision != 0 and value is != 0
+    if (!(flags & FLAGS_PRECISION) || value) {
+        do {
+            const char digit = (char) (value % base);
+            buf[len++] = (char)(digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10);
+            value /= base;
+        } while (value && (len < PICO_PRINTF_NTOA_BUFFER_SIZE));
+    }
+
+    return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int) base, prec, width, flags);
+}
+
+#endif  // PICO_PRINTF_SUPPORT_LONG_LONG
+
+
+#if PICO_PRINTF_SUPPORT_FLOAT
+
+#if PICO_PRINTF_SUPPORT_EXPONENTIAL
+// forward declaration so that _ftoa can switch to exp notation for values > PICO_PRINTF_MAX_FLOAT
+static size_t _etoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, double value, unsigned int prec,
+                    unsigned int width, unsigned int flags);
+#endif
+
+#define is_nan __builtin_isnan
+
+// internal ftoa for fixed decimal floating point
+static size_t _ftoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, double value, unsigned int prec,
+                    unsigned int width, unsigned int flags) {
+    char buf[PICO_PRINTF_FTOA_BUFFER_SIZE];
+    size_t len = 0U;
+    double diff = 0.0;
+
+    // powers of 10
+    static const double pow10[] = {1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000};
+
+    // test for special values
+    if (is_nan(value))
+        return _out_rev(out, buffer, idx, maxlen, "nan", 3, width, flags);
+    if (value < -DBL_MAX)
+        return _out_rev(out, buffer, idx, maxlen, "fni-", 4, width, flags);
+    if (value > DBL_MAX)
+        return _out_rev(out, buffer, idx, maxlen, (flags & FLAGS_PLUS) ? "fni+" : "fni", (flags & FLAGS_PLUS) ? 4U : 3U,
+                        width, flags);
+
+    // test for very large values
+    // standard printf behavior is to print EVERY whole number digit -- which could be 100s of characters overflowing your buffers == bad
+    if ((value > PICO_PRINTF_MAX_FLOAT) || (value < -PICO_PRINTF_MAX_FLOAT)) {
+#if PICO_PRINTF_SUPPORT_EXPONENTIAL
+        return _etoa(out, buffer, idx, maxlen, value, prec, width, flags);
+#else
+        return 0U;
+#endif
+    }
+
+    // test for negative
+    bool negative = false;
+    if (value < 0) {
+        negative = true;
+        value = 0 - value;
+    }
+
+    // set default precision, if not set explicitly
+    if (!(flags & FLAGS_PRECISION)) {
+        prec = PICO_PRINTF_DEFAULT_FLOAT_PRECISION;
+    }
+    // limit precision to 9, cause a prec >= 10 can lead to overflow errors
+    while ((len < PICO_PRINTF_FTOA_BUFFER_SIZE) && (prec > 9U)) {
+        buf[len++] = '0';
+        prec--;
+    }
+
+    int whole = (int) value;
+    double tmp = (value - whole) * pow10[prec];
+    unsigned long frac = (unsigned long) tmp;
+    diff = tmp - frac;
+
+    if (diff > 0.5) {
+        ++frac;
+        // handle rollover, e.g. case 0.99 with prec 1 is 1.0
+        if (frac >= pow10[prec]) {
+            frac = 0;
+            ++whole;
+        }
+    } else if (diff < 0.5) {
+    } else if ((frac == 0U) || (frac & 1U)) {
+        // if halfway, round up if odd OR if last digit is 0
+        ++frac;
+    }
+
+    if (prec == 0U) {
+        diff = value - (double) whole;
+        if (!((diff < 0.5) || (diff > 0.5)) && (whole & 1)) {
+            // exactly 0.5 and ODD, then round up
+            // 1.5 -> 2, but 2.5 -> 2
+            ++whole;
+        }
+    } else {
+        unsigned int count = prec;
+        // now do fractional part, as an unsigned number
+        while (len < PICO_PRINTF_FTOA_BUFFER_SIZE) {
+            --count;
+            buf[len++] = (char) (48U + (frac % 10U));
+            if (!(frac /= 10U)) {
+                break;
+            }
+        }
+        // add extra 0s
+        while ((len < PICO_PRINTF_FTOA_BUFFER_SIZE) && (count-- > 0U)) {
+            buf[len++] = '0';
+        }
+        if (len < PICO_PRINTF_FTOA_BUFFER_SIZE) {
+            // add decimal
+            buf[len++] = '.';
+        }
+    }
+
+    // do whole part, number is reversed
+    while (len < PICO_PRINTF_FTOA_BUFFER_SIZE) {
+        buf[len++] = (char) (48 + (whole % 10));
+        if (!(whole /= 10)) {
+            break;
+        }
+    }
+
+    // pad leading zeros
+    if (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD)) {
+        if (width && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) {
+            width--;
+        }
+        while ((len < width) && (len < PICO_PRINTF_FTOA_BUFFER_SIZE)) {
+            buf[len++] = '0';
+        }
+    }
+
+    if (len < PICO_PRINTF_FTOA_BUFFER_SIZE) {
+        if (negative) {
+            buf[len++] = '-';
+        } else if (flags & FLAGS_PLUS) {
+            buf[len++] = '+';  // ignore the space if the '+' exists
+        } else if (flags & FLAGS_SPACE) {
+            buf[len++] = ' ';
+        }
+    }
+
+    return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags);
+}
+
+
+#if PICO_PRINTF_SUPPORT_EXPONENTIAL
+
+// internal ftoa variant for exponential floating-point type, contributed by Martijn Jasperse <m.jasperse@gmail.com>
+static size_t _etoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, double value, unsigned int prec,
+                    unsigned int width, unsigned int flags) {
+    // check for NaN and special values
+    if (is_nan(value) || (value > DBL_MAX) || (value < -DBL_MAX)) {
+        return _ftoa(out, buffer, idx, maxlen, value, prec, width, flags);
+    }
+
+    // determine the sign
+    const bool negative = value < 0;
+    if (negative) {
+        value = -value;
+    }
+
+    // default precision
+    if (!(flags & FLAGS_PRECISION)) {
+        prec = PICO_PRINTF_DEFAULT_FLOAT_PRECISION;
+    }
+
+    // determine the decimal exponent
+    // based on the algorithm by David Gay (https://www.ampl.com/netlib/fp/dtoa.c)
+    union {
+        uint64_t U;
+        double F;
+    } conv;
+
+    conv.F = value;
+    int expval;
+    if (conv.U) {
+        int exp2 = (int) ((conv.U >> 52U) & 0x07FFU) - 1023;           // effectively log2
+        conv.U = (conv.U & ((1ULL << 52U) - 1U)) | (1023ULL << 52U);  // drop the exponent so conv.F is now in [1,2)
+        // now approximate log10 from the log2 integer part and an expansion of ln around 1.5
+        expval = (int) (0.1760912590558 + exp2 * 0.301029995663981 + (conv.F - 1.5) * 0.289529654602168);
+        // now we want to compute 10^expval but we want to be sure it won't overflow
+        exp2 = (int) (expval * 3.321928094887362 + 0.5);
+        const double z = expval * 2.302585092994046 - exp2 * 0.6931471805599453;
+        const double z2 = z * z;
+        conv.U = (uint64_t) (exp2 + 1023) << 52U;
+        // compute exp(z) using continued fractions, see https://en.wikipedia.org/wiki/Exponential_function#Continued_fractions_for_ex
+        conv.F *= 1 + 2 * z / (2 - z + (z2 / (6 + (z2 / (10 + z2 / 14)))));
+        // correct for rounding errors
+        if (value < conv.F) {
+            expval--;
+            conv.F /= 10;
+        }
+    } else {
+        expval = 0;
+    }
+
+    // the exponent format is "%+03d" and largest value is "307", so set aside 4-5 characters
+    unsigned int minwidth = ((expval < 100) && (expval > -100)) ? 4U : 5U;
+
+    // in "%g" mode, "prec" is the number of *significant figures* not decimals
+    if (flags & FLAGS_ADAPT_EXP) {
+        // do we want to fall-back to "%f" mode?
+        if ((conv.U == 0) || ((value >= 1e-4) && (value < 1e6))) {
+            if ((int) prec > expval) {
+                prec = (unsigned) ((int) prec - expval - 1);
+            } else {
+                prec = 0;
+            }
+            flags |= FLAGS_PRECISION;   // make sure _ftoa respects precision
+            // no characters in exponent
+            minwidth = 0U;
+            expval = 0;
+        } else {
+            // we use one sigfig for the whole part
+            if ((prec > 0) && (flags & FLAGS_PRECISION)) {
+                --prec;
+            }
+        }
+    }
+
+    // will everything fit?
+    unsigned int fwidth = width;
+    if (width > minwidth) {
+        // we didn't fall-back so subtract the characters required for the exponent
+        fwidth -= minwidth;
+    } else {
+        // not enough characters, so go back to default sizing
+        fwidth = 0U;
+    }
+    if ((flags & FLAGS_LEFT) && minwidth) {
+        // if we're padding on the right, DON'T pad the floating part
+        fwidth = 0U;
+    }
+
+    // rescale the float value
+    if (expval) {
+        value /= conv.F;
+    }
+
+    // output the floating part
+    const size_t start_idx = idx;
+    idx = _ftoa(out, buffer, idx, maxlen, negative ? -value : value, prec, fwidth, flags & ~FLAGS_ADAPT_EXP);
+
+    // output the exponent part
+    if (minwidth) {
+        // output the exponential symbol
+        out((flags & FLAGS_UPPERCASE) ? 'E' : 'e', buffer, idx++, maxlen);
+        // output the exponent value
+        idx = _ntoa_long(out, buffer, idx, maxlen, (uint)((expval < 0) ? -expval : expval), expval < 0, 10, 0, minwidth - 1,
+                         FLAGS_ZEROPAD | FLAGS_PLUS);
+        // might need to right-pad spaces
+        if (flags & FLAGS_LEFT) {
+            while (idx - start_idx < width) out(' ', buffer, idx++, maxlen);
+        }
+    }
+    return idx;
+}
+
+#endif  // PICO_PRINTF_SUPPORT_EXPONENTIAL
+#endif  // PICO_PRINTF_SUPPORT_FLOAT
+
+// internal vsnprintf
+static int _vsnprintf(out_fct_type out, char *buffer, const size_t maxlen, const char *format, va_list va) {
+#if !PICO_PRINTF_ALWAYS_INCLUDED
+    lazy_vsnprintf = _vsnprintf;
+#endif
+    unsigned int flags, width, precision, n;
+    size_t idx = 0U;
+
+    if (!buffer) {
+        // use null output function
+        out = _out_null;
+    }
+
+    while (*format) {
+        // format specifier?  %[flags][width][.precision][length]
+        if (*format != '%') {
+            // no
+            out(*format, buffer, idx++, maxlen);
+            format++;
+            continue;
+        } else {
+            // yes, evaluate it
+            format++;
+        }
+
+        // evaluate flags
+        flags = 0U;
+        do {
+            switch (*format) {
+                case '0':
+                    flags |= FLAGS_ZEROPAD;
+                    format++;
+                    n = 1U;
+                    break;
+                case '-':
+                    flags |= FLAGS_LEFT;
+                    format++;
+                    n = 1U;
+                    break;
+                case '+':
+                    flags |= FLAGS_PLUS;
+                    format++;
+                    n = 1U;
+                    break;
+                case ' ':
+                    flags |= FLAGS_SPACE;
+                    format++;
+                    n = 1U;
+                    break;
+                case '#':
+                    flags |= FLAGS_HASH;
+                    format++;
+                    n = 1U;
+                    break;
+                default :
+                    n = 0U;
+                    break;
+            }
+        } while (n);
+
+        // evaluate width field
+        width = 0U;
+        if (_is_digit(*format)) {
+            width = _atoi(&format);
+        } else if (*format == '*') {
+            const int w = va_arg(va, int);
+            if (w < 0) {
+                flags |= FLAGS_LEFT;    // reverse padding
+                width = (unsigned int) -w;
+            } else {
+                width = (unsigned int) w;
+            }
+            format++;
+        }
+
+        // evaluate precision field
+        precision = 0U;
+        if (*format == '.') {
+            flags |= FLAGS_PRECISION;
+            format++;
+            if (_is_digit(*format)) {
+                precision = _atoi(&format);
+            } else if (*format == '*') {
+                const int prec = (int) va_arg(va, int);
+                precision = prec > 0 ? (unsigned int) prec : 0U;
+                format++;
+            }
+        }
+
+        // evaluate length field
+        switch (*format) {
+            case 'l' :
+                flags |= FLAGS_LONG;
+                format++;
+                if (*format == 'l') {
+                    flags |= FLAGS_LONG_LONG;
+                    format++;
+                }
+                break;
+            case 'h' :
+                flags |= FLAGS_SHORT;
+                format++;
+                if (*format == 'h') {
+                    flags |= FLAGS_CHAR;
+                    format++;
+                }
+                break;
+#if PICO_PRINTF_SUPPORT_PTRDIFF_T
+            case 't' :
+                flags |= (sizeof(ptrdiff_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
+                format++;
+                break;
+#endif
+            case 'j' :
+                flags |= (sizeof(intmax_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
+                format++;
+                break;
+            case 'z' :
+                flags |= (sizeof(size_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
+                format++;
+                break;
+            default :
+                break;
+        }
+
+        // evaluate specifier
+        switch (*format) {
+            case 'd' :
+            case 'i' :
+            case 'u' :
+            case 'x' :
+            case 'X' :
+            case 'o' :
+            case 'b' : {
+                // set the base
+                unsigned int base;
+                if (*format == 'x' || *format == 'X') {
+                    base = 16U;
+                } else if (*format == 'o') {
+                    base = 8U;
+                } else if (*format == 'b') {
+                    base = 2U;
+                } else {
+                    base = 10U;
+                    flags &= ~FLAGS_HASH;   // no hash for dec format
+                }
+                // uppercase
+                if (*format == 'X') {
+                    flags |= FLAGS_UPPERCASE;
+                }
+
+                // no plus or space flag for u, x, X, o, b
+                if ((*format != 'i') && (*format != 'd')) {
+                    flags &= ~(FLAGS_PLUS | FLAGS_SPACE);
+                }
+
+                // ignore '0' flag when precision is given
+                if (flags & FLAGS_PRECISION) {
+                    flags &= ~FLAGS_ZEROPAD;
+                }
+
+                // convert the integer
+                if ((*format == 'i') || (*format == 'd')) {
+                    // signed
+                    if (flags & FLAGS_LONG_LONG) {
+#if PICO_PRINTF_SUPPORT_LONG_LONG
+                        const long long value = va_arg(va, long long);
+                        idx = _ntoa_long_long(out, buffer, idx, maxlen,
+                                              (unsigned long long) (value > 0 ? value : 0 - value), value < 0, base,
+                                              precision, width, flags);
+#endif
+                    } else if (flags & FLAGS_LONG) {
+                        const long value = va_arg(va, long);
+                        idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long) (value > 0 ? value : 0 - value),
+                                         value < 0, base, precision, width, flags);
+                    } else {
+                        const int value = (flags & FLAGS_CHAR) ? (char) va_arg(va, int) : (flags & FLAGS_SHORT)
+                                                                                          ? (short int) va_arg(va, int)
+                                                                                          : va_arg(va, int);
+                        idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int) (value > 0 ? value : 0 - value),
+                                         value < 0, base, precision, width, flags);
+                    }
+                } else {
+                    // unsigned
+                    if (flags & FLAGS_LONG_LONG) {
+#if PICO_PRINTF_SUPPORT_LONG_LONG
+                        idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, base,
+                                              precision, width, flags);
+#endif
+                    } else if (flags & FLAGS_LONG) {
+                        idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision,
+                                         width, flags);
+                    } else {
+                        const unsigned int value = (flags & FLAGS_CHAR) ? (unsigned char) va_arg(va, unsigned int)
+                                                                        : (flags & FLAGS_SHORT)
+                                                                          ? (unsigned short int) va_arg(va,
+                                                                                                        unsigned int)
+                                                                          : va_arg(va, unsigned int);
+                        idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags);
+                    }
+                }
+                format++;
+                break;
+            }
+            case 'f' :
+            case 'F' :
+#if PICO_PRINTF_SUPPORT_FLOAT
+                if (*format == 'F') flags |= FLAGS_UPPERCASE;
+                idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags);
+#else
+                for(int i=0;i<2;i++) out('?', buffer, idx++, maxlen);
+                va_arg(va, double);
+#endif
+                format++;
+                break;
+            case 'e':
+            case 'E':
+            case 'g':
+            case 'G':
+#if PICO_PRINTF_SUPPORT_FLOAT && PICO_PRINTF_SUPPORT_EXPONENTIAL
+                if ((*format == 'g') || (*format == 'G')) flags |= FLAGS_ADAPT_EXP;
+                if ((*format == 'E') || (*format == 'G')) flags |= FLAGS_UPPERCASE;
+                idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags);
+#else
+                for(int i=0;i<2;i++) out('?', buffer, idx++, maxlen);
+                va_arg(va, double);
+#endif
+                format++;
+                break;
+            case 'c' : {
+                unsigned int l = 1U;
+                // pre padding
+                if (!(flags & FLAGS_LEFT)) {
+                    while (l++ < width) {
+                        out(' ', buffer, idx++, maxlen);
+                    }
+                }
+                // char output
+                out((char) va_arg(va, int), buffer, idx++, maxlen);
+                // post padding
+                if (flags & FLAGS_LEFT) {
+                    while (l++ < width) {
+                        out(' ', buffer, idx++, maxlen);
+                    }
+                }
+                format++;
+                break;
+            }
+
+            case 's' : {
+                const char *p = va_arg(va, char*);
+                unsigned int l = _strnlen_s(p, precision ? precision : (size_t) -1);
+                // pre padding
+                if (flags & FLAGS_PRECISION) {
+                    l = (l < precision ? l : precision);
+                }
+                if (!(flags & FLAGS_LEFT)) {
+                    while (l++ < width) {
+                        out(' ', buffer, idx++, maxlen);
+                    }
+                }
+                // string output
+                while ((*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) {
+                    out(*(p++), buffer, idx++, maxlen);
+                }
+                // post padding
+                if (flags & FLAGS_LEFT) {
+                    while (l++ < width) {
+                        out(' ', buffer, idx++, maxlen);
+                    }
+                }
+                format++;
+                break;
+            }
+
+            case 'p' : {
+                width = sizeof(void *) * 2U;
+                flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE;
+#if PICO_PRINTF_SUPPORT_LONG_LONG
+                const bool is_ll = sizeof(uintptr_t) == sizeof(long long);
+                if (is_ll) {
+                    idx = _ntoa_long_long(out, buffer, idx, maxlen, (uintptr_t) va_arg(va, void*), false, 16U,
+                                          precision, width, flags);
+                } else {
+#endif
+                    idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long) ((uintptr_t) va_arg(va, void*)), false,
+                                     16U, precision, width, flags);
+#if PICO_PRINTF_SUPPORT_LONG_LONG
+                }
+#endif
+                format++;
+                break;
+            }
+
+            case '%' :
+                out('%', buffer, idx++, maxlen);
+                format++;
+                break;
+
+            default :
+                out(*format, buffer, idx++, maxlen);
+                format++;
+                break;
+        }
+    }
+
+    // termination
+    out((char) 0, buffer, idx < maxlen ? idx : maxlen - 1U, maxlen);
+
+    // return written chars without terminating \0
+    return (int) idx;
+}
+
+
+///////////////////////////////////////////////////////////////////////////////
+
+int WRAPPER_FUNC(sprintf)(char *buffer, const char *format, ...) {
+    va_list va;
+    va_start(va, format);
+    const int ret = _vsnprintf(_out_buffer, buffer, (size_t) -1, format, va);
+    va_end(va);
+    return ret;
+}
+
+int WRAPPER_FUNC(snprintf)(char *buffer, size_t count, const char *format, ...) {
+    va_list va;
+    va_start(va, format);
+    const int ret = _vsnprintf(_out_buffer, buffer, count, format, va);
+    va_end(va);
+    return ret;
+}
+
+int WRAPPER_FUNC(vsnprintf)(char *buffer, size_t count, const char *format, va_list va) {
+    return _vsnprintf(_out_buffer, buffer, count, format, va);
+}
+
+int vfctprintf(void (*out)(char character, void *arg), void *arg, const char *format, va_list va) {
+    const out_fct_wrap_type out_fct_wrap = {out, arg};
+    return _vsnprintf(_out_fct, (char *) (uintptr_t) &out_fct_wrap, (size_t) -1, format, va);
+}
+
+#if LIB_PICO_PRINTF_PICO
+#if !PICO_PRINTF_ALWAYS_INCLUDED
+bool weak_raw_printf(const char *fmt, ...) {
+    va_list va;
+    va_start(va, fmt);
+    bool rc = weak_raw_vprintf(fmt, va);
+    va_end(va);
+    return rc;
+}
+
+bool weak_raw_vprintf(const char *fmt, va_list args) {
+    if (lazy_vsnprintf) {
+        char buffer[1];
+        lazy_vsnprintf(_out_char, buffer, (size_t) -1, fmt, args);
+        return true;
+    } else {
+        puts(fmt);
+        return false;
+    }
+}
+#endif
+#endif
diff --git a/src/rp2_common/pico_printf/printf_none.S b/src/rp2_common/pico_printf/printf_none.S
new file mode 100644
index 0000000..adc00ee
--- /dev/null
+++ b/src/rp2_common/pico_printf/printf_none.S
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/asm_helper.S"
+#include "pico/bootrom/sf_table.h"
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+wrapper_func sprintf
+wrapper_func snprintf
+wrapper_func vsnprintf
+regular_func printf_none_assert
+    push {lr}       // keep stack trace sane
+    ldr r0, =str
+    bl panic
+
+str:
+    .asciz "printf support is disabled"
\ No newline at end of file
diff --git a/src/rp2_common/pico_runtime/CMakeLists.txt b/src/rp2_common/pico_runtime/CMakeLists.txt
new file mode 100644
index 0000000..3b6cc18
--- /dev/null
+++ b/src/rp2_common/pico_runtime/CMakeLists.txt
@@ -0,0 +1,44 @@
+pico_add_impl_library(pico_runtime)
+
+target_sources(pico_runtime INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/runtime.c
+)
+
+target_include_directories(pico_runtime INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+target_link_libraries(pico_runtime INTERFACE
+        hardware_uart
+        hardware_clocks
+        hardware_irq
+        pico_printf
+        pico_sync
+        )
+
+if (TARGET pico_bit_ops)
+    target_link_libraries(pico_runtime INTERFACE pico_bit_ops)
+endif()
+if (TARGET pico_divider)
+    target_link_libraries(pico_runtime INTERFACE pico_divider)
+endif()
+if (TARGET pico_double)
+    target_link_libraries(pico_runtime INTERFACE pico_double)
+endif()
+if (TARGET pico_int64_ops)
+    target_link_libraries(pico_runtime INTERFACE pico_int64_ops)
+endif()
+if (TARGET pico_float)
+    target_link_libraries(pico_runtime INTERFACE pico_float)
+endif()
+if (TARGET pico_malloc)
+    target_link_libraries(pico_runtime INTERFACE pico_malloc)
+endif()
+if (TARGET pico_mem_ops)
+    target_link_libraries(pico_runtime INTERFACE pico_mem_ops)
+endif()
+if (TARGET pico_standard_link)
+    target_link_libraries(pico_runtime INTERFACE pico_standard_link)
+endif()
+
+# todo is this correct/needed?
+target_link_options(pico_runtime INTERFACE "--specs=nosys.specs")
+
diff --git a/src/rp2_common/pico_runtime/include/pico/runtime.h b/src/rp2_common/pico_runtime/include/pico/runtime.h
new file mode 100644
index 0000000..752ec6c
--- /dev/null
+++ b/src/rp2_common/pico_runtime/include/pico/runtime.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_RUNTIME_H
+#define _PICO_RUNTIME_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file runtime.h
+*  \defgroup pico_runtime pico_runtime
+* Aggregate runtime support including @ref pico_bit_ops, @ref pico_divider, @ref pico_double, @ref pico_int64_ops, @ref pico_float, @ref pico_malloc, @ref pico_mem_ops and @ref pico_standard_link
+*/
+
+
+void runtime_install_stack_guard(void *stack_bottom);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_runtime/runtime.c b/src/rp2_common/pico_runtime/runtime.c
new file mode 100644
index 0000000..575e23e
--- /dev/null
+++ b/src/rp2_common/pico_runtime/runtime.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include <stdarg.h>
+#include "pico.h"
+
+#include "hardware/regs/m0plus.h"
+#include "hardware/regs/resets.h"
+#include "hardware/structs/mpu.h"
+#include "hardware/structs/scb.h"
+#include "hardware/structs/padsbank0.h"
+
+#include "hardware/clocks.h"
+#include "hardware/irq.h"
+#include "hardware/resets.h"
+
+#include "pico/mutex.h"
+#include "pico/time.h"
+
+#if LIB_PICO_PRINTF_PICO
+#include "pico/printf.h"
+#else
+#define weak_raw_printf printf
+#define weak_raw_vprintf vprintf
+#endif
+
+#if PICO_ENTER_USB_BOOT_ON_EXIT
+#include "pico/bootrom.h"
+#endif
+
+extern char __StackLimit; /* Set by linker.  */
+
+uint32_t __attribute__((section(".ram_vector_table"))) ram_vector_table[48];
+
+// this is called for each thread since they have their own MPU
+void runtime_install_stack_guard(void *stack_bottom) {
+    // this is called b4 runtime_init is complete, so beware printf or assert
+
+    // make sure no one is using the MPU yet
+    if (mpu_hw->ctrl) {
+        // Note that it would be tempting to change this to a panic, but it happens so early, printing is not a good idea
+        __breakpoint();
+    }
+
+    uintptr_t addr = (uintptr_t) stack_bottom;
+    // the minimum we can protect is 32 bytes on a 32 byte boundary, so round up which will
+    // just shorten the valid stack range a tad
+    addr = (addr + 31u) & ~31u;
+
+    // mask is 1 bit per 32 bytes of the 256 byte range... clear the bit for the segment we want
+    uint32_t subregion_select = 0xffu ^ (1u << ((addr >> 5u) & 7u));
+    mpu_hw->ctrl = 5; // enable mpu with background default map
+    mpu_hw->rbar = (addr & (uint)~0xff) | 0x8 | 0;
+    mpu_hw->rasr = 1 // enable region
+                   | (0x7 << 1) // size 2^(7 + 1) = 256
+                   | (subregion_select << 8)
+                   | 0x10000000; // XN = disable instruction fetch; no other bits means no permissions
+}
+
+void runtime_init(void) {
+    // Reset all peripherals to put system into a known state,
+    // - except for QSPI pads and the XIP IO bank, as this is fatal if running from flash
+    // - and the PLLs, as this is fatal if clock muxing has not been reset on this boot
+    // - and USB, syscfg, as this disturbs USB-to-SWD on core 1
+    reset_block(~(
+            RESETS_RESET_IO_QSPI_BITS |
+            RESETS_RESET_PADS_QSPI_BITS |
+            RESETS_RESET_PLL_USB_BITS |
+            RESETS_RESET_USBCTRL_BITS |
+            RESETS_RESET_SYSCFG_BITS |
+            RESETS_RESET_PLL_SYS_BITS
+    ));
+
+    // Remove reset from peripherals which are clocked only by clk_sys and
+    // clk_ref. Other peripherals stay in reset until we've configured clocks.
+    unreset_block_wait(RESETS_RESET_BITS & ~(
+            RESETS_RESET_ADC_BITS |
+            RESETS_RESET_RTC_BITS |
+            RESETS_RESET_SPI0_BITS |
+            RESETS_RESET_SPI1_BITS |
+            RESETS_RESET_UART0_BITS |
+            RESETS_RESET_UART1_BITS |
+            RESETS_RESET_USBCTRL_BITS
+    ));
+
+    // pre-init runs really early since we need it even for memcpy and divide!
+    // (basically anything in aeabi that uses bootrom)
+
+    // Start and end points of the constructor list,
+    // defined by the linker script.
+    extern void (*__preinit_array_start)(void);
+    extern void (*__preinit_array_end)(void);
+
+    // Call each function in the list.
+    // We have to take the address of the symbols, as __preinit_array_start *is*
+    // the first function pointer, not the address of it.
+    for (void (**p)(void) = &__preinit_array_start; p < &__preinit_array_end; ++p) {
+        (*p)();
+    }
+
+    // After calling preinit we have enough runtime to do the exciting maths
+    // in clocks_init
+    clocks_init();
+
+    // Peripheral clocks should now all be running
+    unreset_block_wait(RESETS_RESET_BITS);
+
+#if !PICO_IE_26_29_UNCHANGED_ON_RESET
+    // after resetting BANK0 we should disable IE on 26-29
+    hw_clear_alias(padsbank0_hw)->io[26] = hw_clear_alias(padsbank0_hw)->io[27] =
+            hw_clear_alias(padsbank0_hw)->io[28] = hw_clear_alias(padsbank0_hw)->io[29] = PADS_BANK0_GPIO0_IE_BITS;
+#endif
+
+    // this is an array of either mutex_t or recursive_mutex_t (i.e. not necessarily the same size)
+    // however each starts with a lock_core_t, and the spin_lock is initialized to address 1 for a recursive
+    // spinlock and 0 for a regular one.
+
+    static_assert(!(sizeof(mutex_t)&3), "");
+    static_assert(!(sizeof(recursive_mutex_t)&3), "");
+    static_assert(!offsetof(mutex_t, core), "");
+    static_assert(!offsetof(recursive_mutex_t, core), "");
+    extern lock_core_t __mutex_array_start;
+    extern lock_core_t __mutex_array_end;
+
+    for (lock_core_t *l = &__mutex_array_start; l < &__mutex_array_end; ) {
+        if (l->spin_lock) {
+            assert(1 == (uintptr_t)l->spin_lock); // indicator for a recursive mutex
+            recursive_mutex_t *rm = (recursive_mutex_t *)l;
+            recursive_mutex_init(rm);
+            l = &rm[1].core; // next
+        } else {
+            mutex_t *m = (mutex_t *)l;
+            mutex_init(m);
+            l = &m[1].core; // next
+        }
+    }
+
+#if !(PICO_NO_RAM_VECTOR_TABLE || PICO_NO_FLASH)
+    __builtin_memcpy(ram_vector_table, (uint32_t *) scb_hw->vtor, sizeof(ram_vector_table));
+    scb_hw->vtor = (uintptr_t) ram_vector_table;
+#endif
+
+#ifndef NDEBUG
+    if (__get_current_exception()) {
+        // crap; started in exception handler
+        __asm ("bkpt #0");
+    }
+#endif
+
+#if PICO_USE_STACK_GUARDS
+    // install core0 stack guard
+    extern char __StackBottom;
+    runtime_install_stack_guard(&__StackBottom);
+#endif
+
+    spin_locks_reset();
+    irq_init_priorities();
+    alarm_pool_init_default();
+
+    // Start and end points of the constructor list,
+    // defined by the linker script.
+    extern void (*__init_array_start)(void);
+    extern void (*__init_array_end)(void);
+
+    // Call each function in the list.
+    // We have to take the address of the symbols, as __init_array_start *is*
+    // the first function pointer, not the address of it.
+    for (void (**p)(void) = &__init_array_start; p < &__init_array_end; ++p) {
+        (*p)();
+    }
+
+}
+
+void _exit(__unused int status) {
+#if PICO_ENTER_USB_BOOT_ON_EXIT
+    reset_usb_boot(0,0);
+#else
+    while (1) {
+        __breakpoint();
+    }
+#endif
+}
+
+void *_sbrk(int incr) {
+    extern char end; /* Set by linker.  */
+    static char *heap_end;
+    char *prev_heap_end;
+
+    if (heap_end == 0)
+        heap_end = &end;
+
+    prev_heap_end = heap_end;
+    char *next_heap_end = heap_end + incr;
+
+    if (__builtin_expect(next_heap_end > (&__StackLimit), false)) {
+#if PICO_USE_OPTIMISTIC_SBRK
+        if (heap_end == &__StackLimit) {
+//        errno = ENOMEM;
+            return (char *) -1;
+        }
+        next_heap_end = &__StackLimit;
+#else
+        return (char *) -1;
+#endif
+    }
+
+    heap_end = next_heap_end;
+    return (void *) prev_heap_end;
+}
+
+// exit is not useful... no desire to pull in __call_exitprocs
+void exit(int status) {
+    _exit(status);
+}
+
+// incorrect warning from GCC 6
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsuggest-attribute=format"
+void __assert_func(const char *file, int line, const char *func, const char *failedexpr) {
+    weak_raw_printf("assertion \"%s\" failed: file \"%s\", line %d%s%s\n",
+           failedexpr, file, line, func ? ", function: " : "",
+           func ? func : "");
+
+    _exit(1);
+}
+
+#pragma GCC diagnostic pop
+
+void __attribute__((noreturn)) panic_unsupported() {
+    panic("not supported");
+}
+
+// PICO_CONFIG: PICO_PANIC_FUNCTION, Name of a function to use in place of the stock panic function or empty string to simply breakpoint on panic, group=pico_runtime
+// note the default is not "panic" it is undefined
+#ifdef PICO_PANIC_FUNCTION
+#define PICO_PANIC_FUNCTION_EMPTY (__CONCAT(PICO_PANIC_FUNCTION, 1) == 1)
+#if !PICO_PANIC_FUNCTION_EMPTY
+extern void __attribute__((noreturn)) __printflike(1, 0) PICO_PANIC_FUNCTION(__unused const char *fmt, ...);
+#endif
+// Use a forwarding method here as it is a little simpler than renaming the symbol as it is used from assembler
+void __attribute__((naked, noreturn)) __printflike(1, 0) panic(__unused const char *fmt, ...) {
+    // if you get an undefined reference here, you didn't define your PICO_PANIC_FUNCTION!
+    __asm (
+            "push {lr}\n"
+#if !PICO_PANIC_FUNCTION_EMPTY
+            "bl " __XSTRING(PICO_PANIC_FUNCTION) "\n"
+#endif
+            "bkpt #0\n"
+            "1: b 1b\n" // loop for ever as we are no return
+        :
+        :
+        :
+    );
+}
+#else
+// todo consider making this try harder to output if we panic early
+//  right now, print mutex may be uninitialised (in which case it deadlocks - although after printing "PANIC")
+//  more importantly there may be no stdout/UART initialized yet
+// todo we may want to think about where we print panic messages to; writing to USB appears to work
+//  though it doesn't seem like we can expect it to... fine for now
+void __attribute__((noreturn)) __printflike(1, 0) panic(const char *fmt, ...) {
+    puts("\n*** PANIC ***\n");
+    if (fmt) {
+#if LIB_PICO_PRINTF_NONE
+        puts(fmt);
+#else
+        va_list args;
+        va_start(args, fmt);
+#if PICO_PRINTF_ALWAYS_INCLUDED
+        vprintf(fmt, args);
+#else
+        weak_raw_vprintf(fmt, args);
+#endif
+        va_end(args);
+        puts("\n");
+#endif
+    }
+
+    _exit(1);
+}
+#endif
+
+void hard_assertion_failure(void) {
+    panic("Hard assert");
+}
diff --git a/src/rp2_common/pico_standard_link/CMakeLists.txt b/src/rp2_common/pico_standard_link/CMakeLists.txt
new file mode 100644
index 0000000..a730540
--- /dev/null
+++ b/src/rp2_common/pico_standard_link/CMakeLists.txt
@@ -0,0 +1,97 @@
+if (NOT TARGET pico_standard_link)
+    pico_add_impl_library(pico_standard_link)
+
+    target_sources(pico_standard_link INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/crt0.S
+        ${CMAKE_CURRENT_LIST_DIR}/new_delete.cpp
+        ${CMAKE_CURRENT_LIST_DIR}/binary_info.c
+    )
+
+    pico_add_map_output(pico_standard_link)
+
+    # todo revisit when we do Clang
+    if (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+        target_link_options(pico_standard_link INTERFACE "LINKER:-nostdlib")
+    endif ()
+
+    target_link_libraries(pico_standard_link INTERFACE hardware_regs boot_stage2_headers pico_bootrom pico_binary_info pico_cxx_options)
+
+    function(pico_add_link_depend TARGET dependency)
+        get_target_property(target_type ${TARGET} TYPE)
+        if (${target_type} STREQUAL "INTERFACE_LIBRARY")
+            set(PROP "INTERFACE_LINK_DEPENDS")
+        else()
+            set(PROP "LINK_DEPENDS")
+        endif()
+        get_target_property(_LINK_DEPENDS ${TARGET} ${PROP})
+        if (NOT _LINK_DEPENDS)
+            set(_LINK_DEPENDS ${dependency})
+        else()
+            list(APPEND _LINK_DEPENDS ${dependency})
+        endif()
+        set_target_properties(${TARGET} PROPERTIES ${PROP} "${_LINK_DEPENDS}")
+    endfunction()
+
+    # need this because cmake does not appear to have a way to override an INTERFACE variable
+    function(pico_set_linker_script TARGET LDSCRIPT)
+        set_target_properties(${TARGET} PROPERTIES PICO_TARGET_LINKER_SCRIPT ${LDSCRIPT})
+        pico_add_link_depend(${TARGET} ${LDSCRIPT})
+    endfunction()
+
+    function(pico_set_binary_type TARGET TYPE)
+        set_target_properties(${TARGET} PROPERTIES PICO_TARGET_BINARY_TYPE ${TYPE})
+    endfunction()
+
+    if (PICO_NO_FLASH)
+        set(PICO_DEFAULT_BINARY_TYPE no_flash)
+    elseif (PICO_USE_BLOCKED_RAM)
+        set(PICO_DEFAULT_BINARY_TYPE blocked_ram)
+    elseif (PICO_COPY_TO_RAM)
+        set(PICO_DEFAULT_BINARY_TYPE copy_to_ram)
+    else()
+        set(PICO_DEFAULT_BINARY_TYPE default)
+    endif()
+
+    # LINKER script will be PICO_TARGET_LINKER_SCRIPT if set on target, or ${CMAKE_CURRENT_LIST_DIR}/memmap_foo.ld
+    # if PICO_TARGET_BINARY_TYPE is set to foo on the target, otherwise ${CMAKE_CURRENT_LIST_DIR}/memmap_${PICO_DEFAULT_BINARY_TYPE).ld
+    target_link_options(pico_standard_link INTERFACE
+            "LINKER:--script=$<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_LINKER_SCRIPT>>,$<TARGET_PROPERTY:PICO_TARGET_LINKER_SCRIPT>,${CMAKE_CURRENT_LIST_DIR}/memmap_$<IF:$<STREQUAL:$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>,>,${PICO_DEFAULT_BINARY_TYPE},$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>>.ld>"
+    )
+
+    # PICO_NO_FLASH will be set based on PICO_TARGET_BUILD_TYPE target property being equal to no_flash if set, otherwise to the value of the PICO_NO_FLASH cmake variable unless PICO_TARGET_TYPE is set to something else
+    # PICO_BUILD_DEFINE: PICO_NO_FLASH, whether this is a 'no_flash' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link
+    target_compile_definitions(pico_standard_link INTERFACE PICO_NO_FLASH=$<IF:$<STREQUAL:$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>,no_flash>,1,$<AND:$<BOOL:${PICO_NO_FLASH}>,$<STREQUAL:,$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>>>>)
+    # PICO_USE_BLOCKED_RAM will be set based on PICO_TARGET_BUILD_TYPE target property being equal to use_blocked_ram if set, otherwise to the value of the PICO_USE_BLOCKED_RAM cmake variable unless PICO_TARGET_TYPE is set to something else
+    # PICO_BUILD_DEFINE: PICO_USE_BLOCKS_RAM, whether this is a 'blocked_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link
+    target_compile_definitions(pico_standard_link INTERFACE PICO_USE_BLOCKED_RAM=$<IF:$<STREQUAL:$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>,use_blocked_ram>,1,$<AND:$<BOOL:${PICO_USE_BLOCKED_RAM}>,$<STREQUAL:,$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>>>>)
+    # PICO_COPY_TO_RAM will be set based on PICO_TARGET_BUILD_TYPE target property being equal to copy_to_ram if set, otherwise to the value of the PICO_COPY_TO_RAM cmake variable unless PICO_TARGET_TYPE is set to something else
+    # PICO_BUILD_DEFINE: PICO_COPY_TO_RAM, whether this is a 'copy_to_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link
+    target_compile_definitions(pico_standard_link INTERFACE PICO_COPY_TO_RAM=$<IF:$<STREQUAL:$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>,copy_to_ram>,1,$<AND:$<BOOL:${PICO_COPY_TO_RAM}>,$<STREQUAL:,$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>>>>)
+
+    target_compile_definitions(pico_standard_link INTERFACE PICO_CMAKE_BUILD_TYPE="${CMAKE_BUILD_TYPE}")
+    if (PICO_DEOPTIMIZED_DEBUG AND "${CMAKE_BUILD_TYPE}" STREQUAL "Debug")
+        target_compile_definitions(pico_standard_link INTERFACE PICO_DEOPTIMIZED_DEBUG=1)
+    endif()
+
+    # todo revisit/recall reasoning for why not -nostartfiles always?
+    # -nostartfiles will be added if PICO_NO_FLASH would be defined to 1
+    target_link_options(pico_standard_link INTERFACE $<$<IF:$<STREQUAL:$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>,no_flash>,1,$<AND:$<BOOL:${PICO_NO_FLASH}>,$<STREQUAL:,$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>>>>:-nostartfiles>)
+    # boot_stage2 will be linked if PICO_NO_FLASH would be defined to 0
+    target_link_libraries(pico_standard_link INTERFACE $<$<NOT:$<IF:$<STREQUAL:$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>,no_flash>,1,$<AND:$<BOOL:${PICO_NO_FLASH}>,$<STREQUAL:,$<TARGET_PROPERTY:PICO_TARGET_BINARY_TYPE>>>>>:$<IF:$<BOOL:$<TARGET_PROPERTY:PICO_TARGET_BOOT_STAGE2>>,$<TARGET_PROPERTY:PICO_TARGET_BOOT_STAGE2>,bs2_default>_library>)
+
+    # PICO_CMAKE_CONFIG: PICO_USE_DEFAULT_MAX_PAGE_SIZE, Don't shrink linker max page to 4096, type=bool, default=0, advanced=true, group=pico_standard_link
+    if (NOT PICO_USE_DEFAULT_MAX_PAGE_SIZE)
+        target_link_options(pico_standard_link INTERFACE "LINKER:-z,max-page-size=4096")
+    endif()
+    # done in compiler now
+    #target_link_options(pico_standard_link INTERFACE "LINKER:--build-id=none")
+
+    # this line occasionally useful for debugging ... todo maybe make a PICO_ var
+    # target_compile_options(pico_standard_link INTERFACE --save-temps) #debugging only
+
+    # PICO_CMAKE_CONFIG: PICO_NO_GC_SECTIONS, Disable -ffunction-sections -fdata-sections, and --gc-sections, type=bool, default=0, advanced=true, group=pico_standard_link
+    if (NOT PICO_NO_GC_SECTIONS)
+        target_compile_options(pico_standard_link INTERFACE -ffunction-sections -fdata-sections)
+        target_link_options(pico_standard_link INTERFACE "LINKER:--gc-sections")
+    endif()
+endif()
diff --git a/src/rp2_common/pico_standard_link/binary_info.c b/src/rp2_common/pico_standard_link/binary_info.c
new file mode 100644
index 0000000..aa67ac4
--- /dev/null
+++ b/src/rp2_common/pico_standard_link/binary_info.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if !PICO_NO_BINARY_INFO && !PICO_NO_PROGRAM_INFO
+#include "pico/binary_info.h"
+
+#if !PICO_NO_FLASH
+#include "boot_stage2/config.h"
+#endif
+
+// Note we put at most 4 pieces of binary info in the reset section because that's how much spare space we had
+// (picked the most common ones)... if there is a link failure because of .reset section overflow then move
+// more out.
+#define reset_section_attr __attribute__((section(".reset")))
+
+#if !PICO_NO_FLASH
+#ifndef PICO_NO_BI_BINARY_SIZE
+extern char __flash_binary_end;
+bi_decl_with_attr(bi_binary_end((intptr_t)&__flash_binary_end), reset_section_attr)
+#endif
+#endif
+
+#if !PICO_NO_BI_PROGRAM_BUILD_DATE
+#ifndef PICO_PROGRAM_BUILD_DATE
+#define PICO_PROGRAM_BUILD_DATE __DATE__
+#endif
+bi_decl_with_attr(bi_program_build_date_string(PICO_PROGRAM_BUILD_DATE), reset_section_attr);
+#endif
+
+#if !PICO_NO_BI_PROGRAM_NAME
+#if !defined(PICO_PROGRAM_NAME) && defined(PICO_TARGET_NAME)
+#define PICO_PROGRAM_NAME PICO_TARGET_NAME
+#endif
+#ifdef PICO_PROGRAM_NAME
+bi_decl_with_attr(bi_program_name(PICO_PROGRAM_NAME), reset_section_attr)
+#endif
+#endif
+
+#if !PICO_NO_BI_PICO_BOARD
+#ifdef PICO_BOARD
+bi_decl(bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PICO_BOARD, PICO_BOARD))
+#endif
+#endif
+
+#if !PICO_NO_BI_SDK_VERSION
+#ifdef PICO_SDK_VERSION_STRING
+bi_decl_with_attr(bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_SDK_VERSION, PICO_SDK_VERSION_STRING),reset_section_attr)
+#endif
+#endif
+
+#if !PICO_NO_BI_PROGRAM_VERSION_STRING
+#ifdef PICO_PROGRAM_VERSION_STRING
+bi_decl(bi_program_version_string(PICO_PROGRAM_VERSION_STRING))
+#endif
+#endif
+
+
+#if !PICO_NO_BI_PROGRAM_DESCRIPTION
+#ifdef PICO_PROGRAM_DESCRIPTION
+bi_decl(bi_program_description(PICO_PROGRAM_DESCRIPTION))
+#endif
+#endif
+
+#if !PICO_NO_BI_PROGRAM_URL
+#ifdef PICO_PROGRAM_URL
+bi_decl(bi_program_url(PICO_PROGRAM_URL))
+#endif
+#endif
+
+#if !PICO_NO_BI_BOOT_STAGE2_NAME
+#ifdef PICO_BOOT_STAGE2_NAME
+bi_decl(bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_BOOT2_NAME, PICO_BOOT_STAGE2_NAME))
+#endif
+#endif
+
+#if !PICO_NO_BI_BUILD_TYPE
+#ifdef PICO_CMAKE_BUILD_TYPE
+bi_decl(bi_program_build_attribute(PICO_CMAKE_BUILD_TYPE))
+#else
+#ifndef NDEBUG
+bi_decl(bi_program_build_attribute("Debug"))
+#else
+bi_decl(bi_program_build_attribute("Release"))
+#endif
+#endif
+
+#if PICO_DEOPTIMIZED_DEBUG
+bi_decl(bi_program_build_attribute("All optimization disabled"))
+#endif
+#endif
+
+#endif
diff --git a/src/rp2_common/pico_standard_link/crt0.S b/src/rp2_common/pico_standard_link/crt0.S
new file mode 100644
index 0000000..f57ddfd
--- /dev/null
+++ b/src/rp2_common/pico_standard_link/crt0.S
@@ -0,0 +1,338 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+#include "hardware/regs/m0plus.h"
+#include "hardware/regs/addressmap.h"
+#include "hardware/regs/sio.h"
+#include "pico/binary_info/defs.h"
+
+#ifdef NDEBUG
+#ifndef COLLAPSE_IRQS
+#define COLLAPSE_IRQS
+#endif
+#endif
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.section .vectors, "ax"
+.align 2
+
+.global __vectors, __VECTOR_TABLE
+__VECTOR_TABLE:
+__vectors:
+.word __StackTop
+.word _reset_handler
+.word isr_nmi
+.word isr_hardfault
+.word isr_invalid // Reserved, should never fire
+.word isr_invalid // Reserved, should never fire
+.word isr_invalid // Reserved, should never fire
+.word isr_invalid // Reserved, should never fire
+.word isr_invalid // Reserved, should never fire
+.word isr_invalid // Reserved, should never fire
+.word isr_invalid // Reserved, should never fire
+.word isr_svcall
+.word isr_invalid // Reserved, should never fire
+.word isr_invalid // Reserved, should never fire
+.word isr_pendsv
+.word isr_systick
+.word isr_irq0
+.word isr_irq1
+.word isr_irq2
+.word isr_irq3
+.word isr_irq4
+.word isr_irq5
+.word isr_irq6
+.word isr_irq7
+.word isr_irq8
+.word isr_irq9
+.word isr_irq10
+.word isr_irq11
+.word isr_irq12
+.word isr_irq13
+.word isr_irq14
+.word isr_irq15
+.word isr_irq16
+.word isr_irq17
+.word isr_irq18
+.word isr_irq19
+.word isr_irq20
+.word isr_irq21
+.word isr_irq22
+.word isr_irq23
+.word isr_irq24
+.word isr_irq25
+.word isr_irq26
+.word isr_irq27
+.word isr_irq28
+.word isr_irq29
+.word isr_irq30
+.word isr_irq31
+
+// all default exception handlers do nothing, and we can check for them being set to our
+// default values by seeing if they point to somewhere between __defaults_isrs_start and __default_isrs_end
+.global __default_isrs_start
+__default_isrs_start:
+
+// Declare a weak symbol for each ISR.
+// By default, they will fall through to the undefined IRQ handler below (breakpoint),
+// but can be overridden by C functions with correct name.
+
+.macro decl_isr_bkpt name
+.weak \name
+.type \name,%function
+.thumb_func
+\name:
+    bkpt #0
+.endm
+
+// these are separated out for clarity
+decl_isr_bkpt isr_invalid
+decl_isr_bkpt isr_nmi
+decl_isr_bkpt isr_hardfault
+decl_isr_bkpt isr_svcall
+decl_isr_bkpt isr_pendsv
+decl_isr_bkpt isr_systick
+
+.global __default_isrs_end
+__default_isrs_end:
+
+.macro decl_isr name
+.weak \name
+.type \name,%function
+.thumb_func
+\name:
+.endm
+
+decl_isr isr_irq0
+decl_isr isr_irq1
+decl_isr isr_irq2
+decl_isr isr_irq3
+decl_isr isr_irq4
+decl_isr isr_irq5
+decl_isr isr_irq6
+decl_isr isr_irq7
+decl_isr isr_irq8
+decl_isr isr_irq9
+decl_isr isr_irq10
+decl_isr isr_irq11
+decl_isr isr_irq12
+decl_isr isr_irq13
+decl_isr isr_irq14
+decl_isr isr_irq15
+decl_isr isr_irq16
+decl_isr isr_irq17
+decl_isr isr_irq18
+decl_isr isr_irq19
+decl_isr isr_irq20
+decl_isr isr_irq21
+decl_isr isr_irq22
+decl_isr isr_irq23
+decl_isr isr_irq24
+decl_isr isr_irq25
+decl_isr isr_irq26
+decl_isr isr_irq27
+decl_isr isr_irq28
+decl_isr isr_irq29
+decl_isr isr_irq30
+decl_isr isr_irq31
+
+// All unhandled USER IRQs fall through to here
+.global __unhandled_user_irq
+.thumb_func
+__unhandled_user_irq:
+    bl __get_current_exception
+    subs r0, #16
+.global unhandled_user_irq_num_in_r0
+unhandled_user_irq_num_in_r0:
+    bkpt #0
+
+// ----------------------------------------------------------------------------
+
+.section .binary_info_header, "a"
+
+// Header must be in first 256 bytes of main image (i.e. excluding flash boot2).
+// For flash builds we put it immediately after vector table; for NO_FLASH the
+// vectors are at a +0x100 offset because the bootrom enters RAM images directly
+// at their lowest address, so we put the header in the VTOR alignment hole.
+
+#if !PICO_NO_BINARY_INFO
+binary_info_header:
+.word BINARY_INFO_MARKER_START
+.word __binary_info_start
+.word __binary_info_end
+.word data_cpy_table // we may need to decode pointers that are in RAM at runtime.
+.word BINARY_INFO_MARKER_END
+#endif
+
+// ----------------------------------------------------------------------------
+
+.section .reset, "ax"
+
+// On flash builds, the vector table comes first in the image (conventional).
+// On NO_FLASH builds, the reset handler section comes first, as the entry
+// point is at offset 0 (fixed due to bootrom), and VTOR is highly-aligned.
+// Image is entered in various ways:
+//
+// - NO_FLASH builds are entered from beginning by UF2 bootloader
+//
+// - Flash builds vector through the table into _reset_handler from boot2
+//
+// - Either type can be entered via _entry_point by the debugger, and flash builds
+//   must then be sent back round the boot sequence to properly initialise flash
+
+// ELF entry point:
+.type _entry_point,%function
+.thumb_func
+.global _entry_point
+_entry_point:
+
+#if PICO_NO_FLASH
+    // Vector through our own table (SP, VTOR will not have been set up at
+    // this point). Same path for debugger entry and bootloader entry.
+    ldr r0, =__vectors
+#else
+    // Debugger tried to run code after loading, so SSI is in 03h-only mode.
+    // Go back through bootrom + boot2 to properly initialise flash.
+    movs r0, #0
+#endif
+    ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET)
+    str r0, [r1]
+    ldmia r0!, {r1, r2}
+    msr msp, r1
+    bx r2
+
+// Reset handler:
+// - initialises .data
+// - clears .bss
+// - calls runtime_init
+// - calls main
+// - calls exit (which should eventually hang the processor via _exit)
+
+.type _reset_handler,%function
+.thumb_func
+_reset_handler:
+    // Only core 0 should run the C runtime startup code; core 1 is normally
+    // sleeping in the bootrom at this point but check to be sure
+    ldr r0, =(SIO_BASE + SIO_CPUID_OFFSET)
+    ldr r0, [r0]
+    cmp r0, #0
+    bne hold_non_core0_in_bootrom
+
+    adr r4, data_cpy_table
+
+    // assume there is at least one entry
+1:
+    ldmia r4!, {r1-r3}
+    cmp r1, #0
+    beq 2f
+    bl data_cpy
+    b 1b
+2:
+
+    // Zero out the BSS
+    ldr r1, =__bss_start__
+    ldr r2, =__bss_end__
+    movs r0, #0
+    b bss_fill_test
+bss_fill_loop:
+    stm r1!, {r0}
+bss_fill_test:
+    cmp r1, r2
+    bne bss_fill_loop
+
+platform_entry: // symbol for stack traces
+    // Use 32-bit jumps, in case these symbols are moved out of branch range
+    // (e.g. if main is in SRAM and crt0 in flash)
+    ldr r1, =runtime_init
+    blx r1
+    ldr r1, =main
+    blx r1
+    ldr r1, =exit
+    blx r1
+    // exit should not return.  If it does, hang the core.
+    // (fall thru into our hang _exit impl
+.weak _exit
+.type _exit,%function
+.thumb_func
+_exit:
+1: // separate label because _exit can be moved out of branch range
+    bkpt #0
+    b 1b
+
+data_cpy_loop:
+    ldm r1!, {r0}
+    stm r2!, {r0}
+data_cpy:
+    cmp r2, r3
+    blo data_cpy_loop
+    bx lr
+
+.align 2
+data_cpy_table:
+#if PICO_COPY_TO_RAM
+.word __ram_text_source__
+.word __ram_text_start__
+.word __ram_text_end__
+#endif
+.word __etext
+.word __data_start__
+.word __data_end__
+
+.word __scratch_x_source__
+.word __scratch_x_start__
+.word __scratch_x_end__
+
+.word __scratch_y_source__
+.word __scratch_y_start__
+.word __scratch_y_end__
+
+.word 0 // null terminator
+
+// ----------------------------------------------------------------------------
+// Provide safe defaults for _exit and runtime_init
+// Full implementations usually provided by platform.c
+
+.weak runtime_init
+.type runtime_init,%function
+.thumb_func
+runtime_init:
+    bx lr
+
+// ----------------------------------------------------------------------------
+// If core 1 somehow gets into crt0 due to a spectacular VTOR mishap, we need to
+// catch it and send back to the sleep-and-launch code in the bootrom. Shouldn't
+// happen (it should sleep in the ROM until given an entry point via the
+// cross-core FIFOs) but it's good to be defensive.
+
+hold_non_core0_in_bootrom:
+    ldr r0, = 'W' | ('V' << 8)
+    bl rom_func_lookup
+    bx r0
+
+.global __get_current_exception
+.thumb_func
+__get_current_exception:
+    mrs  r0, ipsr
+    uxtb r0, r0
+    bx   lr
+
+// ----------------------------------------------------------------------------
+// Stack/heap dummies to set size
+
+.section .stack
+// align to allow for memory protection (although this alignment is pretty much ignored by linker script)
+.align 5
+    .equ StackSize, PICO_STACK_SIZE
+.space StackSize
+
+.section .heap
+.align 2
+    .equ HeapSize, PICO_HEAP_SIZE
+.space HeapSize
diff --git a/src/rp2_common/pico_standard_link/doc.h b/src/rp2_common/pico_standard_link/doc.h
new file mode 100644
index 0000000..d8ce3d4
--- /dev/null
+++ b/src/rp2_common/pico_standard_link/doc.h
@@ -0,0 +1,10 @@
+/**
+ * \defgroup pico_standard_link pico_standard_link
+ * \brief Standard link step providing the basics for creating a runnable binary
+ * 
+ * This includes
+ *   - C runtime initialization
+ *   - Linker scripts for 'default', 'no_flash', 'blocked_ram' and 'copy_to_ram' binaries
+ *   - 'Binary Information' support
+ *   - Linker option control
+ */
diff --git a/src/rp2_common/pico_standard_link/memmap_blocked_ram.ld b/src/rp2_common/pico_standard_link/memmap_blocked_ram.ld
new file mode 100644
index 0000000..5b0afe6
--- /dev/null
+++ b/src/rp2_common/pico_standard_link/memmap_blocked_ram.ld
@@ -0,0 +1,252 @@
+/* Based on GCC ARM embedded samples.
+   Defines the following symbols for use by code:
+    __exidx_start
+    __exidx_end
+    __etext
+    __data_start__
+    __preinit_array_start
+    __preinit_array_end
+    __init_array_start
+    __init_array_end
+    __fini_array_start
+    __fini_array_end
+    __data_end__
+    __bss_start__
+    __bss_end__
+    __end__
+    end
+    __HeapLimit
+    __StackLimit
+    __StackTop
+    __stack (== StackTop)
+*/
+
+MEMORY
+{
+    FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k
+    RAM(rwx) : ORIGIN =  0x21000000, LENGTH = 256k
+    SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k
+    SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k
+}
+
+ENTRY(_entry_point)
+
+SECTIONS
+{
+    /* Second stage bootloader is prepended to the image. It must be 256 bytes big
+       and checksummed. It is usually built by the boot_stage2 target
+       in the Raspberry Pi Pico SDK
+    */
+
+    .flash_begin : {
+        __flash_binary_start = .;
+    } > FLASH
+
+    .boot2 : {
+        __boot2_start__ = .;
+        KEEP (*(.boot2))
+        __boot2_end__ = .;
+    } > FLASH
+
+    ASSERT(__boot2_end__ - __boot2_start__ == 256,
+        "ERROR: Pico second stage bootloader must be 256 bytes in size")
+
+    /* The second stage will always enter the image at the start of .text.
+       The debugger will use the ELF entry point, which is the _entry_point
+       symbol if present, otherwise defaults to start of .text.
+       This can be used to transfer control back to the bootrom on debugger
+       launches only, to perform proper flash setup.
+    */
+
+    .text : {
+        __logical_binary_start = .;
+        KEEP (*(.vectors))
+        KEEP (*(.binary_info_header))
+        __binary_info_header_end = .;
+        KEEP (*(.reset))
+        /* TODO revisit this now memset/memcpy/float in ROM */
+        /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from
+         * FLASH ... we will include any thing excluded here in .data below by default */
+        *(.init)
+        *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*)
+        *(.fini)
+        /* Pull all c'tors into .text */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+        /* Followed by destructors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.eh_frame*)
+        . = ALIGN(4);
+    } > FLASH
+
+    .rodata : {
+        *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*)
+        . = ALIGN(4);
+        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*)))
+        . = ALIGN(4);
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* Machine inspectable binary information */
+    . = ALIGN(4);
+    __binary_info_start = .;
+    .binary_info :
+    {
+        KEEP(*(.binary_info.keep.*))
+        *(.binary_info.*)
+    } > FLASH
+    __binary_info_end = .;
+    . = ALIGN(4);
+
+    /* End of .text-like segments */
+    __etext = .;
+
+   .ram_vector_table (COPY): {
+        *(.ram_vector_table)
+    } > RAM
+
+    .data : {
+        __data_start__ = .;
+        *(vtable)
+
+        *(.time_critical*)
+
+        /* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM */
+        *(.text*)
+        . = ALIGN(4);
+        *(.rodata*)
+        . = ALIGN(4);
+
+        *(.data*)
+
+        . = ALIGN(4);
+        *(.after_data.*)
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__mutex_array_start = .);
+        KEEP(*(SORT(.mutex_array.*)))
+        KEEP(*(.mutex_array))
+        PROVIDE_HIDDEN (__mutex_array_end = .);
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(SORT(.preinit_array.*)))
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        *(SORT(.fini_array.*))
+        *(.fini_array)
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        *(.jcr)
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+    } > RAM AT> FLASH
+
+    .uninitialized_data (COPY): {
+        . = ALIGN(4);
+        *(.uninitialized_data*)
+    } > RAM
+
+    /* Start and end symbols must be word-aligned */
+    .scratch_x : {
+        __scratch_x_start__ = .;
+        *(.scratch_x.*)
+        . = ALIGN(4);
+        __scratch_x_end__ = .;
+    } > SCRATCH_X AT > FLASH
+    __scratch_x_source__ = LOADADDR(.scratch_x);
+
+    .scratch_y : {
+        __scratch_y_start__ = .;
+        *(.scratch_y.*)
+        . = ALIGN(4);
+        __scratch_y_end__ = .;
+    } > SCRATCH_Y AT > FLASH
+    __scratch_y_source__ = LOADADDR(.scratch_y);
+
+    .bss  : {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*)))
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack*_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later
+     *
+     * stack1 section may be empty/missing if platform_launch_core1 is not used */
+
+    /* by default we put core 0 stack at the end of scratch Y, so that if core 1
+     * stack is not used then all of SCRATCH_X is free.
+     */
+    .stack1_dummy (COPY):
+    {
+        *(.stack1*)
+    } > SCRATCH_X
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SCRATCH_Y
+
+    .flash_end : {
+        __flash_binary_end = .;
+    } > FLASH
+
+    /* stack limit is poorly named, but historically is maximum heap ptr */
+    __StackLimit = ORIGIN(RAM) + LENGTH(RAM);
+    __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X);
+    __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y);
+    __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy);
+    __StackBottom = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed")
+
+    ASSERT( __binary_info_header_end - __logical_binary_start <= 256, "Binary info must be in first 256 bytes of the binary")
+    /* todo assert on extra code */
+}
+
diff --git a/src/rp2_common/pico_standard_link/memmap_copy_to_ram.ld b/src/rp2_common/pico_standard_link/memmap_copy_to_ram.ld
new file mode 100644
index 0000000..90975b5
--- /dev/null
+++ b/src/rp2_common/pico_standard_link/memmap_copy_to_ram.ld
@@ -0,0 +1,253 @@
+/* Based on GCC ARM embedded samples.
+   Defines the following symbols for use by code:
+    __exidx_start
+    __exidx_end
+    __etext
+    __data_start__
+    __preinit_array_start
+    __preinit_array_end
+    __init_array_start
+    __init_array_end
+    __fini_array_start
+    __fini_array_end
+    __data_end__
+    __bss_start__
+    __bss_end__
+    __end__
+    end
+    __HeapLimit
+    __StackLimit
+    __StackTop
+    __stack (== StackTop)
+*/
+
+MEMORY
+{
+    FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k
+    RAM(rwx) : ORIGIN =  0x20000000, LENGTH = 256k
+    SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k
+    SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k
+}
+
+ENTRY(_entry_point)
+
+SECTIONS
+{
+    /* Second stage bootloader is prepended to the image. It must be 256 bytes big
+       and checksummed. It is usually built by the boot_stage2 target
+       in the Raspberry Pi Pico SDK
+    */
+
+    .flash_begin : {
+        __flash_binary_start = .;
+    } > FLASH
+
+    .boot2 : {
+        __boot2_start__ = .;
+        KEEP (*(.boot2))
+        __boot2_end__ = .;
+    } > FLASH
+
+    ASSERT(__boot2_end__ - __boot2_start__ == 256,
+        "ERROR: Pico second stage bootloader must be 256 bytes in size")
+
+    /* The second stage will always enter the image at the start of .text.
+       The debugger will use the ELF entry point, which is the _entry_point
+       symbol if present, otherwise defaults to start of .text.
+       This can be used to transfer control back to the bootrom on debugger
+       launches only, to perform proper flash setup.
+    */
+
+    .flashtext : {
+        __logical_binary_start = .;
+        KEEP (*(.vectors))
+        KEEP (*(.binary_info_header))
+        __binary_info_header_end = .;
+        KEEP (*(.reset))
+    }
+
+    .rodata : {
+        /* segments not marked as .flashdata are instead pulled into .data (in RAM) to avoid accidental flash accesses */
+        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*)))
+        . = ALIGN(4);
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* Machine inspectable binary information */
+    . = ALIGN(4);
+    __binary_info_start = .;
+    .binary_info :
+    {
+        KEEP(*(.binary_info.keep.*))
+        *(.binary_info.*)
+    } > FLASH
+    __binary_info_end = .;
+    . = ALIGN(4);
+
+    /* Vector table goes first in RAM, to avoid large alignment hole */
+   .ram_vector_table (COPY): {
+        *(.ram_vector_table)
+    } > RAM
+
+    .text : {
+        __ram_text_start__ = .;
+        *(.init)
+        *(.text*)
+        *(.fini)
+        /* Pull all c'tors into .text */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+        /* Followed by destructors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.eh_frame*)
+        . = ALIGN(4);
+        __ram_text_end__ = .;
+    } > RAM AT> FLASH
+    __ram_text_source__ = LOADADDR(.text);
+
+
+    .data : {
+        __data_start__ = .;
+        *(vtable)
+
+        *(.time_critical*)
+
+        . = ALIGN(4);
+        *(.rodata*)
+        . = ALIGN(4);
+
+        *(.data*)
+
+        . = ALIGN(4);
+        *(.after_data.*)
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__mutex_array_start = .);
+        KEEP(*(SORT(.mutex_array.*)))
+        KEEP(*(.mutex_array))
+        PROVIDE_HIDDEN (__mutex_array_end = .);
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(SORT(.preinit_array.*)))
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        *(SORT(.fini_array.*))
+        *(.fini_array)
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        *(.jcr)
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+    } > RAM AT> FLASH
+    /* __etext is the name of the .data init source pointer (...) */
+    __etext = LOADADDR(.data);
+
+    .uninitialized_data (COPY): {
+        . = ALIGN(4);
+        *(.uninitialized_data*)
+    } > RAM
+
+    /* Start and end symbols must be word-aligned */
+    .scratch_x : {
+        __scratch_x_start__ = .;
+        *(.scratch_x.*)
+        . = ALIGN(4);
+        __scratch_x_end__ = .;
+    } > SCRATCH_X AT > FLASH
+    __scratch_x_source__ = LOADADDR(.scratch_x);
+
+    .scratch_y : {
+        __scratch_y_start__ = .;
+        *(.scratch_y.*)
+        . = ALIGN(4);
+        __scratch_y_end__ = .;
+    } > SCRATCH_Y AT > FLASH
+    __scratch_y_source__ = LOADADDR(.scratch_y);
+
+    .bss  : {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*)))
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack*_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later
+     *
+     * stack1 section may be empty/missing if platform_launch_core1 is not used */
+
+    /* by default we put core 0 stack at the end of scratch Y, so that if core 1
+     * stack is not used then all of SCRATCH_X is free.
+     */
+    .stack1_dummy (COPY):
+    {
+        *(.stack1*)
+    } > SCRATCH_X
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SCRATCH_Y
+
+    .flash_end : {
+        __flash_binary_end = .;
+    } > FLASH
+
+    /* stack limit is poorly named, but historically is maximum heap ptr */
+    __StackLimit = ORIGIN(RAM) + LENGTH(RAM);
+    __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X);
+    __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y);
+    __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy);
+    __StackBottom = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed")
+
+    ASSERT( __binary_info_header_end - __logical_binary_start <= 256, "Binary info must be in first 256 bytes of the binary")
+    /* todo assert on extra code */
+}
+
diff --git a/src/rp2_common/pico_standard_link/memmap_default.ld b/src/rp2_common/pico_standard_link/memmap_default.ld
new file mode 100644
index 0000000..07d5812
--- /dev/null
+++ b/src/rp2_common/pico_standard_link/memmap_default.ld
@@ -0,0 +1,252 @@
+/* Based on GCC ARM embedded samples.
+   Defines the following symbols for use by code:
+    __exidx_start
+    __exidx_end
+    __etext
+    __data_start__
+    __preinit_array_start
+    __preinit_array_end
+    __init_array_start
+    __init_array_end
+    __fini_array_start
+    __fini_array_end
+    __data_end__
+    __bss_start__
+    __bss_end__
+    __end__
+    end
+    __HeapLimit
+    __StackLimit
+    __StackTop
+    __stack (== StackTop)
+*/
+
+MEMORY
+{
+    FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k
+    RAM(rwx) : ORIGIN =  0x20000000, LENGTH = 256k
+    SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k
+    SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k
+}
+
+ENTRY(_entry_point)
+
+SECTIONS
+{
+    /* Second stage bootloader is prepended to the image. It must be 256 bytes big
+       and checksummed. It is usually built by the boot_stage2 target
+       in the Raspberry Pi Pico SDK
+    */
+
+    .flash_begin : {
+        __flash_binary_start = .;
+    } > FLASH
+
+    .boot2 : {
+        __boot2_start__ = .;
+        KEEP (*(.boot2))
+        __boot2_end__ = .;
+    } > FLASH
+
+    ASSERT(__boot2_end__ - __boot2_start__ == 256,
+        "ERROR: Pico second stage bootloader must be 256 bytes in size")
+
+    /* The second stage will always enter the image at the start of .text.
+       The debugger will use the ELF entry point, which is the _entry_point
+       symbol if present, otherwise defaults to start of .text.
+       This can be used to transfer control back to the bootrom on debugger
+       launches only, to perform proper flash setup.
+    */
+
+    .text : {
+        __logical_binary_start = .;
+        KEEP (*(.vectors))
+        KEEP (*(.binary_info_header))
+        __binary_info_header_end = .;
+        KEEP (*(.reset))
+        /* TODO revisit this now memset/memcpy/float in ROM */
+        /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from
+         * FLASH ... we will include any thing excluded here in .data below by default */
+        *(.init)
+        *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*)
+        *(.fini)
+        /* Pull all c'tors into .text */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+        /* Followed by destructors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.eh_frame*)
+        . = ALIGN(4);
+    } > FLASH
+
+    .rodata : {
+        *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*)
+        . = ALIGN(4);
+        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*)))
+        . = ALIGN(4);
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* Machine inspectable binary information */
+    . = ALIGN(4);
+    __binary_info_start = .;
+    .binary_info :
+    {
+        KEEP(*(.binary_info.keep.*))
+        *(.binary_info.*)
+    } > FLASH
+    __binary_info_end = .;
+    . = ALIGN(4);
+
+    /* End of .text-like segments */
+    __etext = .;
+
+   .ram_vector_table (COPY): {
+        *(.ram_vector_table)
+    } > RAM
+
+    .data : {
+        __data_start__ = .;
+        *(vtable)
+
+        *(.time_critical*)
+
+        /* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM */
+        *(.text*)
+        . = ALIGN(4);
+        *(.rodata*)
+        . = ALIGN(4);
+
+        *(.data*)
+
+        . = ALIGN(4);
+        *(.after_data.*)
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__mutex_array_start = .);
+        KEEP(*(SORT(.mutex_array.*)))
+        KEEP(*(.mutex_array))
+        PROVIDE_HIDDEN (__mutex_array_end = .);
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(SORT(.preinit_array.*)))
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        *(SORT(.fini_array.*))
+        *(.fini_array)
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        *(.jcr)
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+    } > RAM AT> FLASH
+
+    .uninitialized_data (COPY): {
+        . = ALIGN(4);
+        *(.uninitialized_data*)
+    } > RAM
+
+    /* Start and end symbols must be word-aligned */
+    .scratch_x : {
+        __scratch_x_start__ = .;
+        *(.scratch_x.*)
+        . = ALIGN(4);
+        __scratch_x_end__ = .;
+    } > SCRATCH_X AT > FLASH
+    __scratch_x_source__ = LOADADDR(.scratch_x);
+
+    .scratch_y : {
+        __scratch_y_start__ = .;
+        *(.scratch_y.*)
+        . = ALIGN(4);
+        __scratch_y_end__ = .;
+    } > SCRATCH_Y AT > FLASH
+    __scratch_y_source__ = LOADADDR(.scratch_y);
+
+    .bss  : {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*)))
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack*_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later
+     *
+     * stack1 section may be empty/missing if platform_launch_core1 is not used */
+
+    /* by default we put core 0 stack at the end of scratch Y, so that if core 1
+     * stack is not used then all of SCRATCH_X is free.
+     */
+    .stack1_dummy (COPY):
+    {
+        *(.stack1*)
+    } > SCRATCH_X
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SCRATCH_Y
+
+    .flash_end : {
+        __flash_binary_end = .;
+    } > FLASH
+
+    /* stack limit is poorly named, but historically is maximum heap ptr */
+    __StackLimit = ORIGIN(RAM) + LENGTH(RAM);
+    __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X);
+    __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y);
+    __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy);
+    __StackBottom = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed")
+
+    ASSERT( __binary_info_header_end - __logical_binary_start <= 256, "Binary info must be in first 256 bytes of the binary")
+    /* todo assert on extra code */
+}
+
diff --git a/src/rp2_common/pico_standard_link/memmap_no_flash.ld b/src/rp2_common/pico_standard_link/memmap_no_flash.ld
new file mode 100644
index 0000000..7a5977f
--- /dev/null
+++ b/src/rp2_common/pico_standard_link/memmap_no_flash.ld
@@ -0,0 +1,217 @@
+/* Based on GCC ARM embedded samples.
+   Defines the following symbols for use by code:
+    __exidx_start
+    __exidx_end
+    __etext
+    __data_start__
+    __preinit_array_start
+    __preinit_array_end
+    __init_array_start
+    __init_array_end
+    __fini_array_start
+    __fini_array_end
+    __data_end__
+    __bss_start__
+    __bss_end__
+    __end__
+    end
+    __HeapLimit
+    __StackLimit
+    __StackTop
+    __stack (== StackTop)
+*/
+
+MEMORY
+{
+    RAM(rwx) : ORIGIN =  0x20000000, LENGTH = 256k
+    SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k
+    SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k
+}
+
+ENTRY(_entry_point)
+
+SECTIONS
+{
+    /* Note in NO_FLASH builds the entry point for both the bootrom, and debugger
+       entry (ELF entry point), are *first* in the image, and the vector table
+       follows immediately afterward. This is because the bootrom enters RAM
+       binaries directly at their lowest address (preferring main RAM over XIP
+       cache-as-SRAM if both are used).
+    */
+
+    .text : {
+        __logical_binary_start = .;
+        __reset_start = .;
+        KEEP (*(.reset))
+        __reset_end = .;
+        KEEP (*(.binary_info_header))
+        __binary_info_header_end = .;
+        . = ALIGN(256);
+          KEEP (*(.vectors))
+        *(.time_critical*)
+        *(.text*)
+        . = ALIGN(4);
+        *(.init)
+        *(.fini)
+        /* Pull all c'tors into .text */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+        /* Followed by destructors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.eh_frame*)
+    } > RAM
+
+    .rodata : {
+        *(.rodata*)
+        . = ALIGN(4);
+        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*)))
+        . = ALIGN(4);
+    } > RAM
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > RAM
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > RAM
+    __exidx_end = .;
+
+    /* Machine inspectable binary information */
+    . = ALIGN(4);
+    __binary_info_start = .;
+    .binary_info :
+    {
+        KEEP(*(.binary_info.keep.*))
+        *(.binary_info.*)
+    } > RAM
+    __binary_info_end = .;
+    . = ALIGN(4);
+
+    .data : {
+        /* End of .text-like segments */
+        __etext = .;
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        *(.after_data.*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__mutex_array_start = .);
+        KEEP(*(SORT(.mutex_array.*)))
+        KEEP(*(.mutex_array))
+        PROVIDE_HIDDEN (__mutex_array_end = .);
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(SORT(.preinit_array.*)))
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        *(SORT(.fini_array.*))
+        *(.fini_array)
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        *(.jcr)
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+    } > RAM
+
+    .uninitialized_data (COPY): {
+        . = ALIGN(4);
+        *(.uninitialized_data*)
+    } > RAM
+
+    /* Start and end symbols must be word-aligned */
+    .scratch_x : {
+        __scratch_x_start__ = .;
+        *(.scratch_x.*)
+        . = ALIGN(4);
+        __scratch_x_end__ = .;
+    } > SCRATCH_X
+    __scratch_x_source__ = LOADADDR(.scratch_x);
+
+    .scratch_y : {
+        __scratch_y_start__ = .;
+        *(.scratch_y.*)
+        . = ALIGN(4);
+        __scratch_y_end__ = .;
+    } > SCRATCH_Y
+    __scratch_y_source__ = LOADADDR(.scratch_y);
+
+    .bss  : {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*)))
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack*_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later
+     *
+     * stack1 section may be empty/missing if platform_launch_core1 is not used */
+
+    /* by default we put core 0 stack at the end of scratch Y, so that if core 1
+     * stack is not used then all of SCRATCH_X is free.
+     */
+    .stack1_dummy (COPY):
+    {
+        *(.stack1*)
+    } > SCRATCH_X
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SCRATCH_Y
+
+    /* stack limit is poorly named, but historically is maximum heap ptr */
+    __StackLimit = ORIGIN(RAM) + LENGTH(RAM);
+    __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X);
+    __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y);
+    __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy);
+    __StackBottom = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed")
+
+    ASSERT( __binary_info_header_end - __logical_binary_start <= 256, "Binary info must be in first 256 bytes of the binary")
+    /* todo assert on extra code */
+}
+
diff --git a/src/rp2_common/pico_standard_link/new_delete.cpp b/src/rp2_common/pico_standard_link/new_delete.cpp
new file mode 100644
index 0000000..c122dc0
--- /dev/null
+++ b/src/rp2_common/pico_standard_link/new_delete.cpp
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if !PICO_CXX_ENABLE_EXCEPTIONS
+// Override the standard allocators to use regular malloc/free
+
+#include <cstdlib>
+
+void *operator new(std::size_t n) {
+    return std::malloc(n);
+}
+
+void *operator new[](std::size_t n) {
+    return std::malloc(n);
+}
+
+void operator delete(void *p) { std::free(p); }
+
+void operator delete[](void *p) noexcept { std::free(p); }
+
+#if __cpp_sized_deallocation
+
+void operator delete(void *p, __unused std::size_t n) noexcept { std::free(p); }
+
+void operator delete[](void *p, __unused std::size_t n) noexcept { std::free(p); }
+
+#endif
+
+#endif
diff --git a/src/rp2_common/pico_stdio/CMakeLists.txt b/src/rp2_common/pico_stdio/CMakeLists.txt
new file mode 100644
index 0000000..cdc9c3b
--- /dev/null
+++ b/src/rp2_common/pico_stdio/CMakeLists.txt
@@ -0,0 +1,19 @@
+if (NOT TARGET pico_stdio)
+    pico_add_impl_library(pico_stdio)
+
+    target_include_directories(pico_stdio INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+    target_sources(pico_stdio INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/stdio.c
+    )
+
+    pico_wrap_function(pico_stdio printf)
+    pico_wrap_function(pico_stdio vprintf)
+    pico_wrap_function(pico_stdio puts)
+    pico_wrap_function(pico_stdio putchar)
+    pico_wrap_function(pico_stdio getchar)
+
+    if (TARGET pico_printf)
+        target_link_libraries(pico_stdio INTERFACE pico_printf)
+    endif()
+endif()
\ No newline at end of file
diff --git a/src/rp2_common/pico_stdio/LICENSE b/src/rp2_common/pico_stdio/LICENSE
new file mode 100644
index 0000000..8f7ebd0
--- /dev/null
+++ b/src/rp2_common/pico_stdio/LICENSE
@@ -0,0 +1,22 @@
+The MIT License (MIT)
+
+Copyright (c) 2014 Marco Paland
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+
diff --git a/src/rp2_common/pico_stdio/include/pico/stdio.h b/src/rp2_common/pico_stdio/include/pico/stdio.h
new file mode 100644
index 0000000..e44c01d
--- /dev/null
+++ b/src/rp2_common/pico_stdio/include/pico/stdio.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_STDIO_H
+#define _PICO_STDIO_H
+
+/** \file stdio.h
+*  \defgroup pico_stdio pico_stdio
+* Customized stdio support allowing for input and output from UART, USB, semi-hosting etc.
+*
+* Note the API for adding additional input output devices is not yet considered stable
+*/
+
+#include "pico.h"
+
+// PICO_CONFIG: PICO_STDOUT_MUTEX, Enable/disable mutex around stdout, type=bool, default=1, group=pico_stdio
+#ifndef PICO_STDOUT_MUTEX
+#define PICO_STDOUT_MUTEX 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_ENABLE_CRLF_SUPPORT, Enable/disable CR/LF output conversion support, type=bool, default=1, group=pico_stdio
+#ifndef PICO_STDIO_ENABLE_CRLF_SUPPORT
+#define PICO_STDIO_ENABLE_CRLF_SUPPORT 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_DEFAULT_CRLF, Default for CR/LF conversion enabled on all stdio outputs, type=bool, default=1, depends=PICO_STDIO_ENABLE_CRLF_SUPPORT, group=pico_stdio
+#ifndef PICO_STDIO_DEFAULT_CRLF
+#define PICO_STDIO_DEFAULT_CRLF 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_STACK_BUFFER_SIZE, Define printf buffer size (on stack)... this is just a working buffer not a max output size, min=0, max=512, default=128, group=pico_stdio
+#ifndef PICO_STDIO_STACK_BUFFER_SIZE
+#define PICO_STDIO_STACK_BUFFER_SIZE 128
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef struct stdio_driver stdio_driver_t;
+
+/*! \brief Initialize all of the present standard stdio types that are linked into the binary.
+ * \ingroup pico_stdio
+ *
+ * Call this method once you have set up your clocks to enable the stdio support for UART, USB
+ * and semihosting based on the presence of the respective libraries in the binary.
+ *
+ * When stdio_usb is configured, this method can be optionally made to block, waiting for a connection
+ * via the variables specified in \ref stdio_usb_init (i.e. \ref PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS)
+ *
+ * \see stdio_uart, stdio_usb, stdio_semihosting
+ */
+void stdio_init_all(void);
+
+/*! \brief Initialize all of the present standard stdio types that are linked into the binary.
+ * \ingroup pico_stdio
+ *
+ * Call this method once you have set up your clocks to enable the stdio support for UART, USB
+ * and semihosting based on the presence of the respective libraries in the binary.
+ *
+ * \see stdio_uart, stdio_usb, stdio_semihosting
+ */
+void stdio_flush(void);
+
+/*! \brief Return a character from stdin if there is one available within a timeout
+ * \ingroup pico_stdio
+ *
+ * \param timeout_us the timeout in microseconds, or 0 to not wait for a character if none available.
+ * \return the character from 0-255 or PICO_ERROR_TIMEOUT if timeout occurs
+ */
+int getchar_timeout_us(uint32_t timeout_us);
+
+/*! \brief Adds or removes a driver from the list of active drivers used for input/output
+ * \ingroup pico_stdio
+ *
+ * \note this method should always be called on an initialized driver and is not re-entrant
+ * \param driver the driver
+ * \param enabled true to add, false to remove
+ */
+void stdio_set_driver_enabled(stdio_driver_t *driver, bool enabled);
+
+/*! \brief Control limiting of output to a single driver
+ * \ingroup pico_stdio
+ *
+ * \note this method should always be called on an initialized driver
+ *
+ * \param driver if non-null then output only that driver will be used for input/output (assuming it is in the list of enabled drivers).
+ *               if NULL then all enabled drivers will be used
+ */
+void stdio_filter_driver(stdio_driver_t *driver);
+
+/*! \brief control conversion of line feeds to carriage return on transmissions
+ * \ingroup pico_stdio
+ *
+ * \note this method should always be called on an initialized driver
+ *
+ * \param driver the driver
+ * \param translate If true, convert line feeds to carriage return on transmissions
+ */
+void stdio_set_translate_crlf(stdio_driver_t *driver, bool translate);
+
+/*! \brief putchar variant that skips any CR/LF conversion if enabled
+ * \ingroup pico_stdio
+ */
+int putchar_raw(int c);
+
+/*! \brief puts variant that skips any CR/LF conversion if enabled
+ * \ingroup pico_stdio
+ */
+int puts_raw(const char *s);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/pico_stdio/include/pico/stdio/driver.h b/src/rp2_common/pico_stdio/include/pico/stdio/driver.h
new file mode 100644
index 0000000..1c8c27c
--- /dev/null
+++ b/src/rp2_common/pico_stdio/include/pico/stdio/driver.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_STDIO_DRIVER_H
+#define _PICO_STDIO_DRIVER_H
+
+#include "pico/stdio.h"
+#include "pico/platform.h"
+
+struct stdio_driver {
+    void (*out_chars)(const char *buf, int len);
+    void (*out_flush)(void);
+    int (*in_chars)(char *buf, int len);
+    stdio_driver_t *next;
+#if PICO_STDIO_ENABLE_CRLF_SUPPORT
+    bool last_ended_with_cr;
+    bool crlf_enabled;
+#endif
+};
+
+#endif
diff --git a/src/rp2_common/pico_stdio/stdio.c b/src/rp2_common/pico_stdio/stdio.c
new file mode 100644
index 0000000..b457b8a
--- /dev/null
+++ b/src/rp2_common/pico_stdio/stdio.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+#include <stdio.h>
+#include <stdarg.h>
+
+#include "pico.h"
+#include "pico/mutex.h"
+#if LIB_PICO_PRINTF_PICO
+#include "pico/printf.h"
+#endif
+#include "pico/stdio.h"
+#include "pico/stdio/driver.h"
+#include "pico/time.h"
+
+#if LIB_PICO_STDIO_UART
+#include "pico/stdio_uart.h"
+#endif
+
+#if LIB_PICO_STDIO_USB
+#include "pico/stdio_usb.h"
+#endif
+
+#if LIB_PICO_STDIO_SEMIHOSTING
+#include "pico/stdio_semihosting.h"
+#endif
+
+static stdio_driver_t *drivers;
+static stdio_driver_t *filter;
+
+#if PICO_STDOUT_MUTEX
+auto_init_mutex(print_mutex);
+
+bool stdout_serialize_begin(void) {
+    lock_owner_id_t caller = lock_get_caller_owner_id();
+    // not using lock_owner_id_t to avoid backwards incompatibility change to mutex_try_enter API
+    static_assert(sizeof(lock_owner_id_t) <= 4, "");
+    uint32_t owner;
+    if (!mutex_try_enter(&print_mutex, &owner)) {
+        if (owner == (uint32_t)caller) {
+            return false;
+        }
+        // we are not a nested call, so lets wait
+        mutex_enter_blocking(&print_mutex);
+    }
+    return true;
+}
+
+void stdout_serialize_end(void) {
+    mutex_exit(&print_mutex);
+}
+
+#else
+static bool stdout_serialize_begin(void) {
+    return true;
+}
+static void stdout_serialize_end(void) {
+}
+#endif
+static void stdio_out_chars_no_crlf(stdio_driver_t *driver, const char *s, int len) {
+    driver->out_chars(s, len);
+}
+
+static void stdio_out_chars_crlf(stdio_driver_t *driver, const char *s, int len) {
+#if PICO_STDIO_ENABLE_CRLF_SUPPORT
+    if (!driver->crlf_enabled) {
+        driver->out_chars(s, len);
+        return;
+    }
+    int first_of_chunk = 0;
+    static const char crlf_str[] = {'\r', '\n'};
+    for (int i = 0; i < len; i++) {
+        bool prev_char_was_cr = i > 0 ? s[i - 1] == '\r' : driver->last_ended_with_cr;
+        if (s[i] == '\n' && !prev_char_was_cr) {
+            if (i > first_of_chunk) {
+                driver->out_chars(&s[first_of_chunk], i - first_of_chunk);
+            }
+            driver->out_chars(crlf_str, 2);
+            first_of_chunk = i + 1;
+        }
+    }
+    if (first_of_chunk < len) {
+        driver->out_chars(&s[first_of_chunk], len - first_of_chunk);
+    }
+    if (len > 0) {
+        driver->last_ended_with_cr = s[len - 1] == '\r';
+    }
+#else
+    driver->out_chars(s, len);
+#endif
+}
+
+static bool stdio_put_string(const char *s, int len, bool newline, bool no_cr) {
+    bool serialized = stdout_serialize_begin();
+    if (!serialized) {
+#if PICO_STDIO_IGNORE_NESTED_STDOUT
+        return false;
+#endif
+    }
+    if (len == -1) len = (int)strlen(s);
+    void (*out_func)(stdio_driver_t *, const char *, int) = no_cr ? stdio_out_chars_no_crlf : stdio_out_chars_crlf;
+    for (stdio_driver_t *driver = drivers; driver; driver = driver->next) {
+        if (!driver->out_chars) continue;
+        if (filter && filter != driver) continue;
+        out_func(driver, s, len);
+        if (newline) {
+            const char c = '\n';
+            out_func(driver, &c, 1);
+        }
+    }
+    if (serialized) {
+        stdout_serialize_end();
+    }
+    return len;
+}
+
+static int stdio_get_until(char *buf, int len, absolute_time_t until) {
+    do {
+        // todo round robin might be nice on each call, but then again hopefully
+        //  no source will starve the others
+        for (stdio_driver_t *driver = drivers; driver; driver = driver->next) {
+            if (filter && filter != driver) continue;
+            if (driver->in_chars) {
+                int read = driver->in_chars(buf, len);
+                if (read > 0) {
+                    return read;
+                }
+            }
+        }
+        // we sleep here in case the in_chars methods acquire mutexes or disable IRQs and
+        // potentially starve out what they are waiting on (have seen this with USB)
+        busy_wait_us(1);
+    } while (!time_reached(until));
+    return PICO_ERROR_TIMEOUT;
+}
+
+int WRAPPER_FUNC(putchar)(int c) {
+    char cc = (char)c;
+    stdio_put_string(&cc, 1, false, false);
+    return c;
+}
+
+int WRAPPER_FUNC(puts)(const char *s) {
+    int len = (int)strlen(s);
+    stdio_put_string(s, len, true, false);
+    stdio_flush();
+    return len;
+}
+
+int putchar_raw(int c) {
+    char cc = (char)c;
+    stdio_put_string(&cc, 1, false, true);
+    return c;
+}
+
+int puts_raw(const char *s) {
+    int len = (int)strlen(s);
+    stdio_put_string(s, len, true, true);
+    stdio_flush();
+    return len;
+}
+
+int _read(int handle, char *buffer, int length) {
+    if (handle == 0) {
+        return stdio_get_until(buffer, length, at_the_end_of_time);
+    }
+    return -1;
+}
+
+int _write(int handle, char *buffer, int length) {
+    if (handle == 1) {
+        stdio_put_string(buffer, length, false, false);
+        return length;
+    }
+    return -1;
+}
+
+void stdio_set_driver_enabled(stdio_driver_t *driver, bool enable) {
+    stdio_driver_t *prev = drivers;
+    for (stdio_driver_t *d = drivers; d; d = d->next) {
+        if (d == driver) {
+            if (!enable) {
+                prev->next = d->next;
+                driver->next = NULL;
+            }
+            return;
+        }
+        prev = d;
+    }
+    if (enable) {
+        if (prev) prev->next = driver;
+        else drivers = driver;
+    }
+}
+
+void stdio_flush() {
+    for (stdio_driver_t *d = drivers; d; d = d->next) {
+        if (d->out_flush) d->out_flush();
+    }
+}
+
+typedef struct stdio_stack_buffer {
+    int used;
+    char buf[PICO_STDIO_STACK_BUFFER_SIZE];
+} stdio_stack_buffer_t;
+
+static void stdio_stack_buffer_flush(stdio_stack_buffer_t *buffer) {
+    if (buffer->used) {
+        for (stdio_driver_t *d = drivers; d; d = d->next) {
+            if (!d->out_chars) continue;
+            if (filter && filter != d) continue;
+            stdio_out_chars_crlf(d, buffer->buf, buffer->used);
+        }
+        buffer->used = 0;
+    }
+}
+
+static void stdio_buffered_printer(char c, void *arg) {
+    stdio_stack_buffer_t *buffer = (stdio_stack_buffer_t *)arg;
+    if (buffer->used == PICO_STDIO_STACK_BUFFER_SIZE) {
+        stdio_stack_buffer_flush(buffer);
+    }
+    buffer->buf[buffer->used++] = c;
+}
+
+int WRAPPER_FUNC(vprintf)(const char *format, va_list va) {
+    bool serialzed = stdout_serialize_begin();
+    if (!serialzed) {
+#if PICO_STDIO_IGNORE_NESTED_STDOUT
+        return 0;
+#endif
+    }
+    int ret;
+#if LIB_PICO_PRINTF_PICO
+    struct stdio_stack_buffer buffer = {.used = 0};
+    ret = vfctprintf(stdio_buffered_printer, &buffer, format, va);
+    stdio_stack_buffer_flush(&buffer);
+    stdio_flush();
+#elif LIB_PICO_PRINTF_NONE
+    extern void printf_none_assert();
+    printf_none_assert();
+#else
+    extern int REAL_FUNC(vprintf)(const char *format, va_list va);
+    ret = REAL_FUNC(vprintf)(format, va);
+#endif
+    if (serialzed) {
+        stdout_serialize_end();
+    }
+    return ret;
+}
+
+int __printflike(1, 0) WRAPPER_FUNC(printf)(const char* format, ...)
+{
+    va_list va;
+    va_start(va, format);
+    int ret = vprintf(format, va);
+    va_end(va);
+    return ret;
+}
+
+void stdio_init_all(void) {
+    // todo add explicit custom, or registered although you can call stdio_enable_driver explicitly anyway
+    // These are well known ones
+#if LIB_PICO_STDIO_UART
+    stdio_uart_init();
+#endif
+
+#if LIB_PICO_STDIO_SEMIHOSTING
+    stdio_semihosting_init();
+#endif
+
+#if LIB_PICO_STDIO_USB
+    stdio_usb_init();
+#endif
+}
+
+int WRAPPER_FUNC(getchar)(void) {
+    char buf[1];
+    int len = stdio_get_until(buf, 1, at_the_end_of_time);
+    if (len < 0) return len;
+    assert(len == 1);
+    return (uint8_t)buf[0];
+}
+
+int getchar_timeout_us(uint32_t timeout_us) {
+    char buf[1];
+    int rc = stdio_get_until(buf, sizeof(buf), make_timeout_time_us(timeout_us));
+    if (rc < 0) return rc;
+    assert(rc);
+    return (uint8_t)buf[0];
+}
+
+void stdio_filter_driver(stdio_driver_t *driver) {
+    filter = driver;
+}
+
+void stdio_set_translate_crlf(stdio_driver_t *driver, bool enabled) {
+#if PICO_STDIO_ENABLE_CRLF_SUPPORT
+    if (enabled && !driver->crlf_enabled) {
+        driver->last_ended_with_cr = false;
+    }
+    driver->crlf_enabled = enabled;
+#else
+    panic_unsupported();
+#endif
+}
diff --git a/src/rp2_common/pico_stdio_semihosting/CMakeLists.txt b/src/rp2_common/pico_stdio_semihosting/CMakeLists.txt
new file mode 100644
index 0000000..699170e
--- /dev/null
+++ b/src/rp2_common/pico_stdio_semihosting/CMakeLists.txt
@@ -0,0 +1,9 @@
+pico_add_impl_library(pico_stdio_semihosting)
+
+target_sources(pico_stdio_semihosting INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/stdio_semihosting.c
+)
+
+target_include_directories(pico_stdio_semihosting INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+target_link_libraries(pico_stdio_semihosting INTERFACE pico_stdio)
\ No newline at end of file
diff --git a/src/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h b/src/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h
new file mode 100644
index 0000000..3304368
--- /dev/null
+++ b/src/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_STDIO_SEMIHOSTING_H
+#define _PICO_STDIO_SEMIHOSTING_H
+
+#include "pico/stdio.h"
+
+/** \brief Experimental support for stdout using RAM semihosting
+ *  \defgroup pico_stdio_semihosting pico_stdio_semihosting
+ *  \ingroup pico_stdio
+ *
+ *  Linking this library or calling `pico_enable_stdio_semihosting(TARGET)` in the CMake (which
+ *  achieves the same thing) will add semihosting to the drivers used for standard output
+ */
+
+// PICO_CONFIG: PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF, Default state of CR/LF translation for semihosting output, type=bool, default=PICO_STDIO_DEFAULT_CRLF, group=pico_stdio_semihosting
+#ifndef PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF
+#define PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF PICO_STDIO_DEFAULT_CRLF
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern stdio_driver_t stdio_semihosting;
+
+/*! \brief Explicitly initialize stdout over semihosting and add it to the current set of stdout targets
+ *  \ingroup pico_stdio_semihosting
+ *
+ * \note this method is automatically called by \ref stdio_init_all() if `pico_stdio_semihosting` is included in the build
+ */
+void stdio_semihosting_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/pico_stdio_semihosting/stdio_semihosting.c b/src/rp2_common/pico_stdio_semihosting/stdio_semihosting.c
new file mode 100644
index 0000000..4eb673f
--- /dev/null
+++ b/src/rp2_common/pico_stdio_semihosting/stdio_semihosting.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/stdio/driver.h"
+#include "pico/stdio_semihosting.h"
+#include "pico/binary_info.h"
+
+//static void __attribute__((naked)) semihosting_puts(const char *s) {
+//    __asm (
+//
+//    "mov r1, r0\n"
+//    "mov r0, #4\n"
+//    "bkpt 0xab\n"
+//    "bx lr\n"
+//    );
+//}
+
+static void __attribute__((naked)) semihosting_putc(__unused const char *c) {
+    __asm (
+
+    "mov r1, r0\n"
+    "mov r0, #3\n"
+    "bkpt 0xab\n"
+    "bx lr\n"
+    );
+}
+
+
+static void stdio_semihosting_out_chars(const char *buf, int length) {
+    for (int i = 0; i < length; i++) {
+        semihosting_putc(&buf[i]);
+    }
+}
+
+stdio_driver_t stdio_semihosting = {
+        .out_chars = stdio_semihosting_out_chars,
+#if PICO_STDIO_ENABLE_CRLF_SUPPORT
+        .crlf_enabled = PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF
+#endif
+};
+
+void stdio_semihosting_init() {
+#if !PICO_NO_BI_STDIO_SEMIHOSTING
+    bi_decl_if_func_used(bi_program_feature("semihosting stdout"));
+#endif
+    stdio_set_driver_enabled(&stdio_semihosting, true);
+}
+
diff --git a/src/rp2_common/pico_stdio_uart/CMakeLists.txt b/src/rp2_common/pico_stdio_uart/CMakeLists.txt
new file mode 100644
index 0000000..d10507b
--- /dev/null
+++ b/src/rp2_common/pico_stdio_uart/CMakeLists.txt
@@ -0,0 +1,9 @@
+pico_add_impl_library(pico_stdio_uart)
+
+target_sources(pico_stdio_uart INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/stdio_uart.c
+)
+
+target_include_directories(pico_stdio_uart INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+target_link_libraries(pico_stdio_uart INTERFACE pico_stdio)
\ No newline at end of file
diff --git a/src/rp2_common/pico_stdio_uart/include/pico/stdio_uart.h b/src/rp2_common/pico_stdio_uart/include/pico/stdio_uart.h
new file mode 100644
index 0000000..5afe910
--- /dev/null
+++ b/src/rp2_common/pico_stdio_uart/include/pico/stdio_uart.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_STDIO_UART_H
+#define _PICO_STDIO_UART_H
+
+#include "pico/stdio.h"
+#include "hardware/uart.h"
+
+/** \brief Support for stdin/stdout using UART
+ *  \defgroup pico_stdio_uart pico_stdio_uart
+ *  \ingroup pico_stdio
+ *
+ *  Linking this library or calling `pico_enable_stdio_uart(TARGET)` in the CMake (which
+ *  achieves the same thing) will add UART to the drivers used for standard output
+ */
+
+// PICO_CONFIG: PICO_STDIO_UART_DEFAULT_CRLF, Default state of CR/LF translation for UART output, type=bool, default=PICO_STDIO_DEFAULT_CRLF, group=pico_stdio_uart
+#ifndef PICO_STDIO_UART_DEFAULT_CRLF
+#define PICO_STDIO_UART_DEFAULT_CRLF PICO_STDIO_DEFAULT_CRLF
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern stdio_driver_t stdio_uart;
+
+/*! \brief Explicitly initialize stdin/stdout over UART and add it to the current set of stdin/stdout drivers
+ *  \ingroup pico_stdio_uart
+ *
+ * This method sets up PICO_DEFAULT_UART_TX_PIN for UART output (if defined), PICO_DEFAULT_UART_RX_PIN for input (if defined)
+ * and configures the baud rate as PICO_DEFAULT_UART_BAUD_RATE.
+ *
+ * \note this method is automatically called by \ref stdio_init_all() if `pico_stdio_uart` is included in the build
+ */
+void stdio_uart_init(void);
+
+/*! \brief Explicitly initialize stdout only (no stdin) over UART and add it to the current set of stdout drivers
+ *  \ingroup pico_stdio_uart
+ *
+ * This method sets up PICO_DEFAULT_UART_TX_PIN for UART output (if defined) , and configures the baud rate as PICO_DEFAULT_UART_BAUD_RATE
+ */
+void stdout_uart_init(void);
+
+/*! \brief Explicitly initialize stdin only (no stdout) over UART and add it to the current set of stdin drivers
+ *  \ingroup pico_stdio_uart
+ *
+ * This method sets up PICO_DEFAULT_UART_RX_PIN for UART input (if defined) , and configures the baud rate as PICO_DEFAULT_UART_BAUD_RATE
+ */
+void stdin_uart_init(void);
+
+/*! \brief Perform custom initialization initialize stdin/stdout over UART and add it to the current set of stdin/stdout drivers
+ *  \ingroup pico_stdio_uart
+ *
+ * \param uart the uart instance to use, \ref uart0 or \ref uart1
+ * \param baud_rate the baud rate in Hz
+ * \param tx_pin the UART pin to use for stdout (or -1 for no stdout)
+ * \param rx_pin the UART pin to use for stdin (or -1 for no stdin)
+ */
+void stdio_uart_init_full(uart_inst_t *uart, uint baud_rate, int tx_pin, int rx_pin);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/pico_stdio_uart/stdio_uart.c b/src/rp2_common/pico_stdio_uart/stdio_uart.c
new file mode 100644
index 0000000..b8ff761
--- /dev/null
+++ b/src/rp2_common/pico_stdio_uart/stdio_uart.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/stdio/driver.h"
+#include "pico/stdio_uart.h"
+#include "pico/binary_info.h"
+#include "hardware/gpio.h"
+
+static uart_inst_t *uart_instance;
+
+#if PICO_NO_BI_STDIO_UART
+#define stdio_bi_decl_if_func_used(x)
+#else
+#define stdio_bi_decl_if_func_used bi_decl_if_func_used
+#endif
+
+void stdio_uart_init() {
+#ifdef uart_default
+    int tx_pin = -1;
+    int rx_pin = -1;
+#ifdef PICO_DEFAULT_UART_TX_PIN
+    tx_pin = PICO_DEFAULT_UART_TX_PIN;
+#ifdef PICO_DEFAULT_UART_RX_PIN
+    rx_pin = PICO_DEFAULT_UART_RX_PIN;
+    stdio_bi_decl_if_func_used(bi_program_feature("UART stdin / stdout"));
+    bi_decl_if_func_used(bi_2pins_with_func(PICO_DEFAULT_UART_RX_PIN, PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART));
+#else
+    stdio_bi_decl_if_func_used(bi_program_feature("UART stdout"));
+    bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART));
+#endif
+#elif defined(PICO_DEFAULT_UART_RX_PIN)
+    rx_pin = PICO_DEFAULT_UART_RX_PIN;
+    stdio_bi_decl_if_func_used(bi_program_feature("UART stdin"));
+    bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_RX_PIN, GPIO_FUNC_UART));
+#endif
+#if !defined(PICO_DEFAULT_UART_BAUD_RATE)
+    panic("UART baud rate undefined");
+#else
+    stdio_uart_init_full(uart_default, PICO_DEFAULT_UART_BAUD_RATE, tx_pin, rx_pin);
+#endif
+#endif
+}
+
+void stdout_uart_init() {
+#if defined(uart_default) && defined(PICO_DEFAULT_UART_TX_PIN)
+    bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART));
+#if !defined(PICO_DEFAULT_UART_BAUD_RATE)
+    panic("UART baud rate undefined");
+#else
+    stdio_bi_decl_if_func_used(bi_program_feature("UART stdout"));
+    stdio_uart_init_full(uart_default, PICO_DEFAULT_UART_BAUD_RATE, PICO_DEFAULT_UART_TX_PIN, -1);
+#endif
+#endif
+}
+
+void stdin_uart_init() {
+#if defined(uart_default) && defined(PICO_DEFAULT_UART_RX_PIN)
+    bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_RX_PIN, GPIO_FUNC_UART));
+#if !defined(PICO_DEFAULT_UART_BAUD_RATE)
+    panic("UART baud rate undefined");
+#else
+    stdio_bi_decl_if_func_used(bi_program_feature("UART stdin"));
+    stdio_uart_init_full(uart_default, PICO_DEFAULT_UART_BAUD_RATE, -1, PICO_DEFAULT_UART_RX_PIN);
+#endif
+#endif
+}
+
+void stdio_uart_init_full(struct uart_inst *uart, uint baud_rate, int tx_pin, int rx_pin) {
+    uart_instance = uart;
+    uart_init(uart_instance, baud_rate);
+    if (tx_pin >= 0) gpio_set_function((uint)tx_pin, GPIO_FUNC_UART);
+    if (rx_pin >= 0) gpio_set_function((uint)rx_pin, GPIO_FUNC_UART);
+    stdio_set_driver_enabled(&stdio_uart, true);
+}
+
+static void stdio_uart_out_chars(const char *buf, int length) {
+    for (int i = 0; i <length; i++) {
+        uart_putc(uart_instance, buf[i]);
+    }
+}
+
+int stdio_uart_in_chars(char *buf, int length) {
+    int i=0;
+    while (i<length && uart_is_readable(uart_instance)) {
+        buf[i++] = uart_getc(uart_instance);
+    }
+    return i ? i : PICO_ERROR_NO_DATA;
+}
+
+stdio_driver_t stdio_uart = {
+    .out_chars = stdio_uart_out_chars,
+    .in_chars = stdio_uart_in_chars,
+#if PICO_STDIO_ENABLE_CRLF_SUPPORT
+    .crlf_enabled = PICO_STDIO_UART_DEFAULT_CRLF
+#endif
+};
diff --git a/src/rp2_common/pico_stdio_usb/CMakeLists.txt b/src/rp2_common/pico_stdio_usb/CMakeLists.txt
new file mode 100644
index 0000000..b6abadd
--- /dev/null
+++ b/src/rp2_common/pico_stdio_usb/CMakeLists.txt
@@ -0,0 +1,19 @@
+if (TARGET tinyusb_device_unmarked)
+    pico_add_impl_library(pico_stdio_usb)
+
+    target_include_directories(pico_stdio_usb INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+    target_sources(pico_stdio_usb INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/reset_interface.c
+        ${CMAKE_CURRENT_LIST_DIR}/stdio_usb.c
+        ${CMAKE_CURRENT_LIST_DIR}/stdio_usb_descriptors.c
+    )
+
+    target_link_libraries(pico_stdio_usb INTERFACE
+        tinyusb_device_unmarked
+        pico_stdio
+        pico_time
+        pico_unique_id
+        pico_usb_reset_interface_headers
+    )
+endif()
diff --git a/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h b/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h
new file mode 100644
index 0000000..2aeb647
--- /dev/null
+++ b/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_STDIO_USB_H
+#define _PICO_STDIO_USB_H
+
+#include "pico/stdio.h"
+
+/** \brief Support for stdin/stdout over USB serial (CDC)
+ *  \defgroup pico_stdio_usb pico_stdio_usb
+ *  \ingroup pico_stdio
+ *
+ *  Linking this library or calling `pico_enable_stdio_usb(TARGET)` in the CMake (which
+ *  achieves the same thing) will add USB CDC to the drivers used for standard output
+ *
+ *  Note this library is a developer convenience. It is not applicable in all cases; for one it takes full control of the USB device precluding your
+ *  use of the USB in device or host mode. For this reason, this library will automatically disengage if you try to using it alongside \ref tinyusb_device or
+ *  \ref tinyusb_host. It also takes control of a lower level IRQ and sets up a periodic background task.
+ *
+ *  This library also includes (by default) functionality to enable the RP2040 to be reset over the USB interface.
+ */
+
+// PICO_CONFIG: PICO_STDIO_USB_DEFAULT_CRLF, Default state of CR/LF translation for USB output, type=bool, default=PICO_STDIO_DEFAULT_CRLF, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_DEFAULT_CRLF
+#define PICO_STDIO_USB_DEFAULT_CRLF PICO_STDIO_DEFAULT_CRLF
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_STDOUT_TIMEOUT_US, Number of microseconds to be blocked trying to write USB output before assuming the host has disappeared and discarding data, default=500000, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_STDOUT_TIMEOUT_US
+#define PICO_STDIO_USB_STDOUT_TIMEOUT_US 500000
+#endif
+
+// todo perhaps unnecessarily frequent?
+// PICO_CONFIG: PICO_STDIO_USB_TASK_INTERVAL_US, Period of microseconds between calling tud_task in the background, default=1000, advanced=true, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_TASK_INTERVAL_US
+#define PICO_STDIO_USB_TASK_INTERVAL_US 1000
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_LOW_PRIORITY_IRQ, low priority (non hardware) IRQ number to claim for tud_task() background execution, default=31, advanced=true, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_LOW_PRIORITY_IRQ
+#define PICO_STDIO_USB_LOW_PRIORITY_IRQ 31
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE, Enable/disable resetting into BOOTSEL mode if the host sets the baud rate to a magic value (PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE), type=bool, default=1, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE
+#define PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE, baud rate that if selected causes a reset into BOOTSEL mode (if PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE is set), default=1200, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE
+#define PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE 1200
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS, Maximum number of milliseconds to wait during initialization for a CDC connection from the host (negative means indefinite) during initialization, default=0, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS
+#define PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS 0
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS, Number of extra milliseconds to wait when using PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS after a host CDC connection is detected (some host terminals seem to sometimes lose transmissions sent right after connection), default=50, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS
+#define PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS 50
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED, Optionally define a pin to use as bootloader activity LED when BOOTSEL mode is entered via USB (either VIA_BAUD_RATE or VIA_VENDOR_INTERFACE), type=int, min=0, max=29, group=pico_stdio_usb
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED, Whether the pin specified by PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED is fixed or can be modified by picotool over the VENDOR USB interface, type=bool, default=0, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED
+#define PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED 0
+#endif
+
+// Any modes disabled here can't be re-enabled by picotool via VENDOR_INTERFACE.
+// PICO_CONFIG: PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK, Optionally disable either the mass storage interface (bit 0) or the PICOBOOT interface (bit 1) when entering BOOTSEL mode via USB (either VIA_BAUD_RATE or VIA_VENDOR_INTERFACE), type=int, min=0, max=3, default=0, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK
+#define PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK 0u
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE, Enable/disable resetting into BOOTSEL mode via an additional VENDOR USB interface - enables picotool based reset, type=bool, default=1, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE
+#define PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL, If vendor reset interface is included allow rebooting to BOOTSEL mode, type=bool, default=1, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL
+#define PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT, If vendor reset interface is included allow rebooting with regular flash boot, type=bool, default=1, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT
+#define PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_RESET_TO_FLASH_DELAY_MS, delays in ms before rebooting via regular flash boot, default=100, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_RESET_TO_FLASH_DELAY_MS
+#define PICO_STDIO_USB_RESET_RESET_TO_FLASH_DELAY_MS 100
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern stdio_driver_t stdio_usb;
+
+/*! \brief Explicitly initialize USB stdio and add it to the current set of stdin drivers
+ *  \ingroup pico_stdio_usb
+ *
+ *  \ref PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS can be set to cause this method to wait for a CDC connection
+ *  from the host before returning, which is useful if you don't want any initial stdout output to be discarded
+ *  before the connection is established.
+ *
+ *  \return true if the USB CDC was initialized, false if an error occurred
+ */
+bool stdio_usb_init(void);
+
+/*! \brief Check if there is an active stdio CDC connection to a host
+ *  \ingroup pico_stdio_usb
+ *
+ *  \return true if stdio is connected over CDC
+ */
+bool stdio_usb_connected(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb/reset_interface.h b/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb/reset_interface.h
new file mode 100644
index 0000000..e0cca10
--- /dev/null
+++ b/src/rp2_common/pico_stdio_usb/include/pico/stdio_usb/reset_interface.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_STDIO_USB_RESET_INTERFACE_H
+#define _PICO_STDIO_USB_RESET_INTERFACE_H
+
+// definitions have been moved here
+#include "pico/usb_reset_interface.h"
+
+#endif
\ No newline at end of file
diff --git a/src/rp2_common/pico_stdio_usb/include/tusb_config.h b/src/rp2_common/pico_stdio_usb/include/tusb_config.h
new file mode 100644
index 0000000..c0a2843
--- /dev/null
+++ b/src/rp2_common/pico_stdio_usb/include/tusb_config.h
@@ -0,0 +1,40 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2020 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _PICO_STDIO_USB_TUSB_CONFIG_H
+#define _PICO_STDIO_USB_TUSB_CONFIG_H
+
+#include "pico/stdio_usb.h"
+
+#define CFG_TUSB_RHPORT0_MODE   (OPT_MODE_DEVICE)
+
+#define CFG_TUD_CDC             (1)
+#define CFG_TUD_CDC_RX_BUFSIZE  (256)
+#define CFG_TUD_CDC_TX_BUFSIZE  (256)
+
+// We use a vendor specific interface but with our own driver
+#define CFG_TUD_VENDOR            (0)
+#endif
diff --git a/src/rp2_common/pico_stdio_usb/reset_interface.c b/src/rp2_common/pico_stdio_usb/reset_interface.c
new file mode 100644
index 0000000..06dce86
--- /dev/null
+++ b/src/rp2_common/pico_stdio_usb/reset_interface.c
@@ -0,0 +1,112 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "tusb.h"
+
+#include "pico/bootrom.h"
+
+#if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE && !(PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL || PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT)
+#warning PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE has been selected but neither PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL nor PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT have been selected.
+#endif
+
+#if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE
+#include "pico/stdio_usb/reset_interface.h"
+#include "hardware/watchdog.h"
+#include "device/usbd_pvt.h"
+
+static uint8_t itf_num;
+
+static void resetd_init(void) {
+}
+
+static void resetd_reset(uint8_t __unused rhport) {
+    itf_num = 0;
+}
+
+static uint16_t resetd_open(uint8_t __unused rhport, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
+    TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass &&
+              RESET_INTERFACE_SUBCLASS == itf_desc->bInterfaceSubClass &&
+              RESET_INTERFACE_PROTOCOL == itf_desc->bInterfaceProtocol, 0);
+
+    uint16_t const drv_len = sizeof(tusb_desc_interface_t);
+    TU_VERIFY(max_len >= drv_len, 0);
+
+    itf_num = itf_desc->bInterfaceNumber;
+    return drv_len;
+}
+
+// Support for parameterized reset via vendor interface control request
+static bool resetd_control_xfer_cb(uint8_t __unused rhport, uint8_t stage, tusb_control_request_t const * request) {
+    // nothing to do with DATA & ACK stage
+    if (stage != CONTROL_STAGE_SETUP) return true;
+
+    if (request->wIndex == itf_num) {
+
+#if PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL
+        if (request->bRequest == RESET_REQUEST_BOOTSEL) {
+#ifdef PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED
+            uint gpio_mask = 1u << PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED;
+#else
+            uint gpio_mask = 0u;
+#endif
+#if !PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED
+            if (request->wValue & 0x100) {
+                gpio_mask = 1u << (request->wValue >> 9u);
+            }
+#endif
+            reset_usb_boot(gpio_mask, (request->wValue & 0x7f) | PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK);
+            // does not return, otherwise we'd return true
+        }
+#endif
+
+#if PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT
+        if (request->bRequest == RESET_REQUEST_FLASH) {
+            watchdog_reboot(0, 0, PICO_STDIO_USB_RESET_RESET_TO_FLASH_DELAY_MS);
+            return true;
+        }
+#endif
+
+    }
+    return false;
+}
+
+static bool resetd_xfer_cb(uint8_t __unused rhport, uint8_t __unused ep_addr, xfer_result_t __unused result, uint32_t __unused xferred_bytes) {
+    return true;
+}
+
+static usbd_class_driver_t const _resetd_driver =
+{
+#if CFG_TUSB_DEBUG >= 2
+    .name = "RESET",
+#endif
+    .init             = resetd_init,
+    .reset            = resetd_reset,
+    .open             = resetd_open,
+    .control_xfer_cb  = resetd_control_xfer_cb,
+    .xfer_cb          = resetd_xfer_cb,
+    .sof              = NULL
+};
+
+// Implement callback to add our custom driver
+usbd_class_driver_t const *usbd_app_driver_get_cb(uint8_t *driver_count) {
+    *driver_count = 1;
+    return &_resetd_driver;
+}
+#endif
+
+#if PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE
+// Support for default BOOTSEL reset by changing baud rate
+void tud_cdc_line_coding_cb(__unused uint8_t itf, cdc_line_coding_t const* p_line_coding) {
+    if (p_line_coding->bit_rate == PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE) {
+#ifdef PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED
+        const uint gpio_mask = 1u << PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED;
+#else
+        const uint gpio_mask = 0u;
+#endif
+        reset_usb_boot(gpio_mask, PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK);
+    }
+}
+#endif
+
diff --git a/src/rp2_common/pico_stdio_usb/stdio_usb.c b/src/rp2_common/pico_stdio_usb/stdio_usb.c
new file mode 100644
index 0000000..913d606
--- /dev/null
+++ b/src/rp2_common/pico_stdio_usb/stdio_usb.c
@@ -0,0 +1,135 @@
+/**
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if !defined(LIB_TINYUSB_HOST) && !defined(LIB_TINYUSB_DEVICE)
+#include "tusb.h"
+
+#include "pico/time.h"
+#include "pico/stdio/driver.h"
+#include "pico/binary_info.h"
+#include "pico/mutex.h"
+#include "hardware/irq.h"
+
+static_assert(PICO_STDIO_USB_LOW_PRIORITY_IRQ > RTC_IRQ, ""); // note RTC_IRQ is currently the last one
+static mutex_t stdio_usb_mutex;
+
+static void low_priority_worker_irq(void) {
+    // if the mutex is already owned, then we are in user code
+    // in this file which will do a tud_task itself, so we'll just do nothing
+    // until the next tick; we won't starve
+    if (mutex_try_enter(&stdio_usb_mutex, NULL)) {
+        tud_task();
+        mutex_exit(&stdio_usb_mutex);
+    }
+}
+
+static int64_t timer_task(__unused alarm_id_t id, __unused void *user_data) {
+    irq_set_pending(PICO_STDIO_USB_LOW_PRIORITY_IRQ);
+    return PICO_STDIO_USB_TASK_INTERVAL_US;
+}
+
+static void stdio_usb_out_chars(const char *buf, int length) {
+    static uint64_t last_avail_time;
+    uint32_t owner;
+    if (!mutex_try_enter(&stdio_usb_mutex, &owner)) {
+        if (owner == get_core_num()) return; // would deadlock otherwise
+        mutex_enter_blocking(&stdio_usb_mutex);
+    }
+    if (tud_cdc_connected()) {
+        for (int i = 0; i < length;) {
+            int n = length - i;
+            int avail = (int) tud_cdc_write_available();
+            if (n > avail) n = avail;
+            if (n) {
+                int n2 = (int) tud_cdc_write(buf + i, (uint32_t)n);
+                tud_task();
+                tud_cdc_write_flush();
+                i += n2;
+                last_avail_time = time_us_64();
+            } else {
+                tud_task();
+                tud_cdc_write_flush();
+                if (!tud_cdc_connected() ||
+                    (!tud_cdc_write_available() && time_us_64() > last_avail_time + PICO_STDIO_USB_STDOUT_TIMEOUT_US)) {
+                    break;
+                }
+            }
+        }
+    } else {
+        // reset our timeout
+        last_avail_time = 0;
+    }
+    mutex_exit(&stdio_usb_mutex);
+}
+
+int stdio_usb_in_chars(char *buf, int length) {
+    uint32_t owner;
+    if (!mutex_try_enter(&stdio_usb_mutex, &owner)) {
+        if (owner == get_core_num()) return PICO_ERROR_NO_DATA; // would deadlock otherwise
+        mutex_enter_blocking(&stdio_usb_mutex);
+    }
+    int rc = PICO_ERROR_NO_DATA;
+    if (tud_cdc_connected() && tud_cdc_available()) {
+        int count = (int) tud_cdc_read(buf, (uint32_t) length);
+        rc =  count ? count : PICO_ERROR_NO_DATA;
+    }
+    mutex_exit(&stdio_usb_mutex);
+    return rc;
+}
+
+stdio_driver_t stdio_usb = {
+    .out_chars = stdio_usb_out_chars,
+    .in_chars = stdio_usb_in_chars,
+#if PICO_STDIO_ENABLE_CRLF_SUPPORT
+    .crlf_enabled = PICO_STDIO_USB_DEFAULT_CRLF
+#endif
+};
+
+bool stdio_usb_init(void) {
+#if !PICO_NO_BI_STDIO_USB
+    bi_decl_if_func_used(bi_program_feature("USB stdin / stdout"));
+#endif
+
+    // initialize TinyUSB
+    tusb_init();
+
+    irq_set_exclusive_handler(PICO_STDIO_USB_LOW_PRIORITY_IRQ, low_priority_worker_irq);
+    irq_set_enabled(PICO_STDIO_USB_LOW_PRIORITY_IRQ, true);
+
+    mutex_init(&stdio_usb_mutex);
+    bool rc = add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true);
+    if (rc) {
+        stdio_set_driver_enabled(&stdio_usb, true);
+#if PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS
+#if PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS > 0
+        absolute_time_t until = make_timeout_time_ms(PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS);
+#else
+        absolute_time_t until = at_the_end_of_time;
+#endif
+        do {
+            if (stdio_usb_connected()) {
+#if PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS != 0
+                sleep_ms(PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS);
+#endif
+                break;
+            }
+            sleep_ms(10);
+        } while (!time_reached(until));
+#endif
+    }
+    return rc;
+}
+
+bool stdio_usb_connected(void) {
+    return tud_cdc_connected();
+}
+#else
+#include "pico/stdio_usb.h"
+#warning stdio USB was configured, but is being disabled as TinyUSB is explicitly linked
+bool stdio_usb_init(void) {
+    return false;
+}
+#endif
diff --git a/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c b/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c
new file mode 100644
index 0000000..b3cfed0
--- /dev/null
+++ b/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c
@@ -0,0 +1,151 @@
+/*
+ * This file is based on a file originally part of the
+ * MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2019 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#if !defined(LIB_TINYUSB_HOST) && !defined(LIB_TINYUSB_DEVICE)
+
+#include "tusb.h"
+#include "pico/stdio_usb/reset_interface.h"
+#include "pico/unique_id.h"
+
+#define USBD_VID (0x2E8A) // Raspberry Pi
+#define USBD_PID (0x000a) // Raspberry Pi Pico SDK CDC
+
+#define TUD_RPI_RESET_DESC_LEN  9
+#if !PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE
+#define USBD_DESC_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN)
+#else
+#define USBD_DESC_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_RPI_RESET_DESC_LEN)
+#endif
+#define USBD_MAX_POWER_MA (250)
+
+#define USBD_ITF_CDC       (0) // needs 2 interfaces
+#if !PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE
+#define USBD_ITF_MAX       (2)
+#else
+#define USBD_ITF_RPI_RESET (2)
+#define USBD_ITF_MAX       (3)
+#endif
+
+#define USBD_CDC_EP_CMD (0x81)
+#define USBD_CDC_EP_OUT (0x02)
+#define USBD_CDC_EP_IN (0x82)
+#define USBD_CDC_CMD_MAX_SIZE (8)
+#define USBD_CDC_IN_OUT_MAX_SIZE (64)
+
+#define USBD_STR_0 (0x00)
+#define USBD_STR_MANUF (0x01)
+#define USBD_STR_PRODUCT (0x02)
+#define USBD_STR_SERIAL (0x03)
+#define USBD_STR_CDC (0x04)
+#define USBD_STR_RPI_RESET (0x05)
+
+// Note: descriptors returned from callbacks must exist long enough for transfer to complete
+
+static const tusb_desc_device_t usbd_desc_device = {
+    .bLength = sizeof(tusb_desc_device_t),
+    .bDescriptorType = TUSB_DESC_DEVICE,
+    .bcdUSB = 0x0200,
+    .bDeviceClass = TUSB_CLASS_MISC,
+    .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol = MISC_PROTOCOL_IAD,
+    .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+    .idVendor = USBD_VID,
+    .idProduct = USBD_PID,
+    .bcdDevice = 0x0100,
+    .iManufacturer = USBD_STR_MANUF,
+    .iProduct = USBD_STR_PRODUCT,
+    .iSerialNumber = USBD_STR_SERIAL,
+    .bNumConfigurations = 1,
+};
+
+#define TUD_RPI_RESET_DESCRIPTOR(_itfnum, _stridx) \
+  /* Interface */\
+  9, TUSB_DESC_INTERFACE, _itfnum, 0, 0, TUSB_CLASS_VENDOR_SPECIFIC, RESET_INTERFACE_SUBCLASS, RESET_INTERFACE_PROTOCOL, _stridx,
+
+static const uint8_t usbd_desc_cfg[USBD_DESC_LEN] = {
+    TUD_CONFIG_DESCRIPTOR(1, USBD_ITF_MAX, USBD_STR_0, USBD_DESC_LEN,
+        0, USBD_MAX_POWER_MA),
+
+    TUD_CDC_DESCRIPTOR(USBD_ITF_CDC, USBD_STR_CDC, USBD_CDC_EP_CMD,
+        USBD_CDC_CMD_MAX_SIZE, USBD_CDC_EP_OUT, USBD_CDC_EP_IN, USBD_CDC_IN_OUT_MAX_SIZE),
+
+#if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE
+    TUD_RPI_RESET_DESCRIPTOR(USBD_ITF_RPI_RESET, USBD_STR_RPI_RESET)
+#endif
+};
+
+static char usbd_serial_str[PICO_UNIQUE_BOARD_ID_SIZE_BYTES * 2 + 1];
+
+static const char *const usbd_desc_str[] = {
+    [USBD_STR_MANUF] = "Raspberry Pi",
+    [USBD_STR_PRODUCT] = "Pico",
+    [USBD_STR_SERIAL] = usbd_serial_str,
+    [USBD_STR_CDC] = "Board CDC",
+#if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE
+    [USBD_STR_RPI_RESET] = "Reset",
+#endif
+};
+
+const uint8_t *tud_descriptor_device_cb(void) {
+    return (const uint8_t *)&usbd_desc_device;
+}
+
+const uint8_t *tud_descriptor_configuration_cb(__unused uint8_t index) {
+    return usbd_desc_cfg;
+}
+
+const uint16_t *tud_descriptor_string_cb(uint8_t index, __unused uint16_t langid) {
+    #define DESC_STR_MAX (20)
+    static uint16_t desc_str[DESC_STR_MAX];
+
+    // Assign the SN using the unique flash id
+    if (!usbd_serial_str[0]) {
+        pico_get_unique_board_id_string(usbd_serial_str, sizeof(usbd_serial_str));
+    }
+
+    uint8_t len;
+    if (index == 0) {
+        desc_str[1] = 0x0409; // supported language is English
+        len = 1;
+    } else {
+        if (index >= sizeof(usbd_desc_str) / sizeof(usbd_desc_str[0])) {
+            return NULL;
+        }
+        const char *str = usbd_desc_str[index];
+        for (len = 0; len < DESC_STR_MAX - 1 && str[len]; ++len) {
+            desc_str[1 + len] = str[len];
+        }
+    }
+
+    // first byte is length (including header), second byte is string type
+    desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * len + 2));
+
+    return desc_str;
+}
+
+#endif
diff --git a/src/rp2_common/pico_stdlib/CMakeLists.txt b/src/rp2_common/pico_stdlib/CMakeLists.txt
new file mode 100644
index 0000000..b54639b
--- /dev/null
+++ b/src/rp2_common/pico_stdlib/CMakeLists.txt
@@ -0,0 +1,45 @@
+# PICO_CMAKE_CONFIG: PICO_STDIO_UART, OPTION: Globally enable stdio UART, default=1, group=pico_stdlib
+option(PICO_STDIO_UART "Globablly enable stdio UART" 1)
+# PICO_CMAKE_CONFIG: PICO_STDIO_USB, OPTION: Globally enable stdio USB, default=0, group=pico_stdlib
+option(PICO_STDIO_USB "Globablly enable stdio USB" 0)
+# PICO_CMAKE_CONFIG: PICO_STDIO_USB, OPTIONS: Globally enable stdio semihosting, default=0, group=pico_stdlib
+option(PICO_STDIO_USB "Globablly enable stdio semihosting " 0)
+
+if (NOT TARGET pico_stdlib)
+    pico_add_impl_library(pico_stdlib)
+    target_sources(pico_stdlib INTERFACE
+            ${CMAKE_CURRENT_LIST_DIR}/stdlib.c
+    )
+    target_link_libraries(pico_stdlib INTERFACE
+        pico_stdlib_headers
+        pico_platform
+        pico_runtime
+        pico_stdio
+        pico_time
+    )
+
+    function(pico_enable_stdio_uart TARGET ENABLED)
+        set_target_properties(${TARGET} PROPERTIES PICO_TARGET_STDIO_UART ${ENABLED})
+    endfunction()
+
+    function(pico_enable_stdio_usb TARGET ENABLED)
+        set_target_properties(${TARGET} PROPERTIES PICO_TARGET_STDIO_USB ${ENABLED})
+    endfunction()
+
+    function(pico_enable_stdio_semihosting TARGET ENABLED)
+        set_target_properties(${TARGET} PROPERTIES PICO_TARGET_STDIO_SEMIHOSTING ${ENABLED})
+    endfunction()
+
+    if (TARGET pico_stdio_uart)
+        target_link_libraries(pico_stdlib INTERFACE $<IF:$<BOOL:$<IF:$<STREQUAL:$<TARGET_PROPERTY:PICO_TARGET_STDIO_UART>,>,${PICO_STDIO_UART},$<TARGET_PROPERTY:PICO_TARGET_STDIO_UART>>>,pico_stdio_uart,>)
+    endif()
+
+    if (TARGET pico_stdio_usb)
+        target_link_libraries(pico_stdlib INTERFACE $<IF:$<BOOL:$<IF:$<STREQUAL:$<TARGET_PROPERTY:PICO_TARGET_STDIO_USB>,>,${PICO_STDIO_USB},$<TARGET_PROPERTY:PICO_TARGET_STDIO_USB>>>,pico_stdio_usb,>)
+    endif()
+
+    if (TARGET pico_stdio_semihosting)
+        target_link_libraries(pico_stdlib INTERFACE $<IF:$<BOOL:$<IF:$<STREQUAL:$<TARGET_PROPERTY:PICO_TARGET_STDIO_SEMIHOSTING>,>,${PICO_STDIO_SEMIHOSTING},$<TARGET_PROPERTY:PICO_TARGET_STDIO_SEMIHOSTING>>>,pico_stdio_semihosting,>)
+    endif()
+
+endif()
diff --git a/src/rp2_common/pico_stdlib/stdlib.c b/src/rp2_common/pico_stdlib/stdlib.c
new file mode 100644
index 0000000..7c9854e
--- /dev/null
+++ b/src/rp2_common/pico_stdlib/stdlib.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico/stdlib.h"
+#include "hardware/pll.h"
+#include "hardware/clocks.h"
+#if LIB_PICO_STDIO_UART
+#include "pico/stdio_uart.h"
+#else
+#include "pico/binary_info.h"
+#endif
+
+// everything running off the USB oscillator
+void set_sys_clock_48mhz() {
+    if (!running_on_fpga()) {
+        // Change clk_sys to be 48MHz. The simplest way is to take this from PLL_USB
+        // which has a source frequency of 48MHz
+        clock_configure(clk_sys,
+                        CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
+                        CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
+                        48 * MHZ,
+                        48 * MHZ);
+
+        // Turn off PLL sys for good measure
+        pll_deinit(pll_sys);
+
+        // CLK peri is clocked from clk_sys so need to change clk_peri's freq
+        clock_configure(clk_peri,
+                        0,
+                        CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS,
+                        48 * MHZ,
+                        48 * MHZ);
+    }
+}
+
+void set_sys_clock_pll(uint32_t vco_freq, uint post_div1, uint post_div2) {
+    if (!running_on_fpga()) {
+        clock_configure(clk_sys,
+                        CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
+                        CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
+                        48 * MHZ,
+                        48 * MHZ);
+
+        pll_init(pll_sys, 1, vco_freq, post_div1, post_div2);
+        uint32_t freq = vco_freq / (post_div1 * post_div2);
+
+        // Configure clocks
+        // CLK_REF = XOSC (12MHz) / 1 = 12MHz
+        clock_configure(clk_ref,
+                        CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC,
+                        0, // No aux mux
+                        12 * MHZ,
+                        12 * MHZ);
+
+        // CLK SYS = PLL SYS (125MHz) / 1 = 125MHz
+        clock_configure(clk_sys,
+                        CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
+                        CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS,
+                        freq, freq);
+
+        clock_configure(clk_peri,
+                        0, // Only AUX mux on ADC
+                        CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
+                        48 * MHZ,
+                        48 * MHZ);
+    }
+}
+
+bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_out, uint *postdiv1_out, uint *postdiv_out) {
+    uint crystal_freq_khz = clock_get_hz(clk_ref) / 1000;
+    for (uint fbdiv = 320; fbdiv >= 16; fbdiv--) {
+        uint vco = fbdiv * crystal_freq_khz;
+        if (vco < 400000 || vco > 1600000) continue;
+        for (uint postdiv1 = 7; postdiv1 >= 1; postdiv1--) {
+            for (uint postdiv2 = postdiv1; postdiv2 >= 1; postdiv2--) {
+                uint out = vco / (postdiv1 * postdiv2);
+                if (out == freq_khz && !(vco % (postdiv1 * postdiv2))) {
+                    *vco_out = vco * 1000;
+                    *postdiv1_out = postdiv1;
+                    *postdiv_out = postdiv2;
+                    return true;
+                }
+            }
+        }
+    }
+    return false;
+}
+
+void setup_default_uart() {
+#if LIB_PICO_STDIO_UART
+    stdio_uart_init();
+#elif defined(PICO_DEFAULT_UART_BAUD_RATE) && defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN)
+    // this is mostly for backwards compatibility - stdio_uart_init is a bit more nuanced, and usually likely to be present
+    uart_init(uart_default, PICO_DEFAULT_UART_BAUD_RATE);
+    if (PICO_DEFAULT_UART_TX_PIN >= 0)
+        gpio_set_function(PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART);
+    if (PICO_DEFAULT_UART_RX_PIN >= 0)
+        gpio_set_function(PICO_DEFAULT_UART_RX_PIN, GPIO_FUNC_UART);
+    bi_decl_if_func_used(bi_2pins_with_func(PICO_DEFAULT_UART_RX_PIN, PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART));
+#endif
+}
diff --git a/src/rp2_common/pico_unique_id/CMakeLists.txt b/src/rp2_common/pico_unique_id/CMakeLists.txt
new file mode 100644
index 0000000..4c69074
--- /dev/null
+++ b/src/rp2_common/pico_unique_id/CMakeLists.txt
@@ -0,0 +1,9 @@
+pico_add_impl_library(pico_unique_id)
+
+target_sources(pico_unique_id INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/unique_id.c
+)
+
+target_include_directories(pico_unique_id INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
+
+target_link_libraries(pico_unique_id INTERFACE hardware_flash)
diff --git a/src/rp2_common/pico_unique_id/include/pico/unique_id.h b/src/rp2_common/pico_unique_id/include/pico/unique_id.h
new file mode 100644
index 0000000..4132a60
--- /dev/null
+++ b/src/rp2_common/pico_unique_id/include/pico/unique_id.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_UNIQUE_ID_H_
+#define _PICO_UNIQUE_ID_H_
+
+#include "pico.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file pico/unique_id.h
+ *  \defgroup pico_unique_id pico_unique_id
+ *
+ * Unique device ID access API
+ *
+ * RP2040 does not have an on-board unique identifier (all instances of RP2040
+ * silicon are identical and have no persistent state). However, RP2040 boots
+ * from serial NOR flash devices which have a 64-bit unique ID as a standard
+ * feature, and there is a 1:1 association between RP2040 and flash, so this
+ * is suitable for use as a unique identifier for an RP2040-based board.
+ *
+ * This library injects a call to the flash_get_unique_id function from the
+ * hardware_flash library, to run before main, and stores the result in a
+ * static location which can safely be accessed at any time via
+ * pico_get_unique_id().
+ *
+ * This avoids some pitfalls of the hardware_flash API, which requires any
+ * flash-resident interrupt routines to be disabled when called into.
+ */
+
+#define PICO_UNIQUE_BOARD_ID_SIZE_BYTES 8
+
+/**
+ * \brief Unique board identifier
+ * \ingroup pico_unique_id
+ *
+ * This struct is suitable for holding the unique identifier of a NOR flash
+ * device on an RP2040-based board. It contains an array of
+ * PICO_UNIQUE_BOARD_ID_SIZE_BYTES identifier bytes.
+ */
+typedef struct {
+	uint8_t id[PICO_UNIQUE_BOARD_ID_SIZE_BYTES];
+} pico_unique_board_id_t;
+
+/*! \brief Get unique ID
+ *  \ingroup pico_unique_id
+ *
+ * Get the unique 64-bit device identifier which was retrieved from the
+ * external NOR flash device at boot.
+ *
+ * On PICO_NO_FLASH builds the unique identifier is set to all 0xEE.
+ *
+ * \param id_out a pointer to a pico_unique_board_id_t struct, to which the identifier will be written
+ */
+void pico_get_unique_board_id(pico_unique_board_id_t *id_out);
+
+/*! \brief Get unique ID in string format
+ *  \ingroup pico_unique_id
+ *
+ * Get the unique 64-bit device identifier which was retrieved from the
+ * external NOR flash device at boot, formatted as an ASCII hex string.
+ * Will always 0-terminate.
+ *
+ * On PICO_NO_FLASH builds the unique identifier is set to all 0xEE.
+ *
+ * \param id_out a pointer to a char buffer of size len, to which the identifier will be written
+ * \param len the size of id_out. For full serial, len >= 2 * PICO_UNIQUE_BOARD_ID_SIZE_BYTES + 1
+ */
+void pico_get_unique_board_id_string(char *id_out, uint len);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/rp2_common/pico_unique_id/unique_id.c b/src/rp2_common/pico_unique_id/unique_id.c
new file mode 100644
index 0000000..2e652c8
--- /dev/null
+++ b/src/rp2_common/pico_unique_id/unique_id.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/flash.h"
+#include "pico/unique_id.h"
+
+static_assert(PICO_UNIQUE_BOARD_ID_SIZE_BYTES == FLASH_UNIQUE_ID_SIZE_BYTES, "Board ID size must match flash ID size");
+
+static pico_unique_board_id_t retrieved_id;
+
+static void __attribute__((constructor)) _retrieve_unique_id_on_boot(void) {
+#if PICO_NO_FLASH
+    // The hardware_flash call will panic() if called directly on a NO_FLASH
+    // build. Since this constructor is pre-main it would be annoying to
+    // debug, so just produce something well-defined and obviously wrong.
+    for (int i = 0; i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES; i++)
+        retrieved_id.id[i] = 0xee;
+#else
+    flash_get_unique_id(retrieved_id.id);
+#endif
+}
+
+void pico_get_unique_board_id(pico_unique_board_id_t *id_out) {
+    *id_out = retrieved_id;
+}
+
+void pico_get_unique_board_id_string(char *id_out, uint len) {
+    assert(len > 0);
+    size_t i;
+    // Generate hex one nibble at a time
+    for (i = 0; (i < len - 1) && (i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES * 2); i++) {
+        int nibble = (retrieved_id.id[i/2] >> (4 - 4 * (i&1))) & 0xf;
+        id_out[i] = (char)(nibble < 10 ? nibble + '0' : nibble + 'A' - 10);
+    }
+    id_out[i] = 0;
+}
diff --git a/src/rp2_common/tinyusb/CMakeLists.txt b/src/rp2_common/tinyusb/CMakeLists.txt
new file mode 100644
index 0000000..80a6e78
--- /dev/null
+++ b/src/rp2_common/tinyusb/CMakeLists.txt
@@ -0,0 +1,49 @@
+if (DEFINED ENV{PICO_TINYUSB_PATH} AND (NOT PICO_TINYUSB_PATH))
+    set(PICO_TINYUSB_PATH $ENV{PICO_TINYUSB_PATH})
+    message("Using PICO_TINYUSB_PATH from environment ('${PICO_TINYUSB_PATH}')")
+endif ()
+
+set(TINYUSB_TEST_PATH "src/portable/raspberrypi/rp2040")
+if (NOT PICO_TINYUSB_PATH)
+    set(PICO_TINYUSB_PATH ${PROJECT_SOURCE_DIR}/lib/tinyusb)
+    if (NOT EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH})
+        message(WARNING "TinyUSB submodule has not been initialized; USB support will be unavailable
+hint: try 'git submodule update --init' from your SDK directory (${PICO_SDK_PATH}).")
+    endif()
+elseif (NOT EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH})
+    message(WARNING "PICO_TINYUSB_PATH specified but content not present.")
+endif()
+
+if (EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH})
+    message("TinyUSB available at ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}; enabling build support for USB.")
+
+    pico_register_common_scope_var(PICO_TINYUSB_PATH)
+
+    set(BOARD pico_sdk)
+    set(FAMILY rp2040)
+    include(${PICO_TINYUSB_PATH}/hw/bsp/family_support.cmake)
+
+    add_library(tinyusb_common INTERFACE)
+    target_link_libraries(tinyusb_common INTERFACE tinyusb_common_base)
+
+    add_library(tinyusb_device_unmarked INTERFACE)
+    target_link_libraries(tinyusb_device_unmarked INTERFACE tinyusb_device_base)
+    target_compile_definitions(tinyusb_device_unmarked INTERFACE
+            # off by default note TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX defaults from PICO_RP2040_USB_DEVICE_ENUMERATION_FIX
+#            TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX=1
+    )
+
+    # unmarked version used by stdio USB
+    target_link_libraries(tinyusb_device_unmarked INTERFACE tinyusb_common pico_fix_rp2040_usb_device_enumeration tinyusb_device_base)
+
+    pico_add_impl_library(tinyusb_device)
+    target_link_libraries(tinyusb_device INTERFACE tinyusb_device_unmarked)
+
+    pico_add_impl_library(tinyusb_host)
+    target_link_libraries(tinyusb_host INTERFACE tinyusb_host_base tinyusb_common)
+
+    pico_add_impl_library(tinyusb_board)
+    target_link_libraries(tinyusb_board INTERFACE tinyusb_bsp)
+
+    pico_promote_common_scope_vars()
+endif()
diff --git a/src/rp2_common/tinyusb/doc.h b/src/rp2_common/tinyusb/doc.h
new file mode 100644
index 0000000..6c361e0
--- /dev/null
+++ b/src/rp2_common/tinyusb/doc.h
@@ -0,0 +1,7 @@
+/**
+ * \defgroup tinyusb_device tinyusb_device
+ * \brief <a href="https://github.com/hathach/tinyusb">TinyUSB</a> Device-mode support for the RP2040
+ *
+ * \defgroup tinyusb_host tinyusb_host
+ * \brief <a href="https://github.com/hathach/tinyusb">TinyUSB</a> Host-mode support for the RP2040
+ */