Remove 1 cycle delay in FPGA writes
The FPGA is only taking updates to lengthen the cycle before the next
cycle starts. This is adding 1 cycle of delay when decelerating our
catapult.
The FPGA supports changing the period. So, we can set the period to
1/2, and then skip every other period. This produces the same waveform,
but effectively updates the active FPGA value more frequently.
Change-Id: Ib239f09ff4da652a9fbdf0aa0e552eb71b1d2054
Signed-off-by: Austin Schuh <austin.linux@gmail.com>
diff --git a/y2022/wpilib_interface.cc b/y2022/wpilib_interface.cc
index b1f386c..e538c2c 100644
--- a/y2022/wpilib_interface.cc
+++ b/y2022/wpilib_interface.cc
@@ -664,6 +664,7 @@
// Thread 3.
::aos::ShmEventLoop sensor_reader_event_loop(&config.message());
SensorReader sensor_reader(&sensor_reader_event_loop, values);
+ sensor_reader.set_pwm_trigger(true);
sensor_reader.set_drivetrain_left_encoder(make_encoder(1));
sensor_reader.set_drivetrain_right_encoder(make_encoder(0));