Remove 1 cycle delay in FPGA writes
The FPGA is only taking updates to lengthen the cycle before the next
cycle starts. This is adding 1 cycle of delay when decelerating our
catapult.
The FPGA supports changing the period. So, we can set the period to
1/2, and then skip every other period. This produces the same waveform,
but effectively updates the active FPGA value more frequently.
Change-Id: Ib239f09ff4da652a9fbdf0aa0e552eb71b1d2054
Signed-off-by: Austin Schuh <austin.linux@gmail.com>
diff --git a/frc971/wpilib/ahal/Talon.cc b/frc971/wpilib/ahal/Talon.cc
index e3af567..7caabc0 100644
--- a/frc971/wpilib/ahal/Talon.cc
+++ b/frc971/wpilib/ahal/Talon.cc
@@ -32,7 +32,7 @@
* 0.989ms = full "reverse"
*/
SetBounds(2.037, 1.539, 1.513, 1.487, .989);
- SetPeriodMultiplier(kPeriodMultiplier_1X);
+ SetPeriodMultiplier(kPeriodMultiplier_2X);
SetSpeed(0.0);
SetZeroLatch();