Added ADC buffer schematic.
diff --git a/bbb_cape/schematic/adc_buffer.sch b/bbb_cape/schematic/adc_buffer.sch
new file mode 100644
index 0000000..d1f686f
--- /dev/null
+++ b/bbb_cape/schematic/adc_buffer.sch
@@ -0,0 +1,157 @@
+v 20110115 2
+C 41600 49100 1 0 0 quad_opamp-1.sym
+{
+T 42200 49700 5 10 0 0 0 0 1
+device=QUAD_OPAMP
+T 41800 50000 5 10 1 1 0 0 1
+refdes=U2
+T 44000 51400 5 10 0 0 0 0 1
+footprint=SO14
+T 41800 51600 5 10 0 0 0 0 1
+symversion=0.1
+T 41600 49100 5 10 0 0 0 0 1
+slot=1
+T 41600 49100 5 10 0 0 0 0 1
+footprint=TSSOP14
+}
+C 41600 47600 1 0 0 quad_opamp-1.sym
+{
+T 42200 48200 5 10 0 0 0 0 1
+device=QUAD_OPAMP
+T 41800 48500 5 10 1 1 0 0 1
+refdes=U2
+T 44000 49900 5 10 0 0 0 0 1
+footprint=SO14
+T 41800 50100 5 10 0 0 0 0 1
+symversion=0.1
+T 41600 47600 5 10 0 0 0 0 1
+slot=2
+T 41600 47600 5 10 0 0 0 0 1
+footprint=TSSOP14
+}
+C 41600 46200 1 0 0 quad_opamp-1.sym
+{
+T 42200 46800 5 10 0 0 0 0 1
+device=QUAD_OPAMP
+T 41800 47100 5 10 1 1 0 0 1
+refdes=U2
+T 44000 48500 5 10 0 0 0 0 1
+footprint=SO14
+T 41800 48700 5 10 0 0 0 0 1
+symversion=0.1
+T 41600 46200 5 10 0 0 0 0 1
+slot=3
+T 41600 46200 5 10 0 0 0 0 1
+footprint=TSSOP14
+}
+C 41600 44700 1 0 0 quad_opamp-1.sym
+{
+T 42200 45300 5 10 0 0 0 0 1
+device=QUAD_OPAMP
+T 41800 45600 5 10 1 1 0 0 1
+refdes=U2
+T 44000 47000 5 10 0 0 0 0 1
+footprint=SO14
+T 41800 47200 5 10 0 0 0 0 1
+symversion=0.1
+T 41600 44700 5 10 0 0 0 0 1
+slot=4
+T 41600 44700 5 10 0 0 0 0 1
+footprint=TSSOP14
+}
+N 41600 49700 41500 49700 4
+N 42600 49500 43200 49500 4
+N 41500 49700 41500 50300 4
+N 41500 50300 42800 50300 4
+N 42800 50300 42800 49500 4
+N 41600 48200 41500 48200 4
+N 41500 48200 41500 48800 4
+N 41500 48800 42800 48800 4
+N 42800 48800 42800 48000 4
+N 42600 48000 43200 48000 4
+N 41600 46800 41500 46800 4
+N 41500 46800 41500 47400 4
+N 41500 47400 42800 47400 4
+N 42800 47400 42800 46600 4
+N 42600 46600 43200 46600 4
+N 41500 45300 41600 45300 4
+N 41500 45300 41500 45900 4
+N 41500 45900 42800 45900 4
+N 42800 45900 42800 45100 4
+N 42600 45100 43200 45100 4
+C 40600 49200 1 0 0 in-1.sym
+{
+T 40600 49500 5 10 0 0 0 0 1
+device=INPUT
+T 40600 49500 5 10 1 1 0 0 1
+refdes=in1
+}
+C 40600 44800 1 0 0 in-1.sym
+{
+T 40600 45100 5 10 0 0 0 0 1
+device=INPUT
+T 40600 45100 5 10 1 1 0 0 1
+refdes=in4
+}
+C 40600 46300 1 0 0 in-1.sym
+{
+T 40600 46600 5 10 0 0 0 0 1
+device=INPUT
+T 40600 46600 5 10 1 1 0 0 1
+refdes=in3
+}
+C 40600 47700 1 0 0 in-1.sym
+{
+T 40600 48000 5 10 0 0 0 0 1
+device=INPUT
+T 40600 48000 5 10 1 1 0 0 1
+refdes=in2
+}
+C 42000 51100 1 270 0 in-1.sym
+{
+T 42300 51100 5 10 0 0 270 0 1
+device=INPUT
+T 42200 51000 5 10 1 1 270 0 1
+refdes=VCC
+}
+C 42200 43800 1 90 0 in-1.sym
+{
+T 41900 43800 5 10 0 0 90 0 1
+device=INPUT
+T 42000 43900 5 10 1 1 90 0 1
+refdes=GND
+}
+C 43200 49400 1 0 0 out-1.sym
+{
+T 43200 49700 5 10 0 0 0 0 1
+device=OUTPUT
+T 43200 49600 5 10 1 1 0 0 1
+refdes=out1
+}
+C 43200 47900 1 0 0 out-1.sym
+{
+T 43200 48200 5 10 0 0 0 0 1
+device=OUTPUT
+T 43200 48100 5 10 1 1 0 0 1
+refdes=out2
+}
+C 43200 46500 1 0 0 out-1.sym
+{
+T 43200 46800 5 10 0 0 0 0 1
+device=OUTPUT
+T 43200 46700 5 10 1 1 0 0 1
+refdes=out3
+}
+C 43200 45000 1 0 0 out-1.sym
+{
+T 43200 45300 5 10 0 0 0 0 1
+device=OUTPUT
+T 43200 45200 5 10 1 1 0 0 1
+refdes=out4
+}
+N 41600 49300 41200 49300 4
+N 41600 47800 41200 47800 4
+N 41600 46400 41200 46400 4
+N 41600 44900 41200 44900 4
+N 42100 44400 42100 44700 4
+N 42100 50500 42100 49900 4